drivers/net/ethernet/mellanox/mlx5/core/cmd.c

   1 /*
   2  * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/errno.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/slab.h>
  39 #include <linux/delay.h>
  40 #include <linux/random.h>
  41 #include <linux/io-mapping.h>
  42 #include <linux/mlx5/driver.h>
  43 #include <linux/debugfs.h>
  44
  45 #include "mlx5_core.h"
  46
  47 enum {
  48         CMD_IF_REV = 5,
  49 };
  50
  51 enum {
  52         CMD_MODE_POLLING,
  53         CMD_MODE_EVENTS
  54 };
  55
  56 enum {
  57         NUM_LONG_LISTS    = 2,
  58         NUM_MED_LISTS     = 64,
  59         LONG_LIST_SIZE    = (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE) * 8 + 16 +
  60                                 MLX5_CMD_DATA_BLOCK_SIZE,
  61         MED_LIST_SIZE     = 16 + MLX5_CMD_DATA_BLOCK_SIZE,
  62 };
  63
  64 enum {
  65         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
  66         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
  67         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
  68         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
  69         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
  70         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
  71         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
  72         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
  73         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
  74         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
  75         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
  76 };
  77
  78 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
  79                                            struct mlx5_cmd_msg *in,
  80                                            struct mlx5_cmd_msg *out,
  81                                            void *uout, int uout_size,
  82                                            mlx5_cmd_cbk_t cbk,
  83                                            void *context, int page_queue)
  84 {
  85         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
  86         struct mlx5_cmd_work_ent *ent;
  87
  88         ent = kzalloc(sizeof(*ent), alloc_flags);
  89         if (!ent)
  90                 return ERR_PTR(-ENOMEM);
  91
  92         ent->in         = in;
  93         ent->out        = out;
  94         ent->uout       = uout;
  95         ent->uout_size  = uout_size;
  96         ent->callback   = cbk;
  97         ent->context    = context;
  98         ent->cmd        = cmd;
  99         ent->page_queue = page_queue;
 100
 101         return ent;
 102 }
 103
 104 static u8 alloc_token(struct mlx5_cmd *cmd)
 105 {
 106         u8 token;
 107
 108         spin_lock(&cmd->token_lock);
 109         cmd->token++;
 110         if (cmd->token == 0)
 111                 cmd->token++;
 112         token = cmd->token;
 113         spin_unlock(&cmd->token_lock);
 114
 115         return token;
 116 }
 117
 118 static int alloc_ent(struct mlx5_cmd *cmd)
 119 {
 120         unsigned long flags;
 121         int ret;
 122
 123         spin_lock_irqsave(&cmd->alloc_lock, flags);
 124         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
 125         if (ret < cmd->max_reg_cmds)
 126                 clear_bit(ret, &cmd->bitmask);
 127         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 128
 129         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
 130 }
 131
 132 static void free_ent(struct mlx5_cmd *cmd, int idx)
 133 {
 134         unsigned long flags;
 135
 136         spin_lock_irqsave(&cmd->alloc_lock, flags);
 137         set_bit(idx, &cmd->bitmask);
 138         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 139 }
 140
 141 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
 142 {
 143         return cmd->cmd_buf + (idx << cmd->log_stride);
 144 }
 145
 146 static u8 xor8_buf(void *buf, int len)
 147 {
 148         u8 *ptr = buf;
 149         u8 sum = 0;
 150         int i;
 151
 152         for (i = 0; i < len; i++)
 153                 sum ^= ptr[i];
 154
 155         return sum;
 156 }
 157
 158 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
 159 {
 160         if (xor8_buf(block->rsvd0, sizeof(*block) - sizeof(block->data) - 1) != 0xff)
 161                 return -EINVAL;
 162
 163         if (xor8_buf(block, sizeof(*block)) != 0xff)
 164                 return -EINVAL;
 165
 166         return 0;
 167 }
 168
 169 static void calc_block_sig(struct mlx5_cmd_prot_block *block, u8 token,
 170                            int csum)
 171 {
 172         block->token = token;
 173         if (csum) {
 174                 block->ctrl_sig = ~xor8_buf(block->rsvd0, sizeof(*block) -
 175                                             sizeof(block->data) - 2);
 176                 block->sig = ~xor8_buf(block, sizeof(*block) - 1);
 177         }
 178 }
 179
 180 static void calc_chain_sig(struct mlx5_cmd_msg *msg, u8 token, int csum)
 181 {
 182         struct mlx5_cmd_mailbox *next = msg->next;
 183
 184         while (next) {
 185                 calc_block_sig(next->buf, token, csum);
 186                 next = next->next;
 187         }
 188 }
 189
 190 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
 191 {
 192         ent->lay->sig = ~xor8_buf(ent->lay, sizeof(*ent->lay));
 193         calc_chain_sig(ent->in, ent->token, csum);
 194         calc_chain_sig(ent->out, ent->token, csum);
 195 }
 196
 197 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
 198 {
 199         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
 200         u8 own;
 201
 202         do {
 203                 own = ent->lay->status_own;
 204                 if (!(own & CMD_OWNER_HW)) {
 205                         ent->ret = 0;
 206                         return;
 207                 }
 208                 usleep_range(5000, 10000);
 209         } while (time_before(jiffies, poll_end));
 210
 211         ent->ret = -ETIMEDOUT;
 212 }
 213
 214 static void free_cmd(struct mlx5_cmd_work_ent *ent)
 215 {
 216         kfree(ent);
 217 }
 218
 219
 220 static int verify_signature(struct mlx5_cmd_work_ent *ent)
 221 {
 222         struct mlx5_cmd_mailbox *next = ent->out->next;
 223         int err;
 224         u8 sig;
 225
 226         sig = xor8_buf(ent->lay, sizeof(*ent->lay));
 227         if (sig != 0xff)
 228                 return -EINVAL;
 229
 230         while (next) {
 231                 err = verify_block_sig(next->buf);
 232                 if (err)
 233                         return err;
 234
 235                 next = next->next;
 236         }
 237
 238         return 0;
 239 }
 240
 241 static void dump_buf(void *buf, int size, int data_only, int offset)
 242 {
 243         __be32 *p = buf;
 244         int i;
 245
 246         for (i = 0; i < size; i += 16) {
 247                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
 248                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 249                          be32_to_cpu(p[3]));
 250                 p += 4;
 251                 offset += 16;
 252         }
 253         if (!data_only)
 254                 pr_debug("\n");
 255 }
 256
 257 enum {
 258         MLX5_DRIVER_STATUS_ABORTED = 0xfe,
 259         MLX5_DRIVER_SYND = 0xbadd00de,
 260 };
 261
 262 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
 263                                        u32 *synd, u8 *status)
 264 {
 265         *synd = 0;
 266         *status = 0;
 267
 268         switch (op) {
 269         case MLX5_CMD_OP_TEARDOWN_HCA:
 270         case MLX5_CMD_OP_DISABLE_HCA:
 271         case MLX5_CMD_OP_MANAGE_PAGES:
 272         case MLX5_CMD_OP_DESTROY_MKEY:
 273         case MLX5_CMD_OP_DESTROY_EQ:
 274         case MLX5_CMD_OP_DESTROY_CQ:
 275         case MLX5_CMD_OP_DESTROY_QP:
 276         case MLX5_CMD_OP_DESTROY_PSV:
 277         case MLX5_CMD_OP_DESTROY_SRQ:
 278         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
 279         case MLX5_CMD_OP_DESTROY_DCT:
 280         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
 281         case MLX5_CMD_OP_DEALLOC_PD:
 282         case MLX5_CMD_OP_DEALLOC_UAR:
 283         case MLX5_CMD_OP_DETTACH_FROM_MCG:
 284         case MLX5_CMD_OP_DEALLOC_XRCD:
 285         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
 286         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
 287         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
 288         case MLX5_CMD_OP_DESTROY_TIR:
 289         case MLX5_CMD_OP_DESTROY_SQ:
 290         case MLX5_CMD_OP_DESTROY_RQ:
 291         case MLX5_CMD_OP_DESTROY_RMP:
 292         case MLX5_CMD_OP_DESTROY_TIS:
 293         case MLX5_CMD_OP_DESTROY_RQT:
 294         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
 295         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
 296         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
 297         case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
 298         case MLX5_CMD_OP_2ERR_QP:
 299         case MLX5_CMD_OP_2RST_QP:
 300         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
 301         case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
 302         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
 303         case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
 304                 return MLX5_CMD_STAT_OK;
 305
 306         case MLX5_CMD_OP_QUERY_HCA_CAP:
 307         case MLX5_CMD_OP_QUERY_ADAPTER:
 308         case MLX5_CMD_OP_INIT_HCA:
 309         case MLX5_CMD_OP_ENABLE_HCA:
 310         case MLX5_CMD_OP_QUERY_PAGES:
 311         case MLX5_CMD_OP_SET_HCA_CAP:
 312         case MLX5_CMD_OP_QUERY_ISSI:
 313         case MLX5_CMD_OP_SET_ISSI:
 314         case MLX5_CMD_OP_CREATE_MKEY:
 315         case MLX5_CMD_OP_QUERY_MKEY:
 316         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 317         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
 318         case MLX5_CMD_OP_CREATE_EQ:
 319         case MLX5_CMD_OP_QUERY_EQ:
 320         case MLX5_CMD_OP_GEN_EQE:
 321         case MLX5_CMD_OP_CREATE_CQ:
 322         case MLX5_CMD_OP_QUERY_CQ:
 323         case MLX5_CMD_OP_MODIFY_CQ:
 324         case MLX5_CMD_OP_CREATE_QP:
 325         case MLX5_CMD_OP_RST2INIT_QP:
 326         case MLX5_CMD_OP_INIT2RTR_QP:
 327         case MLX5_CMD_OP_RTR2RTS_QP:
 328         case MLX5_CMD_OP_RTS2RTS_QP:
 329         case MLX5_CMD_OP_SQERR2RTS_QP:
 330         case MLX5_CMD_OP_QUERY_QP:
 331         case MLX5_CMD_OP_SQD_RTS_QP:
 332         case MLX5_CMD_OP_INIT2INIT_QP:
 333         case MLX5_CMD_OP_CREATE_PSV:
 334         case MLX5_CMD_OP_CREATE_SRQ:
 335         case MLX5_CMD_OP_QUERY_SRQ:
 336         case MLX5_CMD_OP_ARM_RQ:
 337         case MLX5_CMD_OP_CREATE_XRC_SRQ:
 338         case MLX5_CMD_OP_QUERY_XRC_SRQ:
 339         case MLX5_CMD_OP_ARM_XRC_SRQ:
 340         case MLX5_CMD_OP_CREATE_DCT:
 341         case MLX5_CMD_OP_DRAIN_DCT:
 342         case MLX5_CMD_OP_QUERY_DCT:
 343         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
 344         case MLX5_CMD_OP_QUERY_VPORT_STATE:
 345         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
 346         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
 347         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
 348         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
 349         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
 350         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
 351         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
 352         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
 353         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
 354         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
 355         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
 356         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
 357         case MLX5_CMD_OP_QUERY_Q_COUNTER:
 358         case MLX5_CMD_OP_ALLOC_PD:
 359         case MLX5_CMD_OP_ALLOC_UAR:
 360         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
 361         case MLX5_CMD_OP_ACCESS_REG:
 362         case MLX5_CMD_OP_ATTACH_TO_MCG:
 363         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
 364         case MLX5_CMD_OP_MAD_IFC:
 365         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
 366         case MLX5_CMD_OP_SET_MAD_DEMUX:
 367         case MLX5_CMD_OP_NOP:
 368         case MLX5_CMD_OP_ALLOC_XRCD:
 369         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
 370         case MLX5_CMD_OP_QUERY_CONG_STATUS:
 371         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
 372         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
 373         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
 374         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
 375         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
 376         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
 377         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
 378         case MLX5_CMD_OP_CREATE_TIR:
 379         case MLX5_CMD_OP_MODIFY_TIR:
 380         case MLX5_CMD_OP_QUERY_TIR:
 381         case MLX5_CMD_OP_CREATE_SQ:
 382         case MLX5_CMD_OP_MODIFY_SQ:
 383         case MLX5_CMD_OP_QUERY_SQ:
 384         case MLX5_CMD_OP_CREATE_RQ:
 385         case MLX5_CMD_OP_MODIFY_RQ:
 386         case MLX5_CMD_OP_QUERY_RQ:
 387         case MLX5_CMD_OP_CREATE_RMP:
 388         case MLX5_CMD_OP_MODIFY_RMP:
 389         case MLX5_CMD_OP_QUERY_RMP:
 390         case MLX5_CMD_OP_CREATE_TIS:
 391         case MLX5_CMD_OP_MODIFY_TIS:
 392         case MLX5_CMD_OP_QUERY_TIS:
 393         case MLX5_CMD_OP_CREATE_RQT:
 394         case MLX5_CMD_OP_MODIFY_RQT:
 395         case MLX5_CMD_OP_QUERY_RQT:
 396
 397         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
 398         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
 399         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
 400         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
 401
 402         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
 403         case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
 404         case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
 405                 *status = MLX5_DRIVER_STATUS_ABORTED;
 406                 *synd = MLX5_DRIVER_SYND;
 407                 return -EIO;
 408         default:
 409                 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
 410                 return -EINVAL;
 411         }
 412 }
 413
 414 const char *mlx5_command_str(int command)
 415 {
 416 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
 417
 418         switch (command) {
 419         MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
 420         MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
 421         MLX5_COMMAND_STR_CASE(INIT_HCA);
 422         MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
 423         MLX5_COMMAND_STR_CASE(ENABLE_HCA);
 424         MLX5_COMMAND_STR_CASE(DISABLE_HCA);
 425         MLX5_COMMAND_STR_CASE(QUERY_PAGES);
 426         MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
 427         MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
 428         MLX5_COMMAND_STR_CASE(QUERY_ISSI);
 429         MLX5_COMMAND_STR_CASE(SET_ISSI);
 430         MLX5_COMMAND_STR_CASE(CREATE_MKEY);
 431         MLX5_COMMAND_STR_CASE(QUERY_MKEY);
 432         MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
 433         MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
 434         MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
 435         MLX5_COMMAND_STR_CASE(CREATE_EQ);
 436         MLX5_COMMAND_STR_CASE(DESTROY_EQ);
 437         MLX5_COMMAND_STR_CASE(QUERY_EQ);
 438         MLX5_COMMAND_STR_CASE(GEN_EQE);
 439         MLX5_COMMAND_STR_CASE(CREATE_CQ);
 440         MLX5_COMMAND_STR_CASE(DESTROY_CQ);
 441         MLX5_COMMAND_STR_CASE(QUERY_CQ);
 442         MLX5_COMMAND_STR_CASE(MODIFY_CQ);
 443         MLX5_COMMAND_STR_CASE(CREATE_QP);
 444         MLX5_COMMAND_STR_CASE(DESTROY_QP);
 445         MLX5_COMMAND_STR_CASE(RST2INIT_QP);
 446         MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
 447         MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
 448         MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
 449         MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
 450         MLX5_COMMAND_STR_CASE(2ERR_QP);
 451         MLX5_COMMAND_STR_CASE(2RST_QP);
 452         MLX5_COMMAND_STR_CASE(QUERY_QP);
 453         MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
 454         MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
 455         MLX5_COMMAND_STR_CASE(CREATE_PSV);
 456         MLX5_COMMAND_STR_CASE(DESTROY_PSV);
 457         MLX5_COMMAND_STR_CASE(CREATE_SRQ);
 458         MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
 459         MLX5_COMMAND_STR_CASE(QUERY_SRQ);
 460         MLX5_COMMAND_STR_CASE(ARM_RQ);
 461         MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
 462         MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
 463         MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
 464         MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
 465         MLX5_COMMAND_STR_CASE(CREATE_DCT);
 466         MLX5_COMMAND_STR_CASE(DESTROY_DCT);
 467         MLX5_COMMAND_STR_CASE(DRAIN_DCT);
 468         MLX5_COMMAND_STR_CASE(QUERY_DCT);
 469         MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
 470         MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
 471         MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
 472         MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
 473         MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
 474         MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
 475         MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
 476         MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
 477         MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
 478         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
 479         MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
 480         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
 481         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
 482         MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
 483         MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
 484         MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
 485         MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
 486         MLX5_COMMAND_STR_CASE(ALLOC_PD);
 487         MLX5_COMMAND_STR_CASE(DEALLOC_PD);
 488         MLX5_COMMAND_STR_CASE(ALLOC_UAR);
 489         MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
 490         MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
 491         MLX5_COMMAND_STR_CASE(ACCESS_REG);
 492         MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
 493         MLX5_COMMAND_STR_CASE(DETTACH_FROM_MCG);
 494         MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
 495         MLX5_COMMAND_STR_CASE(MAD_IFC);
 496         MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
 497         MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
 498         MLX5_COMMAND_STR_CASE(NOP);
 499         MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
 500         MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
 501         MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
 502         MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
 503         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
 504         MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
 505         MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
 506         MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
 507         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
 508         MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
 509         MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
 510         MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
 511         MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
 512         MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
 513         MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
 514         MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
 515         MLX5_COMMAND_STR_CASE(CREATE_TIR);
 516         MLX5_COMMAND_STR_CASE(MODIFY_TIR);
 517         MLX5_COMMAND_STR_CASE(DESTROY_TIR);
 518         MLX5_COMMAND_STR_CASE(QUERY_TIR);
 519         MLX5_COMMAND_STR_CASE(CREATE_SQ);
 520         MLX5_COMMAND_STR_CASE(MODIFY_SQ);
 521         MLX5_COMMAND_STR_CASE(DESTROY_SQ);
 522         MLX5_COMMAND_STR_CASE(QUERY_SQ);
 523         MLX5_COMMAND_STR_CASE(CREATE_RQ);
 524         MLX5_COMMAND_STR_CASE(MODIFY_RQ);
 525         MLX5_COMMAND_STR_CASE(DESTROY_RQ);
 526         MLX5_COMMAND_STR_CASE(QUERY_RQ);
 527         MLX5_COMMAND_STR_CASE(CREATE_RMP);
 528         MLX5_COMMAND_STR_CASE(MODIFY_RMP);
 529         MLX5_COMMAND_STR_CASE(DESTROY_RMP);
 530         MLX5_COMMAND_STR_CASE(QUERY_RMP);
 531         MLX5_COMMAND_STR_CASE(CREATE_TIS);
 532         MLX5_COMMAND_STR_CASE(MODIFY_TIS);
 533         MLX5_COMMAND_STR_CASE(DESTROY_TIS);
 534         MLX5_COMMAND_STR_CASE(QUERY_TIS);
 535         MLX5_COMMAND_STR_CASE(CREATE_RQT);
 536         MLX5_COMMAND_STR_CASE(MODIFY_RQT);
 537         MLX5_COMMAND_STR_CASE(DESTROY_RQT);
 538         MLX5_COMMAND_STR_CASE(QUERY_RQT);
 539         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
 540         MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
 541         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
 542         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
 543         MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
 544         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
 545         MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
 546         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
 547         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
 548         MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
 549         MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
 550         MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
 551         MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
 552         MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
 553         default: return "unknown command opcode";
 554         }
 555 }
 556
 557 static void dump_command(struct mlx5_core_dev *dev,
 558                          struct mlx5_cmd_work_ent *ent, int input)
 559 {
 560         u16 op = be16_to_cpu(((struct mlx5_inbox_hdr *)(ent->lay->in))->opcode);
 561         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
 562         struct mlx5_cmd_mailbox *next = msg->next;
 563         int data_only;
 564         u32 offset = 0;
 565         int dump_len;
 566
 567         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
 568
 569         if (data_only)
 570                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
 571                                    "dump command data %s(0x%x) %s\n",
 572                                    mlx5_command_str(op), op,
 573                                    input ? "INPUT" : "OUTPUT");
 574         else
 575                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
 576                               mlx5_command_str(op), op,
 577                               input ? "INPUT" : "OUTPUT");
 578
 579         if (data_only) {
 580                 if (input) {
 581                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
 582                         offset += sizeof(ent->lay->in);
 583                 } else {
 584                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
 585                         offset += sizeof(ent->lay->out);
 586                 }
 587         } else {
 588                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
 589                 offset += sizeof(*ent->lay);
 590         }
 591
 592         while (next && offset < msg->len) {
 593                 if (data_only) {
 594                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
 595                         dump_buf(next->buf, dump_len, 1, offset);
 596                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
 597                 } else {
 598                         mlx5_core_dbg(dev, "command block:\n");
 599                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
 600                         offset += sizeof(struct mlx5_cmd_prot_block);
 601                 }
 602                 next = next->next;
 603         }
 604
 605         if (data_only)
 606                 pr_debug("\n");
 607 }
 608
 609 static void cmd_work_handler(struct work_struct *work)
 610 {
 611         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
 612         struct mlx5_cmd *cmd = ent->cmd;
 613         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
 614         struct mlx5_cmd_layout *lay;
 615         struct semaphore *sem;
 616         unsigned long flags;
 617
 618         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
 619         down(sem);
 620         if (!ent->page_queue) {
 621                 ent->idx = alloc_ent(cmd);
 622                 if (ent->idx < 0) {
 623                         mlx5_core_err(dev, "failed to allocate command entry\n");
 624                         up(sem);
 625                         return;
 626                 }
 627         } else {
 628                 ent->idx = cmd->max_reg_cmds;
 629                 spin_lock_irqsave(&cmd->alloc_lock, flags);
 630                 clear_bit(ent->idx, &cmd->bitmask);
 631                 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 632         }
 633
 634         ent->token = alloc_token(cmd);
 635         cmd->ent_arr[ent->idx] = ent;
 636         lay = get_inst(cmd, ent->idx);
 637         ent->lay = lay;
 638         memset(lay, 0, sizeof(*lay));
 639         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
 640         ent->op = be32_to_cpu(lay->in[0]) >> 16;
 641         if (ent->in->next)
 642                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
 643         lay->inlen = cpu_to_be32(ent->in->len);
 644         if (ent->out->next)
 645                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
 646         lay->outlen = cpu_to_be32(ent->out->len);
 647         lay->type = MLX5_PCI_CMD_XPORT;
 648         lay->token = ent->token;
 649         lay->status_own = CMD_OWNER_HW;
 650         set_signature(ent, !cmd->checksum_disabled);
 651         dump_command(dev, ent, 1);
 652         ent->ts1 = ktime_get_ns();
 653
 654         /* ring doorbell after the descriptor is valid */
 655         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
 656         wmb();
 657         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
 658         mmiowb();
 659         /* if not in polling don't use ent after this point */
 660         if (cmd->mode == CMD_MODE_POLLING) {
 661                 poll_timeout(ent);
 662                 /* make sure we read the descriptor after ownership is SW */
 663                 rmb();
 664                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
 665         }
 666 }
 667
 668 static const char *deliv_status_to_str(u8 status)
 669 {
 670         switch (status) {
 671         case MLX5_CMD_DELIVERY_STAT_OK:
 672                 return "no errors";
 673         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
 674                 return "signature error";
 675         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
 676                 return "token error";
 677         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
 678                 return "bad block number";
 679         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
 680                 return "output pointer not aligned to block size";
 681         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
 682                 return "input pointer not aligned to block size";
 683         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
 684                 return "firmware internal error";
 685         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
 686                 return "command input length error";
 687         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
 688                 return "command ouput length error";
 689         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
 690                 return "reserved fields not cleared";
 691         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
 692                 return "bad command descriptor type";
 693         default:
 694                 return "unknown status code";
 695         }
 696 }
 697
 698 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
 699 {
 700         struct mlx5_inbox_hdr *hdr = (struct mlx5_inbox_hdr *)(in->first.data);
 701
 702         return be16_to_cpu(hdr->opcode);
 703 }
 704
 705 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
 706 {
 707         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 708         struct mlx5_cmd *cmd = &dev->cmd;
 709         int err;
 710
 711         if (cmd->mode == CMD_MODE_POLLING) {
 712                 wait_for_completion(&ent->done);
 713                 err = ent->ret;
 714         } else {
 715                 if (!wait_for_completion_timeout(&ent->done, timeout))
 716                         err = -ETIMEDOUT;
 717                 else
 718                         err = 0;
 719         }
 720         if (err == -ETIMEDOUT) {
 721                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 722                                mlx5_command_str(msg_to_opcode(ent->in)),
 723                                msg_to_opcode(ent->in));
 724         }
 725         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
 726                       err, deliv_status_to_str(ent->status), ent->status);
 727
 728         return err;
 729 }
 730
 731 static __be32 *get_synd_ptr(struct mlx5_outbox_hdr *out)
 732 {
 733         return &out->syndrome;
 734 }
 735
 736 static u8 *get_status_ptr(struct mlx5_outbox_hdr *out)
 737 {
 738         return &out->status;
 739 }
 740
 741 /*  Notes:
 742  *    1. Callback functions may not sleep
 743  *    2. page queue commands do not support asynchrous completion
 744  */
 745 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
 746                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
 747                            mlx5_cmd_cbk_t callback,
 748                            void *context, int page_queue, u8 *status)
 749 {
 750         struct mlx5_cmd *cmd = &dev->cmd;
 751         struct mlx5_cmd_work_ent *ent;
 752         struct mlx5_cmd_stats *stats;
 753         int err = 0;
 754         s64 ds;
 755         u16 op;
 756
 757         if (callback && page_queue)
 758                 return -EINVAL;
 759
 760         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
 761                         page_queue);
 762         if (IS_ERR(ent))
 763                 return PTR_ERR(ent);
 764
 765         if (!callback)
 766                 init_completion(&ent->done);
 767
 768         INIT_WORK(&ent->work, cmd_work_handler);
 769         if (page_queue) {
 770                 cmd_work_handler(&ent->work);
 771         } else if (!queue_work(cmd->wq, &ent->work)) {
 772                 mlx5_core_warn(dev, "failed to queue work\n");
 773                 err = -ENOMEM;
 774                 goto out_free;
 775         }
 776
 777         if (!callback) {
 778                 err = wait_func(dev, ent);
 779                 if (err == -ETIMEDOUT)
 780                         goto out;
 781
 782                 ds = ent->ts2 - ent->ts1;
 783                 op = be16_to_cpu(((struct mlx5_inbox_hdr *)in->first.data)->opcode);
 784                 if (op < ARRAY_SIZE(cmd->stats)) {
 785                         stats = &cmd->stats[op];
 786                         spin_lock_irq(&stats->lock);
 787                         stats->sum += ds;
 788                         ++stats->n;
 789                         spin_unlock_irq(&stats->lock);
 790                 }
 791                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
 792                                    "fw exec time for %s is %lld nsec\n",
 793                                    mlx5_command_str(op), ds);
 794                 *status = ent->status;
 795                 free_cmd(ent);
 796         }
 797
 798         return err;
 799
 800 out_free:
 801         free_cmd(ent);
 802 out:
 803         return err;
 804 }
 805
 806 static ssize_t dbg_write(struct file *filp, const char __user *buf,
 807                          size_t count, loff_t *pos)
 808 {
 809         struct mlx5_core_dev *dev = filp->private_data;
 810         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 811         char lbuf[3];
 812         int err;
 813
 814         if (!dbg->in_msg || !dbg->out_msg)
 815                 return -ENOMEM;
 816
 817         if (copy_from_user(lbuf, buf, sizeof(lbuf)))
 818                 return -EFAULT;
 819
 820         lbuf[sizeof(lbuf) - 1] = 0;
 821
 822         if (strcmp(lbuf, "go"))
 823                 return -EINVAL;
 824
 825         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
 826
 827         return err ? err : count;
 828 }
 829
 830
 831 static const struct file_operations fops = {
 832         .owner  = THIS_MODULE,
 833         .open   = simple_open,
 834         .write  = dbg_write,
 835 };
 836
 837 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size)
 838 {
 839         struct mlx5_cmd_prot_block *block;
 840         struct mlx5_cmd_mailbox *next;
 841         int copy;
 842
 843         if (!to || !from)
 844                 return -ENOMEM;
 845
 846         copy = min_t(int, size, sizeof(to->first.data));
 847         memcpy(to->first.data, from, copy);
 848         size -= copy;
 849         from += copy;
 850
 851         next = to->next;
 852         while (size) {
 853                 if (!next) {
 854                         /* this is a BUG */
 855                         return -ENOMEM;
 856                 }
 857
 858                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
 859                 block = next->buf;
 860                 memcpy(block->data, from, copy);
 861                 from += copy;
 862                 size -= copy;
 863                 next = next->next;
 864         }
 865
 866         return 0;
 867 }
 868
 869 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
 870 {
 871         struct mlx5_cmd_prot_block *block;
 872         struct mlx5_cmd_mailbox *next;
 873         int copy;
 874
 875         if (!to || !from)
 876                 return -ENOMEM;
 877
 878         copy = min_t(int, size, sizeof(from->first.data));
 879         memcpy(to, from->first.data, copy);
 880         size -= copy;
 881         to += copy;
 882
 883         next = from->next;
 884         while (size) {
 885                 if (!next) {
 886                         /* this is a BUG */
 887                         return -ENOMEM;
 888                 }
 889
 890                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
 891                 block = next->buf;
 892
 893                 memcpy(to, block->data, copy);
 894                 to += copy;
 895                 size -= copy;
 896                 next = next->next;
 897         }
 898
 899         return 0;
 900 }
 901
 902 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
 903                                               gfp_t flags)
 904 {
 905         struct mlx5_cmd_mailbox *mailbox;
 906
 907         mailbox = kmalloc(sizeof(*mailbox), flags);
 908         if (!mailbox)
 909                 return ERR_PTR(-ENOMEM);
 910
 911         mailbox->buf = pci_pool_alloc(dev->cmd.pool, flags,
 912                                       &mailbox->dma);
 913         if (!mailbox->buf) {
 914                 mlx5_core_dbg(dev, "failed allocation\n");
 915                 kfree(mailbox);
 916                 return ERR_PTR(-ENOMEM);
 917         }
 918         memset(mailbox->buf, 0, sizeof(struct mlx5_cmd_prot_block));
 919         mailbox->next = NULL;
 920
 921         return mailbox;
 922 }
 923
 924 static void free_cmd_box(struct mlx5_core_dev *dev,
 925                          struct mlx5_cmd_mailbox *mailbox)
 926 {
 927         pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
 928         kfree(mailbox);
 929 }
 930
 931 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
 932                                                gfp_t flags, int size)
 933 {
 934         struct mlx5_cmd_mailbox *tmp, *head = NULL;
 935         struct mlx5_cmd_prot_block *block;
 936         struct mlx5_cmd_msg *msg;
 937         int blen;
 938         int err;
 939         int n;
 940         int i;
 941
 942         msg = kzalloc(sizeof(*msg), flags);
 943         if (!msg)
 944                 return ERR_PTR(-ENOMEM);
 945
 946         blen = size - min_t(int, sizeof(msg->first.data), size);
 947         n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
 948
 949         for (i = 0; i < n; i++) {
 950                 tmp = alloc_cmd_box(dev, flags);
 951                 if (IS_ERR(tmp)) {
 952                         mlx5_core_warn(dev, "failed allocating block\n");
 953                         err = PTR_ERR(tmp);
 954                         goto err_alloc;
 955                 }
 956
 957                 block = tmp->buf;
 958                 tmp->next = head;
 959                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
 960                 block->block_num = cpu_to_be32(n - i - 1);
 961                 head = tmp;
 962         }
 963         msg->next = head;
 964         msg->len = size;
 965         return msg;
 966
 967 err_alloc:
 968         while (head) {
 969                 tmp = head->next;
 970                 free_cmd_box(dev, head);
 971                 head = tmp;
 972         }
 973         kfree(msg);
 974
 975         return ERR_PTR(err);
 976 }
 977
 978 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
 979                                   struct mlx5_cmd_msg *msg)
 980 {
 981         struct mlx5_cmd_mailbox *head = msg->next;
 982         struct mlx5_cmd_mailbox *next;
 983
 984         while (head) {
 985                 next = head->next;
 986                 free_cmd_box(dev, head);
 987                 head = next;
 988         }
 989         kfree(msg);
 990 }
 991
 992 static ssize_t data_write(struct file *filp, const char __user *buf,
 993                           size_t count, loff_t *pos)
 994 {
 995         struct mlx5_core_dev *dev = filp->private_data;
 996         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 997         void *ptr;
 998         int err;
 999
1000         if (*pos != 0)
1001                 return -EINVAL;
1002
1003         kfree(dbg->in_msg);
1004         dbg->in_msg = NULL;
1005         dbg->inlen = 0;
1006
1007         ptr = kzalloc(count, GFP_KERNEL);
1008         if (!ptr)
1009                 return -ENOMEM;
1010
1011         if (copy_from_user(ptr, buf, count)) {
1012                 err = -EFAULT;
1013                 goto out;
1014         }
1015         dbg->in_msg = ptr;
1016         dbg->inlen = count;
1017
1018         *pos = count;
1019
1020         return count;
1021
1022 out:
1023         kfree(ptr);
1024         return err;
1025 }
1026
1027 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1028                          loff_t *pos)
1029 {
1030         struct mlx5_core_dev *dev = filp->private_data;
1031         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1032         int copy;
1033
1034         if (*pos)
1035                 return 0;
1036
1037         if (!dbg->out_msg)
1038                 return -ENOMEM;
1039
1040         copy = min_t(int, count, dbg->outlen);
1041         if (copy_to_user(buf, dbg->out_msg, copy))
1042                 return -EFAULT;
1043
1044         *pos += copy;
1045
1046         return copy;
1047 }
1048
1049 static const struct file_operations dfops = {
1050         .owner  = THIS_MODULE,
1051         .open   = simple_open,
1052         .write  = data_write,
1053         .read   = data_read,
1054 };
1055
1056 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1057                            loff_t *pos)
1058 {
1059         struct mlx5_core_dev *dev = filp->private_data;
1060         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1061         char outlen[8];
1062         int err;
1063
1064         if (*pos)
1065                 return 0;
1066
1067         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1068         if (err < 0)
1069                 return err;
1070
1071         if (copy_to_user(buf, &outlen, err))
1072                 return -EFAULT;
1073
1074         *pos += err;
1075
1076         return err;
1077 }
1078
1079 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1080                             size_t count, loff_t *pos)
1081 {
1082         struct mlx5_core_dev *dev = filp->private_data;
1083         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1084         char outlen_str[8];
1085         int outlen;
1086         void *ptr;
1087         int err;
1088
1089         if (*pos != 0 || count > 6)
1090                 return -EINVAL;
1091
1092         kfree(dbg->out_msg);
1093         dbg->out_msg = NULL;
1094         dbg->outlen = 0;
1095
1096         if (copy_from_user(outlen_str, buf, count))
1097                 return -EFAULT;
1098
1099         outlen_str[7] = 0;
1100
1101         err = sscanf(outlen_str, "%d", &outlen);
1102         if (err < 0)
1103                 return err;
1104
1105         ptr = kzalloc(outlen, GFP_KERNEL);
1106         if (!ptr)
1107                 return -ENOMEM;
1108
1109         dbg->out_msg = ptr;
1110         dbg->outlen = outlen;
1111
1112         *pos = count;
1113
1114         return count;
1115 }
1116
1117 static const struct file_operations olfops = {
1118         .owner  = THIS_MODULE,
1119         .open   = simple_open,
1120         .write  = outlen_write,
1121         .read   = outlen_read,
1122 };
1123
1124 static void set_wqname(struct mlx5_core_dev *dev)
1125 {
1126         struct mlx5_cmd *cmd = &dev->cmd;
1127
1128         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1129                  dev_name(&dev->pdev->dev));
1130 }
1131
1132 static void clean_debug_files(struct mlx5_core_dev *dev)
1133 {
1134         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1135
1136         if (!mlx5_debugfs_root)
1137                 return;
1138
1139         mlx5_cmdif_debugfs_cleanup(dev);
1140         debugfs_remove_recursive(dbg->dbg_root);
1141 }
1142
1143 static int create_debugfs_files(struct mlx5_core_dev *dev)
1144 {
1145         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1146         int err = -ENOMEM;
1147
1148         if (!mlx5_debugfs_root)
1149                 return 0;
1150
1151         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1152         if (!dbg->dbg_root)
1153                 return err;
1154
1155         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1156                                           dev, &dfops);
1157         if (!dbg->dbg_in)
1158                 goto err_dbg;
1159
1160         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1161                                            dev, &dfops);
1162         if (!dbg->dbg_out)
1163                 goto err_dbg;
1164
1165         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1166                                               dev, &olfops);
1167         if (!dbg->dbg_outlen)
1168                 goto err_dbg;
1169
1170         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1171                                             &dbg->status);
1172         if (!dbg->dbg_status)
1173                 goto err_dbg;
1174
1175         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1176         if (!dbg->dbg_run)
1177                 goto err_dbg;
1178
1179         mlx5_cmdif_debugfs_init(dev);
1180
1181         return 0;
1182
1183 err_dbg:
1184         clean_debug_files(dev);
1185         return err;
1186 }
1187
1188 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1189 {
1190         struct mlx5_cmd *cmd = &dev->cmd;
1191         int i;
1192
1193         for (i = 0; i < cmd->max_reg_cmds; i++)
1194                 down(&cmd->sem);
1195
1196         down(&cmd->pages_sem);
1197
1198         flush_workqueue(cmd->wq);
1199
1200         cmd->mode = CMD_MODE_EVENTS;
1201
1202         up(&cmd->pages_sem);
1203         for (i = 0; i < cmd->max_reg_cmds; i++)
1204                 up(&cmd->sem);
1205 }
1206
1207 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1208 {
1209         struct mlx5_cmd *cmd = &dev->cmd;
1210         int i;
1211
1212         for (i = 0; i < cmd->max_reg_cmds; i++)
1213                 down(&cmd->sem);
1214
1215         down(&cmd->pages_sem);
1216
1217         flush_workqueue(cmd->wq);
1218         cmd->mode = CMD_MODE_POLLING;
1219
1220         up(&cmd->pages_sem);
1221         for (i = 0; i < cmd->max_reg_cmds; i++)
1222                 up(&cmd->sem);
1223 }
1224
1225 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1226 {
1227         unsigned long flags;
1228
1229         if (msg->cache) {
1230                 spin_lock_irqsave(&msg->cache->lock, flags);
1231                 list_add_tail(&msg->list, &msg->cache->head);
1232                 spin_unlock_irqrestore(&msg->cache->lock, flags);
1233         } else {
1234                 mlx5_free_cmd_msg(dev, msg);
1235         }
1236 }
1237
1238 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec)
1239 {
1240         struct mlx5_cmd *cmd = &dev->cmd;
1241         struct mlx5_cmd_work_ent *ent;
1242         mlx5_cmd_cbk_t callback;
1243         void *context;
1244         int err;
1245         int i;
1246         s64 ds;
1247         struct mlx5_cmd_stats *stats;
1248         unsigned long flags;
1249         unsigned long vector;
1250
1251         /* there can be at most 32 command queues */
1252         vector = vec & 0xffffffff;
1253         for (i = 0; i < (1 << cmd->log_sz); i++) {
1254                 if (test_bit(i, &vector)) {
1255                         struct semaphore *sem;
1256
1257                         ent = cmd->ent_arr[i];
1258                         if (ent->page_queue)
1259                                 sem = &cmd->pages_sem;
1260                         else
1261                                 sem = &cmd->sem;
1262                         ent->ts2 = ktime_get_ns();
1263                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1264                         dump_command(dev, ent, 0);
1265                         if (!ent->ret) {
1266                                 if (!cmd->checksum_disabled)
1267                                         ent->ret = verify_signature(ent);
1268                                 else
1269                                         ent->ret = 0;
1270                                 if (vec & MLX5_TRIGGERED_CMD_COMP)
1271                                         ent->status = MLX5_DRIVER_STATUS_ABORTED;
1272                                 else
1273                                         ent->status = ent->lay->status_own >> 1;
1274
1275                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1276                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1277                         }
1278                         free_ent(cmd, ent->idx);
1279
1280                         if (ent->callback) {
1281                                 ds = ent->ts2 - ent->ts1;
1282                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1283                                         stats = &cmd->stats[ent->op];
1284                                         spin_lock_irqsave(&stats->lock, flags);
1285                                         stats->sum += ds;
1286                                         ++stats->n;
1287                                         spin_unlock_irqrestore(&stats->lock, flags);
1288                                 }
1289
1290                                 callback = ent->callback;
1291                                 context = ent->context;
1292                                 err = ent->ret;
1293                                 if (!err)
1294                                         err = mlx5_copy_from_msg(ent->uout,
1295                                                                  ent->out,
1296                                                                  ent->uout_size);
1297
1298                                 mlx5_free_cmd_msg(dev, ent->out);
1299                                 free_msg(dev, ent->in);
1300
1301                                 err = err ? err : ent->status;
1302                                 free_cmd(ent);
1303                                 callback(err, context);
1304                         } else {
1305                                 complete(&ent->done);
1306                         }
1307                         up(sem);
1308                 }
1309         }
1310 }
1311 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1312
1313 static int status_to_err(u8 status)
1314 {
1315         return status ? -1 : 0; /* TBD more meaningful codes */
1316 }
1317
1318 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1319                                       gfp_t gfp)
1320 {
1321         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1322         struct mlx5_cmd *cmd = &dev->cmd;
1323         struct cache_ent *ent = NULL;
1324
1325         if (in_size > MED_LIST_SIZE && in_size <= LONG_LIST_SIZE)
1326                 ent = &cmd->cache.large;
1327         else if (in_size > 16 && in_size <= MED_LIST_SIZE)
1328                 ent = &cmd->cache.med;
1329
1330         if (ent) {
1331                 spin_lock_irq(&ent->lock);
1332                 if (!list_empty(&ent->head)) {
1333                         msg = list_entry(ent->head.next, typeof(*msg), list);
1334                         /* For cached lists, we must explicitly state what is
1335                          * the real size
1336                          */
1337                         msg->len = in_size;
1338                         list_del(&msg->list);
1339                 }
1340                 spin_unlock_irq(&ent->lock);
1341         }
1342
1343         if (IS_ERR(msg))
1344                 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size);
1345
1346         return msg;
1347 }
1348
1349 static u16 opcode_from_in(struct mlx5_inbox_hdr *in)
1350 {
1351         return be16_to_cpu(in->opcode);
1352 }
1353
1354 static int is_manage_pages(struct mlx5_inbox_hdr *in)
1355 {
1356         return be16_to_cpu(in->opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1357 }
1358
1359 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1360                     int out_size, mlx5_cmd_cbk_t callback, void *context)
1361 {
1362         struct mlx5_cmd_msg *inb;
1363         struct mlx5_cmd_msg *outb;
1364         int pages_queue;
1365         gfp_t gfp;
1366         int err;
1367         u8 status = 0;
1368         u32 drv_synd;
1369
1370         if (pci_channel_offline(dev->pdev) ||
1371             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1372                 err = mlx5_internal_err_ret_value(dev, opcode_from_in(in), &drv_synd, &status);
1373                 *get_synd_ptr(out) = cpu_to_be32(drv_synd);
1374                 *get_status_ptr(out) = status;
1375                 return err;
1376         }
1377
1378         pages_queue = is_manage_pages(in);
1379         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1380
1381         inb = alloc_msg(dev, in_size, gfp);
1382         if (IS_ERR(inb)) {
1383                 err = PTR_ERR(inb);
1384                 return err;
1385         }
1386
1387         err = mlx5_copy_to_msg(inb, in, in_size);
1388         if (err) {
1389                 mlx5_core_warn(dev, "err %d\n", err);
1390                 goto out_in;
1391         }
1392
1393         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size);
1394         if (IS_ERR(outb)) {
1395                 err = PTR_ERR(outb);
1396                 goto out_in;
1397         }
1398
1399         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1400                               pages_queue, &status);
1401         if (err)
1402                 goto out_out;
1403
1404         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1405         if (status) {
1406                 err = status_to_err(status);
1407                 goto out_out;
1408         }
1409
1410         if (!callback)
1411                 err = mlx5_copy_from_msg(out, outb, out_size);
1412
1413 out_out:
1414         if (!callback)
1415                 mlx5_free_cmd_msg(dev, outb);
1416
1417 out_in:
1418         if (!callback)
1419                 free_msg(dev, inb);
1420         return err;
1421 }
1422
1423 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1424                   int out_size)
1425 {
1426         return cmd_exec(dev, in, in_size, out, out_size, NULL, NULL);
1427 }
1428 EXPORT_SYMBOL(mlx5_cmd_exec);
1429
1430 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1431                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1432                      void *context)
1433 {
1434         return cmd_exec(dev, in, in_size, out, out_size, callback, context);
1435 }
1436 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1437
1438 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1439 {
1440         struct mlx5_cmd *cmd = &dev->cmd;
1441         struct mlx5_cmd_msg *msg;
1442         struct mlx5_cmd_msg *n;
1443
1444         list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) {
1445                 list_del(&msg->list);
1446                 mlx5_free_cmd_msg(dev, msg);
1447         }
1448
1449         list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) {
1450                 list_del(&msg->list);
1451                 mlx5_free_cmd_msg(dev, msg);
1452         }
1453 }
1454
1455 static int create_msg_cache(struct mlx5_core_dev *dev)
1456 {
1457         struct mlx5_cmd *cmd = &dev->cmd;
1458         struct mlx5_cmd_msg *msg;
1459         int err;
1460         int i;
1461
1462         spin_lock_init(&cmd->cache.large.lock);
1463         INIT_LIST_HEAD(&cmd->cache.large.head);
1464         spin_lock_init(&cmd->cache.med.lock);
1465         INIT_LIST_HEAD(&cmd->cache.med.head);
1466
1467         for (i = 0; i < NUM_LONG_LISTS; i++) {
1468                 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, LONG_LIST_SIZE);
1469                 if (IS_ERR(msg)) {
1470                         err = PTR_ERR(msg);
1471                         goto ex_err;
1472                 }
1473                 msg->cache = &cmd->cache.large;
1474                 list_add_tail(&msg->list, &cmd->cache.large.head);
1475         }
1476
1477         for (i = 0; i < NUM_MED_LISTS; i++) {
1478                 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, MED_LIST_SIZE);
1479                 if (IS_ERR(msg)) {
1480                         err = PTR_ERR(msg);
1481                         goto ex_err;
1482                 }
1483                 msg->cache = &cmd->cache.med;
1484                 list_add_tail(&msg->list, &cmd->cache.med.head);
1485         }
1486
1487         return 0;
1488
1489 ex_err:
1490         destroy_msg_cache(dev);
1491         return err;
1492 }
1493
1494 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1495 {
1496         struct device *ddev = &dev->pdev->dev;
1497
1498         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1499                                                  &cmd->alloc_dma, GFP_KERNEL);
1500         if (!cmd->cmd_alloc_buf)
1501                 return -ENOMEM;
1502
1503         /* make sure it is aligned to 4K */
1504         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1505                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1506                 cmd->dma = cmd->alloc_dma;
1507                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1508                 return 0;
1509         }
1510
1511         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1512                           cmd->alloc_dma);
1513         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1514                                                  2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1515                                                  &cmd->alloc_dma, GFP_KERNEL);
1516         if (!cmd->cmd_alloc_buf)
1517                 return -ENOMEM;
1518
1519         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1520         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1521         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1522         return 0;
1523 }
1524
1525 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1526 {
1527         struct device *ddev = &dev->pdev->dev;
1528
1529         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1530                           cmd->alloc_dma);
1531 }
1532
1533 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1534 {
1535         int size = sizeof(struct mlx5_cmd_prot_block);
1536         int align = roundup_pow_of_two(size);
1537         struct mlx5_cmd *cmd = &dev->cmd;
1538         u32 cmd_h, cmd_l;
1539         u16 cmd_if_rev;
1540         int err;
1541         int i;
1542
1543         memset(cmd, 0, sizeof(*cmd));
1544         cmd_if_rev = cmdif_rev(dev);
1545         if (cmd_if_rev != CMD_IF_REV) {
1546                 dev_err(&dev->pdev->dev,
1547                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1548                         CMD_IF_REV, cmd_if_rev);
1549                 return -EINVAL;
1550         }
1551
1552         cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1553         if (!cmd->pool)
1554                 return -ENOMEM;
1555
1556         err = alloc_cmd_page(dev, cmd);
1557         if (err)
1558                 goto err_free_pool;
1559
1560         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1561         cmd->log_sz = cmd_l >> 4 & 0xf;
1562         cmd->log_stride = cmd_l & 0xf;
1563         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1564                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1565                         1 << cmd->log_sz);
1566                 err = -EINVAL;
1567                 goto err_free_page;
1568         }
1569
1570         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1571                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1572                 err = -EINVAL;
1573                 goto err_free_page;
1574         }
1575
1576         cmd->checksum_disabled = 1;
1577         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1578         cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1579
1580         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1581         if (cmd->cmdif_rev > CMD_IF_REV) {
1582                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1583                         CMD_IF_REV, cmd->cmdif_rev);
1584                 err = -ENOTSUPP;
1585                 goto err_free_page;
1586         }
1587
1588         spin_lock_init(&cmd->alloc_lock);
1589         spin_lock_init(&cmd->token_lock);
1590         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1591                 spin_lock_init(&cmd->stats[i].lock);
1592
1593         sema_init(&cmd->sem, cmd->max_reg_cmds);
1594         sema_init(&cmd->pages_sem, 1);
1595
1596         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1597         cmd_l = (u32)(cmd->dma);
1598         if (cmd_l & 0xfff) {
1599                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1600                 err = -ENOMEM;
1601                 goto err_free_page;
1602         }
1603
1604         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1605         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1606
1607         /* Make sure firmware sees the complete address before we proceed */
1608         wmb();
1609
1610         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1611
1612         cmd->mode = CMD_MODE_POLLING;
1613
1614         err = create_msg_cache(dev);
1615         if (err) {
1616                 dev_err(&dev->pdev->dev, "failed to create command cache\n");
1617                 goto err_free_page;
1618         }
1619
1620         set_wqname(dev);
1621         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1622         if (!cmd->wq) {
1623                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1624                 err = -ENOMEM;
1625                 goto err_cache;
1626         }
1627
1628         err = create_debugfs_files(dev);
1629         if (err) {
1630                 err = -ENOMEM;
1631                 goto err_wq;
1632         }
1633
1634         return 0;
1635
1636 err_wq:
1637         destroy_workqueue(cmd->wq);
1638
1639 err_cache:
1640         destroy_msg_cache(dev);
1641
1642 err_free_page:
1643         free_cmd_page(dev, cmd);
1644
1645 err_free_pool:
1646         pci_pool_destroy(cmd->pool);
1647
1648         return err;
1649 }
1650 EXPORT_SYMBOL(mlx5_cmd_init);
1651
1652 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1653 {
1654         struct mlx5_cmd *cmd = &dev->cmd;
1655
1656         clean_debug_files(dev);
1657         destroy_workqueue(cmd->wq);
1658         destroy_msg_cache(dev);
1659         free_cmd_page(dev, cmd);
1660         pci_pool_destroy(cmd->pool);
1661 }
1662 EXPORT_SYMBOL(mlx5_cmd_cleanup);
1663
1664 static const char *cmd_status_str(u8 status)
1665 {
1666         switch (status) {
1667         case MLX5_CMD_STAT_OK:
1668                 return "OK";
1669         case MLX5_CMD_STAT_INT_ERR:
1670                 return "internal error";
1671         case MLX5_CMD_STAT_BAD_OP_ERR:
1672                 return "bad operation";
1673         case MLX5_CMD_STAT_BAD_PARAM_ERR:
1674                 return "bad parameter";
1675         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
1676                 return "bad system state";
1677         case MLX5_CMD_STAT_BAD_RES_ERR:
1678                 return "bad resource";
1679         case MLX5_CMD_STAT_RES_BUSY:
1680                 return "resource busy";
1681         case MLX5_CMD_STAT_LIM_ERR:
1682                 return "limits exceeded";
1683         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
1684                 return "bad resource state";
1685         case MLX5_CMD_STAT_IX_ERR:
1686                 return "bad index";
1687         case MLX5_CMD_STAT_NO_RES_ERR:
1688                 return "no resources";
1689         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
1690                 return "bad input length";
1691         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
1692                 return "bad output length";
1693         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
1694                 return "bad QP state";
1695         case MLX5_CMD_STAT_BAD_PKT_ERR:
1696                 return "bad packet (discarded)";
1697         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
1698                 return "bad size too many outstanding CQEs";
1699         default:
1700                 return "unknown status";
1701         }
1702 }
1703
1704 static int cmd_status_to_err(u8 status)
1705 {
1706         switch (status) {
1707         case MLX5_CMD_STAT_OK:                          return 0;
1708         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
1709         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
1710         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
1711         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
1712         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
1713         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
1714         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
1715         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
1716         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
1717         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
1718         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
1719         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
1720         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
1721         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
1722         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
1723         default:                                        return -EIO;
1724         }
1725 }
1726
1727 /* this will be available till all the commands use set/get macros */
1728 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr)
1729 {
1730         if (!hdr->status)
1731                 return 0;
1732
1733         pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1734                 cmd_status_str(hdr->status), hdr->status,
1735                 be32_to_cpu(hdr->syndrome));
1736
1737         return cmd_status_to_err(hdr->status);
1738 }
1739
1740 int mlx5_cmd_status_to_err_v2(void *ptr)
1741 {
1742         u32     syndrome;
1743         u8      status;
1744
1745         status = be32_to_cpu(*(__be32 *)ptr) >> 24;
1746         if (!status)
1747                 return 0;
1748
1749         syndrome = be32_to_cpu(*(__be32 *)(ptr + 4));
1750
1751         pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1752                 cmd_status_str(status), status, syndrome);
1753
1754         return cmd_status_to_err(status);
1755 }