2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
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8 * OpenIB.org BSD license below:
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11 * without modification, are permitted provided that the following
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15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/if_vlan.h>
34 #include <linux/etherdevice.h>
35 #include <linux/mlx5/driver.h>
36 #include <linux/mlx5/qp.h>
37 #include <linux/mlx5/cq.h>
38 #include <linux/mlx5/vport.h>
41 #include "mlx5_core.h"
43 #define MLX5E_MAX_NUM_TC 8
45 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7
46 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
47 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
49 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7
50 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
51 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
53 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (16 * 1024)
54 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
55 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
56 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
57 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
58 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
59 #define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7
61 #define MLX5E_TX_CQ_POLL_BUDGET 128
62 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
64 static const char vport_strings[][ETH_GSTRING_LEN] = {
65 /* vport statistics */
78 "rx_multicast_packets",
80 "tx_multicast_packets",
82 "rx_broadcast_packets",
84 "tx_broadcast_packets",
101 struct mlx5e_vport_stats {
107 u64 rx_error_packets;
109 u64 tx_error_packets;
111 u64 rx_unicast_packets;
112 u64 rx_unicast_bytes;
113 u64 tx_unicast_packets;
114 u64 tx_unicast_bytes;
115 u64 rx_multicast_packets;
116 u64 rx_multicast_bytes;
117 u64 tx_multicast_packets;
118 u64 tx_multicast_bytes;
119 u64 rx_broadcast_packets;
120 u64 rx_broadcast_bytes;
121 u64 tx_broadcast_packets;
122 u64 tx_broadcast_bytes;
132 u64 tx_queue_stopped;
134 u64 tx_queue_dropped;
137 #define NUM_VPORT_COUNTERS 31
140 static const char rq_stats_strings[][ETH_GSTRING_LEN] = {
148 struct mlx5e_rq_stats {
154 #define NUM_RQ_STATS 5
157 static const char sq_stats_strings[][ETH_GSTRING_LEN] = {
168 struct mlx5e_sq_stats {
172 u64 csum_offload_none;
177 #define NUM_SQ_STATS 8
181 struct mlx5e_vport_stats vport;
184 struct mlx5e_params {
188 u8 default_vlan_prio;
190 u16 rx_cq_moderation_usec;
191 u16 rx_cq_moderation_pkts;
192 u16 tx_cq_moderation_usec;
193 u16 tx_cq_moderation_pkts;
195 u16 rx_hash_log_tbl_sz;
201 MLX5E_RQ_STATE_POST_WQES_ENABLE,
205 MLX5E_CQ_HAS_CQES = 1,
209 /* data path - accessed per cqe */
214 /* data path - accessed per napi poll */
215 struct napi_struct *napi;
216 struct mlx5_core_cq mcq;
217 struct mlx5e_channel *channel;
220 struct mlx5_wq_ctrl wq_ctrl;
221 } ____cacheline_aligned_in_smp;
225 struct mlx5_wq_ll wq;
227 struct sk_buff **skb;
230 struct net_device *netdev;
231 struct mlx5e_rq_stats stats;
238 struct mlx5_wq_ctrl wq_ctrl;
240 struct mlx5e_channel *channel;
241 } ____cacheline_aligned_in_smp;
243 struct mlx5e_tx_skb_cb {
249 #define MLX5E_TX_SKB_CB(__skb) ((struct mlx5e_tx_skb_cb *)__skb->cb)
251 struct mlx5e_sq_dma {
257 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
263 /* dirtied @completion */
268 u16 pc ____cacheline_aligned_in_smp;
271 struct mlx5e_sq_stats stats;
275 /* pointers to per packet info: write@xmit, read@completion */
276 struct sk_buff **skb;
277 struct mlx5e_sq_dma *dma_fifo;
280 struct mlx5_wq_cyc wq;
282 void __iomem *uar_map;
283 struct netdev_queue *txq;
291 struct mlx5_wq_ctrl wq_ctrl;
293 struct mlx5e_channel *channel;
295 } ____cacheline_aligned_in_smp;
297 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
299 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
304 MLX5E_CHANNEL_NAPI_SCHED = 1,
307 struct mlx5e_channel {
310 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
311 struct napi_struct napi;
313 struct net_device *netdev;
319 struct mlx5e_priv *priv;
324 enum mlx5e_traffic_types {
325 MLX5E_TT_IPV4_TCP = 0,
326 MLX5E_TT_IPV6_TCP = 1,
327 MLX5E_TT_IPV4_UDP = 2,
328 MLX5E_TT_IPV6_UDP = 3,
336 MLX5E_RQT_SPREADING = 0,
337 MLX5E_RQT_DEFAULT_RQ = 1,
341 struct mlx5e_eth_addr_info {
342 u8 addr[ETH_ALEN + 2];
344 u32 ft_ix[MLX5E_NUM_TT]; /* flow table index per traffic type */
347 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
349 struct mlx5e_eth_addr_db {
350 struct hlist_head netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE];
351 struct hlist_head netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE];
352 struct mlx5e_eth_addr_info broadcast;
353 struct mlx5e_eth_addr_info allmulti;
354 struct mlx5e_eth_addr_info promisc;
355 bool broadcast_enabled;
356 bool allmulti_enabled;
357 bool promisc_enabled;
361 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
365 struct mlx5e_vlan_db {
366 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
367 u32 active_vlans_ft_ix[VLAN_N_VID];
368 u32 untagged_rule_ft_ix;
369 u32 any_vlan_rule_ft_ix;
370 bool filter_disabled;
373 struct mlx5e_flow_table {
379 /* priv data path fields - start */
380 int order_base_2_num_channels;
381 int queue_mapping_channel_mask;
383 int default_vlan_prio;
384 /* priv data path fields - end */
387 struct mutex state_lock; /* Protects Interface state */
388 struct mlx5_uar cq_uar;
390 struct mlx5_core_mr mr;
392 struct mlx5e_channel **channel;
393 u32 tisn[MLX5E_MAX_NUM_TC];
395 u32 tirn[MLX5E_NUM_TT];
397 struct mlx5e_flow_table ft;
398 struct mlx5e_eth_addr_db eth_addr;
399 struct mlx5e_vlan_db vlan;
401 struct mlx5e_params params;
402 spinlock_t async_events_spinlock; /* sync hw events */
403 struct work_struct update_carrier_work;
404 struct work_struct set_rx_mode_work;
405 struct delayed_work update_stats_work;
407 struct mlx5_core_dev *mdev;
408 struct net_device *netdev;
409 struct mlx5e_stats stats;
412 #define MLX5E_NET_IP_ALIGN 2
414 struct mlx5e_tx_wqe {
415 struct mlx5_wqe_ctrl_seg ctrl;
416 struct mlx5_wqe_eth_seg eth;
419 struct mlx5e_rx_wqe {
420 struct mlx5_wqe_srq_next_seg next;
421 struct mlx5_wqe_data_seg data;
424 enum mlx5e_link_mode {
425 MLX5E_1000BASE_CX_SGMII = 0,
426 MLX5E_1000BASE_KX = 1,
427 MLX5E_10GBASE_CX4 = 2,
428 MLX5E_10GBASE_KX4 = 3,
429 MLX5E_10GBASE_KR = 4,
430 MLX5E_20GBASE_KR2 = 5,
431 MLX5E_40GBASE_CR4 = 6,
432 MLX5E_40GBASE_KR4 = 7,
433 MLX5E_56GBASE_R4 = 8,
434 MLX5E_10GBASE_CR = 12,
435 MLX5E_10GBASE_SR = 13,
436 MLX5E_10GBASE_ER = 14,
437 MLX5E_40GBASE_SR4 = 15,
438 MLX5E_40GBASE_LR4 = 16,
439 MLX5E_100GBASE_CR4 = 20,
440 MLX5E_100GBASE_SR4 = 21,
441 MLX5E_100GBASE_KR4 = 22,
442 MLX5E_100GBASE_LR4 = 23,
443 MLX5E_100BASE_TX = 24,
444 MLX5E_100BASE_T = 25,
445 MLX5E_10GBASE_T = 26,
446 MLX5E_25GBASE_CR = 27,
447 MLX5E_25GBASE_KR = 28,
448 MLX5E_25GBASE_SR = 29,
449 MLX5E_50GBASE_CR2 = 30,
450 MLX5E_50GBASE_KR2 = 31,
451 MLX5E_LINK_MODES_NUMBER,
454 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
456 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
457 void *accel_priv, select_queue_fallback_t fallback);
458 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
459 netdev_tx_t mlx5e_xmit_multi_tc(struct sk_buff *skb, struct net_device *dev);
461 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
462 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
463 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
464 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq);
465 bool mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
466 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
467 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
469 void mlx5e_update_stats(struct mlx5e_priv *priv);
471 int mlx5e_open_flow_table(struct mlx5e_priv *priv);
472 void mlx5e_close_flow_table(struct mlx5e_priv *priv);
473 void mlx5e_init_eth_addr(struct mlx5e_priv *priv);
474 void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv);
475 void mlx5e_set_rx_mode_work(struct work_struct *work);
477 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
479 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
481 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
482 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
483 int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv);
484 void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv);
486 int mlx5e_open_locked(struct net_device *netdev);
487 int mlx5e_close_locked(struct net_device *netdev);
488 int mlx5e_update_priv_params(struct mlx5e_priv *priv,
489 struct mlx5e_params *new_params);
491 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
492 struct mlx5e_tx_wqe *wqe)
494 /* ensure wqe is visible to device before updating doorbell record */
497 *sq->wq.db = cpu_to_be32(sq->pc);
499 /* ensure doorbell record is visible to device before ringing the
504 mlx5_write64((__be32 *)&wqe->ctrl,
505 sq->uar_map + MLX5_BF_OFFSET + sq->bf_offset,
508 sq->bf_offset ^= sq->bf_buf_size;
511 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
513 struct mlx5_core_cq *mcq;
516 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
519 extern const struct ethtool_ops mlx5e_ethtool_ops;