drivers/net/ethernet/mellanox/mlx5/core/en_clock.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/clocksource.h>
  34 #include "en.h"
  35
  36 enum {
  37         MLX5E_CYCLES_SHIFT      = 23
  38 };
  39
  40 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *tstamp, u64 timestamp,
  41                         struct skb_shared_hwtstamps *hwts)
  42 {
  43         u64 nsec;
  44
  45         read_lock(&tstamp->lock);
  46         nsec = timecounter_cyc2time(&tstamp->clock, timestamp);
  47         read_unlock(&tstamp->lock);
  48
  49         hwts->hwtstamp = ns_to_ktime(nsec);
  50 }
  51
  52 static cycle_t mlx5e_read_internal_timer(const struct cyclecounter *cc)
  53 {
  54         struct mlx5e_tstamp *tstamp = container_of(cc, struct mlx5e_tstamp,
  55                                                    cycles);
  56
  57         return mlx5_read_internal_timer(tstamp->mdev) & cc->mask;
  58 }
  59
  60 static void mlx5e_timestamp_overflow(struct work_struct *work)
  61 {
  62         struct delayed_work *dwork = to_delayed_work(work);
  63         struct mlx5e_tstamp *tstamp = container_of(dwork, struct mlx5e_tstamp,
  64                                                    overflow_work);
  65         unsigned long flags;
  66
  67         write_lock_irqsave(&tstamp->lock, flags);
  68         timecounter_read(&tstamp->clock);
  69         write_unlock_irqrestore(&tstamp->lock, flags);
  70         schedule_delayed_work(&tstamp->overflow_work, tstamp->overflow_period);
  71 }
  72
  73 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr)
  74 {
  75         struct mlx5e_priv *priv = netdev_priv(dev);
  76         struct hwtstamp_config config;
  77
  78         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
  79                 return -EOPNOTSUPP;
  80
  81         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
  82                 return -EFAULT;
  83
  84         /* TX HW timestamp */
  85         switch (config.tx_type) {
  86         case HWTSTAMP_TX_OFF:
  87         case HWTSTAMP_TX_ON:
  88                 break;
  89         default:
  90                 return -ERANGE;
  91         }
  92
  93         /* RX HW timestamp */
  94         switch (config.rx_filter) {
  95         case HWTSTAMP_FILTER_NONE:
  96                 break;
  97         case HWTSTAMP_FILTER_ALL:
  98         case HWTSTAMP_FILTER_SOME:
  99         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 100         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 101         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 102         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 103         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 104         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 105         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 106         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
 107         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
 108         case HWTSTAMP_FILTER_PTP_V2_EVENT:
 109         case HWTSTAMP_FILTER_PTP_V2_SYNC:
 110         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 111                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 112                 break;
 113         default:
 114                 return -ERANGE;
 115         }
 116
 117         memcpy(&priv->tstamp.hwtstamp_config, &config, sizeof(config));
 118
 119         return copy_to_user(ifr->ifr_data, &config,
 120                             sizeof(config)) ? -EFAULT : 0;
 121 }
 122
 123 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr)
 124 {
 125         struct mlx5e_priv *priv = netdev_priv(dev);
 126         struct hwtstamp_config *cfg = &priv->tstamp.hwtstamp_config;
 127
 128         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
 129                 return -EOPNOTSUPP;
 130
 131         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
 132 }
 133
 134 static int mlx5e_ptp_settime(struct ptp_clock_info *ptp,
 135                              const struct timespec64 *ts)
 136 {
 137         struct mlx5e_tstamp *tstamp = container_of(ptp, struct mlx5e_tstamp,
 138                                                    ptp_info);
 139         u64 ns = timespec64_to_ns(ts);
 140         unsigned long flags;
 141
 142         write_lock_irqsave(&tstamp->lock, flags);
 143         timecounter_init(&tstamp->clock, &tstamp->cycles, ns);
 144         write_unlock_irqrestore(&tstamp->lock, flags);
 145
 146         return 0;
 147 }
 148
 149 static int mlx5e_ptp_gettime(struct ptp_clock_info *ptp,
 150                              struct timespec64 *ts)
 151 {
 152         struct mlx5e_tstamp *tstamp = container_of(ptp, struct mlx5e_tstamp,
 153                                                    ptp_info);
 154         u64 ns;
 155         unsigned long flags;
 156
 157         write_lock_irqsave(&tstamp->lock, flags);
 158         ns = timecounter_read(&tstamp->clock);
 159         write_unlock_irqrestore(&tstamp->lock, flags);
 160
 161         *ts = ns_to_timespec64(ns);
 162
 163         return 0;
 164 }
 165
 166 static int mlx5e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
 167 {
 168         struct mlx5e_tstamp *tstamp = container_of(ptp, struct mlx5e_tstamp,
 169                                                    ptp_info);
 170         unsigned long flags;
 171
 172         write_lock_irqsave(&tstamp->lock, flags);
 173         timecounter_adjtime(&tstamp->clock, delta);
 174         write_unlock_irqrestore(&tstamp->lock, flags);
 175
 176         return 0;
 177 }
 178
 179 static int mlx5e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 delta)
 180 {
 181         u64 adj;
 182         u32 diff;
 183         unsigned long flags;
 184         int neg_adj = 0;
 185         struct mlx5e_tstamp *tstamp = container_of(ptp, struct mlx5e_tstamp,
 186                                                   ptp_info);
 187
 188         if (delta < 0) {
 189                 neg_adj = 1;
 190                 delta = -delta;
 191         }
 192
 193         adj = tstamp->nominal_c_mult;
 194         adj *= delta;
 195         diff = div_u64(adj, 1000000000ULL);
 196
 197         write_lock_irqsave(&tstamp->lock, flags);
 198         timecounter_read(&tstamp->clock);
 199         tstamp->cycles.mult = neg_adj ? tstamp->nominal_c_mult - diff :
 200                                         tstamp->nominal_c_mult + diff;
 201         write_unlock_irqrestore(&tstamp->lock, flags);
 202
 203         return 0;
 204 }
 205
 206 static const struct ptp_clock_info mlx5e_ptp_clock_info = {
 207         .owner          = THIS_MODULE,
 208         .max_adj        = 100000000,
 209         .n_alarm        = 0,
 210         .n_ext_ts       = 0,
 211         .n_per_out      = 0,
 212         .n_pins         = 0,
 213         .pps            = 0,
 214         .adjfreq        = mlx5e_ptp_adjfreq,
 215         .adjtime        = mlx5e_ptp_adjtime,
 216         .gettime64      = mlx5e_ptp_gettime,
 217         .settime64      = mlx5e_ptp_settime,
 218         .enable         = NULL,
 219 };
 220
 221 static void mlx5e_timestamp_init_config(struct mlx5e_tstamp *tstamp)
 222 {
 223         tstamp->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF;
 224         tstamp->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
 225 }
 226
 227 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
 228 {
 229         struct mlx5e_tstamp *tstamp = &priv->tstamp;
 230         u64 ns;
 231         u64 frac = 0;
 232         u32 dev_freq;
 233
 234         mlx5e_timestamp_init_config(tstamp);
 235         dev_freq = MLX5_CAP_GEN(priv->mdev, device_frequency_khz);
 236         if (!dev_freq) {
 237                 mlx5_core_warn(priv->mdev, "invalid device_frequency_khz, aborting HW clock init\n");
 238                 return;
 239         }
 240         rwlock_init(&tstamp->lock);
 241         tstamp->cycles.read = mlx5e_read_internal_timer;
 242         tstamp->cycles.shift = MLX5E_CYCLES_SHIFT;
 243         tstamp->cycles.mult = clocksource_khz2mult(dev_freq,
 244                                                    tstamp->cycles.shift);
 245         tstamp->nominal_c_mult = tstamp->cycles.mult;
 246         tstamp->cycles.mask = CLOCKSOURCE_MASK(41);
 247         tstamp->mdev = priv->mdev;
 248
 249         timecounter_init(&tstamp->clock, &tstamp->cycles,
 250                          ktime_to_ns(ktime_get_real()));
 251
 252         /* Calculate period in seconds to call the overflow watchdog - to make
 253          * sure counter is checked at least once every wrap around.
 254          */
 255         ns = cyclecounter_cyc2ns(&tstamp->cycles, tstamp->cycles.mask,
 256                                  frac, &frac);
 257         do_div(ns, NSEC_PER_SEC / 2 / HZ);
 258         tstamp->overflow_period = ns;
 259
 260         INIT_DELAYED_WORK(&tstamp->overflow_work, mlx5e_timestamp_overflow);
 261         if (tstamp->overflow_period)
 262                 schedule_delayed_work(&tstamp->overflow_work, 0);
 263         else
 264                 mlx5_core_warn(priv->mdev, "invalid overflow period, overflow_work is not scheduled\n");
 265
 266         /* Configure the PHC */
 267         tstamp->ptp_info = mlx5e_ptp_clock_info;
 268         snprintf(tstamp->ptp_info.name, 16, "mlx5 ptp");
 269
 270         tstamp->ptp = ptp_clock_register(&tstamp->ptp_info,
 271                                          &priv->mdev->pdev->dev);
 272         if (IS_ERR_OR_NULL(tstamp->ptp)) {
 273                 mlx5_core_warn(priv->mdev, "ptp_clock_register failed %ld\n",
 274                                PTR_ERR(tstamp->ptp));
 275                 tstamp->ptp = NULL;
 276         }
 277 }
 278
 279 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv)
 280 {
 281         struct mlx5e_tstamp *tstamp = &priv->tstamp;
 282
 283         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
 284                 return;
 285
 286         if (priv->tstamp.ptp) {
 287                 ptp_clock_unregister(priv->tstamp.ptp);
 288                 priv->tstamp.ptp = NULL;
 289         }
 290
 291         cancel_delayed_work_sync(&tstamp->overflow_work);
 292 }