2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 static void mlx5e_get_drvinfo(struct net_device *dev,
36 struct ethtool_drvinfo *drvinfo)
38 struct mlx5e_priv *priv = netdev_priv(dev);
39 struct mlx5_core_dev *mdev = priv->mdev;
41 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
42 strlcpy(drvinfo->version, DRIVER_VERSION " (" DRIVER_RELDATE ")",
43 sizeof(drvinfo->version));
44 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
46 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev));
47 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
48 sizeof(drvinfo->bus_info));
55 } ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER] = {
56 [MLX5E_1000BASE_CX_SGMII] = {
57 .supported = SUPPORTED_1000baseKX_Full,
58 .advertised = ADVERTISED_1000baseKX_Full,
61 [MLX5E_1000BASE_KX] = {
62 .supported = SUPPORTED_1000baseKX_Full,
63 .advertised = ADVERTISED_1000baseKX_Full,
66 [MLX5E_10GBASE_CX4] = {
67 .supported = SUPPORTED_10000baseKX4_Full,
68 .advertised = ADVERTISED_10000baseKX4_Full,
71 [MLX5E_10GBASE_KX4] = {
72 .supported = SUPPORTED_10000baseKX4_Full,
73 .advertised = ADVERTISED_10000baseKX4_Full,
76 [MLX5E_10GBASE_KR] = {
77 .supported = SUPPORTED_10000baseKR_Full,
78 .advertised = ADVERTISED_10000baseKR_Full,
81 [MLX5E_20GBASE_KR2] = {
82 .supported = SUPPORTED_20000baseKR2_Full,
83 .advertised = ADVERTISED_20000baseKR2_Full,
86 [MLX5E_40GBASE_CR4] = {
87 .supported = SUPPORTED_40000baseCR4_Full,
88 .advertised = ADVERTISED_40000baseCR4_Full,
91 [MLX5E_40GBASE_KR4] = {
92 .supported = SUPPORTED_40000baseKR4_Full,
93 .advertised = ADVERTISED_40000baseKR4_Full,
96 [MLX5E_56GBASE_R4] = {
97 .supported = SUPPORTED_56000baseKR4_Full,
98 .advertised = ADVERTISED_56000baseKR4_Full,
101 [MLX5E_10GBASE_CR] = {
102 .supported = SUPPORTED_10000baseKR_Full,
103 .advertised = ADVERTISED_10000baseKR_Full,
106 [MLX5E_10GBASE_SR] = {
107 .supported = SUPPORTED_10000baseKR_Full,
108 .advertised = ADVERTISED_10000baseKR_Full,
111 [MLX5E_10GBASE_ER] = {
112 .supported = SUPPORTED_10000baseKR_Full,
113 .advertised = ADVERTISED_10000baseKR_Full,
116 [MLX5E_40GBASE_SR4] = {
117 .supported = SUPPORTED_40000baseSR4_Full,
118 .advertised = ADVERTISED_40000baseSR4_Full,
121 [MLX5E_40GBASE_LR4] = {
122 .supported = SUPPORTED_40000baseLR4_Full,
123 .advertised = ADVERTISED_40000baseLR4_Full,
126 [MLX5E_100GBASE_CR4] = {
129 [MLX5E_100GBASE_SR4] = {
132 [MLX5E_100GBASE_KR4] = {
135 [MLX5E_100GBASE_LR4] = {
138 [MLX5E_100BASE_TX] = {
141 [MLX5E_100BASE_T] = {
142 .supported = SUPPORTED_100baseT_Full,
143 .advertised = ADVERTISED_100baseT_Full,
146 [MLX5E_10GBASE_T] = {
147 .supported = SUPPORTED_10000baseT_Full,
148 .advertised = ADVERTISED_10000baseT_Full,
151 [MLX5E_25GBASE_CR] = {
154 [MLX5E_25GBASE_KR] = {
157 [MLX5E_25GBASE_SR] = {
160 [MLX5E_50GBASE_CR2] = {
163 [MLX5E_50GBASE_KR2] = {
168 #define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter))
170 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
172 struct mlx5e_priv *priv = netdev_priv(dev);
176 return NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS +
177 MLX5E_NUM_Q_CNTRS(priv) +
178 priv->params.num_channels * NUM_RQ_STATS +
179 priv->params.num_channels * priv->params.num_tc *
187 static void mlx5e_get_strings(struct net_device *dev,
188 uint32_t stringset, uint8_t *data)
190 int i, j, tc, idx = 0;
191 struct mlx5e_priv *priv = netdev_priv(dev);
194 case ETH_SS_PRIV_FLAGS:
202 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
203 strcpy(data + (idx++) * ETH_GSTRING_LEN,
207 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
208 strcpy(data + (idx++) * ETH_GSTRING_LEN,
209 qcounter_stats_strings[i]);
212 for (i = 0; i < NUM_PPORT_COUNTERS; i++)
213 strcpy(data + (idx++) * ETH_GSTRING_LEN,
216 /* per channel counters */
217 for (i = 0; i < priv->params.num_channels; i++)
218 for (j = 0; j < NUM_RQ_STATS; j++)
219 sprintf(data + (idx++) * ETH_GSTRING_LEN,
220 "rx%d_%s", i, rq_stats_strings[j]);
222 for (tc = 0; tc < priv->params.num_tc; tc++)
223 for (i = 0; i < priv->params.num_channels; i++)
224 for (j = 0; j < NUM_SQ_STATS; j++)
226 (idx++) * ETH_GSTRING_LEN,
228 priv->channeltc_to_txq_map[i][tc],
229 sq_stats_strings[j]);
234 static void mlx5e_get_ethtool_stats(struct net_device *dev,
235 struct ethtool_stats *stats, u64 *data)
237 struct mlx5e_priv *priv = netdev_priv(dev);
238 int i, j, tc, idx = 0;
243 mutex_lock(&priv->state_lock);
244 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
245 mlx5e_update_stats(priv);
246 mutex_unlock(&priv->state_lock);
248 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
249 data[idx++] = ((u64 *)&priv->stats.vport)[i];
251 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
252 data[idx++] = ((u32 *)&priv->stats.qcnt)[i];
254 for (i = 0; i < NUM_PPORT_COUNTERS; i++)
255 data[idx++] = be64_to_cpu(((__be64 *)&priv->stats.pport)[i]);
257 /* per channel counters */
258 for (i = 0; i < priv->params.num_channels; i++)
259 for (j = 0; j < NUM_RQ_STATS; j++)
260 data[idx++] = !test_bit(MLX5E_STATE_OPENED,
262 ((u64 *)&priv->channel[i]->rq.stats)[j];
264 for (tc = 0; tc < priv->params.num_tc; tc++)
265 for (i = 0; i < priv->params.num_channels; i++)
266 for (j = 0; j < NUM_SQ_STATS; j++)
267 data[idx++] = !test_bit(MLX5E_STATE_OPENED,
269 ((u64 *)&priv->channel[i]->sq[tc].stats)[j];
272 static void mlx5e_get_ringparam(struct net_device *dev,
273 struct ethtool_ringparam *param)
275 struct mlx5e_priv *priv = netdev_priv(dev);
276 int rq_wq_type = priv->params.rq_wq_type;
278 param->rx_max_pending = 1 << mlx5_max_log_rq_size(rq_wq_type);
279 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
280 param->rx_pending = 1 << priv->params.log_rq_size;
281 param->tx_pending = 1 << priv->params.log_sq_size;
284 static int mlx5e_set_ringparam(struct net_device *dev,
285 struct ethtool_ringparam *param)
287 struct mlx5e_priv *priv = netdev_priv(dev);
289 int rq_wq_type = priv->params.rq_wq_type;
295 if (param->rx_jumbo_pending) {
296 netdev_info(dev, "%s: rx_jumbo_pending not supported\n",
300 if (param->rx_mini_pending) {
301 netdev_info(dev, "%s: rx_mini_pending not supported\n",
305 if (param->rx_pending < (1 << mlx5_min_log_rq_size(rq_wq_type))) {
306 netdev_info(dev, "%s: rx_pending (%d) < min (%d)\n",
307 __func__, param->rx_pending,
308 1 << mlx5_min_log_rq_size(rq_wq_type));
311 if (param->rx_pending > (1 << mlx5_max_log_rq_size(rq_wq_type))) {
312 netdev_info(dev, "%s: rx_pending (%d) > max (%d)\n",
313 __func__, param->rx_pending,
314 1 << mlx5_max_log_rq_size(rq_wq_type));
317 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
318 netdev_info(dev, "%s: tx_pending (%d) < min (%d)\n",
319 __func__, param->tx_pending,
320 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
323 if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
324 netdev_info(dev, "%s: tx_pending (%d) > max (%d)\n",
325 __func__, param->tx_pending,
326 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
330 log_rq_size = order_base_2(param->rx_pending);
331 log_sq_size = order_base_2(param->tx_pending);
332 min_rx_wqes = mlx5_min_rx_wqes(rq_wq_type, param->rx_pending);
334 if (log_rq_size == priv->params.log_rq_size &&
335 log_sq_size == priv->params.log_sq_size &&
336 min_rx_wqes == priv->params.min_rx_wqes)
339 mutex_lock(&priv->state_lock);
341 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
343 mlx5e_close_locked(dev);
345 priv->params.log_rq_size = log_rq_size;
346 priv->params.log_sq_size = log_sq_size;
347 priv->params.min_rx_wqes = min_rx_wqes;
350 err = mlx5e_open_locked(dev);
352 mutex_unlock(&priv->state_lock);
357 static void mlx5e_get_channels(struct net_device *dev,
358 struct ethtool_channels *ch)
360 struct mlx5e_priv *priv = netdev_priv(dev);
362 ch->max_combined = mlx5e_get_max_num_channels(priv->mdev);
363 ch->combined_count = priv->params.num_channels;
366 static int mlx5e_set_channels(struct net_device *dev,
367 struct ethtool_channels *ch)
369 struct mlx5e_priv *priv = netdev_priv(dev);
370 int ncv = mlx5e_get_max_num_channels(priv->mdev);
371 unsigned int count = ch->combined_count;
376 netdev_info(dev, "%s: combined_count=0 not supported\n",
380 if (ch->rx_count || ch->tx_count) {
381 netdev_info(dev, "%s: separate rx/tx count not supported\n",
386 netdev_info(dev, "%s: count (%d) > max (%d)\n",
387 __func__, count, ncv);
391 if (priv->params.num_channels == count)
394 mutex_lock(&priv->state_lock);
396 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
398 mlx5e_close_locked(dev);
400 priv->params.num_channels = count;
401 mlx5e_build_default_indir_rqt(priv->mdev, priv->params.indirection_rqt,
402 MLX5E_INDIR_RQT_SIZE, count);
405 err = mlx5e_open_locked(dev);
407 mutex_unlock(&priv->state_lock);
412 static int mlx5e_get_coalesce(struct net_device *netdev,
413 struct ethtool_coalesce *coal)
415 struct mlx5e_priv *priv = netdev_priv(netdev);
417 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
420 coal->rx_coalesce_usecs = priv->params.rx_cq_moderation_usec;
421 coal->rx_max_coalesced_frames = priv->params.rx_cq_moderation_pkts;
422 coal->tx_coalesce_usecs = priv->params.tx_cq_moderation_usec;
423 coal->tx_max_coalesced_frames = priv->params.tx_cq_moderation_pkts;
428 static int mlx5e_set_coalesce(struct net_device *netdev,
429 struct ethtool_coalesce *coal)
431 struct mlx5e_priv *priv = netdev_priv(netdev);
432 struct mlx5_core_dev *mdev = priv->mdev;
433 struct mlx5e_channel *c;
437 if (!MLX5_CAP_GEN(mdev, cq_moderation))
440 mutex_lock(&priv->state_lock);
441 priv->params.tx_cq_moderation_usec = coal->tx_coalesce_usecs;
442 priv->params.tx_cq_moderation_pkts = coal->tx_max_coalesced_frames;
443 priv->params.rx_cq_moderation_usec = coal->rx_coalesce_usecs;
444 priv->params.rx_cq_moderation_pkts = coal->rx_max_coalesced_frames;
446 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
449 for (i = 0; i < priv->params.num_channels; ++i) {
450 c = priv->channel[i];
452 for (tc = 0; tc < c->num_tc; tc++) {
453 mlx5_core_modify_cq_moderation(mdev,
455 coal->tx_coalesce_usecs,
456 coal->tx_max_coalesced_frames);
459 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
460 coal->rx_coalesce_usecs,
461 coal->rx_max_coalesced_frames);
465 mutex_unlock(&priv->state_lock);
469 static u32 ptys2ethtool_supported_link(u32 eth_proto_cap)
472 u32 supported_modes = 0;
474 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
475 if (eth_proto_cap & MLX5E_PROT_MASK(i))
476 supported_modes |= ptys2ethtool_table[i].supported;
478 return supported_modes;
481 static u32 ptys2ethtool_adver_link(u32 eth_proto_cap)
484 u32 advertising_modes = 0;
486 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
487 if (eth_proto_cap & MLX5E_PROT_MASK(i))
488 advertising_modes |= ptys2ethtool_table[i].advertised;
490 return advertising_modes;
493 static u32 ptys2ethtool_supported_port(u32 eth_proto_cap)
495 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
496 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
497 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
498 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
499 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
500 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
501 return SUPPORTED_FIBRE;
504 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
505 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
506 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
507 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
508 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
509 return SUPPORTED_Backplane;
514 static void get_speed_duplex(struct net_device *netdev,
516 struct ethtool_cmd *cmd)
519 u32 speed = SPEED_UNKNOWN;
520 u8 duplex = DUPLEX_UNKNOWN;
522 if (!netif_carrier_ok(netdev))
525 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
526 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
527 speed = ptys2ethtool_table[i].speed;
528 duplex = DUPLEX_FULL;
533 ethtool_cmd_speed_set(cmd, speed);
534 cmd->duplex = duplex;
537 static void get_supported(u32 eth_proto_cap, u32 *supported)
539 *supported |= ptys2ethtool_supported_port(eth_proto_cap);
540 *supported |= ptys2ethtool_supported_link(eth_proto_cap);
541 *supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
544 static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
545 u8 rx_pause, u32 *advertising)
547 *advertising |= ptys2ethtool_adver_link(eth_proto_cap);
548 *advertising |= tx_pause ? ADVERTISED_Pause : 0;
549 *advertising |= (tx_pause ^ rx_pause) ? ADVERTISED_Asym_Pause : 0;
552 static u8 get_connector_port(u32 eth_proto)
554 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
555 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
556 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
557 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
561 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
562 | MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
563 | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
567 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
568 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
569 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
570 | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
577 static void get_lp_advertising(u32 eth_proto_lp, u32 *lp_advertising)
579 *lp_advertising = ptys2ethtool_adver_link(eth_proto_lp);
582 static int mlx5e_get_settings(struct net_device *netdev,
583 struct ethtool_cmd *cmd)
585 struct mlx5e_priv *priv = netdev_priv(netdev);
586 struct mlx5_core_dev *mdev = priv->mdev;
587 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
594 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
597 netdev_err(netdev, "%s: query port ptys failed: %d\n",
602 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
603 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
604 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
605 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
608 cmd->advertising = 0;
610 get_supported(eth_proto_cap, &cmd->supported);
611 get_advertising(eth_proto_admin, 0, 0, &cmd->advertising);
612 get_speed_duplex(netdev, eth_proto_oper, cmd);
614 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
616 cmd->port = get_connector_port(eth_proto_oper);
617 get_lp_advertising(eth_proto_lp, &cmd->lp_advertising);
619 cmd->transceiver = XCVR_INTERNAL;
625 static u32 mlx5e_ethtool2ptys_adver_link(u32 link_modes)
627 u32 i, ptys_modes = 0;
629 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
630 if (ptys2ethtool_table[i].advertised & link_modes)
631 ptys_modes |= MLX5E_PROT_MASK(i);
637 static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
639 u32 i, speed_links = 0;
641 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
642 if (ptys2ethtool_table[i].speed == speed)
643 speed_links |= MLX5E_PROT_MASK(i);
649 static int mlx5e_set_settings(struct net_device *netdev,
650 struct ethtool_cmd *cmd)
652 struct mlx5e_priv *priv = netdev_priv(netdev);
653 struct mlx5_core_dev *mdev = priv->mdev;
656 u32 eth_proto_cap, eth_proto_admin;
657 enum mlx5_port_status ps;
660 speed = ethtool_cmd_speed(cmd);
662 link_modes = cmd->autoneg == AUTONEG_ENABLE ?
663 mlx5e_ethtool2ptys_adver_link(cmd->advertising) :
664 mlx5e_ethtool2ptys_speed_link(speed);
666 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
668 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
673 link_modes = link_modes & eth_proto_cap;
675 netdev_err(netdev, "%s: Not supported link mode(s) requested",
681 err = mlx5_query_port_proto_admin(mdev, ð_proto_admin, MLX5_PTYS_EN);
683 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
688 if (link_modes == eth_proto_admin)
691 mlx5_query_port_admin_status(mdev, &ps);
692 if (ps == MLX5_PORT_UP)
693 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
694 mlx5_set_port_proto(mdev, link_modes, MLX5_PTYS_EN);
695 if (ps == MLX5_PORT_UP)
696 mlx5_set_port_admin_status(mdev, MLX5_PORT_UP);
702 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
704 struct mlx5e_priv *priv = netdev_priv(netdev);
706 return sizeof(priv->params.toeplitz_hash_key);
709 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
711 return MLX5E_INDIR_RQT_SIZE;
714 static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
717 struct mlx5e_priv *priv = netdev_priv(netdev);
720 memcpy(indir, priv->params.indirection_rqt,
721 sizeof(priv->params.indirection_rqt));
724 memcpy(key, priv->params.toeplitz_hash_key,
725 sizeof(priv->params.toeplitz_hash_key));
728 *hfunc = priv->params.rss_hfunc;
733 static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
735 struct mlx5_core_dev *mdev = priv->mdev;
736 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
739 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
740 mlx5e_build_tir_ctx_hash(tirc, priv);
742 for (i = 0; i < MLX5E_NUM_TT; i++)
743 if (IS_HASHING_TT(i))
744 mlx5_core_modify_tir(mdev, priv->tirn[i], in, inlen);
747 static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
748 const u8 *key, const u8 hfunc)
750 struct mlx5e_priv *priv = netdev_priv(dev);
751 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
754 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
755 (hfunc != ETH_RSS_HASH_XOR) &&
756 (hfunc != ETH_RSS_HASH_TOP))
759 in = mlx5_vzalloc(inlen);
763 mutex_lock(&priv->state_lock);
766 memcpy(priv->params.indirection_rqt, indir,
767 sizeof(priv->params.indirection_rqt));
768 mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
772 memcpy(priv->params.toeplitz_hash_key, key,
773 sizeof(priv->params.toeplitz_hash_key));
775 if (hfunc != ETH_RSS_HASH_NO_CHANGE)
776 priv->params.rss_hfunc = hfunc;
778 mlx5e_modify_tirs_hash(priv, in, inlen);
780 mutex_unlock(&priv->state_lock);
787 static int mlx5e_get_rxnfc(struct net_device *netdev,
788 struct ethtool_rxnfc *info, u32 *rule_locs)
790 struct mlx5e_priv *priv = netdev_priv(netdev);
794 case ETHTOOL_GRXRINGS:
795 info->data = priv->params.num_channels;
805 static int mlx5e_get_tunable(struct net_device *dev,
806 const struct ethtool_tunable *tuna,
809 const struct mlx5e_priv *priv = netdev_priv(dev);
813 case ETHTOOL_TX_COPYBREAK:
814 *(u32 *)data = priv->params.tx_max_inline;
824 static int mlx5e_set_tunable(struct net_device *dev,
825 const struct ethtool_tunable *tuna,
828 struct mlx5e_priv *priv = netdev_priv(dev);
829 struct mlx5_core_dev *mdev = priv->mdev;
835 case ETHTOOL_TX_COPYBREAK:
837 if (val > mlx5e_get_max_inline_cap(mdev)) {
842 mutex_lock(&priv->state_lock);
844 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
846 mlx5e_close_locked(dev);
848 priv->params.tx_max_inline = val;
851 err = mlx5e_open_locked(dev);
853 mutex_unlock(&priv->state_lock);
863 static void mlx5e_get_pauseparam(struct net_device *netdev,
864 struct ethtool_pauseparam *pauseparam)
866 struct mlx5e_priv *priv = netdev_priv(netdev);
867 struct mlx5_core_dev *mdev = priv->mdev;
870 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
871 &pauseparam->tx_pause);
873 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
878 static int mlx5e_set_pauseparam(struct net_device *netdev,
879 struct ethtool_pauseparam *pauseparam)
881 struct mlx5e_priv *priv = netdev_priv(netdev);
882 struct mlx5_core_dev *mdev = priv->mdev;
885 if (pauseparam->autoneg)
888 err = mlx5_set_port_pause(mdev,
889 pauseparam->rx_pause ? 1 : 0,
890 pauseparam->tx_pause ? 1 : 0);
892 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
899 static int mlx5e_get_ts_info(struct net_device *dev,
900 struct ethtool_ts_info *info)
902 struct mlx5e_priv *priv = netdev_priv(dev);
905 ret = ethtool_op_get_ts_info(dev, info);
909 info->phc_index = priv->tstamp.ptp ?
910 ptp_clock_index(priv->tstamp.ptp) : -1;
912 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
915 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
916 SOF_TIMESTAMPING_RX_HARDWARE |
917 SOF_TIMESTAMPING_RAW_HARDWARE;
919 info->tx_types = (BIT(1) << HWTSTAMP_TX_OFF) |
920 (BIT(1) << HWTSTAMP_TX_ON);
922 info->rx_filters = (BIT(1) << HWTSTAMP_FILTER_NONE) |
923 (BIT(1) << HWTSTAMP_FILTER_ALL);
928 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
932 if (MLX5_CAP_GEN(mdev, wol_g))
935 if (MLX5_CAP_GEN(mdev, wol_s))
936 ret |= WAKE_MAGICSECURE;
938 if (MLX5_CAP_GEN(mdev, wol_a))
941 if (MLX5_CAP_GEN(mdev, wol_b))
944 if (MLX5_CAP_GEN(mdev, wol_m))
947 if (MLX5_CAP_GEN(mdev, wol_u))
950 if (MLX5_CAP_GEN(mdev, wol_p))
956 static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
960 if (mode & MLX5_WOL_MAGIC)
963 if (mode & MLX5_WOL_SECURED_MAGIC)
964 ret |= WAKE_MAGICSECURE;
966 if (mode & MLX5_WOL_ARP)
969 if (mode & MLX5_WOL_BROADCAST)
972 if (mode & MLX5_WOL_MULTICAST)
975 if (mode & MLX5_WOL_UNICAST)
978 if (mode & MLX5_WOL_PHY_ACTIVITY)
984 static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
988 if (mode & WAKE_MAGIC)
989 ret |= MLX5_WOL_MAGIC;
991 if (mode & WAKE_MAGICSECURE)
992 ret |= MLX5_WOL_SECURED_MAGIC;
997 if (mode & WAKE_BCAST)
998 ret |= MLX5_WOL_BROADCAST;
1000 if (mode & WAKE_MCAST)
1001 ret |= MLX5_WOL_MULTICAST;
1003 if (mode & WAKE_UCAST)
1004 ret |= MLX5_WOL_UNICAST;
1006 if (mode & WAKE_PHY)
1007 ret |= MLX5_WOL_PHY_ACTIVITY;
1012 static void mlx5e_get_wol(struct net_device *netdev,
1013 struct ethtool_wolinfo *wol)
1015 struct mlx5e_priv *priv = netdev_priv(netdev);
1016 struct mlx5_core_dev *mdev = priv->mdev;
1020 memset(wol, 0, sizeof(*wol));
1022 wol->supported = mlx5e_get_wol_supported(mdev);
1023 if (!wol->supported)
1026 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1030 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1033 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1035 struct mlx5e_priv *priv = netdev_priv(netdev);
1036 struct mlx5_core_dev *mdev = priv->mdev;
1037 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1043 if (wol->wolopts & ~wol_supported)
1046 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1048 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1051 const struct ethtool_ops mlx5e_ethtool_ops = {
1052 .get_drvinfo = mlx5e_get_drvinfo,
1053 .get_link = ethtool_op_get_link,
1054 .get_strings = mlx5e_get_strings,
1055 .get_sset_count = mlx5e_get_sset_count,
1056 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1057 .get_ringparam = mlx5e_get_ringparam,
1058 .set_ringparam = mlx5e_set_ringparam,
1059 .get_channels = mlx5e_get_channels,
1060 .set_channels = mlx5e_set_channels,
1061 .get_coalesce = mlx5e_get_coalesce,
1062 .set_coalesce = mlx5e_set_coalesce,
1063 .get_settings = mlx5e_get_settings,
1064 .set_settings = mlx5e_set_settings,
1065 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1066 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
1067 .get_rxfh = mlx5e_get_rxfh,
1068 .set_rxfh = mlx5e_set_rxfh,
1069 .get_rxnfc = mlx5e_get_rxnfc,
1070 .get_tunable = mlx5e_get_tunable,
1071 .set_tunable = mlx5e_set_tunable,
1072 .get_pauseparam = mlx5e_get_pauseparam,
1073 .set_pauseparam = mlx5e_set_pauseparam,
1074 .get_ts_info = mlx5e_get_ts_info,
1075 .get_wol = mlx5e_get_wol,
1076 .set_wol = mlx5e_set_wol,