drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 struct mlx5e_rq_param {
  43         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  44         struct mlx5_wq_param    wq;
  45         bool                    am_enabled;
  46 };
  47
  48 struct mlx5e_sq_param {
  49         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  50         struct mlx5_wq_param       wq;
  51         u16                        max_inline;
  52         u8                         min_inline_mode;
  53         bool                       icosq;
  54 };
  55
  56 struct mlx5e_cq_param {
  57         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  58         struct mlx5_wq_param       wq;
  59         u16                        eq_ix;
  60         u8                         cq_period_mode;
  61 };
  62
  63 struct mlx5e_channel_param {
  64         struct mlx5e_rq_param      rq;
  65         struct mlx5e_sq_param      sq;
  66         struct mlx5e_sq_param      icosq;
  67         struct mlx5e_cq_param      rx_cq;
  68         struct mlx5e_cq_param      tx_cq;
  69         struct mlx5e_cq_param      icosq_cq;
  70 };
  71
  72 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  73 {
  74         struct mlx5_core_dev *mdev = priv->mdev;
  75         u8 port_state;
  76
  77         port_state = mlx5_query_vport_state(mdev,
  78                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  79
  80         if (port_state == VPORT_STATE_UP) {
  81                 netdev_info(priv->netdev, "Link up\n");
  82                 netif_carrier_on(priv->netdev);
  83         } else {
  84                 netdev_info(priv->netdev, "Link down\n");
  85                 netif_carrier_off(priv->netdev);
  86         }
  87 }
  88
  89 static void mlx5e_update_carrier_work(struct work_struct *work)
  90 {
  91         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  92                                                update_carrier_work);
  93
  94         mutex_lock(&priv->state_lock);
  95         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  96                 mlx5e_update_carrier(priv);
  97         mutex_unlock(&priv->state_lock);
  98 }
  99
 100 static void mlx5e_tx_timeout_work(struct work_struct *work)
 101 {
 102         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 103                                                tx_timeout_work);
 104         int err;
 105
 106         rtnl_lock();
 107         mutex_lock(&priv->state_lock);
 108         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 109                 goto unlock;
 110         mlx5e_close_locked(priv->netdev);
 111         err = mlx5e_open_locked(priv->netdev);
 112         if (err)
 113                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 114                            err);
 115 unlock:
 116         mutex_unlock(&priv->state_lock);
 117         rtnl_unlock();
 118 }
 119
 120 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 121 {
 122         struct mlx5e_sw_stats *s = &priv->stats.sw;
 123         struct mlx5e_rq_stats *rq_stats;
 124         struct mlx5e_sq_stats *sq_stats;
 125         u64 tx_offload_none = 0;
 126         int i, j;
 127
 128         memset(s, 0, sizeof(*s));
 129         for (i = 0; i < priv->params.num_channels; i++) {
 130                 rq_stats = &priv->channel[i]->rq.stats;
 131
 132                 s->rx_packets   += rq_stats->packets;
 133                 s->rx_bytes     += rq_stats->bytes;
 134                 s->rx_lro_packets += rq_stats->lro_packets;
 135                 s->rx_lro_bytes += rq_stats->lro_bytes;
 136                 s->rx_csum_none += rq_stats->csum_none;
 137                 s->rx_csum_complete += rq_stats->csum_complete;
 138                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 139                 s->rx_wqe_err   += rq_stats->wqe_err;
 140                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 141                 s->rx_mpwqe_frag   += rq_stats->mpwqe_frag;
 142                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 143                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 144                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 145
 146                 for (j = 0; j < priv->params.num_tc; j++) {
 147                         sq_stats = &priv->channel[i]->sq[j].stats;
 148
 149                         s->tx_packets           += sq_stats->packets;
 150                         s->tx_bytes             += sq_stats->bytes;
 151                         s->tx_tso_packets       += sq_stats->tso_packets;
 152                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 153                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 154                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 155                         s->tx_queue_stopped     += sq_stats->stopped;
 156                         s->tx_queue_wake        += sq_stats->wake;
 157                         s->tx_queue_dropped     += sq_stats->dropped;
 158                         s->tx_xmit_more         += sq_stats->xmit_more;
 159                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 160                         tx_offload_none         += sq_stats->csum_none;
 161                 }
 162         }
 163
 164         /* Update calculated offload counters */
 165         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
 166         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 167
 168         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 169                                 priv->stats.pport.phy_counters,
 170                                 counter_set.phys_layer_cntrs.link_down_events);
 171 }
 172
 173 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 174 {
 175         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 176         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 177         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
 178         struct mlx5_core_dev *mdev = priv->mdev;
 179
 180         MLX5_SET(query_vport_counter_in, in, opcode,
 181                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 182         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 183         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 184
 185         memset(out, 0, outlen);
 186         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 187 }
 188
 189 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 190 {
 191         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 192         struct mlx5_core_dev *mdev = priv->mdev;
 193         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 194         int prio;
 195         void *out;
 196         u32 *in;
 197
 198         in = mlx5_vzalloc(sz);
 199         if (!in)
 200                 goto free_out;
 201
 202         MLX5_SET(ppcnt_reg, in, local_port, 1);
 203
 204         out = pstats->IEEE_802_3_counters;
 205         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 206         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 207
 208         out = pstats->RFC_2863_counters;
 209         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 210         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 211
 212         out = pstats->RFC_2819_counters;
 213         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 214         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 215
 216         out = pstats->phy_counters;
 217         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 218         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 219
 220         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 221         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 222                 out = pstats->per_prio_counters[prio];
 223                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 224                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 225                                      MLX5_REG_PPCNT, 0, 0);
 226         }
 227
 228 free_out:
 229         kvfree(in);
 230 }
 231
 232 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 233 {
 234         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 235
 236         if (!priv->q_counter)
 237                 return;
 238
 239         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 240                                       &qcnt->rx_out_of_buffer);
 241 }
 242
 243 void mlx5e_update_stats(struct mlx5e_priv *priv)
 244 {
 245         mlx5e_update_q_counter(priv);
 246         mlx5e_update_vport_counters(priv);
 247         mlx5e_update_pport_counters(priv);
 248         mlx5e_update_sw_counters(priv);
 249 }
 250
 251 void mlx5e_update_stats_work(struct work_struct *work)
 252 {
 253         struct delayed_work *dwork = to_delayed_work(work);
 254         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 255                                                update_stats_work);
 256         mutex_lock(&priv->state_lock);
 257         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 258                 priv->profile->update_stats(priv);
 259                 queue_delayed_work(priv->wq, dwork,
 260                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 261         }
 262         mutex_unlock(&priv->state_lock);
 263 }
 264
 265 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 266                               enum mlx5_dev_event event, unsigned long param)
 267 {
 268         struct mlx5e_priv *priv = vpriv;
 269
 270         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 271                 return;
 272
 273         switch (event) {
 274         case MLX5_DEV_EVENT_PORT_UP:
 275         case MLX5_DEV_EVENT_PORT_DOWN:
 276                 queue_work(priv->wq, &priv->update_carrier_work);
 277                 break;
 278
 279         default:
 280                 break;
 281         }
 282 }
 283
 284 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 285 {
 286         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 287 }
 288
 289 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 290 {
 291         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 292         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 293 }
 294
 295 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 296 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 297
 298 static int mlx5e_create_rq(struct mlx5e_channel *c,
 299                            struct mlx5e_rq_param *param,
 300                            struct mlx5e_rq *rq)
 301 {
 302         struct mlx5e_priv *priv = c->priv;
 303         struct mlx5_core_dev *mdev = priv->mdev;
 304         void *rqc = param->rqc;
 305         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 306         u32 byte_count;
 307         int wq_sz;
 308         int err;
 309         int i;
 310
 311         param->wq.db_numa_node = cpu_to_node(c->cpu);
 312
 313         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 314                                 &rq->wq_ctrl);
 315         if (err)
 316                 return err;
 317
 318         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 319
 320         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 321
 322         switch (priv->params.rq_wq_type) {
 323         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 324                 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
 325                                             GFP_KERNEL, cpu_to_node(c->cpu));
 326                 if (!rq->wqe_info) {
 327                         err = -ENOMEM;
 328                         goto err_rq_wq_destroy;
 329                 }
 330                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 331                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 332                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 333
 334                 rq->mpwqe_mtt_offset = c->ix *
 335                         MLX5E_REQUIRED_MTTS(1, BIT(priv->params.log_rq_size));
 336
 337                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 338                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 339                 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 340                 byte_count = rq->wqe_sz;
 341                 break;
 342         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 343                 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 344                                        cpu_to_node(c->cpu));
 345                 if (!rq->skb) {
 346                         err = -ENOMEM;
 347                         goto err_rq_wq_destroy;
 348                 }
 349                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 350                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 351                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 352
 353                 rq->wqe_sz = (priv->params.lro_en) ?
 354                                 priv->params.lro_wqe_sz :
 355                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 356                 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
 357                 byte_count = rq->wqe_sz;
 358                 byte_count |= MLX5_HW_START_PADDING;
 359         }
 360
 361         for (i = 0; i < wq_sz; i++) {
 362                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 363
 364                 wqe->data.byte_count = cpu_to_be32(byte_count);
 365         }
 366
 367         INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
 368         rq->am.mode = priv->params.rx_cq_period_mode;
 369
 370         rq->wq_type = priv->params.rq_wq_type;
 371         rq->pdev    = c->pdev;
 372         rq->netdev  = c->netdev;
 373         rq->tstamp  = &priv->tstamp;
 374         rq->channel = c;
 375         rq->ix      = c->ix;
 376         rq->priv    = c->priv;
 377         rq->mkey_be = c->mkey_be;
 378         rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 379
 380         return 0;
 381
 382 err_rq_wq_destroy:
 383         mlx5_wq_destroy(&rq->wq_ctrl);
 384
 385         return err;
 386 }
 387
 388 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 389 {
 390         switch (rq->wq_type) {
 391         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 392                 kfree(rq->wqe_info);
 393                 break;
 394         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 395                 kfree(rq->skb);
 396         }
 397
 398         mlx5_wq_destroy(&rq->wq_ctrl);
 399 }
 400
 401 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 402 {
 403         struct mlx5e_priv *priv = rq->priv;
 404         struct mlx5_core_dev *mdev = priv->mdev;
 405
 406         void *in;
 407         void *rqc;
 408         void *wq;
 409         int inlen;
 410         int err;
 411
 412         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 413                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 414         in = mlx5_vzalloc(inlen);
 415         if (!in)
 416                 return -ENOMEM;
 417
 418         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 419         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 420
 421         memcpy(rqc, param->rqc, sizeof(param->rqc));
 422
 423         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 424         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 425         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 426         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 427                                                 MLX5_ADAPTER_PAGE_SHIFT);
 428         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 429
 430         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 431                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 432
 433         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 434
 435         kvfree(in);
 436
 437         return err;
 438 }
 439
 440 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 441                                  int next_state)
 442 {
 443         struct mlx5e_channel *c = rq->channel;
 444         struct mlx5e_priv *priv = c->priv;
 445         struct mlx5_core_dev *mdev = priv->mdev;
 446
 447         void *in;
 448         void *rqc;
 449         int inlen;
 450         int err;
 451
 452         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 453         in = mlx5_vzalloc(inlen);
 454         if (!in)
 455                 return -ENOMEM;
 456
 457         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 458
 459         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 460         MLX5_SET(rqc, rqc, state, next_state);
 461
 462         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 463
 464         kvfree(in);
 465
 466         return err;
 467 }
 468
 469 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 470 {
 471         struct mlx5e_channel *c = rq->channel;
 472         struct mlx5e_priv *priv = c->priv;
 473         struct mlx5_core_dev *mdev = priv->mdev;
 474
 475         void *in;
 476         void *rqc;
 477         int inlen;
 478         int err;
 479
 480         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 481         in = mlx5_vzalloc(inlen);
 482         if (!in)
 483                 return -ENOMEM;
 484
 485         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 486
 487         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 488         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 489                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 490         MLX5_SET(rqc, rqc, vsd, vsd);
 491         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 492
 493         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 494
 495         kvfree(in);
 496
 497         return err;
 498 }
 499
 500 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 501 {
 502         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 503 }
 504
 505 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 506 {
 507         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 508         struct mlx5e_channel *c = rq->channel;
 509         struct mlx5e_priv *priv = c->priv;
 510         struct mlx5_wq_ll *wq = &rq->wq;
 511
 512         while (time_before(jiffies, exp_time)) {
 513                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 514                         return 0;
 515
 516                 msleep(20);
 517         }
 518
 519         return -ETIMEDOUT;
 520 }
 521
 522 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 523 {
 524         struct mlx5_wq_ll *wq = &rq->wq;
 525         struct mlx5e_rx_wqe *wqe;
 526         __be16 wqe_ix_be;
 527         u16 wqe_ix;
 528
 529         /* UMR WQE (if in progress) is always at wq->head */
 530         if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
 531                 mlx5e_free_rx_fragmented_mpwqe(rq, &rq->wqe_info[wq->head]);
 532
 533         while (!mlx5_wq_ll_is_empty(wq)) {
 534                 wqe_ix_be = *wq->tail_next;
 535                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 536                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 537                 rq->dealloc_wqe(rq, wqe_ix);
 538                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 539                                &wqe->next.next_wqe_index);
 540         }
 541 }
 542
 543 static int mlx5e_open_rq(struct mlx5e_channel *c,
 544                          struct mlx5e_rq_param *param,
 545                          struct mlx5e_rq *rq)
 546 {
 547         struct mlx5e_sq *sq = &c->icosq;
 548         u16 pi = sq->pc & sq->wq.sz_m1;
 549         int err;
 550
 551         err = mlx5e_create_rq(c, param, rq);
 552         if (err)
 553                 return err;
 554
 555         err = mlx5e_enable_rq(rq, param);
 556         if (err)
 557                 goto err_destroy_rq;
 558
 559         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 560         if (err)
 561                 goto err_disable_rq;
 562
 563         if (param->am_enabled)
 564                 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 565
 566         sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
 567         sq->ico_wqe_info[pi].num_wqebbs = 1;
 568         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 569
 570         return 0;
 571
 572 err_disable_rq:
 573         mlx5e_disable_rq(rq);
 574 err_destroy_rq:
 575         mlx5e_destroy_rq(rq);
 576
 577         return err;
 578 }
 579
 580 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 581 {
 582         set_bit(MLX5E_RQ_STATE_FLUSH, &rq->state);
 583         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 584         cancel_work_sync(&rq->am.work);
 585
 586         mlx5e_disable_rq(rq);
 587         mlx5e_free_rx_descs(rq);
 588         mlx5e_destroy_rq(rq);
 589 }
 590
 591 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 592 {
 593         kfree(sq->wqe_info);
 594         kfree(sq->dma_fifo);
 595         kfree(sq->skb);
 596 }
 597
 598 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 599 {
 600         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 601         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 602
 603         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 604         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 605                                     numa);
 606         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 607                                     numa);
 608
 609         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 610                 mlx5e_free_sq_db(sq);
 611                 return -ENOMEM;
 612         }
 613
 614         sq->dma_fifo_mask = df_sz - 1;
 615
 616         return 0;
 617 }
 618
 619 static int mlx5e_create_sq(struct mlx5e_channel *c,
 620                            int tc,
 621                            struct mlx5e_sq_param *param,
 622                            struct mlx5e_sq *sq)
 623 {
 624         struct mlx5e_priv *priv = c->priv;
 625         struct mlx5_core_dev *mdev = priv->mdev;
 626
 627         void *sqc = param->sqc;
 628         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 629         int err;
 630
 631         err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
 632         if (err)
 633                 return err;
 634
 635         param->wq.db_numa_node = cpu_to_node(c->cpu);
 636
 637         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 638                                  &sq->wq_ctrl);
 639         if (err)
 640                 goto err_unmap_free_uar;
 641
 642         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 643         if (sq->uar.bf_map) {
 644                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 645                 sq->uar_map = sq->uar.bf_map;
 646         } else {
 647                 sq->uar_map = sq->uar.map;
 648         }
 649         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 650         sq->max_inline  = param->max_inline;
 651         sq->min_inline_mode =
 652                 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
 653                 param->min_inline_mode : 0;
 654
 655         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 656         if (err)
 657                 goto err_sq_wq_destroy;
 658
 659         if (param->icosq) {
 660                 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 661
 662                 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
 663                                                 wq_sz,
 664                                                 GFP_KERNEL,
 665                                                 cpu_to_node(c->cpu));
 666                 if (!sq->ico_wqe_info) {
 667                         err = -ENOMEM;
 668                         goto err_free_sq_db;
 669                 }
 670         } else {
 671                 int txq_ix;
 672
 673                 txq_ix = c->ix + tc * priv->params.num_channels;
 674                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 675                 priv->txq_to_sq_map[txq_ix] = sq;
 676         }
 677
 678         sq->pdev      = c->pdev;
 679         sq->tstamp    = &priv->tstamp;
 680         sq->mkey_be   = c->mkey_be;
 681         sq->channel   = c;
 682         sq->tc        = tc;
 683         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 684         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 685
 686         return 0;
 687
 688 err_free_sq_db:
 689         mlx5e_free_sq_db(sq);
 690
 691 err_sq_wq_destroy:
 692         mlx5_wq_destroy(&sq->wq_ctrl);
 693
 694 err_unmap_free_uar:
 695         mlx5_unmap_free_uar(mdev, &sq->uar);
 696
 697         return err;
 698 }
 699
 700 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 701 {
 702         struct mlx5e_channel *c = sq->channel;
 703         struct mlx5e_priv *priv = c->priv;
 704
 705         kfree(sq->ico_wqe_info);
 706         mlx5e_free_sq_db(sq);
 707         mlx5_wq_destroy(&sq->wq_ctrl);
 708         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 709 }
 710
 711 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 712 {
 713         struct mlx5e_channel *c = sq->channel;
 714         struct mlx5e_priv *priv = c->priv;
 715         struct mlx5_core_dev *mdev = priv->mdev;
 716
 717         void *in;
 718         void *sqc;
 719         void *wq;
 720         int inlen;
 721         int err;
 722
 723         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 724                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 725         in = mlx5_vzalloc(inlen);
 726         if (!in)
 727                 return -ENOMEM;
 728
 729         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 730         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 731
 732         memcpy(sqc, param->sqc, sizeof(param->sqc));
 733
 734         MLX5_SET(sqc,  sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
 735         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
 736         MLX5_SET(sqc,  sqc, min_wqe_inline_mode, sq->min_inline_mode);
 737         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 738         MLX5_SET(sqc,  sqc, tis_lst_sz,         param->icosq ? 0 : 1);
 739         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 740
 741         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 742         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 743         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 744                                           MLX5_ADAPTER_PAGE_SHIFT);
 745         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 746
 747         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 748                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 749
 750         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 751
 752         kvfree(in);
 753
 754         return err;
 755 }
 756
 757 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
 758                            int next_state, bool update_rl, int rl_index)
 759 {
 760         struct mlx5e_channel *c = sq->channel;
 761         struct mlx5e_priv *priv = c->priv;
 762         struct mlx5_core_dev *mdev = priv->mdev;
 763
 764         void *in;
 765         void *sqc;
 766         int inlen;
 767         int err;
 768
 769         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 770         in = mlx5_vzalloc(inlen);
 771         if (!in)
 772                 return -ENOMEM;
 773
 774         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 775
 776         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 777         MLX5_SET(sqc, sqc, state, next_state);
 778         if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
 779                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
 780                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, rl_index);
 781         }
 782
 783         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 784
 785         kvfree(in);
 786
 787         return err;
 788 }
 789
 790 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 791 {
 792         struct mlx5e_channel *c = sq->channel;
 793         struct mlx5e_priv *priv = c->priv;
 794         struct mlx5_core_dev *mdev = priv->mdev;
 795
 796         mlx5_core_destroy_sq(mdev, sq->sqn);
 797         if (sq->rate_limit)
 798                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
 799 }
 800
 801 static int mlx5e_open_sq(struct mlx5e_channel *c,
 802                          int tc,
 803                          struct mlx5e_sq_param *param,
 804                          struct mlx5e_sq *sq)
 805 {
 806         int err;
 807
 808         err = mlx5e_create_sq(c, tc, param, sq);
 809         if (err)
 810                 return err;
 811
 812         err = mlx5e_enable_sq(sq, param);
 813         if (err)
 814                 goto err_destroy_sq;
 815
 816         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
 817                               false, 0);
 818         if (err)
 819                 goto err_disable_sq;
 820
 821         if (sq->txq) {
 822                 netdev_tx_reset_queue(sq->txq);
 823                 netif_tx_start_queue(sq->txq);
 824         }
 825
 826         return 0;
 827
 828 err_disable_sq:
 829         mlx5e_disable_sq(sq);
 830 err_destroy_sq:
 831         mlx5e_destroy_sq(sq);
 832
 833         return err;
 834 }
 835
 836 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 837 {
 838         __netif_tx_lock_bh(txq);
 839         netif_tx_stop_queue(txq);
 840         __netif_tx_unlock_bh(txq);
 841 }
 842
 843 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 844 {
 845         set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
 846         /* prevent netif_tx_wake_queue */
 847         napi_synchronize(&sq->channel->napi);
 848
 849         if (sq->txq) {
 850                 netif_tx_disable_queue(sq->txq);
 851
 852                 /* last doorbell out, godspeed .. */
 853                 if (mlx5e_sq_has_room_for(sq, 1))
 854                         mlx5e_send_nop(sq, true);
 855         }
 856
 857         mlx5e_disable_sq(sq);
 858         mlx5e_free_tx_descs(sq);
 859         mlx5e_destroy_sq(sq);
 860 }
 861
 862 static int mlx5e_create_cq(struct mlx5e_channel *c,
 863                            struct mlx5e_cq_param *param,
 864                            struct mlx5e_cq *cq)
 865 {
 866         struct mlx5e_priv *priv = c->priv;
 867         struct mlx5_core_dev *mdev = priv->mdev;
 868         struct mlx5_core_cq *mcq = &cq->mcq;
 869         int eqn_not_used;
 870         unsigned int irqn;
 871         int err;
 872         u32 i;
 873
 874         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 875         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 876         param->eq_ix   = c->ix;
 877
 878         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 879                                &cq->wq_ctrl);
 880         if (err)
 881                 return err;
 882
 883         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 884
 885         cq->napi        = &c->napi;
 886
 887         mcq->cqe_sz     = 64;
 888         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 889         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 890         *mcq->set_ci_db = 0;
 891         *mcq->arm_db    = 0;
 892         mcq->vector     = param->eq_ix;
 893         mcq->comp       = mlx5e_completion_event;
 894         mcq->event      = mlx5e_cq_error_event;
 895         mcq->irqn       = irqn;
 896         mcq->uar        = &mdev->mlx5e_res.cq_uar;
 897
 898         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 899                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 900
 901                 cqe->op_own = 0xf1;
 902         }
 903
 904         cq->channel = c;
 905         cq->priv = priv;
 906
 907         return 0;
 908 }
 909
 910 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 911 {
 912         mlx5_wq_destroy(&cq->wq_ctrl);
 913 }
 914
 915 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 916 {
 917         struct mlx5e_priv *priv = cq->priv;
 918         struct mlx5_core_dev *mdev = priv->mdev;
 919         struct mlx5_core_cq *mcq = &cq->mcq;
 920
 921         void *in;
 922         void *cqc;
 923         int inlen;
 924         unsigned int irqn_not_used;
 925         int eqn;
 926         int err;
 927
 928         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 929                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 930         in = mlx5_vzalloc(inlen);
 931         if (!in)
 932                 return -ENOMEM;
 933
 934         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 935
 936         memcpy(cqc, param->cqc, sizeof(param->cqc));
 937
 938         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 939                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 940
 941         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 942
 943         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
 944         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 945         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 946         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 947                                             MLX5_ADAPTER_PAGE_SHIFT);
 948         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 949
 950         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 951
 952         kvfree(in);
 953
 954         if (err)
 955                 return err;
 956
 957         mlx5e_cq_arm(cq);
 958
 959         return 0;
 960 }
 961
 962 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 963 {
 964         struct mlx5e_priv *priv = cq->priv;
 965         struct mlx5_core_dev *mdev = priv->mdev;
 966
 967         mlx5_core_destroy_cq(mdev, &cq->mcq);
 968 }
 969
 970 static int mlx5e_open_cq(struct mlx5e_channel *c,
 971                          struct mlx5e_cq_param *param,
 972                          struct mlx5e_cq *cq,
 973                          struct mlx5e_cq_moder moderation)
 974 {
 975         int err;
 976         struct mlx5e_priv *priv = c->priv;
 977         struct mlx5_core_dev *mdev = priv->mdev;
 978
 979         err = mlx5e_create_cq(c, param, cq);
 980         if (err)
 981                 return err;
 982
 983         err = mlx5e_enable_cq(cq, param);
 984         if (err)
 985                 goto err_destroy_cq;
 986
 987         if (MLX5_CAP_GEN(mdev, cq_moderation))
 988                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 989                                                moderation.usec,
 990                                                moderation.pkts);
 991         return 0;
 992
 993 err_destroy_cq:
 994         mlx5e_destroy_cq(cq);
 995
 996         return err;
 997 }
 998
 999 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1000 {
1001         mlx5e_disable_cq(cq);
1002         mlx5e_destroy_cq(cq);
1003 }
1004
1005 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1006 {
1007         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1008 }
1009
1010 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1011                              struct mlx5e_channel_param *cparam)
1012 {
1013         struct mlx5e_priv *priv = c->priv;
1014         int err;
1015         int tc;
1016
1017         for (tc = 0; tc < c->num_tc; tc++) {
1018                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1019                                     priv->params.tx_cq_moderation);
1020                 if (err)
1021                         goto err_close_tx_cqs;
1022         }
1023
1024         return 0;
1025
1026 err_close_tx_cqs:
1027         for (tc--; tc >= 0; tc--)
1028                 mlx5e_close_cq(&c->sq[tc].cq);
1029
1030         return err;
1031 }
1032
1033 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1034 {
1035         int tc;
1036
1037         for (tc = 0; tc < c->num_tc; tc++)
1038                 mlx5e_close_cq(&c->sq[tc].cq);
1039 }
1040
1041 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1042                           struct mlx5e_channel_param *cparam)
1043 {
1044         int err;
1045         int tc;
1046
1047         for (tc = 0; tc < c->num_tc; tc++) {
1048                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1049                 if (err)
1050                         goto err_close_sqs;
1051         }
1052
1053         return 0;
1054
1055 err_close_sqs:
1056         for (tc--; tc >= 0; tc--)
1057                 mlx5e_close_sq(&c->sq[tc]);
1058
1059         return err;
1060 }
1061
1062 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1063 {
1064         int tc;
1065
1066         for (tc = 0; tc < c->num_tc; tc++)
1067                 mlx5e_close_sq(&c->sq[tc]);
1068 }
1069
1070 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1071 {
1072         int i;
1073
1074         for (i = 0; i < priv->profile->max_tc; i++)
1075                 priv->channeltc_to_txq_map[ix][i] =
1076                         ix + i * priv->params.num_channels;
1077 }
1078
1079 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1080                                 struct mlx5e_sq *sq, u32 rate)
1081 {
1082         struct mlx5e_priv *priv = netdev_priv(dev);
1083         struct mlx5_core_dev *mdev = priv->mdev;
1084         u16 rl_index = 0;
1085         int err;
1086
1087         if (rate == sq->rate_limit)
1088                 /* nothing to do */
1089                 return 0;
1090
1091         if (sq->rate_limit)
1092                 /* remove current rl index to free space to next ones */
1093                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1094
1095         sq->rate_limit = 0;
1096
1097         if (rate) {
1098                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1099                 if (err) {
1100                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1101                                    rate, err);
1102                         return err;
1103                 }
1104         }
1105
1106         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1107                               MLX5_SQC_STATE_RDY, true, rl_index);
1108         if (err) {
1109                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1110                            rate, err);
1111                 /* remove the rate from the table */
1112                 if (rate)
1113                         mlx5_rl_remove_rate(mdev, rate);
1114                 return err;
1115         }
1116
1117         sq->rate_limit = rate;
1118         return 0;
1119 }
1120
1121 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1122 {
1123         struct mlx5e_priv *priv = netdev_priv(dev);
1124         struct mlx5_core_dev *mdev = priv->mdev;
1125         struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1126         int err = 0;
1127
1128         if (!mlx5_rl_is_supported(mdev)) {
1129                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1130                 return -EINVAL;
1131         }
1132
1133         /* rate is given in Mb/sec, HW config is in Kb/sec */
1134         rate = rate << 10;
1135
1136         /* Check whether rate in valid range, 0 is always valid */
1137         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1138                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1139                 return -ERANGE;
1140         }
1141
1142         mutex_lock(&priv->state_lock);
1143         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1144                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1145         if (!err)
1146                 priv->tx_rates[index] = rate;
1147         mutex_unlock(&priv->state_lock);
1148
1149         return err;
1150 }
1151
1152 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1153                               struct mlx5e_channel_param *cparam,
1154                               struct mlx5e_channel **cp)
1155 {
1156         struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1157         struct net_device *netdev = priv->netdev;
1158         struct mlx5e_cq_moder rx_cq_profile;
1159         int cpu = mlx5e_get_cpu(priv, ix);
1160         struct mlx5e_channel *c;
1161         struct mlx5e_sq *sq;
1162         int err;
1163         int i;
1164
1165         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1166         if (!c)
1167                 return -ENOMEM;
1168
1169         c->priv     = priv;
1170         c->ix       = ix;
1171         c->cpu      = cpu;
1172         c->pdev     = &priv->mdev->pdev->dev;
1173         c->netdev   = priv->netdev;
1174         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1175         c->num_tc   = priv->params.num_tc;
1176
1177         if (priv->params.rx_am_enabled)
1178                 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1179         else
1180                 rx_cq_profile = priv->params.rx_cq_moderation;
1181
1182         mlx5e_build_channeltc_to_txq_map(priv, ix);
1183
1184         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1185
1186         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1187         if (err)
1188                 goto err_napi_del;
1189
1190         err = mlx5e_open_tx_cqs(c, cparam);
1191         if (err)
1192                 goto err_close_icosq_cq;
1193
1194         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1195                             rx_cq_profile);
1196         if (err)
1197                 goto err_close_tx_cqs;
1198
1199         napi_enable(&c->napi);
1200
1201         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1202         if (err)
1203                 goto err_disable_napi;
1204
1205         err = mlx5e_open_sqs(c, cparam);
1206         if (err)
1207                 goto err_close_icosq;
1208
1209         for (i = 0; i < priv->params.num_tc; i++) {
1210                 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1211
1212                 if (priv->tx_rates[txq_ix]) {
1213                         sq = priv->txq_to_sq_map[txq_ix];
1214                         mlx5e_set_sq_maxrate(priv->netdev, sq,
1215                                              priv->tx_rates[txq_ix]);
1216                 }
1217         }
1218
1219         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1220         if (err)
1221                 goto err_close_sqs;
1222
1223         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1224         *cp = c;
1225
1226         return 0;
1227
1228 err_close_sqs:
1229         mlx5e_close_sqs(c);
1230
1231 err_close_icosq:
1232         mlx5e_close_sq(&c->icosq);
1233
1234 err_disable_napi:
1235         napi_disable(&c->napi);
1236         mlx5e_close_cq(&c->rq.cq);
1237
1238 err_close_tx_cqs:
1239         mlx5e_close_tx_cqs(c);
1240
1241 err_close_icosq_cq:
1242         mlx5e_close_cq(&c->icosq.cq);
1243
1244 err_napi_del:
1245         netif_napi_del(&c->napi);
1246         napi_hash_del(&c->napi);
1247         kfree(c);
1248
1249         return err;
1250 }
1251
1252 static void mlx5e_close_channel(struct mlx5e_channel *c)
1253 {
1254         mlx5e_close_rq(&c->rq);
1255         mlx5e_close_sqs(c);
1256         mlx5e_close_sq(&c->icosq);
1257         napi_disable(&c->napi);
1258         mlx5e_close_cq(&c->rq.cq);
1259         mlx5e_close_tx_cqs(c);
1260         mlx5e_close_cq(&c->icosq.cq);
1261         netif_napi_del(&c->napi);
1262
1263         napi_hash_del(&c->napi);
1264         synchronize_rcu();
1265
1266         kfree(c);
1267 }
1268
1269 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1270                                  struct mlx5e_rq_param *param)
1271 {
1272         void *rqc = param->rqc;
1273         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1274
1275         switch (priv->params.rq_wq_type) {
1276         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1277                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1278                          priv->params.mpwqe_log_num_strides - 9);
1279                 MLX5_SET(wq, wq, log_wqe_stride_size,
1280                          priv->params.mpwqe_log_stride_sz - 6);
1281                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1282                 break;
1283         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1284                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1285         }
1286
1287         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1288         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1289         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1290         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1291         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1292
1293         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1294         param->wq.linear = 1;
1295
1296         param->am_enabled = priv->params.rx_am_enabled;
1297 }
1298
1299 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1300 {
1301         void *rqc = param->rqc;
1302         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1303
1304         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1305         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1306 }
1307
1308 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1309                                         struct mlx5e_sq_param *param)
1310 {
1311         void *sqc = param->sqc;
1312         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1313
1314         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1315         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1316
1317         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1318 }
1319
1320 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1321                                  struct mlx5e_sq_param *param)
1322 {
1323         void *sqc = param->sqc;
1324         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1325
1326         mlx5e_build_sq_param_common(priv, param);
1327         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1328
1329         param->max_inline = priv->params.tx_max_inline;
1330         param->min_inline_mode = priv->params.tx_min_inline_mode;
1331 }
1332
1333 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1334                                         struct mlx5e_cq_param *param)
1335 {
1336         void *cqc = param->cqc;
1337
1338         MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
1339 }
1340
1341 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1342                                     struct mlx5e_cq_param *param)
1343 {
1344         void *cqc = param->cqc;
1345         u8 log_cq_size;
1346
1347         switch (priv->params.rq_wq_type) {
1348         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1349                 log_cq_size = priv->params.log_rq_size +
1350                         priv->params.mpwqe_log_num_strides;
1351                 break;
1352         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1353                 log_cq_size = priv->params.log_rq_size;
1354         }
1355
1356         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1357         if (priv->params.rx_cqe_compress) {
1358                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1359                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1360         }
1361
1362         mlx5e_build_common_cq_param(priv, param);
1363
1364         param->cq_period_mode = priv->params.rx_cq_period_mode;
1365 }
1366
1367 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1368                                     struct mlx5e_cq_param *param)
1369 {
1370         void *cqc = param->cqc;
1371
1372         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1373
1374         mlx5e_build_common_cq_param(priv, param);
1375
1376         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1377 }
1378
1379 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1380                                      struct mlx5e_cq_param *param,
1381                                      u8 log_wq_size)
1382 {
1383         void *cqc = param->cqc;
1384
1385         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1386
1387         mlx5e_build_common_cq_param(priv, param);
1388
1389         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1390 }
1391
1392 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1393                                     struct mlx5e_sq_param *param,
1394                                     u8 log_wq_size)
1395 {
1396         void *sqc = param->sqc;
1397         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1398
1399         mlx5e_build_sq_param_common(priv, param);
1400
1401         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1402         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1403
1404         param->icosq = true;
1405 }
1406
1407 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1408 {
1409         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1410
1411         mlx5e_build_rq_param(priv, &cparam->rq);
1412         mlx5e_build_sq_param(priv, &cparam->sq);
1413         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1414         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1415         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1416         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1417 }
1418
1419 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1420 {
1421         struct mlx5e_channel_param *cparam;
1422         int nch = priv->params.num_channels;
1423         int err = -ENOMEM;
1424         int i;
1425         int j;
1426
1427         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1428                                 GFP_KERNEL);
1429
1430         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1431                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1432
1433         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1434
1435         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1436                 goto err_free_txq_to_sq_map;
1437
1438         mlx5e_build_channel_param(priv, cparam);
1439
1440         for (i = 0; i < nch; i++) {
1441                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1442                 if (err)
1443                         goto err_close_channels;
1444         }
1445
1446         for (j = 0; j < nch; j++) {
1447                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1448                 if (err)
1449                         goto err_close_channels;
1450         }
1451
1452         /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1453          * polling for inactive tx queues.
1454          */
1455         netif_tx_start_all_queues(priv->netdev);
1456
1457         kfree(cparam);
1458         return 0;
1459
1460 err_close_channels:
1461         for (i--; i >= 0; i--)
1462                 mlx5e_close_channel(priv->channel[i]);
1463
1464 err_free_txq_to_sq_map:
1465         kfree(priv->txq_to_sq_map);
1466         kfree(priv->channel);
1467         kfree(cparam);
1468
1469         return err;
1470 }
1471
1472 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1473 {
1474         int i;
1475
1476         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1477          * polling for inactive tx queues.
1478          */
1479         netif_tx_stop_all_queues(priv->netdev);
1480         netif_tx_disable(priv->netdev);
1481
1482         for (i = 0; i < priv->params.num_channels; i++)
1483                 mlx5e_close_channel(priv->channel[i]);
1484
1485         kfree(priv->txq_to_sq_map);
1486         kfree(priv->channel);
1487 }
1488
1489 static int mlx5e_rx_hash_fn(int hfunc)
1490 {
1491         return (hfunc == ETH_RSS_HASH_TOP) ?
1492                MLX5_RX_HASH_FN_TOEPLITZ :
1493                MLX5_RX_HASH_FN_INVERTED_XOR8;
1494 }
1495
1496 static int mlx5e_bits_invert(unsigned long a, int size)
1497 {
1498         int inv = 0;
1499         int i;
1500
1501         for (i = 0; i < size; i++)
1502                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1503
1504         return inv;
1505 }
1506
1507 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1508 {
1509         int i;
1510
1511         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1512                 int ix = i;
1513                 u32 rqn;
1514
1515                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1516                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1517
1518                 ix = priv->params.indirection_rqt[ix];
1519                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1520                                 priv->channel[ix]->rq.rqn :
1521                                 priv->drop_rq.rqn;
1522                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1523         }
1524 }
1525
1526 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1527                                       int ix)
1528 {
1529         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1530                         priv->channel[ix]->rq.rqn :
1531                         priv->drop_rq.rqn;
1532
1533         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1534 }
1535
1536 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1537                             int ix, struct mlx5e_rqt *rqt)
1538 {
1539         struct mlx5_core_dev *mdev = priv->mdev;
1540         void *rqtc;
1541         int inlen;
1542         int err;
1543         u32 *in;
1544
1545         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1546         in = mlx5_vzalloc(inlen);
1547         if (!in)
1548                 return -ENOMEM;
1549
1550         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1551
1552         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1553         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1554
1555         if (sz > 1) /* RSS */
1556                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1557         else
1558                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1559
1560         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1561         if (!err)
1562                 rqt->enabled = true;
1563
1564         kvfree(in);
1565         return err;
1566 }
1567
1568 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1569 {
1570         rqt->enabled = false;
1571         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1572 }
1573
1574 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1575 {
1576         struct mlx5e_rqt *rqt = &priv->indir_rqt;
1577
1578         return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1579 }
1580
1581 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1582 {
1583         struct mlx5e_rqt *rqt;
1584         int err;
1585         int ix;
1586
1587         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1588                 rqt = &priv->direct_tir[ix].rqt;
1589                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1590                 if (err)
1591                         goto err_destroy_rqts;
1592         }
1593
1594         return 0;
1595
1596 err_destroy_rqts:
1597         for (ix--; ix >= 0; ix--)
1598                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1599
1600         return err;
1601 }
1602
1603 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1604 {
1605         struct mlx5_core_dev *mdev = priv->mdev;
1606         void *rqtc;
1607         int inlen;
1608         u32 *in;
1609         int err;
1610
1611         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1612         in = mlx5_vzalloc(inlen);
1613         if (!in)
1614                 return -ENOMEM;
1615
1616         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1617
1618         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1619         if (sz > 1) /* RSS */
1620                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1621         else
1622                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1623
1624         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1625
1626         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1627
1628         kvfree(in);
1629
1630         return err;
1631 }
1632
1633 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1634 {
1635         u32 rqtn;
1636         int ix;
1637
1638         if (priv->indir_rqt.enabled) {
1639                 rqtn = priv->indir_rqt.rqtn;
1640                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1641         }
1642
1643         for (ix = 0; ix < priv->params.num_channels; ix++) {
1644                 if (!priv->direct_tir[ix].rqt.enabled)
1645                         continue;
1646                 rqtn = priv->direct_tir[ix].rqt.rqtn;
1647                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1648         }
1649 }
1650
1651 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1652 {
1653         if (!priv->params.lro_en)
1654                 return;
1655
1656 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1657
1658         MLX5_SET(tirc, tirc, lro_enable_mask,
1659                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1660                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1661         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1662                  (priv->params.lro_wqe_sz -
1663                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1664         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1665                  MLX5_CAP_ETH(priv->mdev,
1666                               lro_timer_supported_periods[2]));
1667 }
1668
1669 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1670 {
1671         MLX5_SET(tirc, tirc, rx_hash_fn,
1672                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1673         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1674                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1675                                              rx_hash_toeplitz_key);
1676                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1677                                                rx_hash_toeplitz_key);
1678
1679                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1680                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1681         }
1682 }
1683
1684 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1685 {
1686         struct mlx5_core_dev *mdev = priv->mdev;
1687
1688         void *in;
1689         void *tirc;
1690         int inlen;
1691         int err;
1692         int tt;
1693         int ix;
1694
1695         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1696         in = mlx5_vzalloc(inlen);
1697         if (!in)
1698                 return -ENOMEM;
1699
1700         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1701         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1702
1703         mlx5e_build_tir_ctx_lro(tirc, priv);
1704
1705         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1706                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1707                                            inlen);
1708                 if (err)
1709                         goto free_in;
1710         }
1711
1712         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1713                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1714                                            in, inlen);
1715                 if (err)
1716                         goto free_in;
1717         }
1718
1719 free_in:
1720         kvfree(in);
1721
1722         return err;
1723 }
1724
1725 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1726 {
1727         struct mlx5_core_dev *mdev = priv->mdev;
1728         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1729         int err;
1730
1731         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1732         if (err)
1733                 return err;
1734
1735         /* Update vport context MTU */
1736         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1737         return 0;
1738 }
1739
1740 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1741 {
1742         struct mlx5_core_dev *mdev = priv->mdev;
1743         u16 hw_mtu = 0;
1744         int err;
1745
1746         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1747         if (err || !hw_mtu) /* fallback to port oper mtu */
1748                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1749
1750         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1751 }
1752
1753 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1754 {
1755         struct mlx5e_priv *priv = netdev_priv(netdev);
1756         u16 mtu;
1757         int err;
1758
1759         err = mlx5e_set_mtu(priv, netdev->mtu);
1760         if (err)
1761                 return err;
1762
1763         mlx5e_query_mtu(priv, &mtu);
1764         if (mtu != netdev->mtu)
1765                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1766                             __func__, mtu, netdev->mtu);
1767
1768         netdev->mtu = mtu;
1769         return 0;
1770 }
1771
1772 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1773 {
1774         struct mlx5e_priv *priv = netdev_priv(netdev);
1775         int nch = priv->params.num_channels;
1776         int ntc = priv->params.num_tc;
1777         int tc;
1778
1779         netdev_reset_tc(netdev);
1780
1781         if (ntc == 1)
1782                 return;
1783
1784         netdev_set_num_tc(netdev, ntc);
1785
1786         /* Map netdev TCs to offset 0
1787          * We have our own UP to TXQ mapping for QoS
1788          */
1789         for (tc = 0; tc < ntc; tc++)
1790                 netdev_set_tc_queue(netdev, tc, nch, 0);
1791 }
1792
1793 int mlx5e_open_locked(struct net_device *netdev)
1794 {
1795         struct mlx5e_priv *priv = netdev_priv(netdev);
1796         struct mlx5_core_dev *mdev = priv->mdev;
1797         int num_txqs;
1798         int err;
1799
1800         set_bit(MLX5E_STATE_OPENED, &priv->state);
1801
1802         mlx5e_netdev_set_tcs(netdev);
1803
1804         num_txqs = priv->params.num_channels * priv->params.num_tc;
1805         netif_set_real_num_tx_queues(netdev, num_txqs);
1806         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1807
1808         err = mlx5e_open_channels(priv);
1809         if (err) {
1810                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1811                            __func__, err);
1812                 goto err_clear_state_opened_flag;
1813         }
1814
1815         err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
1816         if (err) {
1817                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1818                            __func__, err);
1819                 goto err_close_channels;
1820         }
1821
1822         mlx5e_redirect_rqts(priv);
1823         mlx5e_update_carrier(priv);
1824         mlx5e_timestamp_init(priv);
1825 #ifdef CONFIG_RFS_ACCEL
1826         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1827 #endif
1828         if (priv->profile->update_stats)
1829                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1830
1831         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
1832                 err = mlx5e_add_sqs_fwd_rules(priv);
1833                 if (err)
1834                         goto err_close_channels;
1835         }
1836         return 0;
1837
1838 err_close_channels:
1839         mlx5e_close_channels(priv);
1840 err_clear_state_opened_flag:
1841         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1842         return err;
1843 }
1844
1845 int mlx5e_open(struct net_device *netdev)
1846 {
1847         struct mlx5e_priv *priv = netdev_priv(netdev);
1848         int err;
1849
1850         mutex_lock(&priv->state_lock);
1851         err = mlx5e_open_locked(netdev);
1852         mutex_unlock(&priv->state_lock);
1853
1854         return err;
1855 }
1856
1857 int mlx5e_close_locked(struct net_device *netdev)
1858 {
1859         struct mlx5e_priv *priv = netdev_priv(netdev);
1860         struct mlx5_core_dev *mdev = priv->mdev;
1861
1862         /* May already be CLOSED in case a previous configuration operation
1863          * (e.g RX/TX queue size change) that involves close&open failed.
1864          */
1865         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1866                 return 0;
1867
1868         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1869
1870         if (MLX5_CAP_GEN(mdev, vport_group_manager))
1871                 mlx5e_remove_sqs_fwd_rules(priv);
1872
1873         mlx5e_timestamp_cleanup(priv);
1874         netif_carrier_off(priv->netdev);
1875         mlx5e_redirect_rqts(priv);
1876         mlx5e_close_channels(priv);
1877
1878         return 0;
1879 }
1880
1881 int mlx5e_close(struct net_device *netdev)
1882 {
1883         struct mlx5e_priv *priv = netdev_priv(netdev);
1884         int err;
1885
1886         mutex_lock(&priv->state_lock);
1887         err = mlx5e_close_locked(netdev);
1888         mutex_unlock(&priv->state_lock);
1889
1890         return err;
1891 }
1892
1893 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1894                                 struct mlx5e_rq *rq,
1895                                 struct mlx5e_rq_param *param)
1896 {
1897         struct mlx5_core_dev *mdev = priv->mdev;
1898         void *rqc = param->rqc;
1899         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1900         int err;
1901
1902         param->wq.db_numa_node = param->wq.buf_numa_node;
1903
1904         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1905                                 &rq->wq_ctrl);
1906         if (err)
1907                 return err;
1908
1909         rq->priv = priv;
1910
1911         return 0;
1912 }
1913
1914 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1915                                 struct mlx5e_cq *cq,
1916                                 struct mlx5e_cq_param *param)
1917 {
1918         struct mlx5_core_dev *mdev = priv->mdev;
1919         struct mlx5_core_cq *mcq = &cq->mcq;
1920         int eqn_not_used;
1921         unsigned int irqn;
1922         int err;
1923
1924         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1925                                &cq->wq_ctrl);
1926         if (err)
1927                 return err;
1928
1929         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1930
1931         mcq->cqe_sz     = 64;
1932         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1933         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1934         *mcq->set_ci_db = 0;
1935         *mcq->arm_db    = 0;
1936         mcq->vector     = param->eq_ix;
1937         mcq->comp       = mlx5e_completion_event;
1938         mcq->event      = mlx5e_cq_error_event;
1939         mcq->irqn       = irqn;
1940         mcq->uar        = &mdev->mlx5e_res.cq_uar;
1941
1942         cq->priv = priv;
1943
1944         return 0;
1945 }
1946
1947 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1948 {
1949         struct mlx5e_cq_param cq_param;
1950         struct mlx5e_rq_param rq_param;
1951         struct mlx5e_rq *rq = &priv->drop_rq;
1952         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1953         int err;
1954
1955         memset(&cq_param, 0, sizeof(cq_param));
1956         memset(&rq_param, 0, sizeof(rq_param));
1957         mlx5e_build_drop_rq_param(&rq_param);
1958
1959         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1960         if (err)
1961                 return err;
1962
1963         err = mlx5e_enable_cq(cq, &cq_param);
1964         if (err)
1965                 goto err_destroy_cq;
1966
1967         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1968         if (err)
1969                 goto err_disable_cq;
1970
1971         err = mlx5e_enable_rq(rq, &rq_param);
1972         if (err)
1973                 goto err_destroy_rq;
1974
1975         return 0;
1976
1977 err_destroy_rq:
1978         mlx5e_destroy_rq(&priv->drop_rq);
1979
1980 err_disable_cq:
1981         mlx5e_disable_cq(&priv->drop_rq.cq);
1982
1983 err_destroy_cq:
1984         mlx5e_destroy_cq(&priv->drop_rq.cq);
1985
1986         return err;
1987 }
1988
1989 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1990 {
1991         mlx5e_disable_rq(&priv->drop_rq);
1992         mlx5e_destroy_rq(&priv->drop_rq);
1993         mlx5e_disable_cq(&priv->drop_rq.cq);
1994         mlx5e_destroy_cq(&priv->drop_rq.cq);
1995 }
1996
1997 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1998 {
1999         struct mlx5_core_dev *mdev = priv->mdev;
2000         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2001         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2002
2003         MLX5_SET(tisc, tisc, prio, tc << 1);
2004         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2005
2006         if (mlx5_lag_is_lacp_owner(mdev))
2007                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2008
2009         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2010 }
2011
2012 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2013 {
2014         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2015 }
2016
2017 int mlx5e_create_tises(struct mlx5e_priv *priv)
2018 {
2019         int err;
2020         int tc;
2021
2022         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2023                 err = mlx5e_create_tis(priv, tc);
2024                 if (err)
2025                         goto err_close_tises;
2026         }
2027
2028         return 0;
2029
2030 err_close_tises:
2031         for (tc--; tc >= 0; tc--)
2032                 mlx5e_destroy_tis(priv, tc);
2033
2034         return err;
2035 }
2036
2037 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2038 {
2039         int tc;
2040
2041         for (tc = 0; tc < priv->profile->max_tc; tc++)
2042                 mlx5e_destroy_tis(priv, tc);
2043 }
2044
2045 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2046                                       enum mlx5e_traffic_types tt)
2047 {
2048         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2049
2050         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2051
2052 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2053                                  MLX5_HASH_FIELD_SEL_DST_IP)
2054
2055 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2056                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2057                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2058                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2059
2060 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2061                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2062                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2063
2064         mlx5e_build_tir_ctx_lro(tirc, priv);
2065
2066         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2067         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2068         mlx5e_build_tir_ctx_hash(tirc, priv);
2069
2070         switch (tt) {
2071         case MLX5E_TT_IPV4_TCP:
2072                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2073                          MLX5_L3_PROT_TYPE_IPV4);
2074                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2075                          MLX5_L4_PROT_TYPE_TCP);
2076                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2077                          MLX5_HASH_IP_L4PORTS);
2078                 break;
2079
2080         case MLX5E_TT_IPV6_TCP:
2081                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2082                          MLX5_L3_PROT_TYPE_IPV6);
2083                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2084                          MLX5_L4_PROT_TYPE_TCP);
2085                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2086                          MLX5_HASH_IP_L4PORTS);
2087                 break;
2088
2089         case MLX5E_TT_IPV4_UDP:
2090                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2091                          MLX5_L3_PROT_TYPE_IPV4);
2092                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2093                          MLX5_L4_PROT_TYPE_UDP);
2094                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2095                          MLX5_HASH_IP_L4PORTS);
2096                 break;
2097
2098         case MLX5E_TT_IPV6_UDP:
2099                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2100                          MLX5_L3_PROT_TYPE_IPV6);
2101                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2102                          MLX5_L4_PROT_TYPE_UDP);
2103                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2104                          MLX5_HASH_IP_L4PORTS);
2105                 break;
2106
2107         case MLX5E_TT_IPV4_IPSEC_AH:
2108                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2109                          MLX5_L3_PROT_TYPE_IPV4);
2110                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2111                          MLX5_HASH_IP_IPSEC_SPI);
2112                 break;
2113
2114         case MLX5E_TT_IPV6_IPSEC_AH:
2115                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2116                          MLX5_L3_PROT_TYPE_IPV6);
2117                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2118                          MLX5_HASH_IP_IPSEC_SPI);
2119                 break;
2120
2121         case MLX5E_TT_IPV4_IPSEC_ESP:
2122                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2123                          MLX5_L3_PROT_TYPE_IPV4);
2124                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2125                          MLX5_HASH_IP_IPSEC_SPI);
2126                 break;
2127
2128         case MLX5E_TT_IPV6_IPSEC_ESP:
2129                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2130                          MLX5_L3_PROT_TYPE_IPV6);
2131                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2132                          MLX5_HASH_IP_IPSEC_SPI);
2133                 break;
2134
2135         case MLX5E_TT_IPV4:
2136                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2137                          MLX5_L3_PROT_TYPE_IPV4);
2138                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2139                          MLX5_HASH_IP);
2140                 break;
2141
2142         case MLX5E_TT_IPV6:
2143                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2144                          MLX5_L3_PROT_TYPE_IPV6);
2145                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2146                          MLX5_HASH_IP);
2147                 break;
2148         default:
2149                 WARN_ONCE(true,
2150                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2151         }
2152 }
2153
2154 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2155                                        u32 rqtn)
2156 {
2157         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2158
2159         mlx5e_build_tir_ctx_lro(tirc, priv);
2160
2161         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2162         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2163         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2164 }
2165
2166 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2167 {
2168         struct mlx5e_tir *tir;
2169         void *tirc;
2170         int inlen;
2171         int err;
2172         u32 *in;
2173         int tt;
2174
2175         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2176         in = mlx5_vzalloc(inlen);
2177         if (!in)
2178                 return -ENOMEM;
2179
2180         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2181                 memset(in, 0, inlen);
2182                 tir = &priv->indir_tir[tt];
2183                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2184                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2185                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2186                 if (err)
2187                         goto err_destroy_tirs;
2188         }
2189
2190         kvfree(in);
2191
2192         return 0;
2193
2194 err_destroy_tirs:
2195         for (tt--; tt >= 0; tt--)
2196                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2197
2198         kvfree(in);
2199
2200         return err;
2201 }
2202
2203 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2204 {
2205         int nch = priv->profile->max_nch(priv->mdev);
2206         struct mlx5e_tir *tir;
2207         void *tirc;
2208         int inlen;
2209         int err;
2210         u32 *in;
2211         int ix;
2212
2213         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2214         in = mlx5_vzalloc(inlen);
2215         if (!in)
2216                 return -ENOMEM;
2217
2218         for (ix = 0; ix < nch; ix++) {
2219                 memset(in, 0, inlen);
2220                 tir = &priv->direct_tir[ix];
2221                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2222                 mlx5e_build_direct_tir_ctx(priv, tirc,
2223                                            priv->direct_tir[ix].rqt.rqtn);
2224                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2225                 if (err)
2226                         goto err_destroy_ch_tirs;
2227         }
2228
2229         kvfree(in);
2230
2231         return 0;
2232
2233 err_destroy_ch_tirs:
2234         for (ix--; ix >= 0; ix--)
2235                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2236
2237         kvfree(in);
2238
2239         return err;
2240 }
2241
2242 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2243 {
2244         int i;
2245
2246         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2247                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2248 }
2249
2250 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2251 {
2252         int nch = priv->profile->max_nch(priv->mdev);
2253         int i;
2254
2255         for (i = 0; i < nch; i++)
2256                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2257 }
2258
2259 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2260 {
2261         int err = 0;
2262         int i;
2263
2264         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2265                 return 0;
2266
2267         for (i = 0; i < priv->params.num_channels; i++) {
2268                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2269                 if (err)
2270                         return err;
2271         }
2272
2273         return 0;
2274 }
2275
2276 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2277 {
2278         struct mlx5e_priv *priv = netdev_priv(netdev);
2279         bool was_opened;
2280         int err = 0;
2281
2282         if (tc && tc != MLX5E_MAX_NUM_TC)
2283                 return -EINVAL;
2284
2285         mutex_lock(&priv->state_lock);
2286
2287         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2288         if (was_opened)
2289                 mlx5e_close_locked(priv->netdev);
2290
2291         priv->params.num_tc = tc ? tc : 1;
2292
2293         if (was_opened)
2294                 err = mlx5e_open_locked(priv->netdev);
2295
2296         mutex_unlock(&priv->state_lock);
2297
2298         return err;
2299 }
2300
2301 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2302                               __be16 proto, struct tc_to_netdev *tc)
2303 {
2304         struct mlx5e_priv *priv = netdev_priv(dev);
2305
2306         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2307                 goto mqprio;
2308
2309         switch (tc->type) {
2310         case TC_SETUP_CLSFLOWER:
2311                 switch (tc->cls_flower->command) {
2312                 case TC_CLSFLOWER_REPLACE:
2313                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2314                 case TC_CLSFLOWER_DESTROY:
2315                         return mlx5e_delete_flower(priv, tc->cls_flower);
2316                 case TC_CLSFLOWER_STATS:
2317                         return mlx5e_stats_flower(priv, tc->cls_flower);
2318                 }
2319         default:
2320                 return -EOPNOTSUPP;
2321         }
2322
2323 mqprio:
2324         if (tc->type != TC_SETUP_MQPRIO)
2325                 return -EINVAL;
2326
2327         return mlx5e_setup_tc(dev, tc->tc);
2328 }
2329
2330 struct rtnl_link_stats64 *
2331 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2332 {
2333         struct mlx5e_priv *priv = netdev_priv(dev);
2334         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2335         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2336         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2337
2338         stats->rx_packets = sstats->rx_packets;
2339         stats->rx_bytes   = sstats->rx_bytes;
2340         stats->tx_packets = sstats->tx_packets;
2341         stats->tx_bytes   = sstats->tx_bytes;
2342
2343         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2344         stats->tx_dropped = sstats->tx_queue_dropped;
2345
2346         stats->rx_length_errors =
2347                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2348                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2349                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2350         stats->rx_crc_errors =
2351                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2352         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2353         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2354         stats->tx_carrier_errors =
2355                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2356         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2357                            stats->rx_frame_errors;
2358         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2359
2360         /* vport multicast also counts packets that are dropped due to steering
2361          * or rx out of buffer
2362          */
2363         stats->multicast =
2364                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2365
2366         return stats;
2367 }
2368
2369 static void mlx5e_set_rx_mode(struct net_device *dev)
2370 {
2371         struct mlx5e_priv *priv = netdev_priv(dev);
2372
2373         queue_work(priv->wq, &priv->set_rx_mode_work);
2374 }
2375
2376 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2377 {
2378         struct mlx5e_priv *priv = netdev_priv(netdev);
2379         struct sockaddr *saddr = addr;
2380
2381         if (!is_valid_ether_addr(saddr->sa_data))
2382                 return -EADDRNOTAVAIL;
2383
2384         netif_addr_lock_bh(netdev);
2385         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2386         netif_addr_unlock_bh(netdev);
2387
2388         queue_work(priv->wq, &priv->set_rx_mode_work);
2389
2390         return 0;
2391 }
2392
2393 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2394         do {                                            \
2395                 if (enable)                             \
2396                         netdev->features |= feature;    \
2397                 else                                    \
2398                         netdev->features &= ~feature;   \
2399         } while (0)
2400
2401 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2402
2403 static int set_feature_lro(struct net_device *netdev, bool enable)
2404 {
2405         struct mlx5e_priv *priv = netdev_priv(netdev);
2406         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2407         int err;
2408
2409         mutex_lock(&priv->state_lock);
2410
2411         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2412                 mlx5e_close_locked(priv->netdev);
2413
2414         priv->params.lro_en = enable;
2415         err = mlx5e_modify_tirs_lro(priv);
2416         if (err) {
2417                 netdev_err(netdev, "lro modify failed, %d\n", err);
2418                 priv->params.lro_en = !enable;
2419         }
2420
2421         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2422                 mlx5e_open_locked(priv->netdev);
2423
2424         mutex_unlock(&priv->state_lock);
2425
2426         return err;
2427 }
2428
2429 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2430 {
2431         struct mlx5e_priv *priv = netdev_priv(netdev);
2432
2433         if (enable)
2434                 mlx5e_enable_vlan_filter(priv);
2435         else
2436                 mlx5e_disable_vlan_filter(priv);
2437
2438         return 0;
2439 }
2440
2441 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2442 {
2443         struct mlx5e_priv *priv = netdev_priv(netdev);
2444
2445         if (!enable && mlx5e_tc_num_filters(priv)) {
2446                 netdev_err(netdev,
2447                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2448                 return -EINVAL;
2449         }
2450
2451         return 0;
2452 }
2453
2454 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2455 {
2456         struct mlx5e_priv *priv = netdev_priv(netdev);
2457         struct mlx5_core_dev *mdev = priv->mdev;
2458
2459         return mlx5_set_port_fcs(mdev, !enable);
2460 }
2461
2462 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2463 {
2464         struct mlx5e_priv *priv = netdev_priv(netdev);
2465         int err;
2466
2467         mutex_lock(&priv->state_lock);
2468
2469         priv->params.vlan_strip_disable = !enable;
2470         err = mlx5e_modify_rqs_vsd(priv, !enable);
2471         if (err)
2472                 priv->params.vlan_strip_disable = enable;
2473
2474         mutex_unlock(&priv->state_lock);
2475
2476         return err;
2477 }
2478
2479 #ifdef CONFIG_RFS_ACCEL
2480 static int set_feature_arfs(struct net_device *netdev, bool enable)
2481 {
2482         struct mlx5e_priv *priv = netdev_priv(netdev);
2483         int err;
2484
2485         if (enable)
2486                 err = mlx5e_arfs_enable(priv);
2487         else
2488                 err = mlx5e_arfs_disable(priv);
2489
2490         return err;
2491 }
2492 #endif
2493
2494 static int mlx5e_handle_feature(struct net_device *netdev,
2495                                 netdev_features_t wanted_features,
2496                                 netdev_features_t feature,
2497                                 mlx5e_feature_handler feature_handler)
2498 {
2499         netdev_features_t changes = wanted_features ^ netdev->features;
2500         bool enable = !!(wanted_features & feature);
2501         int err;
2502
2503         if (!(changes & feature))
2504                 return 0;
2505
2506         err = feature_handler(netdev, enable);
2507         if (err) {
2508                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2509                            enable ? "Enable" : "Disable", feature, err);
2510                 return err;
2511         }
2512
2513         MLX5E_SET_FEATURE(netdev, feature, enable);
2514         return 0;
2515 }
2516
2517 static int mlx5e_set_features(struct net_device *netdev,
2518                               netdev_features_t features)
2519 {
2520         int err;
2521
2522         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2523                                     set_feature_lro);
2524         err |= mlx5e_handle_feature(netdev, features,
2525                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2526                                     set_feature_vlan_filter);
2527         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2528                                     set_feature_tc_num_filters);
2529         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2530                                     set_feature_rx_all);
2531         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2532                                     set_feature_rx_vlan);
2533 #ifdef CONFIG_RFS_ACCEL
2534         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2535                                     set_feature_arfs);
2536 #endif
2537
2538         return err ? -EINVAL : 0;
2539 }
2540
2541 #define MXL5_HW_MIN_MTU 64
2542 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2543
2544 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2545 {
2546         struct mlx5e_priv *priv = netdev_priv(netdev);
2547         struct mlx5_core_dev *mdev = priv->mdev;
2548         bool was_opened;
2549         u16 max_mtu;
2550         u16 min_mtu;
2551         int err = 0;
2552         bool reset;
2553
2554         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2555
2556         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2557         min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2558
2559         if (new_mtu > max_mtu || new_mtu < min_mtu) {
2560                 netdev_err(netdev,
2561                            "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2562                            __func__, new_mtu, min_mtu, max_mtu);
2563                 return -EINVAL;
2564         }
2565
2566         mutex_lock(&priv->state_lock);
2567
2568         reset = !priv->params.lro_en &&
2569                 (priv->params.rq_wq_type !=
2570                  MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2571
2572         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2573         if (was_opened && reset)
2574                 mlx5e_close_locked(netdev);
2575
2576         netdev->mtu = new_mtu;
2577         mlx5e_set_dev_port_mtu(netdev);
2578
2579         if (was_opened && reset)
2580                 err = mlx5e_open_locked(netdev);
2581
2582         mutex_unlock(&priv->state_lock);
2583
2584         return err;
2585 }
2586
2587 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2588 {
2589         switch (cmd) {
2590         case SIOCSHWTSTAMP:
2591                 return mlx5e_hwstamp_set(dev, ifr);
2592         case SIOCGHWTSTAMP:
2593                 return mlx5e_hwstamp_get(dev, ifr);
2594         default:
2595                 return -EOPNOTSUPP;
2596         }
2597 }
2598
2599 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2600 {
2601         struct mlx5e_priv *priv = netdev_priv(dev);
2602         struct mlx5_core_dev *mdev = priv->mdev;
2603
2604         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2605 }
2606
2607 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2608 {
2609         struct mlx5e_priv *priv = netdev_priv(dev);
2610         struct mlx5_core_dev *mdev = priv->mdev;
2611
2612         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2613                                            vlan, qos);
2614 }
2615
2616 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2617 {
2618         struct mlx5e_priv *priv = netdev_priv(dev);
2619         struct mlx5_core_dev *mdev = priv->mdev;
2620
2621         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2622 }
2623
2624 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2625 {
2626         struct mlx5e_priv *priv = netdev_priv(dev);
2627         struct mlx5_core_dev *mdev = priv->mdev;
2628
2629         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2630 }
2631 static int mlx5_vport_link2ifla(u8 esw_link)
2632 {
2633         switch (esw_link) {
2634         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2635                 return IFLA_VF_LINK_STATE_DISABLE;
2636         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2637                 return IFLA_VF_LINK_STATE_ENABLE;
2638         }
2639         return IFLA_VF_LINK_STATE_AUTO;
2640 }
2641
2642 static int mlx5_ifla_link2vport(u8 ifla_link)
2643 {
2644         switch (ifla_link) {
2645         case IFLA_VF_LINK_STATE_DISABLE:
2646                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2647         case IFLA_VF_LINK_STATE_ENABLE:
2648                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2649         }
2650         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2651 }
2652
2653 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2654                                    int link_state)
2655 {
2656         struct mlx5e_priv *priv = netdev_priv(dev);
2657         struct mlx5_core_dev *mdev = priv->mdev;
2658
2659         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2660                                             mlx5_ifla_link2vport(link_state));
2661 }
2662
2663 static int mlx5e_get_vf_config(struct net_device *dev,
2664                                int vf, struct ifla_vf_info *ivi)
2665 {
2666         struct mlx5e_priv *priv = netdev_priv(dev);
2667         struct mlx5_core_dev *mdev = priv->mdev;
2668         int err;
2669
2670         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2671         if (err)
2672                 return err;
2673         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2674         return 0;
2675 }
2676
2677 static int mlx5e_get_vf_stats(struct net_device *dev,
2678                               int vf, struct ifla_vf_stats *vf_stats)
2679 {
2680         struct mlx5e_priv *priv = netdev_priv(dev);
2681         struct mlx5_core_dev *mdev = priv->mdev;
2682
2683         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2684                                             vf_stats);
2685 }
2686
2687 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2688                                  struct udp_tunnel_info *ti)
2689 {
2690         struct mlx5e_priv *priv = netdev_priv(netdev);
2691
2692         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2693                 return;
2694
2695         if (!mlx5e_vxlan_allowed(priv->mdev))
2696                 return;
2697
2698         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
2699 }
2700
2701 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2702                                  struct udp_tunnel_info *ti)
2703 {
2704         struct mlx5e_priv *priv = netdev_priv(netdev);
2705
2706         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2707                 return;
2708
2709         if (!mlx5e_vxlan_allowed(priv->mdev))
2710                 return;
2711
2712         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
2713 }
2714
2715 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2716                                                     struct sk_buff *skb,
2717                                                     netdev_features_t features)
2718 {
2719         struct udphdr *udph;
2720         u16 proto;
2721         u16 port = 0;
2722
2723         switch (vlan_get_protocol(skb)) {
2724         case htons(ETH_P_IP):
2725                 proto = ip_hdr(skb)->protocol;
2726                 break;
2727         case htons(ETH_P_IPV6):
2728                 proto = ipv6_hdr(skb)->nexthdr;
2729                 break;
2730         default:
2731                 goto out;
2732         }
2733
2734         if (proto == IPPROTO_UDP) {
2735                 udph = udp_hdr(skb);
2736                 port = be16_to_cpu(udph->dest);
2737         }
2738
2739         /* Verify if UDP port is being offloaded by HW */
2740         if (port && mlx5e_vxlan_lookup_port(priv, port))
2741                 return features;
2742
2743 out:
2744         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2745         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2746 }
2747
2748 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2749                                               struct net_device *netdev,
2750                                               netdev_features_t features)
2751 {
2752         struct mlx5e_priv *priv = netdev_priv(netdev);
2753
2754         features = vlan_features_check(skb, features);
2755         features = vxlan_features_check(skb, features);
2756
2757         /* Validate if the tunneled packet is being offloaded by HW */
2758         if (skb->encapsulation &&
2759             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2760                 return mlx5e_vxlan_features_check(priv, skb, features);
2761
2762         return features;
2763 }
2764
2765 static void mlx5e_tx_timeout(struct net_device *dev)
2766 {
2767         struct mlx5e_priv *priv = netdev_priv(dev);
2768         bool sched_work = false;
2769         int i;
2770
2771         netdev_err(dev, "TX timeout detected\n");
2772
2773         for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
2774                 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
2775
2776                 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
2777                         continue;
2778                 sched_work = true;
2779                 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
2780                 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
2781                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
2782         }
2783
2784         if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
2785                 schedule_work(&priv->tx_timeout_work);
2786 }
2787
2788 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2789         .ndo_open                = mlx5e_open,
2790         .ndo_stop                = mlx5e_close,
2791         .ndo_start_xmit          = mlx5e_xmit,
2792         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2793         .ndo_select_queue        = mlx5e_select_queue,
2794         .ndo_get_stats64         = mlx5e_get_stats,
2795         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2796         .ndo_set_mac_address     = mlx5e_set_mac,
2797         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2798         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2799         .ndo_set_features        = mlx5e_set_features,
2800         .ndo_change_mtu          = mlx5e_change_mtu,
2801         .ndo_do_ioctl            = mlx5e_ioctl,
2802         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
2803 #ifdef CONFIG_RFS_ACCEL
2804         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2805 #endif
2806         .ndo_tx_timeout          = mlx5e_tx_timeout,
2807 };
2808
2809 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2810         .ndo_open                = mlx5e_open,
2811         .ndo_stop                = mlx5e_close,
2812         .ndo_start_xmit          = mlx5e_xmit,
2813         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2814         .ndo_select_queue        = mlx5e_select_queue,
2815         .ndo_get_stats64         = mlx5e_get_stats,
2816         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2817         .ndo_set_mac_address     = mlx5e_set_mac,
2818         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2819         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2820         .ndo_set_features        = mlx5e_set_features,
2821         .ndo_change_mtu          = mlx5e_change_mtu,
2822         .ndo_do_ioctl            = mlx5e_ioctl,
2823         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
2824         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
2825         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
2826         .ndo_features_check      = mlx5e_features_check,
2827 #ifdef CONFIG_RFS_ACCEL
2828         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2829 #endif
2830         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2831         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2832         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
2833         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
2834         .ndo_get_vf_config       = mlx5e_get_vf_config,
2835         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2836         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2837         .ndo_tx_timeout          = mlx5e_tx_timeout,
2838 };
2839
2840 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2841 {
2842         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2843                 return -ENOTSUPP;
2844         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2845             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2846             !MLX5_CAP_ETH(mdev, csum_cap) ||
2847             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2848             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2849             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2850             MLX5_CAP_FLOWTABLE(mdev,
2851                                flow_table_properties_nic_receive.max_ft_level)
2852                                < 3) {
2853                 mlx5_core_warn(mdev,
2854                                "Not creating net device, some required device capabilities are missing\n");
2855                 return -ENOTSUPP;
2856         }
2857         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2858                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2859         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2860                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2861
2862         return 0;
2863 }
2864
2865 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2866 {
2867         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2868
2869         return bf_buf_size -
2870                sizeof(struct mlx5e_tx_wqe) +
2871                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2872 }
2873
2874 #ifdef CONFIG_MLX5_CORE_EN_DCB
2875 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2876 {
2877         int i;
2878
2879         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2880         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2881                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2882                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2883                 priv->params.ets.prio_tc[i] = i;
2884         }
2885
2886         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2887         priv->params.ets.prio_tc[0] = 1;
2888         priv->params.ets.prio_tc[1] = 0;
2889 }
2890 #endif
2891
2892 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2893                                    u32 *indirection_rqt, int len,
2894                                    int num_channels)
2895 {
2896         int node = mdev->priv.numa_node;
2897         int node_num_of_cores;
2898         int i;
2899
2900         if (node == -1)
2901                 node = first_online_node;
2902
2903         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2904
2905         if (node_num_of_cores)
2906                 num_channels = min_t(int, num_channels, node_num_of_cores);
2907
2908         for (i = 0; i < len; i++)
2909                 indirection_rqt[i] = i % num_channels;
2910 }
2911
2912 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2913 {
2914         return MLX5_CAP_GEN(mdev, striding_rq) &&
2915                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2916                 MLX5_CAP_ETH(mdev, reg_umr_sq);
2917 }
2918
2919 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2920 {
2921         enum pcie_link_width width;
2922         enum pci_bus_speed speed;
2923         int err = 0;
2924
2925         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2926         if (err)
2927                 return err;
2928
2929         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2930                 return -EINVAL;
2931
2932         switch (speed) {
2933         case PCIE_SPEED_2_5GT:
2934                 *pci_bw = 2500 * width;
2935                 break;
2936         case PCIE_SPEED_5_0GT:
2937                 *pci_bw = 5000 * width;
2938                 break;
2939         case PCIE_SPEED_8_0GT:
2940                 *pci_bw = 8000 * width;
2941                 break;
2942         default:
2943                 return -EINVAL;
2944         }
2945
2946         return 0;
2947 }
2948
2949 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2950 {
2951         return (link_speed && pci_bw &&
2952                 (pci_bw < 40000) && (pci_bw < link_speed));
2953 }
2954
2955 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
2956 {
2957         params->rx_cq_period_mode = cq_period_mode;
2958
2959         params->rx_cq_moderation.pkts =
2960                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2961         params->rx_cq_moderation.usec =
2962                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2963
2964         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
2965                 params->rx_cq_moderation.usec =
2966                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
2967 }
2968
2969 static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
2970                                    u8 *min_inline_mode)
2971 {
2972         switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
2973         case MLX5E_INLINE_MODE_L2:
2974                 *min_inline_mode = MLX5_INLINE_MODE_L2;
2975                 break;
2976         case MLX5E_INLINE_MODE_VPORT_CONTEXT:
2977                 mlx5_query_nic_vport_min_inline(mdev,
2978                                                 min_inline_mode);
2979                 break;
2980         case MLX5_INLINE_MODE_NOT_REQUIRED:
2981                 *min_inline_mode = MLX5_INLINE_MODE_NONE;
2982                 break;
2983         }
2984 }
2985
2986 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
2987                                         struct net_device *netdev,
2988                                         const struct mlx5e_profile *profile,
2989                                         void *ppriv)
2990 {
2991         struct mlx5e_priv *priv = netdev_priv(netdev);
2992         u32 link_speed = 0;
2993         u32 pci_bw = 0;
2994         u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2995                                          MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
2996                                          MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2997
2998         priv->params.log_sq_size           =
2999                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3000         priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
3001                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
3002                 MLX5_WQ_TYPE_LINKED_LIST;
3003
3004         /* set CQE compression */
3005         priv->params.rx_cqe_compress_admin = false;
3006         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3007             MLX5_CAP_GEN(mdev, vport_group_manager)) {
3008                 mlx5e_get_max_linkspeed(mdev, &link_speed);
3009                 mlx5e_get_pci_bw(mdev, &pci_bw);
3010                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3011                               link_speed, pci_bw);
3012                 priv->params.rx_cqe_compress_admin =
3013                         cqe_compress_heuristic(link_speed, pci_bw);
3014         }
3015
3016         priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3017
3018         switch (priv->params.rq_wq_type) {
3019         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
3020                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
3021                 priv->params.mpwqe_log_stride_sz =
3022                         priv->params.rx_cqe_compress ?
3023                         MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
3024                         MLX5_MPWRQ_LOG_STRIDE_SIZE;
3025                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
3026                         priv->params.mpwqe_log_stride_sz;
3027                 priv->params.lro_en = true;
3028                 break;
3029         default: /* MLX5_WQ_TYPE_LINKED_LIST */
3030                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3031         }
3032
3033         mlx5_core_info(mdev,
3034                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
3035                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
3036                        BIT(priv->params.log_rq_size),
3037                        BIT(priv->params.mpwqe_log_stride_sz),
3038                        priv->params.rx_cqe_compress_admin);
3039
3040         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
3041                                             BIT(priv->params.log_rq_size));
3042
3043         priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3044         mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3045
3046         priv->params.tx_cq_moderation.usec =
3047                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3048         priv->params.tx_cq_moderation.pkts =
3049                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3050         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
3051         mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3052         priv->params.num_tc                = 1;
3053         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
3054
3055         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3056                             sizeof(priv->params.toeplitz_hash_key));
3057
3058         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3059                                       MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3060
3061         priv->params.lro_wqe_sz            =
3062                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3063
3064         /* Initialize pflags */
3065         MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3066                             priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3067
3068         priv->mdev                         = mdev;
3069         priv->netdev                       = netdev;
3070         priv->params.num_channels          = profile->max_nch(mdev);
3071         priv->profile                      = profile;
3072         priv->ppriv                        = ppriv;
3073
3074 #ifdef CONFIG_MLX5_CORE_EN_DCB
3075         mlx5e_ets_init(priv);
3076 #endif
3077
3078         mutex_init(&priv->state_lock);
3079
3080         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3081         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3082         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3083         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3084 }
3085
3086 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3087 {
3088         struct mlx5e_priv *priv = netdev_priv(netdev);
3089
3090         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3091         if (is_zero_ether_addr(netdev->dev_addr) &&
3092             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3093                 eth_hw_addr_random(netdev);
3094                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3095         }
3096 }
3097
3098 static const struct switchdev_ops mlx5e_switchdev_ops = {
3099         .switchdev_port_attr_get        = mlx5e_attr_get,
3100 };
3101
3102 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3103 {
3104         struct mlx5e_priv *priv = netdev_priv(netdev);
3105         struct mlx5_core_dev *mdev = priv->mdev;
3106         bool fcs_supported;
3107         bool fcs_enabled;
3108
3109         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3110
3111         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3112                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3113 #ifdef CONFIG_MLX5_CORE_EN_DCB
3114                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3115 #endif
3116         } else {
3117                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3118         }
3119
3120         netdev->watchdog_timeo    = 15 * HZ;
3121
3122         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
3123
3124         netdev->vlan_features    |= NETIF_F_SG;
3125         netdev->vlan_features    |= NETIF_F_IP_CSUM;
3126         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
3127         netdev->vlan_features    |= NETIF_F_GRO;
3128         netdev->vlan_features    |= NETIF_F_TSO;
3129         netdev->vlan_features    |= NETIF_F_TSO6;
3130         netdev->vlan_features    |= NETIF_F_RXCSUM;
3131         netdev->vlan_features    |= NETIF_F_RXHASH;
3132
3133         if (!!MLX5_CAP_ETH(mdev, lro_cap))
3134                 netdev->vlan_features    |= NETIF_F_LRO;
3135
3136         netdev->hw_features       = netdev->vlan_features;
3137         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
3138         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
3139         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
3140
3141         if (mlx5e_vxlan_allowed(mdev)) {
3142                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
3143                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
3144                                            NETIF_F_GSO_PARTIAL;
3145                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3146                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3147                 netdev->hw_enc_features |= NETIF_F_TSO;
3148                 netdev->hw_enc_features |= NETIF_F_TSO6;
3149                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3150                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3151                                            NETIF_F_GSO_PARTIAL;
3152                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3153         }
3154
3155         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3156
3157         if (fcs_supported)
3158                 netdev->hw_features |= NETIF_F_RXALL;
3159
3160         netdev->features          = netdev->hw_features;
3161         if (!priv->params.lro_en)
3162                 netdev->features  &= ~NETIF_F_LRO;
3163
3164         if (fcs_enabled)
3165                 netdev->features  &= ~NETIF_F_RXALL;
3166
3167 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3168         if (FT_CAP(flow_modify_en) &&
3169             FT_CAP(modify_root) &&
3170             FT_CAP(identified_miss_table_mode) &&
3171             FT_CAP(flow_table_modify)) {
3172                 netdev->hw_features      |= NETIF_F_HW_TC;
3173 #ifdef CONFIG_RFS_ACCEL
3174                 netdev->hw_features      |= NETIF_F_NTUPLE;
3175 #endif
3176         }
3177
3178         netdev->features         |= NETIF_F_HIGHDMA;
3179
3180         netdev->priv_flags       |= IFF_UNICAST_FLT;
3181
3182         mlx5e_set_netdev_dev_addr(netdev);
3183
3184 #ifdef CONFIG_NET_SWITCHDEV
3185         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3186                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3187 #endif
3188 }
3189
3190 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3191 {
3192         struct mlx5_core_dev *mdev = priv->mdev;
3193         int err;
3194
3195         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3196         if (err) {
3197                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3198                 priv->q_counter = 0;
3199         }
3200 }
3201
3202 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3203 {
3204         if (!priv->q_counter)
3205                 return;
3206
3207         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3208 }
3209
3210 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3211 {
3212         struct mlx5_core_dev *mdev = priv->mdev;
3213         u64 npages = MLX5E_REQUIRED_MTTS(priv->profile->max_nch(mdev),
3214                                          BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW));
3215         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3216         void *mkc;
3217         u32 *in;
3218         int err;
3219
3220         in = mlx5_vzalloc(inlen);
3221         if (!in)
3222                 return -ENOMEM;
3223
3224         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3225
3226         npages = min_t(u32, ALIGN(U16_MAX, 4) * 2, npages);
3227
3228         MLX5_SET(mkc, mkc, free, 1);
3229         MLX5_SET(mkc, mkc, umr_en, 1);
3230         MLX5_SET(mkc, mkc, lw, 1);
3231         MLX5_SET(mkc, mkc, lr, 1);
3232         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
3233
3234         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3235         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
3236         MLX5_SET64(mkc, mkc, len, npages << PAGE_SHIFT);
3237         MLX5_SET(mkc, mkc, translations_octword_size,
3238                  MLX5_MTT_OCTW(npages));
3239         MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
3240
3241         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen);
3242
3243         kvfree(in);
3244         return err;
3245 }
3246
3247 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3248                            struct net_device *netdev,
3249                            const struct mlx5e_profile *profile,
3250                            void *ppriv)
3251 {
3252         struct mlx5e_priv *priv = netdev_priv(netdev);
3253
3254         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3255         mlx5e_build_nic_netdev(netdev);
3256         mlx5e_vxlan_init(priv);
3257 }
3258
3259 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3260 {
3261         struct mlx5_core_dev *mdev = priv->mdev;
3262         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3263
3264         mlx5e_vxlan_cleanup(priv);
3265
3266         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3267                 mlx5_eswitch_unregister_vport_rep(esw, 0);
3268 }
3269
3270 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3271 {
3272         struct mlx5_core_dev *mdev = priv->mdev;
3273         int err;
3274         int i;
3275
3276         err = mlx5e_create_indirect_rqts(priv);
3277         if (err) {
3278                 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3279                 return err;
3280         }
3281
3282         err = mlx5e_create_direct_rqts(priv);
3283         if (err) {
3284                 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3285                 goto err_destroy_indirect_rqts;
3286         }
3287
3288         err = mlx5e_create_indirect_tirs(priv);
3289         if (err) {
3290                 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3291                 goto err_destroy_direct_rqts;
3292         }
3293
3294         err = mlx5e_create_direct_tirs(priv);
3295         if (err) {
3296                 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3297                 goto err_destroy_indirect_tirs;
3298         }
3299
3300         err = mlx5e_create_flow_steering(priv);
3301         if (err) {
3302                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3303                 goto err_destroy_direct_tirs;
3304         }
3305
3306         err = mlx5e_tc_init(priv);
3307         if (err)
3308                 goto err_destroy_flow_steering;
3309
3310         return 0;
3311
3312 err_destroy_flow_steering:
3313         mlx5e_destroy_flow_steering(priv);
3314 err_destroy_direct_tirs:
3315         mlx5e_destroy_direct_tirs(priv);
3316 err_destroy_indirect_tirs:
3317         mlx5e_destroy_indirect_tirs(priv);
3318 err_destroy_direct_rqts:
3319         for (i = 0; i < priv->profile->max_nch(mdev); i++)
3320                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3321 err_destroy_indirect_rqts:
3322         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3323         return err;
3324 }
3325
3326 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3327 {
3328         int i;
3329
3330         mlx5e_tc_cleanup(priv);
3331         mlx5e_destroy_flow_steering(priv);
3332         mlx5e_destroy_direct_tirs(priv);
3333         mlx5e_destroy_indirect_tirs(priv);
3334         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3335                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3336         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3337 }
3338
3339 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3340 {
3341         int err;
3342
3343         err = mlx5e_create_tises(priv);
3344         if (err) {
3345                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3346                 return err;
3347         }
3348
3349 #ifdef CONFIG_MLX5_CORE_EN_DCB
3350         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3351 #endif
3352         return 0;
3353 }
3354
3355 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3356 {
3357         struct net_device *netdev = priv->netdev;
3358         struct mlx5_core_dev *mdev = priv->mdev;
3359         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3360         struct mlx5_eswitch_rep rep;
3361
3362         mlx5_lag_add(mdev, netdev);
3363
3364         if (mlx5e_vxlan_allowed(mdev)) {
3365                 rtnl_lock();
3366                 udp_tunnel_get_rx_info(netdev);
3367                 rtnl_unlock();
3368         }
3369
3370         mlx5e_enable_async_events(priv);
3371         queue_work(priv->wq, &priv->set_rx_mode_work);
3372
3373         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3374                 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
3375                 rep.load = mlx5e_nic_rep_load;
3376                 rep.unload = mlx5e_nic_rep_unload;
3377                 rep.vport = 0;
3378                 rep.priv_data = priv;
3379                 mlx5_eswitch_register_vport_rep(esw, &rep);
3380         }
3381 }
3382
3383 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3384 {
3385         queue_work(priv->wq, &priv->set_rx_mode_work);
3386         mlx5e_disable_async_events(priv);
3387         mlx5_lag_remove(priv->mdev);
3388 }
3389
3390 static const struct mlx5e_profile mlx5e_nic_profile = {
3391         .init              = mlx5e_nic_init,
3392         .cleanup           = mlx5e_nic_cleanup,
3393         .init_rx           = mlx5e_init_nic_rx,
3394         .cleanup_rx        = mlx5e_cleanup_nic_rx,
3395         .init_tx           = mlx5e_init_nic_tx,
3396         .cleanup_tx        = mlx5e_cleanup_nic_tx,
3397         .enable            = mlx5e_nic_enable,
3398         .disable           = mlx5e_nic_disable,
3399         .update_stats      = mlx5e_update_stats,
3400         .max_nch           = mlx5e_get_max_num_channels,
3401         .max_tc            = MLX5E_MAX_NUM_TC,
3402 };
3403
3404 void *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3405                           const struct mlx5e_profile *profile, void *ppriv)
3406 {
3407         struct net_device *netdev;
3408         struct mlx5e_priv *priv;
3409         int nch = profile->max_nch(mdev);
3410         int err;
3411
3412         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3413                                     nch * profile->max_tc,
3414                                     nch);
3415         if (!netdev) {
3416                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3417                 return NULL;
3418         }
3419
3420         profile->init(mdev, netdev, profile, ppriv);
3421
3422         netif_carrier_off(netdev);
3423
3424         priv = netdev_priv(netdev);
3425
3426         priv->wq = create_singlethread_workqueue("mlx5e");
3427         if (!priv->wq)
3428                 goto err_free_netdev;
3429
3430         err = mlx5e_create_umr_mkey(priv);
3431         if (err) {
3432                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3433                 goto err_destroy_wq;
3434         }
3435
3436         err = profile->init_tx(priv);
3437         if (err)
3438                 goto err_destroy_umr_mkey;
3439
3440         err = mlx5e_open_drop_rq(priv);
3441         if (err) {
3442                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3443                 goto err_cleanup_tx;
3444         }
3445
3446         err = profile->init_rx(priv);
3447         if (err)
3448                 goto err_close_drop_rq;
3449
3450         mlx5e_create_q_counter(priv);
3451
3452         mlx5e_init_l2_addr(priv);
3453
3454         mlx5e_set_dev_port_mtu(netdev);
3455
3456         err = register_netdev(netdev);
3457         if (err) {
3458                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3459                 goto err_dealloc_q_counters;
3460         }
3461
3462         if (profile->enable)
3463                 profile->enable(priv);
3464
3465         return priv;
3466
3467 err_dealloc_q_counters:
3468         mlx5e_destroy_q_counter(priv);
3469         profile->cleanup_rx(priv);
3470
3471 err_close_drop_rq:
3472         mlx5e_close_drop_rq(priv);
3473
3474 err_cleanup_tx:
3475         profile->cleanup_tx(priv);
3476
3477 err_destroy_umr_mkey:
3478         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3479
3480 err_destroy_wq:
3481         destroy_workqueue(priv->wq);
3482
3483 err_free_netdev:
3484         free_netdev(netdev);
3485
3486         return NULL;
3487 }
3488
3489 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3490 {
3491         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3492         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3493         int vport;
3494         u8 mac[ETH_ALEN];
3495
3496         if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3497                 return;
3498
3499         mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3500
3501         for (vport = 1; vport < total_vfs; vport++) {
3502                 struct mlx5_eswitch_rep rep;
3503
3504                 rep.load = mlx5e_vport_rep_load;
3505                 rep.unload = mlx5e_vport_rep_unload;
3506                 rep.vport = vport;
3507                 ether_addr_copy(rep.hw_id, mac);
3508                 mlx5_eswitch_register_vport_rep(esw, &rep);
3509         }
3510 }
3511
3512 static void *mlx5e_add(struct mlx5_core_dev *mdev)
3513 {
3514         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3515         void *ppriv = NULL;
3516         void *ret;
3517
3518         if (mlx5e_check_required_hca_cap(mdev))
3519                 return NULL;
3520
3521         if (mlx5e_create_mdev_resources(mdev))
3522                 return NULL;
3523
3524         mlx5e_register_vport_rep(mdev);
3525
3526         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3527                 ppriv = &esw->offloads.vport_reps[0];
3528
3529         ret = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
3530         if (!ret) {
3531                 mlx5e_destroy_mdev_resources(mdev);
3532                 return NULL;
3533         }
3534         return ret;
3535 }
3536
3537 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
3538 {
3539         const struct mlx5e_profile *profile = priv->profile;
3540         struct net_device *netdev = priv->netdev;
3541
3542         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3543         if (profile->disable)
3544                 profile->disable(priv);
3545
3546         flush_workqueue(priv->wq);
3547         if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3548                 netif_device_detach(netdev);
3549                 mlx5e_close(netdev);
3550         } else {
3551                 unregister_netdev(netdev);
3552         }
3553
3554         mlx5e_destroy_q_counter(priv);
3555         profile->cleanup_rx(priv);
3556         mlx5e_close_drop_rq(priv);
3557         profile->cleanup_tx(priv);
3558         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3559         cancel_delayed_work_sync(&priv->update_stats_work);
3560         destroy_workqueue(priv->wq);
3561         if (profile->cleanup)
3562                 profile->cleanup(priv);
3563
3564         if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3565                 free_netdev(netdev);
3566 }
3567
3568 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
3569 {
3570         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3571         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3572         struct mlx5e_priv *priv = vpriv;
3573         int vport;
3574
3575         mlx5e_destroy_netdev(mdev, priv);
3576
3577         for (vport = 1; vport < total_vfs; vport++)
3578                 mlx5_eswitch_unregister_vport_rep(esw, vport);
3579
3580         mlx5e_destroy_mdev_resources(mdev);
3581 }
3582
3583 static void *mlx5e_get_netdev(void *vpriv)
3584 {
3585         struct mlx5e_priv *priv = vpriv;
3586
3587         return priv->netdev;
3588 }
3589
3590 static struct mlx5_interface mlx5e_interface = {
3591         .add       = mlx5e_add,
3592         .remove    = mlx5e_remove,
3593         .event     = mlx5e_async_event,
3594         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
3595         .get_dev   = mlx5e_get_netdev,
3596 };
3597
3598 void mlx5e_init(void)
3599 {
3600         mlx5e_build_ptys2ethtool_map();
3601         mlx5_register_interface(&mlx5e_interface);
3602 }
3603
3604 void mlx5e_cleanup(void)
3605 {
3606         mlx5_unregister_interface(&mlx5e_interface);
3607 }