drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/mlx5/flow_table.h>
  34 #include "en.h"
  35
  36 struct mlx5e_rq_param {
  37         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  38         struct mlx5_wq_param       wq;
  39 };
  40
  41 struct mlx5e_sq_param {
  42         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  43         struct mlx5_wq_param       wq;
  44 };
  45
  46 struct mlx5e_cq_param {
  47         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  48         struct mlx5_wq_param       wq;
  49         u16                        eq_ix;
  50 };
  51
  52 struct mlx5e_channel_param {
  53         struct mlx5e_rq_param      rq;
  54         struct mlx5e_sq_param      sq;
  55         struct mlx5e_cq_param      rx_cq;
  56         struct mlx5e_cq_param      tx_cq;
  57 };
  58
  59 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  60 {
  61         struct mlx5_core_dev *mdev = priv->mdev;
  62         u8 port_state;
  63
  64         port_state = mlx5_query_vport_state(mdev,
  65                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT);
  66
  67         if (port_state == VPORT_STATE_UP)
  68                 netif_carrier_on(priv->netdev);
  69         else
  70                 netif_carrier_off(priv->netdev);
  71 }
  72
  73 static void mlx5e_update_carrier_work(struct work_struct *work)
  74 {
  75         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  76                                                update_carrier_work);
  77
  78         mutex_lock(&priv->state_lock);
  79         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  80                 mlx5e_update_carrier(priv);
  81         mutex_unlock(&priv->state_lock);
  82 }
  83
  84 void mlx5e_update_stats(struct mlx5e_priv *priv)
  85 {
  86         struct mlx5_core_dev *mdev = priv->mdev;
  87         struct mlx5e_vport_stats *s = &priv->stats.vport;
  88         struct mlx5e_rq_stats *rq_stats;
  89         struct mlx5e_sq_stats *sq_stats;
  90         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
  91         u32 *out;
  92         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
  93         u64 tx_offload_none;
  94         int i, j;
  95
  96         out = mlx5_vzalloc(outlen);
  97         if (!out)
  98                 return;
  99
 100         /* Collect firts the SW counters and then HW for consistency */
 101         s->tso_packets          = 0;
 102         s->tso_bytes            = 0;
 103         s->tx_queue_stopped     = 0;
 104         s->tx_queue_wake        = 0;
 105         s->tx_queue_dropped     = 0;
 106         tx_offload_none         = 0;
 107         s->lro_packets          = 0;
 108         s->lro_bytes            = 0;
 109         s->rx_csum_none         = 0;
 110         s->rx_wqe_err           = 0;
 111         for (i = 0; i < priv->params.num_channels; i++) {
 112                 rq_stats = &priv->channel[i]->rq.stats;
 113
 114                 s->lro_packets  += rq_stats->lro_packets;
 115                 s->lro_bytes    += rq_stats->lro_bytes;
 116                 s->rx_csum_none += rq_stats->csum_none;
 117                 s->rx_wqe_err   += rq_stats->wqe_err;
 118
 119                 for (j = 0; j < priv->num_tc; j++) {
 120                         sq_stats = &priv->channel[i]->sq[j].stats;
 121
 122                         s->tso_packets          += sq_stats->tso_packets;
 123                         s->tso_bytes            += sq_stats->tso_bytes;
 124                         s->tx_queue_stopped     += sq_stats->stopped;
 125                         s->tx_queue_wake        += sq_stats->wake;
 126                         s->tx_queue_dropped     += sq_stats->dropped;
 127                         tx_offload_none         += sq_stats->csum_offload_none;
 128                 }
 129         }
 130
 131         /* HW counters */
 132         memset(in, 0, sizeof(in));
 133
 134         MLX5_SET(query_vport_counter_in, in, opcode,
 135                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 136         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 137         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 138
 139         memset(out, 0, outlen);
 140
 141         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 142                 goto free_out;
 143
 144 #define MLX5_GET_CTR(p, x) \
 145         MLX5_GET64(query_vport_counter_out, p, x)
 146
 147         s->rx_error_packets     =
 148                 MLX5_GET_CTR(out, received_errors.packets);
 149         s->rx_error_bytes       =
 150                 MLX5_GET_CTR(out, received_errors.octets);
 151         s->tx_error_packets     =
 152                 MLX5_GET_CTR(out, transmit_errors.packets);
 153         s->tx_error_bytes       =
 154                 MLX5_GET_CTR(out, transmit_errors.octets);
 155
 156         s->rx_unicast_packets   =
 157                 MLX5_GET_CTR(out, received_eth_unicast.packets);
 158         s->rx_unicast_bytes     =
 159                 MLX5_GET_CTR(out, received_eth_unicast.octets);
 160         s->tx_unicast_packets   =
 161                 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 162         s->tx_unicast_bytes     =
 163                 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 164
 165         s->rx_multicast_packets =
 166                 MLX5_GET_CTR(out, received_eth_multicast.packets);
 167         s->rx_multicast_bytes   =
 168                 MLX5_GET_CTR(out, received_eth_multicast.octets);
 169         s->tx_multicast_packets =
 170                 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 171         s->tx_multicast_bytes   =
 172                 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 173
 174         s->rx_broadcast_packets =
 175                 MLX5_GET_CTR(out, received_eth_broadcast.packets);
 176         s->rx_broadcast_bytes   =
 177                 MLX5_GET_CTR(out, received_eth_broadcast.octets);
 178         s->tx_broadcast_packets =
 179                 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 180         s->tx_broadcast_bytes   =
 181                 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 182
 183         s->rx_packets =
 184                 s->rx_unicast_packets +
 185                 s->rx_multicast_packets +
 186                 s->rx_broadcast_packets;
 187         s->rx_bytes =
 188                 s->rx_unicast_bytes +
 189                 s->rx_multicast_bytes +
 190                 s->rx_broadcast_bytes;
 191         s->tx_packets =
 192                 s->tx_unicast_packets +
 193                 s->tx_multicast_packets +
 194                 s->tx_broadcast_packets;
 195         s->tx_bytes =
 196                 s->tx_unicast_bytes +
 197                 s->tx_multicast_bytes +
 198                 s->tx_broadcast_bytes;
 199
 200         /* Update calculated offload counters */
 201         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 202         s->rx_csum_good    = s->rx_packets - s->rx_csum_none;
 203
 204 free_out:
 205         kvfree(out);
 206 }
 207
 208 static void mlx5e_update_stats_work(struct work_struct *work)
 209 {
 210         struct delayed_work *dwork = to_delayed_work(work);
 211         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 212                                                update_stats_work);
 213         mutex_lock(&priv->state_lock);
 214         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 215                 mlx5e_update_stats(priv);
 216                 schedule_delayed_work(dwork,
 217                                       msecs_to_jiffies(
 218                                               MLX5E_UPDATE_STATS_INTERVAL));
 219         }
 220         mutex_unlock(&priv->state_lock);
 221 }
 222
 223 static void __mlx5e_async_event(struct mlx5e_priv *priv,
 224                                 enum mlx5_dev_event event)
 225 {
 226         switch (event) {
 227         case MLX5_DEV_EVENT_PORT_UP:
 228         case MLX5_DEV_EVENT_PORT_DOWN:
 229                 schedule_work(&priv->update_carrier_work);
 230                 break;
 231
 232         default:
 233                 break;
 234         }
 235 }
 236
 237 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 238                               enum mlx5_dev_event event, unsigned long param)
 239 {
 240         struct mlx5e_priv *priv = vpriv;
 241
 242         spin_lock(&priv->async_events_spinlock);
 243         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 244                 __mlx5e_async_event(priv, event);
 245         spin_unlock(&priv->async_events_spinlock);
 246 }
 247
 248 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 249 {
 250         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 251 }
 252
 253 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 254 {
 255         spin_lock_irq(&priv->async_events_spinlock);
 256         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 257         spin_unlock_irq(&priv->async_events_spinlock);
 258 }
 259
 260 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 261 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 262
 263 static int mlx5e_create_rq(struct mlx5e_channel *c,
 264                            struct mlx5e_rq_param *param,
 265                            struct mlx5e_rq *rq)
 266 {
 267         struct mlx5e_priv *priv = c->priv;
 268         struct mlx5_core_dev *mdev = priv->mdev;
 269         void *rqc = param->rqc;
 270         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 271         int wq_sz;
 272         int err;
 273         int i;
 274
 275         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 276                                 &rq->wq_ctrl);
 277         if (err)
 278                 return err;
 279
 280         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 281
 282         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 283         rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 284                                cpu_to_node(c->cpu));
 285         if (!rq->skb) {
 286                 err = -ENOMEM;
 287                 goto err_rq_wq_destroy;
 288         }
 289
 290         rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
 291                                              MLX5E_SW2HW_MTU(priv->netdev->mtu);
 292         rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
 293
 294         for (i = 0; i < wq_sz; i++) {
 295                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 296                 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 297
 298                 wqe->data.lkey       = c->mkey_be;
 299                 wqe->data.byte_count =
 300                         cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 301         }
 302
 303         rq->pdev    = c->pdev;
 304         rq->netdev  = c->netdev;
 305         rq->channel = c;
 306         rq->ix      = c->ix;
 307
 308         return 0;
 309
 310 err_rq_wq_destroy:
 311         mlx5_wq_destroy(&rq->wq_ctrl);
 312
 313         return err;
 314 }
 315
 316 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 317 {
 318         kfree(rq->skb);
 319         mlx5_wq_destroy(&rq->wq_ctrl);
 320 }
 321
 322 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 323 {
 324         struct mlx5e_channel *c = rq->channel;
 325         struct mlx5e_priv *priv = c->priv;
 326         struct mlx5_core_dev *mdev = priv->mdev;
 327
 328         void *in;
 329         void *rqc;
 330         void *wq;
 331         int inlen;
 332         int err;
 333
 334         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 335                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 336         in = mlx5_vzalloc(inlen);
 337         if (!in)
 338                 return -ENOMEM;
 339
 340         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 341         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 342
 343         memcpy(rqc, param->rqc, sizeof(param->rqc));
 344
 345         MLX5_SET(rqc,  rqc, cqn,                c->rq.cq.mcq.cqn);
 346         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 347         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 348         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 349                                                 PAGE_SHIFT);
 350         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 351
 352         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 353                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 354
 355         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 356
 357         kvfree(in);
 358
 359         return err;
 360 }
 361
 362 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 363 {
 364         struct mlx5e_channel *c = rq->channel;
 365         struct mlx5e_priv *priv = c->priv;
 366         struct mlx5_core_dev *mdev = priv->mdev;
 367
 368         void *in;
 369         void *rqc;
 370         int inlen;
 371         int err;
 372
 373         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 374         in = mlx5_vzalloc(inlen);
 375         if (!in)
 376                 return -ENOMEM;
 377
 378         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 379
 380         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 381         MLX5_SET(rqc, rqc, state, next_state);
 382
 383         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 384
 385         kvfree(in);
 386
 387         return err;
 388 }
 389
 390 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 391 {
 392         struct mlx5e_channel *c = rq->channel;
 393         struct mlx5e_priv *priv = c->priv;
 394         struct mlx5_core_dev *mdev = priv->mdev;
 395
 396         mlx5_core_destroy_rq(mdev, rq->rqn);
 397 }
 398
 399 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 400 {
 401         struct mlx5e_channel *c = rq->channel;
 402         struct mlx5e_priv *priv = c->priv;
 403         struct mlx5_wq_ll *wq = &rq->wq;
 404         int i;
 405
 406         for (i = 0; i < 1000; i++) {
 407                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 408                         return 0;
 409
 410                 msleep(20);
 411         }
 412
 413         return -ETIMEDOUT;
 414 }
 415
 416 static int mlx5e_open_rq(struct mlx5e_channel *c,
 417                          struct mlx5e_rq_param *param,
 418                          struct mlx5e_rq *rq)
 419 {
 420         int err;
 421
 422         err = mlx5e_create_rq(c, param, rq);
 423         if (err)
 424                 return err;
 425
 426         err = mlx5e_enable_rq(rq, param);
 427         if (err)
 428                 goto err_destroy_rq;
 429
 430         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 431         if (err)
 432                 goto err_disable_rq;
 433
 434         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 435         mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
 436
 437         return 0;
 438
 439 err_disable_rq:
 440         mlx5e_disable_rq(rq);
 441 err_destroy_rq:
 442         mlx5e_destroy_rq(rq);
 443
 444         return err;
 445 }
 446
 447 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 448 {
 449         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 450         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 451
 452         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 453         while (!mlx5_wq_ll_is_empty(&rq->wq))
 454                 msleep(20);
 455
 456         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 457         napi_synchronize(&rq->channel->napi);
 458
 459         mlx5e_disable_rq(rq);
 460         mlx5e_destroy_rq(rq);
 461 }
 462
 463 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 464 {
 465         kfree(sq->dma_fifo);
 466         kfree(sq->skb);
 467 }
 468
 469 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 470 {
 471         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 472         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 473
 474         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 475         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 476                                     numa);
 477
 478         if (!sq->skb || !sq->dma_fifo) {
 479                 mlx5e_free_sq_db(sq);
 480                 return -ENOMEM;
 481         }
 482
 483         sq->dma_fifo_mask = df_sz - 1;
 484
 485         return 0;
 486 }
 487
 488 static int mlx5e_create_sq(struct mlx5e_channel *c,
 489                            int tc,
 490                            struct mlx5e_sq_param *param,
 491                            struct mlx5e_sq *sq)
 492 {
 493         struct mlx5e_priv *priv = c->priv;
 494         struct mlx5_core_dev *mdev = priv->mdev;
 495
 496         void *sqc = param->sqc;
 497         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 498         int txq_ix;
 499         int err;
 500
 501         err = mlx5_alloc_map_uar(mdev, &sq->uar);
 502         if (err)
 503                 return err;
 504
 505         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 506                                  &sq->wq_ctrl);
 507         if (err)
 508                 goto err_unmap_free_uar;
 509
 510         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 511         sq->uar_map     = sq->uar.map;
 512         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 513
 514         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 515         if (err)
 516                 goto err_sq_wq_destroy;
 517
 518         txq_ix = c->ix + tc * priv->params.num_channels;
 519         sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 520
 521         sq->pdev    = c->pdev;
 522         sq->mkey_be = c->mkey_be;
 523         sq->channel = c;
 524         sq->tc      = tc;
 525         sq->edge    = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 526         priv->txq_to_sq_map[txq_ix] = sq;
 527
 528         return 0;
 529
 530 err_sq_wq_destroy:
 531         mlx5_wq_destroy(&sq->wq_ctrl);
 532
 533 err_unmap_free_uar:
 534         mlx5_unmap_free_uar(mdev, &sq->uar);
 535
 536         return err;
 537 }
 538
 539 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 540 {
 541         struct mlx5e_channel *c = sq->channel;
 542         struct mlx5e_priv *priv = c->priv;
 543
 544         mlx5e_free_sq_db(sq);
 545         mlx5_wq_destroy(&sq->wq_ctrl);
 546         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 547 }
 548
 549 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 550 {
 551         struct mlx5e_channel *c = sq->channel;
 552         struct mlx5e_priv *priv = c->priv;
 553         struct mlx5_core_dev *mdev = priv->mdev;
 554
 555         void *in;
 556         void *sqc;
 557         void *wq;
 558         int inlen;
 559         int err;
 560
 561         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 562                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 563         in = mlx5_vzalloc(inlen);
 564         if (!in)
 565                 return -ENOMEM;
 566
 567         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 568         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 569
 570         memcpy(sqc, param->sqc, sizeof(param->sqc));
 571
 572         MLX5_SET(sqc,  sqc, user_index,         sq->tc);
 573         MLX5_SET(sqc,  sqc, tis_num_0,          priv->tisn[sq->tc]);
 574         MLX5_SET(sqc,  sqc, cqn,                c->sq[sq->tc].cq.mcq.cqn);
 575         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 576         MLX5_SET(sqc,  sqc, tis_lst_sz,         1);
 577         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 578
 579         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 580         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 581         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 582                                           PAGE_SHIFT);
 583         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 584
 585         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 586                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 587
 588         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 589
 590         kvfree(in);
 591
 592         return err;
 593 }
 594
 595 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 596 {
 597         struct mlx5e_channel *c = sq->channel;
 598         struct mlx5e_priv *priv = c->priv;
 599         struct mlx5_core_dev *mdev = priv->mdev;
 600
 601         void *in;
 602         void *sqc;
 603         int inlen;
 604         int err;
 605
 606         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 607         in = mlx5_vzalloc(inlen);
 608         if (!in)
 609                 return -ENOMEM;
 610
 611         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 612
 613         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 614         MLX5_SET(sqc, sqc, state, next_state);
 615
 616         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 617
 618         kvfree(in);
 619
 620         return err;
 621 }
 622
 623 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 624 {
 625         struct mlx5e_channel *c = sq->channel;
 626         struct mlx5e_priv *priv = c->priv;
 627         struct mlx5_core_dev *mdev = priv->mdev;
 628
 629         mlx5_core_destroy_sq(mdev, sq->sqn);
 630 }
 631
 632 static int mlx5e_open_sq(struct mlx5e_channel *c,
 633                          int tc,
 634                          struct mlx5e_sq_param *param,
 635                          struct mlx5e_sq *sq)
 636 {
 637         int err;
 638
 639         err = mlx5e_create_sq(c, tc, param, sq);
 640         if (err)
 641                 return err;
 642
 643         err = mlx5e_enable_sq(sq, param);
 644         if (err)
 645                 goto err_destroy_sq;
 646
 647         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 648         if (err)
 649                 goto err_disable_sq;
 650
 651         set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 652         netdev_tx_reset_queue(sq->txq);
 653         netif_tx_start_queue(sq->txq);
 654
 655         return 0;
 656
 657 err_disable_sq:
 658         mlx5e_disable_sq(sq);
 659 err_destroy_sq:
 660         mlx5e_destroy_sq(sq);
 661
 662         return err;
 663 }
 664
 665 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 666 {
 667         __netif_tx_lock_bh(txq);
 668         netif_tx_stop_queue(txq);
 669         __netif_tx_unlock_bh(txq);
 670 }
 671
 672 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 673 {
 674         clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 675         napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
 676         netif_tx_disable_queue(sq->txq);
 677
 678         /* ensure hw is notified of all pending wqes */
 679         if (mlx5e_sq_has_room_for(sq, 1))
 680                 mlx5e_send_nop(sq, true);
 681
 682         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 683         while (sq->cc != sq->pc) /* wait till sq is empty */
 684                 msleep(20);
 685
 686         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 687         napi_synchronize(&sq->channel->napi);
 688
 689         mlx5e_disable_sq(sq);
 690         mlx5e_destroy_sq(sq);
 691 }
 692
 693 static int mlx5e_create_cq(struct mlx5e_channel *c,
 694                            struct mlx5e_cq_param *param,
 695                            struct mlx5e_cq *cq)
 696 {
 697         struct mlx5e_priv *priv = c->priv;
 698         struct mlx5_core_dev *mdev = priv->mdev;
 699         struct mlx5_core_cq *mcq = &cq->mcq;
 700         int eqn_not_used;
 701         int irqn;
 702         int err;
 703         u32 i;
 704
 705         param->wq.numa = cpu_to_node(c->cpu);
 706         param->eq_ix   = c->ix;
 707
 708         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 709                                &cq->wq_ctrl);
 710         if (err)
 711                 return err;
 712
 713         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 714
 715         cq->napi        = &c->napi;
 716
 717         mcq->cqe_sz     = 64;
 718         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 719         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 720         *mcq->set_ci_db = 0;
 721         *mcq->arm_db    = 0;
 722         mcq->vector     = param->eq_ix;
 723         mcq->comp       = mlx5e_completion_event;
 724         mcq->event      = mlx5e_cq_error_event;
 725         mcq->irqn       = irqn;
 726         mcq->uar        = &priv->cq_uar;
 727
 728         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 729                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 730
 731                 cqe->op_own = 0xf1;
 732         }
 733
 734         cq->channel = c;
 735
 736         return 0;
 737 }
 738
 739 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 740 {
 741         mlx5_wq_destroy(&cq->wq_ctrl);
 742 }
 743
 744 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 745 {
 746         struct mlx5e_channel *c = cq->channel;
 747         struct mlx5e_priv *priv = c->priv;
 748         struct mlx5_core_dev *mdev = priv->mdev;
 749         struct mlx5_core_cq *mcq = &cq->mcq;
 750
 751         void *in;
 752         void *cqc;
 753         int inlen;
 754         int irqn_not_used;
 755         int eqn;
 756         int err;
 757
 758         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 759                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 760         in = mlx5_vzalloc(inlen);
 761         if (!in)
 762                 return -ENOMEM;
 763
 764         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 765
 766         memcpy(cqc, param->cqc, sizeof(param->cqc));
 767
 768         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 769                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 770
 771         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 772
 773         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 774         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 775         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 776                                             PAGE_SHIFT);
 777         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 778
 779         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 780
 781         kvfree(in);
 782
 783         if (err)
 784                 return err;
 785
 786         mlx5e_cq_arm(cq);
 787
 788         return 0;
 789 }
 790
 791 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 792 {
 793         struct mlx5e_channel *c = cq->channel;
 794         struct mlx5e_priv *priv = c->priv;
 795         struct mlx5_core_dev *mdev = priv->mdev;
 796
 797         mlx5_core_destroy_cq(mdev, &cq->mcq);
 798 }
 799
 800 static int mlx5e_open_cq(struct mlx5e_channel *c,
 801                          struct mlx5e_cq_param *param,
 802                          struct mlx5e_cq *cq,
 803                          u16 moderation_usecs,
 804                          u16 moderation_frames)
 805 {
 806         int err;
 807         struct mlx5e_priv *priv = c->priv;
 808         struct mlx5_core_dev *mdev = priv->mdev;
 809
 810         err = mlx5e_create_cq(c, param, cq);
 811         if (err)
 812                 return err;
 813
 814         err = mlx5e_enable_cq(cq, param);
 815         if (err)
 816                 goto err_destroy_cq;
 817
 818         err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 819                                              moderation_usecs,
 820                                              moderation_frames);
 821         if (err)
 822                 goto err_destroy_cq;
 823
 824         return 0;
 825
 826 err_destroy_cq:
 827         mlx5e_destroy_cq(cq);
 828
 829         return err;
 830 }
 831
 832 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 833 {
 834         mlx5e_disable_cq(cq);
 835         mlx5e_destroy_cq(cq);
 836 }
 837
 838 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 839 {
 840         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 841 }
 842
 843 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 844                              struct mlx5e_channel_param *cparam)
 845 {
 846         struct mlx5e_priv *priv = c->priv;
 847         int err;
 848         int tc;
 849
 850         for (tc = 0; tc < c->num_tc; tc++) {
 851                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 852                                     priv->params.tx_cq_moderation_usec,
 853                                     priv->params.tx_cq_moderation_pkts);
 854                 if (err)
 855                         goto err_close_tx_cqs;
 856         }
 857
 858         return 0;
 859
 860 err_close_tx_cqs:
 861         for (tc--; tc >= 0; tc--)
 862                 mlx5e_close_cq(&c->sq[tc].cq);
 863
 864         return err;
 865 }
 866
 867 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 868 {
 869         int tc;
 870
 871         for (tc = 0; tc < c->num_tc; tc++)
 872                 mlx5e_close_cq(&c->sq[tc].cq);
 873 }
 874
 875 static int mlx5e_open_sqs(struct mlx5e_channel *c,
 876                           struct mlx5e_channel_param *cparam)
 877 {
 878         int err;
 879         int tc;
 880
 881         for (tc = 0; tc < c->num_tc; tc++) {
 882                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
 883                 if (err)
 884                         goto err_close_sqs;
 885         }
 886
 887         return 0;
 888
 889 err_close_sqs:
 890         for (tc--; tc >= 0; tc--)
 891                 mlx5e_close_sq(&c->sq[tc]);
 892
 893         return err;
 894 }
 895
 896 static void mlx5e_close_sqs(struct mlx5e_channel *c)
 897 {
 898         int tc;
 899
 900         for (tc = 0; tc < c->num_tc; tc++)
 901                 mlx5e_close_sq(&c->sq[tc]);
 902 }
 903
 904 static void mlx5e_build_tc_to_txq_map(struct mlx5e_channel *c,
 905                                       int num_channels)
 906 {
 907         int i;
 908
 909         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
 910                 c->tc_to_txq_map[i] = c->ix + i * num_channels;
 911 }
 912
 913 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
 914                               struct mlx5e_channel_param *cparam,
 915                               struct mlx5e_channel **cp)
 916 {
 917         struct net_device *netdev = priv->netdev;
 918         int cpu = mlx5e_get_cpu(priv, ix);
 919         struct mlx5e_channel *c;
 920         int err;
 921
 922         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
 923         if (!c)
 924                 return -ENOMEM;
 925
 926         c->priv     = priv;
 927         c->ix       = ix;
 928         c->cpu      = cpu;
 929         c->pdev     = &priv->mdev->pdev->dev;
 930         c->netdev   = priv->netdev;
 931         c->mkey_be  = cpu_to_be32(priv->mr.key);
 932         c->num_tc   = priv->num_tc;
 933
 934         mlx5e_build_tc_to_txq_map(c, priv->params.num_channels);
 935
 936         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
 937
 938         err = mlx5e_open_tx_cqs(c, cparam);
 939         if (err)
 940                 goto err_napi_del;
 941
 942         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
 943                             priv->params.rx_cq_moderation_usec,
 944                             priv->params.rx_cq_moderation_pkts);
 945         if (err)
 946                 goto err_close_tx_cqs;
 947
 948         napi_enable(&c->napi);
 949
 950         err = mlx5e_open_sqs(c, cparam);
 951         if (err)
 952                 goto err_disable_napi;
 953
 954         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
 955         if (err)
 956                 goto err_close_sqs;
 957
 958         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
 959         *cp = c;
 960
 961         return 0;
 962
 963 err_close_sqs:
 964         mlx5e_close_sqs(c);
 965
 966 err_disable_napi:
 967         napi_disable(&c->napi);
 968         mlx5e_close_cq(&c->rq.cq);
 969
 970 err_close_tx_cqs:
 971         mlx5e_close_tx_cqs(c);
 972
 973 err_napi_del:
 974         netif_napi_del(&c->napi);
 975         kfree(c);
 976
 977         return err;
 978 }
 979
 980 static void mlx5e_close_channel(struct mlx5e_channel *c)
 981 {
 982         mlx5e_close_rq(&c->rq);
 983         mlx5e_close_sqs(c);
 984         napi_disable(&c->napi);
 985         mlx5e_close_cq(&c->rq.cq);
 986         mlx5e_close_tx_cqs(c);
 987         netif_napi_del(&c->napi);
 988         kfree(c);
 989 }
 990
 991 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
 992                                  struct mlx5e_rq_param *param)
 993 {
 994         void *rqc = param->rqc;
 995         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
 996
 997         MLX5_SET(wq, wq, wq_type,          MLX5_WQ_TYPE_LINKED_LIST);
 998         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
 999         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1000         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1001         MLX5_SET(wq, wq, pd,               priv->pdn);
1002
1003         param->wq.numa   = dev_to_node(&priv->mdev->pdev->dev);
1004         param->wq.linear = 1;
1005 }
1006
1007 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1008                                  struct mlx5e_sq_param *param)
1009 {
1010         void *sqc = param->sqc;
1011         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1012
1013         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1014         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1015         MLX5_SET(wq, wq, pd,            priv->pdn);
1016
1017         param->wq.numa = dev_to_node(&priv->mdev->pdev->dev);
1018 }
1019
1020 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1021                                         struct mlx5e_cq_param *param)
1022 {
1023         void *cqc = param->cqc;
1024
1025         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1026 }
1027
1028 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1029                                     struct mlx5e_cq_param *param)
1030 {
1031         void *cqc = param->cqc;
1032
1033         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_rq_size);
1034
1035         mlx5e_build_common_cq_param(priv, param);
1036 }
1037
1038 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1039                                     struct mlx5e_cq_param *param)
1040 {
1041         void *cqc = param->cqc;
1042
1043         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_sq_size);
1044
1045         mlx5e_build_common_cq_param(priv, param);
1046 }
1047
1048 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1049                                       struct mlx5e_channel_param *cparam)
1050 {
1051         memset(cparam, 0, sizeof(*cparam));
1052
1053         mlx5e_build_rq_param(priv, &cparam->rq);
1054         mlx5e_build_sq_param(priv, &cparam->sq);
1055         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1056         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1057 }
1058
1059 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1060 {
1061         struct mlx5e_channel_param cparam;
1062         int err = -ENOMEM;
1063         int i;
1064         int j;
1065
1066         priv->channel = kcalloc(priv->params.num_channels,
1067                                 sizeof(struct mlx5e_channel *), GFP_KERNEL);
1068
1069         priv->txq_to_sq_map = kcalloc(priv->params.num_channels * priv->num_tc,
1070                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1071
1072         if (!priv->channel || !priv->txq_to_sq_map)
1073                 goto err_free_txq_to_sq_map;
1074
1075         mlx5e_build_channel_param(priv, &cparam);
1076         for (i = 0; i < priv->params.num_channels; i++) {
1077                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1078                 if (err)
1079                         goto err_close_channels;
1080         }
1081
1082         for (j = 0; j < priv->params.num_channels; j++) {
1083                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1084                 if (err)
1085                         goto err_close_channels;
1086         }
1087
1088         return 0;
1089
1090 err_close_channels:
1091         for (i--; i >= 0; i--)
1092                 mlx5e_close_channel(priv->channel[i]);
1093
1094 err_free_txq_to_sq_map:
1095         kfree(priv->txq_to_sq_map);
1096         kfree(priv->channel);
1097
1098         return err;
1099 }
1100
1101 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1102 {
1103         int i;
1104
1105         for (i = 0; i < priv->params.num_channels; i++)
1106                 mlx5e_close_channel(priv->channel[i]);
1107
1108         kfree(priv->txq_to_sq_map);
1109         kfree(priv->channel);
1110 }
1111
1112 static int mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1113 {
1114         struct mlx5_core_dev *mdev = priv->mdev;
1115         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1116         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1117
1118         memset(in, 0, sizeof(in));
1119
1120         MLX5_SET(tisc, tisc, prio,  tc);
1121         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1122
1123         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1124 }
1125
1126 static void mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1127 {
1128         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1129 }
1130
1131 static int mlx5e_open_tises(struct mlx5e_priv *priv)
1132 {
1133         int num_tc = priv->num_tc;
1134         int err;
1135         int tc;
1136
1137         for (tc = 0; tc < num_tc; tc++) {
1138                 err = mlx5e_open_tis(priv, tc);
1139                 if (err)
1140                         goto err_close_tises;
1141         }
1142
1143         return 0;
1144
1145 err_close_tises:
1146         for (tc--; tc >= 0; tc--)
1147                 mlx5e_close_tis(priv, tc);
1148
1149         return err;
1150 }
1151
1152 static void mlx5e_close_tises(struct mlx5e_priv *priv)
1153 {
1154         int num_tc = priv->num_tc;
1155         int tc;
1156
1157         for (tc = 0; tc < num_tc; tc++)
1158                 mlx5e_close_tis(priv, tc);
1159 }
1160
1161 static int mlx5e_rx_hash_fn(int hfunc)
1162 {
1163         return (hfunc == ETH_RSS_HASH_TOP) ?
1164                MLX5_RX_HASH_FN_TOEPLITZ :
1165                MLX5_RX_HASH_FN_INVERTED_XOR8;
1166 }
1167
1168 static int mlx5e_bits_invert(unsigned long a, int size)
1169 {
1170         int inv = 0;
1171         int i;
1172
1173         for (i = 0; i < size; i++)
1174                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1175
1176         return inv;
1177 }
1178
1179 static int mlx5e_open_rqt(struct mlx5e_priv *priv)
1180 {
1181         struct mlx5_core_dev *mdev = priv->mdev;
1182         u32 *in;
1183         u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1184         void *rqtc;
1185         int inlen;
1186         int err;
1187         int log_tbl_sz = priv->params.rx_hash_log_tbl_sz;
1188         int sz = 1 << log_tbl_sz;
1189         int i;
1190
1191         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1192         in = mlx5_vzalloc(inlen);
1193         if (!in)
1194                 return -ENOMEM;
1195
1196         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1197
1198         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1199         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1200
1201         for (i = 0; i < sz; i++) {
1202                 int ix = i;
1203
1204                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1205                         ix = mlx5e_bits_invert(i, log_tbl_sz);
1206
1207                 ix = ix % priv->params.num_channels;
1208                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
1209         }
1210
1211         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1212
1213         memset(out, 0, sizeof(out));
1214         err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
1215         if (!err)
1216                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
1217
1218         kvfree(in);
1219
1220         return err;
1221 }
1222
1223 static void mlx5e_close_rqt(struct mlx5e_priv *priv)
1224 {
1225         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
1226         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
1227
1228         memset(in, 0, sizeof(in));
1229
1230         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
1231         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
1232
1233         mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
1234                                    sizeof(out));
1235 }
1236
1237 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1238 {
1239         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1240
1241         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1242
1243 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1244
1245 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1246                           MLX5_HASH_FIELD_SEL_DST_IP)
1247
1248 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1249                           MLX5_HASH_FIELD_SEL_DST_IP   |\
1250                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
1251                           MLX5_HASH_FIELD_SEL_L4_DPORT)
1252
1253         if (priv->params.lro_en) {
1254                 MLX5_SET(tirc, tirc, lro_enable_mask,
1255                          MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1256                          MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1257                 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1258                          (priv->params.lro_wqe_sz -
1259                           ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1260                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1261                          MLX5_CAP_ETH(priv->mdev,
1262                                       lro_timer_supported_periods[3]));
1263         }
1264
1265         switch (tt) {
1266         case MLX5E_TT_ANY:
1267                 MLX5_SET(tirc, tirc, disp_type,
1268                          MLX5_TIRC_DISP_TYPE_DIRECT);
1269                 MLX5_SET(tirc, tirc, inline_rqn,
1270                          priv->channel[0]->rq.rqn);
1271                 break;
1272         default:
1273                 MLX5_SET(tirc, tirc, disp_type,
1274                          MLX5_TIRC_DISP_TYPE_INDIRECT);
1275                 MLX5_SET(tirc, tirc, indirect_table,
1276                          priv->rqtn);
1277                 MLX5_SET(tirc, tirc, rx_hash_fn,
1278                          mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1279                 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1280                         void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1281                                                      rx_hash_toeplitz_key);
1282                         size_t len = MLX5_FLD_SZ_BYTES(tirc,
1283                                                        rx_hash_toeplitz_key);
1284
1285                         MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1286                         netdev_rss_key_fill(rss_key, len);
1287                 }
1288                 break;
1289         }
1290
1291         switch (tt) {
1292         case MLX5E_TT_IPV4_TCP:
1293                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1294                          MLX5_L3_PROT_TYPE_IPV4);
1295                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1296                          MLX5_L4_PROT_TYPE_TCP);
1297                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1298                          MLX5_HASH_ALL);
1299                 break;
1300
1301         case MLX5E_TT_IPV6_TCP:
1302                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1303                          MLX5_L3_PROT_TYPE_IPV6);
1304                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1305                          MLX5_L4_PROT_TYPE_TCP);
1306                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1307                          MLX5_HASH_ALL);
1308                 break;
1309
1310         case MLX5E_TT_IPV4_UDP:
1311                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1312                          MLX5_L3_PROT_TYPE_IPV4);
1313                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1314                          MLX5_L4_PROT_TYPE_UDP);
1315                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1316                          MLX5_HASH_ALL);
1317                 break;
1318
1319         case MLX5E_TT_IPV6_UDP:
1320                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1321                          MLX5_L3_PROT_TYPE_IPV6);
1322                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1323                          MLX5_L4_PROT_TYPE_UDP);
1324                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1325                          MLX5_HASH_ALL);
1326                 break;
1327
1328         case MLX5E_TT_IPV4:
1329                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1330                          MLX5_L3_PROT_TYPE_IPV4);
1331                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1332                          MLX5_HASH_IP);
1333                 break;
1334
1335         case MLX5E_TT_IPV6:
1336                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1337                          MLX5_L3_PROT_TYPE_IPV6);
1338                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1339                          MLX5_HASH_IP);
1340                 break;
1341         }
1342 }
1343
1344 static int mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
1345 {
1346         struct mlx5_core_dev *mdev = priv->mdev;
1347         u32 *in;
1348         void *tirc;
1349         int inlen;
1350         int err;
1351
1352         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1353         in = mlx5_vzalloc(inlen);
1354         if (!in)
1355                 return -ENOMEM;
1356
1357         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1358
1359         mlx5e_build_tir_ctx(priv, tirc, tt);
1360
1361         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1362
1363         kvfree(in);
1364
1365         return err;
1366 }
1367
1368 static void mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
1369 {
1370         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1371 }
1372
1373 static int mlx5e_open_tirs(struct mlx5e_priv *priv)
1374 {
1375         int err;
1376         int i;
1377
1378         for (i = 0; i < MLX5E_NUM_TT; i++) {
1379                 err = mlx5e_open_tir(priv, i);
1380                 if (err)
1381                         goto err_close_tirs;
1382         }
1383
1384         return 0;
1385
1386 err_close_tirs:
1387         for (i--; i >= 0; i--)
1388                 mlx5e_close_tir(priv, i);
1389
1390         return err;
1391 }
1392
1393 static void mlx5e_close_tirs(struct mlx5e_priv *priv)
1394 {
1395         int i;
1396
1397         for (i = 0; i < MLX5E_NUM_TT; i++)
1398                 mlx5e_close_tir(priv, i);
1399 }
1400
1401 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1402 {
1403         struct mlx5e_priv *priv = netdev_priv(netdev);
1404         struct mlx5_core_dev *mdev = priv->mdev;
1405         int hw_mtu;
1406         int err;
1407
1408         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1409         if (err)
1410                 return err;
1411
1412         mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1413
1414         if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1415                 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1416                             __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1417
1418         netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1419         return 0;
1420 }
1421
1422 int mlx5e_open_locked(struct net_device *netdev)
1423 {
1424         struct mlx5e_priv *priv = netdev_priv(netdev);
1425         int num_txqs;
1426         int err;
1427
1428         num_txqs = priv->params.num_channels * priv->params.num_tc;
1429         netif_set_real_num_tx_queues(netdev, num_txqs);
1430         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1431
1432         err = mlx5e_set_dev_port_mtu(netdev);
1433         if (err)
1434                 return err;
1435
1436         err = mlx5e_open_tises(priv);
1437         if (err) {
1438                 netdev_err(netdev, "%s: mlx5e_open_tises failed, %d\n",
1439                            __func__, err);
1440                 return err;
1441         }
1442
1443         err = mlx5e_open_channels(priv);
1444         if (err) {
1445                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1446                            __func__, err);
1447                 goto err_close_tises;
1448         }
1449
1450         err = mlx5e_open_rqt(priv);
1451         if (err) {
1452                 netdev_err(netdev, "%s: mlx5e_open_rqt failed, %d\n",
1453                            __func__, err);
1454                 goto err_close_channels;
1455         }
1456
1457         err = mlx5e_open_tirs(priv);
1458         if (err) {
1459                 netdev_err(netdev, "%s: mlx5e_open_tir failed, %d\n",
1460                            __func__, err);
1461                 goto err_close_rqls;
1462         }
1463
1464         err = mlx5e_open_flow_table(priv);
1465         if (err) {
1466                 netdev_err(netdev, "%s: mlx5e_open_flow_table failed, %d\n",
1467                            __func__, err);
1468                 goto err_close_tirs;
1469         }
1470
1471         err = mlx5e_add_all_vlan_rules(priv);
1472         if (err) {
1473                 netdev_err(netdev, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
1474                            __func__, err);
1475                 goto err_close_flow_table;
1476         }
1477
1478         mlx5e_init_eth_addr(priv);
1479
1480         set_bit(MLX5E_STATE_OPENED, &priv->state);
1481
1482         mlx5e_update_carrier(priv);
1483         mlx5e_set_rx_mode_core(priv);
1484
1485         schedule_delayed_work(&priv->update_stats_work, 0);
1486         return 0;
1487
1488 err_close_flow_table:
1489         mlx5e_close_flow_table(priv);
1490
1491 err_close_tirs:
1492         mlx5e_close_tirs(priv);
1493
1494 err_close_rqls:
1495         mlx5e_close_rqt(priv);
1496
1497 err_close_channels:
1498         mlx5e_close_channels(priv);
1499
1500 err_close_tises:
1501         mlx5e_close_tises(priv);
1502
1503         return err;
1504 }
1505
1506 static int mlx5e_open(struct net_device *netdev)
1507 {
1508         struct mlx5e_priv *priv = netdev_priv(netdev);
1509         int err;
1510
1511         mutex_lock(&priv->state_lock);
1512         err = mlx5e_open_locked(netdev);
1513         mutex_unlock(&priv->state_lock);
1514
1515         return err;
1516 }
1517
1518 int mlx5e_close_locked(struct net_device *netdev)
1519 {
1520         struct mlx5e_priv *priv = netdev_priv(netdev);
1521
1522         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1523
1524         mlx5e_set_rx_mode_core(priv);
1525         mlx5e_del_all_vlan_rules(priv);
1526         netif_carrier_off(priv->netdev);
1527         mlx5e_close_flow_table(priv);
1528         mlx5e_close_tirs(priv);
1529         mlx5e_close_rqt(priv);
1530         mlx5e_close_channels(priv);
1531         mlx5e_close_tises(priv);
1532
1533         return 0;
1534 }
1535
1536 static int mlx5e_close(struct net_device *netdev)
1537 {
1538         struct mlx5e_priv *priv = netdev_priv(netdev);
1539         int err;
1540
1541         mutex_lock(&priv->state_lock);
1542         err = mlx5e_close_locked(netdev);
1543         mutex_unlock(&priv->state_lock);
1544
1545         return err;
1546 }
1547
1548 int mlx5e_update_priv_params(struct mlx5e_priv *priv,
1549                              struct mlx5e_params *new_params)
1550 {
1551         int err = 0;
1552         int was_opened;
1553
1554         WARN_ON(!mutex_is_locked(&priv->state_lock));
1555
1556         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1557         if (was_opened)
1558                 mlx5e_close_locked(priv->netdev);
1559
1560         priv->params = *new_params;
1561
1562         if (was_opened)
1563                 err = mlx5e_open_locked(priv->netdev);
1564
1565         return err;
1566 }
1567
1568 static struct rtnl_link_stats64 *
1569 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1570 {
1571         struct mlx5e_priv *priv = netdev_priv(dev);
1572         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1573
1574         stats->rx_packets = vstats->rx_packets;
1575         stats->rx_bytes   = vstats->rx_bytes;
1576         stats->tx_packets = vstats->tx_packets;
1577         stats->tx_bytes   = vstats->tx_bytes;
1578         stats->multicast  = vstats->rx_multicast_packets +
1579                             vstats->tx_multicast_packets;
1580         stats->tx_errors  = vstats->tx_error_packets;
1581         stats->rx_errors  = vstats->rx_error_packets;
1582         stats->tx_dropped = vstats->tx_queue_dropped;
1583         stats->rx_crc_errors = 0;
1584         stats->rx_length_errors = 0;
1585
1586         return stats;
1587 }
1588
1589 static void mlx5e_set_rx_mode(struct net_device *dev)
1590 {
1591         struct mlx5e_priv *priv = netdev_priv(dev);
1592
1593         schedule_work(&priv->set_rx_mode_work);
1594 }
1595
1596 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1597 {
1598         struct mlx5e_priv *priv = netdev_priv(netdev);
1599         struct sockaddr *saddr = addr;
1600
1601         if (!is_valid_ether_addr(saddr->sa_data))
1602                 return -EADDRNOTAVAIL;
1603
1604         netif_addr_lock_bh(netdev);
1605         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1606         netif_addr_unlock_bh(netdev);
1607
1608         schedule_work(&priv->set_rx_mode_work);
1609
1610         return 0;
1611 }
1612
1613 static int mlx5e_set_features(struct net_device *netdev,
1614                               netdev_features_t features)
1615 {
1616         struct mlx5e_priv *priv = netdev_priv(netdev);
1617         netdev_features_t changes = features ^ netdev->features;
1618         struct mlx5e_params new_params;
1619         bool update_params = false;
1620
1621         mutex_lock(&priv->state_lock);
1622         new_params = priv->params;
1623
1624         if (changes & NETIF_F_LRO) {
1625                 new_params.lro_en = !!(features & NETIF_F_LRO);
1626                 update_params = true;
1627         }
1628
1629         if (update_params)
1630                 mlx5e_update_priv_params(priv, &new_params);
1631
1632         if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1633                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1634                         mlx5e_enable_vlan_filter(priv);
1635                 else
1636                         mlx5e_disable_vlan_filter(priv);
1637         }
1638
1639         mutex_unlock(&priv->state_lock);
1640
1641         return 0;
1642 }
1643
1644 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1645 {
1646         struct mlx5e_priv *priv = netdev_priv(netdev);
1647         struct mlx5_core_dev *mdev = priv->mdev;
1648         int max_mtu;
1649         int err;
1650
1651         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
1652
1653         if (new_mtu > max_mtu) {
1654                 netdev_err(netdev,
1655                            "%s: Bad MTU (%d) > (%d) Max\n",
1656                            __func__, new_mtu, max_mtu);
1657                 return -EINVAL;
1658         }
1659
1660         mutex_lock(&priv->state_lock);
1661         netdev->mtu = new_mtu;
1662         err = mlx5e_update_priv_params(priv, &priv->params);
1663         mutex_unlock(&priv->state_lock);
1664
1665         return err;
1666 }
1667
1668 static struct net_device_ops mlx5e_netdev_ops = {
1669         .ndo_open                = mlx5e_open,
1670         .ndo_stop                = mlx5e_close,
1671         .ndo_start_xmit          = mlx5e_xmit,
1672         .ndo_get_stats64         = mlx5e_get_stats,
1673         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
1674         .ndo_set_mac_address     = mlx5e_set_mac,
1675         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
1676         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
1677         .ndo_set_features        = mlx5e_set_features,
1678         .ndo_change_mtu          = mlx5e_change_mtu,
1679 };
1680
1681 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
1682 {
1683         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1684                 return -ENOTSUPP;
1685         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
1686             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
1687             !MLX5_CAP_ETH(mdev, csum_cap) ||
1688             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
1689             !MLX5_CAP_ETH(mdev, vlan_cap) ||
1690             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
1691             MLX5_CAP_FLOWTABLE(mdev,
1692                                flow_table_properties_nic_receive.max_ft_level)
1693                                < 3) {
1694                 mlx5_core_warn(mdev,
1695                                "Not creating net device, some required device capabilities are missing\n");
1696                 return -ENOTSUPP;
1697         }
1698         return 0;
1699 }
1700
1701 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
1702                                     struct net_device *netdev,
1703                                     int num_comp_vectors)
1704 {
1705         struct mlx5e_priv *priv = netdev_priv(netdev);
1706
1707         priv->params.log_sq_size           =
1708                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
1709         priv->params.log_rq_size           =
1710                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
1711         priv->params.rx_cq_moderation_usec =
1712                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
1713         priv->params.rx_cq_moderation_pkts =
1714                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
1715         priv->params.tx_cq_moderation_usec =
1716                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
1717         priv->params.tx_cq_moderation_pkts =
1718                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
1719         priv->params.min_rx_wqes           =
1720                 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
1721         priv->params.rx_hash_log_tbl_sz    =
1722                 (order_base_2(num_comp_vectors) >
1723                  MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
1724                 order_base_2(num_comp_vectors)           :
1725                 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
1726         priv->params.num_tc                = 1;
1727         priv->params.default_vlan_prio     = 0;
1728         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
1729
1730         priv->params.lro_en = false && !!MLX5_CAP_ETH(priv->mdev, lro_cap);
1731         priv->params.lro_wqe_sz            =
1732                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
1733
1734         priv->mdev                         = mdev;
1735         priv->netdev                       = netdev;
1736         priv->params.num_channels          = num_comp_vectors;
1737         priv->num_tc                       = priv->params.num_tc;
1738         priv->default_vlan_prio            = priv->params.default_vlan_prio;
1739
1740         spin_lock_init(&priv->async_events_spinlock);
1741         mutex_init(&priv->state_lock);
1742
1743         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
1744         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
1745         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
1746 }
1747
1748 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
1749 {
1750         struct mlx5e_priv *priv = netdev_priv(netdev);
1751
1752         mlx5_query_nic_vport_mac_address(priv->mdev, netdev->dev_addr);
1753 }
1754
1755 static void mlx5e_build_netdev(struct net_device *netdev)
1756 {
1757         struct mlx5e_priv *priv = netdev_priv(netdev);
1758         struct mlx5_core_dev *mdev = priv->mdev;
1759
1760         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
1761
1762         if (priv->num_tc > 1) {
1763                 mlx5e_netdev_ops.ndo_select_queue = mlx5e_select_queue;
1764         }
1765
1766         netdev->netdev_ops        = &mlx5e_netdev_ops;
1767         netdev->watchdog_timeo    = 15 * HZ;
1768
1769         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
1770
1771         netdev->vlan_features    |= NETIF_F_SG;
1772         netdev->vlan_features    |= NETIF_F_IP_CSUM;
1773         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
1774         netdev->vlan_features    |= NETIF_F_GRO;
1775         netdev->vlan_features    |= NETIF_F_TSO;
1776         netdev->vlan_features    |= NETIF_F_TSO6;
1777         netdev->vlan_features    |= NETIF_F_RXCSUM;
1778         netdev->vlan_features    |= NETIF_F_RXHASH;
1779
1780         if (!!MLX5_CAP_ETH(mdev, lro_cap))
1781                 netdev->vlan_features    |= NETIF_F_LRO;
1782
1783         netdev->hw_features       = netdev->vlan_features;
1784         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
1785         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
1786
1787         netdev->features          = netdev->hw_features;
1788         if (!priv->params.lro_en)
1789                 netdev->features  &= ~NETIF_F_LRO;
1790
1791         netdev->features         |= NETIF_F_HIGHDMA;
1792
1793         netdev->priv_flags       |= IFF_UNICAST_FLT;
1794
1795         mlx5e_set_netdev_dev_addr(netdev);
1796 }
1797
1798 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
1799                              struct mlx5_core_mr *mr)
1800 {
1801         struct mlx5_core_dev *mdev = priv->mdev;
1802         struct mlx5_create_mkey_mbox_in *in;
1803         int err;
1804
1805         in = mlx5_vzalloc(sizeof(*in));
1806         if (!in)
1807                 return -ENOMEM;
1808
1809         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
1810                         MLX5_PERM_LOCAL_READ  |
1811                         MLX5_ACCESS_MODE_PA;
1812         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
1813         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
1814
1815         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
1816                                     NULL);
1817
1818         kvfree(in);
1819
1820         return err;
1821 }
1822
1823 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
1824 {
1825         struct net_device *netdev;
1826         struct mlx5e_priv *priv;
1827         int ncv = mdev->priv.eq_table.num_comp_vectors;
1828         int err;
1829
1830         if (mlx5e_check_required_hca_cap(mdev))
1831                 return NULL;
1832
1833         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), ncv, ncv);
1834         if (!netdev) {
1835                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
1836                 return NULL;
1837         }
1838
1839         mlx5e_build_netdev_priv(mdev, netdev, ncv);
1840         mlx5e_build_netdev(netdev);
1841
1842         netif_carrier_off(netdev);
1843
1844         priv = netdev_priv(netdev);
1845
1846         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
1847         if (err) {
1848                 netdev_err(netdev, "%s: mlx5_alloc_map_uar failed, %d\n",
1849                            __func__, err);
1850                 goto err_free_netdev;
1851         }
1852
1853         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
1854         if (err) {
1855                 netdev_err(netdev, "%s: mlx5_core_alloc_pd failed, %d\n",
1856                            __func__, err);
1857                 goto err_unmap_free_uar;
1858         }
1859
1860         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
1861         if (err) {
1862                 netdev_err(netdev, "%s: mlx5_alloc_transport_domain failed, %d\n",
1863                            __func__, err);
1864                 goto err_dealloc_pd;
1865         }
1866
1867         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
1868         if (err) {
1869                 netdev_err(netdev, "%s: mlx5e_create_mkey failed, %d\n",
1870                            __func__, err);
1871                 goto err_dealloc_transport_domain;
1872         }
1873
1874         err = register_netdev(netdev);
1875         if (err) {
1876                 netdev_err(netdev, "%s: register_netdev failed, %d\n",
1877                            __func__, err);
1878                 goto err_destroy_mkey;
1879         }
1880
1881         mlx5e_enable_async_events(priv);
1882
1883         return priv;
1884
1885 err_destroy_mkey:
1886         mlx5_core_destroy_mkey(mdev, &priv->mr);
1887
1888 err_dealloc_transport_domain:
1889         mlx5_dealloc_transport_domain(mdev, priv->tdn);
1890
1891 err_dealloc_pd:
1892         mlx5_core_dealloc_pd(mdev, priv->pdn);
1893
1894 err_unmap_free_uar:
1895         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
1896
1897 err_free_netdev:
1898         free_netdev(netdev);
1899
1900         return NULL;
1901 }
1902
1903 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
1904 {
1905         struct mlx5e_priv *priv = vpriv;
1906         struct net_device *netdev = priv->netdev;
1907
1908         unregister_netdev(netdev);
1909         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
1910         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
1911         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
1912         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
1913         mlx5e_disable_async_events(priv);
1914         flush_scheduled_work();
1915         free_netdev(netdev);
1916 }
1917
1918 static void *mlx5e_get_netdev(void *vpriv)
1919 {
1920         struct mlx5e_priv *priv = vpriv;
1921
1922         return priv->netdev;
1923 }
1924
1925 static struct mlx5_interface mlx5e_interface = {
1926         .add       = mlx5e_create_netdev,
1927         .remove    = mlx5e_destroy_netdev,
1928         .event     = mlx5e_async_event,
1929         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
1930         .get_dev   = mlx5e_get_netdev,
1931 };
1932
1933 void mlx5e_init(void)
1934 {
1935         mlx5_register_interface(&mlx5e_interface);
1936 }
1937
1938 void mlx5e_cleanup(void)
1939 {
1940         mlx5_unregister_interface(&mlx5e_interface);
1941 }