drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 enum {
  43         MLX5_EN_QP_FLUSH_TIMEOUT_MS     = 5000,
  44         MLX5_EN_QP_FLUSH_MSLEEP_QUANT   = 20,
  45         MLX5_EN_QP_FLUSH_MAX_ITER       = MLX5_EN_QP_FLUSH_TIMEOUT_MS /
  46                                           MLX5_EN_QP_FLUSH_MSLEEP_QUANT,
  47 };
  48
  49 struct mlx5e_rq_param {
  50         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  51         struct mlx5_wq_param    wq;
  52         bool                    am_enabled;
  53 };
  54
  55 struct mlx5e_sq_param {
  56         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  57         struct mlx5_wq_param       wq;
  58         u16                        max_inline;
  59         u8                         min_inline_mode;
  60         bool                       icosq;
  61 };
  62
  63 struct mlx5e_cq_param {
  64         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  65         struct mlx5_wq_param       wq;
  66         u16                        eq_ix;
  67         u8                         cq_period_mode;
  68 };
  69
  70 struct mlx5e_channel_param {
  71         struct mlx5e_rq_param      rq;
  72         struct mlx5e_sq_param      sq;
  73         struct mlx5e_sq_param      icosq;
  74         struct mlx5e_cq_param      rx_cq;
  75         struct mlx5e_cq_param      tx_cq;
  76         struct mlx5e_cq_param      icosq_cq;
  77 };
  78
  79 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  80 {
  81         struct mlx5_core_dev *mdev = priv->mdev;
  82         u8 port_state;
  83
  84         port_state = mlx5_query_vport_state(mdev,
  85                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  86
  87         if (port_state == VPORT_STATE_UP) {
  88                 netdev_info(priv->netdev, "Link up\n");
  89                 netif_carrier_on(priv->netdev);
  90         } else {
  91                 netdev_info(priv->netdev, "Link down\n");
  92                 netif_carrier_off(priv->netdev);
  93         }
  94 }
  95
  96 static void mlx5e_update_carrier_work(struct work_struct *work)
  97 {
  98         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  99                                                update_carrier_work);
 100
 101         mutex_lock(&priv->state_lock);
 102         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 103                 mlx5e_update_carrier(priv);
 104         mutex_unlock(&priv->state_lock);
 105 }
 106
 107 static void mlx5e_tx_timeout_work(struct work_struct *work)
 108 {
 109         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 110                                                tx_timeout_work);
 111         int err;
 112
 113         rtnl_lock();
 114         mutex_lock(&priv->state_lock);
 115         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 116                 goto unlock;
 117         mlx5e_close_locked(priv->netdev);
 118         err = mlx5e_open_locked(priv->netdev);
 119         if (err)
 120                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 121                            err);
 122 unlock:
 123         mutex_unlock(&priv->state_lock);
 124         rtnl_unlock();
 125 }
 126
 127 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 128 {
 129         struct mlx5e_sw_stats *s = &priv->stats.sw;
 130         struct mlx5e_rq_stats *rq_stats;
 131         struct mlx5e_sq_stats *sq_stats;
 132         u64 tx_offload_none = 0;
 133         int i, j;
 134
 135         memset(s, 0, sizeof(*s));
 136         for (i = 0; i < priv->params.num_channels; i++) {
 137                 rq_stats = &priv->channel[i]->rq.stats;
 138
 139                 s->rx_packets   += rq_stats->packets;
 140                 s->rx_bytes     += rq_stats->bytes;
 141                 s->rx_lro_packets += rq_stats->lro_packets;
 142                 s->rx_lro_bytes += rq_stats->lro_bytes;
 143                 s->rx_csum_none += rq_stats->csum_none;
 144                 s->rx_csum_complete += rq_stats->csum_complete;
 145                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 146                 s->rx_wqe_err   += rq_stats->wqe_err;
 147                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 148                 s->rx_mpwqe_frag   += rq_stats->mpwqe_frag;
 149                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 150                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 151                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 152
 153                 for (j = 0; j < priv->params.num_tc; j++) {
 154                         sq_stats = &priv->channel[i]->sq[j].stats;
 155
 156                         s->tx_packets           += sq_stats->packets;
 157                         s->tx_bytes             += sq_stats->bytes;
 158                         s->tx_tso_packets       += sq_stats->tso_packets;
 159                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 160                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 161                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 162                         s->tx_queue_stopped     += sq_stats->stopped;
 163                         s->tx_queue_wake        += sq_stats->wake;
 164                         s->tx_queue_dropped     += sq_stats->dropped;
 165                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 166                         tx_offload_none         += sq_stats->csum_none;
 167                 }
 168         }
 169
 170         /* Update calculated offload counters */
 171         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
 172         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 173
 174         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 175                                 priv->stats.pport.phy_counters,
 176                                 counter_set.phys_layer_cntrs.link_down_events);
 177 }
 178
 179 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 180 {
 181         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 182         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 183         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 184         struct mlx5_core_dev *mdev = priv->mdev;
 185
 186         memset(in, 0, sizeof(in));
 187
 188         MLX5_SET(query_vport_counter_in, in, opcode,
 189                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 190         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 191         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 192
 193         memset(out, 0, outlen);
 194
 195         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 196 }
 197
 198 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 199 {
 200         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 201         struct mlx5_core_dev *mdev = priv->mdev;
 202         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 203         int prio;
 204         void *out;
 205         u32 *in;
 206
 207         in = mlx5_vzalloc(sz);
 208         if (!in)
 209                 goto free_out;
 210
 211         MLX5_SET(ppcnt_reg, in, local_port, 1);
 212
 213         out = pstats->IEEE_802_3_counters;
 214         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 215         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 216
 217         out = pstats->RFC_2863_counters;
 218         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 219         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 220
 221         out = pstats->RFC_2819_counters;
 222         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 223         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 224
 225         out = pstats->phy_counters;
 226         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 227         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 228
 229         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 230         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 231                 out = pstats->per_prio_counters[prio];
 232                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 233                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 234                                      MLX5_REG_PPCNT, 0, 0);
 235         }
 236
 237 free_out:
 238         kvfree(in);
 239 }
 240
 241 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 242 {
 243         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 244
 245         if (!priv->q_counter)
 246                 return;
 247
 248         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 249                                       &qcnt->rx_out_of_buffer);
 250 }
 251
 252 void mlx5e_update_stats(struct mlx5e_priv *priv)
 253 {
 254         mlx5e_update_q_counter(priv);
 255         mlx5e_update_vport_counters(priv);
 256         mlx5e_update_pport_counters(priv);
 257         mlx5e_update_sw_counters(priv);
 258 }
 259
 260 void mlx5e_update_stats_work(struct work_struct *work)
 261 {
 262         struct delayed_work *dwork = to_delayed_work(work);
 263         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 264                                                update_stats_work);
 265         mutex_lock(&priv->state_lock);
 266         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 267                 priv->profile->update_stats(priv);
 268                 queue_delayed_work(priv->wq, dwork,
 269                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 270         }
 271         mutex_unlock(&priv->state_lock);
 272 }
 273
 274 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 275                               enum mlx5_dev_event event, unsigned long param)
 276 {
 277         struct mlx5e_priv *priv = vpriv;
 278
 279         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 280                 return;
 281
 282         switch (event) {
 283         case MLX5_DEV_EVENT_PORT_UP:
 284         case MLX5_DEV_EVENT_PORT_DOWN:
 285                 queue_work(priv->wq, &priv->update_carrier_work);
 286                 break;
 287
 288         default:
 289                 break;
 290         }
 291 }
 292
 293 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 294 {
 295         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 296 }
 297
 298 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 299 {
 300         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 301         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 302 }
 303
 304 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 305 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 306
 307 static int mlx5e_create_rq(struct mlx5e_channel *c,
 308                            struct mlx5e_rq_param *param,
 309                            struct mlx5e_rq *rq)
 310 {
 311         struct mlx5e_priv *priv = c->priv;
 312         struct mlx5_core_dev *mdev = priv->mdev;
 313         void *rqc = param->rqc;
 314         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 315         u32 byte_count;
 316         int wq_sz;
 317         int err;
 318         int i;
 319
 320         param->wq.db_numa_node = cpu_to_node(c->cpu);
 321
 322         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 323                                 &rq->wq_ctrl);
 324         if (err)
 325                 return err;
 326
 327         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 328
 329         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 330
 331         switch (priv->params.rq_wq_type) {
 332         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 333                 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
 334                                             GFP_KERNEL, cpu_to_node(c->cpu));
 335                 if (!rq->wqe_info) {
 336                         err = -ENOMEM;
 337                         goto err_rq_wq_destroy;
 338                 }
 339                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 340                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 341                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 342
 343                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 344                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 345                 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 346                 byte_count = rq->wqe_sz;
 347                 break;
 348         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 349                 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 350                                        cpu_to_node(c->cpu));
 351                 if (!rq->skb) {
 352                         err = -ENOMEM;
 353                         goto err_rq_wq_destroy;
 354                 }
 355                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 356                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 357                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 358
 359                 rq->wqe_sz = (priv->params.lro_en) ?
 360                                 priv->params.lro_wqe_sz :
 361                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 362                 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
 363                 byte_count = rq->wqe_sz;
 364                 byte_count |= MLX5_HW_START_PADDING;
 365         }
 366
 367         for (i = 0; i < wq_sz; i++) {
 368                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 369
 370                 wqe->data.byte_count = cpu_to_be32(byte_count);
 371         }
 372
 373         INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
 374         rq->am.mode = priv->params.rx_cq_period_mode;
 375
 376         rq->wq_type = priv->params.rq_wq_type;
 377         rq->pdev    = c->pdev;
 378         rq->netdev  = c->netdev;
 379         rq->tstamp  = &priv->tstamp;
 380         rq->channel = c;
 381         rq->ix      = c->ix;
 382         rq->priv    = c->priv;
 383         rq->mkey_be = c->mkey_be;
 384         rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 385
 386         return 0;
 387
 388 err_rq_wq_destroy:
 389         mlx5_wq_destroy(&rq->wq_ctrl);
 390
 391         return err;
 392 }
 393
 394 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 395 {
 396         switch (rq->wq_type) {
 397         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 398                 kfree(rq->wqe_info);
 399                 break;
 400         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 401                 kfree(rq->skb);
 402         }
 403
 404         mlx5_wq_destroy(&rq->wq_ctrl);
 405 }
 406
 407 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 408 {
 409         struct mlx5e_priv *priv = rq->priv;
 410         struct mlx5_core_dev *mdev = priv->mdev;
 411
 412         void *in;
 413         void *rqc;
 414         void *wq;
 415         int inlen;
 416         int err;
 417
 418         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 419                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 420         in = mlx5_vzalloc(inlen);
 421         if (!in)
 422                 return -ENOMEM;
 423
 424         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 425         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 426
 427         memcpy(rqc, param->rqc, sizeof(param->rqc));
 428
 429         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 430         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 431         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 432         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 433         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 434                                                 MLX5_ADAPTER_PAGE_SHIFT);
 435         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 436
 437         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 438                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 439
 440         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 441
 442         kvfree(in);
 443
 444         return err;
 445 }
 446
 447 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 448                                  int next_state)
 449 {
 450         struct mlx5e_channel *c = rq->channel;
 451         struct mlx5e_priv *priv = c->priv;
 452         struct mlx5_core_dev *mdev = priv->mdev;
 453
 454         void *in;
 455         void *rqc;
 456         int inlen;
 457         int err;
 458
 459         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 460         in = mlx5_vzalloc(inlen);
 461         if (!in)
 462                 return -ENOMEM;
 463
 464         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 465
 466         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 467         MLX5_SET(rqc, rqc, state, next_state);
 468
 469         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 470
 471         kvfree(in);
 472
 473         return err;
 474 }
 475
 476 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 477 {
 478         struct mlx5e_channel *c = rq->channel;
 479         struct mlx5e_priv *priv = c->priv;
 480         struct mlx5_core_dev *mdev = priv->mdev;
 481
 482         void *in;
 483         void *rqc;
 484         int inlen;
 485         int err;
 486
 487         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 488         in = mlx5_vzalloc(inlen);
 489         if (!in)
 490                 return -ENOMEM;
 491
 492         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 493
 494         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 495         MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
 496         MLX5_SET(rqc, rqc, vsd, vsd);
 497         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 498
 499         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 500
 501         kvfree(in);
 502
 503         return err;
 504 }
 505
 506 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 507 {
 508         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 509 }
 510
 511 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 512 {
 513         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 514         struct mlx5e_channel *c = rq->channel;
 515         struct mlx5e_priv *priv = c->priv;
 516         struct mlx5_wq_ll *wq = &rq->wq;
 517
 518         while (time_before(jiffies, exp_time)) {
 519                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 520                         return 0;
 521
 522                 msleep(20);
 523         }
 524
 525         return -ETIMEDOUT;
 526 }
 527
 528 static int mlx5e_open_rq(struct mlx5e_channel *c,
 529                          struct mlx5e_rq_param *param,
 530                          struct mlx5e_rq *rq)
 531 {
 532         struct mlx5e_sq *sq = &c->icosq;
 533         u16 pi = sq->pc & sq->wq.sz_m1;
 534         int err;
 535
 536         err = mlx5e_create_rq(c, param, rq);
 537         if (err)
 538                 return err;
 539
 540         err = mlx5e_enable_rq(rq, param);
 541         if (err)
 542                 goto err_destroy_rq;
 543
 544         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 545         if (err)
 546                 goto err_disable_rq;
 547
 548         if (param->am_enabled)
 549                 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 550
 551         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 552
 553         sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
 554         sq->ico_wqe_info[pi].num_wqebbs = 1;
 555         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 556
 557         return 0;
 558
 559 err_disable_rq:
 560         mlx5e_disable_rq(rq);
 561 err_destroy_rq:
 562         mlx5e_destroy_rq(rq);
 563
 564         return err;
 565 }
 566
 567 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 568 {
 569         int tout = 0;
 570         int err;
 571
 572         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 573         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 574
 575         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 576         while (!mlx5_wq_ll_is_empty(&rq->wq) && !err &&
 577                tout++ < MLX5_EN_QP_FLUSH_MAX_ITER)
 578                 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
 579
 580         if (err || tout == MLX5_EN_QP_FLUSH_MAX_ITER)
 581                 set_bit(MLX5E_RQ_STATE_FLUSH_TIMEOUT, &rq->state);
 582
 583         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 584         napi_synchronize(&rq->channel->napi);
 585
 586         cancel_work_sync(&rq->am.work);
 587
 588         mlx5e_disable_rq(rq);
 589         mlx5e_free_rx_descs(rq);
 590         mlx5e_destroy_rq(rq);
 591 }
 592
 593 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 594 {
 595         kfree(sq->wqe_info);
 596         kfree(sq->dma_fifo);
 597         kfree(sq->skb);
 598 }
 599
 600 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 601 {
 602         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 603         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 604
 605         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 606         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 607                                     numa);
 608         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 609                                     numa);
 610
 611         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 612                 mlx5e_free_sq_db(sq);
 613                 return -ENOMEM;
 614         }
 615
 616         sq->dma_fifo_mask = df_sz - 1;
 617
 618         return 0;
 619 }
 620
 621 static int mlx5e_create_sq(struct mlx5e_channel *c,
 622                            int tc,
 623                            struct mlx5e_sq_param *param,
 624                            struct mlx5e_sq *sq)
 625 {
 626         struct mlx5e_priv *priv = c->priv;
 627         struct mlx5_core_dev *mdev = priv->mdev;
 628
 629         void *sqc = param->sqc;
 630         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 631         int err;
 632
 633         err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
 634         if (err)
 635                 return err;
 636
 637         param->wq.db_numa_node = cpu_to_node(c->cpu);
 638
 639         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 640                                  &sq->wq_ctrl);
 641         if (err)
 642                 goto err_unmap_free_uar;
 643
 644         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 645         if (sq->uar.bf_map) {
 646                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 647                 sq->uar_map = sq->uar.bf_map;
 648         } else {
 649                 sq->uar_map = sq->uar.map;
 650         }
 651         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 652         sq->max_inline  = param->max_inline;
 653         sq->min_inline_mode =
 654                 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
 655                 param->min_inline_mode : 0;
 656
 657         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 658         if (err)
 659                 goto err_sq_wq_destroy;
 660
 661         if (param->icosq) {
 662                 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 663
 664                 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
 665                                                 wq_sz,
 666                                                 GFP_KERNEL,
 667                                                 cpu_to_node(c->cpu));
 668                 if (!sq->ico_wqe_info) {
 669                         err = -ENOMEM;
 670                         goto err_free_sq_db;
 671                 }
 672         } else {
 673                 int txq_ix;
 674
 675                 txq_ix = c->ix + tc * priv->params.num_channels;
 676                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 677                 priv->txq_to_sq_map[txq_ix] = sq;
 678         }
 679
 680         sq->pdev      = c->pdev;
 681         sq->tstamp    = &priv->tstamp;
 682         sq->mkey_be   = c->mkey_be;
 683         sq->channel   = c;
 684         sq->tc        = tc;
 685         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 686         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 687
 688         return 0;
 689
 690 err_free_sq_db:
 691         mlx5e_free_sq_db(sq);
 692
 693 err_sq_wq_destroy:
 694         mlx5_wq_destroy(&sq->wq_ctrl);
 695
 696 err_unmap_free_uar:
 697         mlx5_unmap_free_uar(mdev, &sq->uar);
 698
 699         return err;
 700 }
 701
 702 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 703 {
 704         struct mlx5e_channel *c = sq->channel;
 705         struct mlx5e_priv *priv = c->priv;
 706
 707         kfree(sq->ico_wqe_info);
 708         mlx5e_free_sq_db(sq);
 709         mlx5_wq_destroy(&sq->wq_ctrl);
 710         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 711 }
 712
 713 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 714 {
 715         struct mlx5e_channel *c = sq->channel;
 716         struct mlx5e_priv *priv = c->priv;
 717         struct mlx5_core_dev *mdev = priv->mdev;
 718
 719         void *in;
 720         void *sqc;
 721         void *wq;
 722         int inlen;
 723         int err;
 724
 725         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 726                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 727         in = mlx5_vzalloc(inlen);
 728         if (!in)
 729                 return -ENOMEM;
 730
 731         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 732         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 733
 734         memcpy(sqc, param->sqc, sizeof(param->sqc));
 735
 736         MLX5_SET(sqc,  sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
 737         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
 738         MLX5_SET(sqc,  sqc, min_wqe_inline_mode, sq->min_inline_mode);
 739         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 740         MLX5_SET(sqc,  sqc, tis_lst_sz,         param->icosq ? 0 : 1);
 741         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 742
 743         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 744         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 745         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 746                                           MLX5_ADAPTER_PAGE_SHIFT);
 747         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 748
 749         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 750                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 751
 752         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 753
 754         kvfree(in);
 755
 756         return err;
 757 }
 758
 759 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
 760                            int next_state, bool update_rl, int rl_index)
 761 {
 762         struct mlx5e_channel *c = sq->channel;
 763         struct mlx5e_priv *priv = c->priv;
 764         struct mlx5_core_dev *mdev = priv->mdev;
 765
 766         void *in;
 767         void *sqc;
 768         int inlen;
 769         int err;
 770
 771         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 772         in = mlx5_vzalloc(inlen);
 773         if (!in)
 774                 return -ENOMEM;
 775
 776         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 777
 778         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 779         MLX5_SET(sqc, sqc, state, next_state);
 780         if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
 781                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
 782                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, rl_index);
 783         }
 784
 785         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 786
 787         kvfree(in);
 788
 789         return err;
 790 }
 791
 792 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 793 {
 794         struct mlx5e_channel *c = sq->channel;
 795         struct mlx5e_priv *priv = c->priv;
 796         struct mlx5_core_dev *mdev = priv->mdev;
 797
 798         mlx5_core_destroy_sq(mdev, sq->sqn);
 799         if (sq->rate_limit)
 800                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
 801 }
 802
 803 static int mlx5e_open_sq(struct mlx5e_channel *c,
 804                          int tc,
 805                          struct mlx5e_sq_param *param,
 806                          struct mlx5e_sq *sq)
 807 {
 808         int err;
 809
 810         err = mlx5e_create_sq(c, tc, param, sq);
 811         if (err)
 812                 return err;
 813
 814         err = mlx5e_enable_sq(sq, param);
 815         if (err)
 816                 goto err_destroy_sq;
 817
 818         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
 819                               false, 0);
 820         if (err)
 821                 goto err_disable_sq;
 822
 823         if (sq->txq) {
 824                 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 825                 netdev_tx_reset_queue(sq->txq);
 826                 netif_tx_start_queue(sq->txq);
 827         }
 828
 829         return 0;
 830
 831 err_disable_sq:
 832         mlx5e_disable_sq(sq);
 833 err_destroy_sq:
 834         mlx5e_destroy_sq(sq);
 835
 836         return err;
 837 }
 838
 839 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 840 {
 841         __netif_tx_lock_bh(txq);
 842         netif_tx_stop_queue(txq);
 843         __netif_tx_unlock_bh(txq);
 844 }
 845
 846 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 847 {
 848         int tout = 0;
 849         int err;
 850
 851         if (sq->txq) {
 852                 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 853                 /* prevent netif_tx_wake_queue */
 854                 napi_synchronize(&sq->channel->napi);
 855                 netif_tx_disable_queue(sq->txq);
 856
 857                 /* ensure hw is notified of all pending wqes */
 858                 if (mlx5e_sq_has_room_for(sq, 1))
 859                         mlx5e_send_nop(sq, true);
 860
 861                 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
 862                                       MLX5_SQC_STATE_ERR, false, 0);
 863                 if (err)
 864                         set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
 865         }
 866
 867         /* wait till sq is empty, unless a TX timeout occurred on this SQ */
 868         while (sq->cc != sq->pc &&
 869                !test_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state)) {
 870                 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
 871                 if (tout++ > MLX5_EN_QP_FLUSH_MAX_ITER)
 872                         set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
 873         }
 874
 875         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 876         napi_synchronize(&sq->channel->napi);
 877
 878         mlx5e_free_tx_descs(sq);
 879         mlx5e_disable_sq(sq);
 880         mlx5e_destroy_sq(sq);
 881 }
 882
 883 static int mlx5e_create_cq(struct mlx5e_channel *c,
 884                            struct mlx5e_cq_param *param,
 885                            struct mlx5e_cq *cq)
 886 {
 887         struct mlx5e_priv *priv = c->priv;
 888         struct mlx5_core_dev *mdev = priv->mdev;
 889         struct mlx5_core_cq *mcq = &cq->mcq;
 890         int eqn_not_used;
 891         unsigned int irqn;
 892         int err;
 893         u32 i;
 894
 895         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 896         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 897         param->eq_ix   = c->ix;
 898
 899         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 900                                &cq->wq_ctrl);
 901         if (err)
 902                 return err;
 903
 904         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 905
 906         cq->napi        = &c->napi;
 907
 908         mcq->cqe_sz     = 64;
 909         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 910         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 911         *mcq->set_ci_db = 0;
 912         *mcq->arm_db    = 0;
 913         mcq->vector     = param->eq_ix;
 914         mcq->comp       = mlx5e_completion_event;
 915         mcq->event      = mlx5e_cq_error_event;
 916         mcq->irqn       = irqn;
 917         mcq->uar        = &mdev->mlx5e_res.cq_uar;
 918
 919         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 920                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 921
 922                 cqe->op_own = 0xf1;
 923         }
 924
 925         cq->channel = c;
 926         cq->priv = priv;
 927
 928         return 0;
 929 }
 930
 931 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 932 {
 933         mlx5_wq_destroy(&cq->wq_ctrl);
 934 }
 935
 936 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 937 {
 938         struct mlx5e_priv *priv = cq->priv;
 939         struct mlx5_core_dev *mdev = priv->mdev;
 940         struct mlx5_core_cq *mcq = &cq->mcq;
 941
 942         void *in;
 943         void *cqc;
 944         int inlen;
 945         unsigned int irqn_not_used;
 946         int eqn;
 947         int err;
 948
 949         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 950                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 951         in = mlx5_vzalloc(inlen);
 952         if (!in)
 953                 return -ENOMEM;
 954
 955         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 956
 957         memcpy(cqc, param->cqc, sizeof(param->cqc));
 958
 959         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 960                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 961
 962         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 963
 964         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
 965         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 966         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 967         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 968                                             MLX5_ADAPTER_PAGE_SHIFT);
 969         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 970
 971         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 972
 973         kvfree(in);
 974
 975         if (err)
 976                 return err;
 977
 978         mlx5e_cq_arm(cq);
 979
 980         return 0;
 981 }
 982
 983 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 984 {
 985         struct mlx5e_priv *priv = cq->priv;
 986         struct mlx5_core_dev *mdev = priv->mdev;
 987
 988         mlx5_core_destroy_cq(mdev, &cq->mcq);
 989 }
 990
 991 static int mlx5e_open_cq(struct mlx5e_channel *c,
 992                          struct mlx5e_cq_param *param,
 993                          struct mlx5e_cq *cq,
 994                          struct mlx5e_cq_moder moderation)
 995 {
 996         int err;
 997         struct mlx5e_priv *priv = c->priv;
 998         struct mlx5_core_dev *mdev = priv->mdev;
 999
1000         err = mlx5e_create_cq(c, param, cq);
1001         if (err)
1002                 return err;
1003
1004         err = mlx5e_enable_cq(cq, param);
1005         if (err)
1006                 goto err_destroy_cq;
1007
1008         if (MLX5_CAP_GEN(mdev, cq_moderation))
1009                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1010                                                moderation.usec,
1011                                                moderation.pkts);
1012         return 0;
1013
1014 err_destroy_cq:
1015         mlx5e_destroy_cq(cq);
1016
1017         return err;
1018 }
1019
1020 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1021 {
1022         mlx5e_disable_cq(cq);
1023         mlx5e_destroy_cq(cq);
1024 }
1025
1026 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1027 {
1028         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1029 }
1030
1031 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1032                              struct mlx5e_channel_param *cparam)
1033 {
1034         struct mlx5e_priv *priv = c->priv;
1035         int err;
1036         int tc;
1037
1038         for (tc = 0; tc < c->num_tc; tc++) {
1039                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1040                                     priv->params.tx_cq_moderation);
1041                 if (err)
1042                         goto err_close_tx_cqs;
1043         }
1044
1045         return 0;
1046
1047 err_close_tx_cqs:
1048         for (tc--; tc >= 0; tc--)
1049                 mlx5e_close_cq(&c->sq[tc].cq);
1050
1051         return err;
1052 }
1053
1054 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1055 {
1056         int tc;
1057
1058         for (tc = 0; tc < c->num_tc; tc++)
1059                 mlx5e_close_cq(&c->sq[tc].cq);
1060 }
1061
1062 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1063                           struct mlx5e_channel_param *cparam)
1064 {
1065         int err;
1066         int tc;
1067
1068         for (tc = 0; tc < c->num_tc; tc++) {
1069                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1070                 if (err)
1071                         goto err_close_sqs;
1072         }
1073
1074         return 0;
1075
1076 err_close_sqs:
1077         for (tc--; tc >= 0; tc--)
1078                 mlx5e_close_sq(&c->sq[tc]);
1079
1080         return err;
1081 }
1082
1083 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1084 {
1085         int tc;
1086
1087         for (tc = 0; tc < c->num_tc; tc++)
1088                 mlx5e_close_sq(&c->sq[tc]);
1089 }
1090
1091 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1092 {
1093         int i;
1094
1095         for (i = 0; i < priv->profile->max_tc; i++)
1096                 priv->channeltc_to_txq_map[ix][i] =
1097                         ix + i * priv->params.num_channels;
1098 }
1099
1100 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1101                                 struct mlx5e_sq *sq, u32 rate)
1102 {
1103         struct mlx5e_priv *priv = netdev_priv(dev);
1104         struct mlx5_core_dev *mdev = priv->mdev;
1105         u16 rl_index = 0;
1106         int err;
1107
1108         if (rate == sq->rate_limit)
1109                 /* nothing to do */
1110                 return 0;
1111
1112         if (sq->rate_limit)
1113                 /* remove current rl index to free space to next ones */
1114                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1115
1116         sq->rate_limit = 0;
1117
1118         if (rate) {
1119                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1120                 if (err) {
1121                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1122                                    rate, err);
1123                         return err;
1124                 }
1125         }
1126
1127         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1128                               MLX5_SQC_STATE_RDY, true, rl_index);
1129         if (err) {
1130                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1131                            rate, err);
1132                 /* remove the rate from the table */
1133                 if (rate)
1134                         mlx5_rl_remove_rate(mdev, rate);
1135                 return err;
1136         }
1137
1138         sq->rate_limit = rate;
1139         return 0;
1140 }
1141
1142 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1143 {
1144         struct mlx5e_priv *priv = netdev_priv(dev);
1145         struct mlx5_core_dev *mdev = priv->mdev;
1146         struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1147         int err = 0;
1148
1149         if (!mlx5_rl_is_supported(mdev)) {
1150                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1151                 return -EINVAL;
1152         }
1153
1154         /* rate is given in Mb/sec, HW config is in Kb/sec */
1155         rate = rate << 10;
1156
1157         /* Check whether rate in valid range, 0 is always valid */
1158         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1159                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1160                 return -ERANGE;
1161         }
1162
1163         mutex_lock(&priv->state_lock);
1164         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1165                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1166         if (!err)
1167                 priv->tx_rates[index] = rate;
1168         mutex_unlock(&priv->state_lock);
1169
1170         return err;
1171 }
1172
1173 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1174                               struct mlx5e_channel_param *cparam,
1175                               struct mlx5e_channel **cp)
1176 {
1177         struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1178         struct net_device *netdev = priv->netdev;
1179         struct mlx5e_cq_moder rx_cq_profile;
1180         int cpu = mlx5e_get_cpu(priv, ix);
1181         struct mlx5e_channel *c;
1182         struct mlx5e_sq *sq;
1183         int err;
1184         int i;
1185
1186         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1187         if (!c)
1188                 return -ENOMEM;
1189
1190         c->priv     = priv;
1191         c->ix       = ix;
1192         c->cpu      = cpu;
1193         c->pdev     = &priv->mdev->pdev->dev;
1194         c->netdev   = priv->netdev;
1195         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1196         c->num_tc   = priv->params.num_tc;
1197
1198         if (priv->params.rx_am_enabled)
1199                 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1200         else
1201                 rx_cq_profile = priv->params.rx_cq_moderation;
1202
1203         mlx5e_build_channeltc_to_txq_map(priv, ix);
1204
1205         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1206
1207         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1208         if (err)
1209                 goto err_napi_del;
1210
1211         err = mlx5e_open_tx_cqs(c, cparam);
1212         if (err)
1213                 goto err_close_icosq_cq;
1214
1215         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1216                             rx_cq_profile);
1217         if (err)
1218                 goto err_close_tx_cqs;
1219
1220         napi_enable(&c->napi);
1221
1222         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1223         if (err)
1224                 goto err_disable_napi;
1225
1226         err = mlx5e_open_sqs(c, cparam);
1227         if (err)
1228                 goto err_close_icosq;
1229
1230         for (i = 0; i < priv->params.num_tc; i++) {
1231                 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1232
1233                 if (priv->tx_rates[txq_ix]) {
1234                         sq = priv->txq_to_sq_map[txq_ix];
1235                         mlx5e_set_sq_maxrate(priv->netdev, sq,
1236                                              priv->tx_rates[txq_ix]);
1237                 }
1238         }
1239
1240         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1241         if (err)
1242                 goto err_close_sqs;
1243
1244         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1245         *cp = c;
1246
1247         return 0;
1248
1249 err_close_sqs:
1250         mlx5e_close_sqs(c);
1251
1252 err_close_icosq:
1253         mlx5e_close_sq(&c->icosq);
1254
1255 err_disable_napi:
1256         napi_disable(&c->napi);
1257         mlx5e_close_cq(&c->rq.cq);
1258
1259 err_close_tx_cqs:
1260         mlx5e_close_tx_cqs(c);
1261
1262 err_close_icosq_cq:
1263         mlx5e_close_cq(&c->icosq.cq);
1264
1265 err_napi_del:
1266         netif_napi_del(&c->napi);
1267         napi_hash_del(&c->napi);
1268         kfree(c);
1269
1270         return err;
1271 }
1272
1273 static void mlx5e_close_channel(struct mlx5e_channel *c)
1274 {
1275         mlx5e_close_rq(&c->rq);
1276         mlx5e_close_sqs(c);
1277         mlx5e_close_sq(&c->icosq);
1278         napi_disable(&c->napi);
1279         mlx5e_close_cq(&c->rq.cq);
1280         mlx5e_close_tx_cqs(c);
1281         mlx5e_close_cq(&c->icosq.cq);
1282         netif_napi_del(&c->napi);
1283
1284         napi_hash_del(&c->napi);
1285         synchronize_rcu();
1286
1287         kfree(c);
1288 }
1289
1290 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1291                                  struct mlx5e_rq_param *param)
1292 {
1293         void *rqc = param->rqc;
1294         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1295
1296         switch (priv->params.rq_wq_type) {
1297         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1298                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1299                          priv->params.mpwqe_log_num_strides - 9);
1300                 MLX5_SET(wq, wq, log_wqe_stride_size,
1301                          priv->params.mpwqe_log_stride_sz - 6);
1302                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1303                 break;
1304         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1305                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1306         }
1307
1308         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1309         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1310         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1311         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1312         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1313
1314         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1315         param->wq.linear = 1;
1316
1317         param->am_enabled = priv->params.rx_am_enabled;
1318 }
1319
1320 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1321 {
1322         void *rqc = param->rqc;
1323         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1324
1325         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1326         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1327 }
1328
1329 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1330                                         struct mlx5e_sq_param *param)
1331 {
1332         void *sqc = param->sqc;
1333         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1334
1335         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1336         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1337
1338         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1339 }
1340
1341 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1342                                  struct mlx5e_sq_param *param)
1343 {
1344         void *sqc = param->sqc;
1345         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1346
1347         mlx5e_build_sq_param_common(priv, param);
1348         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1349
1350         param->max_inline = priv->params.tx_max_inline;
1351         param->min_inline_mode = priv->params.tx_min_inline_mode;
1352 }
1353
1354 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1355                                         struct mlx5e_cq_param *param)
1356 {
1357         void *cqc = param->cqc;
1358
1359         MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
1360 }
1361
1362 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1363                                     struct mlx5e_cq_param *param)
1364 {
1365         void *cqc = param->cqc;
1366         u8 log_cq_size;
1367
1368         switch (priv->params.rq_wq_type) {
1369         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1370                 log_cq_size = priv->params.log_rq_size +
1371                         priv->params.mpwqe_log_num_strides;
1372                 break;
1373         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1374                 log_cq_size = priv->params.log_rq_size;
1375         }
1376
1377         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1378         if (priv->params.rx_cqe_compress) {
1379                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1380                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1381         }
1382
1383         mlx5e_build_common_cq_param(priv, param);
1384
1385         param->cq_period_mode = priv->params.rx_cq_period_mode;
1386 }
1387
1388 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1389                                     struct mlx5e_cq_param *param)
1390 {
1391         void *cqc = param->cqc;
1392
1393         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1394
1395         mlx5e_build_common_cq_param(priv, param);
1396
1397         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1398 }
1399
1400 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1401                                      struct mlx5e_cq_param *param,
1402                                      u8 log_wq_size)
1403 {
1404         void *cqc = param->cqc;
1405
1406         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1407
1408         mlx5e_build_common_cq_param(priv, param);
1409
1410         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1411 }
1412
1413 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1414                                     struct mlx5e_sq_param *param,
1415                                     u8 log_wq_size)
1416 {
1417         void *sqc = param->sqc;
1418         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1419
1420         mlx5e_build_sq_param_common(priv, param);
1421
1422         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1423         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1424
1425         param->icosq = true;
1426 }
1427
1428 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1429 {
1430         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1431
1432         mlx5e_build_rq_param(priv, &cparam->rq);
1433         mlx5e_build_sq_param(priv, &cparam->sq);
1434         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1435         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1436         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1437         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1438 }
1439
1440 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1441 {
1442         struct mlx5e_channel_param *cparam;
1443         int nch = priv->params.num_channels;
1444         int err = -ENOMEM;
1445         int i;
1446         int j;
1447
1448         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1449                                 GFP_KERNEL);
1450
1451         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1452                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1453
1454         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1455
1456         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1457                 goto err_free_txq_to_sq_map;
1458
1459         mlx5e_build_channel_param(priv, cparam);
1460
1461         for (i = 0; i < nch; i++) {
1462                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1463                 if (err)
1464                         goto err_close_channels;
1465         }
1466
1467         for (j = 0; j < nch; j++) {
1468                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1469                 if (err)
1470                         goto err_close_channels;
1471         }
1472
1473         /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1474          * polling for inactive tx queues.
1475          */
1476         netif_tx_start_all_queues(priv->netdev);
1477
1478         kfree(cparam);
1479         return 0;
1480
1481 err_close_channels:
1482         for (i--; i >= 0; i--)
1483                 mlx5e_close_channel(priv->channel[i]);
1484
1485 err_free_txq_to_sq_map:
1486         kfree(priv->txq_to_sq_map);
1487         kfree(priv->channel);
1488         kfree(cparam);
1489
1490         return err;
1491 }
1492
1493 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1494 {
1495         int i;
1496
1497         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1498          * polling for inactive tx queues.
1499          */
1500         netif_tx_stop_all_queues(priv->netdev);
1501         netif_tx_disable(priv->netdev);
1502
1503         for (i = 0; i < priv->params.num_channels; i++)
1504                 mlx5e_close_channel(priv->channel[i]);
1505
1506         kfree(priv->txq_to_sq_map);
1507         kfree(priv->channel);
1508 }
1509
1510 static int mlx5e_rx_hash_fn(int hfunc)
1511 {
1512         return (hfunc == ETH_RSS_HASH_TOP) ?
1513                MLX5_RX_HASH_FN_TOEPLITZ :
1514                MLX5_RX_HASH_FN_INVERTED_XOR8;
1515 }
1516
1517 static int mlx5e_bits_invert(unsigned long a, int size)
1518 {
1519         int inv = 0;
1520         int i;
1521
1522         for (i = 0; i < size; i++)
1523                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1524
1525         return inv;
1526 }
1527
1528 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1529 {
1530         int i;
1531
1532         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1533                 int ix = i;
1534                 u32 rqn;
1535
1536                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1537                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1538
1539                 ix = priv->params.indirection_rqt[ix];
1540                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1541                                 priv->channel[ix]->rq.rqn :
1542                                 priv->drop_rq.rqn;
1543                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1544         }
1545 }
1546
1547 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1548                                       int ix)
1549 {
1550         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1551                         priv->channel[ix]->rq.rqn :
1552                         priv->drop_rq.rqn;
1553
1554         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1555 }
1556
1557 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1558                             int ix, struct mlx5e_rqt *rqt)
1559 {
1560         struct mlx5_core_dev *mdev = priv->mdev;
1561         void *rqtc;
1562         int inlen;
1563         int err;
1564         u32 *in;
1565
1566         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1567         in = mlx5_vzalloc(inlen);
1568         if (!in)
1569                 return -ENOMEM;
1570
1571         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1572
1573         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1574         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1575
1576         if (sz > 1) /* RSS */
1577                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1578         else
1579                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1580
1581         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1582         if (!err)
1583                 rqt->enabled = true;
1584
1585         kvfree(in);
1586         return err;
1587 }
1588
1589 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1590 {
1591         rqt->enabled = false;
1592         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1593 }
1594
1595 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1596 {
1597         struct mlx5e_rqt *rqt = &priv->indir_rqt;
1598
1599         return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1600 }
1601
1602 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1603 {
1604         struct mlx5e_rqt *rqt;
1605         int err;
1606         int ix;
1607
1608         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1609                 rqt = &priv->direct_tir[ix].rqt;
1610                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1611                 if (err)
1612                         goto err_destroy_rqts;
1613         }
1614
1615         return 0;
1616
1617 err_destroy_rqts:
1618         for (ix--; ix >= 0; ix--)
1619                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1620
1621         return err;
1622 }
1623
1624 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1625 {
1626         struct mlx5_core_dev *mdev = priv->mdev;
1627         void *rqtc;
1628         int inlen;
1629         u32 *in;
1630         int err;
1631
1632         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1633         in = mlx5_vzalloc(inlen);
1634         if (!in)
1635                 return -ENOMEM;
1636
1637         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1638
1639         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1640         if (sz > 1) /* RSS */
1641                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1642         else
1643                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1644
1645         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1646
1647         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1648
1649         kvfree(in);
1650
1651         return err;
1652 }
1653
1654 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1655 {
1656         u32 rqtn;
1657         int ix;
1658
1659         if (priv->indir_rqt.enabled) {
1660                 rqtn = priv->indir_rqt.rqtn;
1661                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1662         }
1663
1664         for (ix = 0; ix < priv->params.num_channels; ix++) {
1665                 if (!priv->direct_tir[ix].rqt.enabled)
1666                         continue;
1667                 rqtn = priv->direct_tir[ix].rqt.rqtn;
1668                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1669         }
1670 }
1671
1672 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1673 {
1674         if (!priv->params.lro_en)
1675                 return;
1676
1677 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1678
1679         MLX5_SET(tirc, tirc, lro_enable_mask,
1680                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1681                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1682         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1683                  (priv->params.lro_wqe_sz -
1684                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1685         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1686                  MLX5_CAP_ETH(priv->mdev,
1687                               lro_timer_supported_periods[2]));
1688 }
1689
1690 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1691 {
1692         MLX5_SET(tirc, tirc, rx_hash_fn,
1693                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1694         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1695                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1696                                              rx_hash_toeplitz_key);
1697                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1698                                                rx_hash_toeplitz_key);
1699
1700                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1701                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1702         }
1703 }
1704
1705 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1706 {
1707         struct mlx5_core_dev *mdev = priv->mdev;
1708
1709         void *in;
1710         void *tirc;
1711         int inlen;
1712         int err;
1713         int tt;
1714         int ix;
1715
1716         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1717         in = mlx5_vzalloc(inlen);
1718         if (!in)
1719                 return -ENOMEM;
1720
1721         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1722         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1723
1724         mlx5e_build_tir_ctx_lro(tirc, priv);
1725
1726         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1727                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1728                                            inlen);
1729                 if (err)
1730                         goto free_in;
1731         }
1732
1733         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1734                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1735                                            in, inlen);
1736                 if (err)
1737                         goto free_in;
1738         }
1739
1740 free_in:
1741         kvfree(in);
1742
1743         return err;
1744 }
1745
1746 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1747 {
1748         struct mlx5_core_dev *mdev = priv->mdev;
1749         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1750         int err;
1751
1752         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1753         if (err)
1754                 return err;
1755
1756         /* Update vport context MTU */
1757         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1758         return 0;
1759 }
1760
1761 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1762 {
1763         struct mlx5_core_dev *mdev = priv->mdev;
1764         u16 hw_mtu = 0;
1765         int err;
1766
1767         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1768         if (err || !hw_mtu) /* fallback to port oper mtu */
1769                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1770
1771         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1772 }
1773
1774 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1775 {
1776         struct mlx5e_priv *priv = netdev_priv(netdev);
1777         u16 mtu;
1778         int err;
1779
1780         err = mlx5e_set_mtu(priv, netdev->mtu);
1781         if (err)
1782                 return err;
1783
1784         mlx5e_query_mtu(priv, &mtu);
1785         if (mtu != netdev->mtu)
1786                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1787                             __func__, mtu, netdev->mtu);
1788
1789         netdev->mtu = mtu;
1790         return 0;
1791 }
1792
1793 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1794 {
1795         struct mlx5e_priv *priv = netdev_priv(netdev);
1796         int nch = priv->params.num_channels;
1797         int ntc = priv->params.num_tc;
1798         int tc;
1799
1800         netdev_reset_tc(netdev);
1801
1802         if (ntc == 1)
1803                 return;
1804
1805         netdev_set_num_tc(netdev, ntc);
1806
1807         /* Map netdev TCs to offset 0
1808          * We have our own UP to TXQ mapping for QoS
1809          */
1810         for (tc = 0; tc < ntc; tc++)
1811                 netdev_set_tc_queue(netdev, tc, nch, 0);
1812 }
1813
1814 int mlx5e_open_locked(struct net_device *netdev)
1815 {
1816         struct mlx5e_priv *priv = netdev_priv(netdev);
1817         struct mlx5_core_dev *mdev = priv->mdev;
1818         int num_txqs;
1819         int err;
1820
1821         set_bit(MLX5E_STATE_OPENED, &priv->state);
1822
1823         mlx5e_netdev_set_tcs(netdev);
1824
1825         num_txqs = priv->params.num_channels * priv->params.num_tc;
1826         netif_set_real_num_tx_queues(netdev, num_txqs);
1827         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1828
1829         err = mlx5e_open_channels(priv);
1830         if (err) {
1831                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1832                            __func__, err);
1833                 goto err_clear_state_opened_flag;
1834         }
1835
1836         err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
1837         if (err) {
1838                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1839                            __func__, err);
1840                 goto err_close_channels;
1841         }
1842
1843         mlx5e_redirect_rqts(priv);
1844         mlx5e_update_carrier(priv);
1845         mlx5e_timestamp_init(priv);
1846 #ifdef CONFIG_RFS_ACCEL
1847         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1848 #endif
1849         if (priv->profile->update_stats)
1850                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1851
1852         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
1853                 err = mlx5e_add_sqs_fwd_rules(priv);
1854                 if (err)
1855                         goto err_close_channels;
1856         }
1857         return 0;
1858
1859 err_close_channels:
1860         mlx5e_close_channels(priv);
1861 err_clear_state_opened_flag:
1862         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1863         return err;
1864 }
1865
1866 int mlx5e_open(struct net_device *netdev)
1867 {
1868         struct mlx5e_priv *priv = netdev_priv(netdev);
1869         int err;
1870
1871         mutex_lock(&priv->state_lock);
1872         err = mlx5e_open_locked(netdev);
1873         mutex_unlock(&priv->state_lock);
1874
1875         return err;
1876 }
1877
1878 int mlx5e_close_locked(struct net_device *netdev)
1879 {
1880         struct mlx5e_priv *priv = netdev_priv(netdev);
1881         struct mlx5_core_dev *mdev = priv->mdev;
1882
1883         /* May already be CLOSED in case a previous configuration operation
1884          * (e.g RX/TX queue size change) that involves close&open failed.
1885          */
1886         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1887                 return 0;
1888
1889         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1890
1891         if (MLX5_CAP_GEN(mdev, vport_group_manager))
1892                 mlx5e_remove_sqs_fwd_rules(priv);
1893
1894         mlx5e_timestamp_cleanup(priv);
1895         netif_carrier_off(priv->netdev);
1896         mlx5e_redirect_rqts(priv);
1897         mlx5e_close_channels(priv);
1898
1899         return 0;
1900 }
1901
1902 int mlx5e_close(struct net_device *netdev)
1903 {
1904         struct mlx5e_priv *priv = netdev_priv(netdev);
1905         int err;
1906
1907         mutex_lock(&priv->state_lock);
1908         err = mlx5e_close_locked(netdev);
1909         mutex_unlock(&priv->state_lock);
1910
1911         return err;
1912 }
1913
1914 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1915                                 struct mlx5e_rq *rq,
1916                                 struct mlx5e_rq_param *param)
1917 {
1918         struct mlx5_core_dev *mdev = priv->mdev;
1919         void *rqc = param->rqc;
1920         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1921         int err;
1922
1923         param->wq.db_numa_node = param->wq.buf_numa_node;
1924
1925         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1926                                 &rq->wq_ctrl);
1927         if (err)
1928                 return err;
1929
1930         rq->priv = priv;
1931
1932         return 0;
1933 }
1934
1935 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1936                                 struct mlx5e_cq *cq,
1937                                 struct mlx5e_cq_param *param)
1938 {
1939         struct mlx5_core_dev *mdev = priv->mdev;
1940         struct mlx5_core_cq *mcq = &cq->mcq;
1941         int eqn_not_used;
1942         unsigned int irqn;
1943         int err;
1944
1945         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1946                                &cq->wq_ctrl);
1947         if (err)
1948                 return err;
1949
1950         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1951
1952         mcq->cqe_sz     = 64;
1953         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1954         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1955         *mcq->set_ci_db = 0;
1956         *mcq->arm_db    = 0;
1957         mcq->vector     = param->eq_ix;
1958         mcq->comp       = mlx5e_completion_event;
1959         mcq->event      = mlx5e_cq_error_event;
1960         mcq->irqn       = irqn;
1961         mcq->uar        = &mdev->mlx5e_res.cq_uar;
1962
1963         cq->priv = priv;
1964
1965         return 0;
1966 }
1967
1968 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1969 {
1970         struct mlx5e_cq_param cq_param;
1971         struct mlx5e_rq_param rq_param;
1972         struct mlx5e_rq *rq = &priv->drop_rq;
1973         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1974         int err;
1975
1976         memset(&cq_param, 0, sizeof(cq_param));
1977         memset(&rq_param, 0, sizeof(rq_param));
1978         mlx5e_build_drop_rq_param(&rq_param);
1979
1980         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1981         if (err)
1982                 return err;
1983
1984         err = mlx5e_enable_cq(cq, &cq_param);
1985         if (err)
1986                 goto err_destroy_cq;
1987
1988         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1989         if (err)
1990                 goto err_disable_cq;
1991
1992         err = mlx5e_enable_rq(rq, &rq_param);
1993         if (err)
1994                 goto err_destroy_rq;
1995
1996         return 0;
1997
1998 err_destroy_rq:
1999         mlx5e_destroy_rq(&priv->drop_rq);
2000
2001 err_disable_cq:
2002         mlx5e_disable_cq(&priv->drop_rq.cq);
2003
2004 err_destroy_cq:
2005         mlx5e_destroy_cq(&priv->drop_rq.cq);
2006
2007         return err;
2008 }
2009
2010 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2011 {
2012         mlx5e_disable_rq(&priv->drop_rq);
2013         mlx5e_destroy_rq(&priv->drop_rq);
2014         mlx5e_disable_cq(&priv->drop_rq.cq);
2015         mlx5e_destroy_cq(&priv->drop_rq.cq);
2016 }
2017
2018 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2019 {
2020         struct mlx5_core_dev *mdev = priv->mdev;
2021         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2022         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2023
2024         memset(in, 0, sizeof(in));
2025
2026         MLX5_SET(tisc, tisc, prio, tc << 1);
2027         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2028
2029         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2030 }
2031
2032 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2033 {
2034         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2035 }
2036
2037 int mlx5e_create_tises(struct mlx5e_priv *priv)
2038 {
2039         int err;
2040         int tc;
2041
2042         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2043                 err = mlx5e_create_tis(priv, tc);
2044                 if (err)
2045                         goto err_close_tises;
2046         }
2047
2048         return 0;
2049
2050 err_close_tises:
2051         for (tc--; tc >= 0; tc--)
2052                 mlx5e_destroy_tis(priv, tc);
2053
2054         return err;
2055 }
2056
2057 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2058 {
2059         int tc;
2060
2061         for (tc = 0; tc < priv->profile->max_tc; tc++)
2062                 mlx5e_destroy_tis(priv, tc);
2063 }
2064
2065 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2066                                       enum mlx5e_traffic_types tt)
2067 {
2068         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2069
2070         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2071
2072 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2073                                  MLX5_HASH_FIELD_SEL_DST_IP)
2074
2075 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2076                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2077                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2078                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2079
2080 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2081                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2082                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2083
2084         mlx5e_build_tir_ctx_lro(tirc, priv);
2085
2086         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2087         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2088         mlx5e_build_tir_ctx_hash(tirc, priv);
2089
2090         switch (tt) {
2091         case MLX5E_TT_IPV4_TCP:
2092                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2093                          MLX5_L3_PROT_TYPE_IPV4);
2094                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2095                          MLX5_L4_PROT_TYPE_TCP);
2096                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2097                          MLX5_HASH_IP_L4PORTS);
2098                 break;
2099
2100         case MLX5E_TT_IPV6_TCP:
2101                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2102                          MLX5_L3_PROT_TYPE_IPV6);
2103                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2104                          MLX5_L4_PROT_TYPE_TCP);
2105                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2106                          MLX5_HASH_IP_L4PORTS);
2107                 break;
2108
2109         case MLX5E_TT_IPV4_UDP:
2110                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2111                          MLX5_L3_PROT_TYPE_IPV4);
2112                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2113                          MLX5_L4_PROT_TYPE_UDP);
2114                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2115                          MLX5_HASH_IP_L4PORTS);
2116                 break;
2117
2118         case MLX5E_TT_IPV6_UDP:
2119                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2120                          MLX5_L3_PROT_TYPE_IPV6);
2121                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2122                          MLX5_L4_PROT_TYPE_UDP);
2123                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2124                          MLX5_HASH_IP_L4PORTS);
2125                 break;
2126
2127         case MLX5E_TT_IPV4_IPSEC_AH:
2128                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2129                          MLX5_L3_PROT_TYPE_IPV4);
2130                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2131                          MLX5_HASH_IP_IPSEC_SPI);
2132                 break;
2133
2134         case MLX5E_TT_IPV6_IPSEC_AH:
2135                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2136                          MLX5_L3_PROT_TYPE_IPV6);
2137                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2138                          MLX5_HASH_IP_IPSEC_SPI);
2139                 break;
2140
2141         case MLX5E_TT_IPV4_IPSEC_ESP:
2142                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2143                          MLX5_L3_PROT_TYPE_IPV4);
2144                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2145                          MLX5_HASH_IP_IPSEC_SPI);
2146                 break;
2147
2148         case MLX5E_TT_IPV6_IPSEC_ESP:
2149                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2150                          MLX5_L3_PROT_TYPE_IPV6);
2151                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2152                          MLX5_HASH_IP_IPSEC_SPI);
2153                 break;
2154
2155         case MLX5E_TT_IPV4:
2156                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2157                          MLX5_L3_PROT_TYPE_IPV4);
2158                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2159                          MLX5_HASH_IP);
2160                 break;
2161
2162         case MLX5E_TT_IPV6:
2163                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2164                          MLX5_L3_PROT_TYPE_IPV6);
2165                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2166                          MLX5_HASH_IP);
2167                 break;
2168         default:
2169                 WARN_ONCE(true,
2170                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2171         }
2172 }
2173
2174 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2175                                        u32 rqtn)
2176 {
2177         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2178
2179         mlx5e_build_tir_ctx_lro(tirc, priv);
2180
2181         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2182         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2183         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2184 }
2185
2186 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2187 {
2188         struct mlx5e_tir *tir;
2189         void *tirc;
2190         int inlen;
2191         int err;
2192         u32 *in;
2193         int tt;
2194
2195         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2196         in = mlx5_vzalloc(inlen);
2197         if (!in)
2198                 return -ENOMEM;
2199
2200         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2201                 memset(in, 0, inlen);
2202                 tir = &priv->indir_tir[tt];
2203                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2204                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2205                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2206                 if (err)
2207                         goto err_destroy_tirs;
2208         }
2209
2210         kvfree(in);
2211
2212         return 0;
2213
2214 err_destroy_tirs:
2215         for (tt--; tt >= 0; tt--)
2216                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2217
2218         kvfree(in);
2219
2220         return err;
2221 }
2222
2223 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2224 {
2225         int nch = priv->profile->max_nch(priv->mdev);
2226         struct mlx5e_tir *tir;
2227         void *tirc;
2228         int inlen;
2229         int err;
2230         u32 *in;
2231         int ix;
2232
2233         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2234         in = mlx5_vzalloc(inlen);
2235         if (!in)
2236                 return -ENOMEM;
2237
2238         for (ix = 0; ix < nch; ix++) {
2239                 memset(in, 0, inlen);
2240                 tir = &priv->direct_tir[ix];
2241                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2242                 mlx5e_build_direct_tir_ctx(priv, tirc,
2243                                            priv->direct_tir[ix].rqt.rqtn);
2244                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2245                 if (err)
2246                         goto err_destroy_ch_tirs;
2247         }
2248
2249         kvfree(in);
2250
2251         return 0;
2252
2253 err_destroy_ch_tirs:
2254         for (ix--; ix >= 0; ix--)
2255                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2256
2257         kvfree(in);
2258
2259         return err;
2260 }
2261
2262 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2263 {
2264         int i;
2265
2266         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2267                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2268 }
2269
2270 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2271 {
2272         int nch = priv->profile->max_nch(priv->mdev);
2273         int i;
2274
2275         for (i = 0; i < nch; i++)
2276                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2277 }
2278
2279 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2280 {
2281         int err = 0;
2282         int i;
2283
2284         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2285                 return 0;
2286
2287         for (i = 0; i < priv->params.num_channels; i++) {
2288                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2289                 if (err)
2290                         return err;
2291         }
2292
2293         return 0;
2294 }
2295
2296 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2297 {
2298         struct mlx5e_priv *priv = netdev_priv(netdev);
2299         bool was_opened;
2300         int err = 0;
2301
2302         if (tc && tc != MLX5E_MAX_NUM_TC)
2303                 return -EINVAL;
2304
2305         mutex_lock(&priv->state_lock);
2306
2307         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2308         if (was_opened)
2309                 mlx5e_close_locked(priv->netdev);
2310
2311         priv->params.num_tc = tc ? tc : 1;
2312
2313         if (was_opened)
2314                 err = mlx5e_open_locked(priv->netdev);
2315
2316         mutex_unlock(&priv->state_lock);
2317
2318         return err;
2319 }
2320
2321 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2322                               __be16 proto, struct tc_to_netdev *tc)
2323 {
2324         struct mlx5e_priv *priv = netdev_priv(dev);
2325
2326         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2327                 goto mqprio;
2328
2329         switch (tc->type) {
2330         case TC_SETUP_CLSFLOWER:
2331                 switch (tc->cls_flower->command) {
2332                 case TC_CLSFLOWER_REPLACE:
2333                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2334                 case TC_CLSFLOWER_DESTROY:
2335                         return mlx5e_delete_flower(priv, tc->cls_flower);
2336                 case TC_CLSFLOWER_STATS:
2337                         return mlx5e_stats_flower(priv, tc->cls_flower);
2338                 }
2339         default:
2340                 return -EOPNOTSUPP;
2341         }
2342
2343 mqprio:
2344         if (tc->type != TC_SETUP_MQPRIO)
2345                 return -EINVAL;
2346
2347         return mlx5e_setup_tc(dev, tc->tc);
2348 }
2349
2350 struct rtnl_link_stats64 *
2351 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2352 {
2353         struct mlx5e_priv *priv = netdev_priv(dev);
2354         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2355         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2356         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2357
2358         stats->rx_packets = sstats->rx_packets;
2359         stats->rx_bytes   = sstats->rx_bytes;
2360         stats->tx_packets = sstats->tx_packets;
2361         stats->tx_bytes   = sstats->tx_bytes;
2362
2363         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2364         stats->tx_dropped = sstats->tx_queue_dropped;
2365
2366         stats->rx_length_errors =
2367                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2368                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2369                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2370         stats->rx_crc_errors =
2371                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2372         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2373         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2374         stats->tx_carrier_errors =
2375                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2376         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2377                            stats->rx_frame_errors;
2378         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2379
2380         /* vport multicast also counts packets that are dropped due to steering
2381          * or rx out of buffer
2382          */
2383         stats->multicast =
2384                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2385
2386         return stats;
2387 }
2388
2389 static void mlx5e_set_rx_mode(struct net_device *dev)
2390 {
2391         struct mlx5e_priv *priv = netdev_priv(dev);
2392
2393         queue_work(priv->wq, &priv->set_rx_mode_work);
2394 }
2395
2396 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2397 {
2398         struct mlx5e_priv *priv = netdev_priv(netdev);
2399         struct sockaddr *saddr = addr;
2400
2401         if (!is_valid_ether_addr(saddr->sa_data))
2402                 return -EADDRNOTAVAIL;
2403
2404         netif_addr_lock_bh(netdev);
2405         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2406         netif_addr_unlock_bh(netdev);
2407
2408         queue_work(priv->wq, &priv->set_rx_mode_work);
2409
2410         return 0;
2411 }
2412
2413 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2414         do {                                            \
2415                 if (enable)                             \
2416                         netdev->features |= feature;    \
2417                 else                                    \
2418                         netdev->features &= ~feature;   \
2419         } while (0)
2420
2421 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2422
2423 static int set_feature_lro(struct net_device *netdev, bool enable)
2424 {
2425         struct mlx5e_priv *priv = netdev_priv(netdev);
2426         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2427         int err;
2428
2429         mutex_lock(&priv->state_lock);
2430
2431         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2432                 mlx5e_close_locked(priv->netdev);
2433
2434         priv->params.lro_en = enable;
2435         err = mlx5e_modify_tirs_lro(priv);
2436         if (err) {
2437                 netdev_err(netdev, "lro modify failed, %d\n", err);
2438                 priv->params.lro_en = !enable;
2439         }
2440
2441         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2442                 mlx5e_open_locked(priv->netdev);
2443
2444         mutex_unlock(&priv->state_lock);
2445
2446         return err;
2447 }
2448
2449 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2450 {
2451         struct mlx5e_priv *priv = netdev_priv(netdev);
2452
2453         if (enable)
2454                 mlx5e_enable_vlan_filter(priv);
2455         else
2456                 mlx5e_disable_vlan_filter(priv);
2457
2458         return 0;
2459 }
2460
2461 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2462 {
2463         struct mlx5e_priv *priv = netdev_priv(netdev);
2464
2465         if (!enable && mlx5e_tc_num_filters(priv)) {
2466                 netdev_err(netdev,
2467                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2468                 return -EINVAL;
2469         }
2470
2471         return 0;
2472 }
2473
2474 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2475 {
2476         struct mlx5e_priv *priv = netdev_priv(netdev);
2477         struct mlx5_core_dev *mdev = priv->mdev;
2478
2479         return mlx5_set_port_fcs(mdev, !enable);
2480 }
2481
2482 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2483 {
2484         struct mlx5e_priv *priv = netdev_priv(netdev);
2485         int err;
2486
2487         mutex_lock(&priv->state_lock);
2488
2489         priv->params.vlan_strip_disable = !enable;
2490         err = mlx5e_modify_rqs_vsd(priv, !enable);
2491         if (err)
2492                 priv->params.vlan_strip_disable = enable;
2493
2494         mutex_unlock(&priv->state_lock);
2495
2496         return err;
2497 }
2498
2499 #ifdef CONFIG_RFS_ACCEL
2500 static int set_feature_arfs(struct net_device *netdev, bool enable)
2501 {
2502         struct mlx5e_priv *priv = netdev_priv(netdev);
2503         int err;
2504
2505         if (enable)
2506                 err = mlx5e_arfs_enable(priv);
2507         else
2508                 err = mlx5e_arfs_disable(priv);
2509
2510         return err;
2511 }
2512 #endif
2513
2514 static int mlx5e_handle_feature(struct net_device *netdev,
2515                                 netdev_features_t wanted_features,
2516                                 netdev_features_t feature,
2517                                 mlx5e_feature_handler feature_handler)
2518 {
2519         netdev_features_t changes = wanted_features ^ netdev->features;
2520         bool enable = !!(wanted_features & feature);
2521         int err;
2522
2523         if (!(changes & feature))
2524                 return 0;
2525
2526         err = feature_handler(netdev, enable);
2527         if (err) {
2528                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2529                            enable ? "Enable" : "Disable", feature, err);
2530                 return err;
2531         }
2532
2533         MLX5E_SET_FEATURE(netdev, feature, enable);
2534         return 0;
2535 }
2536
2537 static int mlx5e_set_features(struct net_device *netdev,
2538                               netdev_features_t features)
2539 {
2540         int err;
2541
2542         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2543                                     set_feature_lro);
2544         err |= mlx5e_handle_feature(netdev, features,
2545                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2546                                     set_feature_vlan_filter);
2547         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2548                                     set_feature_tc_num_filters);
2549         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2550                                     set_feature_rx_all);
2551         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2552                                     set_feature_rx_vlan);
2553 #ifdef CONFIG_RFS_ACCEL
2554         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2555                                     set_feature_arfs);
2556 #endif
2557
2558         return err ? -EINVAL : 0;
2559 }
2560
2561 #define MXL5_HW_MIN_MTU 64
2562 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2563
2564 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2565 {
2566         struct mlx5e_priv *priv = netdev_priv(netdev);
2567         struct mlx5_core_dev *mdev = priv->mdev;
2568         bool was_opened;
2569         u16 max_mtu;
2570         u16 min_mtu;
2571         int err = 0;
2572
2573         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2574
2575         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2576         min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2577
2578         if (new_mtu > max_mtu || new_mtu < min_mtu) {
2579                 netdev_err(netdev,
2580                            "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2581                            __func__, new_mtu, min_mtu, max_mtu);
2582                 return -EINVAL;
2583         }
2584
2585         mutex_lock(&priv->state_lock);
2586
2587         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2588         if (was_opened)
2589                 mlx5e_close_locked(netdev);
2590
2591         netdev->mtu = new_mtu;
2592         mlx5e_set_dev_port_mtu(netdev);
2593
2594         if (was_opened)
2595                 err = mlx5e_open_locked(netdev);
2596
2597         mutex_unlock(&priv->state_lock);
2598
2599         return err;
2600 }
2601
2602 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2603 {
2604         switch (cmd) {
2605         case SIOCSHWTSTAMP:
2606                 return mlx5e_hwstamp_set(dev, ifr);
2607         case SIOCGHWTSTAMP:
2608                 return mlx5e_hwstamp_get(dev, ifr);
2609         default:
2610                 return -EOPNOTSUPP;
2611         }
2612 }
2613
2614 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2615 {
2616         struct mlx5e_priv *priv = netdev_priv(dev);
2617         struct mlx5_core_dev *mdev = priv->mdev;
2618
2619         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2620 }
2621
2622 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2623 {
2624         struct mlx5e_priv *priv = netdev_priv(dev);
2625         struct mlx5_core_dev *mdev = priv->mdev;
2626
2627         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2628                                            vlan, qos);
2629 }
2630
2631 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2632 {
2633         struct mlx5e_priv *priv = netdev_priv(dev);
2634         struct mlx5_core_dev *mdev = priv->mdev;
2635
2636         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2637 }
2638
2639 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2640 {
2641         struct mlx5e_priv *priv = netdev_priv(dev);
2642         struct mlx5_core_dev *mdev = priv->mdev;
2643
2644         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2645 }
2646 static int mlx5_vport_link2ifla(u8 esw_link)
2647 {
2648         switch (esw_link) {
2649         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2650                 return IFLA_VF_LINK_STATE_DISABLE;
2651         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2652                 return IFLA_VF_LINK_STATE_ENABLE;
2653         }
2654         return IFLA_VF_LINK_STATE_AUTO;
2655 }
2656
2657 static int mlx5_ifla_link2vport(u8 ifla_link)
2658 {
2659         switch (ifla_link) {
2660         case IFLA_VF_LINK_STATE_DISABLE:
2661                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2662         case IFLA_VF_LINK_STATE_ENABLE:
2663                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2664         }
2665         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2666 }
2667
2668 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2669                                    int link_state)
2670 {
2671         struct mlx5e_priv *priv = netdev_priv(dev);
2672         struct mlx5_core_dev *mdev = priv->mdev;
2673
2674         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2675                                             mlx5_ifla_link2vport(link_state));
2676 }
2677
2678 static int mlx5e_get_vf_config(struct net_device *dev,
2679                                int vf, struct ifla_vf_info *ivi)
2680 {
2681         struct mlx5e_priv *priv = netdev_priv(dev);
2682         struct mlx5_core_dev *mdev = priv->mdev;
2683         int err;
2684
2685         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2686         if (err)
2687                 return err;
2688         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2689         return 0;
2690 }
2691
2692 static int mlx5e_get_vf_stats(struct net_device *dev,
2693                               int vf, struct ifla_vf_stats *vf_stats)
2694 {
2695         struct mlx5e_priv *priv = netdev_priv(dev);
2696         struct mlx5_core_dev *mdev = priv->mdev;
2697
2698         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2699                                             vf_stats);
2700 }
2701
2702 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2703                                  struct udp_tunnel_info *ti)
2704 {
2705         struct mlx5e_priv *priv = netdev_priv(netdev);
2706
2707         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2708                 return;
2709
2710         if (!mlx5e_vxlan_allowed(priv->mdev))
2711                 return;
2712
2713         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
2714 }
2715
2716 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2717                                  struct udp_tunnel_info *ti)
2718 {
2719         struct mlx5e_priv *priv = netdev_priv(netdev);
2720
2721         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2722                 return;
2723
2724         if (!mlx5e_vxlan_allowed(priv->mdev))
2725                 return;
2726
2727         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
2728 }
2729
2730 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2731                                                     struct sk_buff *skb,
2732                                                     netdev_features_t features)
2733 {
2734         struct udphdr *udph;
2735         u16 proto;
2736         u16 port = 0;
2737
2738         switch (vlan_get_protocol(skb)) {
2739         case htons(ETH_P_IP):
2740                 proto = ip_hdr(skb)->protocol;
2741                 break;
2742         case htons(ETH_P_IPV6):
2743                 proto = ipv6_hdr(skb)->nexthdr;
2744                 break;
2745         default:
2746                 goto out;
2747         }
2748
2749         if (proto == IPPROTO_UDP) {
2750                 udph = udp_hdr(skb);
2751                 port = be16_to_cpu(udph->dest);
2752         }
2753
2754         /* Verify if UDP port is being offloaded by HW */
2755         if (port && mlx5e_vxlan_lookup_port(priv, port))
2756                 return features;
2757
2758 out:
2759         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2760         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2761 }
2762
2763 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2764                                               struct net_device *netdev,
2765                                               netdev_features_t features)
2766 {
2767         struct mlx5e_priv *priv = netdev_priv(netdev);
2768
2769         features = vlan_features_check(skb, features);
2770         features = vxlan_features_check(skb, features);
2771
2772         /* Validate if the tunneled packet is being offloaded by HW */
2773         if (skb->encapsulation &&
2774             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2775                 return mlx5e_vxlan_features_check(priv, skb, features);
2776
2777         return features;
2778 }
2779
2780 static void mlx5e_tx_timeout(struct net_device *dev)
2781 {
2782         struct mlx5e_priv *priv = netdev_priv(dev);
2783         bool sched_work = false;
2784         int i;
2785
2786         netdev_err(dev, "TX timeout detected\n");
2787
2788         for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
2789                 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
2790
2791                 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
2792                         continue;
2793                 sched_work = true;
2794                 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
2795                 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
2796                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
2797         }
2798
2799         if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
2800                 schedule_work(&priv->tx_timeout_work);
2801 }
2802
2803 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2804         .ndo_open                = mlx5e_open,
2805         .ndo_stop                = mlx5e_close,
2806         .ndo_start_xmit          = mlx5e_xmit,
2807         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2808         .ndo_select_queue        = mlx5e_select_queue,
2809         .ndo_get_stats64         = mlx5e_get_stats,
2810         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2811         .ndo_set_mac_address     = mlx5e_set_mac,
2812         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2813         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2814         .ndo_set_features        = mlx5e_set_features,
2815         .ndo_change_mtu          = mlx5e_change_mtu,
2816         .ndo_do_ioctl            = mlx5e_ioctl,
2817         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
2818 #ifdef CONFIG_RFS_ACCEL
2819         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2820 #endif
2821         .ndo_tx_timeout          = mlx5e_tx_timeout,
2822 };
2823
2824 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2825         .ndo_open                = mlx5e_open,
2826         .ndo_stop                = mlx5e_close,
2827         .ndo_start_xmit          = mlx5e_xmit,
2828         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2829         .ndo_select_queue        = mlx5e_select_queue,
2830         .ndo_get_stats64         = mlx5e_get_stats,
2831         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2832         .ndo_set_mac_address     = mlx5e_set_mac,
2833         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2834         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2835         .ndo_set_features        = mlx5e_set_features,
2836         .ndo_change_mtu          = mlx5e_change_mtu,
2837         .ndo_do_ioctl            = mlx5e_ioctl,
2838         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
2839         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
2840         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
2841         .ndo_features_check      = mlx5e_features_check,
2842 #ifdef CONFIG_RFS_ACCEL
2843         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2844 #endif
2845         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2846         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2847         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
2848         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
2849         .ndo_get_vf_config       = mlx5e_get_vf_config,
2850         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2851         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2852         .ndo_tx_timeout          = mlx5e_tx_timeout,
2853 };
2854
2855 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2856 {
2857         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2858                 return -ENOTSUPP;
2859         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2860             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2861             !MLX5_CAP_ETH(mdev, csum_cap) ||
2862             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2863             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2864             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2865             MLX5_CAP_FLOWTABLE(mdev,
2866                                flow_table_properties_nic_receive.max_ft_level)
2867                                < 3) {
2868                 mlx5_core_warn(mdev,
2869                                "Not creating net device, some required device capabilities are missing\n");
2870                 return -ENOTSUPP;
2871         }
2872         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2873                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2874         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2875                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2876
2877         return 0;
2878 }
2879
2880 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2881 {
2882         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2883
2884         return bf_buf_size -
2885                sizeof(struct mlx5e_tx_wqe) +
2886                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2887 }
2888
2889 #ifdef CONFIG_MLX5_CORE_EN_DCB
2890 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2891 {
2892         int i;
2893
2894         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2895         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2896                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2897                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2898                 priv->params.ets.prio_tc[i] = i;
2899         }
2900
2901         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2902         priv->params.ets.prio_tc[0] = 1;
2903         priv->params.ets.prio_tc[1] = 0;
2904 }
2905 #endif
2906
2907 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2908                                    u32 *indirection_rqt, int len,
2909                                    int num_channels)
2910 {
2911         int node = mdev->priv.numa_node;
2912         int node_num_of_cores;
2913         int i;
2914
2915         if (node == -1)
2916                 node = first_online_node;
2917
2918         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2919
2920         if (node_num_of_cores)
2921                 num_channels = min_t(int, num_channels, node_num_of_cores);
2922
2923         for (i = 0; i < len; i++)
2924                 indirection_rqt[i] = i % num_channels;
2925 }
2926
2927 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2928 {
2929         return MLX5_CAP_GEN(mdev, striding_rq) &&
2930                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2931                 MLX5_CAP_ETH(mdev, reg_umr_sq);
2932 }
2933
2934 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2935 {
2936         enum pcie_link_width width;
2937         enum pci_bus_speed speed;
2938         int err = 0;
2939
2940         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2941         if (err)
2942                 return err;
2943
2944         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2945                 return -EINVAL;
2946
2947         switch (speed) {
2948         case PCIE_SPEED_2_5GT:
2949                 *pci_bw = 2500 * width;
2950                 break;
2951         case PCIE_SPEED_5_0GT:
2952                 *pci_bw = 5000 * width;
2953                 break;
2954         case PCIE_SPEED_8_0GT:
2955                 *pci_bw = 8000 * width;
2956                 break;
2957         default:
2958                 return -EINVAL;
2959         }
2960
2961         return 0;
2962 }
2963
2964 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2965 {
2966         return (link_speed && pci_bw &&
2967                 (pci_bw < 40000) && (pci_bw < link_speed));
2968 }
2969
2970 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
2971 {
2972         params->rx_cq_period_mode = cq_period_mode;
2973
2974         params->rx_cq_moderation.pkts =
2975                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2976         params->rx_cq_moderation.usec =
2977                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2978
2979         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
2980                 params->rx_cq_moderation.usec =
2981                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
2982 }
2983
2984 static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
2985                                    u8 *min_inline_mode)
2986 {
2987         switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
2988         case MLX5E_INLINE_MODE_L2:
2989                 *min_inline_mode = MLX5_INLINE_MODE_L2;
2990                 break;
2991         case MLX5E_INLINE_MODE_VPORT_CONTEXT:
2992                 mlx5_query_nic_vport_min_inline(mdev,
2993                                                 min_inline_mode);
2994                 break;
2995         case MLX5_INLINE_MODE_NOT_REQUIRED:
2996                 *min_inline_mode = MLX5_INLINE_MODE_NONE;
2997                 break;
2998         }
2999 }
3000
3001 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3002                                         struct net_device *netdev,
3003                                         const struct mlx5e_profile *profile,
3004                                         void *ppriv)
3005 {
3006         struct mlx5e_priv *priv = netdev_priv(netdev);
3007         u32 link_speed = 0;
3008         u32 pci_bw = 0;
3009         u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3010                                          MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3011                                          MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3012
3013         priv->params.log_sq_size           =
3014                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3015         priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
3016                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
3017                 MLX5_WQ_TYPE_LINKED_LIST;
3018
3019         /* set CQE compression */
3020         priv->params.rx_cqe_compress_admin = false;
3021         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3022             MLX5_CAP_GEN(mdev, vport_group_manager)) {
3023                 mlx5e_get_max_linkspeed(mdev, &link_speed);
3024                 mlx5e_get_pci_bw(mdev, &pci_bw);
3025                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3026                               link_speed, pci_bw);
3027                 priv->params.rx_cqe_compress_admin =
3028                         cqe_compress_heuristic(link_speed, pci_bw);
3029         }
3030
3031         priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3032
3033         switch (priv->params.rq_wq_type) {
3034         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
3035                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
3036                 priv->params.mpwqe_log_stride_sz =
3037                         priv->params.rx_cqe_compress ?
3038                         MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
3039                         MLX5_MPWRQ_LOG_STRIDE_SIZE;
3040                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
3041                         priv->params.mpwqe_log_stride_sz;
3042                 priv->params.lro_en = true;
3043                 break;
3044         default: /* MLX5_WQ_TYPE_LINKED_LIST */
3045                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3046         }
3047
3048         mlx5_core_info(mdev,
3049                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
3050                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
3051                        BIT(priv->params.log_rq_size),
3052                        BIT(priv->params.mpwqe_log_stride_sz),
3053                        priv->params.rx_cqe_compress_admin);
3054
3055         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
3056                                             BIT(priv->params.log_rq_size));
3057
3058         priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3059         mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3060
3061         priv->params.tx_cq_moderation.usec =
3062                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3063         priv->params.tx_cq_moderation.pkts =
3064                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3065         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
3066         mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3067         priv->params.num_tc                = 1;
3068         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
3069
3070         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3071                             sizeof(priv->params.toeplitz_hash_key));
3072
3073         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3074                                       MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3075
3076         priv->params.lro_wqe_sz            =
3077                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3078
3079         /* Initialize pflags */
3080         MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3081                             priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3082
3083         priv->mdev                         = mdev;
3084         priv->netdev                       = netdev;
3085         priv->params.num_channels          = profile->max_nch(mdev);
3086         priv->profile                      = profile;
3087         priv->ppriv                        = ppriv;
3088
3089 #ifdef CONFIG_MLX5_CORE_EN_DCB
3090         mlx5e_ets_init(priv);
3091 #endif
3092
3093         mutex_init(&priv->state_lock);
3094
3095         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3096         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3097         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3098         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3099 }
3100
3101 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3102 {
3103         struct mlx5e_priv *priv = netdev_priv(netdev);
3104
3105         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3106         if (is_zero_ether_addr(netdev->dev_addr) &&
3107             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3108                 eth_hw_addr_random(netdev);
3109                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3110         }
3111 }
3112
3113 static const struct switchdev_ops mlx5e_switchdev_ops = {
3114         .switchdev_port_attr_get        = mlx5e_attr_get,
3115 };
3116
3117 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3118 {
3119         struct mlx5e_priv *priv = netdev_priv(netdev);
3120         struct mlx5_core_dev *mdev = priv->mdev;
3121         bool fcs_supported;
3122         bool fcs_enabled;
3123
3124         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3125
3126         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3127                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3128 #ifdef CONFIG_MLX5_CORE_EN_DCB
3129                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3130 #endif
3131         } else {
3132                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3133         }
3134
3135         netdev->watchdog_timeo    = 15 * HZ;
3136
3137         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
3138
3139         netdev->vlan_features    |= NETIF_F_SG;
3140         netdev->vlan_features    |= NETIF_F_IP_CSUM;
3141         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
3142         netdev->vlan_features    |= NETIF_F_GRO;
3143         netdev->vlan_features    |= NETIF_F_TSO;
3144         netdev->vlan_features    |= NETIF_F_TSO6;
3145         netdev->vlan_features    |= NETIF_F_RXCSUM;
3146         netdev->vlan_features    |= NETIF_F_RXHASH;
3147
3148         if (!!MLX5_CAP_ETH(mdev, lro_cap))
3149                 netdev->vlan_features    |= NETIF_F_LRO;
3150
3151         netdev->hw_features       = netdev->vlan_features;
3152         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
3153         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
3154         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
3155
3156         if (mlx5e_vxlan_allowed(mdev)) {
3157                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
3158                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
3159                                            NETIF_F_GSO_PARTIAL;
3160                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3161                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3162                 netdev->hw_enc_features |= NETIF_F_TSO;
3163                 netdev->hw_enc_features |= NETIF_F_TSO6;
3164                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3165                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3166                                            NETIF_F_GSO_PARTIAL;
3167                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3168         }
3169
3170         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3171
3172         if (fcs_supported)
3173                 netdev->hw_features |= NETIF_F_RXALL;
3174
3175         netdev->features          = netdev->hw_features;
3176         if (!priv->params.lro_en)
3177                 netdev->features  &= ~NETIF_F_LRO;
3178
3179         if (fcs_enabled)
3180                 netdev->features  &= ~NETIF_F_RXALL;
3181
3182 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3183         if (FT_CAP(flow_modify_en) &&
3184             FT_CAP(modify_root) &&
3185             FT_CAP(identified_miss_table_mode) &&
3186             FT_CAP(flow_table_modify)) {
3187                 netdev->hw_features      |= NETIF_F_HW_TC;
3188 #ifdef CONFIG_RFS_ACCEL
3189                 netdev->hw_features      |= NETIF_F_NTUPLE;
3190 #endif
3191         }
3192
3193         netdev->features         |= NETIF_F_HIGHDMA;
3194
3195         netdev->priv_flags       |= IFF_UNICAST_FLT;
3196
3197         mlx5e_set_netdev_dev_addr(netdev);
3198
3199 #ifdef CONFIG_NET_SWITCHDEV
3200         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3201                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3202 #endif
3203 }
3204
3205 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3206 {
3207         struct mlx5_core_dev *mdev = priv->mdev;
3208         int err;
3209
3210         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3211         if (err) {
3212                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3213                 priv->q_counter = 0;
3214         }
3215 }
3216
3217 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3218 {
3219         if (!priv->q_counter)
3220                 return;
3221
3222         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3223 }
3224
3225 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3226 {
3227         struct mlx5_core_dev *mdev = priv->mdev;
3228         struct mlx5_create_mkey_mbox_in *in;
3229         struct mlx5_mkey_seg *mkc;
3230         int inlen = sizeof(*in);
3231         u64 npages =
3232                 priv->profile->max_nch(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
3233         int err;
3234
3235         in = mlx5_vzalloc(inlen);
3236         if (!in)
3237                 return -ENOMEM;
3238
3239         mkc = &in->seg;
3240         mkc->status = MLX5_MKEY_STATUS_FREE;
3241         mkc->flags = MLX5_PERM_UMR_EN |
3242                      MLX5_PERM_LOCAL_READ |
3243                      MLX5_PERM_LOCAL_WRITE |
3244                      MLX5_ACCESS_MODE_MTT;
3245
3246         mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3247         mkc->flags_pd = cpu_to_be32(mdev->mlx5e_res.pdn);
3248         mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
3249         mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
3250         mkc->log2_page_size = PAGE_SHIFT;
3251
3252         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
3253                                     NULL, NULL);
3254
3255         kvfree(in);
3256
3257         return err;
3258 }
3259
3260 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3261                            struct net_device *netdev,
3262                            const struct mlx5e_profile *profile,
3263                            void *ppriv)
3264 {
3265         struct mlx5e_priv *priv = netdev_priv(netdev);
3266
3267         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3268         mlx5e_build_nic_netdev(netdev);
3269         mlx5e_vxlan_init(priv);
3270 }
3271
3272 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3273 {
3274         struct mlx5_core_dev *mdev = priv->mdev;
3275         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3276
3277         mlx5e_vxlan_cleanup(priv);
3278
3279         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3280                 mlx5_eswitch_unregister_vport_rep(esw, 0);
3281 }
3282
3283 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3284 {
3285         struct mlx5_core_dev *mdev = priv->mdev;
3286         int err;
3287         int i;
3288
3289         err = mlx5e_create_indirect_rqts(priv);
3290         if (err) {
3291                 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3292                 return err;
3293         }
3294
3295         err = mlx5e_create_direct_rqts(priv);
3296         if (err) {
3297                 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3298                 goto err_destroy_indirect_rqts;
3299         }
3300
3301         err = mlx5e_create_indirect_tirs(priv);
3302         if (err) {
3303                 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3304                 goto err_destroy_direct_rqts;
3305         }
3306
3307         err = mlx5e_create_direct_tirs(priv);
3308         if (err) {
3309                 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3310                 goto err_destroy_indirect_tirs;
3311         }
3312
3313         err = mlx5e_create_flow_steering(priv);
3314         if (err) {
3315                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3316                 goto err_destroy_direct_tirs;
3317         }
3318
3319         err = mlx5e_tc_init(priv);
3320         if (err)
3321                 goto err_destroy_flow_steering;
3322
3323         return 0;
3324
3325 err_destroy_flow_steering:
3326         mlx5e_destroy_flow_steering(priv);
3327 err_destroy_direct_tirs:
3328         mlx5e_destroy_direct_tirs(priv);
3329 err_destroy_indirect_tirs:
3330         mlx5e_destroy_indirect_tirs(priv);
3331 err_destroy_direct_rqts:
3332         for (i = 0; i < priv->profile->max_nch(mdev); i++)
3333                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3334 err_destroy_indirect_rqts:
3335         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3336         return err;
3337 }
3338
3339 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3340 {
3341         int i;
3342
3343         mlx5e_tc_cleanup(priv);
3344         mlx5e_destroy_flow_steering(priv);
3345         mlx5e_destroy_direct_tirs(priv);
3346         mlx5e_destroy_indirect_tirs(priv);
3347         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3348                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3349         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3350 }
3351
3352 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3353 {
3354         int err;
3355
3356         err = mlx5e_create_tises(priv);
3357         if (err) {
3358                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3359                 return err;
3360         }
3361
3362 #ifdef CONFIG_MLX5_CORE_EN_DCB
3363         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3364 #endif
3365         return 0;
3366 }
3367
3368 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3369 {
3370         struct net_device *netdev = priv->netdev;
3371         struct mlx5_core_dev *mdev = priv->mdev;
3372         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3373         struct mlx5_eswitch_rep rep;
3374
3375         if (mlx5e_vxlan_allowed(mdev)) {
3376                 rtnl_lock();
3377                 udp_tunnel_get_rx_info(netdev);
3378                 rtnl_unlock();
3379         }
3380
3381         mlx5e_enable_async_events(priv);
3382         queue_work(priv->wq, &priv->set_rx_mode_work);
3383
3384         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3385                 rep.load = mlx5e_nic_rep_load;
3386                 rep.unload = mlx5e_nic_rep_unload;
3387                 rep.vport = 0;
3388                 rep.priv_data = priv;
3389                 mlx5_eswitch_register_vport_rep(esw, &rep);
3390         }
3391 }
3392
3393 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3394 {
3395         queue_work(priv->wq, &priv->set_rx_mode_work);
3396         mlx5e_disable_async_events(priv);
3397 }
3398
3399 static const struct mlx5e_profile mlx5e_nic_profile = {
3400         .init              = mlx5e_nic_init,
3401         .cleanup           = mlx5e_nic_cleanup,
3402         .init_rx           = mlx5e_init_nic_rx,
3403         .cleanup_rx        = mlx5e_cleanup_nic_rx,
3404         .init_tx           = mlx5e_init_nic_tx,
3405         .cleanup_tx        = mlx5e_cleanup_nic_tx,
3406         .enable            = mlx5e_nic_enable,
3407         .disable           = mlx5e_nic_disable,
3408         .update_stats      = mlx5e_update_stats,
3409         .max_nch           = mlx5e_get_max_num_channels,
3410         .max_tc            = MLX5E_MAX_NUM_TC,
3411 };
3412
3413 void *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3414                           const struct mlx5e_profile *profile, void *ppriv)
3415 {
3416         struct net_device *netdev;
3417         struct mlx5e_priv *priv;
3418         int nch = profile->max_nch(mdev);
3419         int err;
3420
3421         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3422                                     nch * profile->max_tc,
3423                                     nch);
3424         if (!netdev) {
3425                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3426                 return NULL;
3427         }
3428
3429         profile->init(mdev, netdev, profile, ppriv);
3430
3431         netif_carrier_off(netdev);
3432
3433         priv = netdev_priv(netdev);
3434
3435         priv->wq = create_singlethread_workqueue("mlx5e");
3436         if (!priv->wq)
3437                 goto err_free_netdev;
3438
3439         err = mlx5e_create_umr_mkey(priv);
3440         if (err) {
3441                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3442                 goto err_destroy_wq;
3443         }
3444
3445         err = profile->init_tx(priv);
3446         if (err)
3447                 goto err_destroy_umr_mkey;
3448
3449         err = mlx5e_open_drop_rq(priv);
3450         if (err) {
3451                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3452                 goto err_cleanup_tx;
3453         }
3454
3455         err = profile->init_rx(priv);
3456         if (err)
3457                 goto err_close_drop_rq;
3458
3459         mlx5e_create_q_counter(priv);
3460
3461         mlx5e_init_l2_addr(priv);
3462
3463         mlx5e_set_dev_port_mtu(netdev);
3464
3465         err = register_netdev(netdev);
3466         if (err) {
3467                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3468                 goto err_dealloc_q_counters;
3469         }
3470
3471         if (profile->enable)
3472                 profile->enable(priv);
3473
3474         return priv;
3475
3476 err_dealloc_q_counters:
3477         mlx5e_destroy_q_counter(priv);
3478         profile->cleanup_rx(priv);
3479
3480 err_close_drop_rq:
3481         mlx5e_close_drop_rq(priv);
3482
3483 err_cleanup_tx:
3484         profile->cleanup_tx(priv);
3485
3486 err_destroy_umr_mkey:
3487         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3488
3489 err_destroy_wq:
3490         destroy_workqueue(priv->wq);
3491
3492 err_free_netdev:
3493         free_netdev(netdev);
3494
3495         return NULL;
3496 }
3497
3498 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3499 {
3500         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3501         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3502         int vport;
3503
3504         if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3505                 return;
3506
3507         for (vport = 1; vport < total_vfs; vport++) {
3508                 struct mlx5_eswitch_rep rep;
3509
3510                 rep.load = mlx5e_vport_rep_load;
3511                 rep.unload = mlx5e_vport_rep_unload;
3512                 rep.vport = vport;
3513                 mlx5_eswitch_register_vport_rep(esw, &rep);
3514         }
3515 }
3516
3517 static void *mlx5e_add(struct mlx5_core_dev *mdev)
3518 {
3519         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3520         void *ppriv = NULL;
3521         void *ret;
3522
3523         if (mlx5e_check_required_hca_cap(mdev))
3524                 return NULL;
3525
3526         if (mlx5e_create_mdev_resources(mdev))
3527                 return NULL;
3528
3529         mlx5e_register_vport_rep(mdev);
3530
3531         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3532                 ppriv = &esw->offloads.vport_reps[0];
3533
3534         ret = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
3535         if (!ret) {
3536                 mlx5e_destroy_mdev_resources(mdev);
3537                 return NULL;
3538         }
3539         return ret;
3540 }
3541
3542 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
3543 {
3544         const struct mlx5e_profile *profile = priv->profile;
3545         struct net_device *netdev = priv->netdev;
3546
3547         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3548         if (profile->disable)
3549                 profile->disable(priv);
3550
3551         flush_workqueue(priv->wq);
3552         if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3553                 netif_device_detach(netdev);
3554                 mlx5e_close(netdev);
3555         } else {
3556                 unregister_netdev(netdev);
3557         }
3558
3559         mlx5e_destroy_q_counter(priv);
3560         profile->cleanup_rx(priv);
3561         mlx5e_close_drop_rq(priv);
3562         profile->cleanup_tx(priv);
3563         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3564         cancel_delayed_work_sync(&priv->update_stats_work);
3565         destroy_workqueue(priv->wq);
3566         if (profile->cleanup)
3567                 profile->cleanup(priv);
3568
3569         if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3570                 free_netdev(netdev);
3571 }
3572
3573 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
3574 {
3575         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3576         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3577         struct mlx5e_priv *priv = vpriv;
3578         int vport;
3579
3580         mlx5e_destroy_netdev(mdev, priv);
3581
3582         for (vport = 1; vport < total_vfs; vport++)
3583                 mlx5_eswitch_unregister_vport_rep(esw, vport);
3584
3585         mlx5e_destroy_mdev_resources(mdev);
3586 }
3587
3588 static void *mlx5e_get_netdev(void *vpriv)
3589 {
3590         struct mlx5e_priv *priv = vpriv;
3591
3592         return priv->netdev;
3593 }
3594
3595 static struct mlx5_interface mlx5e_interface = {
3596         .add       = mlx5e_add,
3597         .remove    = mlx5e_remove,
3598         .event     = mlx5e_async_event,
3599         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
3600         .get_dev   = mlx5e_get_netdev,
3601 };
3602
3603 void mlx5e_init(void)
3604 {
3605         mlx5e_build_ptys2ethtool_map();
3606         mlx5_register_interface(&mlx5e_interface);
3607 }
3608
3609 void mlx5e_cleanup(void)
3610 {
3611         mlx5_unregister_interface(&mlx5e_interface);
3612 }