drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 enum {
  43         MLX5_EN_QP_FLUSH_TIMEOUT_MS     = 5000,
  44         MLX5_EN_QP_FLUSH_MSLEEP_QUANT   = 20,
  45         MLX5_EN_QP_FLUSH_MAX_ITER       = MLX5_EN_QP_FLUSH_TIMEOUT_MS /
  46                                           MLX5_EN_QP_FLUSH_MSLEEP_QUANT,
  47 };
  48
  49 struct mlx5e_rq_param {
  50         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  51         struct mlx5_wq_param       wq;
  52 };
  53
  54 struct mlx5e_sq_param {
  55         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  56         struct mlx5_wq_param       wq;
  57         u16                        max_inline;
  58         bool                       icosq;
  59 };
  60
  61 struct mlx5e_cq_param {
  62         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  63         struct mlx5_wq_param       wq;
  64         u16                        eq_ix;
  65 };
  66
  67 struct mlx5e_channel_param {
  68         struct mlx5e_rq_param      rq;
  69         struct mlx5e_sq_param      sq;
  70         struct mlx5e_sq_param      icosq;
  71         struct mlx5e_cq_param      rx_cq;
  72         struct mlx5e_cq_param      tx_cq;
  73         struct mlx5e_cq_param      icosq_cq;
  74 };
  75
  76 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  77 {
  78         struct mlx5_core_dev *mdev = priv->mdev;
  79         u8 port_state;
  80
  81         port_state = mlx5_query_vport_state(mdev,
  82                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  83
  84         if (port_state == VPORT_STATE_UP)
  85                 netif_carrier_on(priv->netdev);
  86         else
  87                 netif_carrier_off(priv->netdev);
  88 }
  89
  90 static void mlx5e_update_carrier_work(struct work_struct *work)
  91 {
  92         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  93                                                update_carrier_work);
  94
  95         mutex_lock(&priv->state_lock);
  96         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  97                 mlx5e_update_carrier(priv);
  98         mutex_unlock(&priv->state_lock);
  99 }
 100
 101 static void mlx5e_tx_timeout_work(struct work_struct *work)
 102 {
 103         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 104                                                tx_timeout_work);
 105         int err;
 106
 107         rtnl_lock();
 108         mutex_lock(&priv->state_lock);
 109         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 110                 goto unlock;
 111         mlx5e_close_locked(priv->netdev);
 112         err = mlx5e_open_locked(priv->netdev);
 113         if (err)
 114                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 115                            err);
 116 unlock:
 117         mutex_unlock(&priv->state_lock);
 118         rtnl_unlock();
 119 }
 120
 121 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 122 {
 123         struct mlx5e_sw_stats *s = &priv->stats.sw;
 124         struct mlx5e_rq_stats *rq_stats;
 125         struct mlx5e_sq_stats *sq_stats;
 126         u64 tx_offload_none = 0;
 127         int i, j;
 128
 129         memset(s, 0, sizeof(*s));
 130         for (i = 0; i < priv->params.num_channels; i++) {
 131                 rq_stats = &priv->channel[i]->rq.stats;
 132
 133                 s->rx_packets   += rq_stats->packets;
 134                 s->rx_bytes     += rq_stats->bytes;
 135                 s->rx_lro_packets += rq_stats->lro_packets;
 136                 s->rx_lro_bytes += rq_stats->lro_bytes;
 137                 s->rx_csum_none += rq_stats->csum_none;
 138                 s->rx_csum_complete += rq_stats->csum_complete;
 139                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 140                 s->rx_wqe_err   += rq_stats->wqe_err;
 141                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 142                 s->rx_mpwqe_frag   += rq_stats->mpwqe_frag;
 143                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 144                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 145                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 146
 147                 for (j = 0; j < priv->params.num_tc; j++) {
 148                         sq_stats = &priv->channel[i]->sq[j].stats;
 149
 150                         s->tx_packets           += sq_stats->packets;
 151                         s->tx_bytes             += sq_stats->bytes;
 152                         s->tx_tso_packets       += sq_stats->tso_packets;
 153                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 154                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 155                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 156                         s->tx_queue_stopped     += sq_stats->stopped;
 157                         s->tx_queue_wake        += sq_stats->wake;
 158                         s->tx_queue_dropped     += sq_stats->dropped;
 159                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 160                         tx_offload_none         += sq_stats->csum_none;
 161                 }
 162         }
 163
 164         /* Update calculated offload counters */
 165         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
 166         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 167
 168         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 169                                 priv->stats.pport.phy_counters,
 170                                 counter_set.phys_layer_cntrs.link_down_events);
 171 }
 172
 173 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 174 {
 175         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 176         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 177         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 178         struct mlx5_core_dev *mdev = priv->mdev;
 179
 180         memset(in, 0, sizeof(in));
 181
 182         MLX5_SET(query_vport_counter_in, in, opcode,
 183                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 184         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 185         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 186
 187         memset(out, 0, outlen);
 188
 189         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 190 }
 191
 192 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 193 {
 194         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 195         struct mlx5_core_dev *mdev = priv->mdev;
 196         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 197         int prio;
 198         void *out;
 199         u32 *in;
 200
 201         in = mlx5_vzalloc(sz);
 202         if (!in)
 203                 goto free_out;
 204
 205         MLX5_SET(ppcnt_reg, in, local_port, 1);
 206
 207         out = pstats->IEEE_802_3_counters;
 208         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 209         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 210
 211         out = pstats->RFC_2863_counters;
 212         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 213         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 214
 215         out = pstats->RFC_2819_counters;
 216         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 217         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 218
 219         out = pstats->phy_counters;
 220         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 221         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 222
 223         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 224         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 225                 out = pstats->per_prio_counters[prio];
 226                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 227                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 228                                      MLX5_REG_PPCNT, 0, 0);
 229         }
 230
 231 free_out:
 232         kvfree(in);
 233 }
 234
 235 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 236 {
 237         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 238
 239         if (!priv->q_counter)
 240                 return;
 241
 242         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 243                                       &qcnt->rx_out_of_buffer);
 244 }
 245
 246 void mlx5e_update_stats(struct mlx5e_priv *priv)
 247 {
 248         mlx5e_update_q_counter(priv);
 249         mlx5e_update_vport_counters(priv);
 250         mlx5e_update_pport_counters(priv);
 251         mlx5e_update_sw_counters(priv);
 252 }
 253
 254 static void mlx5e_update_stats_work(struct work_struct *work)
 255 {
 256         struct delayed_work *dwork = to_delayed_work(work);
 257         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 258                                                update_stats_work);
 259         mutex_lock(&priv->state_lock);
 260         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 261                 mlx5e_update_stats(priv);
 262                 queue_delayed_work(priv->wq, dwork,
 263                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 264         }
 265         mutex_unlock(&priv->state_lock);
 266 }
 267
 268 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 269                               enum mlx5_dev_event event, unsigned long param)
 270 {
 271         struct mlx5e_priv *priv = vpriv;
 272
 273         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 274                 return;
 275
 276         switch (event) {
 277         case MLX5_DEV_EVENT_PORT_UP:
 278         case MLX5_DEV_EVENT_PORT_DOWN:
 279                 queue_work(priv->wq, &priv->update_carrier_work);
 280                 break;
 281
 282         default:
 283                 break;
 284         }
 285 }
 286
 287 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 288 {
 289         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 290 }
 291
 292 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 293 {
 294         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 295         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 296 }
 297
 298 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 299 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 300
 301 static int mlx5e_create_rq(struct mlx5e_channel *c,
 302                            struct mlx5e_rq_param *param,
 303                            struct mlx5e_rq *rq)
 304 {
 305         struct mlx5e_priv *priv = c->priv;
 306         struct mlx5_core_dev *mdev = priv->mdev;
 307         void *rqc = param->rqc;
 308         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 309         u32 byte_count;
 310         int wq_sz;
 311         int err;
 312         int i;
 313
 314         param->wq.db_numa_node = cpu_to_node(c->cpu);
 315
 316         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 317                                 &rq->wq_ctrl);
 318         if (err)
 319                 return err;
 320
 321         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 322
 323         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 324
 325         switch (priv->params.rq_wq_type) {
 326         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 327                 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
 328                                             GFP_KERNEL, cpu_to_node(c->cpu));
 329                 if (!rq->wqe_info) {
 330                         err = -ENOMEM;
 331                         goto err_rq_wq_destroy;
 332                 }
 333                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 334                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 335                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 336
 337                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 338                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 339                 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 340                 byte_count = rq->wqe_sz;
 341                 break;
 342         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 343                 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 344                                        cpu_to_node(c->cpu));
 345                 if (!rq->skb) {
 346                         err = -ENOMEM;
 347                         goto err_rq_wq_destroy;
 348                 }
 349                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 350                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 351                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 352
 353                 rq->wqe_sz = (priv->params.lro_en) ?
 354                                 priv->params.lro_wqe_sz :
 355                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 356                 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
 357                 byte_count = rq->wqe_sz;
 358                 byte_count |= MLX5_HW_START_PADDING;
 359         }
 360
 361         for (i = 0; i < wq_sz; i++) {
 362                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 363
 364                 wqe->data.byte_count = cpu_to_be32(byte_count);
 365         }
 366
 367         rq->wq_type = priv->params.rq_wq_type;
 368         rq->pdev    = c->pdev;
 369         rq->netdev  = c->netdev;
 370         rq->tstamp  = &priv->tstamp;
 371         rq->channel = c;
 372         rq->ix      = c->ix;
 373         rq->priv    = c->priv;
 374         rq->mkey_be = c->mkey_be;
 375         rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 376
 377         return 0;
 378
 379 err_rq_wq_destroy:
 380         mlx5_wq_destroy(&rq->wq_ctrl);
 381
 382         return err;
 383 }
 384
 385 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 386 {
 387         switch (rq->wq_type) {
 388         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 389                 kfree(rq->wqe_info);
 390                 break;
 391         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 392                 kfree(rq->skb);
 393         }
 394
 395         mlx5_wq_destroy(&rq->wq_ctrl);
 396 }
 397
 398 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 399 {
 400         struct mlx5e_priv *priv = rq->priv;
 401         struct mlx5_core_dev *mdev = priv->mdev;
 402
 403         void *in;
 404         void *rqc;
 405         void *wq;
 406         int inlen;
 407         int err;
 408
 409         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 410                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 411         in = mlx5_vzalloc(inlen);
 412         if (!in)
 413                 return -ENOMEM;
 414
 415         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 416         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 417
 418         memcpy(rqc, param->rqc, sizeof(param->rqc));
 419
 420         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 421         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 422         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 423         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 424         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 425                                                 MLX5_ADAPTER_PAGE_SHIFT);
 426         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 427
 428         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 429                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 430
 431         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 432
 433         kvfree(in);
 434
 435         return err;
 436 }
 437
 438 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 439                                  int next_state)
 440 {
 441         struct mlx5e_channel *c = rq->channel;
 442         struct mlx5e_priv *priv = c->priv;
 443         struct mlx5_core_dev *mdev = priv->mdev;
 444
 445         void *in;
 446         void *rqc;
 447         int inlen;
 448         int err;
 449
 450         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 451         in = mlx5_vzalloc(inlen);
 452         if (!in)
 453                 return -ENOMEM;
 454
 455         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 456
 457         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 458         MLX5_SET(rqc, rqc, state, next_state);
 459
 460         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 461
 462         kvfree(in);
 463
 464         return err;
 465 }
 466
 467 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 468 {
 469         struct mlx5e_channel *c = rq->channel;
 470         struct mlx5e_priv *priv = c->priv;
 471         struct mlx5_core_dev *mdev = priv->mdev;
 472
 473         void *in;
 474         void *rqc;
 475         int inlen;
 476         int err;
 477
 478         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 479         in = mlx5_vzalloc(inlen);
 480         if (!in)
 481                 return -ENOMEM;
 482
 483         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 484
 485         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 486         MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
 487         MLX5_SET(rqc, rqc, vsd, vsd);
 488         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 489
 490         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 491
 492         kvfree(in);
 493
 494         return err;
 495 }
 496
 497 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 498 {
 499         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 500 }
 501
 502 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 503 {
 504         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 505         struct mlx5e_channel *c = rq->channel;
 506         struct mlx5e_priv *priv = c->priv;
 507         struct mlx5_wq_ll *wq = &rq->wq;
 508
 509         while (time_before(jiffies, exp_time)) {
 510                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 511                         return 0;
 512
 513                 msleep(20);
 514         }
 515
 516         return -ETIMEDOUT;
 517 }
 518
 519 static int mlx5e_open_rq(struct mlx5e_channel *c,
 520                          struct mlx5e_rq_param *param,
 521                          struct mlx5e_rq *rq)
 522 {
 523         struct mlx5e_sq *sq = &c->icosq;
 524         u16 pi = sq->pc & sq->wq.sz_m1;
 525         int err;
 526
 527         err = mlx5e_create_rq(c, param, rq);
 528         if (err)
 529                 return err;
 530
 531         err = mlx5e_enable_rq(rq, param);
 532         if (err)
 533                 goto err_destroy_rq;
 534
 535         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 536         if (err)
 537                 goto err_disable_rq;
 538
 539         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 540
 541         sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
 542         sq->ico_wqe_info[pi].num_wqebbs = 1;
 543         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 544
 545         return 0;
 546
 547 err_disable_rq:
 548         mlx5e_disable_rq(rq);
 549 err_destroy_rq:
 550         mlx5e_destroy_rq(rq);
 551
 552         return err;
 553 }
 554
 555 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 556 {
 557         int tout = 0;
 558         int err;
 559
 560         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 561         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 562
 563         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 564         while (!mlx5_wq_ll_is_empty(&rq->wq) && !err &&
 565                tout++ < MLX5_EN_QP_FLUSH_MAX_ITER)
 566                 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
 567
 568         if (err || tout == MLX5_EN_QP_FLUSH_MAX_ITER)
 569                 set_bit(MLX5E_RQ_STATE_FLUSH_TIMEOUT, &rq->state);
 570
 571         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 572         napi_synchronize(&rq->channel->napi);
 573
 574         mlx5e_disable_rq(rq);
 575         mlx5e_free_rx_descs(rq);
 576         mlx5e_destroy_rq(rq);
 577 }
 578
 579 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 580 {
 581         kfree(sq->wqe_info);
 582         kfree(sq->dma_fifo);
 583         kfree(sq->skb);
 584 }
 585
 586 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 587 {
 588         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 589         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 590
 591         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 592         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 593                                     numa);
 594         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 595                                     numa);
 596
 597         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 598                 mlx5e_free_sq_db(sq);
 599                 return -ENOMEM;
 600         }
 601
 602         sq->dma_fifo_mask = df_sz - 1;
 603
 604         return 0;
 605 }
 606
 607 static int mlx5e_create_sq(struct mlx5e_channel *c,
 608                            int tc,
 609                            struct mlx5e_sq_param *param,
 610                            struct mlx5e_sq *sq)
 611 {
 612         struct mlx5e_priv *priv = c->priv;
 613         struct mlx5_core_dev *mdev = priv->mdev;
 614
 615         void *sqc = param->sqc;
 616         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 617         int err;
 618
 619         err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
 620         if (err)
 621                 return err;
 622
 623         param->wq.db_numa_node = cpu_to_node(c->cpu);
 624
 625         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 626                                  &sq->wq_ctrl);
 627         if (err)
 628                 goto err_unmap_free_uar;
 629
 630         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 631         if (sq->uar.bf_map) {
 632                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 633                 sq->uar_map = sq->uar.bf_map;
 634         } else {
 635                 sq->uar_map = sq->uar.map;
 636         }
 637         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 638         sq->max_inline  = param->max_inline;
 639
 640         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 641         if (err)
 642                 goto err_sq_wq_destroy;
 643
 644         if (param->icosq) {
 645                 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 646
 647                 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
 648                                                 wq_sz,
 649                                                 GFP_KERNEL,
 650                                                 cpu_to_node(c->cpu));
 651                 if (!sq->ico_wqe_info) {
 652                         err = -ENOMEM;
 653                         goto err_free_sq_db;
 654                 }
 655         } else {
 656                 int txq_ix;
 657
 658                 txq_ix = c->ix + tc * priv->params.num_channels;
 659                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 660                 priv->txq_to_sq_map[txq_ix] = sq;
 661         }
 662
 663         sq->pdev      = c->pdev;
 664         sq->tstamp    = &priv->tstamp;
 665         sq->mkey_be   = c->mkey_be;
 666         sq->channel   = c;
 667         sq->tc        = tc;
 668         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 669         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 670
 671         return 0;
 672
 673 err_free_sq_db:
 674         mlx5e_free_sq_db(sq);
 675
 676 err_sq_wq_destroy:
 677         mlx5_wq_destroy(&sq->wq_ctrl);
 678
 679 err_unmap_free_uar:
 680         mlx5_unmap_free_uar(mdev, &sq->uar);
 681
 682         return err;
 683 }
 684
 685 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 686 {
 687         struct mlx5e_channel *c = sq->channel;
 688         struct mlx5e_priv *priv = c->priv;
 689
 690         kfree(sq->ico_wqe_info);
 691         mlx5e_free_sq_db(sq);
 692         mlx5_wq_destroy(&sq->wq_ctrl);
 693         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 694 }
 695
 696 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 697 {
 698         struct mlx5e_channel *c = sq->channel;
 699         struct mlx5e_priv *priv = c->priv;
 700         struct mlx5_core_dev *mdev = priv->mdev;
 701
 702         void *in;
 703         void *sqc;
 704         void *wq;
 705         int inlen;
 706         int err;
 707
 708         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 709                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 710         in = mlx5_vzalloc(inlen);
 711         if (!in)
 712                 return -ENOMEM;
 713
 714         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 715         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 716
 717         memcpy(sqc, param->sqc, sizeof(param->sqc));
 718
 719         MLX5_SET(sqc,  sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
 720         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
 721         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 722         MLX5_SET(sqc,  sqc, tis_lst_sz,         param->icosq ? 0 : 1);
 723         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 724
 725         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 726         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 727         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 728                                           MLX5_ADAPTER_PAGE_SHIFT);
 729         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 730
 731         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 732                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 733
 734         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 735
 736         kvfree(in);
 737
 738         return err;
 739 }
 740
 741 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 742 {
 743         struct mlx5e_channel *c = sq->channel;
 744         struct mlx5e_priv *priv = c->priv;
 745         struct mlx5_core_dev *mdev = priv->mdev;
 746
 747         void *in;
 748         void *sqc;
 749         int inlen;
 750         int err;
 751
 752         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 753         in = mlx5_vzalloc(inlen);
 754         if (!in)
 755                 return -ENOMEM;
 756
 757         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 758
 759         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 760         MLX5_SET(sqc, sqc, state, next_state);
 761
 762         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 763
 764         kvfree(in);
 765
 766         return err;
 767 }
 768
 769 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 770 {
 771         struct mlx5e_channel *c = sq->channel;
 772         struct mlx5e_priv *priv = c->priv;
 773         struct mlx5_core_dev *mdev = priv->mdev;
 774
 775         mlx5_core_destroy_sq(mdev, sq->sqn);
 776 }
 777
 778 static int mlx5e_open_sq(struct mlx5e_channel *c,
 779                          int tc,
 780                          struct mlx5e_sq_param *param,
 781                          struct mlx5e_sq *sq)
 782 {
 783         int err;
 784
 785         err = mlx5e_create_sq(c, tc, param, sq);
 786         if (err)
 787                 return err;
 788
 789         err = mlx5e_enable_sq(sq, param);
 790         if (err)
 791                 goto err_destroy_sq;
 792
 793         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 794         if (err)
 795                 goto err_disable_sq;
 796
 797         if (sq->txq) {
 798                 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 799                 netdev_tx_reset_queue(sq->txq);
 800                 netif_tx_start_queue(sq->txq);
 801         }
 802
 803         return 0;
 804
 805 err_disable_sq:
 806         mlx5e_disable_sq(sq);
 807 err_destroy_sq:
 808         mlx5e_destroy_sq(sq);
 809
 810         return err;
 811 }
 812
 813 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 814 {
 815         __netif_tx_lock_bh(txq);
 816         netif_tx_stop_queue(txq);
 817         __netif_tx_unlock_bh(txq);
 818 }
 819
 820 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 821 {
 822         int tout = 0;
 823         int err;
 824
 825         if (sq->txq) {
 826                 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 827                 /* prevent netif_tx_wake_queue */
 828                 napi_synchronize(&sq->channel->napi);
 829                 netif_tx_disable_queue(sq->txq);
 830
 831                 /* ensure hw is notified of all pending wqes */
 832                 if (mlx5e_sq_has_room_for(sq, 1))
 833                         mlx5e_send_nop(sq, true);
 834
 835                 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
 836                                       MLX5_SQC_STATE_ERR);
 837                 if (err)
 838                         set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
 839         }
 840
 841         /* wait till sq is empty, unless a TX timeout occurred on this SQ */
 842         while (sq->cc != sq->pc &&
 843                !test_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state)) {
 844                 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
 845                 if (tout++ > MLX5_EN_QP_FLUSH_MAX_ITER)
 846                         set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
 847         }
 848
 849         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 850         napi_synchronize(&sq->channel->napi);
 851
 852         mlx5e_free_tx_descs(sq);
 853         mlx5e_disable_sq(sq);
 854         mlx5e_destroy_sq(sq);
 855 }
 856
 857 static int mlx5e_create_cq(struct mlx5e_channel *c,
 858                            struct mlx5e_cq_param *param,
 859                            struct mlx5e_cq *cq)
 860 {
 861         struct mlx5e_priv *priv = c->priv;
 862         struct mlx5_core_dev *mdev = priv->mdev;
 863         struct mlx5_core_cq *mcq = &cq->mcq;
 864         int eqn_not_used;
 865         unsigned int irqn;
 866         int err;
 867         u32 i;
 868
 869         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 870         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 871         param->eq_ix   = c->ix;
 872
 873         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 874                                &cq->wq_ctrl);
 875         if (err)
 876                 return err;
 877
 878         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 879
 880         cq->napi        = &c->napi;
 881
 882         mcq->cqe_sz     = 64;
 883         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 884         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 885         *mcq->set_ci_db = 0;
 886         *mcq->arm_db    = 0;
 887         mcq->vector     = param->eq_ix;
 888         mcq->comp       = mlx5e_completion_event;
 889         mcq->event      = mlx5e_cq_error_event;
 890         mcq->irqn       = irqn;
 891         mcq->uar        = &priv->cq_uar;
 892
 893         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 894                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 895
 896                 cqe->op_own = 0xf1;
 897         }
 898
 899         cq->channel = c;
 900         cq->priv = priv;
 901
 902         return 0;
 903 }
 904
 905 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 906 {
 907         mlx5_wq_destroy(&cq->wq_ctrl);
 908 }
 909
 910 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 911 {
 912         struct mlx5e_priv *priv = cq->priv;
 913         struct mlx5_core_dev *mdev = priv->mdev;
 914         struct mlx5_core_cq *mcq = &cq->mcq;
 915
 916         void *in;
 917         void *cqc;
 918         int inlen;
 919         unsigned int irqn_not_used;
 920         int eqn;
 921         int err;
 922
 923         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 924                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 925         in = mlx5_vzalloc(inlen);
 926         if (!in)
 927                 return -ENOMEM;
 928
 929         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 930
 931         memcpy(cqc, param->cqc, sizeof(param->cqc));
 932
 933         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 934                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 935
 936         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 937
 938         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 939         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 940         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 941                                             MLX5_ADAPTER_PAGE_SHIFT);
 942         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 943
 944         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 945
 946         kvfree(in);
 947
 948         if (err)
 949                 return err;
 950
 951         mlx5e_cq_arm(cq);
 952
 953         return 0;
 954 }
 955
 956 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 957 {
 958         struct mlx5e_priv *priv = cq->priv;
 959         struct mlx5_core_dev *mdev = priv->mdev;
 960
 961         mlx5_core_destroy_cq(mdev, &cq->mcq);
 962 }
 963
 964 static int mlx5e_open_cq(struct mlx5e_channel *c,
 965                          struct mlx5e_cq_param *param,
 966                          struct mlx5e_cq *cq,
 967                          u16 moderation_usecs,
 968                          u16 moderation_frames)
 969 {
 970         int err;
 971         struct mlx5e_priv *priv = c->priv;
 972         struct mlx5_core_dev *mdev = priv->mdev;
 973
 974         err = mlx5e_create_cq(c, param, cq);
 975         if (err)
 976                 return err;
 977
 978         err = mlx5e_enable_cq(cq, param);
 979         if (err)
 980                 goto err_destroy_cq;
 981
 982         if (MLX5_CAP_GEN(mdev, cq_moderation))
 983                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 984                                                moderation_usecs,
 985                                                moderation_frames);
 986         return 0;
 987
 988 err_destroy_cq:
 989         mlx5e_destroy_cq(cq);
 990
 991         return err;
 992 }
 993
 994 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 995 {
 996         mlx5e_disable_cq(cq);
 997         mlx5e_destroy_cq(cq);
 998 }
 999
1000 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1001 {
1002         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1003 }
1004
1005 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1006                              struct mlx5e_channel_param *cparam)
1007 {
1008         struct mlx5e_priv *priv = c->priv;
1009         int err;
1010         int tc;
1011
1012         for (tc = 0; tc < c->num_tc; tc++) {
1013                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1014                                     priv->params.tx_cq_moderation_usec,
1015                                     priv->params.tx_cq_moderation_pkts);
1016                 if (err)
1017                         goto err_close_tx_cqs;
1018         }
1019
1020         return 0;
1021
1022 err_close_tx_cqs:
1023         for (tc--; tc >= 0; tc--)
1024                 mlx5e_close_cq(&c->sq[tc].cq);
1025
1026         return err;
1027 }
1028
1029 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1030 {
1031         int tc;
1032
1033         for (tc = 0; tc < c->num_tc; tc++)
1034                 mlx5e_close_cq(&c->sq[tc].cq);
1035 }
1036
1037 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1038                           struct mlx5e_channel_param *cparam)
1039 {
1040         int err;
1041         int tc;
1042
1043         for (tc = 0; tc < c->num_tc; tc++) {
1044                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1045                 if (err)
1046                         goto err_close_sqs;
1047         }
1048
1049         return 0;
1050
1051 err_close_sqs:
1052         for (tc--; tc >= 0; tc--)
1053                 mlx5e_close_sq(&c->sq[tc]);
1054
1055         return err;
1056 }
1057
1058 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1059 {
1060         int tc;
1061
1062         for (tc = 0; tc < c->num_tc; tc++)
1063                 mlx5e_close_sq(&c->sq[tc]);
1064 }
1065
1066 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1067 {
1068         int i;
1069
1070         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
1071                 priv->channeltc_to_txq_map[ix][i] =
1072                         ix + i * priv->params.num_channels;
1073 }
1074
1075 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1076                               struct mlx5e_channel_param *cparam,
1077                               struct mlx5e_channel **cp)
1078 {
1079         struct net_device *netdev = priv->netdev;
1080         int cpu = mlx5e_get_cpu(priv, ix);
1081         struct mlx5e_channel *c;
1082         int err;
1083
1084         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1085         if (!c)
1086                 return -ENOMEM;
1087
1088         c->priv     = priv;
1089         c->ix       = ix;
1090         c->cpu      = cpu;
1091         c->pdev     = &priv->mdev->pdev->dev;
1092         c->netdev   = priv->netdev;
1093         c->mkey_be  = cpu_to_be32(priv->mkey.key);
1094         c->num_tc   = priv->params.num_tc;
1095
1096         mlx5e_build_channeltc_to_txq_map(priv, ix);
1097
1098         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1099
1100         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
1101         if (err)
1102                 goto err_napi_del;
1103
1104         err = mlx5e_open_tx_cqs(c, cparam);
1105         if (err)
1106                 goto err_close_icosq_cq;
1107
1108         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1109                             priv->params.rx_cq_moderation_usec,
1110                             priv->params.rx_cq_moderation_pkts);
1111         if (err)
1112                 goto err_close_tx_cqs;
1113
1114         napi_enable(&c->napi);
1115
1116         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1117         if (err)
1118                 goto err_disable_napi;
1119
1120         err = mlx5e_open_sqs(c, cparam);
1121         if (err)
1122                 goto err_close_icosq;
1123
1124         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1125         if (err)
1126                 goto err_close_sqs;
1127
1128         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1129         *cp = c;
1130
1131         return 0;
1132
1133 err_close_sqs:
1134         mlx5e_close_sqs(c);
1135
1136 err_close_icosq:
1137         mlx5e_close_sq(&c->icosq);
1138
1139 err_disable_napi:
1140         napi_disable(&c->napi);
1141         mlx5e_close_cq(&c->rq.cq);
1142
1143 err_close_tx_cqs:
1144         mlx5e_close_tx_cqs(c);
1145
1146 err_close_icosq_cq:
1147         mlx5e_close_cq(&c->icosq.cq);
1148
1149 err_napi_del:
1150         netif_napi_del(&c->napi);
1151         napi_hash_del(&c->napi);
1152         kfree(c);
1153
1154         return err;
1155 }
1156
1157 static void mlx5e_close_channel(struct mlx5e_channel *c)
1158 {
1159         mlx5e_close_rq(&c->rq);
1160         mlx5e_close_sqs(c);
1161         mlx5e_close_sq(&c->icosq);
1162         napi_disable(&c->napi);
1163         mlx5e_close_cq(&c->rq.cq);
1164         mlx5e_close_tx_cqs(c);
1165         mlx5e_close_cq(&c->icosq.cq);
1166         netif_napi_del(&c->napi);
1167
1168         napi_hash_del(&c->napi);
1169         synchronize_rcu();
1170
1171         kfree(c);
1172 }
1173
1174 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1175                                  struct mlx5e_rq_param *param)
1176 {
1177         void *rqc = param->rqc;
1178         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1179
1180         switch (priv->params.rq_wq_type) {
1181         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1182                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1183                          priv->params.mpwqe_log_num_strides - 9);
1184                 MLX5_SET(wq, wq, log_wqe_stride_size,
1185                          priv->params.mpwqe_log_stride_sz - 6);
1186                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1187                 break;
1188         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1189                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1190         }
1191
1192         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1193         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1194         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1195         MLX5_SET(wq, wq, pd,               priv->pdn);
1196         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1197
1198         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1199         param->wq.linear = 1;
1200 }
1201
1202 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1203 {
1204         void *rqc = param->rqc;
1205         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1206
1207         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1208         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1209 }
1210
1211 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1212                                         struct mlx5e_sq_param *param)
1213 {
1214         void *sqc = param->sqc;
1215         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1216
1217         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1218         MLX5_SET(wq, wq, pd,            priv->pdn);
1219
1220         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1221 }
1222
1223 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1224                                  struct mlx5e_sq_param *param)
1225 {
1226         void *sqc = param->sqc;
1227         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1228
1229         mlx5e_build_sq_param_common(priv, param);
1230         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1231
1232         param->max_inline = priv->params.tx_max_inline;
1233 }
1234
1235 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1236                                         struct mlx5e_cq_param *param)
1237 {
1238         void *cqc = param->cqc;
1239
1240         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1241 }
1242
1243 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1244                                     struct mlx5e_cq_param *param)
1245 {
1246         void *cqc = param->cqc;
1247         u8 log_cq_size;
1248
1249         switch (priv->params.rq_wq_type) {
1250         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1251                 log_cq_size = priv->params.log_rq_size +
1252                         priv->params.mpwqe_log_num_strides;
1253                 break;
1254         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1255                 log_cq_size = priv->params.log_rq_size;
1256         }
1257
1258         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1259         if (priv->params.rx_cqe_compress) {
1260                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1261                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1262         }
1263
1264         mlx5e_build_common_cq_param(priv, param);
1265 }
1266
1267 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1268                                     struct mlx5e_cq_param *param)
1269 {
1270         void *cqc = param->cqc;
1271
1272         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1273
1274         mlx5e_build_common_cq_param(priv, param);
1275 }
1276
1277 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1278                                      struct mlx5e_cq_param *param,
1279                                      u8 log_wq_size)
1280 {
1281         void *cqc = param->cqc;
1282
1283         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1284
1285         mlx5e_build_common_cq_param(priv, param);
1286 }
1287
1288 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1289                                     struct mlx5e_sq_param *param,
1290                                     u8 log_wq_size)
1291 {
1292         void *sqc = param->sqc;
1293         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1294
1295         mlx5e_build_sq_param_common(priv, param);
1296
1297         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1298         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1299
1300         param->icosq = true;
1301 }
1302
1303 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1304 {
1305         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1306
1307         mlx5e_build_rq_param(priv, &cparam->rq);
1308         mlx5e_build_sq_param(priv, &cparam->sq);
1309         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1310         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1311         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1312         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1313 }
1314
1315 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1316 {
1317         struct mlx5e_channel_param *cparam;
1318         int nch = priv->params.num_channels;
1319         int err = -ENOMEM;
1320         int i;
1321         int j;
1322
1323         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1324                                 GFP_KERNEL);
1325
1326         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1327                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1328
1329         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1330
1331         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1332                 goto err_free_txq_to_sq_map;
1333
1334         mlx5e_build_channel_param(priv, cparam);
1335
1336         for (i = 0; i < nch; i++) {
1337                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1338                 if (err)
1339                         goto err_close_channels;
1340         }
1341
1342         for (j = 0; j < nch; j++) {
1343                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1344                 if (err)
1345                         goto err_close_channels;
1346         }
1347
1348         kfree(cparam);
1349         return 0;
1350
1351 err_close_channels:
1352         for (i--; i >= 0; i--)
1353                 mlx5e_close_channel(priv->channel[i]);
1354
1355 err_free_txq_to_sq_map:
1356         kfree(priv->txq_to_sq_map);
1357         kfree(priv->channel);
1358         kfree(cparam);
1359
1360         return err;
1361 }
1362
1363 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1364 {
1365         int i;
1366
1367         for (i = 0; i < priv->params.num_channels; i++)
1368                 mlx5e_close_channel(priv->channel[i]);
1369
1370         kfree(priv->txq_to_sq_map);
1371         kfree(priv->channel);
1372 }
1373
1374 static int mlx5e_rx_hash_fn(int hfunc)
1375 {
1376         return (hfunc == ETH_RSS_HASH_TOP) ?
1377                MLX5_RX_HASH_FN_TOEPLITZ :
1378                MLX5_RX_HASH_FN_INVERTED_XOR8;
1379 }
1380
1381 static int mlx5e_bits_invert(unsigned long a, int size)
1382 {
1383         int inv = 0;
1384         int i;
1385
1386         for (i = 0; i < size; i++)
1387                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1388
1389         return inv;
1390 }
1391
1392 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1393 {
1394         int i;
1395
1396         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1397                 int ix = i;
1398                 u32 rqn;
1399
1400                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1401                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1402
1403                 ix = priv->params.indirection_rqt[ix];
1404                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1405                                 priv->channel[ix]->rq.rqn :
1406                                 priv->drop_rq.rqn;
1407                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1408         }
1409 }
1410
1411 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1412                                       int ix)
1413 {
1414         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1415                         priv->channel[ix]->rq.rqn :
1416                         priv->drop_rq.rqn;
1417
1418         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1419 }
1420
1421 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, int ix, u32 *rqtn)
1422 {
1423         struct mlx5_core_dev *mdev = priv->mdev;
1424         void *rqtc;
1425         int inlen;
1426         int err;
1427         u32 *in;
1428
1429         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1430         in = mlx5_vzalloc(inlen);
1431         if (!in)
1432                 return -ENOMEM;
1433
1434         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1435
1436         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1437         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1438
1439         if (sz > 1) /* RSS */
1440                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1441         else
1442                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1443
1444         err = mlx5_core_create_rqt(mdev, in, inlen, rqtn);
1445
1446         kvfree(in);
1447         return err;
1448 }
1449
1450 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, u32 rqtn)
1451 {
1452         mlx5_core_destroy_rqt(priv->mdev, rqtn);
1453 }
1454
1455 static int mlx5e_create_rqts(struct mlx5e_priv *priv)
1456 {
1457         int nch = mlx5e_get_max_num_channels(priv->mdev);
1458         u32 *rqtn;
1459         int err;
1460         int ix;
1461
1462         /* Indirect RQT */
1463         rqtn = &priv->indir_rqtn;
1464         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqtn);
1465         if (err)
1466                 return err;
1467
1468         /* Direct RQTs */
1469         for (ix = 0; ix < nch; ix++) {
1470                 rqtn = &priv->direct_tir[ix].rqtn;
1471                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqtn);
1472                 if (err)
1473                         goto err_destroy_rqts;
1474         }
1475
1476         return 0;
1477
1478 err_destroy_rqts:
1479         for (ix--; ix >= 0; ix--)
1480                 mlx5e_destroy_rqt(priv, priv->direct_tir[ix].rqtn);
1481
1482         mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1483
1484         return err;
1485 }
1486
1487 static void mlx5e_destroy_rqts(struct mlx5e_priv *priv)
1488 {
1489         int nch = mlx5e_get_max_num_channels(priv->mdev);
1490         int i;
1491
1492         for (i = 0; i < nch; i++)
1493                 mlx5e_destroy_rqt(priv, priv->direct_tir[i].rqtn);
1494
1495         mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1496 }
1497
1498 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1499 {
1500         struct mlx5_core_dev *mdev = priv->mdev;
1501         void *rqtc;
1502         int inlen;
1503         u32 *in;
1504         int err;
1505
1506         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1507         in = mlx5_vzalloc(inlen);
1508         if (!in)
1509                 return -ENOMEM;
1510
1511         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1512
1513         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1514         if (sz > 1) /* RSS */
1515                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1516         else
1517                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1518
1519         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1520
1521         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1522
1523         kvfree(in);
1524
1525         return err;
1526 }
1527
1528 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1529 {
1530         u32 rqtn;
1531         int ix;
1532
1533         rqtn = priv->indir_rqtn;
1534         mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1535         for (ix = 0; ix < priv->params.num_channels; ix++) {
1536                 rqtn = priv->direct_tir[ix].rqtn;
1537                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1538         }
1539 }
1540
1541 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1542 {
1543         if (!priv->params.lro_en)
1544                 return;
1545
1546 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1547
1548         MLX5_SET(tirc, tirc, lro_enable_mask,
1549                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1550                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1551         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1552                  (priv->params.lro_wqe_sz -
1553                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1554         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1555                  MLX5_CAP_ETH(priv->mdev,
1556                               lro_timer_supported_periods[2]));
1557 }
1558
1559 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1560 {
1561         MLX5_SET(tirc, tirc, rx_hash_fn,
1562                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1563         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1564                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1565                                              rx_hash_toeplitz_key);
1566                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1567                                                rx_hash_toeplitz_key);
1568
1569                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1570                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1571         }
1572 }
1573
1574 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1575 {
1576         struct mlx5_core_dev *mdev = priv->mdev;
1577
1578         void *in;
1579         void *tirc;
1580         int inlen;
1581         int err;
1582         int tt;
1583         int ix;
1584
1585         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1586         in = mlx5_vzalloc(inlen);
1587         if (!in)
1588                 return -ENOMEM;
1589
1590         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1591         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1592
1593         mlx5e_build_tir_ctx_lro(tirc, priv);
1594
1595         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1596                 err = mlx5_core_modify_tir(mdev, priv->indir_tirn[tt], in,
1597                                            inlen);
1598                 if (err)
1599                         goto free_in;
1600         }
1601
1602         for (ix = 0; ix < mlx5e_get_max_num_channels(mdev); ix++) {
1603                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1604                                            in, inlen);
1605                 if (err)
1606                         goto free_in;
1607         }
1608
1609 free_in:
1610         kvfree(in);
1611
1612         return err;
1613 }
1614
1615 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1616 {
1617         void *in;
1618         int inlen;
1619         int err;
1620         int i;
1621
1622         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1623         in = mlx5_vzalloc(inlen);
1624         if (!in)
1625                 return -ENOMEM;
1626
1627         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1628
1629         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
1630                 err = mlx5_core_modify_tir(priv->mdev, priv->indir_tirn[i], in,
1631                                            inlen);
1632                 if (err)
1633                         return err;
1634         }
1635
1636         for (i = 0; i < priv->params.num_channels; i++) {
1637                 err = mlx5_core_modify_tir(priv->mdev,
1638                                            priv->direct_tir[i].tirn, in,
1639                                            inlen);
1640                 if (err)
1641                         return err;
1642         }
1643
1644         kvfree(in);
1645
1646         return 0;
1647 }
1648
1649 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1650 {
1651         struct mlx5_core_dev *mdev = priv->mdev;
1652         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1653         int err;
1654
1655         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1656         if (err)
1657                 return err;
1658
1659         /* Update vport context MTU */
1660         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1661         return 0;
1662 }
1663
1664 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1665 {
1666         struct mlx5_core_dev *mdev = priv->mdev;
1667         u16 hw_mtu = 0;
1668         int err;
1669
1670         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1671         if (err || !hw_mtu) /* fallback to port oper mtu */
1672                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1673
1674         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1675 }
1676
1677 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1678 {
1679         struct mlx5e_priv *priv = netdev_priv(netdev);
1680         u16 mtu;
1681         int err;
1682
1683         err = mlx5e_set_mtu(priv, netdev->mtu);
1684         if (err)
1685                 return err;
1686
1687         mlx5e_query_mtu(priv, &mtu);
1688         if (mtu != netdev->mtu)
1689                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1690                             __func__, mtu, netdev->mtu);
1691
1692         netdev->mtu = mtu;
1693         return 0;
1694 }
1695
1696 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1697 {
1698         struct mlx5e_priv *priv = netdev_priv(netdev);
1699         int nch = priv->params.num_channels;
1700         int ntc = priv->params.num_tc;
1701         int tc;
1702
1703         netdev_reset_tc(netdev);
1704
1705         if (ntc == 1)
1706                 return;
1707
1708         netdev_set_num_tc(netdev, ntc);
1709
1710         for (tc = 0; tc < ntc; tc++)
1711                 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1712 }
1713
1714 int mlx5e_open_locked(struct net_device *netdev)
1715 {
1716         struct mlx5e_priv *priv = netdev_priv(netdev);
1717         int num_txqs;
1718         int err;
1719
1720         set_bit(MLX5E_STATE_OPENED, &priv->state);
1721
1722         mlx5e_netdev_set_tcs(netdev);
1723
1724         num_txqs = priv->params.num_channels * priv->params.num_tc;
1725         netif_set_real_num_tx_queues(netdev, num_txqs);
1726         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1727
1728         err = mlx5e_set_dev_port_mtu(netdev);
1729         if (err)
1730                 goto err_clear_state_opened_flag;
1731
1732         err = mlx5e_open_channels(priv);
1733         if (err) {
1734                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1735                            __func__, err);
1736                 goto err_clear_state_opened_flag;
1737         }
1738
1739         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1740         if (err) {
1741                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1742                            __func__, err);
1743                 goto err_close_channels;
1744         }
1745
1746         mlx5e_redirect_rqts(priv);
1747         mlx5e_update_carrier(priv);
1748         mlx5e_timestamp_init(priv);
1749 #ifdef CONFIG_RFS_ACCEL
1750         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1751 #endif
1752
1753         queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1754
1755         return 0;
1756
1757 err_close_channels:
1758         mlx5e_close_channels(priv);
1759 err_clear_state_opened_flag:
1760         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1761         return err;
1762 }
1763
1764 static int mlx5e_open(struct net_device *netdev)
1765 {
1766         struct mlx5e_priv *priv = netdev_priv(netdev);
1767         int err;
1768
1769         mutex_lock(&priv->state_lock);
1770         err = mlx5e_open_locked(netdev);
1771         mutex_unlock(&priv->state_lock);
1772
1773         return err;
1774 }
1775
1776 int mlx5e_close_locked(struct net_device *netdev)
1777 {
1778         struct mlx5e_priv *priv = netdev_priv(netdev);
1779
1780         /* May already be CLOSED in case a previous configuration operation
1781          * (e.g RX/TX queue size change) that involves close&open failed.
1782          */
1783         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1784                 return 0;
1785
1786         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1787
1788         mlx5e_timestamp_cleanup(priv);
1789         netif_carrier_off(priv->netdev);
1790         mlx5e_redirect_rqts(priv);
1791         mlx5e_close_channels(priv);
1792
1793         return 0;
1794 }
1795
1796 static int mlx5e_close(struct net_device *netdev)
1797 {
1798         struct mlx5e_priv *priv = netdev_priv(netdev);
1799         int err;
1800
1801         mutex_lock(&priv->state_lock);
1802         err = mlx5e_close_locked(netdev);
1803         mutex_unlock(&priv->state_lock);
1804
1805         return err;
1806 }
1807
1808 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1809                                 struct mlx5e_rq *rq,
1810                                 struct mlx5e_rq_param *param)
1811 {
1812         struct mlx5_core_dev *mdev = priv->mdev;
1813         void *rqc = param->rqc;
1814         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1815         int err;
1816
1817         param->wq.db_numa_node = param->wq.buf_numa_node;
1818
1819         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1820                                 &rq->wq_ctrl);
1821         if (err)
1822                 return err;
1823
1824         rq->priv = priv;
1825
1826         return 0;
1827 }
1828
1829 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1830                                 struct mlx5e_cq *cq,
1831                                 struct mlx5e_cq_param *param)
1832 {
1833         struct mlx5_core_dev *mdev = priv->mdev;
1834         struct mlx5_core_cq *mcq = &cq->mcq;
1835         int eqn_not_used;
1836         unsigned int irqn;
1837         int err;
1838
1839         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1840                                &cq->wq_ctrl);
1841         if (err)
1842                 return err;
1843
1844         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1845
1846         mcq->cqe_sz     = 64;
1847         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1848         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1849         *mcq->set_ci_db = 0;
1850         *mcq->arm_db    = 0;
1851         mcq->vector     = param->eq_ix;
1852         mcq->comp       = mlx5e_completion_event;
1853         mcq->event      = mlx5e_cq_error_event;
1854         mcq->irqn       = irqn;
1855         mcq->uar        = &priv->cq_uar;
1856
1857         cq->priv = priv;
1858
1859         return 0;
1860 }
1861
1862 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1863 {
1864         struct mlx5e_cq_param cq_param;
1865         struct mlx5e_rq_param rq_param;
1866         struct mlx5e_rq *rq = &priv->drop_rq;
1867         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1868         int err;
1869
1870         memset(&cq_param, 0, sizeof(cq_param));
1871         memset(&rq_param, 0, sizeof(rq_param));
1872         mlx5e_build_drop_rq_param(&rq_param);
1873
1874         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1875         if (err)
1876                 return err;
1877
1878         err = mlx5e_enable_cq(cq, &cq_param);
1879         if (err)
1880                 goto err_destroy_cq;
1881
1882         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1883         if (err)
1884                 goto err_disable_cq;
1885
1886         err = mlx5e_enable_rq(rq, &rq_param);
1887         if (err)
1888                 goto err_destroy_rq;
1889
1890         return 0;
1891
1892 err_destroy_rq:
1893         mlx5e_destroy_rq(&priv->drop_rq);
1894
1895 err_disable_cq:
1896         mlx5e_disable_cq(&priv->drop_rq.cq);
1897
1898 err_destroy_cq:
1899         mlx5e_destroy_cq(&priv->drop_rq.cq);
1900
1901         return err;
1902 }
1903
1904 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1905 {
1906         mlx5e_disable_rq(&priv->drop_rq);
1907         mlx5e_destroy_rq(&priv->drop_rq);
1908         mlx5e_disable_cq(&priv->drop_rq.cq);
1909         mlx5e_destroy_cq(&priv->drop_rq.cq);
1910 }
1911
1912 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1913 {
1914         struct mlx5_core_dev *mdev = priv->mdev;
1915         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1916         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1917
1918         memset(in, 0, sizeof(in));
1919
1920         MLX5_SET(tisc, tisc, prio, tc << 1);
1921         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1922
1923         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1924 }
1925
1926 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1927 {
1928         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1929 }
1930
1931 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1932 {
1933         int err;
1934         int tc;
1935
1936         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1937                 err = mlx5e_create_tis(priv, tc);
1938                 if (err)
1939                         goto err_close_tises;
1940         }
1941
1942         return 0;
1943
1944 err_close_tises:
1945         for (tc--; tc >= 0; tc--)
1946                 mlx5e_destroy_tis(priv, tc);
1947
1948         return err;
1949 }
1950
1951 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1952 {
1953         int tc;
1954
1955         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1956                 mlx5e_destroy_tis(priv, tc);
1957 }
1958
1959 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
1960                                       enum mlx5e_traffic_types tt)
1961 {
1962         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1963
1964         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1965
1966 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1967                                  MLX5_HASH_FIELD_SEL_DST_IP)
1968
1969 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1970                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1971                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1972                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1973
1974 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1975                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1976                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1977
1978         mlx5e_build_tir_ctx_lro(tirc, priv);
1979
1980         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1981         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqtn);
1982         mlx5e_build_tir_ctx_hash(tirc, priv);
1983
1984         switch (tt) {
1985         case MLX5E_TT_IPV4_TCP:
1986                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1987                          MLX5_L3_PROT_TYPE_IPV4);
1988                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1989                          MLX5_L4_PROT_TYPE_TCP);
1990                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1991                          MLX5_HASH_IP_L4PORTS);
1992                 break;
1993
1994         case MLX5E_TT_IPV6_TCP:
1995                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1996                          MLX5_L3_PROT_TYPE_IPV6);
1997                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1998                          MLX5_L4_PROT_TYPE_TCP);
1999                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2000                          MLX5_HASH_IP_L4PORTS);
2001                 break;
2002
2003         case MLX5E_TT_IPV4_UDP:
2004                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2005                          MLX5_L3_PROT_TYPE_IPV4);
2006                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2007                          MLX5_L4_PROT_TYPE_UDP);
2008                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2009                          MLX5_HASH_IP_L4PORTS);
2010                 break;
2011
2012         case MLX5E_TT_IPV6_UDP:
2013                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2014                          MLX5_L3_PROT_TYPE_IPV6);
2015                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2016                          MLX5_L4_PROT_TYPE_UDP);
2017                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2018                          MLX5_HASH_IP_L4PORTS);
2019                 break;
2020
2021         case MLX5E_TT_IPV4_IPSEC_AH:
2022                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2023                          MLX5_L3_PROT_TYPE_IPV4);
2024                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2025                          MLX5_HASH_IP_IPSEC_SPI);
2026                 break;
2027
2028         case MLX5E_TT_IPV6_IPSEC_AH:
2029                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2030                          MLX5_L3_PROT_TYPE_IPV6);
2031                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2032                          MLX5_HASH_IP_IPSEC_SPI);
2033                 break;
2034
2035         case MLX5E_TT_IPV4_IPSEC_ESP:
2036                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2037                          MLX5_L3_PROT_TYPE_IPV4);
2038                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2039                          MLX5_HASH_IP_IPSEC_SPI);
2040                 break;
2041
2042         case MLX5E_TT_IPV6_IPSEC_ESP:
2043                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2044                          MLX5_L3_PROT_TYPE_IPV6);
2045                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2046                          MLX5_HASH_IP_IPSEC_SPI);
2047                 break;
2048
2049         case MLX5E_TT_IPV4:
2050                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2051                          MLX5_L3_PROT_TYPE_IPV4);
2052                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2053                          MLX5_HASH_IP);
2054                 break;
2055
2056         case MLX5E_TT_IPV6:
2057                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2058                          MLX5_L3_PROT_TYPE_IPV6);
2059                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2060                          MLX5_HASH_IP);
2061                 break;
2062         default:
2063                 WARN_ONCE(true,
2064                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2065         }
2066 }
2067
2068 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2069                                        u32 rqtn)
2070 {
2071         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2072
2073         mlx5e_build_tir_ctx_lro(tirc, priv);
2074
2075         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2076         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2077         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2078 }
2079
2080 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
2081 {
2082         int nch = mlx5e_get_max_num_channels(priv->mdev);
2083         void *tirc;
2084         int inlen;
2085         u32 *tirn;
2086         int err;
2087         u32 *in;
2088         int ix;
2089         int tt;
2090
2091         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2092         in = mlx5_vzalloc(inlen);
2093         if (!in)
2094                 return -ENOMEM;
2095
2096         /* indirect tirs */
2097         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2098                 memset(in, 0, inlen);
2099                 tirn = &priv->indir_tirn[tt];
2100                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2101                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2102                 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2103                 if (err)
2104                         goto err_destroy_tirs;
2105         }
2106
2107         /* direct tirs */
2108         for (ix = 0; ix < nch; ix++) {
2109                 memset(in, 0, inlen);
2110                 tirn = &priv->direct_tir[ix].tirn;
2111                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2112                 mlx5e_build_direct_tir_ctx(priv, tirc,
2113                                            priv->direct_tir[ix].rqtn);
2114                 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2115                 if (err)
2116                         goto err_destroy_ch_tirs;
2117         }
2118
2119         kvfree(in);
2120
2121         return 0;
2122
2123 err_destroy_ch_tirs:
2124         for (ix--; ix >= 0; ix--)
2125                 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[ix].tirn);
2126
2127 err_destroy_tirs:
2128         for (tt--; tt >= 0; tt--)
2129                 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[tt]);
2130
2131         kvfree(in);
2132
2133         return err;
2134 }
2135
2136 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
2137 {
2138         int nch = mlx5e_get_max_num_channels(priv->mdev);
2139         int i;
2140
2141         for (i = 0; i < nch; i++)
2142                 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[i].tirn);
2143
2144         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2145                 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[i]);
2146 }
2147
2148 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2149 {
2150         int err = 0;
2151         int i;
2152
2153         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2154                 return 0;
2155
2156         for (i = 0; i < priv->params.num_channels; i++) {
2157                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2158                 if (err)
2159                         return err;
2160         }
2161
2162         return 0;
2163 }
2164
2165 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2166 {
2167         struct mlx5e_priv *priv = netdev_priv(netdev);
2168         bool was_opened;
2169         int err = 0;
2170
2171         if (tc && tc != MLX5E_MAX_NUM_TC)
2172                 return -EINVAL;
2173
2174         mutex_lock(&priv->state_lock);
2175
2176         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2177         if (was_opened)
2178                 mlx5e_close_locked(priv->netdev);
2179
2180         priv->params.num_tc = tc ? tc : 1;
2181
2182         if (was_opened)
2183                 err = mlx5e_open_locked(priv->netdev);
2184
2185         mutex_unlock(&priv->state_lock);
2186
2187         return err;
2188 }
2189
2190 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2191                               __be16 proto, struct tc_to_netdev *tc)
2192 {
2193         struct mlx5e_priv *priv = netdev_priv(dev);
2194
2195         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2196                 goto mqprio;
2197
2198         switch (tc->type) {
2199         case TC_SETUP_CLSFLOWER:
2200                 switch (tc->cls_flower->command) {
2201                 case TC_CLSFLOWER_REPLACE:
2202                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2203                 case TC_CLSFLOWER_DESTROY:
2204                         return mlx5e_delete_flower(priv, tc->cls_flower);
2205                 case TC_CLSFLOWER_STATS:
2206                         return mlx5e_stats_flower(priv, tc->cls_flower);
2207                 }
2208         default:
2209                 return -EOPNOTSUPP;
2210         }
2211
2212 mqprio:
2213         if (tc->type != TC_SETUP_MQPRIO)
2214                 return -EINVAL;
2215
2216         return mlx5e_setup_tc(dev, tc->tc);
2217 }
2218
2219 static struct rtnl_link_stats64 *
2220 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2221 {
2222         struct mlx5e_priv *priv = netdev_priv(dev);
2223         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2224         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2225         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2226
2227         stats->rx_packets = sstats->rx_packets;
2228         stats->rx_bytes   = sstats->rx_bytes;
2229         stats->tx_packets = sstats->tx_packets;
2230         stats->tx_bytes   = sstats->tx_bytes;
2231
2232         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2233         stats->tx_dropped = sstats->tx_queue_dropped;
2234
2235         stats->rx_length_errors =
2236                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2237                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2238                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2239         stats->rx_crc_errors =
2240                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2241         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2242         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2243         stats->tx_carrier_errors =
2244                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2245         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2246                            stats->rx_frame_errors;
2247         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2248
2249         /* vport multicast also counts packets that are dropped due to steering
2250          * or rx out of buffer
2251          */
2252         stats->multicast =
2253                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2254
2255         return stats;
2256 }
2257
2258 static void mlx5e_set_rx_mode(struct net_device *dev)
2259 {
2260         struct mlx5e_priv *priv = netdev_priv(dev);
2261
2262         queue_work(priv->wq, &priv->set_rx_mode_work);
2263 }
2264
2265 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2266 {
2267         struct mlx5e_priv *priv = netdev_priv(netdev);
2268         struct sockaddr *saddr = addr;
2269
2270         if (!is_valid_ether_addr(saddr->sa_data))
2271                 return -EADDRNOTAVAIL;
2272
2273         netif_addr_lock_bh(netdev);
2274         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2275         netif_addr_unlock_bh(netdev);
2276
2277         queue_work(priv->wq, &priv->set_rx_mode_work);
2278
2279         return 0;
2280 }
2281
2282 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2283         do {                                            \
2284                 if (enable)                             \
2285                         netdev->features |= feature;    \
2286                 else                                    \
2287                         netdev->features &= ~feature;   \
2288         } while (0)
2289
2290 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2291
2292 static int set_feature_lro(struct net_device *netdev, bool enable)
2293 {
2294         struct mlx5e_priv *priv = netdev_priv(netdev);
2295         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2296         int err;
2297
2298         mutex_lock(&priv->state_lock);
2299
2300         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2301                 mlx5e_close_locked(priv->netdev);
2302
2303         priv->params.lro_en = enable;
2304         err = mlx5e_modify_tirs_lro(priv);
2305         if (err) {
2306                 netdev_err(netdev, "lro modify failed, %d\n", err);
2307                 priv->params.lro_en = !enable;
2308         }
2309
2310         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2311                 mlx5e_open_locked(priv->netdev);
2312
2313         mutex_unlock(&priv->state_lock);
2314
2315         return err;
2316 }
2317
2318 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2319 {
2320         struct mlx5e_priv *priv = netdev_priv(netdev);
2321
2322         if (enable)
2323                 mlx5e_enable_vlan_filter(priv);
2324         else
2325                 mlx5e_disable_vlan_filter(priv);
2326
2327         return 0;
2328 }
2329
2330 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2331 {
2332         struct mlx5e_priv *priv = netdev_priv(netdev);
2333
2334         if (!enable && mlx5e_tc_num_filters(priv)) {
2335                 netdev_err(netdev,
2336                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2337                 return -EINVAL;
2338         }
2339
2340         return 0;
2341 }
2342
2343 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2344 {
2345         struct mlx5e_priv *priv = netdev_priv(netdev);
2346         struct mlx5_core_dev *mdev = priv->mdev;
2347
2348         return mlx5_set_port_fcs(mdev, !enable);
2349 }
2350
2351 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2352 {
2353         struct mlx5e_priv *priv = netdev_priv(netdev);
2354         int err;
2355
2356         mutex_lock(&priv->state_lock);
2357
2358         priv->params.vlan_strip_disable = !enable;
2359         err = mlx5e_modify_rqs_vsd(priv, !enable);
2360         if (err)
2361                 priv->params.vlan_strip_disable = enable;
2362
2363         mutex_unlock(&priv->state_lock);
2364
2365         return err;
2366 }
2367
2368 #ifdef CONFIG_RFS_ACCEL
2369 static int set_feature_arfs(struct net_device *netdev, bool enable)
2370 {
2371         struct mlx5e_priv *priv = netdev_priv(netdev);
2372         int err;
2373
2374         if (enable)
2375                 err = mlx5e_arfs_enable(priv);
2376         else
2377                 err = mlx5e_arfs_disable(priv);
2378
2379         return err;
2380 }
2381 #endif
2382
2383 static int mlx5e_handle_feature(struct net_device *netdev,
2384                                 netdev_features_t wanted_features,
2385                                 netdev_features_t feature,
2386                                 mlx5e_feature_handler feature_handler)
2387 {
2388         netdev_features_t changes = wanted_features ^ netdev->features;
2389         bool enable = !!(wanted_features & feature);
2390         int err;
2391
2392         if (!(changes & feature))
2393                 return 0;
2394
2395         err = feature_handler(netdev, enable);
2396         if (err) {
2397                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2398                            enable ? "Enable" : "Disable", feature, err);
2399                 return err;
2400         }
2401
2402         MLX5E_SET_FEATURE(netdev, feature, enable);
2403         return 0;
2404 }
2405
2406 static int mlx5e_set_features(struct net_device *netdev,
2407                               netdev_features_t features)
2408 {
2409         int err;
2410
2411         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2412                                     set_feature_lro);
2413         err |= mlx5e_handle_feature(netdev, features,
2414                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2415                                     set_feature_vlan_filter);
2416         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2417                                     set_feature_tc_num_filters);
2418         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2419                                     set_feature_rx_all);
2420         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2421                                     set_feature_rx_vlan);
2422 #ifdef CONFIG_RFS_ACCEL
2423         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2424                                     set_feature_arfs);
2425 #endif
2426
2427         return err ? -EINVAL : 0;
2428 }
2429
2430 #define MXL5_HW_MIN_MTU 64
2431 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2432
2433 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2434 {
2435         struct mlx5e_priv *priv = netdev_priv(netdev);
2436         struct mlx5_core_dev *mdev = priv->mdev;
2437         bool was_opened;
2438         u16 max_mtu;
2439         u16 min_mtu;
2440         int err = 0;
2441
2442         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2443
2444         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2445         min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2446
2447         if (new_mtu > max_mtu || new_mtu < min_mtu) {
2448                 netdev_err(netdev,
2449                            "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2450                            __func__, new_mtu, min_mtu, max_mtu);
2451                 return -EINVAL;
2452         }
2453
2454         mutex_lock(&priv->state_lock);
2455
2456         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2457         if (was_opened)
2458                 mlx5e_close_locked(netdev);
2459
2460         netdev->mtu = new_mtu;
2461
2462         if (was_opened)
2463                 err = mlx5e_open_locked(netdev);
2464
2465         mutex_unlock(&priv->state_lock);
2466
2467         return err;
2468 }
2469
2470 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2471 {
2472         switch (cmd) {
2473         case SIOCSHWTSTAMP:
2474                 return mlx5e_hwstamp_set(dev, ifr);
2475         case SIOCGHWTSTAMP:
2476                 return mlx5e_hwstamp_get(dev, ifr);
2477         default:
2478                 return -EOPNOTSUPP;
2479         }
2480 }
2481
2482 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2483 {
2484         struct mlx5e_priv *priv = netdev_priv(dev);
2485         struct mlx5_core_dev *mdev = priv->mdev;
2486
2487         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2488 }
2489
2490 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2491 {
2492         struct mlx5e_priv *priv = netdev_priv(dev);
2493         struct mlx5_core_dev *mdev = priv->mdev;
2494
2495         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2496                                            vlan, qos);
2497 }
2498
2499 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2500 {
2501         struct mlx5e_priv *priv = netdev_priv(dev);
2502         struct mlx5_core_dev *mdev = priv->mdev;
2503
2504         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2505 }
2506
2507 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2508 {
2509         struct mlx5e_priv *priv = netdev_priv(dev);
2510         struct mlx5_core_dev *mdev = priv->mdev;
2511
2512         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2513 }
2514 static int mlx5_vport_link2ifla(u8 esw_link)
2515 {
2516         switch (esw_link) {
2517         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2518                 return IFLA_VF_LINK_STATE_DISABLE;
2519         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2520                 return IFLA_VF_LINK_STATE_ENABLE;
2521         }
2522         return IFLA_VF_LINK_STATE_AUTO;
2523 }
2524
2525 static int mlx5_ifla_link2vport(u8 ifla_link)
2526 {
2527         switch (ifla_link) {
2528         case IFLA_VF_LINK_STATE_DISABLE:
2529                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2530         case IFLA_VF_LINK_STATE_ENABLE:
2531                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2532         }
2533         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2534 }
2535
2536 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2537                                    int link_state)
2538 {
2539         struct mlx5e_priv *priv = netdev_priv(dev);
2540         struct mlx5_core_dev *mdev = priv->mdev;
2541
2542         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2543                                             mlx5_ifla_link2vport(link_state));
2544 }
2545
2546 static int mlx5e_get_vf_config(struct net_device *dev,
2547                                int vf, struct ifla_vf_info *ivi)
2548 {
2549         struct mlx5e_priv *priv = netdev_priv(dev);
2550         struct mlx5_core_dev *mdev = priv->mdev;
2551         int err;
2552
2553         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2554         if (err)
2555                 return err;
2556         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2557         return 0;
2558 }
2559
2560 static int mlx5e_get_vf_stats(struct net_device *dev,
2561                               int vf, struct ifla_vf_stats *vf_stats)
2562 {
2563         struct mlx5e_priv *priv = netdev_priv(dev);
2564         struct mlx5_core_dev *mdev = priv->mdev;
2565
2566         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2567                                             vf_stats);
2568 }
2569
2570 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2571                                  sa_family_t sa_family, __be16 port)
2572 {
2573         struct mlx5e_priv *priv = netdev_priv(netdev);
2574
2575         if (!mlx5e_vxlan_allowed(priv->mdev))
2576                 return;
2577
2578         mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 1);
2579 }
2580
2581 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2582                                  sa_family_t sa_family, __be16 port)
2583 {
2584         struct mlx5e_priv *priv = netdev_priv(netdev);
2585
2586         if (!mlx5e_vxlan_allowed(priv->mdev))
2587                 return;
2588
2589         mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 0);
2590 }
2591
2592 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2593                                                     struct sk_buff *skb,
2594                                                     netdev_features_t features)
2595 {
2596         struct udphdr *udph;
2597         u16 proto;
2598         u16 port = 0;
2599
2600         switch (vlan_get_protocol(skb)) {
2601         case htons(ETH_P_IP):
2602                 proto = ip_hdr(skb)->protocol;
2603                 break;
2604         case htons(ETH_P_IPV6):
2605                 proto = ipv6_hdr(skb)->nexthdr;
2606                 break;
2607         default:
2608                 goto out;
2609         }
2610
2611         if (proto == IPPROTO_UDP) {
2612                 udph = udp_hdr(skb);
2613                 port = be16_to_cpu(udph->dest);
2614         }
2615
2616         /* Verify if UDP port is being offloaded by HW */
2617         if (port && mlx5e_vxlan_lookup_port(priv, port))
2618                 return features;
2619
2620 out:
2621         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2622         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2623 }
2624
2625 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2626                                               struct net_device *netdev,
2627                                               netdev_features_t features)
2628 {
2629         struct mlx5e_priv *priv = netdev_priv(netdev);
2630
2631         features = vlan_features_check(skb, features);
2632         features = vxlan_features_check(skb, features);
2633
2634         /* Validate if the tunneled packet is being offloaded by HW */
2635         if (skb->encapsulation &&
2636             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2637                 return mlx5e_vxlan_features_check(priv, skb, features);
2638
2639         return features;
2640 }
2641
2642 static void mlx5e_tx_timeout(struct net_device *dev)
2643 {
2644         struct mlx5e_priv *priv = netdev_priv(dev);
2645         bool sched_work = false;
2646         int i;
2647
2648         netdev_err(dev, "TX timeout detected\n");
2649
2650         for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
2651                 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
2652
2653                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i)))
2654                         continue;
2655                 sched_work = true;
2656                 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
2657                 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
2658                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
2659         }
2660
2661         if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
2662                 schedule_work(&priv->tx_timeout_work);
2663 }
2664
2665 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2666         .ndo_open                = mlx5e_open,
2667         .ndo_stop                = mlx5e_close,
2668         .ndo_start_xmit          = mlx5e_xmit,
2669         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2670         .ndo_select_queue        = mlx5e_select_queue,
2671         .ndo_get_stats64         = mlx5e_get_stats,
2672         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2673         .ndo_set_mac_address     = mlx5e_set_mac,
2674         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2675         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2676         .ndo_set_features        = mlx5e_set_features,
2677         .ndo_change_mtu          = mlx5e_change_mtu,
2678         .ndo_do_ioctl            = mlx5e_ioctl,
2679 #ifdef CONFIG_RFS_ACCEL
2680         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2681 #endif
2682         .ndo_tx_timeout          = mlx5e_tx_timeout,
2683 };
2684
2685 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2686         .ndo_open                = mlx5e_open,
2687         .ndo_stop                = mlx5e_close,
2688         .ndo_start_xmit          = mlx5e_xmit,
2689         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2690         .ndo_select_queue        = mlx5e_select_queue,
2691         .ndo_get_stats64         = mlx5e_get_stats,
2692         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2693         .ndo_set_mac_address     = mlx5e_set_mac,
2694         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2695         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2696         .ndo_set_features        = mlx5e_set_features,
2697         .ndo_change_mtu          = mlx5e_change_mtu,
2698         .ndo_do_ioctl            = mlx5e_ioctl,
2699         .ndo_add_vxlan_port      = mlx5e_add_vxlan_port,
2700         .ndo_del_vxlan_port      = mlx5e_del_vxlan_port,
2701         .ndo_features_check      = mlx5e_features_check,
2702 #ifdef CONFIG_RFS_ACCEL
2703         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2704 #endif
2705         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2706         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2707         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
2708         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
2709         .ndo_get_vf_config       = mlx5e_get_vf_config,
2710         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2711         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2712         .ndo_tx_timeout          = mlx5e_tx_timeout,
2713 };
2714
2715 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2716 {
2717         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2718                 return -ENOTSUPP;
2719         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2720             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2721             !MLX5_CAP_ETH(mdev, csum_cap) ||
2722             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2723             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2724             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2725             MLX5_CAP_FLOWTABLE(mdev,
2726                                flow_table_properties_nic_receive.max_ft_level)
2727                                < 3) {
2728                 mlx5_core_warn(mdev,
2729                                "Not creating net device, some required device capabilities are missing\n");
2730                 return -ENOTSUPP;
2731         }
2732         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2733                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2734         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2735                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2736
2737         return 0;
2738 }
2739
2740 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2741 {
2742         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2743
2744         return bf_buf_size -
2745                sizeof(struct mlx5e_tx_wqe) +
2746                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2747 }
2748
2749 #ifdef CONFIG_MLX5_CORE_EN_DCB
2750 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2751 {
2752         int i;
2753
2754         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2755         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2756                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2757                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2758                 priv->params.ets.prio_tc[i] = i;
2759         }
2760
2761         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2762         priv->params.ets.prio_tc[0] = 1;
2763         priv->params.ets.prio_tc[1] = 0;
2764 }
2765 #endif
2766
2767 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2768                                    u32 *indirection_rqt, int len,
2769                                    int num_channels)
2770 {
2771         int node = mdev->priv.numa_node;
2772         int node_num_of_cores;
2773         int i;
2774
2775         if (node == -1)
2776                 node = first_online_node;
2777
2778         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2779
2780         if (node_num_of_cores)
2781                 num_channels = min_t(int, num_channels, node_num_of_cores);
2782
2783         for (i = 0; i < len; i++)
2784                 indirection_rqt[i] = i % num_channels;
2785 }
2786
2787 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2788 {
2789         return MLX5_CAP_GEN(mdev, striding_rq) &&
2790                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2791                 MLX5_CAP_ETH(mdev, reg_umr_sq);
2792 }
2793
2794 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2795 {
2796         enum pcie_link_width width;
2797         enum pci_bus_speed speed;
2798         int err = 0;
2799
2800         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2801         if (err)
2802                 return err;
2803
2804         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2805                 return -EINVAL;
2806
2807         switch (speed) {
2808         case PCIE_SPEED_2_5GT:
2809                 *pci_bw = 2500 * width;
2810                 break;
2811         case PCIE_SPEED_5_0GT:
2812                 *pci_bw = 5000 * width;
2813                 break;
2814         case PCIE_SPEED_8_0GT:
2815                 *pci_bw = 8000 * width;
2816                 break;
2817         default:
2818                 return -EINVAL;
2819         }
2820
2821         return 0;
2822 }
2823
2824 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2825 {
2826         return (link_speed && pci_bw &&
2827                 (pci_bw < 40000) && (pci_bw < link_speed));
2828 }
2829
2830 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2831                                     struct net_device *netdev,
2832                                     int num_channels)
2833 {
2834         struct mlx5e_priv *priv = netdev_priv(netdev);
2835         u32 link_speed = 0;
2836         u32 pci_bw = 0;
2837
2838         priv->params.log_sq_size           =
2839                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2840         priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
2841                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2842                 MLX5_WQ_TYPE_LINKED_LIST;
2843
2844         /* set CQE compression */
2845         priv->params.rx_cqe_compress_admin = false;
2846         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
2847             MLX5_CAP_GEN(mdev, vport_group_manager)) {
2848                 mlx5e_get_max_linkspeed(mdev, &link_speed);
2849                 mlx5e_get_pci_bw(mdev, &pci_bw);
2850                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
2851                               link_speed, pci_bw);
2852                 priv->params.rx_cqe_compress_admin =
2853                         cqe_compress_heuristic(link_speed, pci_bw);
2854         }
2855
2856         priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
2857
2858         switch (priv->params.rq_wq_type) {
2859         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2860                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2861                 priv->params.mpwqe_log_stride_sz =
2862                         priv->params.rx_cqe_compress ?
2863                         MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
2864                         MLX5_MPWRQ_LOG_STRIDE_SIZE;
2865                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
2866                         priv->params.mpwqe_log_stride_sz;
2867                 priv->params.lro_en = true;
2868                 break;
2869         default: /* MLX5_WQ_TYPE_LINKED_LIST */
2870                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2871         }
2872
2873         mlx5_core_info(mdev,
2874                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
2875                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
2876                        BIT(priv->params.log_rq_size),
2877                        BIT(priv->params.mpwqe_log_stride_sz),
2878                        priv->params.rx_cqe_compress_admin);
2879
2880         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2881                                             BIT(priv->params.log_rq_size));
2882         priv->params.rx_cq_moderation_usec =
2883                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2884         priv->params.rx_cq_moderation_pkts =
2885                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2886         priv->params.tx_cq_moderation_usec =
2887                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2888         priv->params.tx_cq_moderation_pkts =
2889                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2890         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
2891         priv->params.num_tc                = 1;
2892         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2893
2894         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2895                             sizeof(priv->params.toeplitz_hash_key));
2896
2897         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2898                                       MLX5E_INDIR_RQT_SIZE, num_channels);
2899
2900         priv->params.lro_wqe_sz            =
2901                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2902
2903         priv->mdev                         = mdev;
2904         priv->netdev                       = netdev;
2905         priv->params.num_channels          = num_channels;
2906
2907 #ifdef CONFIG_MLX5_CORE_EN_DCB
2908         mlx5e_ets_init(priv);
2909 #endif
2910
2911         mutex_init(&priv->state_lock);
2912
2913         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2914         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2915         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
2916         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2917 }
2918
2919 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2920 {
2921         struct mlx5e_priv *priv = netdev_priv(netdev);
2922
2923         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2924         if (is_zero_ether_addr(netdev->dev_addr) &&
2925             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2926                 eth_hw_addr_random(netdev);
2927                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2928         }
2929 }
2930
2931 static void mlx5e_build_netdev(struct net_device *netdev)
2932 {
2933         struct mlx5e_priv *priv = netdev_priv(netdev);
2934         struct mlx5_core_dev *mdev = priv->mdev;
2935         bool fcs_supported;
2936         bool fcs_enabled;
2937
2938         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2939
2940         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2941                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2942 #ifdef CONFIG_MLX5_CORE_EN_DCB
2943                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2944 #endif
2945         } else {
2946                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2947         }
2948
2949         netdev->watchdog_timeo    = 15 * HZ;
2950
2951         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
2952
2953         netdev->vlan_features    |= NETIF_F_SG;
2954         netdev->vlan_features    |= NETIF_F_IP_CSUM;
2955         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
2956         netdev->vlan_features    |= NETIF_F_GRO;
2957         netdev->vlan_features    |= NETIF_F_TSO;
2958         netdev->vlan_features    |= NETIF_F_TSO6;
2959         netdev->vlan_features    |= NETIF_F_RXCSUM;
2960         netdev->vlan_features    |= NETIF_F_RXHASH;
2961
2962         if (!!MLX5_CAP_ETH(mdev, lro_cap))
2963                 netdev->vlan_features    |= NETIF_F_LRO;
2964
2965         netdev->hw_features       = netdev->vlan_features;
2966         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
2967         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
2968         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
2969
2970         if (mlx5e_vxlan_allowed(mdev)) {
2971                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
2972                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
2973                                            NETIF_F_GSO_PARTIAL;
2974                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2975                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
2976                 netdev->hw_enc_features |= NETIF_F_TSO;
2977                 netdev->hw_enc_features |= NETIF_F_TSO6;
2978                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2979                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
2980                                            NETIF_F_GSO_PARTIAL;
2981                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
2982         }
2983
2984         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
2985
2986         if (fcs_supported)
2987                 netdev->hw_features |= NETIF_F_RXALL;
2988
2989         netdev->features          = netdev->hw_features;
2990         if (!priv->params.lro_en)
2991                 netdev->features  &= ~NETIF_F_LRO;
2992
2993         if (fcs_enabled)
2994                 netdev->features  &= ~NETIF_F_RXALL;
2995
2996 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2997         if (FT_CAP(flow_modify_en) &&
2998             FT_CAP(modify_root) &&
2999             FT_CAP(identified_miss_table_mode) &&
3000             FT_CAP(flow_table_modify)) {
3001                 netdev->hw_features      |= NETIF_F_HW_TC;
3002 #ifdef CONFIG_RFS_ACCEL
3003                 netdev->hw_features      |= NETIF_F_NTUPLE;
3004 #endif
3005         }
3006
3007         netdev->features         |= NETIF_F_HIGHDMA;
3008
3009         netdev->priv_flags       |= IFF_UNICAST_FLT;
3010
3011         mlx5e_set_netdev_dev_addr(netdev);
3012 }
3013
3014 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3015                              struct mlx5_core_mkey *mkey)
3016 {
3017         struct mlx5_core_dev *mdev = priv->mdev;
3018         struct mlx5_create_mkey_mbox_in *in;
3019         int err;
3020
3021         in = mlx5_vzalloc(sizeof(*in));
3022         if (!in)
3023                 return -ENOMEM;
3024
3025         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
3026                         MLX5_PERM_LOCAL_READ  |
3027                         MLX5_ACCESS_MODE_PA;
3028         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
3029         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3030
3031         err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
3032                                     NULL);
3033
3034         kvfree(in);
3035
3036         return err;
3037 }
3038
3039 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3040 {
3041         struct mlx5_core_dev *mdev = priv->mdev;
3042         int err;
3043
3044         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3045         if (err) {
3046                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3047                 priv->q_counter = 0;
3048         }
3049 }
3050
3051 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3052 {
3053         if (!priv->q_counter)
3054                 return;
3055
3056         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3057 }
3058
3059 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3060 {
3061         struct mlx5_core_dev *mdev = priv->mdev;
3062         struct mlx5_create_mkey_mbox_in *in;
3063         struct mlx5_mkey_seg *mkc;
3064         int inlen = sizeof(*in);
3065         u64 npages =
3066                 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
3067         int err;
3068
3069         in = mlx5_vzalloc(inlen);
3070         if (!in)
3071                 return -ENOMEM;
3072
3073         mkc = &in->seg;
3074         mkc->status = MLX5_MKEY_STATUS_FREE;
3075         mkc->flags = MLX5_PERM_UMR_EN |
3076                      MLX5_PERM_LOCAL_READ |
3077                      MLX5_PERM_LOCAL_WRITE |
3078                      MLX5_ACCESS_MODE_MTT;
3079
3080         mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3081         mkc->flags_pd = cpu_to_be32(priv->pdn);
3082         mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
3083         mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
3084         mkc->log2_page_size = PAGE_SHIFT;
3085
3086         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
3087                                     NULL, NULL);
3088
3089         kvfree(in);
3090
3091         return err;
3092 }
3093
3094 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
3095 {
3096         struct net_device *netdev;
3097         struct mlx5e_priv *priv;
3098         int nch = mlx5e_get_max_num_channels(mdev);
3099         int err;
3100
3101         if (mlx5e_check_required_hca_cap(mdev))
3102                 return NULL;
3103
3104         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3105                                     nch * MLX5E_MAX_NUM_TC,
3106                                     nch);
3107         if (!netdev) {
3108                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3109                 return NULL;
3110         }
3111
3112         mlx5e_build_netdev_priv(mdev, netdev, nch);
3113         mlx5e_build_netdev(netdev);
3114
3115         netif_carrier_off(netdev);
3116
3117         priv = netdev_priv(netdev);
3118
3119         priv->wq = create_singlethread_workqueue("mlx5e");
3120         if (!priv->wq)
3121                 goto err_free_netdev;
3122
3123         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
3124         if (err) {
3125                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
3126                 goto err_destroy_wq;
3127         }
3128
3129         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3130         if (err) {
3131                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
3132                 goto err_unmap_free_uar;
3133         }
3134
3135         err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
3136         if (err) {
3137                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3138                 goto err_dealloc_pd;
3139         }
3140
3141         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
3142         if (err) {
3143                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3144                 goto err_dealloc_transport_domain;
3145         }
3146
3147         err = mlx5e_create_umr_mkey(priv);
3148         if (err) {
3149                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3150                 goto err_destroy_mkey;
3151         }
3152
3153         err = mlx5e_create_tises(priv);
3154         if (err) {
3155                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
3156                 goto err_destroy_umr_mkey;
3157         }
3158
3159         err = mlx5e_open_drop_rq(priv);
3160         if (err) {
3161                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3162                 goto err_destroy_tises;
3163         }
3164
3165         err = mlx5e_create_rqts(priv);
3166         if (err) {
3167                 mlx5_core_warn(mdev, "create rqts failed, %d\n", err);
3168                 goto err_close_drop_rq;
3169         }
3170
3171         err = mlx5e_create_tirs(priv);
3172         if (err) {
3173                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
3174                 goto err_destroy_rqts;
3175         }
3176
3177         err = mlx5e_create_flow_steering(priv);
3178         if (err) {
3179                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3180                 goto err_destroy_tirs;
3181         }
3182
3183         mlx5e_create_q_counter(priv);
3184
3185         mlx5e_init_l2_addr(priv);
3186
3187         mlx5e_vxlan_init(priv);
3188
3189         err = mlx5e_tc_init(priv);
3190         if (err)
3191                 goto err_dealloc_q_counters;
3192
3193 #ifdef CONFIG_MLX5_CORE_EN_DCB
3194         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3195 #endif
3196
3197         err = register_netdev(netdev);
3198         if (err) {
3199                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3200                 goto err_tc_cleanup;
3201         }
3202
3203         if (mlx5e_vxlan_allowed(mdev)) {
3204                 rtnl_lock();
3205                 vxlan_get_rx_port(netdev);
3206                 rtnl_unlock();
3207         }
3208
3209         mlx5e_enable_async_events(priv);
3210         queue_work(priv->wq, &priv->set_rx_mode_work);
3211
3212         return priv;
3213
3214 err_tc_cleanup:
3215         mlx5e_tc_cleanup(priv);
3216
3217 err_dealloc_q_counters:
3218         mlx5e_destroy_q_counter(priv);
3219         mlx5e_destroy_flow_steering(priv);
3220
3221 err_destroy_tirs:
3222         mlx5e_destroy_tirs(priv);
3223
3224 err_destroy_rqts:
3225         mlx5e_destroy_rqts(priv);
3226
3227 err_close_drop_rq:
3228         mlx5e_close_drop_rq(priv);
3229
3230 err_destroy_tises:
3231         mlx5e_destroy_tises(priv);
3232
3233 err_destroy_umr_mkey:
3234         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3235
3236 err_destroy_mkey:
3237         mlx5_core_destroy_mkey(mdev, &priv->mkey);
3238
3239 err_dealloc_transport_domain:
3240         mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3241
3242 err_dealloc_pd:
3243         mlx5_core_dealloc_pd(mdev, priv->pdn);
3244
3245 err_unmap_free_uar:
3246         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3247
3248 err_destroy_wq:
3249         destroy_workqueue(priv->wq);
3250
3251 err_free_netdev:
3252         free_netdev(netdev);
3253
3254         return NULL;
3255 }
3256
3257 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
3258 {
3259         struct mlx5e_priv *priv = vpriv;
3260         struct net_device *netdev = priv->netdev;
3261
3262         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3263
3264         queue_work(priv->wq, &priv->set_rx_mode_work);
3265         mlx5e_disable_async_events(priv);
3266         flush_workqueue(priv->wq);
3267         if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3268                 netif_device_detach(netdev);
3269                 mlx5e_close(netdev);
3270         } else {
3271                 unregister_netdev(netdev);
3272         }
3273
3274         mlx5e_tc_cleanup(priv);
3275         mlx5e_vxlan_cleanup(priv);
3276         mlx5e_destroy_q_counter(priv);
3277         mlx5e_destroy_flow_steering(priv);
3278         mlx5e_destroy_tirs(priv);
3279         mlx5e_destroy_rqts(priv);
3280         mlx5e_close_drop_rq(priv);
3281         mlx5e_destroy_tises(priv);
3282         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3283         mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
3284         mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
3285         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3286         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3287         cancel_delayed_work_sync(&priv->update_stats_work);
3288         destroy_workqueue(priv->wq);
3289
3290         if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3291                 free_netdev(netdev);
3292 }
3293
3294 static void *mlx5e_get_netdev(void *vpriv)
3295 {
3296         struct mlx5e_priv *priv = vpriv;
3297
3298         return priv->netdev;
3299 }
3300
3301 static struct mlx5_interface mlx5e_interface = {
3302         .add       = mlx5e_create_netdev,
3303         .remove    = mlx5e_destroy_netdev,
3304         .event     = mlx5e_async_event,
3305         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
3306         .get_dev   = mlx5e_get_netdev,
3307 };
3308
3309 void mlx5e_init(void)
3310 {
3311         mlx5_register_interface(&mlx5e_interface);
3312 }
3313
3314 void mlx5e_cleanup(void)
3315 {
3316         mlx5_unregister_interface(&mlx5e_interface);
3317 }