drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 struct mlx5e_rq_param {
  43         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  44         struct mlx5_wq_param    wq;
  45         bool                    am_enabled;
  46 };
  47
  48 struct mlx5e_sq_param {
  49         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  50         struct mlx5_wq_param       wq;
  51         u16                        max_inline;
  52         u8                         min_inline_mode;
  53         bool                       icosq;
  54 };
  55
  56 struct mlx5e_cq_param {
  57         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  58         struct mlx5_wq_param       wq;
  59         u16                        eq_ix;
  60         u8                         cq_period_mode;
  61 };
  62
  63 struct mlx5e_channel_param {
  64         struct mlx5e_rq_param      rq;
  65         struct mlx5e_sq_param      sq;
  66         struct mlx5e_sq_param      icosq;
  67         struct mlx5e_cq_param      rx_cq;
  68         struct mlx5e_cq_param      tx_cq;
  69         struct mlx5e_cq_param      icosq_cq;
  70 };
  71
  72 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  73 {
  74         struct mlx5_core_dev *mdev = priv->mdev;
  75         u8 port_state;
  76
  77         port_state = mlx5_query_vport_state(mdev,
  78                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  79
  80         if (port_state == VPORT_STATE_UP) {
  81                 netdev_info(priv->netdev, "Link up\n");
  82                 netif_carrier_on(priv->netdev);
  83         } else {
  84                 netdev_info(priv->netdev, "Link down\n");
  85                 netif_carrier_off(priv->netdev);
  86         }
  87 }
  88
  89 static void mlx5e_update_carrier_work(struct work_struct *work)
  90 {
  91         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  92                                                update_carrier_work);
  93
  94         mutex_lock(&priv->state_lock);
  95         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  96                 mlx5e_update_carrier(priv);
  97         mutex_unlock(&priv->state_lock);
  98 }
  99
 100 static void mlx5e_tx_timeout_work(struct work_struct *work)
 101 {
 102         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 103                                                tx_timeout_work);
 104         int err;
 105
 106         rtnl_lock();
 107         mutex_lock(&priv->state_lock);
 108         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 109                 goto unlock;
 110         mlx5e_close_locked(priv->netdev);
 111         err = mlx5e_open_locked(priv->netdev);
 112         if (err)
 113                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 114                            err);
 115 unlock:
 116         mutex_unlock(&priv->state_lock);
 117         rtnl_unlock();
 118 }
 119
 120 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 121 {
 122         struct mlx5e_sw_stats *s = &priv->stats.sw;
 123         struct mlx5e_rq_stats *rq_stats;
 124         struct mlx5e_sq_stats *sq_stats;
 125         u64 tx_offload_none = 0;
 126         int i, j;
 127
 128         memset(s, 0, sizeof(*s));
 129         for (i = 0; i < priv->params.num_channels; i++) {
 130                 rq_stats = &priv->channel[i]->rq.stats;
 131
 132                 s->rx_packets   += rq_stats->packets;
 133                 s->rx_bytes     += rq_stats->bytes;
 134                 s->rx_lro_packets += rq_stats->lro_packets;
 135                 s->rx_lro_bytes += rq_stats->lro_bytes;
 136                 s->rx_csum_none += rq_stats->csum_none;
 137                 s->rx_csum_complete += rq_stats->csum_complete;
 138                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 139                 s->rx_wqe_err   += rq_stats->wqe_err;
 140                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 141                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 142                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 143                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 144
 145                 for (j = 0; j < priv->params.num_tc; j++) {
 146                         sq_stats = &priv->channel[i]->sq[j].stats;
 147
 148                         s->tx_packets           += sq_stats->packets;
 149                         s->tx_bytes             += sq_stats->bytes;
 150                         s->tx_tso_packets       += sq_stats->tso_packets;
 151                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 152                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 153                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 154                         s->tx_queue_stopped     += sq_stats->stopped;
 155                         s->tx_queue_wake        += sq_stats->wake;
 156                         s->tx_queue_dropped     += sq_stats->dropped;
 157                         s->tx_xmit_more         += sq_stats->xmit_more;
 158                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 159                         tx_offload_none         += sq_stats->csum_none;
 160                 }
 161         }
 162
 163         /* Update calculated offload counters */
 164         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
 165         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 166
 167         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 168                                 priv->stats.pport.phy_counters,
 169                                 counter_set.phys_layer_cntrs.link_down_events);
 170 }
 171
 172 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 173 {
 174         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 175         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 176         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
 177         struct mlx5_core_dev *mdev = priv->mdev;
 178
 179         MLX5_SET(query_vport_counter_in, in, opcode,
 180                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 181         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 182         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 183
 184         memset(out, 0, outlen);
 185         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 186 }
 187
 188 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 189 {
 190         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 191         struct mlx5_core_dev *mdev = priv->mdev;
 192         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 193         int prio;
 194         void *out;
 195         u32 *in;
 196
 197         in = mlx5_vzalloc(sz);
 198         if (!in)
 199                 goto free_out;
 200
 201         MLX5_SET(ppcnt_reg, in, local_port, 1);
 202
 203         out = pstats->IEEE_802_3_counters;
 204         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 205         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 206
 207         out = pstats->RFC_2863_counters;
 208         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 209         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 210
 211         out = pstats->RFC_2819_counters;
 212         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 213         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 214
 215         out = pstats->phy_counters;
 216         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 217         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 218
 219         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 220         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 221                 out = pstats->per_prio_counters[prio];
 222                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 223                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 224                                      MLX5_REG_PPCNT, 0, 0);
 225         }
 226
 227 free_out:
 228         kvfree(in);
 229 }
 230
 231 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 232 {
 233         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 234
 235         if (!priv->q_counter)
 236                 return;
 237
 238         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 239                                       &qcnt->rx_out_of_buffer);
 240 }
 241
 242 void mlx5e_update_stats(struct mlx5e_priv *priv)
 243 {
 244         mlx5e_update_q_counter(priv);
 245         mlx5e_update_vport_counters(priv);
 246         mlx5e_update_pport_counters(priv);
 247         mlx5e_update_sw_counters(priv);
 248 }
 249
 250 void mlx5e_update_stats_work(struct work_struct *work)
 251 {
 252         struct delayed_work *dwork = to_delayed_work(work);
 253         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 254                                                update_stats_work);
 255         mutex_lock(&priv->state_lock);
 256         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 257                 priv->profile->update_stats(priv);
 258                 queue_delayed_work(priv->wq, dwork,
 259                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 260         }
 261         mutex_unlock(&priv->state_lock);
 262 }
 263
 264 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 265                               enum mlx5_dev_event event, unsigned long param)
 266 {
 267         struct mlx5e_priv *priv = vpriv;
 268
 269         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 270                 return;
 271
 272         switch (event) {
 273         case MLX5_DEV_EVENT_PORT_UP:
 274         case MLX5_DEV_EVENT_PORT_DOWN:
 275                 queue_work(priv->wq, &priv->update_carrier_work);
 276                 break;
 277
 278         default:
 279                 break;
 280         }
 281 }
 282
 283 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 284 {
 285         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 286 }
 287
 288 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 289 {
 290         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 291         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 292 }
 293
 294 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 295 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 296
 297 static inline int mlx5e_get_wqe_mtt_sz(void)
 298 {
 299         /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
 300          * To avoid copying garbage after the mtt array, we allocate
 301          * a little more.
 302          */
 303         return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
 304                      MLX5_UMR_MTT_ALIGNMENT);
 305 }
 306
 307 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
 308                                        struct mlx5e_umr_wqe *wqe, u16 ix)
 309 {
 310         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 311         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 312         struct mlx5_wqe_data_seg      *dseg = &wqe->data;
 313         struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
 314         u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
 315         u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
 316
 317         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 318                                       ds_cnt);
 319         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 320         cseg->imm       = rq->mkey_be;
 321
 322         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
 323         ucseg->klm_octowords =
 324                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 325         ucseg->bsf_octowords =
 326                 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
 327         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 328
 329         dseg->lkey = sq->mkey_be;
 330         dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
 331 }
 332
 333 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 334                                      struct mlx5e_channel *c)
 335 {
 336         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 337         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 338         int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
 339         int i;
 340
 341         rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
 342                                     GFP_KERNEL, cpu_to_node(c->cpu));
 343         if (!rq->wqe_info)
 344                 goto err_out;
 345
 346         /* We allocate more than mtt_sz as we will align the pointer */
 347         rq->mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
 348                                         cpu_to_node(c->cpu));
 349         if (unlikely(!rq->mtt_no_align))
 350                 goto err_free_wqe_info;
 351
 352         for (i = 0; i < wq_sz; i++) {
 353                 struct mlx5e_mpw_info *wi = &rq->wqe_info[i];
 354
 355                 wi->umr.mtt = PTR_ALIGN(rq->mtt_no_align + i * mtt_alloc,
 356                                         MLX5_UMR_ALIGN);
 357                 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
 358                                                   PCI_DMA_TODEVICE);
 359                 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
 360                         goto err_unmap_mtts;
 361
 362                 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
 363         }
 364
 365         return 0;
 366
 367 err_unmap_mtts:
 368         while (--i >= 0) {
 369                 struct mlx5e_mpw_info *wi = &rq->wqe_info[i];
 370
 371                 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
 372                                  PCI_DMA_TODEVICE);
 373         }
 374         kfree(rq->mtt_no_align);
 375 err_free_wqe_info:
 376         kfree(rq->wqe_info);
 377
 378 err_out:
 379         return -ENOMEM;
 380 }
 381
 382 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
 383 {
 384         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 385         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 386         int i;
 387
 388         for (i = 0; i < wq_sz; i++) {
 389                 struct mlx5e_mpw_info *wi = &rq->wqe_info[i];
 390
 391                 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
 392                                  PCI_DMA_TODEVICE);
 393         }
 394         kfree(rq->mtt_no_align);
 395         kfree(rq->wqe_info);
 396 }
 397
 398 static int mlx5e_create_rq(struct mlx5e_channel *c,
 399                            struct mlx5e_rq_param *param,
 400                            struct mlx5e_rq *rq)
 401 {
 402         struct mlx5e_priv *priv = c->priv;
 403         struct mlx5_core_dev *mdev = priv->mdev;
 404         void *rqc = param->rqc;
 405         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 406         u32 byte_count;
 407         int wq_sz;
 408         int err;
 409         int i;
 410
 411         param->wq.db_numa_node = cpu_to_node(c->cpu);
 412
 413         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 414                                 &rq->wq_ctrl);
 415         if (err)
 416                 return err;
 417
 418         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 419
 420         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 421
 422         rq->wq_type = priv->params.rq_wq_type;
 423         rq->pdev    = c->pdev;
 424         rq->netdev  = c->netdev;
 425         rq->tstamp  = &priv->tstamp;
 426         rq->channel = c;
 427         rq->ix      = c->ix;
 428         rq->priv    = c->priv;
 429
 430         switch (priv->params.rq_wq_type) {
 431         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 432                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 433                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 434                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 435
 436                 rq->mpwqe_mtt_offset = c->ix *
 437                         MLX5E_REQUIRED_MTTS(1, BIT(priv->params.log_rq_size));
 438
 439                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 440                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 441                 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 442                 byte_count = rq->wqe_sz;
 443                 rq->mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 444                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 445                 if (err)
 446                         goto err_rq_wq_destroy;
 447                 break;
 448         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 449                 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 450                                        cpu_to_node(c->cpu));
 451                 if (!rq->skb) {
 452                         err = -ENOMEM;
 453                         goto err_rq_wq_destroy;
 454                 }
 455                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 456                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 457                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 458
 459                 rq->wqe_sz = (priv->params.lro_en) ?
 460                                 priv->params.lro_wqe_sz :
 461                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 462                 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
 463                 byte_count = rq->wqe_sz;
 464                 byte_count |= MLX5_HW_START_PADDING;
 465                 rq->mkey_be = c->mkey_be;
 466         }
 467
 468         for (i = 0; i < wq_sz; i++) {
 469                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 470
 471                 wqe->data.byte_count = cpu_to_be32(byte_count);
 472                 wqe->data.lkey = rq->mkey_be;
 473         }
 474
 475         INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
 476         rq->am.mode = priv->params.rx_cq_period_mode;
 477
 478         return 0;
 479
 480 err_rq_wq_destroy:
 481         mlx5_wq_destroy(&rq->wq_ctrl);
 482
 483         return err;
 484 }
 485
 486 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 487 {
 488         switch (rq->wq_type) {
 489         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 490                 mlx5e_rq_free_mpwqe_info(rq);
 491                 break;
 492         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 493                 kfree(rq->skb);
 494         }
 495
 496         mlx5_wq_destroy(&rq->wq_ctrl);
 497 }
 498
 499 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 500 {
 501         struct mlx5e_priv *priv = rq->priv;
 502         struct mlx5_core_dev *mdev = priv->mdev;
 503
 504         void *in;
 505         void *rqc;
 506         void *wq;
 507         int inlen;
 508         int err;
 509
 510         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 511                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 512         in = mlx5_vzalloc(inlen);
 513         if (!in)
 514                 return -ENOMEM;
 515
 516         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 517         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 518
 519         memcpy(rqc, param->rqc, sizeof(param->rqc));
 520
 521         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 522         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 523         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 524         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 525                                                 MLX5_ADAPTER_PAGE_SHIFT);
 526         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 527
 528         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 529                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 530
 531         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 532
 533         kvfree(in);
 534
 535         return err;
 536 }
 537
 538 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 539                                  int next_state)
 540 {
 541         struct mlx5e_channel *c = rq->channel;
 542         struct mlx5e_priv *priv = c->priv;
 543         struct mlx5_core_dev *mdev = priv->mdev;
 544
 545         void *in;
 546         void *rqc;
 547         int inlen;
 548         int err;
 549
 550         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 551         in = mlx5_vzalloc(inlen);
 552         if (!in)
 553                 return -ENOMEM;
 554
 555         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 556
 557         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 558         MLX5_SET(rqc, rqc, state, next_state);
 559
 560         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 561
 562         kvfree(in);
 563
 564         return err;
 565 }
 566
 567 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 568 {
 569         struct mlx5e_channel *c = rq->channel;
 570         struct mlx5e_priv *priv = c->priv;
 571         struct mlx5_core_dev *mdev = priv->mdev;
 572
 573         void *in;
 574         void *rqc;
 575         int inlen;
 576         int err;
 577
 578         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 579         in = mlx5_vzalloc(inlen);
 580         if (!in)
 581                 return -ENOMEM;
 582
 583         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 584
 585         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 586         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 587                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 588         MLX5_SET(rqc, rqc, vsd, vsd);
 589         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 590
 591         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 592
 593         kvfree(in);
 594
 595         return err;
 596 }
 597
 598 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 599 {
 600         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 601 }
 602
 603 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 604 {
 605         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 606         struct mlx5e_channel *c = rq->channel;
 607         struct mlx5e_priv *priv = c->priv;
 608         struct mlx5_wq_ll *wq = &rq->wq;
 609
 610         while (time_before(jiffies, exp_time)) {
 611                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 612                         return 0;
 613
 614                 msleep(20);
 615         }
 616
 617         return -ETIMEDOUT;
 618 }
 619
 620 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 621 {
 622         struct mlx5_wq_ll *wq = &rq->wq;
 623         struct mlx5e_rx_wqe *wqe;
 624         __be16 wqe_ix_be;
 625         u16 wqe_ix;
 626
 627         /* UMR WQE (if in progress) is always at wq->head */
 628         if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
 629                 mlx5e_free_rx_mpwqe(rq, &rq->wqe_info[wq->head]);
 630
 631         while (!mlx5_wq_ll_is_empty(wq)) {
 632                 wqe_ix_be = *wq->tail_next;
 633                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 634                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 635                 rq->dealloc_wqe(rq, wqe_ix);
 636                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 637                                &wqe->next.next_wqe_index);
 638         }
 639 }
 640
 641 static int mlx5e_open_rq(struct mlx5e_channel *c,
 642                          struct mlx5e_rq_param *param,
 643                          struct mlx5e_rq *rq)
 644 {
 645         struct mlx5e_sq *sq = &c->icosq;
 646         u16 pi = sq->pc & sq->wq.sz_m1;
 647         int err;
 648
 649         err = mlx5e_create_rq(c, param, rq);
 650         if (err)
 651                 return err;
 652
 653         err = mlx5e_enable_rq(rq, param);
 654         if (err)
 655                 goto err_destroy_rq;
 656
 657         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 658         if (err)
 659                 goto err_disable_rq;
 660
 661         if (param->am_enabled)
 662                 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 663
 664         sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
 665         sq->ico_wqe_info[pi].num_wqebbs = 1;
 666         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 667
 668         return 0;
 669
 670 err_disable_rq:
 671         mlx5e_disable_rq(rq);
 672 err_destroy_rq:
 673         mlx5e_destroy_rq(rq);
 674
 675         return err;
 676 }
 677
 678 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 679 {
 680         set_bit(MLX5E_RQ_STATE_FLUSH, &rq->state);
 681         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 682         cancel_work_sync(&rq->am.work);
 683
 684         mlx5e_disable_rq(rq);
 685         mlx5e_free_rx_descs(rq);
 686         mlx5e_destroy_rq(rq);
 687 }
 688
 689 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 690 {
 691         kfree(sq->wqe_info);
 692         kfree(sq->dma_fifo);
 693         kfree(sq->skb);
 694 }
 695
 696 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 697 {
 698         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 699         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 700
 701         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 702         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 703                                     numa);
 704         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 705                                     numa);
 706
 707         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 708                 mlx5e_free_sq_db(sq);
 709                 return -ENOMEM;
 710         }
 711
 712         sq->dma_fifo_mask = df_sz - 1;
 713
 714         return 0;
 715 }
 716
 717 static int mlx5e_create_sq(struct mlx5e_channel *c,
 718                            int tc,
 719                            struct mlx5e_sq_param *param,
 720                            struct mlx5e_sq *sq)
 721 {
 722         struct mlx5e_priv *priv = c->priv;
 723         struct mlx5_core_dev *mdev = priv->mdev;
 724
 725         void *sqc = param->sqc;
 726         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 727         int err;
 728
 729         err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
 730         if (err)
 731                 return err;
 732
 733         param->wq.db_numa_node = cpu_to_node(c->cpu);
 734
 735         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 736                                  &sq->wq_ctrl);
 737         if (err)
 738                 goto err_unmap_free_uar;
 739
 740         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 741         if (sq->uar.bf_map) {
 742                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 743                 sq->uar_map = sq->uar.bf_map;
 744         } else {
 745                 sq->uar_map = sq->uar.map;
 746         }
 747         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 748         sq->max_inline  = param->max_inline;
 749         sq->min_inline_mode =
 750                 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
 751                 param->min_inline_mode : 0;
 752
 753         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 754         if (err)
 755                 goto err_sq_wq_destroy;
 756
 757         if (param->icosq) {
 758                 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 759
 760                 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
 761                                                 wq_sz,
 762                                                 GFP_KERNEL,
 763                                                 cpu_to_node(c->cpu));
 764                 if (!sq->ico_wqe_info) {
 765                         err = -ENOMEM;
 766                         goto err_free_sq_db;
 767                 }
 768         } else {
 769                 int txq_ix;
 770
 771                 txq_ix = c->ix + tc * priv->params.num_channels;
 772                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 773                 priv->txq_to_sq_map[txq_ix] = sq;
 774         }
 775
 776         sq->pdev      = c->pdev;
 777         sq->tstamp    = &priv->tstamp;
 778         sq->mkey_be   = c->mkey_be;
 779         sq->channel   = c;
 780         sq->tc        = tc;
 781         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 782         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 783
 784         return 0;
 785
 786 err_free_sq_db:
 787         mlx5e_free_sq_db(sq);
 788
 789 err_sq_wq_destroy:
 790         mlx5_wq_destroy(&sq->wq_ctrl);
 791
 792 err_unmap_free_uar:
 793         mlx5_unmap_free_uar(mdev, &sq->uar);
 794
 795         return err;
 796 }
 797
 798 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 799 {
 800         struct mlx5e_channel *c = sq->channel;
 801         struct mlx5e_priv *priv = c->priv;
 802
 803         kfree(sq->ico_wqe_info);
 804         mlx5e_free_sq_db(sq);
 805         mlx5_wq_destroy(&sq->wq_ctrl);
 806         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 807 }
 808
 809 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 810 {
 811         struct mlx5e_channel *c = sq->channel;
 812         struct mlx5e_priv *priv = c->priv;
 813         struct mlx5_core_dev *mdev = priv->mdev;
 814
 815         void *in;
 816         void *sqc;
 817         void *wq;
 818         int inlen;
 819         int err;
 820
 821         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 822                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 823         in = mlx5_vzalloc(inlen);
 824         if (!in)
 825                 return -ENOMEM;
 826
 827         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 828         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 829
 830         memcpy(sqc, param->sqc, sizeof(param->sqc));
 831
 832         MLX5_SET(sqc,  sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
 833         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
 834         MLX5_SET(sqc,  sqc, min_wqe_inline_mode, sq->min_inline_mode);
 835         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 836         MLX5_SET(sqc,  sqc, tis_lst_sz,         param->icosq ? 0 : 1);
 837         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 838
 839         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 840         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 841         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 842                                           MLX5_ADAPTER_PAGE_SHIFT);
 843         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 844
 845         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 846                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 847
 848         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 849
 850         kvfree(in);
 851
 852         return err;
 853 }
 854
 855 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
 856                            int next_state, bool update_rl, int rl_index)
 857 {
 858         struct mlx5e_channel *c = sq->channel;
 859         struct mlx5e_priv *priv = c->priv;
 860         struct mlx5_core_dev *mdev = priv->mdev;
 861
 862         void *in;
 863         void *sqc;
 864         int inlen;
 865         int err;
 866
 867         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 868         in = mlx5_vzalloc(inlen);
 869         if (!in)
 870                 return -ENOMEM;
 871
 872         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 873
 874         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 875         MLX5_SET(sqc, sqc, state, next_state);
 876         if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
 877                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
 878                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, rl_index);
 879         }
 880
 881         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 882
 883         kvfree(in);
 884
 885         return err;
 886 }
 887
 888 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 889 {
 890         struct mlx5e_channel *c = sq->channel;
 891         struct mlx5e_priv *priv = c->priv;
 892         struct mlx5_core_dev *mdev = priv->mdev;
 893
 894         mlx5_core_destroy_sq(mdev, sq->sqn);
 895         if (sq->rate_limit)
 896                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
 897 }
 898
 899 static int mlx5e_open_sq(struct mlx5e_channel *c,
 900                          int tc,
 901                          struct mlx5e_sq_param *param,
 902                          struct mlx5e_sq *sq)
 903 {
 904         int err;
 905
 906         err = mlx5e_create_sq(c, tc, param, sq);
 907         if (err)
 908                 return err;
 909
 910         err = mlx5e_enable_sq(sq, param);
 911         if (err)
 912                 goto err_destroy_sq;
 913
 914         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
 915                               false, 0);
 916         if (err)
 917                 goto err_disable_sq;
 918
 919         if (sq->txq) {
 920                 netdev_tx_reset_queue(sq->txq);
 921                 netif_tx_start_queue(sq->txq);
 922         }
 923
 924         return 0;
 925
 926 err_disable_sq:
 927         mlx5e_disable_sq(sq);
 928 err_destroy_sq:
 929         mlx5e_destroy_sq(sq);
 930
 931         return err;
 932 }
 933
 934 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 935 {
 936         __netif_tx_lock_bh(txq);
 937         netif_tx_stop_queue(txq);
 938         __netif_tx_unlock_bh(txq);
 939 }
 940
 941 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 942 {
 943         set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
 944         /* prevent netif_tx_wake_queue */
 945         napi_synchronize(&sq->channel->napi);
 946
 947         if (sq->txq) {
 948                 netif_tx_disable_queue(sq->txq);
 949
 950                 /* last doorbell out, godspeed .. */
 951                 if (mlx5e_sq_has_room_for(sq, 1))
 952                         mlx5e_send_nop(sq, true);
 953         }
 954
 955         mlx5e_disable_sq(sq);
 956         mlx5e_free_tx_descs(sq);
 957         mlx5e_destroy_sq(sq);
 958 }
 959
 960 static int mlx5e_create_cq(struct mlx5e_channel *c,
 961                            struct mlx5e_cq_param *param,
 962                            struct mlx5e_cq *cq)
 963 {
 964         struct mlx5e_priv *priv = c->priv;
 965         struct mlx5_core_dev *mdev = priv->mdev;
 966         struct mlx5_core_cq *mcq = &cq->mcq;
 967         int eqn_not_used;
 968         unsigned int irqn;
 969         int err;
 970         u32 i;
 971
 972         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 973         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 974         param->eq_ix   = c->ix;
 975
 976         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 977                                &cq->wq_ctrl);
 978         if (err)
 979                 return err;
 980
 981         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 982
 983         cq->napi        = &c->napi;
 984
 985         mcq->cqe_sz     = 64;
 986         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 987         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 988         *mcq->set_ci_db = 0;
 989         *mcq->arm_db    = 0;
 990         mcq->vector     = param->eq_ix;
 991         mcq->comp       = mlx5e_completion_event;
 992         mcq->event      = mlx5e_cq_error_event;
 993         mcq->irqn       = irqn;
 994         mcq->uar        = &mdev->mlx5e_res.cq_uar;
 995
 996         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 997                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 998
 999                 cqe->op_own = 0xf1;
1000         }
1001
1002         cq->channel = c;
1003         cq->priv = priv;
1004
1005         return 0;
1006 }
1007
1008 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1009 {
1010         mlx5_wq_destroy(&cq->wq_ctrl);
1011 }
1012
1013 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1014 {
1015         struct mlx5e_priv *priv = cq->priv;
1016         struct mlx5_core_dev *mdev = priv->mdev;
1017         struct mlx5_core_cq *mcq = &cq->mcq;
1018
1019         void *in;
1020         void *cqc;
1021         int inlen;
1022         unsigned int irqn_not_used;
1023         int eqn;
1024         int err;
1025
1026         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1027                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1028         in = mlx5_vzalloc(inlen);
1029         if (!in)
1030                 return -ENOMEM;
1031
1032         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1033
1034         memcpy(cqc, param->cqc, sizeof(param->cqc));
1035
1036         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1037                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1038
1039         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1040
1041         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1042         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1043         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
1044         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1045                                             MLX5_ADAPTER_PAGE_SHIFT);
1046         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1047
1048         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1049
1050         kvfree(in);
1051
1052         if (err)
1053                 return err;
1054
1055         mlx5e_cq_arm(cq);
1056
1057         return 0;
1058 }
1059
1060 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1061 {
1062         struct mlx5e_priv *priv = cq->priv;
1063         struct mlx5_core_dev *mdev = priv->mdev;
1064
1065         mlx5_core_destroy_cq(mdev, &cq->mcq);
1066 }
1067
1068 static int mlx5e_open_cq(struct mlx5e_channel *c,
1069                          struct mlx5e_cq_param *param,
1070                          struct mlx5e_cq *cq,
1071                          struct mlx5e_cq_moder moderation)
1072 {
1073         int err;
1074         struct mlx5e_priv *priv = c->priv;
1075         struct mlx5_core_dev *mdev = priv->mdev;
1076
1077         err = mlx5e_create_cq(c, param, cq);
1078         if (err)
1079                 return err;
1080
1081         err = mlx5e_enable_cq(cq, param);
1082         if (err)
1083                 goto err_destroy_cq;
1084
1085         if (MLX5_CAP_GEN(mdev, cq_moderation))
1086                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1087                                                moderation.usec,
1088                                                moderation.pkts);
1089         return 0;
1090
1091 err_destroy_cq:
1092         mlx5e_destroy_cq(cq);
1093
1094         return err;
1095 }
1096
1097 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1098 {
1099         mlx5e_disable_cq(cq);
1100         mlx5e_destroy_cq(cq);
1101 }
1102
1103 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1104 {
1105         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1106 }
1107
1108 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1109                              struct mlx5e_channel_param *cparam)
1110 {
1111         struct mlx5e_priv *priv = c->priv;
1112         int err;
1113         int tc;
1114
1115         for (tc = 0; tc < c->num_tc; tc++) {
1116                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1117                                     priv->params.tx_cq_moderation);
1118                 if (err)
1119                         goto err_close_tx_cqs;
1120         }
1121
1122         return 0;
1123
1124 err_close_tx_cqs:
1125         for (tc--; tc >= 0; tc--)
1126                 mlx5e_close_cq(&c->sq[tc].cq);
1127
1128         return err;
1129 }
1130
1131 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1132 {
1133         int tc;
1134
1135         for (tc = 0; tc < c->num_tc; tc++)
1136                 mlx5e_close_cq(&c->sq[tc].cq);
1137 }
1138
1139 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1140                           struct mlx5e_channel_param *cparam)
1141 {
1142         int err;
1143         int tc;
1144
1145         for (tc = 0; tc < c->num_tc; tc++) {
1146                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1147                 if (err)
1148                         goto err_close_sqs;
1149         }
1150
1151         return 0;
1152
1153 err_close_sqs:
1154         for (tc--; tc >= 0; tc--)
1155                 mlx5e_close_sq(&c->sq[tc]);
1156
1157         return err;
1158 }
1159
1160 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1161 {
1162         int tc;
1163
1164         for (tc = 0; tc < c->num_tc; tc++)
1165                 mlx5e_close_sq(&c->sq[tc]);
1166 }
1167
1168 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1169 {
1170         int i;
1171
1172         for (i = 0; i < priv->profile->max_tc; i++)
1173                 priv->channeltc_to_txq_map[ix][i] =
1174                         ix + i * priv->params.num_channels;
1175 }
1176
1177 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1178                                 struct mlx5e_sq *sq, u32 rate)
1179 {
1180         struct mlx5e_priv *priv = netdev_priv(dev);
1181         struct mlx5_core_dev *mdev = priv->mdev;
1182         u16 rl_index = 0;
1183         int err;
1184
1185         if (rate == sq->rate_limit)
1186                 /* nothing to do */
1187                 return 0;
1188
1189         if (sq->rate_limit)
1190                 /* remove current rl index to free space to next ones */
1191                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1192
1193         sq->rate_limit = 0;
1194
1195         if (rate) {
1196                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1197                 if (err) {
1198                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1199                                    rate, err);
1200                         return err;
1201                 }
1202         }
1203
1204         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1205                               MLX5_SQC_STATE_RDY, true, rl_index);
1206         if (err) {
1207                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1208                            rate, err);
1209                 /* remove the rate from the table */
1210                 if (rate)
1211                         mlx5_rl_remove_rate(mdev, rate);
1212                 return err;
1213         }
1214
1215         sq->rate_limit = rate;
1216         return 0;
1217 }
1218
1219 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1220 {
1221         struct mlx5e_priv *priv = netdev_priv(dev);
1222         struct mlx5_core_dev *mdev = priv->mdev;
1223         struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1224         int err = 0;
1225
1226         if (!mlx5_rl_is_supported(mdev)) {
1227                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1228                 return -EINVAL;
1229         }
1230
1231         /* rate is given in Mb/sec, HW config is in Kb/sec */
1232         rate = rate << 10;
1233
1234         /* Check whether rate in valid range, 0 is always valid */
1235         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1236                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1237                 return -ERANGE;
1238         }
1239
1240         mutex_lock(&priv->state_lock);
1241         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1242                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1243         if (!err)
1244                 priv->tx_rates[index] = rate;
1245         mutex_unlock(&priv->state_lock);
1246
1247         return err;
1248 }
1249
1250 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1251                               struct mlx5e_channel_param *cparam,
1252                               struct mlx5e_channel **cp)
1253 {
1254         struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1255         struct net_device *netdev = priv->netdev;
1256         struct mlx5e_cq_moder rx_cq_profile;
1257         int cpu = mlx5e_get_cpu(priv, ix);
1258         struct mlx5e_channel *c;
1259         struct mlx5e_sq *sq;
1260         int err;
1261         int i;
1262
1263         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1264         if (!c)
1265                 return -ENOMEM;
1266
1267         c->priv     = priv;
1268         c->ix       = ix;
1269         c->cpu      = cpu;
1270         c->pdev     = &priv->mdev->pdev->dev;
1271         c->netdev   = priv->netdev;
1272         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1273         c->num_tc   = priv->params.num_tc;
1274
1275         if (priv->params.rx_am_enabled)
1276                 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1277         else
1278                 rx_cq_profile = priv->params.rx_cq_moderation;
1279
1280         mlx5e_build_channeltc_to_txq_map(priv, ix);
1281
1282         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1283
1284         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1285         if (err)
1286                 goto err_napi_del;
1287
1288         err = mlx5e_open_tx_cqs(c, cparam);
1289         if (err)
1290                 goto err_close_icosq_cq;
1291
1292         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1293                             rx_cq_profile);
1294         if (err)
1295                 goto err_close_tx_cqs;
1296
1297         napi_enable(&c->napi);
1298
1299         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1300         if (err)
1301                 goto err_disable_napi;
1302
1303         err = mlx5e_open_sqs(c, cparam);
1304         if (err)
1305                 goto err_close_icosq;
1306
1307         for (i = 0; i < priv->params.num_tc; i++) {
1308                 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1309
1310                 if (priv->tx_rates[txq_ix]) {
1311                         sq = priv->txq_to_sq_map[txq_ix];
1312                         mlx5e_set_sq_maxrate(priv->netdev, sq,
1313                                              priv->tx_rates[txq_ix]);
1314                 }
1315         }
1316
1317         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1318         if (err)
1319                 goto err_close_sqs;
1320
1321         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1322         *cp = c;
1323
1324         return 0;
1325
1326 err_close_sqs:
1327         mlx5e_close_sqs(c);
1328
1329 err_close_icosq:
1330         mlx5e_close_sq(&c->icosq);
1331
1332 err_disable_napi:
1333         napi_disable(&c->napi);
1334         mlx5e_close_cq(&c->rq.cq);
1335
1336 err_close_tx_cqs:
1337         mlx5e_close_tx_cqs(c);
1338
1339 err_close_icosq_cq:
1340         mlx5e_close_cq(&c->icosq.cq);
1341
1342 err_napi_del:
1343         netif_napi_del(&c->napi);
1344         napi_hash_del(&c->napi);
1345         kfree(c);
1346
1347         return err;
1348 }
1349
1350 static void mlx5e_close_channel(struct mlx5e_channel *c)
1351 {
1352         mlx5e_close_rq(&c->rq);
1353         mlx5e_close_sqs(c);
1354         mlx5e_close_sq(&c->icosq);
1355         napi_disable(&c->napi);
1356         mlx5e_close_cq(&c->rq.cq);
1357         mlx5e_close_tx_cqs(c);
1358         mlx5e_close_cq(&c->icosq.cq);
1359         netif_napi_del(&c->napi);
1360
1361         napi_hash_del(&c->napi);
1362         synchronize_rcu();
1363
1364         kfree(c);
1365 }
1366
1367 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1368                                  struct mlx5e_rq_param *param)
1369 {
1370         void *rqc = param->rqc;
1371         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1372
1373         switch (priv->params.rq_wq_type) {
1374         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1375                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1376                          priv->params.mpwqe_log_num_strides - 9);
1377                 MLX5_SET(wq, wq, log_wqe_stride_size,
1378                          priv->params.mpwqe_log_stride_sz - 6);
1379                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1380                 break;
1381         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1382                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1383         }
1384
1385         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1386         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1387         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1388         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1389         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1390
1391         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1392         param->wq.linear = 1;
1393
1394         param->am_enabled = priv->params.rx_am_enabled;
1395 }
1396
1397 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1398 {
1399         void *rqc = param->rqc;
1400         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1401
1402         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1403         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1404 }
1405
1406 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1407                                         struct mlx5e_sq_param *param)
1408 {
1409         void *sqc = param->sqc;
1410         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1411
1412         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1413         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1414
1415         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1416 }
1417
1418 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1419                                  struct mlx5e_sq_param *param)
1420 {
1421         void *sqc = param->sqc;
1422         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1423
1424         mlx5e_build_sq_param_common(priv, param);
1425         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1426
1427         param->max_inline = priv->params.tx_max_inline;
1428         param->min_inline_mode = priv->params.tx_min_inline_mode;
1429 }
1430
1431 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1432                                         struct mlx5e_cq_param *param)
1433 {
1434         void *cqc = param->cqc;
1435
1436         MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
1437 }
1438
1439 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1440                                     struct mlx5e_cq_param *param)
1441 {
1442         void *cqc = param->cqc;
1443         u8 log_cq_size;
1444
1445         switch (priv->params.rq_wq_type) {
1446         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1447                 log_cq_size = priv->params.log_rq_size +
1448                         priv->params.mpwqe_log_num_strides;
1449                 break;
1450         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1451                 log_cq_size = priv->params.log_rq_size;
1452         }
1453
1454         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1455         if (priv->params.rx_cqe_compress) {
1456                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1457                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1458         }
1459
1460         mlx5e_build_common_cq_param(priv, param);
1461
1462         param->cq_period_mode = priv->params.rx_cq_period_mode;
1463 }
1464
1465 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1466                                     struct mlx5e_cq_param *param)
1467 {
1468         void *cqc = param->cqc;
1469
1470         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1471
1472         mlx5e_build_common_cq_param(priv, param);
1473
1474         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1475 }
1476
1477 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1478                                      struct mlx5e_cq_param *param,
1479                                      u8 log_wq_size)
1480 {
1481         void *cqc = param->cqc;
1482
1483         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1484
1485         mlx5e_build_common_cq_param(priv, param);
1486
1487         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1488 }
1489
1490 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1491                                     struct mlx5e_sq_param *param,
1492                                     u8 log_wq_size)
1493 {
1494         void *sqc = param->sqc;
1495         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1496
1497         mlx5e_build_sq_param_common(priv, param);
1498
1499         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1500         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1501
1502         param->icosq = true;
1503 }
1504
1505 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1506 {
1507         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1508
1509         mlx5e_build_rq_param(priv, &cparam->rq);
1510         mlx5e_build_sq_param(priv, &cparam->sq);
1511         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1512         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1513         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1514         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1515 }
1516
1517 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1518 {
1519         struct mlx5e_channel_param *cparam;
1520         int nch = priv->params.num_channels;
1521         int err = -ENOMEM;
1522         int i;
1523         int j;
1524
1525         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1526                                 GFP_KERNEL);
1527
1528         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1529                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1530
1531         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1532
1533         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1534                 goto err_free_txq_to_sq_map;
1535
1536         mlx5e_build_channel_param(priv, cparam);
1537
1538         for (i = 0; i < nch; i++) {
1539                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1540                 if (err)
1541                         goto err_close_channels;
1542         }
1543
1544         for (j = 0; j < nch; j++) {
1545                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1546                 if (err)
1547                         goto err_close_channels;
1548         }
1549
1550         /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1551          * polling for inactive tx queues.
1552          */
1553         netif_tx_start_all_queues(priv->netdev);
1554
1555         kfree(cparam);
1556         return 0;
1557
1558 err_close_channels:
1559         for (i--; i >= 0; i--)
1560                 mlx5e_close_channel(priv->channel[i]);
1561
1562 err_free_txq_to_sq_map:
1563         kfree(priv->txq_to_sq_map);
1564         kfree(priv->channel);
1565         kfree(cparam);
1566
1567         return err;
1568 }
1569
1570 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1571 {
1572         int i;
1573
1574         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1575          * polling for inactive tx queues.
1576          */
1577         netif_tx_stop_all_queues(priv->netdev);
1578         netif_tx_disable(priv->netdev);
1579
1580         for (i = 0; i < priv->params.num_channels; i++)
1581                 mlx5e_close_channel(priv->channel[i]);
1582
1583         kfree(priv->txq_to_sq_map);
1584         kfree(priv->channel);
1585 }
1586
1587 static int mlx5e_rx_hash_fn(int hfunc)
1588 {
1589         return (hfunc == ETH_RSS_HASH_TOP) ?
1590                MLX5_RX_HASH_FN_TOEPLITZ :
1591                MLX5_RX_HASH_FN_INVERTED_XOR8;
1592 }
1593
1594 static int mlx5e_bits_invert(unsigned long a, int size)
1595 {
1596         int inv = 0;
1597         int i;
1598
1599         for (i = 0; i < size; i++)
1600                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1601
1602         return inv;
1603 }
1604
1605 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1606 {
1607         int i;
1608
1609         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1610                 int ix = i;
1611                 u32 rqn;
1612
1613                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1614                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1615
1616                 ix = priv->params.indirection_rqt[ix];
1617                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1618                                 priv->channel[ix]->rq.rqn :
1619                                 priv->drop_rq.rqn;
1620                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1621         }
1622 }
1623
1624 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1625                                       int ix)
1626 {
1627         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1628                         priv->channel[ix]->rq.rqn :
1629                         priv->drop_rq.rqn;
1630
1631         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1632 }
1633
1634 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1635                             int ix, struct mlx5e_rqt *rqt)
1636 {
1637         struct mlx5_core_dev *mdev = priv->mdev;
1638         void *rqtc;
1639         int inlen;
1640         int err;
1641         u32 *in;
1642
1643         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1644         in = mlx5_vzalloc(inlen);
1645         if (!in)
1646                 return -ENOMEM;
1647
1648         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1649
1650         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1651         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1652
1653         if (sz > 1) /* RSS */
1654                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1655         else
1656                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1657
1658         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1659         if (!err)
1660                 rqt->enabled = true;
1661
1662         kvfree(in);
1663         return err;
1664 }
1665
1666 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1667 {
1668         rqt->enabled = false;
1669         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1670 }
1671
1672 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1673 {
1674         struct mlx5e_rqt *rqt = &priv->indir_rqt;
1675
1676         return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1677 }
1678
1679 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1680 {
1681         struct mlx5e_rqt *rqt;
1682         int err;
1683         int ix;
1684
1685         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1686                 rqt = &priv->direct_tir[ix].rqt;
1687                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1688                 if (err)
1689                         goto err_destroy_rqts;
1690         }
1691
1692         return 0;
1693
1694 err_destroy_rqts:
1695         for (ix--; ix >= 0; ix--)
1696                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1697
1698         return err;
1699 }
1700
1701 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1702 {
1703         struct mlx5_core_dev *mdev = priv->mdev;
1704         void *rqtc;
1705         int inlen;
1706         u32 *in;
1707         int err;
1708
1709         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1710         in = mlx5_vzalloc(inlen);
1711         if (!in)
1712                 return -ENOMEM;
1713
1714         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1715
1716         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1717         if (sz > 1) /* RSS */
1718                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1719         else
1720                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1721
1722         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1723
1724         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1725
1726         kvfree(in);
1727
1728         return err;
1729 }
1730
1731 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1732 {
1733         u32 rqtn;
1734         int ix;
1735
1736         if (priv->indir_rqt.enabled) {
1737                 rqtn = priv->indir_rqt.rqtn;
1738                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1739         }
1740
1741         for (ix = 0; ix < priv->params.num_channels; ix++) {
1742                 if (!priv->direct_tir[ix].rqt.enabled)
1743                         continue;
1744                 rqtn = priv->direct_tir[ix].rqt.rqtn;
1745                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1746         }
1747 }
1748
1749 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1750 {
1751         if (!priv->params.lro_en)
1752                 return;
1753
1754 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1755
1756         MLX5_SET(tirc, tirc, lro_enable_mask,
1757                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1758                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1759         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1760                  (priv->params.lro_wqe_sz -
1761                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1762         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1763                  MLX5_CAP_ETH(priv->mdev,
1764                               lro_timer_supported_periods[2]));
1765 }
1766
1767 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1768 {
1769         MLX5_SET(tirc, tirc, rx_hash_fn,
1770                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1771         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1772                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1773                                              rx_hash_toeplitz_key);
1774                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1775                                                rx_hash_toeplitz_key);
1776
1777                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1778                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1779         }
1780 }
1781
1782 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1783 {
1784         struct mlx5_core_dev *mdev = priv->mdev;
1785
1786         void *in;
1787         void *tirc;
1788         int inlen;
1789         int err;
1790         int tt;
1791         int ix;
1792
1793         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1794         in = mlx5_vzalloc(inlen);
1795         if (!in)
1796                 return -ENOMEM;
1797
1798         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1799         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1800
1801         mlx5e_build_tir_ctx_lro(tirc, priv);
1802
1803         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1804                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1805                                            inlen);
1806                 if (err)
1807                         goto free_in;
1808         }
1809
1810         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1811                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1812                                            in, inlen);
1813                 if (err)
1814                         goto free_in;
1815         }
1816
1817 free_in:
1818         kvfree(in);
1819
1820         return err;
1821 }
1822
1823 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1824 {
1825         struct mlx5_core_dev *mdev = priv->mdev;
1826         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1827         int err;
1828
1829         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1830         if (err)
1831                 return err;
1832
1833         /* Update vport context MTU */
1834         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1835         return 0;
1836 }
1837
1838 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1839 {
1840         struct mlx5_core_dev *mdev = priv->mdev;
1841         u16 hw_mtu = 0;
1842         int err;
1843
1844         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1845         if (err || !hw_mtu) /* fallback to port oper mtu */
1846                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1847
1848         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1849 }
1850
1851 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1852 {
1853         struct mlx5e_priv *priv = netdev_priv(netdev);
1854         u16 mtu;
1855         int err;
1856
1857         err = mlx5e_set_mtu(priv, netdev->mtu);
1858         if (err)
1859                 return err;
1860
1861         mlx5e_query_mtu(priv, &mtu);
1862         if (mtu != netdev->mtu)
1863                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1864                             __func__, mtu, netdev->mtu);
1865
1866         netdev->mtu = mtu;
1867         return 0;
1868 }
1869
1870 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1871 {
1872         struct mlx5e_priv *priv = netdev_priv(netdev);
1873         int nch = priv->params.num_channels;
1874         int ntc = priv->params.num_tc;
1875         int tc;
1876
1877         netdev_reset_tc(netdev);
1878
1879         if (ntc == 1)
1880                 return;
1881
1882         netdev_set_num_tc(netdev, ntc);
1883
1884         /* Map netdev TCs to offset 0
1885          * We have our own UP to TXQ mapping for QoS
1886          */
1887         for (tc = 0; tc < ntc; tc++)
1888                 netdev_set_tc_queue(netdev, tc, nch, 0);
1889 }
1890
1891 int mlx5e_open_locked(struct net_device *netdev)
1892 {
1893         struct mlx5e_priv *priv = netdev_priv(netdev);
1894         struct mlx5_core_dev *mdev = priv->mdev;
1895         int num_txqs;
1896         int err;
1897
1898         set_bit(MLX5E_STATE_OPENED, &priv->state);
1899
1900         mlx5e_netdev_set_tcs(netdev);
1901
1902         num_txqs = priv->params.num_channels * priv->params.num_tc;
1903         netif_set_real_num_tx_queues(netdev, num_txqs);
1904         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1905
1906         err = mlx5e_open_channels(priv);
1907         if (err) {
1908                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1909                            __func__, err);
1910                 goto err_clear_state_opened_flag;
1911         }
1912
1913         err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
1914         if (err) {
1915                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1916                            __func__, err);
1917                 goto err_close_channels;
1918         }
1919
1920         mlx5e_redirect_rqts(priv);
1921         mlx5e_update_carrier(priv);
1922         mlx5e_timestamp_init(priv);
1923 #ifdef CONFIG_RFS_ACCEL
1924         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1925 #endif
1926         if (priv->profile->update_stats)
1927                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1928
1929         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
1930                 err = mlx5e_add_sqs_fwd_rules(priv);
1931                 if (err)
1932                         goto err_close_channels;
1933         }
1934         return 0;
1935
1936 err_close_channels:
1937         mlx5e_close_channels(priv);
1938 err_clear_state_opened_flag:
1939         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1940         return err;
1941 }
1942
1943 int mlx5e_open(struct net_device *netdev)
1944 {
1945         struct mlx5e_priv *priv = netdev_priv(netdev);
1946         int err;
1947
1948         mutex_lock(&priv->state_lock);
1949         err = mlx5e_open_locked(netdev);
1950         mutex_unlock(&priv->state_lock);
1951
1952         return err;
1953 }
1954
1955 int mlx5e_close_locked(struct net_device *netdev)
1956 {
1957         struct mlx5e_priv *priv = netdev_priv(netdev);
1958         struct mlx5_core_dev *mdev = priv->mdev;
1959
1960         /* May already be CLOSED in case a previous configuration operation
1961          * (e.g RX/TX queue size change) that involves close&open failed.
1962          */
1963         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1964                 return 0;
1965
1966         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1967
1968         if (MLX5_CAP_GEN(mdev, vport_group_manager))
1969                 mlx5e_remove_sqs_fwd_rules(priv);
1970
1971         mlx5e_timestamp_cleanup(priv);
1972         netif_carrier_off(priv->netdev);
1973         mlx5e_redirect_rqts(priv);
1974         mlx5e_close_channels(priv);
1975
1976         return 0;
1977 }
1978
1979 int mlx5e_close(struct net_device *netdev)
1980 {
1981         struct mlx5e_priv *priv = netdev_priv(netdev);
1982         int err;
1983
1984         if (!netif_device_present(netdev))
1985                 return -ENODEV;
1986
1987         mutex_lock(&priv->state_lock);
1988         err = mlx5e_close_locked(netdev);
1989         mutex_unlock(&priv->state_lock);
1990
1991         return err;
1992 }
1993
1994 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1995                                 struct mlx5e_rq *rq,
1996                                 struct mlx5e_rq_param *param)
1997 {
1998         struct mlx5_core_dev *mdev = priv->mdev;
1999         void *rqc = param->rqc;
2000         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2001         int err;
2002
2003         param->wq.db_numa_node = param->wq.buf_numa_node;
2004
2005         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2006                                 &rq->wq_ctrl);
2007         if (err)
2008                 return err;
2009
2010         rq->priv = priv;
2011
2012         return 0;
2013 }
2014
2015 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2016                                 struct mlx5e_cq *cq,
2017                                 struct mlx5e_cq_param *param)
2018 {
2019         struct mlx5_core_dev *mdev = priv->mdev;
2020         struct mlx5_core_cq *mcq = &cq->mcq;
2021         int eqn_not_used;
2022         unsigned int irqn;
2023         int err;
2024
2025         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2026                                &cq->wq_ctrl);
2027         if (err)
2028                 return err;
2029
2030         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2031
2032         mcq->cqe_sz     = 64;
2033         mcq->set_ci_db  = cq->wq_ctrl.db.db;
2034         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
2035         *mcq->set_ci_db = 0;
2036         *mcq->arm_db    = 0;
2037         mcq->vector     = param->eq_ix;
2038         mcq->comp       = mlx5e_completion_event;
2039         mcq->event      = mlx5e_cq_error_event;
2040         mcq->irqn       = irqn;
2041         mcq->uar        = &mdev->mlx5e_res.cq_uar;
2042
2043         cq->priv = priv;
2044
2045         return 0;
2046 }
2047
2048 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2049 {
2050         struct mlx5e_cq_param cq_param;
2051         struct mlx5e_rq_param rq_param;
2052         struct mlx5e_rq *rq = &priv->drop_rq;
2053         struct mlx5e_cq *cq = &priv->drop_rq.cq;
2054         int err;
2055
2056         memset(&cq_param, 0, sizeof(cq_param));
2057         memset(&rq_param, 0, sizeof(rq_param));
2058         mlx5e_build_drop_rq_param(&rq_param);
2059
2060         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2061         if (err)
2062                 return err;
2063
2064         err = mlx5e_enable_cq(cq, &cq_param);
2065         if (err)
2066                 goto err_destroy_cq;
2067
2068         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2069         if (err)
2070                 goto err_disable_cq;
2071
2072         err = mlx5e_enable_rq(rq, &rq_param);
2073         if (err)
2074                 goto err_destroy_rq;
2075
2076         return 0;
2077
2078 err_destroy_rq:
2079         mlx5e_destroy_rq(&priv->drop_rq);
2080
2081 err_disable_cq:
2082         mlx5e_disable_cq(&priv->drop_rq.cq);
2083
2084 err_destroy_cq:
2085         mlx5e_destroy_cq(&priv->drop_rq.cq);
2086
2087         return err;
2088 }
2089
2090 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2091 {
2092         mlx5e_disable_rq(&priv->drop_rq);
2093         mlx5e_destroy_rq(&priv->drop_rq);
2094         mlx5e_disable_cq(&priv->drop_rq.cq);
2095         mlx5e_destroy_cq(&priv->drop_rq.cq);
2096 }
2097
2098 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2099 {
2100         struct mlx5_core_dev *mdev = priv->mdev;
2101         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2102         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2103
2104         MLX5_SET(tisc, tisc, prio, tc << 1);
2105         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2106
2107         if (mlx5_lag_is_lacp_owner(mdev))
2108                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2109
2110         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2111 }
2112
2113 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2114 {
2115         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2116 }
2117
2118 int mlx5e_create_tises(struct mlx5e_priv *priv)
2119 {
2120         int err;
2121         int tc;
2122
2123         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2124                 err = mlx5e_create_tis(priv, tc);
2125                 if (err)
2126                         goto err_close_tises;
2127         }
2128
2129         return 0;
2130
2131 err_close_tises:
2132         for (tc--; tc >= 0; tc--)
2133                 mlx5e_destroy_tis(priv, tc);
2134
2135         return err;
2136 }
2137
2138 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2139 {
2140         int tc;
2141
2142         for (tc = 0; tc < priv->profile->max_tc; tc++)
2143                 mlx5e_destroy_tis(priv, tc);
2144 }
2145
2146 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2147                                       enum mlx5e_traffic_types tt)
2148 {
2149         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2150
2151         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2152
2153 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2154                                  MLX5_HASH_FIELD_SEL_DST_IP)
2155
2156 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2157                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2158                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2159                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2160
2161 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2162                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2163                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2164
2165         mlx5e_build_tir_ctx_lro(tirc, priv);
2166
2167         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2168         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2169         mlx5e_build_tir_ctx_hash(tirc, priv);
2170
2171         switch (tt) {
2172         case MLX5E_TT_IPV4_TCP:
2173                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2174                          MLX5_L3_PROT_TYPE_IPV4);
2175                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2176                          MLX5_L4_PROT_TYPE_TCP);
2177                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2178                          MLX5_HASH_IP_L4PORTS);
2179                 break;
2180
2181         case MLX5E_TT_IPV6_TCP:
2182                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2183                          MLX5_L3_PROT_TYPE_IPV6);
2184                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2185                          MLX5_L4_PROT_TYPE_TCP);
2186                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2187                          MLX5_HASH_IP_L4PORTS);
2188                 break;
2189
2190         case MLX5E_TT_IPV4_UDP:
2191                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2192                          MLX5_L3_PROT_TYPE_IPV4);
2193                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2194                          MLX5_L4_PROT_TYPE_UDP);
2195                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2196                          MLX5_HASH_IP_L4PORTS);
2197                 break;
2198
2199         case MLX5E_TT_IPV6_UDP:
2200                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2201                          MLX5_L3_PROT_TYPE_IPV6);
2202                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2203                          MLX5_L4_PROT_TYPE_UDP);
2204                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2205                          MLX5_HASH_IP_L4PORTS);
2206                 break;
2207
2208         case MLX5E_TT_IPV4_IPSEC_AH:
2209                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2210                          MLX5_L3_PROT_TYPE_IPV4);
2211                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2212                          MLX5_HASH_IP_IPSEC_SPI);
2213                 break;
2214
2215         case MLX5E_TT_IPV6_IPSEC_AH:
2216                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2217                          MLX5_L3_PROT_TYPE_IPV6);
2218                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2219                          MLX5_HASH_IP_IPSEC_SPI);
2220                 break;
2221
2222         case MLX5E_TT_IPV4_IPSEC_ESP:
2223                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2224                          MLX5_L3_PROT_TYPE_IPV4);
2225                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2226                          MLX5_HASH_IP_IPSEC_SPI);
2227                 break;
2228
2229         case MLX5E_TT_IPV6_IPSEC_ESP:
2230                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2231                          MLX5_L3_PROT_TYPE_IPV6);
2232                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2233                          MLX5_HASH_IP_IPSEC_SPI);
2234                 break;
2235
2236         case MLX5E_TT_IPV4:
2237                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2238                          MLX5_L3_PROT_TYPE_IPV4);
2239                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2240                          MLX5_HASH_IP);
2241                 break;
2242
2243         case MLX5E_TT_IPV6:
2244                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2245                          MLX5_L3_PROT_TYPE_IPV6);
2246                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2247                          MLX5_HASH_IP);
2248                 break;
2249         default:
2250                 WARN_ONCE(true,
2251                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2252         }
2253 }
2254
2255 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2256                                        u32 rqtn)
2257 {
2258         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2259
2260         mlx5e_build_tir_ctx_lro(tirc, priv);
2261
2262         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2263         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2264         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2265 }
2266
2267 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2268 {
2269         struct mlx5e_tir *tir;
2270         void *tirc;
2271         int inlen;
2272         int err;
2273         u32 *in;
2274         int tt;
2275
2276         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2277         in = mlx5_vzalloc(inlen);
2278         if (!in)
2279                 return -ENOMEM;
2280
2281         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2282                 memset(in, 0, inlen);
2283                 tir = &priv->indir_tir[tt];
2284                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2285                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2286                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2287                 if (err)
2288                         goto err_destroy_tirs;
2289         }
2290
2291         kvfree(in);
2292
2293         return 0;
2294
2295 err_destroy_tirs:
2296         for (tt--; tt >= 0; tt--)
2297                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2298
2299         kvfree(in);
2300
2301         return err;
2302 }
2303
2304 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2305 {
2306         int nch = priv->profile->max_nch(priv->mdev);
2307         struct mlx5e_tir *tir;
2308         void *tirc;
2309         int inlen;
2310         int err;
2311         u32 *in;
2312         int ix;
2313
2314         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2315         in = mlx5_vzalloc(inlen);
2316         if (!in)
2317                 return -ENOMEM;
2318
2319         for (ix = 0; ix < nch; ix++) {
2320                 memset(in, 0, inlen);
2321                 tir = &priv->direct_tir[ix];
2322                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2323                 mlx5e_build_direct_tir_ctx(priv, tirc,
2324                                            priv->direct_tir[ix].rqt.rqtn);
2325                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2326                 if (err)
2327                         goto err_destroy_ch_tirs;
2328         }
2329
2330         kvfree(in);
2331
2332         return 0;
2333
2334 err_destroy_ch_tirs:
2335         for (ix--; ix >= 0; ix--)
2336                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2337
2338         kvfree(in);
2339
2340         return err;
2341 }
2342
2343 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2344 {
2345         int i;
2346
2347         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2348                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2349 }
2350
2351 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2352 {
2353         int nch = priv->profile->max_nch(priv->mdev);
2354         int i;
2355
2356         for (i = 0; i < nch; i++)
2357                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2358 }
2359
2360 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2361 {
2362         int err = 0;
2363         int i;
2364
2365         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2366                 return 0;
2367
2368         for (i = 0; i < priv->params.num_channels; i++) {
2369                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2370                 if (err)
2371                         return err;
2372         }
2373
2374         return 0;
2375 }
2376
2377 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2378 {
2379         struct mlx5e_priv *priv = netdev_priv(netdev);
2380         bool was_opened;
2381         int err = 0;
2382
2383         if (tc && tc != MLX5E_MAX_NUM_TC)
2384                 return -EINVAL;
2385
2386         mutex_lock(&priv->state_lock);
2387
2388         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2389         if (was_opened)
2390                 mlx5e_close_locked(priv->netdev);
2391
2392         priv->params.num_tc = tc ? tc : 1;
2393
2394         if (was_opened)
2395                 err = mlx5e_open_locked(priv->netdev);
2396
2397         mutex_unlock(&priv->state_lock);
2398
2399         return err;
2400 }
2401
2402 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2403                               __be16 proto, struct tc_to_netdev *tc)
2404 {
2405         struct mlx5e_priv *priv = netdev_priv(dev);
2406
2407         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2408                 goto mqprio;
2409
2410         switch (tc->type) {
2411         case TC_SETUP_CLSFLOWER:
2412                 switch (tc->cls_flower->command) {
2413                 case TC_CLSFLOWER_REPLACE:
2414                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2415                 case TC_CLSFLOWER_DESTROY:
2416                         return mlx5e_delete_flower(priv, tc->cls_flower);
2417                 case TC_CLSFLOWER_STATS:
2418                         return mlx5e_stats_flower(priv, tc->cls_flower);
2419                 }
2420         default:
2421                 return -EOPNOTSUPP;
2422         }
2423
2424 mqprio:
2425         if (tc->type != TC_SETUP_MQPRIO)
2426                 return -EINVAL;
2427
2428         return mlx5e_setup_tc(dev, tc->tc);
2429 }
2430
2431 struct rtnl_link_stats64 *
2432 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2433 {
2434         struct mlx5e_priv *priv = netdev_priv(dev);
2435         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2436         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2437         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2438
2439         stats->rx_packets = sstats->rx_packets;
2440         stats->rx_bytes   = sstats->rx_bytes;
2441         stats->tx_packets = sstats->tx_packets;
2442         stats->tx_bytes   = sstats->tx_bytes;
2443
2444         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2445         stats->tx_dropped = sstats->tx_queue_dropped;
2446
2447         stats->rx_length_errors =
2448                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2449                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2450                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2451         stats->rx_crc_errors =
2452                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2453         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2454         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2455         stats->tx_carrier_errors =
2456                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2457         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2458                            stats->rx_frame_errors;
2459         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2460
2461         /* vport multicast also counts packets that are dropped due to steering
2462          * or rx out of buffer
2463          */
2464         stats->multicast =
2465                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2466
2467         return stats;
2468 }
2469
2470 static void mlx5e_set_rx_mode(struct net_device *dev)
2471 {
2472         struct mlx5e_priv *priv = netdev_priv(dev);
2473
2474         queue_work(priv->wq, &priv->set_rx_mode_work);
2475 }
2476
2477 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2478 {
2479         struct mlx5e_priv *priv = netdev_priv(netdev);
2480         struct sockaddr *saddr = addr;
2481
2482         if (!is_valid_ether_addr(saddr->sa_data))
2483                 return -EADDRNOTAVAIL;
2484
2485         netif_addr_lock_bh(netdev);
2486         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2487         netif_addr_unlock_bh(netdev);
2488
2489         queue_work(priv->wq, &priv->set_rx_mode_work);
2490
2491         return 0;
2492 }
2493
2494 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2495         do {                                            \
2496                 if (enable)                             \
2497                         netdev->features |= feature;    \
2498                 else                                    \
2499                         netdev->features &= ~feature;   \
2500         } while (0)
2501
2502 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2503
2504 static int set_feature_lro(struct net_device *netdev, bool enable)
2505 {
2506         struct mlx5e_priv *priv = netdev_priv(netdev);
2507         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2508         int err;
2509
2510         mutex_lock(&priv->state_lock);
2511
2512         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2513                 mlx5e_close_locked(priv->netdev);
2514
2515         priv->params.lro_en = enable;
2516         err = mlx5e_modify_tirs_lro(priv);
2517         if (err) {
2518                 netdev_err(netdev, "lro modify failed, %d\n", err);
2519                 priv->params.lro_en = !enable;
2520         }
2521
2522         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2523                 mlx5e_open_locked(priv->netdev);
2524
2525         mutex_unlock(&priv->state_lock);
2526
2527         return err;
2528 }
2529
2530 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2531 {
2532         struct mlx5e_priv *priv = netdev_priv(netdev);
2533
2534         if (enable)
2535                 mlx5e_enable_vlan_filter(priv);
2536         else
2537                 mlx5e_disable_vlan_filter(priv);
2538
2539         return 0;
2540 }
2541
2542 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2543 {
2544         struct mlx5e_priv *priv = netdev_priv(netdev);
2545
2546         if (!enable && mlx5e_tc_num_filters(priv)) {
2547                 netdev_err(netdev,
2548                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2549                 return -EINVAL;
2550         }
2551
2552         return 0;
2553 }
2554
2555 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2556 {
2557         struct mlx5e_priv *priv = netdev_priv(netdev);
2558         struct mlx5_core_dev *mdev = priv->mdev;
2559
2560         return mlx5_set_port_fcs(mdev, !enable);
2561 }
2562
2563 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2564 {
2565         struct mlx5e_priv *priv = netdev_priv(netdev);
2566         int err;
2567
2568         mutex_lock(&priv->state_lock);
2569
2570         priv->params.vlan_strip_disable = !enable;
2571         err = mlx5e_modify_rqs_vsd(priv, !enable);
2572         if (err)
2573                 priv->params.vlan_strip_disable = enable;
2574
2575         mutex_unlock(&priv->state_lock);
2576
2577         return err;
2578 }
2579
2580 #ifdef CONFIG_RFS_ACCEL
2581 static int set_feature_arfs(struct net_device *netdev, bool enable)
2582 {
2583         struct mlx5e_priv *priv = netdev_priv(netdev);
2584         int err;
2585
2586         if (enable)
2587                 err = mlx5e_arfs_enable(priv);
2588         else
2589                 err = mlx5e_arfs_disable(priv);
2590
2591         return err;
2592 }
2593 #endif
2594
2595 static int mlx5e_handle_feature(struct net_device *netdev,
2596                                 netdev_features_t wanted_features,
2597                                 netdev_features_t feature,
2598                                 mlx5e_feature_handler feature_handler)
2599 {
2600         netdev_features_t changes = wanted_features ^ netdev->features;
2601         bool enable = !!(wanted_features & feature);
2602         int err;
2603
2604         if (!(changes & feature))
2605                 return 0;
2606
2607         err = feature_handler(netdev, enable);
2608         if (err) {
2609                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2610                            enable ? "Enable" : "Disable", feature, err);
2611                 return err;
2612         }
2613
2614         MLX5E_SET_FEATURE(netdev, feature, enable);
2615         return 0;
2616 }
2617
2618 static int mlx5e_set_features(struct net_device *netdev,
2619                               netdev_features_t features)
2620 {
2621         int err;
2622
2623         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2624                                     set_feature_lro);
2625         err |= mlx5e_handle_feature(netdev, features,
2626                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2627                                     set_feature_vlan_filter);
2628         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2629                                     set_feature_tc_num_filters);
2630         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2631                                     set_feature_rx_all);
2632         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2633                                     set_feature_rx_vlan);
2634 #ifdef CONFIG_RFS_ACCEL
2635         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2636                                     set_feature_arfs);
2637 #endif
2638
2639         return err ? -EINVAL : 0;
2640 }
2641
2642 #define MXL5_HW_MIN_MTU 64
2643 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2644
2645 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2646 {
2647         struct mlx5e_priv *priv = netdev_priv(netdev);
2648         struct mlx5_core_dev *mdev = priv->mdev;
2649         bool was_opened;
2650         u16 max_mtu;
2651         u16 min_mtu;
2652         int err = 0;
2653         bool reset;
2654
2655         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2656
2657         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2658         min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2659
2660         if (new_mtu > max_mtu || new_mtu < min_mtu) {
2661                 netdev_err(netdev,
2662                            "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2663                            __func__, new_mtu, min_mtu, max_mtu);
2664                 return -EINVAL;
2665         }
2666
2667         mutex_lock(&priv->state_lock);
2668
2669         reset = !priv->params.lro_en &&
2670                 (priv->params.rq_wq_type !=
2671                  MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2672
2673         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2674         if (was_opened && reset)
2675                 mlx5e_close_locked(netdev);
2676
2677         netdev->mtu = new_mtu;
2678         mlx5e_set_dev_port_mtu(netdev);
2679
2680         if (was_opened && reset)
2681                 err = mlx5e_open_locked(netdev);
2682
2683         mutex_unlock(&priv->state_lock);
2684
2685         return err;
2686 }
2687
2688 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2689 {
2690         switch (cmd) {
2691         case SIOCSHWTSTAMP:
2692                 return mlx5e_hwstamp_set(dev, ifr);
2693         case SIOCGHWTSTAMP:
2694                 return mlx5e_hwstamp_get(dev, ifr);
2695         default:
2696                 return -EOPNOTSUPP;
2697         }
2698 }
2699
2700 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2701 {
2702         struct mlx5e_priv *priv = netdev_priv(dev);
2703         struct mlx5_core_dev *mdev = priv->mdev;
2704
2705         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2706 }
2707
2708 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2709 {
2710         struct mlx5e_priv *priv = netdev_priv(dev);
2711         struct mlx5_core_dev *mdev = priv->mdev;
2712
2713         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2714                                            vlan, qos);
2715 }
2716
2717 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2718 {
2719         struct mlx5e_priv *priv = netdev_priv(dev);
2720         struct mlx5_core_dev *mdev = priv->mdev;
2721
2722         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2723 }
2724
2725 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2726 {
2727         struct mlx5e_priv *priv = netdev_priv(dev);
2728         struct mlx5_core_dev *mdev = priv->mdev;
2729
2730         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2731 }
2732 static int mlx5_vport_link2ifla(u8 esw_link)
2733 {
2734         switch (esw_link) {
2735         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2736                 return IFLA_VF_LINK_STATE_DISABLE;
2737         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2738                 return IFLA_VF_LINK_STATE_ENABLE;
2739         }
2740         return IFLA_VF_LINK_STATE_AUTO;
2741 }
2742
2743 static int mlx5_ifla_link2vport(u8 ifla_link)
2744 {
2745         switch (ifla_link) {
2746         case IFLA_VF_LINK_STATE_DISABLE:
2747                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2748         case IFLA_VF_LINK_STATE_ENABLE:
2749                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2750         }
2751         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2752 }
2753
2754 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2755                                    int link_state)
2756 {
2757         struct mlx5e_priv *priv = netdev_priv(dev);
2758         struct mlx5_core_dev *mdev = priv->mdev;
2759
2760         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2761                                             mlx5_ifla_link2vport(link_state));
2762 }
2763
2764 static int mlx5e_get_vf_config(struct net_device *dev,
2765                                int vf, struct ifla_vf_info *ivi)
2766 {
2767         struct mlx5e_priv *priv = netdev_priv(dev);
2768         struct mlx5_core_dev *mdev = priv->mdev;
2769         int err;
2770
2771         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2772         if (err)
2773                 return err;
2774         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2775         return 0;
2776 }
2777
2778 static int mlx5e_get_vf_stats(struct net_device *dev,
2779                               int vf, struct ifla_vf_stats *vf_stats)
2780 {
2781         struct mlx5e_priv *priv = netdev_priv(dev);
2782         struct mlx5_core_dev *mdev = priv->mdev;
2783
2784         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2785                                             vf_stats);
2786 }
2787
2788 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2789                                  struct udp_tunnel_info *ti)
2790 {
2791         struct mlx5e_priv *priv = netdev_priv(netdev);
2792
2793         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2794                 return;
2795
2796         if (!mlx5e_vxlan_allowed(priv->mdev))
2797                 return;
2798
2799         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
2800 }
2801
2802 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2803                                  struct udp_tunnel_info *ti)
2804 {
2805         struct mlx5e_priv *priv = netdev_priv(netdev);
2806
2807         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2808                 return;
2809
2810         if (!mlx5e_vxlan_allowed(priv->mdev))
2811                 return;
2812
2813         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
2814 }
2815
2816 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2817                                                     struct sk_buff *skb,
2818                                                     netdev_features_t features)
2819 {
2820         struct udphdr *udph;
2821         u16 proto;
2822         u16 port = 0;
2823
2824         switch (vlan_get_protocol(skb)) {
2825         case htons(ETH_P_IP):
2826                 proto = ip_hdr(skb)->protocol;
2827                 break;
2828         case htons(ETH_P_IPV6):
2829                 proto = ipv6_hdr(skb)->nexthdr;
2830                 break;
2831         default:
2832                 goto out;
2833         }
2834
2835         if (proto == IPPROTO_UDP) {
2836                 udph = udp_hdr(skb);
2837                 port = be16_to_cpu(udph->dest);
2838         }
2839
2840         /* Verify if UDP port is being offloaded by HW */
2841         if (port && mlx5e_vxlan_lookup_port(priv, port))
2842                 return features;
2843
2844 out:
2845         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2846         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2847 }
2848
2849 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2850                                               struct net_device *netdev,
2851                                               netdev_features_t features)
2852 {
2853         struct mlx5e_priv *priv = netdev_priv(netdev);
2854
2855         features = vlan_features_check(skb, features);
2856         features = vxlan_features_check(skb, features);
2857
2858         /* Validate if the tunneled packet is being offloaded by HW */
2859         if (skb->encapsulation &&
2860             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2861                 return mlx5e_vxlan_features_check(priv, skb, features);
2862
2863         return features;
2864 }
2865
2866 static void mlx5e_tx_timeout(struct net_device *dev)
2867 {
2868         struct mlx5e_priv *priv = netdev_priv(dev);
2869         bool sched_work = false;
2870         int i;
2871
2872         netdev_err(dev, "TX timeout detected\n");
2873
2874         for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
2875                 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
2876
2877                 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
2878                         continue;
2879                 sched_work = true;
2880                 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
2881                 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
2882                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
2883         }
2884
2885         if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
2886                 schedule_work(&priv->tx_timeout_work);
2887 }
2888
2889 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2890         .ndo_open                = mlx5e_open,
2891         .ndo_stop                = mlx5e_close,
2892         .ndo_start_xmit          = mlx5e_xmit,
2893         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2894         .ndo_select_queue        = mlx5e_select_queue,
2895         .ndo_get_stats64         = mlx5e_get_stats,
2896         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2897         .ndo_set_mac_address     = mlx5e_set_mac,
2898         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2899         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2900         .ndo_set_features        = mlx5e_set_features,
2901         .ndo_change_mtu          = mlx5e_change_mtu,
2902         .ndo_do_ioctl            = mlx5e_ioctl,
2903         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
2904 #ifdef CONFIG_RFS_ACCEL
2905         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2906 #endif
2907         .ndo_tx_timeout          = mlx5e_tx_timeout,
2908 };
2909
2910 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2911         .ndo_open                = mlx5e_open,
2912         .ndo_stop                = mlx5e_close,
2913         .ndo_start_xmit          = mlx5e_xmit,
2914         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2915         .ndo_select_queue        = mlx5e_select_queue,
2916         .ndo_get_stats64         = mlx5e_get_stats,
2917         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2918         .ndo_set_mac_address     = mlx5e_set_mac,
2919         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2920         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2921         .ndo_set_features        = mlx5e_set_features,
2922         .ndo_change_mtu          = mlx5e_change_mtu,
2923         .ndo_do_ioctl            = mlx5e_ioctl,
2924         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
2925         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
2926         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
2927         .ndo_features_check      = mlx5e_features_check,
2928 #ifdef CONFIG_RFS_ACCEL
2929         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2930 #endif
2931         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2932         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2933         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
2934         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
2935         .ndo_get_vf_config       = mlx5e_get_vf_config,
2936         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2937         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2938         .ndo_tx_timeout          = mlx5e_tx_timeout,
2939 };
2940
2941 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2942 {
2943         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2944                 return -ENOTSUPP;
2945         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2946             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2947             !MLX5_CAP_ETH(mdev, csum_cap) ||
2948             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2949             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2950             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2951             MLX5_CAP_FLOWTABLE(mdev,
2952                                flow_table_properties_nic_receive.max_ft_level)
2953                                < 3) {
2954                 mlx5_core_warn(mdev,
2955                                "Not creating net device, some required device capabilities are missing\n");
2956                 return -ENOTSUPP;
2957         }
2958         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2959                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2960         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2961                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2962
2963         return 0;
2964 }
2965
2966 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2967 {
2968         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2969
2970         return bf_buf_size -
2971                sizeof(struct mlx5e_tx_wqe) +
2972                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2973 }
2974
2975 #ifdef CONFIG_MLX5_CORE_EN_DCB
2976 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2977 {
2978         int i;
2979
2980         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2981         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2982                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2983                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2984                 priv->params.ets.prio_tc[i] = i;
2985         }
2986
2987         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2988         priv->params.ets.prio_tc[0] = 1;
2989         priv->params.ets.prio_tc[1] = 0;
2990 }
2991 #endif
2992
2993 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2994                                    u32 *indirection_rqt, int len,
2995                                    int num_channels)
2996 {
2997         int node = mdev->priv.numa_node;
2998         int node_num_of_cores;
2999         int i;
3000
3001         if (node == -1)
3002                 node = first_online_node;
3003
3004         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3005
3006         if (node_num_of_cores)
3007                 num_channels = min_t(int, num_channels, node_num_of_cores);
3008
3009         for (i = 0; i < len; i++)
3010                 indirection_rqt[i] = i % num_channels;
3011 }
3012
3013 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
3014 {
3015         return MLX5_CAP_GEN(mdev, striding_rq) &&
3016                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
3017                 MLX5_CAP_ETH(mdev, reg_umr_sq);
3018 }
3019
3020 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3021 {
3022         enum pcie_link_width width;
3023         enum pci_bus_speed speed;
3024         int err = 0;
3025
3026         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3027         if (err)
3028                 return err;
3029
3030         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3031                 return -EINVAL;
3032
3033         switch (speed) {
3034         case PCIE_SPEED_2_5GT:
3035                 *pci_bw = 2500 * width;
3036                 break;
3037         case PCIE_SPEED_5_0GT:
3038                 *pci_bw = 5000 * width;
3039                 break;
3040         case PCIE_SPEED_8_0GT:
3041                 *pci_bw = 8000 * width;
3042                 break;
3043         default:
3044                 return -EINVAL;
3045         }
3046
3047         return 0;
3048 }
3049
3050 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3051 {
3052         return (link_speed && pci_bw &&
3053                 (pci_bw < 40000) && (pci_bw < link_speed));
3054 }
3055
3056 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3057 {
3058         params->rx_cq_period_mode = cq_period_mode;
3059
3060         params->rx_cq_moderation.pkts =
3061                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3062         params->rx_cq_moderation.usec =
3063                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3064
3065         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3066                 params->rx_cq_moderation.usec =
3067                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3068 }
3069
3070 static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
3071                                    u8 *min_inline_mode)
3072 {
3073         switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
3074         case MLX5E_INLINE_MODE_L2:
3075                 *min_inline_mode = MLX5_INLINE_MODE_L2;
3076                 break;
3077         case MLX5E_INLINE_MODE_VPORT_CONTEXT:
3078                 mlx5_query_nic_vport_min_inline(mdev,
3079                                                 min_inline_mode);
3080                 break;
3081         case MLX5_INLINE_MODE_NOT_REQUIRED:
3082                 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3083                 break;
3084         }
3085 }
3086
3087 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3088                                         struct net_device *netdev,
3089                                         const struct mlx5e_profile *profile,
3090                                         void *ppriv)
3091 {
3092         struct mlx5e_priv *priv = netdev_priv(netdev);
3093         u32 link_speed = 0;
3094         u32 pci_bw = 0;
3095         u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3096                                          MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3097                                          MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3098
3099         priv->params.log_sq_size           =
3100                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3101         priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
3102                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
3103                 MLX5_WQ_TYPE_LINKED_LIST;
3104
3105         /* set CQE compression */
3106         priv->params.rx_cqe_compress_admin = false;
3107         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3108             MLX5_CAP_GEN(mdev, vport_group_manager)) {
3109                 mlx5e_get_max_linkspeed(mdev, &link_speed);
3110                 mlx5e_get_pci_bw(mdev, &pci_bw);
3111                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3112                               link_speed, pci_bw);
3113                 priv->params.rx_cqe_compress_admin =
3114                         cqe_compress_heuristic(link_speed, pci_bw);
3115         }
3116
3117         priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3118
3119         switch (priv->params.rq_wq_type) {
3120         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
3121                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
3122                 priv->params.mpwqe_log_stride_sz =
3123                         priv->params.rx_cqe_compress ?
3124                         MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
3125                         MLX5_MPWRQ_LOG_STRIDE_SIZE;
3126                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
3127                         priv->params.mpwqe_log_stride_sz;
3128                 priv->params.lro_en = true;
3129                 break;
3130         default: /* MLX5_WQ_TYPE_LINKED_LIST */
3131                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3132         }
3133
3134         mlx5_core_info(mdev,
3135                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
3136                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
3137                        BIT(priv->params.log_rq_size),
3138                        BIT(priv->params.mpwqe_log_stride_sz),
3139                        priv->params.rx_cqe_compress_admin);
3140
3141         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
3142                                             BIT(priv->params.log_rq_size));
3143
3144         priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3145         mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3146
3147         priv->params.tx_cq_moderation.usec =
3148                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3149         priv->params.tx_cq_moderation.pkts =
3150                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3151         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
3152         mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3153         priv->params.num_tc                = 1;
3154         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
3155
3156         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3157                             sizeof(priv->params.toeplitz_hash_key));
3158
3159         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3160                                       MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3161
3162         priv->params.lro_wqe_sz            =
3163                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3164
3165         /* Initialize pflags */
3166         MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3167                             priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3168
3169         priv->mdev                         = mdev;
3170         priv->netdev                       = netdev;
3171         priv->params.num_channels          = profile->max_nch(mdev);
3172         priv->profile                      = profile;
3173         priv->ppriv                        = ppriv;
3174
3175 #ifdef CONFIG_MLX5_CORE_EN_DCB
3176         mlx5e_ets_init(priv);
3177 #endif
3178
3179         mutex_init(&priv->state_lock);
3180
3181         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3182         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3183         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3184         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3185 }
3186
3187 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3188 {
3189         struct mlx5e_priv *priv = netdev_priv(netdev);
3190
3191         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3192         if (is_zero_ether_addr(netdev->dev_addr) &&
3193             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3194                 eth_hw_addr_random(netdev);
3195                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3196         }
3197 }
3198
3199 static const struct switchdev_ops mlx5e_switchdev_ops = {
3200         .switchdev_port_attr_get        = mlx5e_attr_get,
3201 };
3202
3203 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3204 {
3205         struct mlx5e_priv *priv = netdev_priv(netdev);
3206         struct mlx5_core_dev *mdev = priv->mdev;
3207         bool fcs_supported;
3208         bool fcs_enabled;
3209
3210         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3211
3212         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3213                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3214 #ifdef CONFIG_MLX5_CORE_EN_DCB
3215                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3216 #endif
3217         } else {
3218                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3219         }
3220
3221         netdev->watchdog_timeo    = 15 * HZ;
3222
3223         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
3224
3225         netdev->vlan_features    |= NETIF_F_SG;
3226         netdev->vlan_features    |= NETIF_F_IP_CSUM;
3227         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
3228         netdev->vlan_features    |= NETIF_F_GRO;
3229         netdev->vlan_features    |= NETIF_F_TSO;
3230         netdev->vlan_features    |= NETIF_F_TSO6;
3231         netdev->vlan_features    |= NETIF_F_RXCSUM;
3232         netdev->vlan_features    |= NETIF_F_RXHASH;
3233
3234         if (!!MLX5_CAP_ETH(mdev, lro_cap))
3235                 netdev->vlan_features    |= NETIF_F_LRO;
3236
3237         netdev->hw_features       = netdev->vlan_features;
3238         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
3239         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
3240         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
3241
3242         if (mlx5e_vxlan_allowed(mdev)) {
3243                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
3244                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
3245                                            NETIF_F_GSO_PARTIAL;
3246                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3247                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3248                 netdev->hw_enc_features |= NETIF_F_TSO;
3249                 netdev->hw_enc_features |= NETIF_F_TSO6;
3250                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3251                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3252                                            NETIF_F_GSO_PARTIAL;
3253                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3254         }
3255
3256         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3257
3258         if (fcs_supported)
3259                 netdev->hw_features |= NETIF_F_RXALL;
3260
3261         netdev->features          = netdev->hw_features;
3262         if (!priv->params.lro_en)
3263                 netdev->features  &= ~NETIF_F_LRO;
3264
3265         if (fcs_enabled)
3266                 netdev->features  &= ~NETIF_F_RXALL;
3267
3268 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3269         if (FT_CAP(flow_modify_en) &&
3270             FT_CAP(modify_root) &&
3271             FT_CAP(identified_miss_table_mode) &&
3272             FT_CAP(flow_table_modify)) {
3273                 netdev->hw_features      |= NETIF_F_HW_TC;
3274 #ifdef CONFIG_RFS_ACCEL
3275                 netdev->hw_features      |= NETIF_F_NTUPLE;
3276 #endif
3277         }
3278
3279         netdev->features         |= NETIF_F_HIGHDMA;
3280
3281         netdev->priv_flags       |= IFF_UNICAST_FLT;
3282
3283         mlx5e_set_netdev_dev_addr(netdev);
3284
3285 #ifdef CONFIG_NET_SWITCHDEV
3286         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3287                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3288 #endif
3289 }
3290
3291 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3292 {
3293         struct mlx5_core_dev *mdev = priv->mdev;
3294         int err;
3295
3296         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3297         if (err) {
3298                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3299                 priv->q_counter = 0;
3300         }
3301 }
3302
3303 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3304 {
3305         if (!priv->q_counter)
3306                 return;
3307
3308         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3309 }
3310
3311 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3312 {
3313         struct mlx5_core_dev *mdev = priv->mdev;
3314         u64 npages = MLX5E_REQUIRED_MTTS(priv->profile->max_nch(mdev),
3315                                          BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW));
3316         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3317         void *mkc;
3318         u32 *in;
3319         int err;
3320
3321         in = mlx5_vzalloc(inlen);
3322         if (!in)
3323                 return -ENOMEM;
3324
3325         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3326
3327         npages = min_t(u32, ALIGN(U16_MAX, 4) * 2, npages);
3328
3329         MLX5_SET(mkc, mkc, free, 1);
3330         MLX5_SET(mkc, mkc, umr_en, 1);
3331         MLX5_SET(mkc, mkc, lw, 1);
3332         MLX5_SET(mkc, mkc, lr, 1);
3333         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
3334
3335         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3336         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
3337         MLX5_SET64(mkc, mkc, len, npages << PAGE_SHIFT);
3338         MLX5_SET(mkc, mkc, translations_octword_size,
3339                  MLX5_MTT_OCTW(npages));
3340         MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
3341
3342         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen);
3343
3344         kvfree(in);
3345         return err;
3346 }
3347
3348 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3349                            struct net_device *netdev,
3350                            const struct mlx5e_profile *profile,
3351                            void *ppriv)
3352 {
3353         struct mlx5e_priv *priv = netdev_priv(netdev);
3354
3355         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3356         mlx5e_build_nic_netdev(netdev);
3357         mlx5e_vxlan_init(priv);
3358 }
3359
3360 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3361 {
3362         struct mlx5_core_dev *mdev = priv->mdev;
3363         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3364
3365         mlx5e_vxlan_cleanup(priv);
3366
3367         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3368                 mlx5_eswitch_unregister_vport_rep(esw, 0);
3369 }
3370
3371 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3372 {
3373         struct mlx5_core_dev *mdev = priv->mdev;
3374         int err;
3375         int i;
3376
3377         err = mlx5e_create_indirect_rqts(priv);
3378         if (err) {
3379                 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3380                 return err;
3381         }
3382
3383         err = mlx5e_create_direct_rqts(priv);
3384         if (err) {
3385                 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3386                 goto err_destroy_indirect_rqts;
3387         }
3388
3389         err = mlx5e_create_indirect_tirs(priv);
3390         if (err) {
3391                 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3392                 goto err_destroy_direct_rqts;
3393         }
3394
3395         err = mlx5e_create_direct_tirs(priv);
3396         if (err) {
3397                 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3398                 goto err_destroy_indirect_tirs;
3399         }
3400
3401         err = mlx5e_create_flow_steering(priv);
3402         if (err) {
3403                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3404                 goto err_destroy_direct_tirs;
3405         }
3406
3407         err = mlx5e_tc_init(priv);
3408         if (err)
3409                 goto err_destroy_flow_steering;
3410
3411         return 0;
3412
3413 err_destroy_flow_steering:
3414         mlx5e_destroy_flow_steering(priv);
3415 err_destroy_direct_tirs:
3416         mlx5e_destroy_direct_tirs(priv);
3417 err_destroy_indirect_tirs:
3418         mlx5e_destroy_indirect_tirs(priv);
3419 err_destroy_direct_rqts:
3420         for (i = 0; i < priv->profile->max_nch(mdev); i++)
3421                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3422 err_destroy_indirect_rqts:
3423         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3424         return err;
3425 }
3426
3427 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3428 {
3429         int i;
3430
3431         mlx5e_tc_cleanup(priv);
3432         mlx5e_destroy_flow_steering(priv);
3433         mlx5e_destroy_direct_tirs(priv);
3434         mlx5e_destroy_indirect_tirs(priv);
3435         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3436                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3437         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3438 }
3439
3440 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3441 {
3442         int err;
3443
3444         err = mlx5e_create_tises(priv);
3445         if (err) {
3446                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3447                 return err;
3448         }
3449
3450 #ifdef CONFIG_MLX5_CORE_EN_DCB
3451         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3452 #endif
3453         return 0;
3454 }
3455
3456 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3457 {
3458         struct net_device *netdev = priv->netdev;
3459         struct mlx5_core_dev *mdev = priv->mdev;
3460         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3461         struct mlx5_eswitch_rep rep;
3462
3463         mlx5_lag_add(mdev, netdev);
3464
3465         if (mlx5e_vxlan_allowed(mdev)) {
3466                 rtnl_lock();
3467                 udp_tunnel_get_rx_info(netdev);
3468                 rtnl_unlock();
3469         }
3470
3471         mlx5e_enable_async_events(priv);
3472         queue_work(priv->wq, &priv->set_rx_mode_work);
3473
3474         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3475                 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
3476                 rep.load = mlx5e_nic_rep_load;
3477                 rep.unload = mlx5e_nic_rep_unload;
3478                 rep.vport = 0;
3479                 rep.priv_data = priv;
3480                 mlx5_eswitch_register_vport_rep(esw, &rep);
3481         }
3482 }
3483
3484 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3485 {
3486         queue_work(priv->wq, &priv->set_rx_mode_work);
3487         mlx5e_disable_async_events(priv);
3488         mlx5_lag_remove(priv->mdev);
3489 }
3490
3491 static const struct mlx5e_profile mlx5e_nic_profile = {
3492         .init              = mlx5e_nic_init,
3493         .cleanup           = mlx5e_nic_cleanup,
3494         .init_rx           = mlx5e_init_nic_rx,
3495         .cleanup_rx        = mlx5e_cleanup_nic_rx,
3496         .init_tx           = mlx5e_init_nic_tx,
3497         .cleanup_tx        = mlx5e_cleanup_nic_tx,
3498         .enable            = mlx5e_nic_enable,
3499         .disable           = mlx5e_nic_disable,
3500         .update_stats      = mlx5e_update_stats,
3501         .max_nch           = mlx5e_get_max_num_channels,
3502         .max_tc            = MLX5E_MAX_NUM_TC,
3503 };
3504
3505 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3506                                        const struct mlx5e_profile *profile,
3507                                        void *ppriv)
3508 {
3509         int nch = profile->max_nch(mdev);
3510         struct net_device *netdev;
3511         struct mlx5e_priv *priv;
3512
3513         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3514                                     nch * profile->max_tc,
3515                                     nch);
3516         if (!netdev) {
3517                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3518                 return NULL;
3519         }
3520
3521         profile->init(mdev, netdev, profile, ppriv);
3522
3523         netif_carrier_off(netdev);
3524
3525         priv = netdev_priv(netdev);
3526
3527         priv->wq = create_singlethread_workqueue("mlx5e");
3528         if (!priv->wq)
3529                 goto err_cleanup_nic;
3530
3531         return netdev;
3532
3533 err_cleanup_nic:
3534         profile->cleanup(priv);
3535         free_netdev(netdev);
3536
3537         return NULL;
3538 }
3539
3540 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3541 {
3542         const struct mlx5e_profile *profile;
3543         struct mlx5e_priv *priv;
3544         int err;
3545
3546         priv = netdev_priv(netdev);
3547         profile = priv->profile;
3548         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
3549
3550         err = mlx5e_create_umr_mkey(priv);
3551         if (err) {
3552                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3553                 goto out;
3554         }
3555
3556         err = profile->init_tx(priv);
3557         if (err)
3558                 goto err_destroy_umr_mkey;
3559
3560         err = mlx5e_open_drop_rq(priv);
3561         if (err) {
3562                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3563                 goto err_cleanup_tx;
3564         }
3565
3566         err = profile->init_rx(priv);
3567         if (err)
3568                 goto err_close_drop_rq;
3569
3570         mlx5e_create_q_counter(priv);
3571
3572         mlx5e_init_l2_addr(priv);
3573
3574         mlx5e_set_dev_port_mtu(netdev);
3575
3576         if (profile->enable)
3577                 profile->enable(priv);
3578
3579         rtnl_lock();
3580         if (netif_running(netdev))
3581                 mlx5e_open(netdev);
3582         netif_device_attach(netdev);
3583         rtnl_unlock();
3584
3585         return 0;
3586
3587 err_close_drop_rq:
3588         mlx5e_close_drop_rq(priv);
3589
3590 err_cleanup_tx:
3591         profile->cleanup_tx(priv);
3592
3593 err_destroy_umr_mkey:
3594         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3595
3596 out:
3597         return err;
3598 }
3599
3600 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3601 {
3602         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3603         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3604         int vport;
3605         u8 mac[ETH_ALEN];
3606
3607         if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3608                 return;
3609
3610         mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3611
3612         for (vport = 1; vport < total_vfs; vport++) {
3613                 struct mlx5_eswitch_rep rep;
3614
3615                 rep.load = mlx5e_vport_rep_load;
3616                 rep.unload = mlx5e_vport_rep_unload;
3617                 rep.vport = vport;
3618                 ether_addr_copy(rep.hw_id, mac);
3619                 mlx5_eswitch_register_vport_rep(esw, &rep);
3620         }
3621 }
3622
3623 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3624 {
3625         struct mlx5e_priv *priv = netdev_priv(netdev);
3626         const struct mlx5e_profile *profile = priv->profile;
3627
3628         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3629         if (profile->disable)
3630                 profile->disable(priv);
3631
3632         flush_workqueue(priv->wq);
3633
3634         rtnl_lock();
3635         if (netif_running(netdev))
3636                 mlx5e_close(netdev);
3637         netif_device_detach(netdev);
3638         rtnl_unlock();
3639
3640         mlx5e_destroy_q_counter(priv);
3641         profile->cleanup_rx(priv);
3642         mlx5e_close_drop_rq(priv);
3643         profile->cleanup_tx(priv);
3644         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3645         cancel_delayed_work_sync(&priv->update_stats_work);
3646 }
3647
3648 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3649  * hardware contexts and to connect it to the current netdev.
3650  */
3651 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
3652 {
3653         struct mlx5e_priv *priv = vpriv;
3654         struct net_device *netdev = priv->netdev;
3655         int err;
3656
3657         if (netif_device_present(netdev))
3658                 return 0;
3659
3660         err = mlx5e_create_mdev_resources(mdev);
3661         if (err)
3662                 return err;
3663
3664         err = mlx5e_attach_netdev(mdev, netdev);
3665         if (err) {
3666                 mlx5e_destroy_mdev_resources(mdev);
3667                 return err;
3668         }
3669
3670         return 0;
3671 }
3672
3673 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
3674 {
3675         struct mlx5e_priv *priv = vpriv;
3676         struct net_device *netdev = priv->netdev;
3677
3678         if (!netif_device_present(netdev))
3679                 return;
3680
3681         mlx5e_detach_netdev(mdev, netdev);
3682         mlx5e_destroy_mdev_resources(mdev);
3683 }
3684
3685 static void *mlx5e_add(struct mlx5_core_dev *mdev)
3686 {
3687         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3688         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3689         void *ppriv = NULL;
3690         void *priv;
3691         int vport;
3692         int err;
3693         struct net_device *netdev;
3694
3695         err = mlx5e_check_required_hca_cap(mdev);
3696         if (err)
3697                 return NULL;
3698
3699         mlx5e_register_vport_rep(mdev);
3700
3701         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3702                 ppriv = &esw->offloads.vport_reps[0];
3703
3704         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
3705         if (!netdev) {
3706                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
3707                 goto err_unregister_reps;
3708         }
3709
3710         priv = netdev_priv(netdev);
3711
3712         err = mlx5e_attach(mdev, priv);
3713         if (err) {
3714                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
3715                 goto err_destroy_netdev;
3716         }
3717
3718         err = register_netdev(netdev);
3719         if (err) {
3720                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3721                 goto err_detach;
3722         }
3723
3724         return priv;
3725
3726 err_detach:
3727         mlx5e_detach(mdev, priv);
3728
3729 err_destroy_netdev:
3730         mlx5e_destroy_netdev(mdev, priv);
3731
3732 err_unregister_reps:
3733         for (vport = 1; vport < total_vfs; vport++)
3734                 mlx5_eswitch_unregister_vport_rep(esw, vport);
3735
3736         return NULL;
3737 }
3738
3739 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
3740 {
3741         const struct mlx5e_profile *profile = priv->profile;
3742         struct net_device *netdev = priv->netdev;
3743
3744         unregister_netdev(netdev);
3745         destroy_workqueue(priv->wq);
3746         if (profile->cleanup)
3747                 profile->cleanup(priv);
3748         free_netdev(netdev);
3749 }
3750
3751 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
3752 {
3753         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3754         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3755         struct mlx5e_priv *priv = vpriv;
3756         int vport;
3757
3758         for (vport = 1; vport < total_vfs; vport++)
3759                 mlx5_eswitch_unregister_vport_rep(esw, vport);
3760
3761         mlx5e_detach(mdev, vpriv);
3762         mlx5e_destroy_netdev(mdev, priv);
3763 }
3764
3765 static void *mlx5e_get_netdev(void *vpriv)
3766 {
3767         struct mlx5e_priv *priv = vpriv;
3768
3769         return priv->netdev;
3770 }
3771
3772 static struct mlx5_interface mlx5e_interface = {
3773         .add       = mlx5e_add,
3774         .remove    = mlx5e_remove,
3775         .attach    = mlx5e_attach,
3776         .detach    = mlx5e_detach,
3777         .event     = mlx5e_async_event,
3778         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
3779         .get_dev   = mlx5e_get_netdev,
3780 };
3781
3782 void mlx5e_init(void)
3783 {
3784         mlx5e_build_ptys2ethtool_map();
3785         mlx5_register_interface(&mlx5e_interface);
3786 }
3787
3788 void mlx5e_cleanup(void)
3789 {
3790         mlx5_unregister_interface(&mlx5e_interface);
3791 }