drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/mlx5/fs.h>
  34 #include "en.h"
  35 #include "eswitch.h"
  36
  37 struct mlx5e_rq_param {
  38         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  39         struct mlx5_wq_param       wq;
  40 };
  41
  42 struct mlx5e_sq_param {
  43         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  44         struct mlx5_wq_param       wq;
  45         u16                        max_inline;
  46 };
  47
  48 struct mlx5e_cq_param {
  49         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  50         struct mlx5_wq_param       wq;
  51         u16                        eq_ix;
  52 };
  53
  54 struct mlx5e_channel_param {
  55         struct mlx5e_rq_param      rq;
  56         struct mlx5e_sq_param      sq;
  57         struct mlx5e_cq_param      rx_cq;
  58         struct mlx5e_cq_param      tx_cq;
  59 };
  60
  61 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  62 {
  63         struct mlx5_core_dev *mdev = priv->mdev;
  64         u8 port_state;
  65
  66         port_state = mlx5_query_vport_state(mdev,
  67                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  68
  69         if (port_state == VPORT_STATE_UP)
  70                 netif_carrier_on(priv->netdev);
  71         else
  72                 netif_carrier_off(priv->netdev);
  73 }
  74
  75 static void mlx5e_update_carrier_work(struct work_struct *work)
  76 {
  77         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  78                                                update_carrier_work);
  79
  80         mutex_lock(&priv->state_lock);
  81         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  82                 mlx5e_update_carrier(priv);
  83         mutex_unlock(&priv->state_lock);
  84 }
  85
  86 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
  87 {
  88         struct mlx5_core_dev *mdev = priv->mdev;
  89         struct mlx5e_pport_stats *s = &priv->stats.pport;
  90         u32 *in;
  91         u32 *out;
  92         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
  93
  94         in  = mlx5_vzalloc(sz);
  95         out = mlx5_vzalloc(sz);
  96         if (!in || !out)
  97                 goto free_out;
  98
  99         MLX5_SET(ppcnt_reg, in, local_port, 1);
 100
 101         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 102         mlx5_core_access_reg(mdev, in, sz, out,
 103                              sz, MLX5_REG_PPCNT, 0, 0);
 104         memcpy(s->IEEE_802_3_counters,
 105                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 106                sizeof(s->IEEE_802_3_counters));
 107
 108         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 109         mlx5_core_access_reg(mdev, in, sz, out,
 110                              sz, MLX5_REG_PPCNT, 0, 0);
 111         memcpy(s->RFC_2863_counters,
 112                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 113                sizeof(s->RFC_2863_counters));
 114
 115         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 116         mlx5_core_access_reg(mdev, in, sz, out,
 117                              sz, MLX5_REG_PPCNT, 0, 0);
 118         memcpy(s->RFC_2819_counters,
 119                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 120                sizeof(s->RFC_2819_counters));
 121
 122 free_out:
 123         kvfree(in);
 124         kvfree(out);
 125 }
 126
 127 void mlx5e_update_stats(struct mlx5e_priv *priv)
 128 {
 129         struct mlx5_core_dev *mdev = priv->mdev;
 130         struct mlx5e_vport_stats *s = &priv->stats.vport;
 131         struct mlx5e_rq_stats *rq_stats;
 132         struct mlx5e_sq_stats *sq_stats;
 133         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 134         u32 *out;
 135         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 136         u64 tx_offload_none;
 137         int i, j;
 138
 139         out = mlx5_vzalloc(outlen);
 140         if (!out)
 141                 return;
 142
 143         /* Collect firts the SW counters and then HW for consistency */
 144         s->tso_packets          = 0;
 145         s->tso_bytes            = 0;
 146         s->tx_queue_stopped     = 0;
 147         s->tx_queue_wake        = 0;
 148         s->tx_queue_dropped     = 0;
 149         tx_offload_none         = 0;
 150         s->lro_packets          = 0;
 151         s->lro_bytes            = 0;
 152         s->rx_csum_none         = 0;
 153         s->rx_csum_sw           = 0;
 154         s->rx_wqe_err           = 0;
 155         for (i = 0; i < priv->params.num_channels; i++) {
 156                 rq_stats = &priv->channel[i]->rq.stats;
 157
 158                 s->lro_packets  += rq_stats->lro_packets;
 159                 s->lro_bytes    += rq_stats->lro_bytes;
 160                 s->rx_csum_none += rq_stats->csum_none;
 161                 s->rx_csum_sw   += rq_stats->csum_sw;
 162                 s->rx_wqe_err   += rq_stats->wqe_err;
 163
 164                 for (j = 0; j < priv->params.num_tc; j++) {
 165                         sq_stats = &priv->channel[i]->sq[j].stats;
 166
 167                         s->tso_packets          += sq_stats->tso_packets;
 168                         s->tso_bytes            += sq_stats->tso_bytes;
 169                         s->tx_queue_stopped     += sq_stats->stopped;
 170                         s->tx_queue_wake        += sq_stats->wake;
 171                         s->tx_queue_dropped     += sq_stats->dropped;
 172                         tx_offload_none         += sq_stats->csum_offload_none;
 173                 }
 174         }
 175
 176         /* HW counters */
 177         memset(in, 0, sizeof(in));
 178
 179         MLX5_SET(query_vport_counter_in, in, opcode,
 180                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 181         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 182         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 183
 184         memset(out, 0, outlen);
 185
 186         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 187                 goto free_out;
 188
 189 #define MLX5_GET_CTR(p, x) \
 190         MLX5_GET64(query_vport_counter_out, p, x)
 191
 192         s->rx_error_packets     =
 193                 MLX5_GET_CTR(out, received_errors.packets);
 194         s->rx_error_bytes       =
 195                 MLX5_GET_CTR(out, received_errors.octets);
 196         s->tx_error_packets     =
 197                 MLX5_GET_CTR(out, transmit_errors.packets);
 198         s->tx_error_bytes       =
 199                 MLX5_GET_CTR(out, transmit_errors.octets);
 200
 201         s->rx_unicast_packets   =
 202                 MLX5_GET_CTR(out, received_eth_unicast.packets);
 203         s->rx_unicast_bytes     =
 204                 MLX5_GET_CTR(out, received_eth_unicast.octets);
 205         s->tx_unicast_packets   =
 206                 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 207         s->tx_unicast_bytes     =
 208                 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 209
 210         s->rx_multicast_packets =
 211                 MLX5_GET_CTR(out, received_eth_multicast.packets);
 212         s->rx_multicast_bytes   =
 213                 MLX5_GET_CTR(out, received_eth_multicast.octets);
 214         s->tx_multicast_packets =
 215                 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 216         s->tx_multicast_bytes   =
 217                 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 218
 219         s->rx_broadcast_packets =
 220                 MLX5_GET_CTR(out, received_eth_broadcast.packets);
 221         s->rx_broadcast_bytes   =
 222                 MLX5_GET_CTR(out, received_eth_broadcast.octets);
 223         s->tx_broadcast_packets =
 224                 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 225         s->tx_broadcast_bytes   =
 226                 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 227
 228         s->rx_packets =
 229                 s->rx_unicast_packets +
 230                 s->rx_multicast_packets +
 231                 s->rx_broadcast_packets;
 232         s->rx_bytes =
 233                 s->rx_unicast_bytes +
 234                 s->rx_multicast_bytes +
 235                 s->rx_broadcast_bytes;
 236         s->tx_packets =
 237                 s->tx_unicast_packets +
 238                 s->tx_multicast_packets +
 239                 s->tx_broadcast_packets;
 240         s->tx_bytes =
 241                 s->tx_unicast_bytes +
 242                 s->tx_multicast_bytes +
 243                 s->tx_broadcast_bytes;
 244
 245         /* Update calculated offload counters */
 246         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 247         s->rx_csum_good    = s->rx_packets - s->rx_csum_none -
 248                                s->rx_csum_sw;
 249
 250         mlx5e_update_pport_counters(priv);
 251 free_out:
 252         kvfree(out);
 253 }
 254
 255 static void mlx5e_update_stats_work(struct work_struct *work)
 256 {
 257         struct delayed_work *dwork = to_delayed_work(work);
 258         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 259                                                update_stats_work);
 260         mutex_lock(&priv->state_lock);
 261         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 262                 mlx5e_update_stats(priv);
 263                 schedule_delayed_work(dwork,
 264                                       msecs_to_jiffies(
 265                                               MLX5E_UPDATE_STATS_INTERVAL));
 266         }
 267         mutex_unlock(&priv->state_lock);
 268 }
 269
 270 static void __mlx5e_async_event(struct mlx5e_priv *priv,
 271                                 enum mlx5_dev_event event)
 272 {
 273         switch (event) {
 274         case MLX5_DEV_EVENT_PORT_UP:
 275         case MLX5_DEV_EVENT_PORT_DOWN:
 276                 schedule_work(&priv->update_carrier_work);
 277                 break;
 278
 279         default:
 280                 break;
 281         }
 282 }
 283
 284 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 285                               enum mlx5_dev_event event, unsigned long param)
 286 {
 287         struct mlx5e_priv *priv = vpriv;
 288
 289         spin_lock(&priv->async_events_spinlock);
 290         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 291                 __mlx5e_async_event(priv, event);
 292         spin_unlock(&priv->async_events_spinlock);
 293 }
 294
 295 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 296 {
 297         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 298 }
 299
 300 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 301 {
 302         spin_lock_irq(&priv->async_events_spinlock);
 303         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 304         spin_unlock_irq(&priv->async_events_spinlock);
 305 }
 306
 307 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 308 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 309
 310 static int mlx5e_create_rq(struct mlx5e_channel *c,
 311                            struct mlx5e_rq_param *param,
 312                            struct mlx5e_rq *rq)
 313 {
 314         struct mlx5e_priv *priv = c->priv;
 315         struct mlx5_core_dev *mdev = priv->mdev;
 316         void *rqc = param->rqc;
 317         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 318         int wq_sz;
 319         int err;
 320         int i;
 321
 322         param->wq.db_numa_node = cpu_to_node(c->cpu);
 323
 324         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 325                                 &rq->wq_ctrl);
 326         if (err)
 327                 return err;
 328
 329         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 330
 331         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 332         rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 333                                cpu_to_node(c->cpu));
 334         if (!rq->skb) {
 335                 err = -ENOMEM;
 336                 goto err_rq_wq_destroy;
 337         }
 338
 339         rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
 340                                              MLX5E_SW2HW_MTU(priv->netdev->mtu);
 341         rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
 342
 343         for (i = 0; i < wq_sz; i++) {
 344                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 345                 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 346
 347                 wqe->data.lkey       = c->mkey_be;
 348                 wqe->data.byte_count =
 349                         cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 350         }
 351
 352         rq->pdev    = c->pdev;
 353         rq->netdev  = c->netdev;
 354         rq->tstamp  = &priv->tstamp;
 355         rq->channel = c;
 356         rq->ix      = c->ix;
 357         rq->priv    = c->priv;
 358
 359         return 0;
 360
 361 err_rq_wq_destroy:
 362         mlx5_wq_destroy(&rq->wq_ctrl);
 363
 364         return err;
 365 }
 366
 367 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 368 {
 369         kfree(rq->skb);
 370         mlx5_wq_destroy(&rq->wq_ctrl);
 371 }
 372
 373 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 374 {
 375         struct mlx5e_priv *priv = rq->priv;
 376         struct mlx5_core_dev *mdev = priv->mdev;
 377
 378         void *in;
 379         void *rqc;
 380         void *wq;
 381         int inlen;
 382         int err;
 383
 384         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 385                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 386         in = mlx5_vzalloc(inlen);
 387         if (!in)
 388                 return -ENOMEM;
 389
 390         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 391         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 392
 393         memcpy(rqc, param->rqc, sizeof(param->rqc));
 394
 395         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 396         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 397         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 398         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 399                                                 MLX5_ADAPTER_PAGE_SHIFT);
 400         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 401
 402         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 403                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 404
 405         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 406
 407         kvfree(in);
 408
 409         return err;
 410 }
 411
 412 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 413 {
 414         struct mlx5e_channel *c = rq->channel;
 415         struct mlx5e_priv *priv = c->priv;
 416         struct mlx5_core_dev *mdev = priv->mdev;
 417
 418         void *in;
 419         void *rqc;
 420         int inlen;
 421         int err;
 422
 423         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 424         in = mlx5_vzalloc(inlen);
 425         if (!in)
 426                 return -ENOMEM;
 427
 428         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 429
 430         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 431         MLX5_SET(rqc, rqc, state, next_state);
 432
 433         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 434
 435         kvfree(in);
 436
 437         return err;
 438 }
 439
 440 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 441 {
 442         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 443 }
 444
 445 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 446 {
 447         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 448         struct mlx5e_channel *c = rq->channel;
 449         struct mlx5e_priv *priv = c->priv;
 450         struct mlx5_wq_ll *wq = &rq->wq;
 451
 452         while (time_before(jiffies, exp_time)) {
 453                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 454                         return 0;
 455
 456                 msleep(20);
 457         }
 458
 459         return -ETIMEDOUT;
 460 }
 461
 462 static int mlx5e_open_rq(struct mlx5e_channel *c,
 463                          struct mlx5e_rq_param *param,
 464                          struct mlx5e_rq *rq)
 465 {
 466         int err;
 467
 468         err = mlx5e_create_rq(c, param, rq);
 469         if (err)
 470                 return err;
 471
 472         err = mlx5e_enable_rq(rq, param);
 473         if (err)
 474                 goto err_destroy_rq;
 475
 476         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 477         if (err)
 478                 goto err_disable_rq;
 479
 480         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 481         mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
 482
 483         return 0;
 484
 485 err_disable_rq:
 486         mlx5e_disable_rq(rq);
 487 err_destroy_rq:
 488         mlx5e_destroy_rq(rq);
 489
 490         return err;
 491 }
 492
 493 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 494 {
 495         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 496         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 497
 498         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 499         while (!mlx5_wq_ll_is_empty(&rq->wq))
 500                 msleep(20);
 501
 502         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 503         napi_synchronize(&rq->channel->napi);
 504
 505         mlx5e_disable_rq(rq);
 506         mlx5e_destroy_rq(rq);
 507 }
 508
 509 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 510 {
 511         kfree(sq->wqe_info);
 512         kfree(sq->dma_fifo);
 513         kfree(sq->skb);
 514 }
 515
 516 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 517 {
 518         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 519         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 520
 521         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 522         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 523                                     numa);
 524         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 525                                     numa);
 526
 527         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 528                 mlx5e_free_sq_db(sq);
 529                 return -ENOMEM;
 530         }
 531
 532         sq->dma_fifo_mask = df_sz - 1;
 533
 534         return 0;
 535 }
 536
 537 static int mlx5e_create_sq(struct mlx5e_channel *c,
 538                            int tc,
 539                            struct mlx5e_sq_param *param,
 540                            struct mlx5e_sq *sq)
 541 {
 542         struct mlx5e_priv *priv = c->priv;
 543         struct mlx5_core_dev *mdev = priv->mdev;
 544
 545         void *sqc = param->sqc;
 546         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 547         int txq_ix;
 548         int err;
 549
 550         err = mlx5_alloc_map_uar(mdev, &sq->uar);
 551         if (err)
 552                 return err;
 553
 554         param->wq.db_numa_node = cpu_to_node(c->cpu);
 555
 556         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 557                                  &sq->wq_ctrl);
 558         if (err)
 559                 goto err_unmap_free_uar;
 560
 561         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 562         sq->uar_map     = sq->uar.map;
 563         sq->uar_bf_map  = sq->uar.bf_map;
 564         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 565         sq->max_inline  = param->max_inline;
 566
 567         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 568         if (err)
 569                 goto err_sq_wq_destroy;
 570
 571         txq_ix = c->ix + tc * priv->params.num_channels;
 572         sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 573
 574         sq->pdev      = c->pdev;
 575         sq->tstamp    = &priv->tstamp;
 576         sq->mkey_be   = c->mkey_be;
 577         sq->channel   = c;
 578         sq->tc        = tc;
 579         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 580         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 581         priv->txq_to_sq_map[txq_ix] = sq;
 582
 583         return 0;
 584
 585 err_sq_wq_destroy:
 586         mlx5_wq_destroy(&sq->wq_ctrl);
 587
 588 err_unmap_free_uar:
 589         mlx5_unmap_free_uar(mdev, &sq->uar);
 590
 591         return err;
 592 }
 593
 594 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 595 {
 596         struct mlx5e_channel *c = sq->channel;
 597         struct mlx5e_priv *priv = c->priv;
 598
 599         mlx5e_free_sq_db(sq);
 600         mlx5_wq_destroy(&sq->wq_ctrl);
 601         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 602 }
 603
 604 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 605 {
 606         struct mlx5e_channel *c = sq->channel;
 607         struct mlx5e_priv *priv = c->priv;
 608         struct mlx5_core_dev *mdev = priv->mdev;
 609
 610         void *in;
 611         void *sqc;
 612         void *wq;
 613         int inlen;
 614         int err;
 615
 616         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 617                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 618         in = mlx5_vzalloc(inlen);
 619         if (!in)
 620                 return -ENOMEM;
 621
 622         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 623         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 624
 625         memcpy(sqc, param->sqc, sizeof(param->sqc));
 626
 627         MLX5_SET(sqc,  sqc, tis_num_0,          priv->tisn[sq->tc]);
 628         MLX5_SET(sqc,  sqc, cqn,                c->sq[sq->tc].cq.mcq.cqn);
 629         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 630         MLX5_SET(sqc,  sqc, tis_lst_sz,         1);
 631         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 632
 633         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 634         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 635         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 636                                           MLX5_ADAPTER_PAGE_SHIFT);
 637         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 638
 639         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 640                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 641
 642         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 643
 644         kvfree(in);
 645
 646         return err;
 647 }
 648
 649 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 650 {
 651         struct mlx5e_channel *c = sq->channel;
 652         struct mlx5e_priv *priv = c->priv;
 653         struct mlx5_core_dev *mdev = priv->mdev;
 654
 655         void *in;
 656         void *sqc;
 657         int inlen;
 658         int err;
 659
 660         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 661         in = mlx5_vzalloc(inlen);
 662         if (!in)
 663                 return -ENOMEM;
 664
 665         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 666
 667         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 668         MLX5_SET(sqc, sqc, state, next_state);
 669
 670         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 671
 672         kvfree(in);
 673
 674         return err;
 675 }
 676
 677 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 678 {
 679         struct mlx5e_channel *c = sq->channel;
 680         struct mlx5e_priv *priv = c->priv;
 681         struct mlx5_core_dev *mdev = priv->mdev;
 682
 683         mlx5_core_destroy_sq(mdev, sq->sqn);
 684 }
 685
 686 static int mlx5e_open_sq(struct mlx5e_channel *c,
 687                          int tc,
 688                          struct mlx5e_sq_param *param,
 689                          struct mlx5e_sq *sq)
 690 {
 691         int err;
 692
 693         err = mlx5e_create_sq(c, tc, param, sq);
 694         if (err)
 695                 return err;
 696
 697         err = mlx5e_enable_sq(sq, param);
 698         if (err)
 699                 goto err_destroy_sq;
 700
 701         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 702         if (err)
 703                 goto err_disable_sq;
 704
 705         set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 706         netdev_tx_reset_queue(sq->txq);
 707         netif_tx_start_queue(sq->txq);
 708
 709         return 0;
 710
 711 err_disable_sq:
 712         mlx5e_disable_sq(sq);
 713 err_destroy_sq:
 714         mlx5e_destroy_sq(sq);
 715
 716         return err;
 717 }
 718
 719 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 720 {
 721         __netif_tx_lock_bh(txq);
 722         netif_tx_stop_queue(txq);
 723         __netif_tx_unlock_bh(txq);
 724 }
 725
 726 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 727 {
 728         clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 729         napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
 730         netif_tx_disable_queue(sq->txq);
 731
 732         /* ensure hw is notified of all pending wqes */
 733         if (mlx5e_sq_has_room_for(sq, 1))
 734                 mlx5e_send_nop(sq, true);
 735
 736         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 737         while (sq->cc != sq->pc) /* wait till sq is empty */
 738                 msleep(20);
 739
 740         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 741         napi_synchronize(&sq->channel->napi);
 742
 743         mlx5e_disable_sq(sq);
 744         mlx5e_destroy_sq(sq);
 745 }
 746
 747 static int mlx5e_create_cq(struct mlx5e_channel *c,
 748                            struct mlx5e_cq_param *param,
 749                            struct mlx5e_cq *cq)
 750 {
 751         struct mlx5e_priv *priv = c->priv;
 752         struct mlx5_core_dev *mdev = priv->mdev;
 753         struct mlx5_core_cq *mcq = &cq->mcq;
 754         int eqn_not_used;
 755         unsigned int irqn;
 756         int err;
 757         u32 i;
 758
 759         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 760         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 761         param->eq_ix   = c->ix;
 762
 763         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 764                                &cq->wq_ctrl);
 765         if (err)
 766                 return err;
 767
 768         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 769
 770         cq->napi        = &c->napi;
 771
 772         mcq->cqe_sz     = 64;
 773         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 774         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 775         *mcq->set_ci_db = 0;
 776         *mcq->arm_db    = 0;
 777         mcq->vector     = param->eq_ix;
 778         mcq->comp       = mlx5e_completion_event;
 779         mcq->event      = mlx5e_cq_error_event;
 780         mcq->irqn       = irqn;
 781         mcq->uar        = &priv->cq_uar;
 782
 783         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 784                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 785
 786                 cqe->op_own = 0xf1;
 787         }
 788
 789         cq->channel = c;
 790         cq->priv = priv;
 791
 792         return 0;
 793 }
 794
 795 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 796 {
 797         mlx5_wq_destroy(&cq->wq_ctrl);
 798 }
 799
 800 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 801 {
 802         struct mlx5e_priv *priv = cq->priv;
 803         struct mlx5_core_dev *mdev = priv->mdev;
 804         struct mlx5_core_cq *mcq = &cq->mcq;
 805
 806         void *in;
 807         void *cqc;
 808         int inlen;
 809         unsigned int irqn_not_used;
 810         int eqn;
 811         int err;
 812
 813         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 814                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 815         in = mlx5_vzalloc(inlen);
 816         if (!in)
 817                 return -ENOMEM;
 818
 819         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 820
 821         memcpy(cqc, param->cqc, sizeof(param->cqc));
 822
 823         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 824                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 825
 826         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 827
 828         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 829         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 830         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 831                                             MLX5_ADAPTER_PAGE_SHIFT);
 832         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 833
 834         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 835
 836         kvfree(in);
 837
 838         if (err)
 839                 return err;
 840
 841         mlx5e_cq_arm(cq);
 842
 843         return 0;
 844 }
 845
 846 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 847 {
 848         struct mlx5e_priv *priv = cq->priv;
 849         struct mlx5_core_dev *mdev = priv->mdev;
 850
 851         mlx5_core_destroy_cq(mdev, &cq->mcq);
 852 }
 853
 854 static int mlx5e_open_cq(struct mlx5e_channel *c,
 855                          struct mlx5e_cq_param *param,
 856                          struct mlx5e_cq *cq,
 857                          u16 moderation_usecs,
 858                          u16 moderation_frames)
 859 {
 860         int err;
 861         struct mlx5e_priv *priv = c->priv;
 862         struct mlx5_core_dev *mdev = priv->mdev;
 863
 864         err = mlx5e_create_cq(c, param, cq);
 865         if (err)
 866                 return err;
 867
 868         err = mlx5e_enable_cq(cq, param);
 869         if (err)
 870                 goto err_destroy_cq;
 871
 872         err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 873                                              moderation_usecs,
 874                                              moderation_frames);
 875         if (err)
 876                 goto err_destroy_cq;
 877
 878         return 0;
 879
 880 err_destroy_cq:
 881         mlx5e_destroy_cq(cq);
 882
 883         return err;
 884 }
 885
 886 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 887 {
 888         mlx5e_disable_cq(cq);
 889         mlx5e_destroy_cq(cq);
 890 }
 891
 892 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 893 {
 894         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 895 }
 896
 897 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 898                              struct mlx5e_channel_param *cparam)
 899 {
 900         struct mlx5e_priv *priv = c->priv;
 901         int err;
 902         int tc;
 903
 904         for (tc = 0; tc < c->num_tc; tc++) {
 905                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 906                                     priv->params.tx_cq_moderation_usec,
 907                                     priv->params.tx_cq_moderation_pkts);
 908                 if (err)
 909                         goto err_close_tx_cqs;
 910         }
 911
 912         return 0;
 913
 914 err_close_tx_cqs:
 915         for (tc--; tc >= 0; tc--)
 916                 mlx5e_close_cq(&c->sq[tc].cq);
 917
 918         return err;
 919 }
 920
 921 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 922 {
 923         int tc;
 924
 925         for (tc = 0; tc < c->num_tc; tc++)
 926                 mlx5e_close_cq(&c->sq[tc].cq);
 927 }
 928
 929 static int mlx5e_open_sqs(struct mlx5e_channel *c,
 930                           struct mlx5e_channel_param *cparam)
 931 {
 932         int err;
 933         int tc;
 934
 935         for (tc = 0; tc < c->num_tc; tc++) {
 936                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
 937                 if (err)
 938                         goto err_close_sqs;
 939         }
 940
 941         return 0;
 942
 943 err_close_sqs:
 944         for (tc--; tc >= 0; tc--)
 945                 mlx5e_close_sq(&c->sq[tc]);
 946
 947         return err;
 948 }
 949
 950 static void mlx5e_close_sqs(struct mlx5e_channel *c)
 951 {
 952         int tc;
 953
 954         for (tc = 0; tc < c->num_tc; tc++)
 955                 mlx5e_close_sq(&c->sq[tc]);
 956 }
 957
 958 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
 959 {
 960         int i;
 961
 962         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
 963                 priv->channeltc_to_txq_map[ix][i] =
 964                         ix + i * priv->params.num_channels;
 965 }
 966
 967 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
 968                               struct mlx5e_channel_param *cparam,
 969                               struct mlx5e_channel **cp)
 970 {
 971         struct net_device *netdev = priv->netdev;
 972         int cpu = mlx5e_get_cpu(priv, ix);
 973         struct mlx5e_channel *c;
 974         int err;
 975
 976         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
 977         if (!c)
 978                 return -ENOMEM;
 979
 980         c->priv     = priv;
 981         c->ix       = ix;
 982         c->cpu      = cpu;
 983         c->pdev     = &priv->mdev->pdev->dev;
 984         c->netdev   = priv->netdev;
 985         c->mkey_be  = cpu_to_be32(priv->mr.key);
 986         c->num_tc   = priv->params.num_tc;
 987
 988         mlx5e_build_channeltc_to_txq_map(priv, ix);
 989
 990         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
 991
 992         err = mlx5e_open_tx_cqs(c, cparam);
 993         if (err)
 994                 goto err_napi_del;
 995
 996         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
 997                             priv->params.rx_cq_moderation_usec,
 998                             priv->params.rx_cq_moderation_pkts);
 999         if (err)
1000                 goto err_close_tx_cqs;
1001
1002         napi_enable(&c->napi);
1003
1004         err = mlx5e_open_sqs(c, cparam);
1005         if (err)
1006                 goto err_disable_napi;
1007
1008         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1009         if (err)
1010                 goto err_close_sqs;
1011
1012         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1013         *cp = c;
1014
1015         return 0;
1016
1017 err_close_sqs:
1018         mlx5e_close_sqs(c);
1019
1020 err_disable_napi:
1021         napi_disable(&c->napi);
1022         mlx5e_close_cq(&c->rq.cq);
1023
1024 err_close_tx_cqs:
1025         mlx5e_close_tx_cqs(c);
1026
1027 err_napi_del:
1028         netif_napi_del(&c->napi);
1029         napi_hash_del(&c->napi);
1030         kfree(c);
1031
1032         return err;
1033 }
1034
1035 static void mlx5e_close_channel(struct mlx5e_channel *c)
1036 {
1037         mlx5e_close_rq(&c->rq);
1038         mlx5e_close_sqs(c);
1039         napi_disable(&c->napi);
1040         mlx5e_close_cq(&c->rq.cq);
1041         mlx5e_close_tx_cqs(c);
1042         netif_napi_del(&c->napi);
1043
1044         napi_hash_del(&c->napi);
1045         synchronize_rcu();
1046
1047         kfree(c);
1048 }
1049
1050 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1051                                  struct mlx5e_rq_param *param)
1052 {
1053         void *rqc = param->rqc;
1054         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1055
1056         MLX5_SET(wq, wq, wq_type,          MLX5_WQ_TYPE_LINKED_LIST);
1057         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1058         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1059         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1060         MLX5_SET(wq, wq, pd,               priv->pdn);
1061
1062         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1063         param->wq.linear = 1;
1064 }
1065
1066 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1067                                  struct mlx5e_sq_param *param)
1068 {
1069         void *sqc = param->sqc;
1070         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1071
1072         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1073         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1074         MLX5_SET(wq, wq, pd,            priv->pdn);
1075
1076         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1077         param->max_inline = priv->params.tx_max_inline;
1078 }
1079
1080 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1081                                         struct mlx5e_cq_param *param)
1082 {
1083         void *cqc = param->cqc;
1084
1085         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1086 }
1087
1088 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1089                                     struct mlx5e_cq_param *param)
1090 {
1091         void *cqc = param->cqc;
1092
1093         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_rq_size);
1094
1095         mlx5e_build_common_cq_param(priv, param);
1096 }
1097
1098 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1099                                     struct mlx5e_cq_param *param)
1100 {
1101         void *cqc = param->cqc;
1102
1103         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_sq_size);
1104
1105         mlx5e_build_common_cq_param(priv, param);
1106 }
1107
1108 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1109                                       struct mlx5e_channel_param *cparam)
1110 {
1111         memset(cparam, 0, sizeof(*cparam));
1112
1113         mlx5e_build_rq_param(priv, &cparam->rq);
1114         mlx5e_build_sq_param(priv, &cparam->sq);
1115         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1116         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1117 }
1118
1119 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1120 {
1121         struct mlx5e_channel_param cparam;
1122         int nch = priv->params.num_channels;
1123         int err = -ENOMEM;
1124         int i;
1125         int j;
1126
1127         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1128                                 GFP_KERNEL);
1129
1130         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1131                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1132
1133         if (!priv->channel || !priv->txq_to_sq_map)
1134                 goto err_free_txq_to_sq_map;
1135
1136         mlx5e_build_channel_param(priv, &cparam);
1137         for (i = 0; i < nch; i++) {
1138                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1139                 if (err)
1140                         goto err_close_channels;
1141         }
1142
1143         for (j = 0; j < nch; j++) {
1144                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1145                 if (err)
1146                         goto err_close_channels;
1147         }
1148
1149         return 0;
1150
1151 err_close_channels:
1152         for (i--; i >= 0; i--)
1153                 mlx5e_close_channel(priv->channel[i]);
1154
1155 err_free_txq_to_sq_map:
1156         kfree(priv->txq_to_sq_map);
1157         kfree(priv->channel);
1158
1159         return err;
1160 }
1161
1162 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1163 {
1164         int i;
1165
1166         for (i = 0; i < priv->params.num_channels; i++)
1167                 mlx5e_close_channel(priv->channel[i]);
1168
1169         kfree(priv->txq_to_sq_map);
1170         kfree(priv->channel);
1171 }
1172
1173 static int mlx5e_rx_hash_fn(int hfunc)
1174 {
1175         return (hfunc == ETH_RSS_HASH_TOP) ?
1176                MLX5_RX_HASH_FN_TOEPLITZ :
1177                MLX5_RX_HASH_FN_INVERTED_XOR8;
1178 }
1179
1180 static int mlx5e_bits_invert(unsigned long a, int size)
1181 {
1182         int inv = 0;
1183         int i;
1184
1185         for (i = 0; i < size; i++)
1186                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1187
1188         return inv;
1189 }
1190
1191 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1192 {
1193         int i;
1194
1195         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1196                 int ix = i;
1197
1198                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1199                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1200
1201                 ix = priv->params.indirection_rqt[ix];
1202                 ix = ix % priv->params.num_channels;
1203                 MLX5_SET(rqtc, rqtc, rq_num[i],
1204                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1205                          priv->channel[ix]->rq.rqn :
1206                          priv->drop_rq.rqn);
1207         }
1208 }
1209
1210 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1211                                 enum mlx5e_rqt_ix rqt_ix)
1212 {
1213
1214         switch (rqt_ix) {
1215         case MLX5E_INDIRECTION_RQT:
1216                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1217
1218                 break;
1219
1220         default: /* MLX5E_SINGLE_RQ_RQT */
1221                 MLX5_SET(rqtc, rqtc, rq_num[0],
1222                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1223                          priv->channel[0]->rq.rqn :
1224                          priv->drop_rq.rqn);
1225
1226                 break;
1227         }
1228 }
1229
1230 static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1231 {
1232         struct mlx5_core_dev *mdev = priv->mdev;
1233         u32 *in;
1234         void *rqtc;
1235         int inlen;
1236         int sz;
1237         int err;
1238
1239         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1240
1241         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1242         in = mlx5_vzalloc(inlen);
1243         if (!in)
1244                 return -ENOMEM;
1245
1246         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1247
1248         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1249         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1250
1251         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1252
1253         err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
1254
1255         kvfree(in);
1256
1257         return err;
1258 }
1259
1260 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1261 {
1262         struct mlx5_core_dev *mdev = priv->mdev;
1263         u32 *in;
1264         void *rqtc;
1265         int inlen;
1266         int sz;
1267         int err;
1268
1269         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1270
1271         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1272         in = mlx5_vzalloc(inlen);
1273         if (!in)
1274                 return -ENOMEM;
1275
1276         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1277
1278         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1279
1280         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1281
1282         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1283
1284         err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1285
1286         kvfree(in);
1287
1288         return err;
1289 }
1290
1291 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1292 {
1293         mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
1294 }
1295
1296 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1297 {
1298         mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1299         mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1300 }
1301
1302 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1303 {
1304         if (!priv->params.lro_en)
1305                 return;
1306
1307 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1308
1309         MLX5_SET(tirc, tirc, lro_enable_mask,
1310                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1311                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1312         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1313                  (priv->params.lro_wqe_sz -
1314                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1315         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1316                  MLX5_CAP_ETH(priv->mdev,
1317                               lro_timer_supported_periods[2]));
1318 }
1319
1320 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1321 {
1322         struct mlx5_core_dev *mdev = priv->mdev;
1323
1324         void *in;
1325         void *tirc;
1326         int inlen;
1327         int err;
1328         int tt;
1329
1330         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1331         in = mlx5_vzalloc(inlen);
1332         if (!in)
1333                 return -ENOMEM;
1334
1335         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1336         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1337
1338         mlx5e_build_tir_ctx_lro(tirc, priv);
1339
1340         for (tt = 0; tt < MLX5E_NUM_TT; tt++) {
1341                 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1342                 if (err)
1343                         break;
1344         }
1345
1346         kvfree(in);
1347
1348         return err;
1349 }
1350
1351 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1352                                                   u32 tirn)
1353 {
1354         void *in;
1355         int inlen;
1356         int err;
1357
1358         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1359         in = mlx5_vzalloc(inlen);
1360         if (!in)
1361                 return -ENOMEM;
1362
1363         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1364
1365         err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1366
1367         kvfree(in);
1368
1369         return err;
1370 }
1371
1372 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1373 {
1374         int err;
1375         int i;
1376
1377         for (i = 0; i < MLX5E_NUM_TT; i++) {
1378                 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1379                                                              priv->tirn[i]);
1380                 if (err)
1381                         return err;
1382         }
1383
1384         return 0;
1385 }
1386
1387 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1388 {
1389         struct mlx5e_priv *priv = netdev_priv(netdev);
1390         struct mlx5_core_dev *mdev = priv->mdev;
1391         int hw_mtu;
1392         int err;
1393
1394         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1395         if (err)
1396                 return err;
1397
1398         mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1399
1400         if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1401                 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1402                             __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1403
1404         netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1405         return 0;
1406 }
1407
1408 int mlx5e_open_locked(struct net_device *netdev)
1409 {
1410         struct mlx5e_priv *priv = netdev_priv(netdev);
1411         int num_txqs;
1412         int err;
1413
1414         set_bit(MLX5E_STATE_OPENED, &priv->state);
1415
1416         num_txqs = priv->params.num_channels * priv->params.num_tc;
1417         netif_set_real_num_tx_queues(netdev, num_txqs);
1418         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1419
1420         err = mlx5e_set_dev_port_mtu(netdev);
1421         if (err)
1422                 goto err_clear_state_opened_flag;
1423
1424         err = mlx5e_open_channels(priv);
1425         if (err) {
1426                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1427                            __func__, err);
1428                 goto err_clear_state_opened_flag;
1429         }
1430
1431         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1432         if (err) {
1433                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1434                            __func__, err);
1435                 goto err_close_channels;
1436         }
1437
1438         mlx5e_update_carrier(priv);
1439         mlx5e_redirect_rqts(priv);
1440         mlx5e_timestamp_init(priv);
1441
1442         schedule_delayed_work(&priv->update_stats_work, 0);
1443
1444         return 0;
1445
1446 err_close_channels:
1447         mlx5e_close_channels(priv);
1448 err_clear_state_opened_flag:
1449         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1450         return err;
1451 }
1452
1453 static int mlx5e_open(struct net_device *netdev)
1454 {
1455         struct mlx5e_priv *priv = netdev_priv(netdev);
1456         int err;
1457
1458         mutex_lock(&priv->state_lock);
1459         err = mlx5e_open_locked(netdev);
1460         mutex_unlock(&priv->state_lock);
1461
1462         return err;
1463 }
1464
1465 int mlx5e_close_locked(struct net_device *netdev)
1466 {
1467         struct mlx5e_priv *priv = netdev_priv(netdev);
1468
1469         /* May already be CLOSED in case a previous configuration operation
1470          * (e.g RX/TX queue size change) that involves close&open failed.
1471          */
1472         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1473                 return 0;
1474
1475         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1476
1477         mlx5e_timestamp_cleanup(priv);
1478         mlx5e_redirect_rqts(priv);
1479         netif_carrier_off(priv->netdev);
1480         mlx5e_close_channels(priv);
1481
1482         return 0;
1483 }
1484
1485 static int mlx5e_close(struct net_device *netdev)
1486 {
1487         struct mlx5e_priv *priv = netdev_priv(netdev);
1488         int err;
1489
1490         mutex_lock(&priv->state_lock);
1491         err = mlx5e_close_locked(netdev);
1492         mutex_unlock(&priv->state_lock);
1493
1494         return err;
1495 }
1496
1497 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1498                                 struct mlx5e_rq *rq,
1499                                 struct mlx5e_rq_param *param)
1500 {
1501         struct mlx5_core_dev *mdev = priv->mdev;
1502         void *rqc = param->rqc;
1503         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1504         int err;
1505
1506         param->wq.db_numa_node = param->wq.buf_numa_node;
1507
1508         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1509                                 &rq->wq_ctrl);
1510         if (err)
1511                 return err;
1512
1513         rq->priv = priv;
1514
1515         return 0;
1516 }
1517
1518 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1519                                 struct mlx5e_cq *cq,
1520                                 struct mlx5e_cq_param *param)
1521 {
1522         struct mlx5_core_dev *mdev = priv->mdev;
1523         struct mlx5_core_cq *mcq = &cq->mcq;
1524         int eqn_not_used;
1525         unsigned int irqn;
1526         int err;
1527
1528         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1529                                &cq->wq_ctrl);
1530         if (err)
1531                 return err;
1532
1533         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1534
1535         mcq->cqe_sz     = 64;
1536         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1537         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1538         *mcq->set_ci_db = 0;
1539         *mcq->arm_db    = 0;
1540         mcq->vector     = param->eq_ix;
1541         mcq->comp       = mlx5e_completion_event;
1542         mcq->event      = mlx5e_cq_error_event;
1543         mcq->irqn       = irqn;
1544         mcq->uar        = &priv->cq_uar;
1545
1546         cq->priv = priv;
1547
1548         return 0;
1549 }
1550
1551 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1552 {
1553         struct mlx5e_cq_param cq_param;
1554         struct mlx5e_rq_param rq_param;
1555         struct mlx5e_rq *rq = &priv->drop_rq;
1556         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1557         int err;
1558
1559         memset(&cq_param, 0, sizeof(cq_param));
1560         memset(&rq_param, 0, sizeof(rq_param));
1561         mlx5e_build_rx_cq_param(priv, &cq_param);
1562         mlx5e_build_rq_param(priv, &rq_param);
1563
1564         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1565         if (err)
1566                 return err;
1567
1568         err = mlx5e_enable_cq(cq, &cq_param);
1569         if (err)
1570                 goto err_destroy_cq;
1571
1572         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1573         if (err)
1574                 goto err_disable_cq;
1575
1576         err = mlx5e_enable_rq(rq, &rq_param);
1577         if (err)
1578                 goto err_destroy_rq;
1579
1580         return 0;
1581
1582 err_destroy_rq:
1583         mlx5e_destroy_rq(&priv->drop_rq);
1584
1585 err_disable_cq:
1586         mlx5e_disable_cq(&priv->drop_rq.cq);
1587
1588 err_destroy_cq:
1589         mlx5e_destroy_cq(&priv->drop_rq.cq);
1590
1591         return err;
1592 }
1593
1594 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1595 {
1596         mlx5e_disable_rq(&priv->drop_rq);
1597         mlx5e_destroy_rq(&priv->drop_rq);
1598         mlx5e_disable_cq(&priv->drop_rq.cq);
1599         mlx5e_destroy_cq(&priv->drop_rq.cq);
1600 }
1601
1602 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1603 {
1604         struct mlx5_core_dev *mdev = priv->mdev;
1605         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1606         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1607
1608         memset(in, 0, sizeof(in));
1609
1610         MLX5_SET(tisc, tisc, prio,  tc);
1611         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1612
1613         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1614 }
1615
1616 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1617 {
1618         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1619 }
1620
1621 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1622 {
1623         int err;
1624         int tc;
1625
1626         for (tc = 0; tc < priv->params.num_tc; tc++) {
1627                 err = mlx5e_create_tis(priv, tc);
1628                 if (err)
1629                         goto err_close_tises;
1630         }
1631
1632         return 0;
1633
1634 err_close_tises:
1635         for (tc--; tc >= 0; tc--)
1636                 mlx5e_destroy_tis(priv, tc);
1637
1638         return err;
1639 }
1640
1641 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1642 {
1643         int tc;
1644
1645         for (tc = 0; tc < priv->params.num_tc; tc++)
1646                 mlx5e_destroy_tis(priv, tc);
1647 }
1648
1649 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1650 {
1651         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1652
1653         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1654
1655 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1656                                  MLX5_HASH_FIELD_SEL_DST_IP)
1657
1658 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1659                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1660                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1661                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1662
1663 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1664                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1665                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1666
1667         mlx5e_build_tir_ctx_lro(tirc, priv);
1668
1669         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1670
1671         switch (tt) {
1672         case MLX5E_TT_ANY:
1673                 MLX5_SET(tirc, tirc, indirect_table,
1674                          priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1675                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
1676                 break;
1677         default:
1678                 MLX5_SET(tirc, tirc, indirect_table,
1679                          priv->rqtn[MLX5E_INDIRECTION_RQT]);
1680                 MLX5_SET(tirc, tirc, rx_hash_fn,
1681                          mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1682                 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1683                         void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1684                                                      rx_hash_toeplitz_key);
1685                         size_t len = MLX5_FLD_SZ_BYTES(tirc,
1686                                                        rx_hash_toeplitz_key);
1687
1688                         MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1689                         memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1690                 }
1691                 break;
1692         }
1693
1694         switch (tt) {
1695         case MLX5E_TT_IPV4_TCP:
1696                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1697                          MLX5_L3_PROT_TYPE_IPV4);
1698                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1699                          MLX5_L4_PROT_TYPE_TCP);
1700                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1701                          MLX5_HASH_IP_L4PORTS);
1702                 break;
1703
1704         case MLX5E_TT_IPV6_TCP:
1705                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1706                          MLX5_L3_PROT_TYPE_IPV6);
1707                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1708                          MLX5_L4_PROT_TYPE_TCP);
1709                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1710                          MLX5_HASH_IP_L4PORTS);
1711                 break;
1712
1713         case MLX5E_TT_IPV4_UDP:
1714                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1715                          MLX5_L3_PROT_TYPE_IPV4);
1716                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1717                          MLX5_L4_PROT_TYPE_UDP);
1718                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1719                          MLX5_HASH_IP_L4PORTS);
1720                 break;
1721
1722         case MLX5E_TT_IPV6_UDP:
1723                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1724                          MLX5_L3_PROT_TYPE_IPV6);
1725                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1726                          MLX5_L4_PROT_TYPE_UDP);
1727                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1728                          MLX5_HASH_IP_L4PORTS);
1729                 break;
1730
1731         case MLX5E_TT_IPV4_IPSEC_AH:
1732                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1733                          MLX5_L3_PROT_TYPE_IPV4);
1734                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1735                          MLX5_HASH_IP_IPSEC_SPI);
1736                 break;
1737
1738         case MLX5E_TT_IPV6_IPSEC_AH:
1739                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1740                          MLX5_L3_PROT_TYPE_IPV6);
1741                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1742                          MLX5_HASH_IP_IPSEC_SPI);
1743                 break;
1744
1745         case MLX5E_TT_IPV4_IPSEC_ESP:
1746                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1747                          MLX5_L3_PROT_TYPE_IPV4);
1748                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1749                          MLX5_HASH_IP_IPSEC_SPI);
1750                 break;
1751
1752         case MLX5E_TT_IPV6_IPSEC_ESP:
1753                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1754                          MLX5_L3_PROT_TYPE_IPV6);
1755                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1756                          MLX5_HASH_IP_IPSEC_SPI);
1757                 break;
1758
1759         case MLX5E_TT_IPV4:
1760                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1761                          MLX5_L3_PROT_TYPE_IPV4);
1762                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1763                          MLX5_HASH_IP);
1764                 break;
1765
1766         case MLX5E_TT_IPV6:
1767                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1768                          MLX5_L3_PROT_TYPE_IPV6);
1769                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1770                          MLX5_HASH_IP);
1771                 break;
1772         }
1773 }
1774
1775 static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
1776 {
1777         struct mlx5_core_dev *mdev = priv->mdev;
1778         u32 *in;
1779         void *tirc;
1780         int inlen;
1781         int err;
1782
1783         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1784         in = mlx5_vzalloc(inlen);
1785         if (!in)
1786                 return -ENOMEM;
1787
1788         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1789
1790         mlx5e_build_tir_ctx(priv, tirc, tt);
1791
1792         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1793
1794         kvfree(in);
1795
1796         return err;
1797 }
1798
1799 static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
1800 {
1801         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1802 }
1803
1804 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
1805 {
1806         int err;
1807         int i;
1808
1809         for (i = 0; i < MLX5E_NUM_TT; i++) {
1810                 err = mlx5e_create_tir(priv, i);
1811                 if (err)
1812                         goto err_destroy_tirs;
1813         }
1814
1815         return 0;
1816
1817 err_destroy_tirs:
1818         for (i--; i >= 0; i--)
1819                 mlx5e_destroy_tir(priv, i);
1820
1821         return err;
1822 }
1823
1824 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
1825 {
1826         int i;
1827
1828         for (i = 0; i < MLX5E_NUM_TT; i++)
1829                 mlx5e_destroy_tir(priv, i);
1830 }
1831
1832 static struct rtnl_link_stats64 *
1833 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1834 {
1835         struct mlx5e_priv *priv = netdev_priv(dev);
1836         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1837
1838         stats->rx_packets = vstats->rx_packets;
1839         stats->rx_bytes   = vstats->rx_bytes;
1840         stats->tx_packets = vstats->tx_packets;
1841         stats->tx_bytes   = vstats->tx_bytes;
1842         stats->multicast  = vstats->rx_multicast_packets +
1843                             vstats->tx_multicast_packets;
1844         stats->tx_errors  = vstats->tx_error_packets;
1845         stats->rx_errors  = vstats->rx_error_packets;
1846         stats->tx_dropped = vstats->tx_queue_dropped;
1847         stats->rx_crc_errors = 0;
1848         stats->rx_length_errors = 0;
1849
1850         return stats;
1851 }
1852
1853 static void mlx5e_set_rx_mode(struct net_device *dev)
1854 {
1855         struct mlx5e_priv *priv = netdev_priv(dev);
1856
1857         schedule_work(&priv->set_rx_mode_work);
1858 }
1859
1860 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1861 {
1862         struct mlx5e_priv *priv = netdev_priv(netdev);
1863         struct sockaddr *saddr = addr;
1864
1865         if (!is_valid_ether_addr(saddr->sa_data))
1866                 return -EADDRNOTAVAIL;
1867
1868         netif_addr_lock_bh(netdev);
1869         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1870         netif_addr_unlock_bh(netdev);
1871
1872         schedule_work(&priv->set_rx_mode_work);
1873
1874         return 0;
1875 }
1876
1877 static int mlx5e_set_features(struct net_device *netdev,
1878                               netdev_features_t features)
1879 {
1880         struct mlx5e_priv *priv = netdev_priv(netdev);
1881         int err = 0;
1882         netdev_features_t changes = features ^ netdev->features;
1883
1884         mutex_lock(&priv->state_lock);
1885
1886         if (changes & NETIF_F_LRO) {
1887                 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1888
1889                 if (was_opened)
1890                         mlx5e_close_locked(priv->netdev);
1891
1892                 priv->params.lro_en = !!(features & NETIF_F_LRO);
1893                 err = mlx5e_modify_tirs_lro(priv);
1894                 if (err)
1895                         mlx5_core_warn(priv->mdev, "lro modify failed, %d\n",
1896                                        err);
1897
1898                 if (was_opened)
1899                         err = mlx5e_open_locked(priv->netdev);
1900         }
1901
1902         mutex_unlock(&priv->state_lock);
1903
1904         if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1905                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1906                         mlx5e_enable_vlan_filter(priv);
1907                 else
1908                         mlx5e_disable_vlan_filter(priv);
1909         }
1910
1911         return err;
1912 }
1913
1914 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1915 {
1916         struct mlx5e_priv *priv = netdev_priv(netdev);
1917         struct mlx5_core_dev *mdev = priv->mdev;
1918         bool was_opened;
1919         int max_mtu;
1920         int err = 0;
1921
1922         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
1923
1924         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
1925
1926         if (new_mtu > max_mtu) {
1927                 netdev_err(netdev,
1928                            "%s: Bad MTU (%d) > (%d) Max\n",
1929                            __func__, new_mtu, max_mtu);
1930                 return -EINVAL;
1931         }
1932
1933         mutex_lock(&priv->state_lock);
1934
1935         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1936         if (was_opened)
1937                 mlx5e_close_locked(netdev);
1938
1939         netdev->mtu = new_mtu;
1940
1941         if (was_opened)
1942                 err = mlx5e_open_locked(netdev);
1943
1944         mutex_unlock(&priv->state_lock);
1945
1946         return err;
1947 }
1948
1949 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1950 {
1951         switch (cmd) {
1952         case SIOCSHWTSTAMP:
1953                 return mlx5e_hwstamp_set(dev, ifr);
1954         case SIOCGHWTSTAMP:
1955                 return mlx5e_hwstamp_get(dev, ifr);
1956         default:
1957                 return -EOPNOTSUPP;
1958         }
1959 }
1960
1961 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
1962 {
1963         struct mlx5e_priv *priv = netdev_priv(dev);
1964         struct mlx5_core_dev *mdev = priv->mdev;
1965
1966         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
1967 }
1968
1969 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
1970 {
1971         struct mlx5e_priv *priv = netdev_priv(dev);
1972         struct mlx5_core_dev *mdev = priv->mdev;
1973
1974         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
1975                                            vlan, qos);
1976 }
1977
1978 static int mlx5_vport_link2ifla(u8 esw_link)
1979 {
1980         switch (esw_link) {
1981         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
1982                 return IFLA_VF_LINK_STATE_DISABLE;
1983         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
1984                 return IFLA_VF_LINK_STATE_ENABLE;
1985         }
1986         return IFLA_VF_LINK_STATE_AUTO;
1987 }
1988
1989 static int mlx5_ifla_link2vport(u8 ifla_link)
1990 {
1991         switch (ifla_link) {
1992         case IFLA_VF_LINK_STATE_DISABLE:
1993                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
1994         case IFLA_VF_LINK_STATE_ENABLE:
1995                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
1996         }
1997         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
1998 }
1999
2000 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2001                                    int link_state)
2002 {
2003         struct mlx5e_priv *priv = netdev_priv(dev);
2004         struct mlx5_core_dev *mdev = priv->mdev;
2005
2006         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2007                                             mlx5_ifla_link2vport(link_state));
2008 }
2009
2010 static int mlx5e_get_vf_config(struct net_device *dev,
2011                                int vf, struct ifla_vf_info *ivi)
2012 {
2013         struct mlx5e_priv *priv = netdev_priv(dev);
2014         struct mlx5_core_dev *mdev = priv->mdev;
2015         int err;
2016
2017         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2018         if (err)
2019                 return err;
2020         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2021         return 0;
2022 }
2023
2024 static int mlx5e_get_vf_stats(struct net_device *dev,
2025                               int vf, struct ifla_vf_stats *vf_stats)
2026 {
2027         struct mlx5e_priv *priv = netdev_priv(dev);
2028         struct mlx5_core_dev *mdev = priv->mdev;
2029
2030         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2031                                             vf_stats);
2032 }
2033
2034 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2035         .ndo_open                = mlx5e_open,
2036         .ndo_stop                = mlx5e_close,
2037         .ndo_start_xmit          = mlx5e_xmit,
2038         .ndo_get_stats64         = mlx5e_get_stats,
2039         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2040         .ndo_set_mac_address     = mlx5e_set_mac,
2041         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2042         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2043         .ndo_set_features        = mlx5e_set_features,
2044         .ndo_change_mtu          = mlx5e_change_mtu,
2045         .ndo_do_ioctl            = mlx5e_ioctl,
2046 };
2047
2048 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2049         .ndo_open                = mlx5e_open,
2050         .ndo_stop                = mlx5e_close,
2051         .ndo_start_xmit          = mlx5e_xmit,
2052         .ndo_get_stats64         = mlx5e_get_stats,
2053         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2054         .ndo_set_mac_address     = mlx5e_set_mac,
2055         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2056         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2057         .ndo_set_features        = mlx5e_set_features,
2058         .ndo_change_mtu          = mlx5e_change_mtu,
2059         .ndo_do_ioctl            = mlx5e_ioctl,
2060         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2061         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2062         .ndo_get_vf_config       = mlx5e_get_vf_config,
2063         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2064         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2065 };
2066
2067 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2068 {
2069         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2070                 return -ENOTSUPP;
2071         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2072             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2073             !MLX5_CAP_ETH(mdev, csum_cap) ||
2074             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2075             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2076             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2077             MLX5_CAP_FLOWTABLE(mdev,
2078                                flow_table_properties_nic_receive.max_ft_level)
2079                                < 3) {
2080                 mlx5_core_warn(mdev,
2081                                "Not creating net device, some required device capabilities are missing\n");
2082                 return -ENOTSUPP;
2083         }
2084         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2085                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2086
2087         return 0;
2088 }
2089
2090 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2091 {
2092         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2093
2094         return bf_buf_size -
2095                sizeof(struct mlx5e_tx_wqe) +
2096                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2097 }
2098
2099 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2100                                     struct net_device *netdev,
2101                                     int num_channels)
2102 {
2103         struct mlx5e_priv *priv = netdev_priv(netdev);
2104         int i;
2105
2106         priv->params.log_sq_size           =
2107                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2108         priv->params.log_rq_size           =
2109                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2110         priv->params.rx_cq_moderation_usec =
2111                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2112         priv->params.rx_cq_moderation_pkts =
2113                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2114         priv->params.tx_cq_moderation_usec =
2115                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2116         priv->params.tx_cq_moderation_pkts =
2117                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2118         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
2119         priv->params.min_rx_wqes           =
2120                 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2121         priv->params.num_tc                = 1;
2122         priv->params.default_vlan_prio     = 0;
2123         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2124
2125         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2126                             sizeof(priv->params.toeplitz_hash_key));
2127
2128         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++)
2129                 priv->params.indirection_rqt[i] = i % num_channels;
2130
2131         priv->params.lro_wqe_sz            =
2132                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2133
2134         priv->mdev                         = mdev;
2135         priv->netdev                       = netdev;
2136         priv->params.num_channels          = num_channels;
2137         priv->default_vlan_prio            = priv->params.default_vlan_prio;
2138
2139         spin_lock_init(&priv->async_events_spinlock);
2140         mutex_init(&priv->state_lock);
2141
2142         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2143         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2144         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2145 }
2146
2147 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2148 {
2149         struct mlx5e_priv *priv = netdev_priv(netdev);
2150
2151         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2152         if (is_zero_ether_addr(netdev->dev_addr) &&
2153             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2154                 eth_hw_addr_random(netdev);
2155                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2156         }
2157 }
2158
2159 static void mlx5e_build_netdev(struct net_device *netdev)
2160 {
2161         struct mlx5e_priv *priv = netdev_priv(netdev);
2162         struct mlx5_core_dev *mdev = priv->mdev;
2163
2164         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2165
2166         if (MLX5_CAP_GEN(mdev, vport_group_manager))
2167                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2168         else
2169                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2170
2171         netdev->watchdog_timeo    = 15 * HZ;
2172
2173         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
2174
2175         netdev->vlan_features    |= NETIF_F_SG;
2176         netdev->vlan_features    |= NETIF_F_IP_CSUM;
2177         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
2178         netdev->vlan_features    |= NETIF_F_GRO;
2179         netdev->vlan_features    |= NETIF_F_TSO;
2180         netdev->vlan_features    |= NETIF_F_TSO6;
2181         netdev->vlan_features    |= NETIF_F_RXCSUM;
2182         netdev->vlan_features    |= NETIF_F_RXHASH;
2183
2184         if (!!MLX5_CAP_ETH(mdev, lro_cap))
2185                 netdev->vlan_features    |= NETIF_F_LRO;
2186
2187         netdev->hw_features       = netdev->vlan_features;
2188         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
2189         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
2190         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
2191
2192         netdev->features          = netdev->hw_features;
2193         if (!priv->params.lro_en)
2194                 netdev->features  &= ~NETIF_F_LRO;
2195
2196         netdev->features         |= NETIF_F_HIGHDMA;
2197
2198         netdev->priv_flags       |= IFF_UNICAST_FLT;
2199
2200         mlx5e_set_netdev_dev_addr(netdev);
2201 }
2202
2203 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2204                              struct mlx5_core_mr *mr)
2205 {
2206         struct mlx5_core_dev *mdev = priv->mdev;
2207         struct mlx5_create_mkey_mbox_in *in;
2208         int err;
2209
2210         in = mlx5_vzalloc(sizeof(*in));
2211         if (!in)
2212                 return -ENOMEM;
2213
2214         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2215                         MLX5_PERM_LOCAL_READ  |
2216                         MLX5_ACCESS_MODE_PA;
2217         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2218         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2219
2220         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2221                                     NULL);
2222
2223         kvfree(in);
2224
2225         return err;
2226 }
2227
2228 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2229 {
2230         struct net_device *netdev;
2231         struct mlx5e_priv *priv;
2232         int nch = mlx5e_get_max_num_channels(mdev);
2233         int err;
2234
2235         if (mlx5e_check_required_hca_cap(mdev))
2236                 return NULL;
2237
2238         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), nch, nch);
2239         if (!netdev) {
2240                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2241                 return NULL;
2242         }
2243
2244         mlx5e_build_netdev_priv(mdev, netdev, nch);
2245         mlx5e_build_netdev(netdev);
2246
2247         netif_carrier_off(netdev);
2248
2249         priv = netdev_priv(netdev);
2250
2251         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2252         if (err) {
2253                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2254                 goto err_free_netdev;
2255         }
2256
2257         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2258         if (err) {
2259                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2260                 goto err_unmap_free_uar;
2261         }
2262
2263         err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
2264         if (err) {
2265                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2266                 goto err_dealloc_pd;
2267         }
2268
2269         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2270         if (err) {
2271                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2272                 goto err_dealloc_transport_domain;
2273         }
2274
2275         err = mlx5e_create_tises(priv);
2276         if (err) {
2277                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2278                 goto err_destroy_mkey;
2279         }
2280
2281         err = mlx5e_open_drop_rq(priv);
2282         if (err) {
2283                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2284                 goto err_destroy_tises;
2285         }
2286
2287         err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
2288         if (err) {
2289                 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
2290                 goto err_close_drop_rq;
2291         }
2292
2293         err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2294         if (err) {
2295                 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2296                 goto err_destroy_rqt_indir;
2297         }
2298
2299         err = mlx5e_create_tirs(priv);
2300         if (err) {
2301                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2302                 goto err_destroy_rqt_single;
2303         }
2304
2305         err = mlx5e_create_flow_tables(priv);
2306         if (err) {
2307                 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2308                 goto err_destroy_tirs;
2309         }
2310
2311         mlx5e_init_eth_addr(priv);
2312
2313         err = register_netdev(netdev);
2314         if (err) {
2315                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2316                 goto err_destroy_flow_tables;
2317         }
2318
2319         mlx5e_enable_async_events(priv);
2320         schedule_work(&priv->set_rx_mode_work);
2321
2322         return priv;
2323
2324 err_destroy_flow_tables:
2325         mlx5e_destroy_flow_tables(priv);
2326
2327 err_destroy_tirs:
2328         mlx5e_destroy_tirs(priv);
2329
2330 err_destroy_rqt_single:
2331         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2332
2333 err_destroy_rqt_indir:
2334         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2335
2336 err_close_drop_rq:
2337         mlx5e_close_drop_rq(priv);
2338
2339 err_destroy_tises:
2340         mlx5e_destroy_tises(priv);
2341
2342 err_destroy_mkey:
2343         mlx5_core_destroy_mkey(mdev, &priv->mr);
2344
2345 err_dealloc_transport_domain:
2346         mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
2347
2348 err_dealloc_pd:
2349         mlx5_core_dealloc_pd(mdev, priv->pdn);
2350
2351 err_unmap_free_uar:
2352         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2353
2354 err_free_netdev:
2355         free_netdev(netdev);
2356
2357         return NULL;
2358 }
2359
2360 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2361 {
2362         struct mlx5e_priv *priv = vpriv;
2363         struct net_device *netdev = priv->netdev;
2364
2365         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2366
2367         schedule_work(&priv->set_rx_mode_work);
2368         mlx5e_disable_async_events(priv);
2369         flush_scheduled_work();
2370         unregister_netdev(netdev);
2371         mlx5e_destroy_flow_tables(priv);
2372         mlx5e_destroy_tirs(priv);
2373         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2374         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2375         mlx5e_close_drop_rq(priv);
2376         mlx5e_destroy_tises(priv);
2377         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
2378         mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
2379         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2380         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2381         free_netdev(netdev);
2382 }
2383
2384 static void *mlx5e_get_netdev(void *vpriv)
2385 {
2386         struct mlx5e_priv *priv = vpriv;
2387
2388         return priv->netdev;
2389 }
2390
2391 static struct mlx5_interface mlx5e_interface = {
2392         .add       = mlx5e_create_netdev,
2393         .remove    = mlx5e_destroy_netdev,
2394         .event     = mlx5e_async_event,
2395         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
2396         .get_dev   = mlx5e_get_netdev,
2397 };
2398
2399 void mlx5e_init(void)
2400 {
2401         mlx5_register_interface(&mlx5e_interface);
2402 }
2403
2404 void mlx5e_cleanup(void)
2405 {
2406         mlx5_unregister_interface(&mlx5e_interface);
2407 }