drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 struct mlx5e_rq_param {
  43         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  44         struct mlx5_wq_param       wq;
  45 };
  46
  47 struct mlx5e_sq_param {
  48         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  49         struct mlx5_wq_param       wq;
  50         u16                        max_inline;
  51 };
  52
  53 struct mlx5e_cq_param {
  54         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  55         struct mlx5_wq_param       wq;
  56         u16                        eq_ix;
  57 };
  58
  59 struct mlx5e_channel_param {
  60         struct mlx5e_rq_param      rq;
  61         struct mlx5e_sq_param      sq;
  62         struct mlx5e_cq_param      rx_cq;
  63         struct mlx5e_cq_param      tx_cq;
  64 };
  65
  66 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  67 {
  68         struct mlx5_core_dev *mdev = priv->mdev;
  69         u8 port_state;
  70
  71         port_state = mlx5_query_vport_state(mdev,
  72                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  73
  74         if (port_state == VPORT_STATE_UP)
  75                 netif_carrier_on(priv->netdev);
  76         else
  77                 netif_carrier_off(priv->netdev);
  78 }
  79
  80 static void mlx5e_update_carrier_work(struct work_struct *work)
  81 {
  82         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  83                                                update_carrier_work);
  84
  85         mutex_lock(&priv->state_lock);
  86         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  87                 mlx5e_update_carrier(priv);
  88         mutex_unlock(&priv->state_lock);
  89 }
  90
  91 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
  92 {
  93         struct mlx5_core_dev *mdev = priv->mdev;
  94         struct mlx5e_pport_stats *s = &priv->stats.pport;
  95         u32 *in;
  96         u32 *out;
  97         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
  98
  99         in  = mlx5_vzalloc(sz);
 100         out = mlx5_vzalloc(sz);
 101         if (!in || !out)
 102                 goto free_out;
 103
 104         MLX5_SET(ppcnt_reg, in, local_port, 1);
 105
 106         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 107         mlx5_core_access_reg(mdev, in, sz, out,
 108                              sz, MLX5_REG_PPCNT, 0, 0);
 109         memcpy(s->IEEE_802_3_counters,
 110                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 111                sizeof(s->IEEE_802_3_counters));
 112
 113         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 114         mlx5_core_access_reg(mdev, in, sz, out,
 115                              sz, MLX5_REG_PPCNT, 0, 0);
 116         memcpy(s->RFC_2863_counters,
 117                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 118                sizeof(s->RFC_2863_counters));
 119
 120         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 121         mlx5_core_access_reg(mdev, in, sz, out,
 122                              sz, MLX5_REG_PPCNT, 0, 0);
 123         memcpy(s->RFC_2819_counters,
 124                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 125                sizeof(s->RFC_2819_counters));
 126
 127 free_out:
 128         kvfree(in);
 129         kvfree(out);
 130 }
 131
 132 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 133 {
 134         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 135
 136         if (!priv->q_counter)
 137                 return;
 138
 139         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 140                                       &qcnt->rx_out_of_buffer);
 141 }
 142
 143 void mlx5e_update_stats(struct mlx5e_priv *priv)
 144 {
 145         struct mlx5_core_dev *mdev = priv->mdev;
 146         struct mlx5e_vport_stats *s = &priv->stats.vport;
 147         struct mlx5e_rq_stats *rq_stats;
 148         struct mlx5e_sq_stats *sq_stats;
 149         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 150         u32 *out;
 151         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 152         u64 tx_offload_none;
 153         int i, j;
 154
 155         out = mlx5_vzalloc(outlen);
 156         if (!out)
 157                 return;
 158
 159         /* Collect firts the SW counters and then HW for consistency */
 160         s->rx_packets           = 0;
 161         s->rx_bytes             = 0;
 162         s->tx_packets           = 0;
 163         s->tx_bytes             = 0;
 164         s->tso_packets          = 0;
 165         s->tso_bytes            = 0;
 166         s->tso_inner_packets    = 0;
 167         s->tso_inner_bytes      = 0;
 168         s->tx_queue_stopped     = 0;
 169         s->tx_queue_wake        = 0;
 170         s->tx_queue_dropped     = 0;
 171         s->tx_csum_inner        = 0;
 172         tx_offload_none         = 0;
 173         s->lro_packets          = 0;
 174         s->lro_bytes            = 0;
 175         s->rx_csum_none         = 0;
 176         s->rx_csum_sw           = 0;
 177         s->rx_wqe_err           = 0;
 178         for (i = 0; i < priv->params.num_channels; i++) {
 179                 rq_stats = &priv->channel[i]->rq.stats;
 180
 181                 s->rx_packets   += rq_stats->packets;
 182                 s->rx_bytes     += rq_stats->bytes;
 183                 s->lro_packets  += rq_stats->lro_packets;
 184                 s->lro_bytes    += rq_stats->lro_bytes;
 185                 s->rx_csum_none += rq_stats->csum_none;
 186                 s->rx_csum_sw   += rq_stats->csum_sw;
 187                 s->rx_wqe_err   += rq_stats->wqe_err;
 188
 189                 for (j = 0; j < priv->params.num_tc; j++) {
 190                         sq_stats = &priv->channel[i]->sq[j].stats;
 191
 192                         s->tx_packets           += sq_stats->packets;
 193                         s->tx_bytes             += sq_stats->bytes;
 194                         s->tso_packets          += sq_stats->tso_packets;
 195                         s->tso_bytes            += sq_stats->tso_bytes;
 196                         s->tso_inner_packets    += sq_stats->tso_inner_packets;
 197                         s->tso_inner_bytes      += sq_stats->tso_inner_bytes;
 198                         s->tx_queue_stopped     += sq_stats->stopped;
 199                         s->tx_queue_wake        += sq_stats->wake;
 200                         s->tx_queue_dropped     += sq_stats->dropped;
 201                         s->tx_csum_inner        += sq_stats->csum_offload_inner;
 202                         tx_offload_none         += sq_stats->csum_offload_none;
 203                 }
 204         }
 205
 206         /* HW counters */
 207         memset(in, 0, sizeof(in));
 208
 209         MLX5_SET(query_vport_counter_in, in, opcode,
 210                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 211         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 212         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 213
 214         memset(out, 0, outlen);
 215
 216         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 217                 goto free_out;
 218
 219 #define MLX5_GET_CTR(p, x) \
 220         MLX5_GET64(query_vport_counter_out, p, x)
 221
 222         s->rx_error_packets     =
 223                 MLX5_GET_CTR(out, received_errors.packets);
 224         s->rx_error_bytes       =
 225                 MLX5_GET_CTR(out, received_errors.octets);
 226         s->tx_error_packets     =
 227                 MLX5_GET_CTR(out, transmit_errors.packets);
 228         s->tx_error_bytes       =
 229                 MLX5_GET_CTR(out, transmit_errors.octets);
 230
 231         s->rx_unicast_packets   =
 232                 MLX5_GET_CTR(out, received_eth_unicast.packets);
 233         s->rx_unicast_bytes     =
 234                 MLX5_GET_CTR(out, received_eth_unicast.octets);
 235         s->tx_unicast_packets   =
 236                 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 237         s->tx_unicast_bytes     =
 238                 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 239
 240         s->rx_multicast_packets =
 241                 MLX5_GET_CTR(out, received_eth_multicast.packets);
 242         s->rx_multicast_bytes   =
 243                 MLX5_GET_CTR(out, received_eth_multicast.octets);
 244         s->tx_multicast_packets =
 245                 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 246         s->tx_multicast_bytes   =
 247                 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 248
 249         s->rx_broadcast_packets =
 250                 MLX5_GET_CTR(out, received_eth_broadcast.packets);
 251         s->rx_broadcast_bytes   =
 252                 MLX5_GET_CTR(out, received_eth_broadcast.octets);
 253         s->tx_broadcast_packets =
 254                 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 255         s->tx_broadcast_bytes   =
 256                 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 257
 258         /* Update calculated offload counters */
 259         s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
 260         s->rx_csum_good    = s->rx_packets - s->rx_csum_none -
 261                                s->rx_csum_sw;
 262
 263         mlx5e_update_pport_counters(priv);
 264         mlx5e_update_q_counter(priv);
 265
 266 free_out:
 267         kvfree(out);
 268 }
 269
 270 static void mlx5e_update_stats_work(struct work_struct *work)
 271 {
 272         struct delayed_work *dwork = to_delayed_work(work);
 273         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 274                                                update_stats_work);
 275         mutex_lock(&priv->state_lock);
 276         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 277                 mlx5e_update_stats(priv);
 278                 schedule_delayed_work(dwork,
 279                                       msecs_to_jiffies(
 280                                               MLX5E_UPDATE_STATS_INTERVAL));
 281         }
 282         mutex_unlock(&priv->state_lock);
 283 }
 284
 285 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 286                               enum mlx5_dev_event event, unsigned long param)
 287 {
 288         struct mlx5e_priv *priv = vpriv;
 289
 290         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 291                 return;
 292
 293         switch (event) {
 294         case MLX5_DEV_EVENT_PORT_UP:
 295         case MLX5_DEV_EVENT_PORT_DOWN:
 296                 schedule_work(&priv->update_carrier_work);
 297                 break;
 298
 299         default:
 300                 break;
 301         }
 302 }
 303
 304 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 305 {
 306         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 307 }
 308
 309 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 310 {
 311         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 312         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 313 }
 314
 315 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 316 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 317
 318 static int mlx5e_create_rq(struct mlx5e_channel *c,
 319                            struct mlx5e_rq_param *param,
 320                            struct mlx5e_rq *rq)
 321 {
 322         struct mlx5e_priv *priv = c->priv;
 323         struct mlx5_core_dev *mdev = priv->mdev;
 324         void *rqc = param->rqc;
 325         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 326         int wq_sz;
 327         int err;
 328         int i;
 329
 330         param->wq.db_numa_node = cpu_to_node(c->cpu);
 331
 332         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 333                                 &rq->wq_ctrl);
 334         if (err)
 335                 return err;
 336
 337         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 338
 339         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 340         rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 341                                cpu_to_node(c->cpu));
 342         if (!rq->skb) {
 343                 err = -ENOMEM;
 344                 goto err_rq_wq_destroy;
 345         }
 346
 347         rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
 348                                              MLX5E_SW2HW_MTU(priv->netdev->mtu);
 349         rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
 350
 351         for (i = 0; i < wq_sz; i++) {
 352                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 353                 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 354
 355                 wqe->data.lkey       = c->mkey_be;
 356                 wqe->data.byte_count =
 357                         cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 358         }
 359
 360         rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 361         rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 362         rq->pdev    = c->pdev;
 363         rq->netdev  = c->netdev;
 364         rq->tstamp  = &priv->tstamp;
 365         rq->channel = c;
 366         rq->ix      = c->ix;
 367         rq->priv    = c->priv;
 368
 369         return 0;
 370
 371 err_rq_wq_destroy:
 372         mlx5_wq_destroy(&rq->wq_ctrl);
 373
 374         return err;
 375 }
 376
 377 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 378 {
 379         kfree(rq->skb);
 380         mlx5_wq_destroy(&rq->wq_ctrl);
 381 }
 382
 383 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 384 {
 385         struct mlx5e_priv *priv = rq->priv;
 386         struct mlx5_core_dev *mdev = priv->mdev;
 387
 388         void *in;
 389         void *rqc;
 390         void *wq;
 391         int inlen;
 392         int err;
 393
 394         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 395                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 396         in = mlx5_vzalloc(inlen);
 397         if (!in)
 398                 return -ENOMEM;
 399
 400         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 401         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 402
 403         memcpy(rqc, param->rqc, sizeof(param->rqc));
 404
 405         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 406         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 407         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 408         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 409                                                 MLX5_ADAPTER_PAGE_SHIFT);
 410         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 411
 412         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 413                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 414
 415         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 416
 417         kvfree(in);
 418
 419         return err;
 420 }
 421
 422 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 423 {
 424         struct mlx5e_channel *c = rq->channel;
 425         struct mlx5e_priv *priv = c->priv;
 426         struct mlx5_core_dev *mdev = priv->mdev;
 427
 428         void *in;
 429         void *rqc;
 430         int inlen;
 431         int err;
 432
 433         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 434         in = mlx5_vzalloc(inlen);
 435         if (!in)
 436                 return -ENOMEM;
 437
 438         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 439
 440         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 441         MLX5_SET(rqc, rqc, state, next_state);
 442
 443         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 444
 445         kvfree(in);
 446
 447         return err;
 448 }
 449
 450 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 451 {
 452         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 453 }
 454
 455 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 456 {
 457         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 458         struct mlx5e_channel *c = rq->channel;
 459         struct mlx5e_priv *priv = c->priv;
 460         struct mlx5_wq_ll *wq = &rq->wq;
 461
 462         while (time_before(jiffies, exp_time)) {
 463                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 464                         return 0;
 465
 466                 msleep(20);
 467         }
 468
 469         return -ETIMEDOUT;
 470 }
 471
 472 static int mlx5e_open_rq(struct mlx5e_channel *c,
 473                          struct mlx5e_rq_param *param,
 474                          struct mlx5e_rq *rq)
 475 {
 476         int err;
 477
 478         err = mlx5e_create_rq(c, param, rq);
 479         if (err)
 480                 return err;
 481
 482         err = mlx5e_enable_rq(rq, param);
 483         if (err)
 484                 goto err_destroy_rq;
 485
 486         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 487         if (err)
 488                 goto err_disable_rq;
 489
 490         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 491         mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
 492
 493         return 0;
 494
 495 err_disable_rq:
 496         mlx5e_disable_rq(rq);
 497 err_destroy_rq:
 498         mlx5e_destroy_rq(rq);
 499
 500         return err;
 501 }
 502
 503 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 504 {
 505         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 506         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 507
 508         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 509         while (!mlx5_wq_ll_is_empty(&rq->wq))
 510                 msleep(20);
 511
 512         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 513         napi_synchronize(&rq->channel->napi);
 514
 515         mlx5e_disable_rq(rq);
 516         mlx5e_destroy_rq(rq);
 517 }
 518
 519 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 520 {
 521         kfree(sq->wqe_info);
 522         kfree(sq->dma_fifo);
 523         kfree(sq->skb);
 524 }
 525
 526 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 527 {
 528         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 529         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 530
 531         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 532         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 533                                     numa);
 534         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 535                                     numa);
 536
 537         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 538                 mlx5e_free_sq_db(sq);
 539                 return -ENOMEM;
 540         }
 541
 542         sq->dma_fifo_mask = df_sz - 1;
 543
 544         return 0;
 545 }
 546
 547 static int mlx5e_create_sq(struct mlx5e_channel *c,
 548                            int tc,
 549                            struct mlx5e_sq_param *param,
 550                            struct mlx5e_sq *sq)
 551 {
 552         struct mlx5e_priv *priv = c->priv;
 553         struct mlx5_core_dev *mdev = priv->mdev;
 554
 555         void *sqc = param->sqc;
 556         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 557         int txq_ix;
 558         int err;
 559
 560         err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
 561         if (err)
 562                 return err;
 563
 564         param->wq.db_numa_node = cpu_to_node(c->cpu);
 565
 566         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 567                                  &sq->wq_ctrl);
 568         if (err)
 569                 goto err_unmap_free_uar;
 570
 571         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 572         if (sq->uar.bf_map) {
 573                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 574                 sq->uar_map = sq->uar.bf_map;
 575         } else {
 576                 sq->uar_map = sq->uar.map;
 577         }
 578         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 579         sq->max_inline  = param->max_inline;
 580
 581         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 582         if (err)
 583                 goto err_sq_wq_destroy;
 584
 585         txq_ix = c->ix + tc * priv->params.num_channels;
 586         sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 587
 588         sq->pdev      = c->pdev;
 589         sq->tstamp    = &priv->tstamp;
 590         sq->mkey_be   = c->mkey_be;
 591         sq->channel   = c;
 592         sq->tc        = tc;
 593         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 594         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 595         priv->txq_to_sq_map[txq_ix] = sq;
 596
 597         return 0;
 598
 599 err_sq_wq_destroy:
 600         mlx5_wq_destroy(&sq->wq_ctrl);
 601
 602 err_unmap_free_uar:
 603         mlx5_unmap_free_uar(mdev, &sq->uar);
 604
 605         return err;
 606 }
 607
 608 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 609 {
 610         struct mlx5e_channel *c = sq->channel;
 611         struct mlx5e_priv *priv = c->priv;
 612
 613         mlx5e_free_sq_db(sq);
 614         mlx5_wq_destroy(&sq->wq_ctrl);
 615         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 616 }
 617
 618 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 619 {
 620         struct mlx5e_channel *c = sq->channel;
 621         struct mlx5e_priv *priv = c->priv;
 622         struct mlx5_core_dev *mdev = priv->mdev;
 623
 624         void *in;
 625         void *sqc;
 626         void *wq;
 627         int inlen;
 628         int err;
 629
 630         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 631                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 632         in = mlx5_vzalloc(inlen);
 633         if (!in)
 634                 return -ENOMEM;
 635
 636         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 637         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 638
 639         memcpy(sqc, param->sqc, sizeof(param->sqc));
 640
 641         MLX5_SET(sqc,  sqc, tis_num_0,          priv->tisn[sq->tc]);
 642         MLX5_SET(sqc,  sqc, cqn,                c->sq[sq->tc].cq.mcq.cqn);
 643         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 644         MLX5_SET(sqc,  sqc, tis_lst_sz,         1);
 645         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 646
 647         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 648         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 649         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 650                                           MLX5_ADAPTER_PAGE_SHIFT);
 651         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 652
 653         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 654                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 655
 656         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 657
 658         kvfree(in);
 659
 660         return err;
 661 }
 662
 663 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 664 {
 665         struct mlx5e_channel *c = sq->channel;
 666         struct mlx5e_priv *priv = c->priv;
 667         struct mlx5_core_dev *mdev = priv->mdev;
 668
 669         void *in;
 670         void *sqc;
 671         int inlen;
 672         int err;
 673
 674         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 675         in = mlx5_vzalloc(inlen);
 676         if (!in)
 677                 return -ENOMEM;
 678
 679         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 680
 681         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 682         MLX5_SET(sqc, sqc, state, next_state);
 683
 684         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 685
 686         kvfree(in);
 687
 688         return err;
 689 }
 690
 691 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 692 {
 693         struct mlx5e_channel *c = sq->channel;
 694         struct mlx5e_priv *priv = c->priv;
 695         struct mlx5_core_dev *mdev = priv->mdev;
 696
 697         mlx5_core_destroy_sq(mdev, sq->sqn);
 698 }
 699
 700 static int mlx5e_open_sq(struct mlx5e_channel *c,
 701                          int tc,
 702                          struct mlx5e_sq_param *param,
 703                          struct mlx5e_sq *sq)
 704 {
 705         int err;
 706
 707         err = mlx5e_create_sq(c, tc, param, sq);
 708         if (err)
 709                 return err;
 710
 711         err = mlx5e_enable_sq(sq, param);
 712         if (err)
 713                 goto err_destroy_sq;
 714
 715         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 716         if (err)
 717                 goto err_disable_sq;
 718
 719         set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 720         netdev_tx_reset_queue(sq->txq);
 721         netif_tx_start_queue(sq->txq);
 722
 723         return 0;
 724
 725 err_disable_sq:
 726         mlx5e_disable_sq(sq);
 727 err_destroy_sq:
 728         mlx5e_destroy_sq(sq);
 729
 730         return err;
 731 }
 732
 733 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 734 {
 735         __netif_tx_lock_bh(txq);
 736         netif_tx_stop_queue(txq);
 737         __netif_tx_unlock_bh(txq);
 738 }
 739
 740 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 741 {
 742         clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 743         napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
 744         netif_tx_disable_queue(sq->txq);
 745
 746         /* ensure hw is notified of all pending wqes */
 747         if (mlx5e_sq_has_room_for(sq, 1))
 748                 mlx5e_send_nop(sq, true);
 749
 750         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 751         while (sq->cc != sq->pc) /* wait till sq is empty */
 752                 msleep(20);
 753
 754         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 755         napi_synchronize(&sq->channel->napi);
 756
 757         mlx5e_disable_sq(sq);
 758         mlx5e_destroy_sq(sq);
 759 }
 760
 761 static int mlx5e_create_cq(struct mlx5e_channel *c,
 762                            struct mlx5e_cq_param *param,
 763                            struct mlx5e_cq *cq)
 764 {
 765         struct mlx5e_priv *priv = c->priv;
 766         struct mlx5_core_dev *mdev = priv->mdev;
 767         struct mlx5_core_cq *mcq = &cq->mcq;
 768         int eqn_not_used;
 769         unsigned int irqn;
 770         int err;
 771         u32 i;
 772
 773         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 774         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 775         param->eq_ix   = c->ix;
 776
 777         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 778                                &cq->wq_ctrl);
 779         if (err)
 780                 return err;
 781
 782         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 783
 784         cq->napi        = &c->napi;
 785
 786         mcq->cqe_sz     = 64;
 787         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 788         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 789         *mcq->set_ci_db = 0;
 790         *mcq->arm_db    = 0;
 791         mcq->vector     = param->eq_ix;
 792         mcq->comp       = mlx5e_completion_event;
 793         mcq->event      = mlx5e_cq_error_event;
 794         mcq->irqn       = irqn;
 795         mcq->uar        = &priv->cq_uar;
 796
 797         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 798                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 799
 800                 cqe->op_own = 0xf1;
 801         }
 802
 803         cq->channel = c;
 804         cq->priv = priv;
 805
 806         return 0;
 807 }
 808
 809 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 810 {
 811         mlx5_wq_destroy(&cq->wq_ctrl);
 812 }
 813
 814 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 815 {
 816         struct mlx5e_priv *priv = cq->priv;
 817         struct mlx5_core_dev *mdev = priv->mdev;
 818         struct mlx5_core_cq *mcq = &cq->mcq;
 819
 820         void *in;
 821         void *cqc;
 822         int inlen;
 823         unsigned int irqn_not_used;
 824         int eqn;
 825         int err;
 826
 827         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 828                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 829         in = mlx5_vzalloc(inlen);
 830         if (!in)
 831                 return -ENOMEM;
 832
 833         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 834
 835         memcpy(cqc, param->cqc, sizeof(param->cqc));
 836
 837         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 838                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 839
 840         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 841
 842         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 843         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 844         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 845                                             MLX5_ADAPTER_PAGE_SHIFT);
 846         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 847
 848         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 849
 850         kvfree(in);
 851
 852         if (err)
 853                 return err;
 854
 855         mlx5e_cq_arm(cq);
 856
 857         return 0;
 858 }
 859
 860 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 861 {
 862         struct mlx5e_priv *priv = cq->priv;
 863         struct mlx5_core_dev *mdev = priv->mdev;
 864
 865         mlx5_core_destroy_cq(mdev, &cq->mcq);
 866 }
 867
 868 static int mlx5e_open_cq(struct mlx5e_channel *c,
 869                          struct mlx5e_cq_param *param,
 870                          struct mlx5e_cq *cq,
 871                          u16 moderation_usecs,
 872                          u16 moderation_frames)
 873 {
 874         int err;
 875         struct mlx5e_priv *priv = c->priv;
 876         struct mlx5_core_dev *mdev = priv->mdev;
 877
 878         err = mlx5e_create_cq(c, param, cq);
 879         if (err)
 880                 return err;
 881
 882         err = mlx5e_enable_cq(cq, param);
 883         if (err)
 884                 goto err_destroy_cq;
 885
 886         if (MLX5_CAP_GEN(mdev, cq_moderation))
 887                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 888                                                moderation_usecs,
 889                                                moderation_frames);
 890         return 0;
 891
 892 err_destroy_cq:
 893         mlx5e_destroy_cq(cq);
 894
 895         return err;
 896 }
 897
 898 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 899 {
 900         mlx5e_disable_cq(cq);
 901         mlx5e_destroy_cq(cq);
 902 }
 903
 904 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 905 {
 906         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 907 }
 908
 909 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 910                              struct mlx5e_channel_param *cparam)
 911 {
 912         struct mlx5e_priv *priv = c->priv;
 913         int err;
 914         int tc;
 915
 916         for (tc = 0; tc < c->num_tc; tc++) {
 917                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 918                                     priv->params.tx_cq_moderation_usec,
 919                                     priv->params.tx_cq_moderation_pkts);
 920                 if (err)
 921                         goto err_close_tx_cqs;
 922         }
 923
 924         return 0;
 925
 926 err_close_tx_cqs:
 927         for (tc--; tc >= 0; tc--)
 928                 mlx5e_close_cq(&c->sq[tc].cq);
 929
 930         return err;
 931 }
 932
 933 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 934 {
 935         int tc;
 936
 937         for (tc = 0; tc < c->num_tc; tc++)
 938                 mlx5e_close_cq(&c->sq[tc].cq);
 939 }
 940
 941 static int mlx5e_open_sqs(struct mlx5e_channel *c,
 942                           struct mlx5e_channel_param *cparam)
 943 {
 944         int err;
 945         int tc;
 946
 947         for (tc = 0; tc < c->num_tc; tc++) {
 948                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
 949                 if (err)
 950                         goto err_close_sqs;
 951         }
 952
 953         return 0;
 954
 955 err_close_sqs:
 956         for (tc--; tc >= 0; tc--)
 957                 mlx5e_close_sq(&c->sq[tc]);
 958
 959         return err;
 960 }
 961
 962 static void mlx5e_close_sqs(struct mlx5e_channel *c)
 963 {
 964         int tc;
 965
 966         for (tc = 0; tc < c->num_tc; tc++)
 967                 mlx5e_close_sq(&c->sq[tc]);
 968 }
 969
 970 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
 971 {
 972         int i;
 973
 974         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
 975                 priv->channeltc_to_txq_map[ix][i] =
 976                         ix + i * priv->params.num_channels;
 977 }
 978
 979 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
 980                               struct mlx5e_channel_param *cparam,
 981                               struct mlx5e_channel **cp)
 982 {
 983         struct net_device *netdev = priv->netdev;
 984         int cpu = mlx5e_get_cpu(priv, ix);
 985         struct mlx5e_channel *c;
 986         int err;
 987
 988         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
 989         if (!c)
 990                 return -ENOMEM;
 991
 992         c->priv     = priv;
 993         c->ix       = ix;
 994         c->cpu      = cpu;
 995         c->pdev     = &priv->mdev->pdev->dev;
 996         c->netdev   = priv->netdev;
 997         c->mkey_be  = cpu_to_be32(priv->mkey.key);
 998         c->num_tc   = priv->params.num_tc;
 999
1000         mlx5e_build_channeltc_to_txq_map(priv, ix);
1001
1002         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1003
1004         err = mlx5e_open_tx_cqs(c, cparam);
1005         if (err)
1006                 goto err_napi_del;
1007
1008         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1009                             priv->params.rx_cq_moderation_usec,
1010                             priv->params.rx_cq_moderation_pkts);
1011         if (err)
1012                 goto err_close_tx_cqs;
1013
1014         napi_enable(&c->napi);
1015
1016         err = mlx5e_open_sqs(c, cparam);
1017         if (err)
1018                 goto err_disable_napi;
1019
1020         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1021         if (err)
1022                 goto err_close_sqs;
1023
1024         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1025         *cp = c;
1026
1027         return 0;
1028
1029 err_close_sqs:
1030         mlx5e_close_sqs(c);
1031
1032 err_disable_napi:
1033         napi_disable(&c->napi);
1034         mlx5e_close_cq(&c->rq.cq);
1035
1036 err_close_tx_cqs:
1037         mlx5e_close_tx_cqs(c);
1038
1039 err_napi_del:
1040         netif_napi_del(&c->napi);
1041         napi_hash_del(&c->napi);
1042         kfree(c);
1043
1044         return err;
1045 }
1046
1047 static void mlx5e_close_channel(struct mlx5e_channel *c)
1048 {
1049         mlx5e_close_rq(&c->rq);
1050         mlx5e_close_sqs(c);
1051         napi_disable(&c->napi);
1052         mlx5e_close_cq(&c->rq.cq);
1053         mlx5e_close_tx_cqs(c);
1054         netif_napi_del(&c->napi);
1055
1056         napi_hash_del(&c->napi);
1057         synchronize_rcu();
1058
1059         kfree(c);
1060 }
1061
1062 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1063                                  struct mlx5e_rq_param *param)
1064 {
1065         void *rqc = param->rqc;
1066         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1067
1068         MLX5_SET(wq, wq, wq_type,          MLX5_WQ_TYPE_LINKED_LIST);
1069         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1070         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1071         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1072         MLX5_SET(wq, wq, pd,               priv->pdn);
1073         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1074
1075         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1076         param->wq.linear = 1;
1077 }
1078
1079 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1080 {
1081         void *rqc = param->rqc;
1082         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1083
1084         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1085         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1086 }
1087
1088 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1089                                  struct mlx5e_sq_param *param)
1090 {
1091         void *sqc = param->sqc;
1092         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1093
1094         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1095         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1096         MLX5_SET(wq, wq, pd,            priv->pdn);
1097
1098         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1099         param->max_inline = priv->params.tx_max_inline;
1100 }
1101
1102 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1103                                         struct mlx5e_cq_param *param)
1104 {
1105         void *cqc = param->cqc;
1106
1107         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1108 }
1109
1110 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1111                                     struct mlx5e_cq_param *param)
1112 {
1113         void *cqc = param->cqc;
1114
1115         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_rq_size);
1116
1117         mlx5e_build_common_cq_param(priv, param);
1118 }
1119
1120 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1121                                     struct mlx5e_cq_param *param)
1122 {
1123         void *cqc = param->cqc;
1124
1125         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_sq_size);
1126
1127         mlx5e_build_common_cq_param(priv, param);
1128 }
1129
1130 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1131                                       struct mlx5e_channel_param *cparam)
1132 {
1133         memset(cparam, 0, sizeof(*cparam));
1134
1135         mlx5e_build_rq_param(priv, &cparam->rq);
1136         mlx5e_build_sq_param(priv, &cparam->sq);
1137         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1138         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1139 }
1140
1141 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1142 {
1143         struct mlx5e_channel_param cparam;
1144         int nch = priv->params.num_channels;
1145         int err = -ENOMEM;
1146         int i;
1147         int j;
1148
1149         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1150                                 GFP_KERNEL);
1151
1152         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1153                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1154
1155         if (!priv->channel || !priv->txq_to_sq_map)
1156                 goto err_free_txq_to_sq_map;
1157
1158         mlx5e_build_channel_param(priv, &cparam);
1159         for (i = 0; i < nch; i++) {
1160                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1161                 if (err)
1162                         goto err_close_channels;
1163         }
1164
1165         for (j = 0; j < nch; j++) {
1166                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1167                 if (err)
1168                         goto err_close_channels;
1169         }
1170
1171         return 0;
1172
1173 err_close_channels:
1174         for (i--; i >= 0; i--)
1175                 mlx5e_close_channel(priv->channel[i]);
1176
1177 err_free_txq_to_sq_map:
1178         kfree(priv->txq_to_sq_map);
1179         kfree(priv->channel);
1180
1181         return err;
1182 }
1183
1184 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1185 {
1186         int i;
1187
1188         for (i = 0; i < priv->params.num_channels; i++)
1189                 mlx5e_close_channel(priv->channel[i]);
1190
1191         kfree(priv->txq_to_sq_map);
1192         kfree(priv->channel);
1193 }
1194
1195 static int mlx5e_rx_hash_fn(int hfunc)
1196 {
1197         return (hfunc == ETH_RSS_HASH_TOP) ?
1198                MLX5_RX_HASH_FN_TOEPLITZ :
1199                MLX5_RX_HASH_FN_INVERTED_XOR8;
1200 }
1201
1202 static int mlx5e_bits_invert(unsigned long a, int size)
1203 {
1204         int inv = 0;
1205         int i;
1206
1207         for (i = 0; i < size; i++)
1208                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1209
1210         return inv;
1211 }
1212
1213 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1214 {
1215         int i;
1216
1217         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1218                 int ix = i;
1219
1220                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1221                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1222
1223                 ix = priv->params.indirection_rqt[ix];
1224                 MLX5_SET(rqtc, rqtc, rq_num[i],
1225                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1226                          priv->channel[ix]->rq.rqn :
1227                          priv->drop_rq.rqn);
1228         }
1229 }
1230
1231 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1232                                 enum mlx5e_rqt_ix rqt_ix)
1233 {
1234
1235         switch (rqt_ix) {
1236         case MLX5E_INDIRECTION_RQT:
1237                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1238
1239                 break;
1240
1241         default: /* MLX5E_SINGLE_RQ_RQT */
1242                 MLX5_SET(rqtc, rqtc, rq_num[0],
1243                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1244                          priv->channel[0]->rq.rqn :
1245                          priv->drop_rq.rqn);
1246
1247                 break;
1248         }
1249 }
1250
1251 static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1252 {
1253         struct mlx5_core_dev *mdev = priv->mdev;
1254         u32 *in;
1255         void *rqtc;
1256         int inlen;
1257         int sz;
1258         int err;
1259
1260         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1261
1262         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1263         in = mlx5_vzalloc(inlen);
1264         if (!in)
1265                 return -ENOMEM;
1266
1267         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1268
1269         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1270         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1271
1272         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1273
1274         err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
1275
1276         kvfree(in);
1277
1278         return err;
1279 }
1280
1281 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1282 {
1283         struct mlx5_core_dev *mdev = priv->mdev;
1284         u32 *in;
1285         void *rqtc;
1286         int inlen;
1287         int sz;
1288         int err;
1289
1290         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1291
1292         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1293         in = mlx5_vzalloc(inlen);
1294         if (!in)
1295                 return -ENOMEM;
1296
1297         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1298
1299         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1300
1301         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1302
1303         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1304
1305         err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1306
1307         kvfree(in);
1308
1309         return err;
1310 }
1311
1312 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1313 {
1314         mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
1315 }
1316
1317 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1318 {
1319         mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1320         mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1321 }
1322
1323 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1324 {
1325         if (!priv->params.lro_en)
1326                 return;
1327
1328 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1329
1330         MLX5_SET(tirc, tirc, lro_enable_mask,
1331                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1332                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1333         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1334                  (priv->params.lro_wqe_sz -
1335                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1336         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1337                  MLX5_CAP_ETH(priv->mdev,
1338                               lro_timer_supported_periods[2]));
1339 }
1340
1341 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1342 {
1343         MLX5_SET(tirc, tirc, rx_hash_fn,
1344                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1345         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1346                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1347                                              rx_hash_toeplitz_key);
1348                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1349                                                rx_hash_toeplitz_key);
1350
1351                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1352                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1353         }
1354 }
1355
1356 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1357 {
1358         struct mlx5_core_dev *mdev = priv->mdev;
1359
1360         void *in;
1361         void *tirc;
1362         int inlen;
1363         int err;
1364         int tt;
1365
1366         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1367         in = mlx5_vzalloc(inlen);
1368         if (!in)
1369                 return -ENOMEM;
1370
1371         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1372         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1373
1374         mlx5e_build_tir_ctx_lro(tirc, priv);
1375
1376         for (tt = 0; tt < MLX5E_NUM_TT; tt++) {
1377                 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1378                 if (err)
1379                         break;
1380         }
1381
1382         kvfree(in);
1383
1384         return err;
1385 }
1386
1387 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1388                                                   u32 tirn)
1389 {
1390         void *in;
1391         int inlen;
1392         int err;
1393
1394         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1395         in = mlx5_vzalloc(inlen);
1396         if (!in)
1397                 return -ENOMEM;
1398
1399         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1400
1401         err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1402
1403         kvfree(in);
1404
1405         return err;
1406 }
1407
1408 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1409 {
1410         int err;
1411         int i;
1412
1413         for (i = 0; i < MLX5E_NUM_TT; i++) {
1414                 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1415                                                              priv->tirn[i]);
1416                 if (err)
1417                         return err;
1418         }
1419
1420         return 0;
1421 }
1422
1423 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1424 {
1425         struct mlx5e_priv *priv = netdev_priv(netdev);
1426         struct mlx5_core_dev *mdev = priv->mdev;
1427         int hw_mtu;
1428         int err;
1429
1430         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1431         if (err)
1432                 return err;
1433
1434         mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1435
1436         if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1437                 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1438                             __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1439
1440         netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1441         return 0;
1442 }
1443
1444 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1445 {
1446         struct mlx5e_priv *priv = netdev_priv(netdev);
1447         int nch = priv->params.num_channels;
1448         int ntc = priv->params.num_tc;
1449         int tc;
1450
1451         netdev_reset_tc(netdev);
1452
1453         if (ntc == 1)
1454                 return;
1455
1456         netdev_set_num_tc(netdev, ntc);
1457
1458         for (tc = 0; tc < ntc; tc++)
1459                 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1460 }
1461
1462 int mlx5e_open_locked(struct net_device *netdev)
1463 {
1464         struct mlx5e_priv *priv = netdev_priv(netdev);
1465         int num_txqs;
1466         int err;
1467
1468         set_bit(MLX5E_STATE_OPENED, &priv->state);
1469
1470         mlx5e_netdev_set_tcs(netdev);
1471
1472         num_txqs = priv->params.num_channels * priv->params.num_tc;
1473         netif_set_real_num_tx_queues(netdev, num_txqs);
1474         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1475
1476         err = mlx5e_set_dev_port_mtu(netdev);
1477         if (err)
1478                 goto err_clear_state_opened_flag;
1479
1480         err = mlx5e_open_channels(priv);
1481         if (err) {
1482                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1483                            __func__, err);
1484                 goto err_clear_state_opened_flag;
1485         }
1486
1487         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1488         if (err) {
1489                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1490                            __func__, err);
1491                 goto err_close_channels;
1492         }
1493
1494         mlx5e_redirect_rqts(priv);
1495         mlx5e_update_carrier(priv);
1496         mlx5e_timestamp_init(priv);
1497
1498         schedule_delayed_work(&priv->update_stats_work, 0);
1499
1500         return 0;
1501
1502 err_close_channels:
1503         mlx5e_close_channels(priv);
1504 err_clear_state_opened_flag:
1505         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1506         return err;
1507 }
1508
1509 static int mlx5e_open(struct net_device *netdev)
1510 {
1511         struct mlx5e_priv *priv = netdev_priv(netdev);
1512         int err;
1513
1514         mutex_lock(&priv->state_lock);
1515         err = mlx5e_open_locked(netdev);
1516         mutex_unlock(&priv->state_lock);
1517
1518         return err;
1519 }
1520
1521 int mlx5e_close_locked(struct net_device *netdev)
1522 {
1523         struct mlx5e_priv *priv = netdev_priv(netdev);
1524
1525         /* May already be CLOSED in case a previous configuration operation
1526          * (e.g RX/TX queue size change) that involves close&open failed.
1527          */
1528         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1529                 return 0;
1530
1531         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1532
1533         mlx5e_timestamp_cleanup(priv);
1534         netif_carrier_off(priv->netdev);
1535         mlx5e_redirect_rqts(priv);
1536         mlx5e_close_channels(priv);
1537
1538         return 0;
1539 }
1540
1541 static int mlx5e_close(struct net_device *netdev)
1542 {
1543         struct mlx5e_priv *priv = netdev_priv(netdev);
1544         int err;
1545
1546         mutex_lock(&priv->state_lock);
1547         err = mlx5e_close_locked(netdev);
1548         mutex_unlock(&priv->state_lock);
1549
1550         return err;
1551 }
1552
1553 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1554                                 struct mlx5e_rq *rq,
1555                                 struct mlx5e_rq_param *param)
1556 {
1557         struct mlx5_core_dev *mdev = priv->mdev;
1558         void *rqc = param->rqc;
1559         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1560         int err;
1561
1562         param->wq.db_numa_node = param->wq.buf_numa_node;
1563
1564         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1565                                 &rq->wq_ctrl);
1566         if (err)
1567                 return err;
1568
1569         rq->priv = priv;
1570
1571         return 0;
1572 }
1573
1574 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1575                                 struct mlx5e_cq *cq,
1576                                 struct mlx5e_cq_param *param)
1577 {
1578         struct mlx5_core_dev *mdev = priv->mdev;
1579         struct mlx5_core_cq *mcq = &cq->mcq;
1580         int eqn_not_used;
1581         unsigned int irqn;
1582         int err;
1583
1584         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1585                                &cq->wq_ctrl);
1586         if (err)
1587                 return err;
1588
1589         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1590
1591         mcq->cqe_sz     = 64;
1592         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1593         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1594         *mcq->set_ci_db = 0;
1595         *mcq->arm_db    = 0;
1596         mcq->vector     = param->eq_ix;
1597         mcq->comp       = mlx5e_completion_event;
1598         mcq->event      = mlx5e_cq_error_event;
1599         mcq->irqn       = irqn;
1600         mcq->uar        = &priv->cq_uar;
1601
1602         cq->priv = priv;
1603
1604         return 0;
1605 }
1606
1607 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1608 {
1609         struct mlx5e_cq_param cq_param;
1610         struct mlx5e_rq_param rq_param;
1611         struct mlx5e_rq *rq = &priv->drop_rq;
1612         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1613         int err;
1614
1615         memset(&cq_param, 0, sizeof(cq_param));
1616         memset(&rq_param, 0, sizeof(rq_param));
1617         mlx5e_build_drop_rq_param(&rq_param);
1618
1619         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1620         if (err)
1621                 return err;
1622
1623         err = mlx5e_enable_cq(cq, &cq_param);
1624         if (err)
1625                 goto err_destroy_cq;
1626
1627         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1628         if (err)
1629                 goto err_disable_cq;
1630
1631         err = mlx5e_enable_rq(rq, &rq_param);
1632         if (err)
1633                 goto err_destroy_rq;
1634
1635         return 0;
1636
1637 err_destroy_rq:
1638         mlx5e_destroy_rq(&priv->drop_rq);
1639
1640 err_disable_cq:
1641         mlx5e_disable_cq(&priv->drop_rq.cq);
1642
1643 err_destroy_cq:
1644         mlx5e_destroy_cq(&priv->drop_rq.cq);
1645
1646         return err;
1647 }
1648
1649 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1650 {
1651         mlx5e_disable_rq(&priv->drop_rq);
1652         mlx5e_destroy_rq(&priv->drop_rq);
1653         mlx5e_disable_cq(&priv->drop_rq.cq);
1654         mlx5e_destroy_cq(&priv->drop_rq.cq);
1655 }
1656
1657 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1658 {
1659         struct mlx5_core_dev *mdev = priv->mdev;
1660         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1661         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1662
1663         memset(in, 0, sizeof(in));
1664
1665         MLX5_SET(tisc, tisc, prio, tc << 1);
1666         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1667
1668         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1669 }
1670
1671 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1672 {
1673         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1674 }
1675
1676 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1677 {
1678         int err;
1679         int tc;
1680
1681         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1682                 err = mlx5e_create_tis(priv, tc);
1683                 if (err)
1684                         goto err_close_tises;
1685         }
1686
1687         return 0;
1688
1689 err_close_tises:
1690         for (tc--; tc >= 0; tc--)
1691                 mlx5e_destroy_tis(priv, tc);
1692
1693         return err;
1694 }
1695
1696 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1697 {
1698         int tc;
1699
1700         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1701                 mlx5e_destroy_tis(priv, tc);
1702 }
1703
1704 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1705 {
1706         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1707
1708         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1709
1710 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1711                                  MLX5_HASH_FIELD_SEL_DST_IP)
1712
1713 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1714                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1715                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1716                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1717
1718 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1719                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1720                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1721
1722         mlx5e_build_tir_ctx_lro(tirc, priv);
1723
1724         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1725
1726         switch (tt) {
1727         case MLX5E_TT_ANY:
1728                 MLX5_SET(tirc, tirc, indirect_table,
1729                          priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1730                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
1731                 break;
1732         default:
1733                 MLX5_SET(tirc, tirc, indirect_table,
1734                          priv->rqtn[MLX5E_INDIRECTION_RQT]);
1735                 mlx5e_build_tir_ctx_hash(tirc, priv);
1736                 break;
1737         }
1738
1739         switch (tt) {
1740         case MLX5E_TT_IPV4_TCP:
1741                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1742                          MLX5_L3_PROT_TYPE_IPV4);
1743                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1744                          MLX5_L4_PROT_TYPE_TCP);
1745                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1746                          MLX5_HASH_IP_L4PORTS);
1747                 break;
1748
1749         case MLX5E_TT_IPV6_TCP:
1750                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1751                          MLX5_L3_PROT_TYPE_IPV6);
1752                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1753                          MLX5_L4_PROT_TYPE_TCP);
1754                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1755                          MLX5_HASH_IP_L4PORTS);
1756                 break;
1757
1758         case MLX5E_TT_IPV4_UDP:
1759                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1760                          MLX5_L3_PROT_TYPE_IPV4);
1761                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1762                          MLX5_L4_PROT_TYPE_UDP);
1763                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1764                          MLX5_HASH_IP_L4PORTS);
1765                 break;
1766
1767         case MLX5E_TT_IPV6_UDP:
1768                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1769                          MLX5_L3_PROT_TYPE_IPV6);
1770                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1771                          MLX5_L4_PROT_TYPE_UDP);
1772                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1773                          MLX5_HASH_IP_L4PORTS);
1774                 break;
1775
1776         case MLX5E_TT_IPV4_IPSEC_AH:
1777                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1778                          MLX5_L3_PROT_TYPE_IPV4);
1779                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1780                          MLX5_HASH_IP_IPSEC_SPI);
1781                 break;
1782
1783         case MLX5E_TT_IPV6_IPSEC_AH:
1784                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1785                          MLX5_L3_PROT_TYPE_IPV6);
1786                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1787                          MLX5_HASH_IP_IPSEC_SPI);
1788                 break;
1789
1790         case MLX5E_TT_IPV4_IPSEC_ESP:
1791                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1792                          MLX5_L3_PROT_TYPE_IPV4);
1793                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1794                          MLX5_HASH_IP_IPSEC_SPI);
1795                 break;
1796
1797         case MLX5E_TT_IPV6_IPSEC_ESP:
1798                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1799                          MLX5_L3_PROT_TYPE_IPV6);
1800                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1801                          MLX5_HASH_IP_IPSEC_SPI);
1802                 break;
1803
1804         case MLX5E_TT_IPV4:
1805                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1806                          MLX5_L3_PROT_TYPE_IPV4);
1807                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1808                          MLX5_HASH_IP);
1809                 break;
1810
1811         case MLX5E_TT_IPV6:
1812                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1813                          MLX5_L3_PROT_TYPE_IPV6);
1814                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1815                          MLX5_HASH_IP);
1816                 break;
1817         }
1818 }
1819
1820 static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
1821 {
1822         struct mlx5_core_dev *mdev = priv->mdev;
1823         u32 *in;
1824         void *tirc;
1825         int inlen;
1826         int err;
1827
1828         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1829         in = mlx5_vzalloc(inlen);
1830         if (!in)
1831                 return -ENOMEM;
1832
1833         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1834
1835         mlx5e_build_tir_ctx(priv, tirc, tt);
1836
1837         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1838
1839         kvfree(in);
1840
1841         return err;
1842 }
1843
1844 static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
1845 {
1846         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1847 }
1848
1849 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
1850 {
1851         int err;
1852         int i;
1853
1854         for (i = 0; i < MLX5E_NUM_TT; i++) {
1855                 err = mlx5e_create_tir(priv, i);
1856                 if (err)
1857                         goto err_destroy_tirs;
1858         }
1859
1860         return 0;
1861
1862 err_destroy_tirs:
1863         for (i--; i >= 0; i--)
1864                 mlx5e_destroy_tir(priv, i);
1865
1866         return err;
1867 }
1868
1869 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
1870 {
1871         int i;
1872
1873         for (i = 0; i < MLX5E_NUM_TT; i++)
1874                 mlx5e_destroy_tir(priv, i);
1875 }
1876
1877 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
1878 {
1879         struct mlx5e_priv *priv = netdev_priv(netdev);
1880         bool was_opened;
1881         int err = 0;
1882
1883         if (tc && tc != MLX5E_MAX_NUM_TC)
1884                 return -EINVAL;
1885
1886         mutex_lock(&priv->state_lock);
1887
1888         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1889         if (was_opened)
1890                 mlx5e_close_locked(priv->netdev);
1891
1892         priv->params.num_tc = tc ? tc : 1;
1893
1894         if (was_opened)
1895                 err = mlx5e_open_locked(priv->netdev);
1896
1897         mutex_unlock(&priv->state_lock);
1898
1899         return err;
1900 }
1901
1902 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
1903                               __be16 proto, struct tc_to_netdev *tc)
1904 {
1905         struct mlx5e_priv *priv = netdev_priv(dev);
1906
1907         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
1908                 goto mqprio;
1909
1910         switch (tc->type) {
1911         case TC_SETUP_CLSFLOWER:
1912                 switch (tc->cls_flower->command) {
1913                 case TC_CLSFLOWER_REPLACE:
1914                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
1915                 case TC_CLSFLOWER_DESTROY:
1916                         return mlx5e_delete_flower(priv, tc->cls_flower);
1917                 }
1918         default:
1919                 return -EOPNOTSUPP;
1920         }
1921
1922 mqprio:
1923         if (tc->type != TC_SETUP_MQPRIO)
1924                 return -EINVAL;
1925
1926         return mlx5e_setup_tc(dev, tc->tc);
1927 }
1928
1929 static struct rtnl_link_stats64 *
1930 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1931 {
1932         struct mlx5e_priv *priv = netdev_priv(dev);
1933         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1934
1935         stats->rx_packets = vstats->rx_packets;
1936         stats->rx_bytes   = vstats->rx_bytes;
1937         stats->tx_packets = vstats->tx_packets;
1938         stats->tx_bytes   = vstats->tx_bytes;
1939         stats->multicast  = vstats->rx_multicast_packets +
1940                             vstats->tx_multicast_packets;
1941         stats->tx_errors  = vstats->tx_error_packets;
1942         stats->rx_errors  = vstats->rx_error_packets;
1943         stats->tx_dropped = vstats->tx_queue_dropped;
1944         stats->rx_crc_errors = 0;
1945         stats->rx_length_errors = 0;
1946
1947         return stats;
1948 }
1949
1950 static void mlx5e_set_rx_mode(struct net_device *dev)
1951 {
1952         struct mlx5e_priv *priv = netdev_priv(dev);
1953
1954         schedule_work(&priv->set_rx_mode_work);
1955 }
1956
1957 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1958 {
1959         struct mlx5e_priv *priv = netdev_priv(netdev);
1960         struct sockaddr *saddr = addr;
1961
1962         if (!is_valid_ether_addr(saddr->sa_data))
1963                 return -EADDRNOTAVAIL;
1964
1965         netif_addr_lock_bh(netdev);
1966         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1967         netif_addr_unlock_bh(netdev);
1968
1969         schedule_work(&priv->set_rx_mode_work);
1970
1971         return 0;
1972 }
1973
1974 static int mlx5e_set_features(struct net_device *netdev,
1975                               netdev_features_t features)
1976 {
1977         struct mlx5e_priv *priv = netdev_priv(netdev);
1978         int err = 0;
1979         netdev_features_t changes = features ^ netdev->features;
1980
1981         mutex_lock(&priv->state_lock);
1982
1983         if (changes & NETIF_F_LRO) {
1984                 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1985
1986                 if (was_opened)
1987                         mlx5e_close_locked(priv->netdev);
1988
1989                 priv->params.lro_en = !!(features & NETIF_F_LRO);
1990                 err = mlx5e_modify_tirs_lro(priv);
1991                 if (err)
1992                         mlx5_core_warn(priv->mdev, "lro modify failed, %d\n",
1993                                        err);
1994
1995                 if (was_opened)
1996                         err = mlx5e_open_locked(priv->netdev);
1997         }
1998
1999         mutex_unlock(&priv->state_lock);
2000
2001         if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
2002                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
2003                         mlx5e_enable_vlan_filter(priv);
2004                 else
2005                         mlx5e_disable_vlan_filter(priv);
2006         }
2007
2008         if ((changes & NETIF_F_HW_TC) && !(features & NETIF_F_HW_TC) &&
2009             mlx5e_tc_num_filters(priv)) {
2010                 netdev_err(netdev,
2011                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2012                 return -EINVAL;
2013         }
2014
2015         return err;
2016 }
2017
2018 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2019 {
2020         struct mlx5e_priv *priv = netdev_priv(netdev);
2021         struct mlx5_core_dev *mdev = priv->mdev;
2022         bool was_opened;
2023         int max_mtu;
2024         int err = 0;
2025
2026         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2027
2028         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2029
2030         if (new_mtu > max_mtu) {
2031                 netdev_err(netdev,
2032                            "%s: Bad MTU (%d) > (%d) Max\n",
2033                            __func__, new_mtu, max_mtu);
2034                 return -EINVAL;
2035         }
2036
2037         mutex_lock(&priv->state_lock);
2038
2039         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2040         if (was_opened)
2041                 mlx5e_close_locked(netdev);
2042
2043         netdev->mtu = new_mtu;
2044
2045         if (was_opened)
2046                 err = mlx5e_open_locked(netdev);
2047
2048         mutex_unlock(&priv->state_lock);
2049
2050         return err;
2051 }
2052
2053 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2054 {
2055         switch (cmd) {
2056         case SIOCSHWTSTAMP:
2057                 return mlx5e_hwstamp_set(dev, ifr);
2058         case SIOCGHWTSTAMP:
2059                 return mlx5e_hwstamp_get(dev, ifr);
2060         default:
2061                 return -EOPNOTSUPP;
2062         }
2063 }
2064
2065 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2066 {
2067         struct mlx5e_priv *priv = netdev_priv(dev);
2068         struct mlx5_core_dev *mdev = priv->mdev;
2069
2070         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2071 }
2072
2073 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2074 {
2075         struct mlx5e_priv *priv = netdev_priv(dev);
2076         struct mlx5_core_dev *mdev = priv->mdev;
2077
2078         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2079                                            vlan, qos);
2080 }
2081
2082 static int mlx5_vport_link2ifla(u8 esw_link)
2083 {
2084         switch (esw_link) {
2085         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2086                 return IFLA_VF_LINK_STATE_DISABLE;
2087         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2088                 return IFLA_VF_LINK_STATE_ENABLE;
2089         }
2090         return IFLA_VF_LINK_STATE_AUTO;
2091 }
2092
2093 static int mlx5_ifla_link2vport(u8 ifla_link)
2094 {
2095         switch (ifla_link) {
2096         case IFLA_VF_LINK_STATE_DISABLE:
2097                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2098         case IFLA_VF_LINK_STATE_ENABLE:
2099                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2100         }
2101         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2102 }
2103
2104 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2105                                    int link_state)
2106 {
2107         struct mlx5e_priv *priv = netdev_priv(dev);
2108         struct mlx5_core_dev *mdev = priv->mdev;
2109
2110         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2111                                             mlx5_ifla_link2vport(link_state));
2112 }
2113
2114 static int mlx5e_get_vf_config(struct net_device *dev,
2115                                int vf, struct ifla_vf_info *ivi)
2116 {
2117         struct mlx5e_priv *priv = netdev_priv(dev);
2118         struct mlx5_core_dev *mdev = priv->mdev;
2119         int err;
2120
2121         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2122         if (err)
2123                 return err;
2124         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2125         return 0;
2126 }
2127
2128 static int mlx5e_get_vf_stats(struct net_device *dev,
2129                               int vf, struct ifla_vf_stats *vf_stats)
2130 {
2131         struct mlx5e_priv *priv = netdev_priv(dev);
2132         struct mlx5_core_dev *mdev = priv->mdev;
2133
2134         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2135                                             vf_stats);
2136 }
2137
2138 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2139                                  sa_family_t sa_family, __be16 port)
2140 {
2141         struct mlx5e_priv *priv = netdev_priv(netdev);
2142
2143         if (!mlx5e_vxlan_allowed(priv->mdev))
2144                 return;
2145
2146         mlx5e_vxlan_add_port(priv, be16_to_cpu(port));
2147 }
2148
2149 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2150                                  sa_family_t sa_family, __be16 port)
2151 {
2152         struct mlx5e_priv *priv = netdev_priv(netdev);
2153
2154         if (!mlx5e_vxlan_allowed(priv->mdev))
2155                 return;
2156
2157         mlx5e_vxlan_del_port(priv, be16_to_cpu(port));
2158 }
2159
2160 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2161                                                     struct sk_buff *skb,
2162                                                     netdev_features_t features)
2163 {
2164         struct udphdr *udph;
2165         u16 proto;
2166         u16 port = 0;
2167
2168         switch (vlan_get_protocol(skb)) {
2169         case htons(ETH_P_IP):
2170                 proto = ip_hdr(skb)->protocol;
2171                 break;
2172         case htons(ETH_P_IPV6):
2173                 proto = ipv6_hdr(skb)->nexthdr;
2174                 break;
2175         default:
2176                 goto out;
2177         }
2178
2179         if (proto == IPPROTO_UDP) {
2180                 udph = udp_hdr(skb);
2181                 port = be16_to_cpu(udph->dest);
2182         }
2183
2184         /* Verify if UDP port is being offloaded by HW */
2185         if (port && mlx5e_vxlan_lookup_port(priv, port))
2186                 return features;
2187
2188 out:
2189         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2190         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2191 }
2192
2193 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2194                                               struct net_device *netdev,
2195                                               netdev_features_t features)
2196 {
2197         struct mlx5e_priv *priv = netdev_priv(netdev);
2198
2199         features = vlan_features_check(skb, features);
2200         features = vxlan_features_check(skb, features);
2201
2202         /* Validate if the tunneled packet is being offloaded by HW */
2203         if (skb->encapsulation &&
2204             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2205                 return mlx5e_vxlan_features_check(priv, skb, features);
2206
2207         return features;
2208 }
2209
2210 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2211         .ndo_open                = mlx5e_open,
2212         .ndo_stop                = mlx5e_close,
2213         .ndo_start_xmit          = mlx5e_xmit,
2214         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2215         .ndo_select_queue        = mlx5e_select_queue,
2216         .ndo_get_stats64         = mlx5e_get_stats,
2217         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2218         .ndo_set_mac_address     = mlx5e_set_mac,
2219         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2220         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2221         .ndo_set_features        = mlx5e_set_features,
2222         .ndo_change_mtu          = mlx5e_change_mtu,
2223         .ndo_do_ioctl            = mlx5e_ioctl,
2224 };
2225
2226 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2227         .ndo_open                = mlx5e_open,
2228         .ndo_stop                = mlx5e_close,
2229         .ndo_start_xmit          = mlx5e_xmit,
2230         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2231         .ndo_select_queue        = mlx5e_select_queue,
2232         .ndo_get_stats64         = mlx5e_get_stats,
2233         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2234         .ndo_set_mac_address     = mlx5e_set_mac,
2235         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2236         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2237         .ndo_set_features        = mlx5e_set_features,
2238         .ndo_change_mtu          = mlx5e_change_mtu,
2239         .ndo_do_ioctl            = mlx5e_ioctl,
2240         .ndo_add_vxlan_port      = mlx5e_add_vxlan_port,
2241         .ndo_del_vxlan_port      = mlx5e_del_vxlan_port,
2242         .ndo_features_check      = mlx5e_features_check,
2243         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2244         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2245         .ndo_get_vf_config       = mlx5e_get_vf_config,
2246         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2247         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2248 };
2249
2250 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2251 {
2252         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2253                 return -ENOTSUPP;
2254         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2255             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2256             !MLX5_CAP_ETH(mdev, csum_cap) ||
2257             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2258             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2259             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2260             MLX5_CAP_FLOWTABLE(mdev,
2261                                flow_table_properties_nic_receive.max_ft_level)
2262                                < 3) {
2263                 mlx5_core_warn(mdev,
2264                                "Not creating net device, some required device capabilities are missing\n");
2265                 return -ENOTSUPP;
2266         }
2267         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2268                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2269         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2270                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2271
2272         return 0;
2273 }
2274
2275 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2276 {
2277         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2278
2279         return bf_buf_size -
2280                sizeof(struct mlx5e_tx_wqe) +
2281                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2282 }
2283
2284 #ifdef CONFIG_MLX5_CORE_EN_DCB
2285 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2286 {
2287         int i;
2288
2289         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2290         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2291                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2292                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2293                 priv->params.ets.prio_tc[i] = i;
2294         }
2295
2296         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2297         priv->params.ets.prio_tc[0] = 1;
2298         priv->params.ets.prio_tc[1] = 0;
2299 }
2300 #endif
2301
2302 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2303                                    u32 *indirection_rqt, int len,
2304                                    int num_channels)
2305 {
2306         int node = mdev->priv.numa_node;
2307         int node_num_of_cores;
2308         int i;
2309
2310         if (node == -1)
2311                 node = first_online_node;
2312
2313         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2314
2315         if (node_num_of_cores)
2316                 num_channels = min_t(int, num_channels, node_num_of_cores);
2317
2318         for (i = 0; i < len; i++)
2319                 indirection_rqt[i] = i % num_channels;
2320 }
2321
2322 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2323                                     struct net_device *netdev,
2324                                     int num_channels)
2325 {
2326         struct mlx5e_priv *priv = netdev_priv(netdev);
2327
2328         priv->params.log_sq_size           =
2329                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2330         priv->params.log_rq_size           =
2331                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2332         priv->params.rx_cq_moderation_usec =
2333                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2334         priv->params.rx_cq_moderation_pkts =
2335                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2336         priv->params.tx_cq_moderation_usec =
2337                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2338         priv->params.tx_cq_moderation_pkts =
2339                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2340         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
2341         priv->params.min_rx_wqes           =
2342                 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2343         priv->params.num_tc                = 1;
2344         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2345
2346         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2347                             sizeof(priv->params.toeplitz_hash_key));
2348
2349         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2350                                       MLX5E_INDIR_RQT_SIZE, num_channels);
2351
2352         priv->params.lro_wqe_sz            =
2353                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2354
2355         priv->mdev                         = mdev;
2356         priv->netdev                       = netdev;
2357         priv->params.num_channels          = num_channels;
2358
2359 #ifdef CONFIG_MLX5_CORE_EN_DCB
2360         mlx5e_ets_init(priv);
2361 #endif
2362
2363         mutex_init(&priv->state_lock);
2364
2365         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2366         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2367         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2368 }
2369
2370 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2371 {
2372         struct mlx5e_priv *priv = netdev_priv(netdev);
2373
2374         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2375         if (is_zero_ether_addr(netdev->dev_addr) &&
2376             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2377                 eth_hw_addr_random(netdev);
2378                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2379         }
2380 }
2381
2382 static void mlx5e_build_netdev(struct net_device *netdev)
2383 {
2384         struct mlx5e_priv *priv = netdev_priv(netdev);
2385         struct mlx5_core_dev *mdev = priv->mdev;
2386
2387         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2388
2389         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2390                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2391 #ifdef CONFIG_MLX5_CORE_EN_DCB
2392                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2393 #endif
2394         } else {
2395                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2396         }
2397
2398         netdev->watchdog_timeo    = 15 * HZ;
2399
2400         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
2401
2402         netdev->vlan_features    |= NETIF_F_SG;
2403         netdev->vlan_features    |= NETIF_F_IP_CSUM;
2404         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
2405         netdev->vlan_features    |= NETIF_F_GRO;
2406         netdev->vlan_features    |= NETIF_F_TSO;
2407         netdev->vlan_features    |= NETIF_F_TSO6;
2408         netdev->vlan_features    |= NETIF_F_RXCSUM;
2409         netdev->vlan_features    |= NETIF_F_RXHASH;
2410
2411         if (!!MLX5_CAP_ETH(mdev, lro_cap))
2412                 netdev->vlan_features    |= NETIF_F_LRO;
2413
2414         netdev->hw_features       = netdev->vlan_features;
2415         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
2416         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
2417         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
2418
2419         if (mlx5e_vxlan_allowed(mdev)) {
2420                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL;
2421                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2422                 netdev->hw_enc_features |= NETIF_F_RXCSUM;
2423                 netdev->hw_enc_features |= NETIF_F_TSO;
2424                 netdev->hw_enc_features |= NETIF_F_TSO6;
2425                 netdev->hw_enc_features |= NETIF_F_RXHASH;
2426                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2427         }
2428
2429         netdev->features          = netdev->hw_features;
2430         if (!priv->params.lro_en)
2431                 netdev->features  &= ~NETIF_F_LRO;
2432
2433 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2434         if (FT_CAP(flow_modify_en) &&
2435             FT_CAP(modify_root) &&
2436             FT_CAP(identified_miss_table_mode) &&
2437             FT_CAP(flow_table_modify))
2438                 priv->netdev->hw_features      |= NETIF_F_HW_TC;
2439
2440         netdev->features         |= NETIF_F_HIGHDMA;
2441
2442         netdev->priv_flags       |= IFF_UNICAST_FLT;
2443
2444         mlx5e_set_netdev_dev_addr(netdev);
2445 }
2446
2447 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2448                              struct mlx5_core_mkey *mkey)
2449 {
2450         struct mlx5_core_dev *mdev = priv->mdev;
2451         struct mlx5_create_mkey_mbox_in *in;
2452         int err;
2453
2454         in = mlx5_vzalloc(sizeof(*in));
2455         if (!in)
2456                 return -ENOMEM;
2457
2458         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2459                         MLX5_PERM_LOCAL_READ  |
2460                         MLX5_ACCESS_MODE_PA;
2461         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2462         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2463
2464         err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
2465                                     NULL);
2466
2467         kvfree(in);
2468
2469         return err;
2470 }
2471
2472 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2473 {
2474         struct mlx5_core_dev *mdev = priv->mdev;
2475         int err;
2476
2477         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2478         if (err) {
2479                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2480                 priv->q_counter = 0;
2481         }
2482 }
2483
2484 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2485 {
2486         if (!priv->q_counter)
2487                 return;
2488
2489         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2490 }
2491
2492 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2493 {
2494         struct net_device *netdev;
2495         struct mlx5e_priv *priv;
2496         int nch = mlx5e_get_max_num_channels(mdev);
2497         int err;
2498
2499         if (mlx5e_check_required_hca_cap(mdev))
2500                 return NULL;
2501
2502         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2503                                     nch * MLX5E_MAX_NUM_TC,
2504                                     nch);
2505         if (!netdev) {
2506                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2507                 return NULL;
2508         }
2509
2510         mlx5e_build_netdev_priv(mdev, netdev, nch);
2511         mlx5e_build_netdev(netdev);
2512
2513         netif_carrier_off(netdev);
2514
2515         priv = netdev_priv(netdev);
2516
2517         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
2518         if (err) {
2519                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2520                 goto err_free_netdev;
2521         }
2522
2523         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2524         if (err) {
2525                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2526                 goto err_unmap_free_uar;
2527         }
2528
2529         err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
2530         if (err) {
2531                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2532                 goto err_dealloc_pd;
2533         }
2534
2535         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
2536         if (err) {
2537                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2538                 goto err_dealloc_transport_domain;
2539         }
2540
2541         err = mlx5e_create_tises(priv);
2542         if (err) {
2543                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2544                 goto err_destroy_mkey;
2545         }
2546
2547         err = mlx5e_open_drop_rq(priv);
2548         if (err) {
2549                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2550                 goto err_destroy_tises;
2551         }
2552
2553         err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
2554         if (err) {
2555                 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
2556                 goto err_close_drop_rq;
2557         }
2558
2559         err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2560         if (err) {
2561                 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2562                 goto err_destroy_rqt_indir;
2563         }
2564
2565         err = mlx5e_create_tirs(priv);
2566         if (err) {
2567                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2568                 goto err_destroy_rqt_single;
2569         }
2570
2571         err = mlx5e_create_flow_tables(priv);
2572         if (err) {
2573                 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2574                 goto err_destroy_tirs;
2575         }
2576
2577         mlx5e_create_q_counter(priv);
2578
2579         mlx5e_init_eth_addr(priv);
2580
2581         mlx5e_vxlan_init(priv);
2582
2583         err = mlx5e_tc_init(priv);
2584         if (err)
2585                 goto err_dealloc_q_counters;
2586
2587 #ifdef CONFIG_MLX5_CORE_EN_DCB
2588         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2589 #endif
2590
2591         err = register_netdev(netdev);
2592         if (err) {
2593                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2594                 goto err_tc_cleanup;
2595         }
2596
2597         if (mlx5e_vxlan_allowed(mdev))
2598                 vxlan_get_rx_port(netdev);
2599
2600         mlx5e_enable_async_events(priv);
2601         schedule_work(&priv->set_rx_mode_work);
2602
2603         return priv;
2604
2605 err_tc_cleanup:
2606         mlx5e_tc_cleanup(priv);
2607
2608 err_dealloc_q_counters:
2609         mlx5e_destroy_q_counter(priv);
2610         mlx5e_destroy_flow_tables(priv);
2611
2612 err_destroy_tirs:
2613         mlx5e_destroy_tirs(priv);
2614
2615 err_destroy_rqt_single:
2616         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2617
2618 err_destroy_rqt_indir:
2619         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2620
2621 err_close_drop_rq:
2622         mlx5e_close_drop_rq(priv);
2623
2624 err_destroy_tises:
2625         mlx5e_destroy_tises(priv);
2626
2627 err_destroy_mkey:
2628         mlx5_core_destroy_mkey(mdev, &priv->mkey);
2629
2630 err_dealloc_transport_domain:
2631         mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
2632
2633 err_dealloc_pd:
2634         mlx5_core_dealloc_pd(mdev, priv->pdn);
2635
2636 err_unmap_free_uar:
2637         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2638
2639 err_free_netdev:
2640         free_netdev(netdev);
2641
2642         return NULL;
2643 }
2644
2645 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2646 {
2647         struct mlx5e_priv *priv = vpriv;
2648         struct net_device *netdev = priv->netdev;
2649
2650         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2651
2652         schedule_work(&priv->set_rx_mode_work);
2653         mlx5e_disable_async_events(priv);
2654         flush_scheduled_work();
2655         unregister_netdev(netdev);
2656         mlx5e_tc_cleanup(priv);
2657         mlx5e_vxlan_cleanup(priv);
2658         mlx5e_destroy_q_counter(priv);
2659         mlx5e_destroy_flow_tables(priv);
2660         mlx5e_destroy_tirs(priv);
2661         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2662         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2663         mlx5e_close_drop_rq(priv);
2664         mlx5e_destroy_tises(priv);
2665         mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
2666         mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
2667         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2668         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2669         free_netdev(netdev);
2670 }
2671
2672 static void *mlx5e_get_netdev(void *vpriv)
2673 {
2674         struct mlx5e_priv *priv = vpriv;
2675
2676         return priv->netdev;
2677 }
2678
2679 static struct mlx5_interface mlx5e_interface = {
2680         .add       = mlx5e_create_netdev,
2681         .remove    = mlx5e_destroy_netdev,
2682         .event     = mlx5e_async_event,
2683         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
2684         .get_dev   = mlx5e_get_netdev,
2685 };
2686
2687 void mlx5e_init(void)
2688 {
2689         mlx5_register_interface(&mlx5e_interface);
2690 }
2691
2692 void mlx5e_cleanup(void)
2693 {
2694         mlx5_unregister_interface(&mlx5e_interface);
2695 }