drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 enum {
  43         MLX5_EN_QP_FLUSH_TIMEOUT_MS     = 5000,
  44         MLX5_EN_QP_FLUSH_MSLEEP_QUANT   = 20,
  45         MLX5_EN_QP_FLUSH_MAX_ITER       = MLX5_EN_QP_FLUSH_TIMEOUT_MS /
  46                                           MLX5_EN_QP_FLUSH_MSLEEP_QUANT,
  47 };
  48
  49 struct mlx5e_rq_param {
  50         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  51         struct mlx5_wq_param    wq;
  52         bool                    am_enabled;
  53 };
  54
  55 struct mlx5e_sq_param {
  56         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  57         struct mlx5_wq_param       wq;
  58         u16                        max_inline;
  59         u8                         min_inline_mode;
  60         bool                       icosq;
  61 };
  62
  63 struct mlx5e_cq_param {
  64         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  65         struct mlx5_wq_param       wq;
  66         u16                        eq_ix;
  67         u8                         cq_period_mode;
  68 };
  69
  70 struct mlx5e_channel_param {
  71         struct mlx5e_rq_param      rq;
  72         struct mlx5e_sq_param      sq;
  73         struct mlx5e_sq_param      icosq;
  74         struct mlx5e_cq_param      rx_cq;
  75         struct mlx5e_cq_param      tx_cq;
  76         struct mlx5e_cq_param      icosq_cq;
  77 };
  78
  79 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  80 {
  81         struct mlx5_core_dev *mdev = priv->mdev;
  82         u8 port_state;
  83
  84         port_state = mlx5_query_vport_state(mdev,
  85                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  86
  87         if (port_state == VPORT_STATE_UP) {
  88                 netdev_info(priv->netdev, "Link up\n");
  89                 netif_carrier_on(priv->netdev);
  90         } else {
  91                 netdev_info(priv->netdev, "Link down\n");
  92                 netif_carrier_off(priv->netdev);
  93         }
  94 }
  95
  96 static void mlx5e_update_carrier_work(struct work_struct *work)
  97 {
  98         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  99                                                update_carrier_work);
 100
 101         mutex_lock(&priv->state_lock);
 102         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 103                 mlx5e_update_carrier(priv);
 104         mutex_unlock(&priv->state_lock);
 105 }
 106
 107 static void mlx5e_tx_timeout_work(struct work_struct *work)
 108 {
 109         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 110                                                tx_timeout_work);
 111         int err;
 112
 113         rtnl_lock();
 114         mutex_lock(&priv->state_lock);
 115         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 116                 goto unlock;
 117         mlx5e_close_locked(priv->netdev);
 118         err = mlx5e_open_locked(priv->netdev);
 119         if (err)
 120                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 121                            err);
 122 unlock:
 123         mutex_unlock(&priv->state_lock);
 124         rtnl_unlock();
 125 }
 126
 127 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 128 {
 129         struct mlx5e_sw_stats *s = &priv->stats.sw;
 130         struct mlx5e_rq_stats *rq_stats;
 131         struct mlx5e_sq_stats *sq_stats;
 132         u64 tx_offload_none = 0;
 133         int i, j;
 134
 135         memset(s, 0, sizeof(*s));
 136         for (i = 0; i < priv->params.num_channels; i++) {
 137                 rq_stats = &priv->channel[i]->rq.stats;
 138
 139                 s->rx_packets   += rq_stats->packets;
 140                 s->rx_bytes     += rq_stats->bytes;
 141                 s->rx_lro_packets += rq_stats->lro_packets;
 142                 s->rx_lro_bytes += rq_stats->lro_bytes;
 143                 s->rx_csum_none += rq_stats->csum_none;
 144                 s->rx_csum_complete += rq_stats->csum_complete;
 145                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 146                 s->rx_wqe_err   += rq_stats->wqe_err;
 147                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 148                 s->rx_mpwqe_frag   += rq_stats->mpwqe_frag;
 149                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 150                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 151                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 152
 153                 for (j = 0; j < priv->params.num_tc; j++) {
 154                         sq_stats = &priv->channel[i]->sq[j].stats;
 155
 156                         s->tx_packets           += sq_stats->packets;
 157                         s->tx_bytes             += sq_stats->bytes;
 158                         s->tx_tso_packets       += sq_stats->tso_packets;
 159                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 160                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 161                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 162                         s->tx_queue_stopped     += sq_stats->stopped;
 163                         s->tx_queue_wake        += sq_stats->wake;
 164                         s->tx_queue_dropped     += sq_stats->dropped;
 165                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 166                         tx_offload_none         += sq_stats->csum_none;
 167                 }
 168         }
 169
 170         /* Update calculated offload counters */
 171         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
 172         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 173
 174         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 175                                 priv->stats.pport.phy_counters,
 176                                 counter_set.phys_layer_cntrs.link_down_events);
 177 }
 178
 179 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 180 {
 181         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 182         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 183         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 184         struct mlx5_core_dev *mdev = priv->mdev;
 185
 186         memset(in, 0, sizeof(in));
 187
 188         MLX5_SET(query_vport_counter_in, in, opcode,
 189                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 190         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 191         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 192
 193         memset(out, 0, outlen);
 194
 195         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 196 }
 197
 198 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 199 {
 200         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 201         struct mlx5_core_dev *mdev = priv->mdev;
 202         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 203         int prio;
 204         void *out;
 205         u32 *in;
 206
 207         in = mlx5_vzalloc(sz);
 208         if (!in)
 209                 goto free_out;
 210
 211         MLX5_SET(ppcnt_reg, in, local_port, 1);
 212
 213         out = pstats->IEEE_802_3_counters;
 214         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 215         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 216
 217         out = pstats->RFC_2863_counters;
 218         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 219         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 220
 221         out = pstats->RFC_2819_counters;
 222         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 223         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 224
 225         out = pstats->phy_counters;
 226         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 227         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 228
 229         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 230         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 231                 out = pstats->per_prio_counters[prio];
 232                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 233                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 234                                      MLX5_REG_PPCNT, 0, 0);
 235         }
 236
 237 free_out:
 238         kvfree(in);
 239 }
 240
 241 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 242 {
 243         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 244
 245         if (!priv->q_counter)
 246                 return;
 247
 248         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 249                                       &qcnt->rx_out_of_buffer);
 250 }
 251
 252 void mlx5e_update_stats(struct mlx5e_priv *priv)
 253 {
 254         mlx5e_update_q_counter(priv);
 255         mlx5e_update_vport_counters(priv);
 256         mlx5e_update_pport_counters(priv);
 257         mlx5e_update_sw_counters(priv);
 258 }
 259
 260 void mlx5e_update_stats_work(struct work_struct *work)
 261 {
 262         struct delayed_work *dwork = to_delayed_work(work);
 263         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 264                                                update_stats_work);
 265         mutex_lock(&priv->state_lock);
 266         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 267                 priv->profile->update_stats(priv);
 268                 queue_delayed_work(priv->wq, dwork,
 269                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 270         }
 271         mutex_unlock(&priv->state_lock);
 272 }
 273
 274 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 275                               enum mlx5_dev_event event, unsigned long param)
 276 {
 277         struct mlx5e_priv *priv = vpriv;
 278
 279         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 280                 return;
 281
 282         switch (event) {
 283         case MLX5_DEV_EVENT_PORT_UP:
 284         case MLX5_DEV_EVENT_PORT_DOWN:
 285                 queue_work(priv->wq, &priv->update_carrier_work);
 286                 break;
 287
 288         default:
 289                 break;
 290         }
 291 }
 292
 293 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 294 {
 295         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 296 }
 297
 298 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 299 {
 300         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 301         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 302 }
 303
 304 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 305 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 306
 307 static int mlx5e_create_rq(struct mlx5e_channel *c,
 308                            struct mlx5e_rq_param *param,
 309                            struct mlx5e_rq *rq)
 310 {
 311         struct mlx5e_priv *priv = c->priv;
 312         struct mlx5_core_dev *mdev = priv->mdev;
 313         void *rqc = param->rqc;
 314         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 315         u32 byte_count;
 316         int wq_sz;
 317         int err;
 318         int i;
 319
 320         param->wq.db_numa_node = cpu_to_node(c->cpu);
 321
 322         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 323                                 &rq->wq_ctrl);
 324         if (err)
 325                 return err;
 326
 327         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 328
 329         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 330
 331         switch (priv->params.rq_wq_type) {
 332         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 333                 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
 334                                             GFP_KERNEL, cpu_to_node(c->cpu));
 335                 if (!rq->wqe_info) {
 336                         err = -ENOMEM;
 337                         goto err_rq_wq_destroy;
 338                 }
 339                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 340                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 341                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 342
 343                 rq->mpwqe_mtt_offset = c->ix *
 344                         MLX5E_REQUIRED_MTTS(1, BIT(priv->params.log_rq_size));
 345
 346                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 347                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 348                 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 349                 byte_count = rq->wqe_sz;
 350                 break;
 351         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 352                 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 353                                        cpu_to_node(c->cpu));
 354                 if (!rq->skb) {
 355                         err = -ENOMEM;
 356                         goto err_rq_wq_destroy;
 357                 }
 358                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 359                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 360                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 361
 362                 rq->wqe_sz = (priv->params.lro_en) ?
 363                                 priv->params.lro_wqe_sz :
 364                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 365                 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
 366                 byte_count = rq->wqe_sz;
 367                 byte_count |= MLX5_HW_START_PADDING;
 368         }
 369
 370         for (i = 0; i < wq_sz; i++) {
 371                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 372
 373                 wqe->data.byte_count = cpu_to_be32(byte_count);
 374         }
 375
 376         INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
 377         rq->am.mode = priv->params.rx_cq_period_mode;
 378
 379         rq->wq_type = priv->params.rq_wq_type;
 380         rq->pdev    = c->pdev;
 381         rq->netdev  = c->netdev;
 382         rq->tstamp  = &priv->tstamp;
 383         rq->channel = c;
 384         rq->ix      = c->ix;
 385         rq->priv    = c->priv;
 386         rq->mkey_be = c->mkey_be;
 387         rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 388
 389         return 0;
 390
 391 err_rq_wq_destroy:
 392         mlx5_wq_destroy(&rq->wq_ctrl);
 393
 394         return err;
 395 }
 396
 397 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 398 {
 399         switch (rq->wq_type) {
 400         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 401                 kfree(rq->wqe_info);
 402                 break;
 403         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 404                 kfree(rq->skb);
 405         }
 406
 407         mlx5_wq_destroy(&rq->wq_ctrl);
 408 }
 409
 410 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 411 {
 412         struct mlx5e_priv *priv = rq->priv;
 413         struct mlx5_core_dev *mdev = priv->mdev;
 414
 415         void *in;
 416         void *rqc;
 417         void *wq;
 418         int inlen;
 419         int err;
 420
 421         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 422                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 423         in = mlx5_vzalloc(inlen);
 424         if (!in)
 425                 return -ENOMEM;
 426
 427         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 428         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 429
 430         memcpy(rqc, param->rqc, sizeof(param->rqc));
 431
 432         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 433         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 434         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 435         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 436                                                 MLX5_ADAPTER_PAGE_SHIFT);
 437         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 438
 439         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 440                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 441
 442         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 443
 444         kvfree(in);
 445
 446         return err;
 447 }
 448
 449 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 450                                  int next_state)
 451 {
 452         struct mlx5e_channel *c = rq->channel;
 453         struct mlx5e_priv *priv = c->priv;
 454         struct mlx5_core_dev *mdev = priv->mdev;
 455
 456         void *in;
 457         void *rqc;
 458         int inlen;
 459         int err;
 460
 461         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 462         in = mlx5_vzalloc(inlen);
 463         if (!in)
 464                 return -ENOMEM;
 465
 466         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 467
 468         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 469         MLX5_SET(rqc, rqc, state, next_state);
 470
 471         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 472
 473         kvfree(in);
 474
 475         return err;
 476 }
 477
 478 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 479 {
 480         struct mlx5e_channel *c = rq->channel;
 481         struct mlx5e_priv *priv = c->priv;
 482         struct mlx5_core_dev *mdev = priv->mdev;
 483
 484         void *in;
 485         void *rqc;
 486         int inlen;
 487         int err;
 488
 489         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 490         in = mlx5_vzalloc(inlen);
 491         if (!in)
 492                 return -ENOMEM;
 493
 494         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 495
 496         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 497         MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
 498         MLX5_SET(rqc, rqc, vsd, vsd);
 499         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 500
 501         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 502
 503         kvfree(in);
 504
 505         return err;
 506 }
 507
 508 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 509 {
 510         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 511 }
 512
 513 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 514 {
 515         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 516         struct mlx5e_channel *c = rq->channel;
 517         struct mlx5e_priv *priv = c->priv;
 518         struct mlx5_wq_ll *wq = &rq->wq;
 519
 520         while (time_before(jiffies, exp_time)) {
 521                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 522                         return 0;
 523
 524                 msleep(20);
 525         }
 526
 527         return -ETIMEDOUT;
 528 }
 529
 530 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 531 {
 532         struct mlx5_wq_ll *wq = &rq->wq;
 533         struct mlx5e_rx_wqe *wqe;
 534         __be16 wqe_ix_be;
 535         u16 wqe_ix;
 536
 537         while (!mlx5_wq_ll_is_empty(wq)) {
 538                 wqe_ix_be = *wq->tail_next;
 539                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 540                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 541                 rq->dealloc_wqe(rq, wqe_ix);
 542                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 543                                &wqe->next.next_wqe_index);
 544         }
 545 }
 546
 547 static int mlx5e_open_rq(struct mlx5e_channel *c,
 548                          struct mlx5e_rq_param *param,
 549                          struct mlx5e_rq *rq)
 550 {
 551         struct mlx5e_sq *sq = &c->icosq;
 552         u16 pi = sq->pc & sq->wq.sz_m1;
 553         int err;
 554
 555         err = mlx5e_create_rq(c, param, rq);
 556         if (err)
 557                 return err;
 558
 559         err = mlx5e_enable_rq(rq, param);
 560         if (err)
 561                 goto err_destroy_rq;
 562
 563         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 564         if (err)
 565                 goto err_disable_rq;
 566
 567         if (param->am_enabled)
 568                 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 569
 570         sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
 571         sq->ico_wqe_info[pi].num_wqebbs = 1;
 572         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 573
 574         return 0;
 575
 576 err_disable_rq:
 577         mlx5e_disable_rq(rq);
 578 err_destroy_rq:
 579         mlx5e_destroy_rq(rq);
 580
 581         return err;
 582 }
 583
 584 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 585 {
 586         set_bit(MLX5E_RQ_STATE_FLUSH, &rq->state);
 587         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 588         cancel_work_sync(&rq->am.work);
 589
 590         mlx5e_disable_rq(rq);
 591         mlx5e_free_rx_descs(rq);
 592         mlx5e_destroy_rq(rq);
 593 }
 594
 595 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 596 {
 597         kfree(sq->wqe_info);
 598         kfree(sq->dma_fifo);
 599         kfree(sq->skb);
 600 }
 601
 602 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 603 {
 604         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 605         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 606
 607         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 608         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 609                                     numa);
 610         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 611                                     numa);
 612
 613         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 614                 mlx5e_free_sq_db(sq);
 615                 return -ENOMEM;
 616         }
 617
 618         sq->dma_fifo_mask = df_sz - 1;
 619
 620         return 0;
 621 }
 622
 623 static int mlx5e_create_sq(struct mlx5e_channel *c,
 624                            int tc,
 625                            struct mlx5e_sq_param *param,
 626                            struct mlx5e_sq *sq)
 627 {
 628         struct mlx5e_priv *priv = c->priv;
 629         struct mlx5_core_dev *mdev = priv->mdev;
 630
 631         void *sqc = param->sqc;
 632         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 633         int err;
 634
 635         err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
 636         if (err)
 637                 return err;
 638
 639         param->wq.db_numa_node = cpu_to_node(c->cpu);
 640
 641         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 642                                  &sq->wq_ctrl);
 643         if (err)
 644                 goto err_unmap_free_uar;
 645
 646         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 647         if (sq->uar.bf_map) {
 648                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 649                 sq->uar_map = sq->uar.bf_map;
 650         } else {
 651                 sq->uar_map = sq->uar.map;
 652         }
 653         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 654         sq->max_inline  = param->max_inline;
 655         sq->min_inline_mode =
 656                 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
 657                 param->min_inline_mode : 0;
 658
 659         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 660         if (err)
 661                 goto err_sq_wq_destroy;
 662
 663         if (param->icosq) {
 664                 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 665
 666                 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
 667                                                 wq_sz,
 668                                                 GFP_KERNEL,
 669                                                 cpu_to_node(c->cpu));
 670                 if (!sq->ico_wqe_info) {
 671                         err = -ENOMEM;
 672                         goto err_free_sq_db;
 673                 }
 674         } else {
 675                 int txq_ix;
 676
 677                 txq_ix = c->ix + tc * priv->params.num_channels;
 678                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 679                 priv->txq_to_sq_map[txq_ix] = sq;
 680         }
 681
 682         sq->pdev      = c->pdev;
 683         sq->tstamp    = &priv->tstamp;
 684         sq->mkey_be   = c->mkey_be;
 685         sq->channel   = c;
 686         sq->tc        = tc;
 687         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 688         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 689
 690         return 0;
 691
 692 err_free_sq_db:
 693         mlx5e_free_sq_db(sq);
 694
 695 err_sq_wq_destroy:
 696         mlx5_wq_destroy(&sq->wq_ctrl);
 697
 698 err_unmap_free_uar:
 699         mlx5_unmap_free_uar(mdev, &sq->uar);
 700
 701         return err;
 702 }
 703
 704 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 705 {
 706         struct mlx5e_channel *c = sq->channel;
 707         struct mlx5e_priv *priv = c->priv;
 708
 709         kfree(sq->ico_wqe_info);
 710         mlx5e_free_sq_db(sq);
 711         mlx5_wq_destroy(&sq->wq_ctrl);
 712         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 713 }
 714
 715 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 716 {
 717         struct mlx5e_channel *c = sq->channel;
 718         struct mlx5e_priv *priv = c->priv;
 719         struct mlx5_core_dev *mdev = priv->mdev;
 720
 721         void *in;
 722         void *sqc;
 723         void *wq;
 724         int inlen;
 725         int err;
 726
 727         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 728                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 729         in = mlx5_vzalloc(inlen);
 730         if (!in)
 731                 return -ENOMEM;
 732
 733         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 734         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 735
 736         memcpy(sqc, param->sqc, sizeof(param->sqc));
 737
 738         MLX5_SET(sqc,  sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
 739         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
 740         MLX5_SET(sqc,  sqc, min_wqe_inline_mode, sq->min_inline_mode);
 741         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 742         MLX5_SET(sqc,  sqc, tis_lst_sz,         param->icosq ? 0 : 1);
 743         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 744
 745         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 746         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 747         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 748                                           MLX5_ADAPTER_PAGE_SHIFT);
 749         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 750
 751         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 752                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 753
 754         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 755
 756         kvfree(in);
 757
 758         return err;
 759 }
 760
 761 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
 762                            int next_state, bool update_rl, int rl_index)
 763 {
 764         struct mlx5e_channel *c = sq->channel;
 765         struct mlx5e_priv *priv = c->priv;
 766         struct mlx5_core_dev *mdev = priv->mdev;
 767
 768         void *in;
 769         void *sqc;
 770         int inlen;
 771         int err;
 772
 773         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 774         in = mlx5_vzalloc(inlen);
 775         if (!in)
 776                 return -ENOMEM;
 777
 778         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 779
 780         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 781         MLX5_SET(sqc, sqc, state, next_state);
 782         if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
 783                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
 784                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, rl_index);
 785         }
 786
 787         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 788
 789         kvfree(in);
 790
 791         return err;
 792 }
 793
 794 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 795 {
 796         struct mlx5e_channel *c = sq->channel;
 797         struct mlx5e_priv *priv = c->priv;
 798         struct mlx5_core_dev *mdev = priv->mdev;
 799
 800         mlx5_core_destroy_sq(mdev, sq->sqn);
 801         if (sq->rate_limit)
 802                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
 803 }
 804
 805 static int mlx5e_open_sq(struct mlx5e_channel *c,
 806                          int tc,
 807                          struct mlx5e_sq_param *param,
 808                          struct mlx5e_sq *sq)
 809 {
 810         int err;
 811
 812         err = mlx5e_create_sq(c, tc, param, sq);
 813         if (err)
 814                 return err;
 815
 816         err = mlx5e_enable_sq(sq, param);
 817         if (err)
 818                 goto err_destroy_sq;
 819
 820         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
 821                               false, 0);
 822         if (err)
 823                 goto err_disable_sq;
 824
 825         if (sq->txq) {
 826                 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 827                 netdev_tx_reset_queue(sq->txq);
 828                 netif_tx_start_queue(sq->txq);
 829         }
 830
 831         return 0;
 832
 833 err_disable_sq:
 834         mlx5e_disable_sq(sq);
 835 err_destroy_sq:
 836         mlx5e_destroy_sq(sq);
 837
 838         return err;
 839 }
 840
 841 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 842 {
 843         __netif_tx_lock_bh(txq);
 844         netif_tx_stop_queue(txq);
 845         __netif_tx_unlock_bh(txq);
 846 }
 847
 848 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 849 {
 850         int tout = 0;
 851         int err;
 852
 853         if (sq->txq) {
 854                 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 855                 /* prevent netif_tx_wake_queue */
 856                 napi_synchronize(&sq->channel->napi);
 857                 netif_tx_disable_queue(sq->txq);
 858
 859                 /* ensure hw is notified of all pending wqes */
 860                 if (mlx5e_sq_has_room_for(sq, 1))
 861                         mlx5e_send_nop(sq, true);
 862
 863                 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
 864                                       MLX5_SQC_STATE_ERR, false, 0);
 865                 if (err)
 866                         set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
 867         }
 868
 869         /* wait till sq is empty, unless a TX timeout occurred on this SQ */
 870         while (sq->cc != sq->pc &&
 871                !test_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state)) {
 872                 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
 873                 if (tout++ > MLX5_EN_QP_FLUSH_MAX_ITER)
 874                         set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
 875         }
 876
 877         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 878         napi_synchronize(&sq->channel->napi);
 879
 880         mlx5e_free_tx_descs(sq);
 881         mlx5e_disable_sq(sq);
 882         mlx5e_destroy_sq(sq);
 883 }
 884
 885 static int mlx5e_create_cq(struct mlx5e_channel *c,
 886                            struct mlx5e_cq_param *param,
 887                            struct mlx5e_cq *cq)
 888 {
 889         struct mlx5e_priv *priv = c->priv;
 890         struct mlx5_core_dev *mdev = priv->mdev;
 891         struct mlx5_core_cq *mcq = &cq->mcq;
 892         int eqn_not_used;
 893         unsigned int irqn;
 894         int err;
 895         u32 i;
 896
 897         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 898         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 899         param->eq_ix   = c->ix;
 900
 901         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 902                                &cq->wq_ctrl);
 903         if (err)
 904                 return err;
 905
 906         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 907
 908         cq->napi        = &c->napi;
 909
 910         mcq->cqe_sz     = 64;
 911         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 912         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 913         *mcq->set_ci_db = 0;
 914         *mcq->arm_db    = 0;
 915         mcq->vector     = param->eq_ix;
 916         mcq->comp       = mlx5e_completion_event;
 917         mcq->event      = mlx5e_cq_error_event;
 918         mcq->irqn       = irqn;
 919         mcq->uar        = &mdev->mlx5e_res.cq_uar;
 920
 921         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 922                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 923
 924                 cqe->op_own = 0xf1;
 925         }
 926
 927         cq->channel = c;
 928         cq->priv = priv;
 929
 930         return 0;
 931 }
 932
 933 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 934 {
 935         mlx5_wq_destroy(&cq->wq_ctrl);
 936 }
 937
 938 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 939 {
 940         struct mlx5e_priv *priv = cq->priv;
 941         struct mlx5_core_dev *mdev = priv->mdev;
 942         struct mlx5_core_cq *mcq = &cq->mcq;
 943
 944         void *in;
 945         void *cqc;
 946         int inlen;
 947         unsigned int irqn_not_used;
 948         int eqn;
 949         int err;
 950
 951         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 952                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 953         in = mlx5_vzalloc(inlen);
 954         if (!in)
 955                 return -ENOMEM;
 956
 957         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 958
 959         memcpy(cqc, param->cqc, sizeof(param->cqc));
 960
 961         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 962                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 963
 964         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 965
 966         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
 967         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 968         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 969         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 970                                             MLX5_ADAPTER_PAGE_SHIFT);
 971         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 972
 973         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 974
 975         kvfree(in);
 976
 977         if (err)
 978                 return err;
 979
 980         mlx5e_cq_arm(cq);
 981
 982         return 0;
 983 }
 984
 985 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 986 {
 987         struct mlx5e_priv *priv = cq->priv;
 988         struct mlx5_core_dev *mdev = priv->mdev;
 989
 990         mlx5_core_destroy_cq(mdev, &cq->mcq);
 991 }
 992
 993 static int mlx5e_open_cq(struct mlx5e_channel *c,
 994                          struct mlx5e_cq_param *param,
 995                          struct mlx5e_cq *cq,
 996                          struct mlx5e_cq_moder moderation)
 997 {
 998         int err;
 999         struct mlx5e_priv *priv = c->priv;
1000         struct mlx5_core_dev *mdev = priv->mdev;
1001
1002         err = mlx5e_create_cq(c, param, cq);
1003         if (err)
1004                 return err;
1005
1006         err = mlx5e_enable_cq(cq, param);
1007         if (err)
1008                 goto err_destroy_cq;
1009
1010         if (MLX5_CAP_GEN(mdev, cq_moderation))
1011                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1012                                                moderation.usec,
1013                                                moderation.pkts);
1014         return 0;
1015
1016 err_destroy_cq:
1017         mlx5e_destroy_cq(cq);
1018
1019         return err;
1020 }
1021
1022 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1023 {
1024         mlx5e_disable_cq(cq);
1025         mlx5e_destroy_cq(cq);
1026 }
1027
1028 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1029 {
1030         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1031 }
1032
1033 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1034                              struct mlx5e_channel_param *cparam)
1035 {
1036         struct mlx5e_priv *priv = c->priv;
1037         int err;
1038         int tc;
1039
1040         for (tc = 0; tc < c->num_tc; tc++) {
1041                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1042                                     priv->params.tx_cq_moderation);
1043                 if (err)
1044                         goto err_close_tx_cqs;
1045         }
1046
1047         return 0;
1048
1049 err_close_tx_cqs:
1050         for (tc--; tc >= 0; tc--)
1051                 mlx5e_close_cq(&c->sq[tc].cq);
1052
1053         return err;
1054 }
1055
1056 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1057 {
1058         int tc;
1059
1060         for (tc = 0; tc < c->num_tc; tc++)
1061                 mlx5e_close_cq(&c->sq[tc].cq);
1062 }
1063
1064 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1065                           struct mlx5e_channel_param *cparam)
1066 {
1067         int err;
1068         int tc;
1069
1070         for (tc = 0; tc < c->num_tc; tc++) {
1071                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1072                 if (err)
1073                         goto err_close_sqs;
1074         }
1075
1076         return 0;
1077
1078 err_close_sqs:
1079         for (tc--; tc >= 0; tc--)
1080                 mlx5e_close_sq(&c->sq[tc]);
1081
1082         return err;
1083 }
1084
1085 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1086 {
1087         int tc;
1088
1089         for (tc = 0; tc < c->num_tc; tc++)
1090                 mlx5e_close_sq(&c->sq[tc]);
1091 }
1092
1093 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1094 {
1095         int i;
1096
1097         for (i = 0; i < priv->profile->max_tc; i++)
1098                 priv->channeltc_to_txq_map[ix][i] =
1099                         ix + i * priv->params.num_channels;
1100 }
1101
1102 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1103                                 struct mlx5e_sq *sq, u32 rate)
1104 {
1105         struct mlx5e_priv *priv = netdev_priv(dev);
1106         struct mlx5_core_dev *mdev = priv->mdev;
1107         u16 rl_index = 0;
1108         int err;
1109
1110         if (rate == sq->rate_limit)
1111                 /* nothing to do */
1112                 return 0;
1113
1114         if (sq->rate_limit)
1115                 /* remove current rl index to free space to next ones */
1116                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1117
1118         sq->rate_limit = 0;
1119
1120         if (rate) {
1121                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1122                 if (err) {
1123                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1124                                    rate, err);
1125                         return err;
1126                 }
1127         }
1128
1129         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1130                               MLX5_SQC_STATE_RDY, true, rl_index);
1131         if (err) {
1132                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1133                            rate, err);
1134                 /* remove the rate from the table */
1135                 if (rate)
1136                         mlx5_rl_remove_rate(mdev, rate);
1137                 return err;
1138         }
1139
1140         sq->rate_limit = rate;
1141         return 0;
1142 }
1143
1144 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1145 {
1146         struct mlx5e_priv *priv = netdev_priv(dev);
1147         struct mlx5_core_dev *mdev = priv->mdev;
1148         struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1149         int err = 0;
1150
1151         if (!mlx5_rl_is_supported(mdev)) {
1152                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1153                 return -EINVAL;
1154         }
1155
1156         /* rate is given in Mb/sec, HW config is in Kb/sec */
1157         rate = rate << 10;
1158
1159         /* Check whether rate in valid range, 0 is always valid */
1160         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1161                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1162                 return -ERANGE;
1163         }
1164
1165         mutex_lock(&priv->state_lock);
1166         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1167                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1168         if (!err)
1169                 priv->tx_rates[index] = rate;
1170         mutex_unlock(&priv->state_lock);
1171
1172         return err;
1173 }
1174
1175 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1176                               struct mlx5e_channel_param *cparam,
1177                               struct mlx5e_channel **cp)
1178 {
1179         struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1180         struct net_device *netdev = priv->netdev;
1181         struct mlx5e_cq_moder rx_cq_profile;
1182         int cpu = mlx5e_get_cpu(priv, ix);
1183         struct mlx5e_channel *c;
1184         struct mlx5e_sq *sq;
1185         int err;
1186         int i;
1187
1188         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1189         if (!c)
1190                 return -ENOMEM;
1191
1192         c->priv     = priv;
1193         c->ix       = ix;
1194         c->cpu      = cpu;
1195         c->pdev     = &priv->mdev->pdev->dev;
1196         c->netdev   = priv->netdev;
1197         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1198         c->num_tc   = priv->params.num_tc;
1199
1200         if (priv->params.rx_am_enabled)
1201                 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1202         else
1203                 rx_cq_profile = priv->params.rx_cq_moderation;
1204
1205         mlx5e_build_channeltc_to_txq_map(priv, ix);
1206
1207         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1208
1209         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1210         if (err)
1211                 goto err_napi_del;
1212
1213         err = mlx5e_open_tx_cqs(c, cparam);
1214         if (err)
1215                 goto err_close_icosq_cq;
1216
1217         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1218                             rx_cq_profile);
1219         if (err)
1220                 goto err_close_tx_cqs;
1221
1222         napi_enable(&c->napi);
1223
1224         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1225         if (err)
1226                 goto err_disable_napi;
1227
1228         err = mlx5e_open_sqs(c, cparam);
1229         if (err)
1230                 goto err_close_icosq;
1231
1232         for (i = 0; i < priv->params.num_tc; i++) {
1233                 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1234
1235                 if (priv->tx_rates[txq_ix]) {
1236                         sq = priv->txq_to_sq_map[txq_ix];
1237                         mlx5e_set_sq_maxrate(priv->netdev, sq,
1238                                              priv->tx_rates[txq_ix]);
1239                 }
1240         }
1241
1242         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1243         if (err)
1244                 goto err_close_sqs;
1245
1246         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1247         *cp = c;
1248
1249         return 0;
1250
1251 err_close_sqs:
1252         mlx5e_close_sqs(c);
1253
1254 err_close_icosq:
1255         mlx5e_close_sq(&c->icosq);
1256
1257 err_disable_napi:
1258         napi_disable(&c->napi);
1259         mlx5e_close_cq(&c->rq.cq);
1260
1261 err_close_tx_cqs:
1262         mlx5e_close_tx_cqs(c);
1263
1264 err_close_icosq_cq:
1265         mlx5e_close_cq(&c->icosq.cq);
1266
1267 err_napi_del:
1268         netif_napi_del(&c->napi);
1269         napi_hash_del(&c->napi);
1270         kfree(c);
1271
1272         return err;
1273 }
1274
1275 static void mlx5e_close_channel(struct mlx5e_channel *c)
1276 {
1277         mlx5e_close_rq(&c->rq);
1278         mlx5e_close_sqs(c);
1279         mlx5e_close_sq(&c->icosq);
1280         napi_disable(&c->napi);
1281         mlx5e_close_cq(&c->rq.cq);
1282         mlx5e_close_tx_cqs(c);
1283         mlx5e_close_cq(&c->icosq.cq);
1284         netif_napi_del(&c->napi);
1285
1286         napi_hash_del(&c->napi);
1287         synchronize_rcu();
1288
1289         kfree(c);
1290 }
1291
1292 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1293                                  struct mlx5e_rq_param *param)
1294 {
1295         void *rqc = param->rqc;
1296         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1297
1298         switch (priv->params.rq_wq_type) {
1299         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1300                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1301                          priv->params.mpwqe_log_num_strides - 9);
1302                 MLX5_SET(wq, wq, log_wqe_stride_size,
1303                          priv->params.mpwqe_log_stride_sz - 6);
1304                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1305                 break;
1306         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1307                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1308         }
1309
1310         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1311         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1312         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1313         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1314         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1315
1316         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1317         param->wq.linear = 1;
1318
1319         param->am_enabled = priv->params.rx_am_enabled;
1320 }
1321
1322 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1323 {
1324         void *rqc = param->rqc;
1325         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1326
1327         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1328         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1329 }
1330
1331 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1332                                         struct mlx5e_sq_param *param)
1333 {
1334         void *sqc = param->sqc;
1335         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1336
1337         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1338         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1339
1340         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1341 }
1342
1343 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1344                                  struct mlx5e_sq_param *param)
1345 {
1346         void *sqc = param->sqc;
1347         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1348
1349         mlx5e_build_sq_param_common(priv, param);
1350         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1351
1352         param->max_inline = priv->params.tx_max_inline;
1353         param->min_inline_mode = priv->params.tx_min_inline_mode;
1354 }
1355
1356 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1357                                         struct mlx5e_cq_param *param)
1358 {
1359         void *cqc = param->cqc;
1360
1361         MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
1362 }
1363
1364 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1365                                     struct mlx5e_cq_param *param)
1366 {
1367         void *cqc = param->cqc;
1368         u8 log_cq_size;
1369
1370         switch (priv->params.rq_wq_type) {
1371         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1372                 log_cq_size = priv->params.log_rq_size +
1373                         priv->params.mpwqe_log_num_strides;
1374                 break;
1375         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1376                 log_cq_size = priv->params.log_rq_size;
1377         }
1378
1379         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1380         if (priv->params.rx_cqe_compress) {
1381                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1382                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1383         }
1384
1385         mlx5e_build_common_cq_param(priv, param);
1386
1387         param->cq_period_mode = priv->params.rx_cq_period_mode;
1388 }
1389
1390 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1391                                     struct mlx5e_cq_param *param)
1392 {
1393         void *cqc = param->cqc;
1394
1395         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1396
1397         mlx5e_build_common_cq_param(priv, param);
1398
1399         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1400 }
1401
1402 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1403                                      struct mlx5e_cq_param *param,
1404                                      u8 log_wq_size)
1405 {
1406         void *cqc = param->cqc;
1407
1408         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1409
1410         mlx5e_build_common_cq_param(priv, param);
1411
1412         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1413 }
1414
1415 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1416                                     struct mlx5e_sq_param *param,
1417                                     u8 log_wq_size)
1418 {
1419         void *sqc = param->sqc;
1420         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1421
1422         mlx5e_build_sq_param_common(priv, param);
1423
1424         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1425         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1426
1427         param->icosq = true;
1428 }
1429
1430 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1431 {
1432         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1433
1434         mlx5e_build_rq_param(priv, &cparam->rq);
1435         mlx5e_build_sq_param(priv, &cparam->sq);
1436         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1437         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1438         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1439         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1440 }
1441
1442 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1443 {
1444         struct mlx5e_channel_param *cparam;
1445         int nch = priv->params.num_channels;
1446         int err = -ENOMEM;
1447         int i;
1448         int j;
1449
1450         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1451                                 GFP_KERNEL);
1452
1453         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1454                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1455
1456         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1457
1458         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1459                 goto err_free_txq_to_sq_map;
1460
1461         mlx5e_build_channel_param(priv, cparam);
1462
1463         for (i = 0; i < nch; i++) {
1464                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1465                 if (err)
1466                         goto err_close_channels;
1467         }
1468
1469         for (j = 0; j < nch; j++) {
1470                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1471                 if (err)
1472                         goto err_close_channels;
1473         }
1474
1475         /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1476          * polling for inactive tx queues.
1477          */
1478         netif_tx_start_all_queues(priv->netdev);
1479
1480         kfree(cparam);
1481         return 0;
1482
1483 err_close_channels:
1484         for (i--; i >= 0; i--)
1485                 mlx5e_close_channel(priv->channel[i]);
1486
1487 err_free_txq_to_sq_map:
1488         kfree(priv->txq_to_sq_map);
1489         kfree(priv->channel);
1490         kfree(cparam);
1491
1492         return err;
1493 }
1494
1495 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1496 {
1497         int i;
1498
1499         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1500          * polling for inactive tx queues.
1501          */
1502         netif_tx_stop_all_queues(priv->netdev);
1503         netif_tx_disable(priv->netdev);
1504
1505         for (i = 0; i < priv->params.num_channels; i++)
1506                 mlx5e_close_channel(priv->channel[i]);
1507
1508         kfree(priv->txq_to_sq_map);
1509         kfree(priv->channel);
1510 }
1511
1512 static int mlx5e_rx_hash_fn(int hfunc)
1513 {
1514         return (hfunc == ETH_RSS_HASH_TOP) ?
1515                MLX5_RX_HASH_FN_TOEPLITZ :
1516                MLX5_RX_HASH_FN_INVERTED_XOR8;
1517 }
1518
1519 static int mlx5e_bits_invert(unsigned long a, int size)
1520 {
1521         int inv = 0;
1522         int i;
1523
1524         for (i = 0; i < size; i++)
1525                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1526
1527         return inv;
1528 }
1529
1530 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1531 {
1532         int i;
1533
1534         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1535                 int ix = i;
1536                 u32 rqn;
1537
1538                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1539                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1540
1541                 ix = priv->params.indirection_rqt[ix];
1542                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1543                                 priv->channel[ix]->rq.rqn :
1544                                 priv->drop_rq.rqn;
1545                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1546         }
1547 }
1548
1549 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1550                                       int ix)
1551 {
1552         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1553                         priv->channel[ix]->rq.rqn :
1554                         priv->drop_rq.rqn;
1555
1556         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1557 }
1558
1559 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1560                             int ix, struct mlx5e_rqt *rqt)
1561 {
1562         struct mlx5_core_dev *mdev = priv->mdev;
1563         void *rqtc;
1564         int inlen;
1565         int err;
1566         u32 *in;
1567
1568         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1569         in = mlx5_vzalloc(inlen);
1570         if (!in)
1571                 return -ENOMEM;
1572
1573         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1574
1575         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1576         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1577
1578         if (sz > 1) /* RSS */
1579                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1580         else
1581                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1582
1583         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1584         if (!err)
1585                 rqt->enabled = true;
1586
1587         kvfree(in);
1588         return err;
1589 }
1590
1591 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1592 {
1593         rqt->enabled = false;
1594         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1595 }
1596
1597 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1598 {
1599         struct mlx5e_rqt *rqt = &priv->indir_rqt;
1600
1601         return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1602 }
1603
1604 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1605 {
1606         struct mlx5e_rqt *rqt;
1607         int err;
1608         int ix;
1609
1610         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1611                 rqt = &priv->direct_tir[ix].rqt;
1612                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1613                 if (err)
1614                         goto err_destroy_rqts;
1615         }
1616
1617         return 0;
1618
1619 err_destroy_rqts:
1620         for (ix--; ix >= 0; ix--)
1621                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1622
1623         return err;
1624 }
1625
1626 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1627 {
1628         struct mlx5_core_dev *mdev = priv->mdev;
1629         void *rqtc;
1630         int inlen;
1631         u32 *in;
1632         int err;
1633
1634         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1635         in = mlx5_vzalloc(inlen);
1636         if (!in)
1637                 return -ENOMEM;
1638
1639         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1640
1641         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1642         if (sz > 1) /* RSS */
1643                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1644         else
1645                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1646
1647         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1648
1649         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1650
1651         kvfree(in);
1652
1653         return err;
1654 }
1655
1656 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1657 {
1658         u32 rqtn;
1659         int ix;
1660
1661         if (priv->indir_rqt.enabled) {
1662                 rqtn = priv->indir_rqt.rqtn;
1663                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1664         }
1665
1666         for (ix = 0; ix < priv->params.num_channels; ix++) {
1667                 if (!priv->direct_tir[ix].rqt.enabled)
1668                         continue;
1669                 rqtn = priv->direct_tir[ix].rqt.rqtn;
1670                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1671         }
1672 }
1673
1674 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1675 {
1676         if (!priv->params.lro_en)
1677                 return;
1678
1679 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1680
1681         MLX5_SET(tirc, tirc, lro_enable_mask,
1682                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1683                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1684         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1685                  (priv->params.lro_wqe_sz -
1686                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1687         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1688                  MLX5_CAP_ETH(priv->mdev,
1689                               lro_timer_supported_periods[2]));
1690 }
1691
1692 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1693 {
1694         MLX5_SET(tirc, tirc, rx_hash_fn,
1695                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1696         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1697                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1698                                              rx_hash_toeplitz_key);
1699                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1700                                                rx_hash_toeplitz_key);
1701
1702                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1703                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1704         }
1705 }
1706
1707 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1708 {
1709         struct mlx5_core_dev *mdev = priv->mdev;
1710
1711         void *in;
1712         void *tirc;
1713         int inlen;
1714         int err;
1715         int tt;
1716         int ix;
1717
1718         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1719         in = mlx5_vzalloc(inlen);
1720         if (!in)
1721                 return -ENOMEM;
1722
1723         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1724         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1725
1726         mlx5e_build_tir_ctx_lro(tirc, priv);
1727
1728         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1729                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1730                                            inlen);
1731                 if (err)
1732                         goto free_in;
1733         }
1734
1735         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1736                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1737                                            in, inlen);
1738                 if (err)
1739                         goto free_in;
1740         }
1741
1742 free_in:
1743         kvfree(in);
1744
1745         return err;
1746 }
1747
1748 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1749 {
1750         struct mlx5_core_dev *mdev = priv->mdev;
1751         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1752         int err;
1753
1754         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1755         if (err)
1756                 return err;
1757
1758         /* Update vport context MTU */
1759         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1760         return 0;
1761 }
1762
1763 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1764 {
1765         struct mlx5_core_dev *mdev = priv->mdev;
1766         u16 hw_mtu = 0;
1767         int err;
1768
1769         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1770         if (err || !hw_mtu) /* fallback to port oper mtu */
1771                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1772
1773         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1774 }
1775
1776 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1777 {
1778         struct mlx5e_priv *priv = netdev_priv(netdev);
1779         u16 mtu;
1780         int err;
1781
1782         err = mlx5e_set_mtu(priv, netdev->mtu);
1783         if (err)
1784                 return err;
1785
1786         mlx5e_query_mtu(priv, &mtu);
1787         if (mtu != netdev->mtu)
1788                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1789                             __func__, mtu, netdev->mtu);
1790
1791         netdev->mtu = mtu;
1792         return 0;
1793 }
1794
1795 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1796 {
1797         struct mlx5e_priv *priv = netdev_priv(netdev);
1798         int nch = priv->params.num_channels;
1799         int ntc = priv->params.num_tc;
1800         int tc;
1801
1802         netdev_reset_tc(netdev);
1803
1804         if (ntc == 1)
1805                 return;
1806
1807         netdev_set_num_tc(netdev, ntc);
1808
1809         /* Map netdev TCs to offset 0
1810          * We have our own UP to TXQ mapping for QoS
1811          */
1812         for (tc = 0; tc < ntc; tc++)
1813                 netdev_set_tc_queue(netdev, tc, nch, 0);
1814 }
1815
1816 int mlx5e_open_locked(struct net_device *netdev)
1817 {
1818         struct mlx5e_priv *priv = netdev_priv(netdev);
1819         struct mlx5_core_dev *mdev = priv->mdev;
1820         int num_txqs;
1821         int err;
1822
1823         set_bit(MLX5E_STATE_OPENED, &priv->state);
1824
1825         mlx5e_netdev_set_tcs(netdev);
1826
1827         num_txqs = priv->params.num_channels * priv->params.num_tc;
1828         netif_set_real_num_tx_queues(netdev, num_txqs);
1829         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1830
1831         err = mlx5e_open_channels(priv);
1832         if (err) {
1833                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1834                            __func__, err);
1835                 goto err_clear_state_opened_flag;
1836         }
1837
1838         err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
1839         if (err) {
1840                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1841                            __func__, err);
1842                 goto err_close_channels;
1843         }
1844
1845         mlx5e_redirect_rqts(priv);
1846         mlx5e_update_carrier(priv);
1847         mlx5e_timestamp_init(priv);
1848 #ifdef CONFIG_RFS_ACCEL
1849         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1850 #endif
1851         if (priv->profile->update_stats)
1852                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1853
1854         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
1855                 err = mlx5e_add_sqs_fwd_rules(priv);
1856                 if (err)
1857                         goto err_close_channels;
1858         }
1859         return 0;
1860
1861 err_close_channels:
1862         mlx5e_close_channels(priv);
1863 err_clear_state_opened_flag:
1864         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1865         return err;
1866 }
1867
1868 int mlx5e_open(struct net_device *netdev)
1869 {
1870         struct mlx5e_priv *priv = netdev_priv(netdev);
1871         int err;
1872
1873         mutex_lock(&priv->state_lock);
1874         err = mlx5e_open_locked(netdev);
1875         mutex_unlock(&priv->state_lock);
1876
1877         return err;
1878 }
1879
1880 int mlx5e_close_locked(struct net_device *netdev)
1881 {
1882         struct mlx5e_priv *priv = netdev_priv(netdev);
1883         struct mlx5_core_dev *mdev = priv->mdev;
1884
1885         /* May already be CLOSED in case a previous configuration operation
1886          * (e.g RX/TX queue size change) that involves close&open failed.
1887          */
1888         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1889                 return 0;
1890
1891         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1892
1893         if (MLX5_CAP_GEN(mdev, vport_group_manager))
1894                 mlx5e_remove_sqs_fwd_rules(priv);
1895
1896         mlx5e_timestamp_cleanup(priv);
1897         netif_carrier_off(priv->netdev);
1898         mlx5e_redirect_rqts(priv);
1899         mlx5e_close_channels(priv);
1900
1901         return 0;
1902 }
1903
1904 int mlx5e_close(struct net_device *netdev)
1905 {
1906         struct mlx5e_priv *priv = netdev_priv(netdev);
1907         int err;
1908
1909         mutex_lock(&priv->state_lock);
1910         err = mlx5e_close_locked(netdev);
1911         mutex_unlock(&priv->state_lock);
1912
1913         return err;
1914 }
1915
1916 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1917                                 struct mlx5e_rq *rq,
1918                                 struct mlx5e_rq_param *param)
1919 {
1920         struct mlx5_core_dev *mdev = priv->mdev;
1921         void *rqc = param->rqc;
1922         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1923         int err;
1924
1925         param->wq.db_numa_node = param->wq.buf_numa_node;
1926
1927         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1928                                 &rq->wq_ctrl);
1929         if (err)
1930                 return err;
1931
1932         rq->priv = priv;
1933
1934         return 0;
1935 }
1936
1937 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1938                                 struct mlx5e_cq *cq,
1939                                 struct mlx5e_cq_param *param)
1940 {
1941         struct mlx5_core_dev *mdev = priv->mdev;
1942         struct mlx5_core_cq *mcq = &cq->mcq;
1943         int eqn_not_used;
1944         unsigned int irqn;
1945         int err;
1946
1947         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1948                                &cq->wq_ctrl);
1949         if (err)
1950                 return err;
1951
1952         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1953
1954         mcq->cqe_sz     = 64;
1955         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1956         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1957         *mcq->set_ci_db = 0;
1958         *mcq->arm_db    = 0;
1959         mcq->vector     = param->eq_ix;
1960         mcq->comp       = mlx5e_completion_event;
1961         mcq->event      = mlx5e_cq_error_event;
1962         mcq->irqn       = irqn;
1963         mcq->uar        = &mdev->mlx5e_res.cq_uar;
1964
1965         cq->priv = priv;
1966
1967         return 0;
1968 }
1969
1970 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1971 {
1972         struct mlx5e_cq_param cq_param;
1973         struct mlx5e_rq_param rq_param;
1974         struct mlx5e_rq *rq = &priv->drop_rq;
1975         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1976         int err;
1977
1978         memset(&cq_param, 0, sizeof(cq_param));
1979         memset(&rq_param, 0, sizeof(rq_param));
1980         mlx5e_build_drop_rq_param(&rq_param);
1981
1982         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1983         if (err)
1984                 return err;
1985
1986         err = mlx5e_enable_cq(cq, &cq_param);
1987         if (err)
1988                 goto err_destroy_cq;
1989
1990         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1991         if (err)
1992                 goto err_disable_cq;
1993
1994         err = mlx5e_enable_rq(rq, &rq_param);
1995         if (err)
1996                 goto err_destroy_rq;
1997
1998         return 0;
1999
2000 err_destroy_rq:
2001         mlx5e_destroy_rq(&priv->drop_rq);
2002
2003 err_disable_cq:
2004         mlx5e_disable_cq(&priv->drop_rq.cq);
2005
2006 err_destroy_cq:
2007         mlx5e_destroy_cq(&priv->drop_rq.cq);
2008
2009         return err;
2010 }
2011
2012 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2013 {
2014         mlx5e_disable_rq(&priv->drop_rq);
2015         mlx5e_destroy_rq(&priv->drop_rq);
2016         mlx5e_disable_cq(&priv->drop_rq.cq);
2017         mlx5e_destroy_cq(&priv->drop_rq.cq);
2018 }
2019
2020 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2021 {
2022         struct mlx5_core_dev *mdev = priv->mdev;
2023         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2024         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2025
2026         memset(in, 0, sizeof(in));
2027
2028         MLX5_SET(tisc, tisc, prio, tc << 1);
2029         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2030
2031         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2032 }
2033
2034 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2035 {
2036         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2037 }
2038
2039 int mlx5e_create_tises(struct mlx5e_priv *priv)
2040 {
2041         int err;
2042         int tc;
2043
2044         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2045                 err = mlx5e_create_tis(priv, tc);
2046                 if (err)
2047                         goto err_close_tises;
2048         }
2049
2050         return 0;
2051
2052 err_close_tises:
2053         for (tc--; tc >= 0; tc--)
2054                 mlx5e_destroy_tis(priv, tc);
2055
2056         return err;
2057 }
2058
2059 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2060 {
2061         int tc;
2062
2063         for (tc = 0; tc < priv->profile->max_tc; tc++)
2064                 mlx5e_destroy_tis(priv, tc);
2065 }
2066
2067 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2068                                       enum mlx5e_traffic_types tt)
2069 {
2070         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2071
2072         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2073
2074 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2075                                  MLX5_HASH_FIELD_SEL_DST_IP)
2076
2077 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2078                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2079                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2080                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2081
2082 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2083                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2084                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2085
2086         mlx5e_build_tir_ctx_lro(tirc, priv);
2087
2088         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2089         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2090         mlx5e_build_tir_ctx_hash(tirc, priv);
2091
2092         switch (tt) {
2093         case MLX5E_TT_IPV4_TCP:
2094                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2095                          MLX5_L3_PROT_TYPE_IPV4);
2096                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2097                          MLX5_L4_PROT_TYPE_TCP);
2098                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2099                          MLX5_HASH_IP_L4PORTS);
2100                 break;
2101
2102         case MLX5E_TT_IPV6_TCP:
2103                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2104                          MLX5_L3_PROT_TYPE_IPV6);
2105                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2106                          MLX5_L4_PROT_TYPE_TCP);
2107                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2108                          MLX5_HASH_IP_L4PORTS);
2109                 break;
2110
2111         case MLX5E_TT_IPV4_UDP:
2112                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2113                          MLX5_L3_PROT_TYPE_IPV4);
2114                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2115                          MLX5_L4_PROT_TYPE_UDP);
2116                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2117                          MLX5_HASH_IP_L4PORTS);
2118                 break;
2119
2120         case MLX5E_TT_IPV6_UDP:
2121                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2122                          MLX5_L3_PROT_TYPE_IPV6);
2123                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2124                          MLX5_L4_PROT_TYPE_UDP);
2125                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2126                          MLX5_HASH_IP_L4PORTS);
2127                 break;
2128
2129         case MLX5E_TT_IPV4_IPSEC_AH:
2130                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2131                          MLX5_L3_PROT_TYPE_IPV4);
2132                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2133                          MLX5_HASH_IP_IPSEC_SPI);
2134                 break;
2135
2136         case MLX5E_TT_IPV6_IPSEC_AH:
2137                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2138                          MLX5_L3_PROT_TYPE_IPV6);
2139                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2140                          MLX5_HASH_IP_IPSEC_SPI);
2141                 break;
2142
2143         case MLX5E_TT_IPV4_IPSEC_ESP:
2144                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2145                          MLX5_L3_PROT_TYPE_IPV4);
2146                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2147                          MLX5_HASH_IP_IPSEC_SPI);
2148                 break;
2149
2150         case MLX5E_TT_IPV6_IPSEC_ESP:
2151                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2152                          MLX5_L3_PROT_TYPE_IPV6);
2153                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2154                          MLX5_HASH_IP_IPSEC_SPI);
2155                 break;
2156
2157         case MLX5E_TT_IPV4:
2158                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2159                          MLX5_L3_PROT_TYPE_IPV4);
2160                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2161                          MLX5_HASH_IP);
2162                 break;
2163
2164         case MLX5E_TT_IPV6:
2165                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2166                          MLX5_L3_PROT_TYPE_IPV6);
2167                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2168                          MLX5_HASH_IP);
2169                 break;
2170         default:
2171                 WARN_ONCE(true,
2172                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2173         }
2174 }
2175
2176 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2177                                        u32 rqtn)
2178 {
2179         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2180
2181         mlx5e_build_tir_ctx_lro(tirc, priv);
2182
2183         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2184         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2185         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2186 }
2187
2188 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2189 {
2190         struct mlx5e_tir *tir;
2191         void *tirc;
2192         int inlen;
2193         int err;
2194         u32 *in;
2195         int tt;
2196
2197         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2198         in = mlx5_vzalloc(inlen);
2199         if (!in)
2200                 return -ENOMEM;
2201
2202         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2203                 memset(in, 0, inlen);
2204                 tir = &priv->indir_tir[tt];
2205                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2206                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2207                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2208                 if (err)
2209                         goto err_destroy_tirs;
2210         }
2211
2212         kvfree(in);
2213
2214         return 0;
2215
2216 err_destroy_tirs:
2217         for (tt--; tt >= 0; tt--)
2218                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2219
2220         kvfree(in);
2221
2222         return err;
2223 }
2224
2225 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2226 {
2227         int nch = priv->profile->max_nch(priv->mdev);
2228         struct mlx5e_tir *tir;
2229         void *tirc;
2230         int inlen;
2231         int err;
2232         u32 *in;
2233         int ix;
2234
2235         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2236         in = mlx5_vzalloc(inlen);
2237         if (!in)
2238                 return -ENOMEM;
2239
2240         for (ix = 0; ix < nch; ix++) {
2241                 memset(in, 0, inlen);
2242                 tir = &priv->direct_tir[ix];
2243                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2244                 mlx5e_build_direct_tir_ctx(priv, tirc,
2245                                            priv->direct_tir[ix].rqt.rqtn);
2246                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2247                 if (err)
2248                         goto err_destroy_ch_tirs;
2249         }
2250
2251         kvfree(in);
2252
2253         return 0;
2254
2255 err_destroy_ch_tirs:
2256         for (ix--; ix >= 0; ix--)
2257                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2258
2259         kvfree(in);
2260
2261         return err;
2262 }
2263
2264 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2265 {
2266         int i;
2267
2268         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2269                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2270 }
2271
2272 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2273 {
2274         int nch = priv->profile->max_nch(priv->mdev);
2275         int i;
2276
2277         for (i = 0; i < nch; i++)
2278                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2279 }
2280
2281 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2282 {
2283         int err = 0;
2284         int i;
2285
2286         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2287                 return 0;
2288
2289         for (i = 0; i < priv->params.num_channels; i++) {
2290                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2291                 if (err)
2292                         return err;
2293         }
2294
2295         return 0;
2296 }
2297
2298 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2299 {
2300         struct mlx5e_priv *priv = netdev_priv(netdev);
2301         bool was_opened;
2302         int err = 0;
2303
2304         if (tc && tc != MLX5E_MAX_NUM_TC)
2305                 return -EINVAL;
2306
2307         mutex_lock(&priv->state_lock);
2308
2309         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2310         if (was_opened)
2311                 mlx5e_close_locked(priv->netdev);
2312
2313         priv->params.num_tc = tc ? tc : 1;
2314
2315         if (was_opened)
2316                 err = mlx5e_open_locked(priv->netdev);
2317
2318         mutex_unlock(&priv->state_lock);
2319
2320         return err;
2321 }
2322
2323 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2324                               __be16 proto, struct tc_to_netdev *tc)
2325 {
2326         struct mlx5e_priv *priv = netdev_priv(dev);
2327
2328         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2329                 goto mqprio;
2330
2331         switch (tc->type) {
2332         case TC_SETUP_CLSFLOWER:
2333                 switch (tc->cls_flower->command) {
2334                 case TC_CLSFLOWER_REPLACE:
2335                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2336                 case TC_CLSFLOWER_DESTROY:
2337                         return mlx5e_delete_flower(priv, tc->cls_flower);
2338                 case TC_CLSFLOWER_STATS:
2339                         return mlx5e_stats_flower(priv, tc->cls_flower);
2340                 }
2341         default:
2342                 return -EOPNOTSUPP;
2343         }
2344
2345 mqprio:
2346         if (tc->type != TC_SETUP_MQPRIO)
2347                 return -EINVAL;
2348
2349         return mlx5e_setup_tc(dev, tc->tc);
2350 }
2351
2352 struct rtnl_link_stats64 *
2353 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2354 {
2355         struct mlx5e_priv *priv = netdev_priv(dev);
2356         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2357         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2358         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2359
2360         stats->rx_packets = sstats->rx_packets;
2361         stats->rx_bytes   = sstats->rx_bytes;
2362         stats->tx_packets = sstats->tx_packets;
2363         stats->tx_bytes   = sstats->tx_bytes;
2364
2365         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2366         stats->tx_dropped = sstats->tx_queue_dropped;
2367
2368         stats->rx_length_errors =
2369                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2370                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2371                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2372         stats->rx_crc_errors =
2373                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2374         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2375         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2376         stats->tx_carrier_errors =
2377                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2378         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2379                            stats->rx_frame_errors;
2380         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2381
2382         /* vport multicast also counts packets that are dropped due to steering
2383          * or rx out of buffer
2384          */
2385         stats->multicast =
2386                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2387
2388         return stats;
2389 }
2390
2391 static void mlx5e_set_rx_mode(struct net_device *dev)
2392 {
2393         struct mlx5e_priv *priv = netdev_priv(dev);
2394
2395         queue_work(priv->wq, &priv->set_rx_mode_work);
2396 }
2397
2398 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2399 {
2400         struct mlx5e_priv *priv = netdev_priv(netdev);
2401         struct sockaddr *saddr = addr;
2402
2403         if (!is_valid_ether_addr(saddr->sa_data))
2404                 return -EADDRNOTAVAIL;
2405
2406         netif_addr_lock_bh(netdev);
2407         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2408         netif_addr_unlock_bh(netdev);
2409
2410         queue_work(priv->wq, &priv->set_rx_mode_work);
2411
2412         return 0;
2413 }
2414
2415 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2416         do {                                            \
2417                 if (enable)                             \
2418                         netdev->features |= feature;    \
2419                 else                                    \
2420                         netdev->features &= ~feature;   \
2421         } while (0)
2422
2423 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2424
2425 static int set_feature_lro(struct net_device *netdev, bool enable)
2426 {
2427         struct mlx5e_priv *priv = netdev_priv(netdev);
2428         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2429         int err;
2430
2431         mutex_lock(&priv->state_lock);
2432
2433         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2434                 mlx5e_close_locked(priv->netdev);
2435
2436         priv->params.lro_en = enable;
2437         err = mlx5e_modify_tirs_lro(priv);
2438         if (err) {
2439                 netdev_err(netdev, "lro modify failed, %d\n", err);
2440                 priv->params.lro_en = !enable;
2441         }
2442
2443         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2444                 mlx5e_open_locked(priv->netdev);
2445
2446         mutex_unlock(&priv->state_lock);
2447
2448         return err;
2449 }
2450
2451 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2452 {
2453         struct mlx5e_priv *priv = netdev_priv(netdev);
2454
2455         if (enable)
2456                 mlx5e_enable_vlan_filter(priv);
2457         else
2458                 mlx5e_disable_vlan_filter(priv);
2459
2460         return 0;
2461 }
2462
2463 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2464 {
2465         struct mlx5e_priv *priv = netdev_priv(netdev);
2466
2467         if (!enable && mlx5e_tc_num_filters(priv)) {
2468                 netdev_err(netdev,
2469                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2470                 return -EINVAL;
2471         }
2472
2473         return 0;
2474 }
2475
2476 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2477 {
2478         struct mlx5e_priv *priv = netdev_priv(netdev);
2479         struct mlx5_core_dev *mdev = priv->mdev;
2480
2481         return mlx5_set_port_fcs(mdev, !enable);
2482 }
2483
2484 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2485 {
2486         struct mlx5e_priv *priv = netdev_priv(netdev);
2487         int err;
2488
2489         mutex_lock(&priv->state_lock);
2490
2491         priv->params.vlan_strip_disable = !enable;
2492         err = mlx5e_modify_rqs_vsd(priv, !enable);
2493         if (err)
2494                 priv->params.vlan_strip_disable = enable;
2495
2496         mutex_unlock(&priv->state_lock);
2497
2498         return err;
2499 }
2500
2501 #ifdef CONFIG_RFS_ACCEL
2502 static int set_feature_arfs(struct net_device *netdev, bool enable)
2503 {
2504         struct mlx5e_priv *priv = netdev_priv(netdev);
2505         int err;
2506
2507         if (enable)
2508                 err = mlx5e_arfs_enable(priv);
2509         else
2510                 err = mlx5e_arfs_disable(priv);
2511
2512         return err;
2513 }
2514 #endif
2515
2516 static int mlx5e_handle_feature(struct net_device *netdev,
2517                                 netdev_features_t wanted_features,
2518                                 netdev_features_t feature,
2519                                 mlx5e_feature_handler feature_handler)
2520 {
2521         netdev_features_t changes = wanted_features ^ netdev->features;
2522         bool enable = !!(wanted_features & feature);
2523         int err;
2524
2525         if (!(changes & feature))
2526                 return 0;
2527
2528         err = feature_handler(netdev, enable);
2529         if (err) {
2530                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2531                            enable ? "Enable" : "Disable", feature, err);
2532                 return err;
2533         }
2534
2535         MLX5E_SET_FEATURE(netdev, feature, enable);
2536         return 0;
2537 }
2538
2539 static int mlx5e_set_features(struct net_device *netdev,
2540                               netdev_features_t features)
2541 {
2542         int err;
2543
2544         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2545                                     set_feature_lro);
2546         err |= mlx5e_handle_feature(netdev, features,
2547                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2548                                     set_feature_vlan_filter);
2549         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2550                                     set_feature_tc_num_filters);
2551         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2552                                     set_feature_rx_all);
2553         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2554                                     set_feature_rx_vlan);
2555 #ifdef CONFIG_RFS_ACCEL
2556         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2557                                     set_feature_arfs);
2558 #endif
2559
2560         return err ? -EINVAL : 0;
2561 }
2562
2563 #define MXL5_HW_MIN_MTU 64
2564 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2565
2566 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2567 {
2568         struct mlx5e_priv *priv = netdev_priv(netdev);
2569         struct mlx5_core_dev *mdev = priv->mdev;
2570         bool was_opened;
2571         u16 max_mtu;
2572         u16 min_mtu;
2573         int err = 0;
2574         bool reset;
2575
2576         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2577
2578         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2579         min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2580
2581         if (new_mtu > max_mtu || new_mtu < min_mtu) {
2582                 netdev_err(netdev,
2583                            "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2584                            __func__, new_mtu, min_mtu, max_mtu);
2585                 return -EINVAL;
2586         }
2587
2588         mutex_lock(&priv->state_lock);
2589
2590         reset = !priv->params.lro_en &&
2591                 (priv->params.rq_wq_type !=
2592                  MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2593
2594         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2595         if (was_opened && reset)
2596                 mlx5e_close_locked(netdev);
2597
2598         netdev->mtu = new_mtu;
2599         mlx5e_set_dev_port_mtu(netdev);
2600
2601         if (was_opened && reset)
2602                 err = mlx5e_open_locked(netdev);
2603
2604         mutex_unlock(&priv->state_lock);
2605
2606         return err;
2607 }
2608
2609 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2610 {
2611         switch (cmd) {
2612         case SIOCSHWTSTAMP:
2613                 return mlx5e_hwstamp_set(dev, ifr);
2614         case SIOCGHWTSTAMP:
2615                 return mlx5e_hwstamp_get(dev, ifr);
2616         default:
2617                 return -EOPNOTSUPP;
2618         }
2619 }
2620
2621 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2622 {
2623         struct mlx5e_priv *priv = netdev_priv(dev);
2624         struct mlx5_core_dev *mdev = priv->mdev;
2625
2626         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2627 }
2628
2629 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2630 {
2631         struct mlx5e_priv *priv = netdev_priv(dev);
2632         struct mlx5_core_dev *mdev = priv->mdev;
2633
2634         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2635                                            vlan, qos);
2636 }
2637
2638 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2639 {
2640         struct mlx5e_priv *priv = netdev_priv(dev);
2641         struct mlx5_core_dev *mdev = priv->mdev;
2642
2643         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2644 }
2645
2646 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2647 {
2648         struct mlx5e_priv *priv = netdev_priv(dev);
2649         struct mlx5_core_dev *mdev = priv->mdev;
2650
2651         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2652 }
2653 static int mlx5_vport_link2ifla(u8 esw_link)
2654 {
2655         switch (esw_link) {
2656         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2657                 return IFLA_VF_LINK_STATE_DISABLE;
2658         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2659                 return IFLA_VF_LINK_STATE_ENABLE;
2660         }
2661         return IFLA_VF_LINK_STATE_AUTO;
2662 }
2663
2664 static int mlx5_ifla_link2vport(u8 ifla_link)
2665 {
2666         switch (ifla_link) {
2667         case IFLA_VF_LINK_STATE_DISABLE:
2668                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2669         case IFLA_VF_LINK_STATE_ENABLE:
2670                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2671         }
2672         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2673 }
2674
2675 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2676                                    int link_state)
2677 {
2678         struct mlx5e_priv *priv = netdev_priv(dev);
2679         struct mlx5_core_dev *mdev = priv->mdev;
2680
2681         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2682                                             mlx5_ifla_link2vport(link_state));
2683 }
2684
2685 static int mlx5e_get_vf_config(struct net_device *dev,
2686                                int vf, struct ifla_vf_info *ivi)
2687 {
2688         struct mlx5e_priv *priv = netdev_priv(dev);
2689         struct mlx5_core_dev *mdev = priv->mdev;
2690         int err;
2691
2692         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2693         if (err)
2694                 return err;
2695         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2696         return 0;
2697 }
2698
2699 static int mlx5e_get_vf_stats(struct net_device *dev,
2700                               int vf, struct ifla_vf_stats *vf_stats)
2701 {
2702         struct mlx5e_priv *priv = netdev_priv(dev);
2703         struct mlx5_core_dev *mdev = priv->mdev;
2704
2705         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2706                                             vf_stats);
2707 }
2708
2709 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2710                                  struct udp_tunnel_info *ti)
2711 {
2712         struct mlx5e_priv *priv = netdev_priv(netdev);
2713
2714         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2715                 return;
2716
2717         if (!mlx5e_vxlan_allowed(priv->mdev))
2718                 return;
2719
2720         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
2721 }
2722
2723 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2724                                  struct udp_tunnel_info *ti)
2725 {
2726         struct mlx5e_priv *priv = netdev_priv(netdev);
2727
2728         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2729                 return;
2730
2731         if (!mlx5e_vxlan_allowed(priv->mdev))
2732                 return;
2733
2734         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
2735 }
2736
2737 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2738                                                     struct sk_buff *skb,
2739                                                     netdev_features_t features)
2740 {
2741         struct udphdr *udph;
2742         u16 proto;
2743         u16 port = 0;
2744
2745         switch (vlan_get_protocol(skb)) {
2746         case htons(ETH_P_IP):
2747                 proto = ip_hdr(skb)->protocol;
2748                 break;
2749         case htons(ETH_P_IPV6):
2750                 proto = ipv6_hdr(skb)->nexthdr;
2751                 break;
2752         default:
2753                 goto out;
2754         }
2755
2756         if (proto == IPPROTO_UDP) {
2757                 udph = udp_hdr(skb);
2758                 port = be16_to_cpu(udph->dest);
2759         }
2760
2761         /* Verify if UDP port is being offloaded by HW */
2762         if (port && mlx5e_vxlan_lookup_port(priv, port))
2763                 return features;
2764
2765 out:
2766         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2767         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2768 }
2769
2770 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2771                                               struct net_device *netdev,
2772                                               netdev_features_t features)
2773 {
2774         struct mlx5e_priv *priv = netdev_priv(netdev);
2775
2776         features = vlan_features_check(skb, features);
2777         features = vxlan_features_check(skb, features);
2778
2779         /* Validate if the tunneled packet is being offloaded by HW */
2780         if (skb->encapsulation &&
2781             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2782                 return mlx5e_vxlan_features_check(priv, skb, features);
2783
2784         return features;
2785 }
2786
2787 static void mlx5e_tx_timeout(struct net_device *dev)
2788 {
2789         struct mlx5e_priv *priv = netdev_priv(dev);
2790         bool sched_work = false;
2791         int i;
2792
2793         netdev_err(dev, "TX timeout detected\n");
2794
2795         for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
2796                 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
2797
2798                 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
2799                         continue;
2800                 sched_work = true;
2801                 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
2802                 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
2803                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
2804         }
2805
2806         if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
2807                 schedule_work(&priv->tx_timeout_work);
2808 }
2809
2810 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2811         .ndo_open                = mlx5e_open,
2812         .ndo_stop                = mlx5e_close,
2813         .ndo_start_xmit          = mlx5e_xmit,
2814         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2815         .ndo_select_queue        = mlx5e_select_queue,
2816         .ndo_get_stats64         = mlx5e_get_stats,
2817         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2818         .ndo_set_mac_address     = mlx5e_set_mac,
2819         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2820         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2821         .ndo_set_features        = mlx5e_set_features,
2822         .ndo_change_mtu          = mlx5e_change_mtu,
2823         .ndo_do_ioctl            = mlx5e_ioctl,
2824         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
2825 #ifdef CONFIG_RFS_ACCEL
2826         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2827 #endif
2828         .ndo_tx_timeout          = mlx5e_tx_timeout,
2829 };
2830
2831 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2832         .ndo_open                = mlx5e_open,
2833         .ndo_stop                = mlx5e_close,
2834         .ndo_start_xmit          = mlx5e_xmit,
2835         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2836         .ndo_select_queue        = mlx5e_select_queue,
2837         .ndo_get_stats64         = mlx5e_get_stats,
2838         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2839         .ndo_set_mac_address     = mlx5e_set_mac,
2840         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2841         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2842         .ndo_set_features        = mlx5e_set_features,
2843         .ndo_change_mtu          = mlx5e_change_mtu,
2844         .ndo_do_ioctl            = mlx5e_ioctl,
2845         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
2846         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
2847         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
2848         .ndo_features_check      = mlx5e_features_check,
2849 #ifdef CONFIG_RFS_ACCEL
2850         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2851 #endif
2852         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2853         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2854         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
2855         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
2856         .ndo_get_vf_config       = mlx5e_get_vf_config,
2857         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2858         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2859         .ndo_tx_timeout          = mlx5e_tx_timeout,
2860 };
2861
2862 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2863 {
2864         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2865                 return -ENOTSUPP;
2866         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2867             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2868             !MLX5_CAP_ETH(mdev, csum_cap) ||
2869             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2870             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2871             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2872             MLX5_CAP_FLOWTABLE(mdev,
2873                                flow_table_properties_nic_receive.max_ft_level)
2874                                < 3) {
2875                 mlx5_core_warn(mdev,
2876                                "Not creating net device, some required device capabilities are missing\n");
2877                 return -ENOTSUPP;
2878         }
2879         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2880                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2881         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2882                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2883
2884         return 0;
2885 }
2886
2887 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2888 {
2889         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2890
2891         return bf_buf_size -
2892                sizeof(struct mlx5e_tx_wqe) +
2893                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2894 }
2895
2896 #ifdef CONFIG_MLX5_CORE_EN_DCB
2897 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2898 {
2899         int i;
2900
2901         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2902         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2903                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2904                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2905                 priv->params.ets.prio_tc[i] = i;
2906         }
2907
2908         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2909         priv->params.ets.prio_tc[0] = 1;
2910         priv->params.ets.prio_tc[1] = 0;
2911 }
2912 #endif
2913
2914 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2915                                    u32 *indirection_rqt, int len,
2916                                    int num_channels)
2917 {
2918         int node = mdev->priv.numa_node;
2919         int node_num_of_cores;
2920         int i;
2921
2922         if (node == -1)
2923                 node = first_online_node;
2924
2925         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2926
2927         if (node_num_of_cores)
2928                 num_channels = min_t(int, num_channels, node_num_of_cores);
2929
2930         for (i = 0; i < len; i++)
2931                 indirection_rqt[i] = i % num_channels;
2932 }
2933
2934 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2935 {
2936         return MLX5_CAP_GEN(mdev, striding_rq) &&
2937                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2938                 MLX5_CAP_ETH(mdev, reg_umr_sq);
2939 }
2940
2941 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2942 {
2943         enum pcie_link_width width;
2944         enum pci_bus_speed speed;
2945         int err = 0;
2946
2947         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2948         if (err)
2949                 return err;
2950
2951         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2952                 return -EINVAL;
2953
2954         switch (speed) {
2955         case PCIE_SPEED_2_5GT:
2956                 *pci_bw = 2500 * width;
2957                 break;
2958         case PCIE_SPEED_5_0GT:
2959                 *pci_bw = 5000 * width;
2960                 break;
2961         case PCIE_SPEED_8_0GT:
2962                 *pci_bw = 8000 * width;
2963                 break;
2964         default:
2965                 return -EINVAL;
2966         }
2967
2968         return 0;
2969 }
2970
2971 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2972 {
2973         return (link_speed && pci_bw &&
2974                 (pci_bw < 40000) && (pci_bw < link_speed));
2975 }
2976
2977 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
2978 {
2979         params->rx_cq_period_mode = cq_period_mode;
2980
2981         params->rx_cq_moderation.pkts =
2982                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2983         params->rx_cq_moderation.usec =
2984                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2985
2986         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
2987                 params->rx_cq_moderation.usec =
2988                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
2989 }
2990
2991 static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
2992                                    u8 *min_inline_mode)
2993 {
2994         switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
2995         case MLX5E_INLINE_MODE_L2:
2996                 *min_inline_mode = MLX5_INLINE_MODE_L2;
2997                 break;
2998         case MLX5E_INLINE_MODE_VPORT_CONTEXT:
2999                 mlx5_query_nic_vport_min_inline(mdev,
3000                                                 min_inline_mode);
3001                 break;
3002         case MLX5_INLINE_MODE_NOT_REQUIRED:
3003                 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3004                 break;
3005         }
3006 }
3007
3008 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3009                                         struct net_device *netdev,
3010                                         const struct mlx5e_profile *profile,
3011                                         void *ppriv)
3012 {
3013         struct mlx5e_priv *priv = netdev_priv(netdev);
3014         u32 link_speed = 0;
3015         u32 pci_bw = 0;
3016         u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3017                                          MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3018                                          MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3019
3020         priv->params.log_sq_size           =
3021                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3022         priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
3023                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
3024                 MLX5_WQ_TYPE_LINKED_LIST;
3025
3026         /* set CQE compression */
3027         priv->params.rx_cqe_compress_admin = false;
3028         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3029             MLX5_CAP_GEN(mdev, vport_group_manager)) {
3030                 mlx5e_get_max_linkspeed(mdev, &link_speed);
3031                 mlx5e_get_pci_bw(mdev, &pci_bw);
3032                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3033                               link_speed, pci_bw);
3034                 priv->params.rx_cqe_compress_admin =
3035                         cqe_compress_heuristic(link_speed, pci_bw);
3036         }
3037
3038         priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3039
3040         switch (priv->params.rq_wq_type) {
3041         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
3042                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
3043                 priv->params.mpwqe_log_stride_sz =
3044                         priv->params.rx_cqe_compress ?
3045                         MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
3046                         MLX5_MPWRQ_LOG_STRIDE_SIZE;
3047                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
3048                         priv->params.mpwqe_log_stride_sz;
3049                 priv->params.lro_en = true;
3050                 break;
3051         default: /* MLX5_WQ_TYPE_LINKED_LIST */
3052                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3053         }
3054
3055         mlx5_core_info(mdev,
3056                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
3057                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
3058                        BIT(priv->params.log_rq_size),
3059                        BIT(priv->params.mpwqe_log_stride_sz),
3060                        priv->params.rx_cqe_compress_admin);
3061
3062         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
3063                                             BIT(priv->params.log_rq_size));
3064
3065         priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3066         mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3067
3068         priv->params.tx_cq_moderation.usec =
3069                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3070         priv->params.tx_cq_moderation.pkts =
3071                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3072         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
3073         mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3074         priv->params.num_tc                = 1;
3075         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
3076
3077         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3078                             sizeof(priv->params.toeplitz_hash_key));
3079
3080         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3081                                       MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3082
3083         priv->params.lro_wqe_sz            =
3084                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3085
3086         /* Initialize pflags */
3087         MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3088                             priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3089
3090         priv->mdev                         = mdev;
3091         priv->netdev                       = netdev;
3092         priv->params.num_channels          = profile->max_nch(mdev);
3093         priv->profile                      = profile;
3094         priv->ppriv                        = ppriv;
3095
3096 #ifdef CONFIG_MLX5_CORE_EN_DCB
3097         mlx5e_ets_init(priv);
3098 #endif
3099
3100         mutex_init(&priv->state_lock);
3101
3102         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3103         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3104         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3105         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3106 }
3107
3108 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3109 {
3110         struct mlx5e_priv *priv = netdev_priv(netdev);
3111
3112         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3113         if (is_zero_ether_addr(netdev->dev_addr) &&
3114             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3115                 eth_hw_addr_random(netdev);
3116                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3117         }
3118 }
3119
3120 static const struct switchdev_ops mlx5e_switchdev_ops = {
3121         .switchdev_port_attr_get        = mlx5e_attr_get,
3122 };
3123
3124 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3125 {
3126         struct mlx5e_priv *priv = netdev_priv(netdev);
3127         struct mlx5_core_dev *mdev = priv->mdev;
3128         bool fcs_supported;
3129         bool fcs_enabled;
3130
3131         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3132
3133         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3134                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3135 #ifdef CONFIG_MLX5_CORE_EN_DCB
3136                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3137 #endif
3138         } else {
3139                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3140         }
3141
3142         netdev->watchdog_timeo    = 15 * HZ;
3143
3144         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
3145
3146         netdev->vlan_features    |= NETIF_F_SG;
3147         netdev->vlan_features    |= NETIF_F_IP_CSUM;
3148         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
3149         netdev->vlan_features    |= NETIF_F_GRO;
3150         netdev->vlan_features    |= NETIF_F_TSO;
3151         netdev->vlan_features    |= NETIF_F_TSO6;
3152         netdev->vlan_features    |= NETIF_F_RXCSUM;
3153         netdev->vlan_features    |= NETIF_F_RXHASH;
3154
3155         if (!!MLX5_CAP_ETH(mdev, lro_cap))
3156                 netdev->vlan_features    |= NETIF_F_LRO;
3157
3158         netdev->hw_features       = netdev->vlan_features;
3159         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
3160         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
3161         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
3162
3163         if (mlx5e_vxlan_allowed(mdev)) {
3164                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
3165                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
3166                                            NETIF_F_GSO_PARTIAL;
3167                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3168                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3169                 netdev->hw_enc_features |= NETIF_F_TSO;
3170                 netdev->hw_enc_features |= NETIF_F_TSO6;
3171                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3172                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3173                                            NETIF_F_GSO_PARTIAL;
3174                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3175         }
3176
3177         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3178
3179         if (fcs_supported)
3180                 netdev->hw_features |= NETIF_F_RXALL;
3181
3182         netdev->features          = netdev->hw_features;
3183         if (!priv->params.lro_en)
3184                 netdev->features  &= ~NETIF_F_LRO;
3185
3186         if (fcs_enabled)
3187                 netdev->features  &= ~NETIF_F_RXALL;
3188
3189 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3190         if (FT_CAP(flow_modify_en) &&
3191             FT_CAP(modify_root) &&
3192             FT_CAP(identified_miss_table_mode) &&
3193             FT_CAP(flow_table_modify)) {
3194                 netdev->hw_features      |= NETIF_F_HW_TC;
3195 #ifdef CONFIG_RFS_ACCEL
3196                 netdev->hw_features      |= NETIF_F_NTUPLE;
3197 #endif
3198         }
3199
3200         netdev->features         |= NETIF_F_HIGHDMA;
3201
3202         netdev->priv_flags       |= IFF_UNICAST_FLT;
3203
3204         mlx5e_set_netdev_dev_addr(netdev);
3205
3206 #ifdef CONFIG_NET_SWITCHDEV
3207         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3208                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3209 #endif
3210 }
3211
3212 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3213 {
3214         struct mlx5_core_dev *mdev = priv->mdev;
3215         int err;
3216
3217         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3218         if (err) {
3219                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3220                 priv->q_counter = 0;
3221         }
3222 }
3223
3224 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3225 {
3226         if (!priv->q_counter)
3227                 return;
3228
3229         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3230 }
3231
3232 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3233 {
3234         struct mlx5_core_dev *mdev = priv->mdev;
3235         struct mlx5_create_mkey_mbox_in *in;
3236         struct mlx5_mkey_seg *mkc;
3237         int inlen = sizeof(*in);
3238         u64 npages = MLX5E_REQUIRED_MTTS(priv->profile->max_nch(mdev),
3239                                          BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW));
3240         int err;
3241
3242         in = mlx5_vzalloc(inlen);
3243         if (!in)
3244                 return -ENOMEM;
3245
3246         mkc = &in->seg;
3247         mkc->status = MLX5_MKEY_STATUS_FREE;
3248         mkc->flags = MLX5_PERM_UMR_EN |
3249                      MLX5_PERM_LOCAL_READ |
3250                      MLX5_PERM_LOCAL_WRITE |
3251                      MLX5_ACCESS_MODE_MTT;
3252
3253         npages = min_t(u32, ALIGN(U16_MAX, 4) * 2, npages);
3254
3255         mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3256         mkc->flags_pd = cpu_to_be32(mdev->mlx5e_res.pdn);
3257         mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
3258         mkc->xlt_oct_size = cpu_to_be32(MLX5_MTT_OCTW(npages));
3259         mkc->log2_page_size = PAGE_SHIFT;
3260
3261         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
3262                                     NULL, NULL);
3263
3264         kvfree(in);
3265
3266         return err;
3267 }
3268
3269 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3270                            struct net_device *netdev,
3271                            const struct mlx5e_profile *profile,
3272                            void *ppriv)
3273 {
3274         struct mlx5e_priv *priv = netdev_priv(netdev);
3275
3276         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3277         mlx5e_build_nic_netdev(netdev);
3278         mlx5e_vxlan_init(priv);
3279 }
3280
3281 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3282 {
3283         struct mlx5_core_dev *mdev = priv->mdev;
3284         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3285
3286         mlx5e_vxlan_cleanup(priv);
3287
3288         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3289                 mlx5_eswitch_unregister_vport_rep(esw, 0);
3290 }
3291
3292 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3293 {
3294         struct mlx5_core_dev *mdev = priv->mdev;
3295         int err;
3296         int i;
3297
3298         err = mlx5e_create_indirect_rqts(priv);
3299         if (err) {
3300                 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3301                 return err;
3302         }
3303
3304         err = mlx5e_create_direct_rqts(priv);
3305         if (err) {
3306                 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3307                 goto err_destroy_indirect_rqts;
3308         }
3309
3310         err = mlx5e_create_indirect_tirs(priv);
3311         if (err) {
3312                 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3313                 goto err_destroy_direct_rqts;
3314         }
3315
3316         err = mlx5e_create_direct_tirs(priv);
3317         if (err) {
3318                 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3319                 goto err_destroy_indirect_tirs;
3320         }
3321
3322         err = mlx5e_create_flow_steering(priv);
3323         if (err) {
3324                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3325                 goto err_destroy_direct_tirs;
3326         }
3327
3328         err = mlx5e_tc_init(priv);
3329         if (err)
3330                 goto err_destroy_flow_steering;
3331
3332         return 0;
3333
3334 err_destroy_flow_steering:
3335         mlx5e_destroy_flow_steering(priv);
3336 err_destroy_direct_tirs:
3337         mlx5e_destroy_direct_tirs(priv);
3338 err_destroy_indirect_tirs:
3339         mlx5e_destroy_indirect_tirs(priv);
3340 err_destroy_direct_rqts:
3341         for (i = 0; i < priv->profile->max_nch(mdev); i++)
3342                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3343 err_destroy_indirect_rqts:
3344         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3345         return err;
3346 }
3347
3348 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3349 {
3350         int i;
3351
3352         mlx5e_tc_cleanup(priv);
3353         mlx5e_destroy_flow_steering(priv);
3354         mlx5e_destroy_direct_tirs(priv);
3355         mlx5e_destroy_indirect_tirs(priv);
3356         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3357                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3358         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3359 }
3360
3361 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3362 {
3363         int err;
3364
3365         err = mlx5e_create_tises(priv);
3366         if (err) {
3367                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3368                 return err;
3369         }
3370
3371 #ifdef CONFIG_MLX5_CORE_EN_DCB
3372         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3373 #endif
3374         return 0;
3375 }
3376
3377 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3378 {
3379         struct net_device *netdev = priv->netdev;
3380         struct mlx5_core_dev *mdev = priv->mdev;
3381         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3382         struct mlx5_eswitch_rep rep;
3383
3384         if (mlx5e_vxlan_allowed(mdev)) {
3385                 rtnl_lock();
3386                 udp_tunnel_get_rx_info(netdev);
3387                 rtnl_unlock();
3388         }
3389
3390         mlx5e_enable_async_events(priv);
3391         queue_work(priv->wq, &priv->set_rx_mode_work);
3392
3393         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3394                 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
3395                 rep.load = mlx5e_nic_rep_load;
3396                 rep.unload = mlx5e_nic_rep_unload;
3397                 rep.vport = 0;
3398                 rep.priv_data = priv;
3399                 mlx5_eswitch_register_vport_rep(esw, &rep);
3400         }
3401 }
3402
3403 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3404 {
3405         queue_work(priv->wq, &priv->set_rx_mode_work);
3406         mlx5e_disable_async_events(priv);
3407 }
3408
3409 static const struct mlx5e_profile mlx5e_nic_profile = {
3410         .init              = mlx5e_nic_init,
3411         .cleanup           = mlx5e_nic_cleanup,
3412         .init_rx           = mlx5e_init_nic_rx,
3413         .cleanup_rx        = mlx5e_cleanup_nic_rx,
3414         .init_tx           = mlx5e_init_nic_tx,
3415         .cleanup_tx        = mlx5e_cleanup_nic_tx,
3416         .enable            = mlx5e_nic_enable,
3417         .disable           = mlx5e_nic_disable,
3418         .update_stats      = mlx5e_update_stats,
3419         .max_nch           = mlx5e_get_max_num_channels,
3420         .max_tc            = MLX5E_MAX_NUM_TC,
3421 };
3422
3423 void *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3424                           const struct mlx5e_profile *profile, void *ppriv)
3425 {
3426         struct net_device *netdev;
3427         struct mlx5e_priv *priv;
3428         int nch = profile->max_nch(mdev);
3429         int err;
3430
3431         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3432                                     nch * profile->max_tc,
3433                                     nch);
3434         if (!netdev) {
3435                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3436                 return NULL;
3437         }
3438
3439         profile->init(mdev, netdev, profile, ppriv);
3440
3441         netif_carrier_off(netdev);
3442
3443         priv = netdev_priv(netdev);
3444
3445         priv->wq = create_singlethread_workqueue("mlx5e");
3446         if (!priv->wq)
3447                 goto err_free_netdev;
3448
3449         err = mlx5e_create_umr_mkey(priv);
3450         if (err) {
3451                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3452                 goto err_destroy_wq;
3453         }
3454
3455         err = profile->init_tx(priv);
3456         if (err)
3457                 goto err_destroy_umr_mkey;
3458
3459         err = mlx5e_open_drop_rq(priv);
3460         if (err) {
3461                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3462                 goto err_cleanup_tx;
3463         }
3464
3465         err = profile->init_rx(priv);
3466         if (err)
3467                 goto err_close_drop_rq;
3468
3469         mlx5e_create_q_counter(priv);
3470
3471         mlx5e_init_l2_addr(priv);
3472
3473         mlx5e_set_dev_port_mtu(netdev);
3474
3475         err = register_netdev(netdev);
3476         if (err) {
3477                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3478                 goto err_dealloc_q_counters;
3479         }
3480
3481         if (profile->enable)
3482                 profile->enable(priv);
3483
3484         return priv;
3485
3486 err_dealloc_q_counters:
3487         mlx5e_destroy_q_counter(priv);
3488         profile->cleanup_rx(priv);
3489
3490 err_close_drop_rq:
3491         mlx5e_close_drop_rq(priv);
3492
3493 err_cleanup_tx:
3494         profile->cleanup_tx(priv);
3495
3496 err_destroy_umr_mkey:
3497         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3498
3499 err_destroy_wq:
3500         destroy_workqueue(priv->wq);
3501
3502 err_free_netdev:
3503         free_netdev(netdev);
3504
3505         return NULL;
3506 }
3507
3508 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3509 {
3510         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3511         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3512         int vport;
3513         u8 mac[ETH_ALEN];
3514
3515         if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3516                 return;
3517
3518         mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3519
3520         for (vport = 1; vport < total_vfs; vport++) {
3521                 struct mlx5_eswitch_rep rep;
3522
3523                 rep.load = mlx5e_vport_rep_load;
3524                 rep.unload = mlx5e_vport_rep_unload;
3525                 rep.vport = vport;
3526                 ether_addr_copy(rep.hw_id, mac);
3527                 mlx5_eswitch_register_vport_rep(esw, &rep);
3528         }
3529 }
3530
3531 static void *mlx5e_add(struct mlx5_core_dev *mdev)
3532 {
3533         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3534         void *ppriv = NULL;
3535         void *ret;
3536
3537         if (mlx5e_check_required_hca_cap(mdev))
3538                 return NULL;
3539
3540         if (mlx5e_create_mdev_resources(mdev))
3541                 return NULL;
3542
3543         mlx5e_register_vport_rep(mdev);
3544
3545         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3546                 ppriv = &esw->offloads.vport_reps[0];
3547
3548         ret = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
3549         if (!ret) {
3550                 mlx5e_destroy_mdev_resources(mdev);
3551                 return NULL;
3552         }
3553         return ret;
3554 }
3555
3556 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
3557 {
3558         const struct mlx5e_profile *profile = priv->profile;
3559         struct net_device *netdev = priv->netdev;
3560
3561         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3562         if (profile->disable)
3563                 profile->disable(priv);
3564
3565         flush_workqueue(priv->wq);
3566         if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3567                 netif_device_detach(netdev);
3568                 mlx5e_close(netdev);
3569         } else {
3570                 unregister_netdev(netdev);
3571         }
3572
3573         mlx5e_destroy_q_counter(priv);
3574         profile->cleanup_rx(priv);
3575         mlx5e_close_drop_rq(priv);
3576         profile->cleanup_tx(priv);
3577         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3578         cancel_delayed_work_sync(&priv->update_stats_work);
3579         destroy_workqueue(priv->wq);
3580         if (profile->cleanup)
3581                 profile->cleanup(priv);
3582
3583         if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3584                 free_netdev(netdev);
3585 }
3586
3587 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
3588 {
3589         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3590         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3591         struct mlx5e_priv *priv = vpriv;
3592         int vport;
3593
3594         mlx5e_destroy_netdev(mdev, priv);
3595
3596         for (vport = 1; vport < total_vfs; vport++)
3597                 mlx5_eswitch_unregister_vport_rep(esw, vport);
3598
3599         mlx5e_destroy_mdev_resources(mdev);
3600 }
3601
3602 static void *mlx5e_get_netdev(void *vpriv)
3603 {
3604         struct mlx5e_priv *priv = vpriv;
3605
3606         return priv->netdev;
3607 }
3608
3609 static struct mlx5_interface mlx5e_interface = {
3610         .add       = mlx5e_add,
3611         .remove    = mlx5e_remove,
3612         .event     = mlx5e_async_event,
3613         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
3614         .get_dev   = mlx5e_get_netdev,
3615 };
3616
3617 void mlx5e_init(void)
3618 {
3619         mlx5e_build_ptys2ethtool_map();
3620         mlx5_register_interface(&mlx5e_interface);
3621 }
3622
3623 void mlx5e_cleanup(void)
3624 {
3625         mlx5_unregister_interface(&mlx5e_interface);
3626 }