drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/mlx5/fs.h>
  34 #include <net/vxlan.h>
  35 #include "en.h"
  36 #include "eswitch.h"
  37 #include "vxlan.h"
  38
  39 struct mlx5e_rq_param {
  40         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  41         struct mlx5_wq_param       wq;
  42 };
  43
  44 struct mlx5e_sq_param {
  45         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  46         struct mlx5_wq_param       wq;
  47         u16                        max_inline;
  48 };
  49
  50 struct mlx5e_cq_param {
  51         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  52         struct mlx5_wq_param       wq;
  53         u16                        eq_ix;
  54 };
  55
  56 struct mlx5e_channel_param {
  57         struct mlx5e_rq_param      rq;
  58         struct mlx5e_sq_param      sq;
  59         struct mlx5e_cq_param      rx_cq;
  60         struct mlx5e_cq_param      tx_cq;
  61 };
  62
  63 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  64 {
  65         struct mlx5_core_dev *mdev = priv->mdev;
  66         u8 port_state;
  67
  68         port_state = mlx5_query_vport_state(mdev,
  69                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  70
  71         if (port_state == VPORT_STATE_UP)
  72                 netif_carrier_on(priv->netdev);
  73         else
  74                 netif_carrier_off(priv->netdev);
  75 }
  76
  77 static void mlx5e_update_carrier_work(struct work_struct *work)
  78 {
  79         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  80                                                update_carrier_work);
  81
  82         mutex_lock(&priv->state_lock);
  83         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  84                 mlx5e_update_carrier(priv);
  85         mutex_unlock(&priv->state_lock);
  86 }
  87
  88 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
  89 {
  90         struct mlx5_core_dev *mdev = priv->mdev;
  91         struct mlx5e_pport_stats *s = &priv->stats.pport;
  92         u32 *in;
  93         u32 *out;
  94         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
  95
  96         in  = mlx5_vzalloc(sz);
  97         out = mlx5_vzalloc(sz);
  98         if (!in || !out)
  99                 goto free_out;
 100
 101         MLX5_SET(ppcnt_reg, in, local_port, 1);
 102
 103         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 104         mlx5_core_access_reg(mdev, in, sz, out,
 105                              sz, MLX5_REG_PPCNT, 0, 0);
 106         memcpy(s->IEEE_802_3_counters,
 107                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 108                sizeof(s->IEEE_802_3_counters));
 109
 110         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 111         mlx5_core_access_reg(mdev, in, sz, out,
 112                              sz, MLX5_REG_PPCNT, 0, 0);
 113         memcpy(s->RFC_2863_counters,
 114                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 115                sizeof(s->RFC_2863_counters));
 116
 117         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 118         mlx5_core_access_reg(mdev, in, sz, out,
 119                              sz, MLX5_REG_PPCNT, 0, 0);
 120         memcpy(s->RFC_2819_counters,
 121                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 122                sizeof(s->RFC_2819_counters));
 123
 124 free_out:
 125         kvfree(in);
 126         kvfree(out);
 127 }
 128
 129 void mlx5e_update_stats(struct mlx5e_priv *priv)
 130 {
 131         struct mlx5_core_dev *mdev = priv->mdev;
 132         struct mlx5e_vport_stats *s = &priv->stats.vport;
 133         struct mlx5e_rq_stats *rq_stats;
 134         struct mlx5e_sq_stats *sq_stats;
 135         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 136         u32 *out;
 137         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 138         u64 tx_offload_none;
 139         int i, j;
 140
 141         out = mlx5_vzalloc(outlen);
 142         if (!out)
 143                 return;
 144
 145         /* Collect firts the SW counters and then HW for consistency */
 146         s->tso_packets          = 0;
 147         s->tso_bytes            = 0;
 148         s->tso_inner_packets    = 0;
 149         s->tso_inner_bytes      = 0;
 150         s->tx_queue_stopped     = 0;
 151         s->tx_queue_wake        = 0;
 152         s->tx_queue_dropped     = 0;
 153         s->tx_csum_inner        = 0;
 154         tx_offload_none         = 0;
 155         s->lro_packets          = 0;
 156         s->lro_bytes            = 0;
 157         s->rx_csum_none         = 0;
 158         s->rx_csum_sw           = 0;
 159         s->rx_wqe_err           = 0;
 160         for (i = 0; i < priv->params.num_channels; i++) {
 161                 rq_stats = &priv->channel[i]->rq.stats;
 162
 163                 s->lro_packets  += rq_stats->lro_packets;
 164                 s->lro_bytes    += rq_stats->lro_bytes;
 165                 s->rx_csum_none += rq_stats->csum_none;
 166                 s->rx_csum_sw   += rq_stats->csum_sw;
 167                 s->rx_wqe_err   += rq_stats->wqe_err;
 168
 169                 for (j = 0; j < priv->params.num_tc; j++) {
 170                         sq_stats = &priv->channel[i]->sq[j].stats;
 171
 172                         s->tso_packets          += sq_stats->tso_packets;
 173                         s->tso_bytes            += sq_stats->tso_bytes;
 174                         s->tso_inner_packets    += sq_stats->tso_inner_packets;
 175                         s->tso_inner_bytes      += sq_stats->tso_inner_bytes;
 176                         s->tx_queue_stopped     += sq_stats->stopped;
 177                         s->tx_queue_wake        += sq_stats->wake;
 178                         s->tx_queue_dropped     += sq_stats->dropped;
 179                         s->tx_csum_inner        += sq_stats->csum_offload_inner;
 180                         tx_offload_none         += sq_stats->csum_offload_none;
 181                 }
 182         }
 183
 184         /* HW counters */
 185         memset(in, 0, sizeof(in));
 186
 187         MLX5_SET(query_vport_counter_in, in, opcode,
 188                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 189         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 190         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 191
 192         memset(out, 0, outlen);
 193
 194         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 195                 goto free_out;
 196
 197 #define MLX5_GET_CTR(p, x) \
 198         MLX5_GET64(query_vport_counter_out, p, x)
 199
 200         s->rx_error_packets     =
 201                 MLX5_GET_CTR(out, received_errors.packets);
 202         s->rx_error_bytes       =
 203                 MLX5_GET_CTR(out, received_errors.octets);
 204         s->tx_error_packets     =
 205                 MLX5_GET_CTR(out, transmit_errors.packets);
 206         s->tx_error_bytes       =
 207                 MLX5_GET_CTR(out, transmit_errors.octets);
 208
 209         s->rx_unicast_packets   =
 210                 MLX5_GET_CTR(out, received_eth_unicast.packets);
 211         s->rx_unicast_bytes     =
 212                 MLX5_GET_CTR(out, received_eth_unicast.octets);
 213         s->tx_unicast_packets   =
 214                 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 215         s->tx_unicast_bytes     =
 216                 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 217
 218         s->rx_multicast_packets =
 219                 MLX5_GET_CTR(out, received_eth_multicast.packets);
 220         s->rx_multicast_bytes   =
 221                 MLX5_GET_CTR(out, received_eth_multicast.octets);
 222         s->tx_multicast_packets =
 223                 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 224         s->tx_multicast_bytes   =
 225                 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 226
 227         s->rx_broadcast_packets =
 228                 MLX5_GET_CTR(out, received_eth_broadcast.packets);
 229         s->rx_broadcast_bytes   =
 230                 MLX5_GET_CTR(out, received_eth_broadcast.octets);
 231         s->tx_broadcast_packets =
 232                 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 233         s->tx_broadcast_bytes   =
 234                 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 235
 236         s->rx_packets =
 237                 s->rx_unicast_packets +
 238                 s->rx_multicast_packets +
 239                 s->rx_broadcast_packets;
 240         s->rx_bytes =
 241                 s->rx_unicast_bytes +
 242                 s->rx_multicast_bytes +
 243                 s->rx_broadcast_bytes;
 244         s->tx_packets =
 245                 s->tx_unicast_packets +
 246                 s->tx_multicast_packets +
 247                 s->tx_broadcast_packets;
 248         s->tx_bytes =
 249                 s->tx_unicast_bytes +
 250                 s->tx_multicast_bytes +
 251                 s->tx_broadcast_bytes;
 252
 253         /* Update calculated offload counters */
 254         s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
 255         s->rx_csum_good    = s->rx_packets - s->rx_csum_none -
 256                                s->rx_csum_sw;
 257
 258         mlx5e_update_pport_counters(priv);
 259 free_out:
 260         kvfree(out);
 261 }
 262
 263 static void mlx5e_update_stats_work(struct work_struct *work)
 264 {
 265         struct delayed_work *dwork = to_delayed_work(work);
 266         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 267                                                update_stats_work);
 268         mutex_lock(&priv->state_lock);
 269         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 270                 mlx5e_update_stats(priv);
 271                 schedule_delayed_work(dwork,
 272                                       msecs_to_jiffies(
 273                                               MLX5E_UPDATE_STATS_INTERVAL));
 274         }
 275         mutex_unlock(&priv->state_lock);
 276 }
 277
 278 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 279                               enum mlx5_dev_event event, unsigned long param)
 280 {
 281         struct mlx5e_priv *priv = vpriv;
 282
 283         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 284                 return;
 285
 286         switch (event) {
 287         case MLX5_DEV_EVENT_PORT_UP:
 288         case MLX5_DEV_EVENT_PORT_DOWN:
 289                 schedule_work(&priv->update_carrier_work);
 290                 break;
 291
 292         default:
 293                 break;
 294         }
 295 }
 296
 297 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 298 {
 299         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 300 }
 301
 302 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 303 {
 304         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 305         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 306 }
 307
 308 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 309 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 310
 311 static int mlx5e_create_rq(struct mlx5e_channel *c,
 312                            struct mlx5e_rq_param *param,
 313                            struct mlx5e_rq *rq)
 314 {
 315         struct mlx5e_priv *priv = c->priv;
 316         struct mlx5_core_dev *mdev = priv->mdev;
 317         void *rqc = param->rqc;
 318         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 319         int wq_sz;
 320         int err;
 321         int i;
 322
 323         param->wq.db_numa_node = cpu_to_node(c->cpu);
 324
 325         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 326                                 &rq->wq_ctrl);
 327         if (err)
 328                 return err;
 329
 330         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 331
 332         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 333         rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 334                                cpu_to_node(c->cpu));
 335         if (!rq->skb) {
 336                 err = -ENOMEM;
 337                 goto err_rq_wq_destroy;
 338         }
 339
 340         rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
 341                                              MLX5E_SW2HW_MTU(priv->netdev->mtu);
 342         rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
 343
 344         for (i = 0; i < wq_sz; i++) {
 345                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 346                 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 347
 348                 wqe->data.lkey       = c->mkey_be;
 349                 wqe->data.byte_count =
 350                         cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 351         }
 352
 353         rq->pdev    = c->pdev;
 354         rq->netdev  = c->netdev;
 355         rq->tstamp  = &priv->tstamp;
 356         rq->channel = c;
 357         rq->ix      = c->ix;
 358         rq->priv    = c->priv;
 359
 360         return 0;
 361
 362 err_rq_wq_destroy:
 363         mlx5_wq_destroy(&rq->wq_ctrl);
 364
 365         return err;
 366 }
 367
 368 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 369 {
 370         kfree(rq->skb);
 371         mlx5_wq_destroy(&rq->wq_ctrl);
 372 }
 373
 374 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 375 {
 376         struct mlx5e_priv *priv = rq->priv;
 377         struct mlx5_core_dev *mdev = priv->mdev;
 378
 379         void *in;
 380         void *rqc;
 381         void *wq;
 382         int inlen;
 383         int err;
 384
 385         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 386                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 387         in = mlx5_vzalloc(inlen);
 388         if (!in)
 389                 return -ENOMEM;
 390
 391         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 392         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 393
 394         memcpy(rqc, param->rqc, sizeof(param->rqc));
 395
 396         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 397         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 398         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 399         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 400                                                 MLX5_ADAPTER_PAGE_SHIFT);
 401         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 402
 403         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 404                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 405
 406         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 407
 408         kvfree(in);
 409
 410         return err;
 411 }
 412
 413 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 414 {
 415         struct mlx5e_channel *c = rq->channel;
 416         struct mlx5e_priv *priv = c->priv;
 417         struct mlx5_core_dev *mdev = priv->mdev;
 418
 419         void *in;
 420         void *rqc;
 421         int inlen;
 422         int err;
 423
 424         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 425         in = mlx5_vzalloc(inlen);
 426         if (!in)
 427                 return -ENOMEM;
 428
 429         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 430
 431         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 432         MLX5_SET(rqc, rqc, state, next_state);
 433
 434         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 435
 436         kvfree(in);
 437
 438         return err;
 439 }
 440
 441 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 442 {
 443         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 444 }
 445
 446 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 447 {
 448         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 449         struct mlx5e_channel *c = rq->channel;
 450         struct mlx5e_priv *priv = c->priv;
 451         struct mlx5_wq_ll *wq = &rq->wq;
 452
 453         while (time_before(jiffies, exp_time)) {
 454                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 455                         return 0;
 456
 457                 msleep(20);
 458         }
 459
 460         return -ETIMEDOUT;
 461 }
 462
 463 static int mlx5e_open_rq(struct mlx5e_channel *c,
 464                          struct mlx5e_rq_param *param,
 465                          struct mlx5e_rq *rq)
 466 {
 467         int err;
 468
 469         err = mlx5e_create_rq(c, param, rq);
 470         if (err)
 471                 return err;
 472
 473         err = mlx5e_enable_rq(rq, param);
 474         if (err)
 475                 goto err_destroy_rq;
 476
 477         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 478         if (err)
 479                 goto err_disable_rq;
 480
 481         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 482         mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
 483
 484         return 0;
 485
 486 err_disable_rq:
 487         mlx5e_disable_rq(rq);
 488 err_destroy_rq:
 489         mlx5e_destroy_rq(rq);
 490
 491         return err;
 492 }
 493
 494 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 495 {
 496         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 497         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 498
 499         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 500         while (!mlx5_wq_ll_is_empty(&rq->wq))
 501                 msleep(20);
 502
 503         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 504         napi_synchronize(&rq->channel->napi);
 505
 506         mlx5e_disable_rq(rq);
 507         mlx5e_destroy_rq(rq);
 508 }
 509
 510 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 511 {
 512         kfree(sq->wqe_info);
 513         kfree(sq->dma_fifo);
 514         kfree(sq->skb);
 515 }
 516
 517 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 518 {
 519         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 520         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 521
 522         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 523         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 524                                     numa);
 525         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 526                                     numa);
 527
 528         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 529                 mlx5e_free_sq_db(sq);
 530                 return -ENOMEM;
 531         }
 532
 533         sq->dma_fifo_mask = df_sz - 1;
 534
 535         return 0;
 536 }
 537
 538 static int mlx5e_create_sq(struct mlx5e_channel *c,
 539                            int tc,
 540                            struct mlx5e_sq_param *param,
 541                            struct mlx5e_sq *sq)
 542 {
 543         struct mlx5e_priv *priv = c->priv;
 544         struct mlx5_core_dev *mdev = priv->mdev;
 545
 546         void *sqc = param->sqc;
 547         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 548         int txq_ix;
 549         int err;
 550
 551         err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
 552         if (err)
 553                 return err;
 554
 555         param->wq.db_numa_node = cpu_to_node(c->cpu);
 556
 557         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 558                                  &sq->wq_ctrl);
 559         if (err)
 560                 goto err_unmap_free_uar;
 561
 562         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 563         if (sq->uar.bf_map) {
 564                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 565                 sq->uar_map = sq->uar.bf_map;
 566         } else {
 567                 sq->uar_map = sq->uar.map;
 568         }
 569         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 570         sq->max_inline  = param->max_inline;
 571
 572         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 573         if (err)
 574                 goto err_sq_wq_destroy;
 575
 576         txq_ix = c->ix + tc * priv->params.num_channels;
 577         sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 578
 579         sq->pdev      = c->pdev;
 580         sq->tstamp    = &priv->tstamp;
 581         sq->mkey_be   = c->mkey_be;
 582         sq->channel   = c;
 583         sq->tc        = tc;
 584         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 585         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 586         priv->txq_to_sq_map[txq_ix] = sq;
 587
 588         return 0;
 589
 590 err_sq_wq_destroy:
 591         mlx5_wq_destroy(&sq->wq_ctrl);
 592
 593 err_unmap_free_uar:
 594         mlx5_unmap_free_uar(mdev, &sq->uar);
 595
 596         return err;
 597 }
 598
 599 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 600 {
 601         struct mlx5e_channel *c = sq->channel;
 602         struct mlx5e_priv *priv = c->priv;
 603
 604         mlx5e_free_sq_db(sq);
 605         mlx5_wq_destroy(&sq->wq_ctrl);
 606         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 607 }
 608
 609 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 610 {
 611         struct mlx5e_channel *c = sq->channel;
 612         struct mlx5e_priv *priv = c->priv;
 613         struct mlx5_core_dev *mdev = priv->mdev;
 614
 615         void *in;
 616         void *sqc;
 617         void *wq;
 618         int inlen;
 619         int err;
 620
 621         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 622                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 623         in = mlx5_vzalloc(inlen);
 624         if (!in)
 625                 return -ENOMEM;
 626
 627         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 628         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 629
 630         memcpy(sqc, param->sqc, sizeof(param->sqc));
 631
 632         MLX5_SET(sqc,  sqc, tis_num_0,          priv->tisn[sq->tc]);
 633         MLX5_SET(sqc,  sqc, cqn,                c->sq[sq->tc].cq.mcq.cqn);
 634         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 635         MLX5_SET(sqc,  sqc, tis_lst_sz,         1);
 636         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 637
 638         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 639         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 640         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 641                                           MLX5_ADAPTER_PAGE_SHIFT);
 642         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 643
 644         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 645                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 646
 647         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 648
 649         kvfree(in);
 650
 651         return err;
 652 }
 653
 654 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 655 {
 656         struct mlx5e_channel *c = sq->channel;
 657         struct mlx5e_priv *priv = c->priv;
 658         struct mlx5_core_dev *mdev = priv->mdev;
 659
 660         void *in;
 661         void *sqc;
 662         int inlen;
 663         int err;
 664
 665         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 666         in = mlx5_vzalloc(inlen);
 667         if (!in)
 668                 return -ENOMEM;
 669
 670         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 671
 672         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 673         MLX5_SET(sqc, sqc, state, next_state);
 674
 675         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 676
 677         kvfree(in);
 678
 679         return err;
 680 }
 681
 682 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 683 {
 684         struct mlx5e_channel *c = sq->channel;
 685         struct mlx5e_priv *priv = c->priv;
 686         struct mlx5_core_dev *mdev = priv->mdev;
 687
 688         mlx5_core_destroy_sq(mdev, sq->sqn);
 689 }
 690
 691 static int mlx5e_open_sq(struct mlx5e_channel *c,
 692                          int tc,
 693                          struct mlx5e_sq_param *param,
 694                          struct mlx5e_sq *sq)
 695 {
 696         int err;
 697
 698         err = mlx5e_create_sq(c, tc, param, sq);
 699         if (err)
 700                 return err;
 701
 702         err = mlx5e_enable_sq(sq, param);
 703         if (err)
 704                 goto err_destroy_sq;
 705
 706         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 707         if (err)
 708                 goto err_disable_sq;
 709
 710         set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 711         netdev_tx_reset_queue(sq->txq);
 712         netif_tx_start_queue(sq->txq);
 713
 714         return 0;
 715
 716 err_disable_sq:
 717         mlx5e_disable_sq(sq);
 718 err_destroy_sq:
 719         mlx5e_destroy_sq(sq);
 720
 721         return err;
 722 }
 723
 724 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 725 {
 726         __netif_tx_lock_bh(txq);
 727         netif_tx_stop_queue(txq);
 728         __netif_tx_unlock_bh(txq);
 729 }
 730
 731 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 732 {
 733         clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 734         napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
 735         netif_tx_disable_queue(sq->txq);
 736
 737         /* ensure hw is notified of all pending wqes */
 738         if (mlx5e_sq_has_room_for(sq, 1))
 739                 mlx5e_send_nop(sq, true);
 740
 741         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 742         while (sq->cc != sq->pc) /* wait till sq is empty */
 743                 msleep(20);
 744
 745         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 746         napi_synchronize(&sq->channel->napi);
 747
 748         mlx5e_disable_sq(sq);
 749         mlx5e_destroy_sq(sq);
 750 }
 751
 752 static int mlx5e_create_cq(struct mlx5e_channel *c,
 753                            struct mlx5e_cq_param *param,
 754                            struct mlx5e_cq *cq)
 755 {
 756         struct mlx5e_priv *priv = c->priv;
 757         struct mlx5_core_dev *mdev = priv->mdev;
 758         struct mlx5_core_cq *mcq = &cq->mcq;
 759         int eqn_not_used;
 760         unsigned int irqn;
 761         int err;
 762         u32 i;
 763
 764         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 765         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 766         param->eq_ix   = c->ix;
 767
 768         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 769                                &cq->wq_ctrl);
 770         if (err)
 771                 return err;
 772
 773         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 774
 775         cq->napi        = &c->napi;
 776
 777         mcq->cqe_sz     = 64;
 778         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 779         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 780         *mcq->set_ci_db = 0;
 781         *mcq->arm_db    = 0;
 782         mcq->vector     = param->eq_ix;
 783         mcq->comp       = mlx5e_completion_event;
 784         mcq->event      = mlx5e_cq_error_event;
 785         mcq->irqn       = irqn;
 786         mcq->uar        = &priv->cq_uar;
 787
 788         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 789                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 790
 791                 cqe->op_own = 0xf1;
 792         }
 793
 794         cq->channel = c;
 795         cq->priv = priv;
 796
 797         return 0;
 798 }
 799
 800 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 801 {
 802         mlx5_wq_destroy(&cq->wq_ctrl);
 803 }
 804
 805 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 806 {
 807         struct mlx5e_priv *priv = cq->priv;
 808         struct mlx5_core_dev *mdev = priv->mdev;
 809         struct mlx5_core_cq *mcq = &cq->mcq;
 810
 811         void *in;
 812         void *cqc;
 813         int inlen;
 814         unsigned int irqn_not_used;
 815         int eqn;
 816         int err;
 817
 818         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 819                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 820         in = mlx5_vzalloc(inlen);
 821         if (!in)
 822                 return -ENOMEM;
 823
 824         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 825
 826         memcpy(cqc, param->cqc, sizeof(param->cqc));
 827
 828         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 829                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 830
 831         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 832
 833         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 834         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 835         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 836                                             MLX5_ADAPTER_PAGE_SHIFT);
 837         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 838
 839         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 840
 841         kvfree(in);
 842
 843         if (err)
 844                 return err;
 845
 846         mlx5e_cq_arm(cq);
 847
 848         return 0;
 849 }
 850
 851 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 852 {
 853         struct mlx5e_priv *priv = cq->priv;
 854         struct mlx5_core_dev *mdev = priv->mdev;
 855
 856         mlx5_core_destroy_cq(mdev, &cq->mcq);
 857 }
 858
 859 static int mlx5e_open_cq(struct mlx5e_channel *c,
 860                          struct mlx5e_cq_param *param,
 861                          struct mlx5e_cq *cq,
 862                          u16 moderation_usecs,
 863                          u16 moderation_frames)
 864 {
 865         int err;
 866         struct mlx5e_priv *priv = c->priv;
 867         struct mlx5_core_dev *mdev = priv->mdev;
 868
 869         err = mlx5e_create_cq(c, param, cq);
 870         if (err)
 871                 return err;
 872
 873         err = mlx5e_enable_cq(cq, param);
 874         if (err)
 875                 goto err_destroy_cq;
 876
 877         if (MLX5_CAP_GEN(mdev, cq_moderation))
 878                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 879                                                moderation_usecs,
 880                                                moderation_frames);
 881         return 0;
 882
 883 err_destroy_cq:
 884         mlx5e_destroy_cq(cq);
 885
 886         return err;
 887 }
 888
 889 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 890 {
 891         mlx5e_disable_cq(cq);
 892         mlx5e_destroy_cq(cq);
 893 }
 894
 895 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 896 {
 897         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 898 }
 899
 900 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 901                              struct mlx5e_channel_param *cparam)
 902 {
 903         struct mlx5e_priv *priv = c->priv;
 904         int err;
 905         int tc;
 906
 907         for (tc = 0; tc < c->num_tc; tc++) {
 908                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 909                                     priv->params.tx_cq_moderation_usec,
 910                                     priv->params.tx_cq_moderation_pkts);
 911                 if (err)
 912                         goto err_close_tx_cqs;
 913         }
 914
 915         return 0;
 916
 917 err_close_tx_cqs:
 918         for (tc--; tc >= 0; tc--)
 919                 mlx5e_close_cq(&c->sq[tc].cq);
 920
 921         return err;
 922 }
 923
 924 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 925 {
 926         int tc;
 927
 928         for (tc = 0; tc < c->num_tc; tc++)
 929                 mlx5e_close_cq(&c->sq[tc].cq);
 930 }
 931
 932 static int mlx5e_open_sqs(struct mlx5e_channel *c,
 933                           struct mlx5e_channel_param *cparam)
 934 {
 935         int err;
 936         int tc;
 937
 938         for (tc = 0; tc < c->num_tc; tc++) {
 939                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
 940                 if (err)
 941                         goto err_close_sqs;
 942         }
 943
 944         return 0;
 945
 946 err_close_sqs:
 947         for (tc--; tc >= 0; tc--)
 948                 mlx5e_close_sq(&c->sq[tc]);
 949
 950         return err;
 951 }
 952
 953 static void mlx5e_close_sqs(struct mlx5e_channel *c)
 954 {
 955         int tc;
 956
 957         for (tc = 0; tc < c->num_tc; tc++)
 958                 mlx5e_close_sq(&c->sq[tc]);
 959 }
 960
 961 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
 962 {
 963         int i;
 964
 965         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
 966                 priv->channeltc_to_txq_map[ix][i] =
 967                         ix + i * priv->params.num_channels;
 968 }
 969
 970 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
 971                               struct mlx5e_channel_param *cparam,
 972                               struct mlx5e_channel **cp)
 973 {
 974         struct net_device *netdev = priv->netdev;
 975         int cpu = mlx5e_get_cpu(priv, ix);
 976         struct mlx5e_channel *c;
 977         int err;
 978
 979         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
 980         if (!c)
 981                 return -ENOMEM;
 982
 983         c->priv     = priv;
 984         c->ix       = ix;
 985         c->cpu      = cpu;
 986         c->pdev     = &priv->mdev->pdev->dev;
 987         c->netdev   = priv->netdev;
 988         c->mkey_be  = cpu_to_be32(priv->mr.key);
 989         c->num_tc   = priv->params.num_tc;
 990
 991         mlx5e_build_channeltc_to_txq_map(priv, ix);
 992
 993         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
 994
 995         err = mlx5e_open_tx_cqs(c, cparam);
 996         if (err)
 997                 goto err_napi_del;
 998
 999         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1000                             priv->params.rx_cq_moderation_usec,
1001                             priv->params.rx_cq_moderation_pkts);
1002         if (err)
1003                 goto err_close_tx_cqs;
1004
1005         napi_enable(&c->napi);
1006
1007         err = mlx5e_open_sqs(c, cparam);
1008         if (err)
1009                 goto err_disable_napi;
1010
1011         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1012         if (err)
1013                 goto err_close_sqs;
1014
1015         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1016         *cp = c;
1017
1018         return 0;
1019
1020 err_close_sqs:
1021         mlx5e_close_sqs(c);
1022
1023 err_disable_napi:
1024         napi_disable(&c->napi);
1025         mlx5e_close_cq(&c->rq.cq);
1026
1027 err_close_tx_cqs:
1028         mlx5e_close_tx_cqs(c);
1029
1030 err_napi_del:
1031         netif_napi_del(&c->napi);
1032         napi_hash_del(&c->napi);
1033         kfree(c);
1034
1035         return err;
1036 }
1037
1038 static void mlx5e_close_channel(struct mlx5e_channel *c)
1039 {
1040         mlx5e_close_rq(&c->rq);
1041         mlx5e_close_sqs(c);
1042         napi_disable(&c->napi);
1043         mlx5e_close_cq(&c->rq.cq);
1044         mlx5e_close_tx_cqs(c);
1045         netif_napi_del(&c->napi);
1046
1047         napi_hash_del(&c->napi);
1048         synchronize_rcu();
1049
1050         kfree(c);
1051 }
1052
1053 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1054                                  struct mlx5e_rq_param *param)
1055 {
1056         void *rqc = param->rqc;
1057         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1058
1059         MLX5_SET(wq, wq, wq_type,          MLX5_WQ_TYPE_LINKED_LIST);
1060         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1061         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1062         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1063         MLX5_SET(wq, wq, pd,               priv->pdn);
1064
1065         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1066         param->wq.linear = 1;
1067 }
1068
1069 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1070 {
1071         void *rqc = param->rqc;
1072         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1073
1074         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1075         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1076 }
1077
1078 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1079                                  struct mlx5e_sq_param *param)
1080 {
1081         void *sqc = param->sqc;
1082         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1083
1084         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1085         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1086         MLX5_SET(wq, wq, pd,            priv->pdn);
1087
1088         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1089         param->max_inline = priv->params.tx_max_inline;
1090 }
1091
1092 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1093                                         struct mlx5e_cq_param *param)
1094 {
1095         void *cqc = param->cqc;
1096
1097         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1098 }
1099
1100 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1101                                     struct mlx5e_cq_param *param)
1102 {
1103         void *cqc = param->cqc;
1104
1105         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_rq_size);
1106
1107         mlx5e_build_common_cq_param(priv, param);
1108 }
1109
1110 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1111                                     struct mlx5e_cq_param *param)
1112 {
1113         void *cqc = param->cqc;
1114
1115         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_sq_size);
1116
1117         mlx5e_build_common_cq_param(priv, param);
1118 }
1119
1120 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1121                                       struct mlx5e_channel_param *cparam)
1122 {
1123         memset(cparam, 0, sizeof(*cparam));
1124
1125         mlx5e_build_rq_param(priv, &cparam->rq);
1126         mlx5e_build_sq_param(priv, &cparam->sq);
1127         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1128         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1129 }
1130
1131 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1132 {
1133         struct mlx5e_channel_param cparam;
1134         int nch = priv->params.num_channels;
1135         int err = -ENOMEM;
1136         int i;
1137         int j;
1138
1139         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1140                                 GFP_KERNEL);
1141
1142         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1143                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1144
1145         if (!priv->channel || !priv->txq_to_sq_map)
1146                 goto err_free_txq_to_sq_map;
1147
1148         mlx5e_build_channel_param(priv, &cparam);
1149         for (i = 0; i < nch; i++) {
1150                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1151                 if (err)
1152                         goto err_close_channels;
1153         }
1154
1155         for (j = 0; j < nch; j++) {
1156                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1157                 if (err)
1158                         goto err_close_channels;
1159         }
1160
1161         return 0;
1162
1163 err_close_channels:
1164         for (i--; i >= 0; i--)
1165                 mlx5e_close_channel(priv->channel[i]);
1166
1167 err_free_txq_to_sq_map:
1168         kfree(priv->txq_to_sq_map);
1169         kfree(priv->channel);
1170
1171         return err;
1172 }
1173
1174 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1175 {
1176         int i;
1177
1178         for (i = 0; i < priv->params.num_channels; i++)
1179                 mlx5e_close_channel(priv->channel[i]);
1180
1181         kfree(priv->txq_to_sq_map);
1182         kfree(priv->channel);
1183 }
1184
1185 static int mlx5e_rx_hash_fn(int hfunc)
1186 {
1187         return (hfunc == ETH_RSS_HASH_TOP) ?
1188                MLX5_RX_HASH_FN_TOEPLITZ :
1189                MLX5_RX_HASH_FN_INVERTED_XOR8;
1190 }
1191
1192 static int mlx5e_bits_invert(unsigned long a, int size)
1193 {
1194         int inv = 0;
1195         int i;
1196
1197         for (i = 0; i < size; i++)
1198                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1199
1200         return inv;
1201 }
1202
1203 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1204 {
1205         int i;
1206
1207         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1208                 int ix = i;
1209
1210                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1211                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1212
1213                 ix = priv->params.indirection_rqt[ix];
1214                 ix = ix % priv->params.num_channels;
1215                 MLX5_SET(rqtc, rqtc, rq_num[i],
1216                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1217                          priv->channel[ix]->rq.rqn :
1218                          priv->drop_rq.rqn);
1219         }
1220 }
1221
1222 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1223                                 enum mlx5e_rqt_ix rqt_ix)
1224 {
1225
1226         switch (rqt_ix) {
1227         case MLX5E_INDIRECTION_RQT:
1228                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1229
1230                 break;
1231
1232         default: /* MLX5E_SINGLE_RQ_RQT */
1233                 MLX5_SET(rqtc, rqtc, rq_num[0],
1234                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1235                          priv->channel[0]->rq.rqn :
1236                          priv->drop_rq.rqn);
1237
1238                 break;
1239         }
1240 }
1241
1242 static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1243 {
1244         struct mlx5_core_dev *mdev = priv->mdev;
1245         u32 *in;
1246         void *rqtc;
1247         int inlen;
1248         int sz;
1249         int err;
1250
1251         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1252
1253         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1254         in = mlx5_vzalloc(inlen);
1255         if (!in)
1256                 return -ENOMEM;
1257
1258         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1259
1260         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1261         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1262
1263         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1264
1265         err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
1266
1267         kvfree(in);
1268
1269         return err;
1270 }
1271
1272 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1273 {
1274         struct mlx5_core_dev *mdev = priv->mdev;
1275         u32 *in;
1276         void *rqtc;
1277         int inlen;
1278         int sz;
1279         int err;
1280
1281         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1282
1283         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1284         in = mlx5_vzalloc(inlen);
1285         if (!in)
1286                 return -ENOMEM;
1287
1288         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1289
1290         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1291
1292         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1293
1294         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1295
1296         err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1297
1298         kvfree(in);
1299
1300         return err;
1301 }
1302
1303 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1304 {
1305         mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
1306 }
1307
1308 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1309 {
1310         mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1311         mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1312 }
1313
1314 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1315 {
1316         if (!priv->params.lro_en)
1317                 return;
1318
1319 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1320
1321         MLX5_SET(tirc, tirc, lro_enable_mask,
1322                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1323                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1324         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1325                  (priv->params.lro_wqe_sz -
1326                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1327         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1328                  MLX5_CAP_ETH(priv->mdev,
1329                               lro_timer_supported_periods[2]));
1330 }
1331
1332 static int mlx5e_modify_tir_lro(struct mlx5e_priv *priv, int tt)
1333 {
1334         struct mlx5_core_dev *mdev = priv->mdev;
1335
1336         void *in;
1337         void *tirc;
1338         int inlen;
1339         int err;
1340
1341         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1342         in = mlx5_vzalloc(inlen);
1343         if (!in)
1344                 return -ENOMEM;
1345
1346         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1347         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1348
1349         mlx5e_build_tir_ctx_lro(tirc, priv);
1350
1351         err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1352
1353         kvfree(in);
1354
1355         return err;
1356 }
1357
1358 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1359                                                   u32 tirn)
1360 {
1361         void *in;
1362         int inlen;
1363         int err;
1364
1365         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1366         in = mlx5_vzalloc(inlen);
1367         if (!in)
1368                 return -ENOMEM;
1369
1370         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1371
1372         err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1373
1374         kvfree(in);
1375
1376         return err;
1377 }
1378
1379 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1380 {
1381         int err;
1382         int i;
1383
1384         for (i = 0; i < MLX5E_NUM_TT; i++) {
1385                 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1386                                                              priv->tirn[i]);
1387                 if (err)
1388                         return err;
1389         }
1390
1391         return 0;
1392 }
1393
1394 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1395 {
1396         struct mlx5e_priv *priv = netdev_priv(netdev);
1397         struct mlx5_core_dev *mdev = priv->mdev;
1398         int hw_mtu;
1399         int err;
1400
1401         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1402         if (err)
1403                 return err;
1404
1405         mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1406
1407         if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1408                 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1409                             __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1410
1411         netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1412         return 0;
1413 }
1414
1415 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1416 {
1417         struct mlx5e_priv *priv = netdev_priv(netdev);
1418         int nch = priv->params.num_channels;
1419         int ntc = priv->params.num_tc;
1420         int tc;
1421
1422         netdev_reset_tc(netdev);
1423
1424         if (ntc == 1)
1425                 return;
1426
1427         netdev_set_num_tc(netdev, ntc);
1428
1429         for (tc = 0; tc < ntc; tc++)
1430                 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1431 }
1432
1433 int mlx5e_open_locked(struct net_device *netdev)
1434 {
1435         struct mlx5e_priv *priv = netdev_priv(netdev);
1436         int num_txqs;
1437         int err;
1438
1439         set_bit(MLX5E_STATE_OPENED, &priv->state);
1440
1441         mlx5e_netdev_set_tcs(netdev);
1442
1443         num_txqs = priv->params.num_channels * priv->params.num_tc;
1444         netif_set_real_num_tx_queues(netdev, num_txqs);
1445         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1446
1447         err = mlx5e_set_dev_port_mtu(netdev);
1448         if (err)
1449                 goto err_clear_state_opened_flag;
1450
1451         err = mlx5e_open_channels(priv);
1452         if (err) {
1453                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1454                            __func__, err);
1455                 goto err_clear_state_opened_flag;
1456         }
1457
1458         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1459         if (err) {
1460                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1461                            __func__, err);
1462                 goto err_close_channels;
1463         }
1464
1465         mlx5e_redirect_rqts(priv);
1466         mlx5e_update_carrier(priv);
1467         mlx5e_timestamp_init(priv);
1468
1469         schedule_delayed_work(&priv->update_stats_work, 0);
1470
1471         return 0;
1472
1473 err_close_channels:
1474         mlx5e_close_channels(priv);
1475 err_clear_state_opened_flag:
1476         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1477         return err;
1478 }
1479
1480 static int mlx5e_open(struct net_device *netdev)
1481 {
1482         struct mlx5e_priv *priv = netdev_priv(netdev);
1483         int err;
1484
1485         mutex_lock(&priv->state_lock);
1486         err = mlx5e_open_locked(netdev);
1487         mutex_unlock(&priv->state_lock);
1488
1489         return err;
1490 }
1491
1492 int mlx5e_close_locked(struct net_device *netdev)
1493 {
1494         struct mlx5e_priv *priv = netdev_priv(netdev);
1495
1496         /* May already be CLOSED in case a previous configuration operation
1497          * (e.g RX/TX queue size change) that involves close&open failed.
1498          */
1499         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1500                 return 0;
1501
1502         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1503
1504         mlx5e_timestamp_cleanup(priv);
1505         netif_carrier_off(priv->netdev);
1506         mlx5e_redirect_rqts(priv);
1507         mlx5e_close_channels(priv);
1508
1509         return 0;
1510 }
1511
1512 static int mlx5e_close(struct net_device *netdev)
1513 {
1514         struct mlx5e_priv *priv = netdev_priv(netdev);
1515         int err;
1516
1517         mutex_lock(&priv->state_lock);
1518         err = mlx5e_close_locked(netdev);
1519         mutex_unlock(&priv->state_lock);
1520
1521         return err;
1522 }
1523
1524 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1525                                 struct mlx5e_rq *rq,
1526                                 struct mlx5e_rq_param *param)
1527 {
1528         struct mlx5_core_dev *mdev = priv->mdev;
1529         void *rqc = param->rqc;
1530         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1531         int err;
1532
1533         param->wq.db_numa_node = param->wq.buf_numa_node;
1534
1535         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1536                                 &rq->wq_ctrl);
1537         if (err)
1538                 return err;
1539
1540         rq->priv = priv;
1541
1542         return 0;
1543 }
1544
1545 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1546                                 struct mlx5e_cq *cq,
1547                                 struct mlx5e_cq_param *param)
1548 {
1549         struct mlx5_core_dev *mdev = priv->mdev;
1550         struct mlx5_core_cq *mcq = &cq->mcq;
1551         int eqn_not_used;
1552         unsigned int irqn;
1553         int err;
1554
1555         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1556                                &cq->wq_ctrl);
1557         if (err)
1558                 return err;
1559
1560         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1561
1562         mcq->cqe_sz     = 64;
1563         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1564         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1565         *mcq->set_ci_db = 0;
1566         *mcq->arm_db    = 0;
1567         mcq->vector     = param->eq_ix;
1568         mcq->comp       = mlx5e_completion_event;
1569         mcq->event      = mlx5e_cq_error_event;
1570         mcq->irqn       = irqn;
1571         mcq->uar        = &priv->cq_uar;
1572
1573         cq->priv = priv;
1574
1575         return 0;
1576 }
1577
1578 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1579 {
1580         struct mlx5e_cq_param cq_param;
1581         struct mlx5e_rq_param rq_param;
1582         struct mlx5e_rq *rq = &priv->drop_rq;
1583         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1584         int err;
1585
1586         memset(&cq_param, 0, sizeof(cq_param));
1587         memset(&rq_param, 0, sizeof(rq_param));
1588         mlx5e_build_drop_rq_param(&rq_param);
1589
1590         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1591         if (err)
1592                 return err;
1593
1594         err = mlx5e_enable_cq(cq, &cq_param);
1595         if (err)
1596                 goto err_destroy_cq;
1597
1598         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1599         if (err)
1600                 goto err_disable_cq;
1601
1602         err = mlx5e_enable_rq(rq, &rq_param);
1603         if (err)
1604                 goto err_destroy_rq;
1605
1606         return 0;
1607
1608 err_destroy_rq:
1609         mlx5e_destroy_rq(&priv->drop_rq);
1610
1611 err_disable_cq:
1612         mlx5e_disable_cq(&priv->drop_rq.cq);
1613
1614 err_destroy_cq:
1615         mlx5e_destroy_cq(&priv->drop_rq.cq);
1616
1617         return err;
1618 }
1619
1620 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1621 {
1622         mlx5e_disable_rq(&priv->drop_rq);
1623         mlx5e_destroy_rq(&priv->drop_rq);
1624         mlx5e_disable_cq(&priv->drop_rq.cq);
1625         mlx5e_destroy_cq(&priv->drop_rq.cq);
1626 }
1627
1628 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1629 {
1630         struct mlx5_core_dev *mdev = priv->mdev;
1631         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1632         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1633
1634         memset(in, 0, sizeof(in));
1635
1636         MLX5_SET(tisc, tisc, prio, tc << 1);
1637         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1638
1639         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1640 }
1641
1642 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1643 {
1644         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1645 }
1646
1647 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1648 {
1649         int err;
1650         int tc;
1651
1652         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1653                 err = mlx5e_create_tis(priv, tc);
1654                 if (err)
1655                         goto err_close_tises;
1656         }
1657
1658         return 0;
1659
1660 err_close_tises:
1661         for (tc--; tc >= 0; tc--)
1662                 mlx5e_destroy_tis(priv, tc);
1663
1664         return err;
1665 }
1666
1667 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1668 {
1669         int tc;
1670
1671         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1672                 mlx5e_destroy_tis(priv, tc);
1673 }
1674
1675 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1676 {
1677         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1678
1679         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1680
1681 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1682                                  MLX5_HASH_FIELD_SEL_DST_IP)
1683
1684 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1685                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1686                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1687                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1688
1689 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1690                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1691                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1692
1693         mlx5e_build_tir_ctx_lro(tirc, priv);
1694
1695         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1696
1697         switch (tt) {
1698         case MLX5E_TT_ANY:
1699                 MLX5_SET(tirc, tirc, indirect_table,
1700                          priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1701                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
1702                 break;
1703         default:
1704                 MLX5_SET(tirc, tirc, indirect_table,
1705                          priv->rqtn[MLX5E_INDIRECTION_RQT]);
1706                 MLX5_SET(tirc, tirc, rx_hash_fn,
1707                          mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1708                 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1709                         void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1710                                                      rx_hash_toeplitz_key);
1711                         size_t len = MLX5_FLD_SZ_BYTES(tirc,
1712                                                        rx_hash_toeplitz_key);
1713
1714                         MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1715                         memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1716                 }
1717                 break;
1718         }
1719
1720         switch (tt) {
1721         case MLX5E_TT_IPV4_TCP:
1722                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1723                          MLX5_L3_PROT_TYPE_IPV4);
1724                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1725                          MLX5_L4_PROT_TYPE_TCP);
1726                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1727                          MLX5_HASH_IP_L4PORTS);
1728                 break;
1729
1730         case MLX5E_TT_IPV6_TCP:
1731                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1732                          MLX5_L3_PROT_TYPE_IPV6);
1733                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1734                          MLX5_L4_PROT_TYPE_TCP);
1735                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1736                          MLX5_HASH_IP_L4PORTS);
1737                 break;
1738
1739         case MLX5E_TT_IPV4_UDP:
1740                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1741                          MLX5_L3_PROT_TYPE_IPV4);
1742                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1743                          MLX5_L4_PROT_TYPE_UDP);
1744                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1745                          MLX5_HASH_IP_L4PORTS);
1746                 break;
1747
1748         case MLX5E_TT_IPV6_UDP:
1749                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1750                          MLX5_L3_PROT_TYPE_IPV6);
1751                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1752                          MLX5_L4_PROT_TYPE_UDP);
1753                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1754                          MLX5_HASH_IP_L4PORTS);
1755                 break;
1756
1757         case MLX5E_TT_IPV4_IPSEC_AH:
1758                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1759                          MLX5_L3_PROT_TYPE_IPV4);
1760                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1761                          MLX5_HASH_IP_IPSEC_SPI);
1762                 break;
1763
1764         case MLX5E_TT_IPV6_IPSEC_AH:
1765                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1766                          MLX5_L3_PROT_TYPE_IPV6);
1767                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1768                          MLX5_HASH_IP_IPSEC_SPI);
1769                 break;
1770
1771         case MLX5E_TT_IPV4_IPSEC_ESP:
1772                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1773                          MLX5_L3_PROT_TYPE_IPV4);
1774                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1775                          MLX5_HASH_IP_IPSEC_SPI);
1776                 break;
1777
1778         case MLX5E_TT_IPV6_IPSEC_ESP:
1779                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1780                          MLX5_L3_PROT_TYPE_IPV6);
1781                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1782                          MLX5_HASH_IP_IPSEC_SPI);
1783                 break;
1784
1785         case MLX5E_TT_IPV4:
1786                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1787                          MLX5_L3_PROT_TYPE_IPV4);
1788                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1789                          MLX5_HASH_IP);
1790                 break;
1791
1792         case MLX5E_TT_IPV6:
1793                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1794                          MLX5_L3_PROT_TYPE_IPV6);
1795                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1796                          MLX5_HASH_IP);
1797                 break;
1798         }
1799 }
1800
1801 static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
1802 {
1803         struct mlx5_core_dev *mdev = priv->mdev;
1804         u32 *in;
1805         void *tirc;
1806         int inlen;
1807         int err;
1808
1809         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1810         in = mlx5_vzalloc(inlen);
1811         if (!in)
1812                 return -ENOMEM;
1813
1814         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1815
1816         mlx5e_build_tir_ctx(priv, tirc, tt);
1817
1818         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1819
1820         kvfree(in);
1821
1822         return err;
1823 }
1824
1825 static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
1826 {
1827         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1828 }
1829
1830 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
1831 {
1832         int err;
1833         int i;
1834
1835         for (i = 0; i < MLX5E_NUM_TT; i++) {
1836                 err = mlx5e_create_tir(priv, i);
1837                 if (err)
1838                         goto err_destroy_tirs;
1839         }
1840
1841         return 0;
1842
1843 err_destroy_tirs:
1844         for (i--; i >= 0; i--)
1845                 mlx5e_destroy_tir(priv, i);
1846
1847         return err;
1848 }
1849
1850 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
1851 {
1852         int i;
1853
1854         for (i = 0; i < MLX5E_NUM_TT; i++)
1855                 mlx5e_destroy_tir(priv, i);
1856 }
1857
1858 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
1859 {
1860         struct mlx5e_priv *priv = netdev_priv(netdev);
1861         bool was_opened;
1862         int err = 0;
1863
1864         if (tc && tc != MLX5E_MAX_NUM_TC)
1865                 return -EINVAL;
1866
1867         mutex_lock(&priv->state_lock);
1868
1869         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1870         if (was_opened)
1871                 mlx5e_close_locked(priv->netdev);
1872
1873         priv->params.num_tc = tc ? tc : 1;
1874
1875         if (was_opened)
1876                 err = mlx5e_open_locked(priv->netdev);
1877
1878         mutex_unlock(&priv->state_lock);
1879
1880         return err;
1881 }
1882
1883 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
1884                               __be16 proto, struct tc_to_netdev *tc)
1885 {
1886         if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO)
1887                 return -EINVAL;
1888
1889         return mlx5e_setup_tc(dev, tc->tc);
1890 }
1891
1892 static struct rtnl_link_stats64 *
1893 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1894 {
1895         struct mlx5e_priv *priv = netdev_priv(dev);
1896         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1897
1898         stats->rx_packets = vstats->rx_packets;
1899         stats->rx_bytes   = vstats->rx_bytes;
1900         stats->tx_packets = vstats->tx_packets;
1901         stats->tx_bytes   = vstats->tx_bytes;
1902         stats->multicast  = vstats->rx_multicast_packets +
1903                             vstats->tx_multicast_packets;
1904         stats->tx_errors  = vstats->tx_error_packets;
1905         stats->rx_errors  = vstats->rx_error_packets;
1906         stats->tx_dropped = vstats->tx_queue_dropped;
1907         stats->rx_crc_errors = 0;
1908         stats->rx_length_errors = 0;
1909
1910         return stats;
1911 }
1912
1913 static void mlx5e_set_rx_mode(struct net_device *dev)
1914 {
1915         struct mlx5e_priv *priv = netdev_priv(dev);
1916
1917         schedule_work(&priv->set_rx_mode_work);
1918 }
1919
1920 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1921 {
1922         struct mlx5e_priv *priv = netdev_priv(netdev);
1923         struct sockaddr *saddr = addr;
1924
1925         if (!is_valid_ether_addr(saddr->sa_data))
1926                 return -EADDRNOTAVAIL;
1927
1928         netif_addr_lock_bh(netdev);
1929         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1930         netif_addr_unlock_bh(netdev);
1931
1932         schedule_work(&priv->set_rx_mode_work);
1933
1934         return 0;
1935 }
1936
1937 static int mlx5e_set_features(struct net_device *netdev,
1938                               netdev_features_t features)
1939 {
1940         struct mlx5e_priv *priv = netdev_priv(netdev);
1941         int err = 0;
1942         netdev_features_t changes = features ^ netdev->features;
1943
1944         mutex_lock(&priv->state_lock);
1945
1946         if (changes & NETIF_F_LRO) {
1947                 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1948
1949                 if (was_opened)
1950                         mlx5e_close_locked(priv->netdev);
1951
1952                 priv->params.lro_en = !!(features & NETIF_F_LRO);
1953                 mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV4_TCP);
1954                 mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV6_TCP);
1955
1956                 if (was_opened)
1957                         err = mlx5e_open_locked(priv->netdev);
1958         }
1959
1960         mutex_unlock(&priv->state_lock);
1961
1962         if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1963                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1964                         mlx5e_enable_vlan_filter(priv);
1965                 else
1966                         mlx5e_disable_vlan_filter(priv);
1967         }
1968
1969         return err;
1970 }
1971
1972 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1973 {
1974         struct mlx5e_priv *priv = netdev_priv(netdev);
1975         struct mlx5_core_dev *mdev = priv->mdev;
1976         bool was_opened;
1977         int max_mtu;
1978         int err = 0;
1979
1980         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
1981
1982         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
1983
1984         if (new_mtu > max_mtu) {
1985                 netdev_err(netdev,
1986                            "%s: Bad MTU (%d) > (%d) Max\n",
1987                            __func__, new_mtu, max_mtu);
1988                 return -EINVAL;
1989         }
1990
1991         mutex_lock(&priv->state_lock);
1992
1993         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1994         if (was_opened)
1995                 mlx5e_close_locked(netdev);
1996
1997         netdev->mtu = new_mtu;
1998
1999         if (was_opened)
2000                 err = mlx5e_open_locked(netdev);
2001
2002         mutex_unlock(&priv->state_lock);
2003
2004         return err;
2005 }
2006
2007 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2008 {
2009         switch (cmd) {
2010         case SIOCSHWTSTAMP:
2011                 return mlx5e_hwstamp_set(dev, ifr);
2012         case SIOCGHWTSTAMP:
2013                 return mlx5e_hwstamp_get(dev, ifr);
2014         default:
2015                 return -EOPNOTSUPP;
2016         }
2017 }
2018
2019 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2020 {
2021         struct mlx5e_priv *priv = netdev_priv(dev);
2022         struct mlx5_core_dev *mdev = priv->mdev;
2023
2024         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2025 }
2026
2027 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2028 {
2029         struct mlx5e_priv *priv = netdev_priv(dev);
2030         struct mlx5_core_dev *mdev = priv->mdev;
2031
2032         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2033                                            vlan, qos);
2034 }
2035
2036 static int mlx5_vport_link2ifla(u8 esw_link)
2037 {
2038         switch (esw_link) {
2039         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2040                 return IFLA_VF_LINK_STATE_DISABLE;
2041         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2042                 return IFLA_VF_LINK_STATE_ENABLE;
2043         }
2044         return IFLA_VF_LINK_STATE_AUTO;
2045 }
2046
2047 static int mlx5_ifla_link2vport(u8 ifla_link)
2048 {
2049         switch (ifla_link) {
2050         case IFLA_VF_LINK_STATE_DISABLE:
2051                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2052         case IFLA_VF_LINK_STATE_ENABLE:
2053                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2054         }
2055         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2056 }
2057
2058 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2059                                    int link_state)
2060 {
2061         struct mlx5e_priv *priv = netdev_priv(dev);
2062         struct mlx5_core_dev *mdev = priv->mdev;
2063
2064         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2065                                             mlx5_ifla_link2vport(link_state));
2066 }
2067
2068 static int mlx5e_get_vf_config(struct net_device *dev,
2069                                int vf, struct ifla_vf_info *ivi)
2070 {
2071         struct mlx5e_priv *priv = netdev_priv(dev);
2072         struct mlx5_core_dev *mdev = priv->mdev;
2073         int err;
2074
2075         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2076         if (err)
2077                 return err;
2078         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2079         return 0;
2080 }
2081
2082 static int mlx5e_get_vf_stats(struct net_device *dev,
2083                               int vf, struct ifla_vf_stats *vf_stats)
2084 {
2085         struct mlx5e_priv *priv = netdev_priv(dev);
2086         struct mlx5_core_dev *mdev = priv->mdev;
2087
2088         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2089                                             vf_stats);
2090 }
2091
2092 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2093                                  sa_family_t sa_family, __be16 port)
2094 {
2095         struct mlx5e_priv *priv = netdev_priv(netdev);
2096
2097         if (!mlx5e_vxlan_allowed(priv->mdev))
2098                 return;
2099
2100         mlx5e_vxlan_add_port(priv, be16_to_cpu(port));
2101 }
2102
2103 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2104                                  sa_family_t sa_family, __be16 port)
2105 {
2106         struct mlx5e_priv *priv = netdev_priv(netdev);
2107
2108         if (!mlx5e_vxlan_allowed(priv->mdev))
2109                 return;
2110
2111         mlx5e_vxlan_del_port(priv, be16_to_cpu(port));
2112 }
2113
2114 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2115                                                     struct sk_buff *skb,
2116                                                     netdev_features_t features)
2117 {
2118         struct udphdr *udph;
2119         u16 proto;
2120         u16 port = 0;
2121
2122         switch (vlan_get_protocol(skb)) {
2123         case htons(ETH_P_IP):
2124                 proto = ip_hdr(skb)->protocol;
2125                 break;
2126         case htons(ETH_P_IPV6):
2127                 proto = ipv6_hdr(skb)->nexthdr;
2128                 break;
2129         default:
2130                 goto out;
2131         }
2132
2133         if (proto == IPPROTO_UDP) {
2134                 udph = udp_hdr(skb);
2135                 port = be16_to_cpu(udph->dest);
2136         }
2137
2138         /* Verify if UDP port is being offloaded by HW */
2139         if (port && mlx5e_vxlan_lookup_port(priv, port))
2140                 return features;
2141
2142 out:
2143         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2144         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2145 }
2146
2147 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2148                                               struct net_device *netdev,
2149                                               netdev_features_t features)
2150 {
2151         struct mlx5e_priv *priv = netdev_priv(netdev);
2152
2153         features = vlan_features_check(skb, features);
2154         features = vxlan_features_check(skb, features);
2155
2156         /* Validate if the tunneled packet is being offloaded by HW */
2157         if (skb->encapsulation &&
2158             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2159                 return mlx5e_vxlan_features_check(priv, skb, features);
2160
2161         return features;
2162 }
2163
2164 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2165         .ndo_open                = mlx5e_open,
2166         .ndo_stop                = mlx5e_close,
2167         .ndo_start_xmit          = mlx5e_xmit,
2168         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2169         .ndo_select_queue        = mlx5e_select_queue,
2170         .ndo_get_stats64         = mlx5e_get_stats,
2171         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2172         .ndo_set_mac_address     = mlx5e_set_mac,
2173         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2174         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2175         .ndo_set_features        = mlx5e_set_features,
2176         .ndo_change_mtu          = mlx5e_change_mtu,
2177         .ndo_do_ioctl            = mlx5e_ioctl,
2178 };
2179
2180 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2181         .ndo_open                = mlx5e_open,
2182         .ndo_stop                = mlx5e_close,
2183         .ndo_start_xmit          = mlx5e_xmit,
2184         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2185         .ndo_select_queue        = mlx5e_select_queue,
2186         .ndo_get_stats64         = mlx5e_get_stats,
2187         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2188         .ndo_set_mac_address     = mlx5e_set_mac,
2189         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2190         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2191         .ndo_set_features        = mlx5e_set_features,
2192         .ndo_change_mtu          = mlx5e_change_mtu,
2193         .ndo_do_ioctl            = mlx5e_ioctl,
2194         .ndo_add_vxlan_port      = mlx5e_add_vxlan_port,
2195         .ndo_del_vxlan_port      = mlx5e_del_vxlan_port,
2196         .ndo_features_check      = mlx5e_features_check,
2197         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2198         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2199         .ndo_get_vf_config       = mlx5e_get_vf_config,
2200         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2201         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2202 };
2203
2204 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2205 {
2206         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2207                 return -ENOTSUPP;
2208         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2209             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2210             !MLX5_CAP_ETH(mdev, csum_cap) ||
2211             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2212             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2213             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2214             MLX5_CAP_FLOWTABLE(mdev,
2215                                flow_table_properties_nic_receive.max_ft_level)
2216                                < 3) {
2217                 mlx5_core_warn(mdev,
2218                                "Not creating net device, some required device capabilities are missing\n");
2219                 return -ENOTSUPP;
2220         }
2221         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2222                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2223         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2224                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2225
2226         return 0;
2227 }
2228
2229 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2230 {
2231         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2232
2233         return bf_buf_size -
2234                sizeof(struct mlx5e_tx_wqe) +
2235                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2236 }
2237
2238 #ifdef CONFIG_MLX5_CORE_EN_DCB
2239 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2240 {
2241         int i;
2242
2243         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2244         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2245                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2246                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2247                 priv->params.ets.prio_tc[i] = i;
2248         }
2249
2250         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2251         priv->params.ets.prio_tc[0] = 1;
2252         priv->params.ets.prio_tc[1] = 0;
2253 }
2254 #endif
2255
2256 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2257                                     struct net_device *netdev,
2258                                     int num_channels)
2259 {
2260         struct mlx5e_priv *priv = netdev_priv(netdev);
2261         int i;
2262
2263         priv->params.log_sq_size           =
2264                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2265         priv->params.log_rq_size           =
2266                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2267         priv->params.rx_cq_moderation_usec =
2268                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2269         priv->params.rx_cq_moderation_pkts =
2270                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2271         priv->params.tx_cq_moderation_usec =
2272                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2273         priv->params.tx_cq_moderation_pkts =
2274                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2275         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
2276         priv->params.min_rx_wqes           =
2277                 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2278         priv->params.num_tc                = 1;
2279         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2280
2281         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2282                             sizeof(priv->params.toeplitz_hash_key));
2283
2284         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++)
2285                 priv->params.indirection_rqt[i] = i % num_channels;
2286
2287         priv->params.lro_wqe_sz            =
2288                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2289
2290         priv->mdev                         = mdev;
2291         priv->netdev                       = netdev;
2292         priv->params.num_channels          = num_channels;
2293
2294 #ifdef CONFIG_MLX5_CORE_EN_DCB
2295         mlx5e_ets_init(priv);
2296 #endif
2297
2298         mutex_init(&priv->state_lock);
2299
2300         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2301         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2302         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2303 }
2304
2305 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2306 {
2307         struct mlx5e_priv *priv = netdev_priv(netdev);
2308
2309         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2310         if (is_zero_ether_addr(netdev->dev_addr) &&
2311             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2312                 eth_hw_addr_random(netdev);
2313                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2314         }
2315 }
2316
2317 static void mlx5e_build_netdev(struct net_device *netdev)
2318 {
2319         struct mlx5e_priv *priv = netdev_priv(netdev);
2320         struct mlx5_core_dev *mdev = priv->mdev;
2321
2322         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2323
2324         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2325                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2326 #ifdef CONFIG_MLX5_CORE_EN_DCB
2327                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2328 #endif
2329         } else {
2330                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2331         }
2332
2333         netdev->watchdog_timeo    = 15 * HZ;
2334
2335         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
2336
2337         netdev->vlan_features    |= NETIF_F_SG;
2338         netdev->vlan_features    |= NETIF_F_IP_CSUM;
2339         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
2340         netdev->vlan_features    |= NETIF_F_GRO;
2341         netdev->vlan_features    |= NETIF_F_TSO;
2342         netdev->vlan_features    |= NETIF_F_TSO6;
2343         netdev->vlan_features    |= NETIF_F_RXCSUM;
2344         netdev->vlan_features    |= NETIF_F_RXHASH;
2345
2346         if (!!MLX5_CAP_ETH(mdev, lro_cap))
2347                 netdev->vlan_features    |= NETIF_F_LRO;
2348
2349         netdev->hw_features       = netdev->vlan_features;
2350         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
2351         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
2352         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
2353
2354         if (mlx5e_vxlan_allowed(mdev)) {
2355                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL;
2356                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2357                 netdev->hw_enc_features |= NETIF_F_RXCSUM;
2358                 netdev->hw_enc_features |= NETIF_F_TSO;
2359                 netdev->hw_enc_features |= NETIF_F_TSO6;
2360                 netdev->hw_enc_features |= NETIF_F_RXHASH;
2361                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2362         }
2363
2364         netdev->features          = netdev->hw_features;
2365         if (!priv->params.lro_en)
2366                 netdev->features  &= ~NETIF_F_LRO;
2367
2368         netdev->features         |= NETIF_F_HIGHDMA;
2369
2370         netdev->priv_flags       |= IFF_UNICAST_FLT;
2371
2372         mlx5e_set_netdev_dev_addr(netdev);
2373 }
2374
2375 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2376                              struct mlx5_core_mr *mr)
2377 {
2378         struct mlx5_core_dev *mdev = priv->mdev;
2379         struct mlx5_create_mkey_mbox_in *in;
2380         int err;
2381
2382         in = mlx5_vzalloc(sizeof(*in));
2383         if (!in)
2384                 return -ENOMEM;
2385
2386         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2387                         MLX5_PERM_LOCAL_READ  |
2388                         MLX5_ACCESS_MODE_PA;
2389         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2390         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2391
2392         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2393                                     NULL);
2394
2395         kvfree(in);
2396
2397         return err;
2398 }
2399
2400 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2401 {
2402         struct net_device *netdev;
2403         struct mlx5e_priv *priv;
2404         int nch = mlx5e_get_max_num_channels(mdev);
2405         int err;
2406
2407         if (mlx5e_check_required_hca_cap(mdev))
2408                 return NULL;
2409
2410         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2411                                     nch * MLX5E_MAX_NUM_TC,
2412                                     nch);
2413         if (!netdev) {
2414                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2415                 return NULL;
2416         }
2417
2418         mlx5e_build_netdev_priv(mdev, netdev, nch);
2419         mlx5e_build_netdev(netdev);
2420
2421         netif_carrier_off(netdev);
2422
2423         priv = netdev_priv(netdev);
2424
2425         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
2426         if (err) {
2427                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2428                 goto err_free_netdev;
2429         }
2430
2431         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2432         if (err) {
2433                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2434                 goto err_unmap_free_uar;
2435         }
2436
2437         err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
2438         if (err) {
2439                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2440                 goto err_dealloc_pd;
2441         }
2442
2443         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2444         if (err) {
2445                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2446                 goto err_dealloc_transport_domain;
2447         }
2448
2449         err = mlx5e_create_tises(priv);
2450         if (err) {
2451                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2452                 goto err_destroy_mkey;
2453         }
2454
2455         err = mlx5e_open_drop_rq(priv);
2456         if (err) {
2457                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2458                 goto err_destroy_tises;
2459         }
2460
2461         err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
2462         if (err) {
2463                 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
2464                 goto err_close_drop_rq;
2465         }
2466
2467         err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2468         if (err) {
2469                 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2470                 goto err_destroy_rqt_indir;
2471         }
2472
2473         err = mlx5e_create_tirs(priv);
2474         if (err) {
2475                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2476                 goto err_destroy_rqt_single;
2477         }
2478
2479         err = mlx5e_create_flow_tables(priv);
2480         if (err) {
2481                 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2482                 goto err_destroy_tirs;
2483         }
2484
2485         mlx5e_init_eth_addr(priv);
2486
2487         mlx5e_vxlan_init(priv);
2488
2489 #ifdef CONFIG_MLX5_CORE_EN_DCB
2490         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2491 #endif
2492
2493         err = register_netdev(netdev);
2494         if (err) {
2495                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2496                 goto err_destroy_flow_tables;
2497         }
2498
2499         if (mlx5e_vxlan_allowed(mdev))
2500                 vxlan_get_rx_port(netdev);
2501
2502         mlx5e_enable_async_events(priv);
2503         schedule_work(&priv->set_rx_mode_work);
2504
2505         return priv;
2506
2507 err_destroy_flow_tables:
2508         mlx5e_destroy_flow_tables(priv);
2509
2510 err_destroy_tirs:
2511         mlx5e_destroy_tirs(priv);
2512
2513 err_destroy_rqt_single:
2514         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2515
2516 err_destroy_rqt_indir:
2517         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2518
2519 err_close_drop_rq:
2520         mlx5e_close_drop_rq(priv);
2521
2522 err_destroy_tises:
2523         mlx5e_destroy_tises(priv);
2524
2525 err_destroy_mkey:
2526         mlx5_core_destroy_mkey(mdev, &priv->mr);
2527
2528 err_dealloc_transport_domain:
2529         mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
2530
2531 err_dealloc_pd:
2532         mlx5_core_dealloc_pd(mdev, priv->pdn);
2533
2534 err_unmap_free_uar:
2535         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2536
2537 err_free_netdev:
2538         free_netdev(netdev);
2539
2540         return NULL;
2541 }
2542
2543 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2544 {
2545         struct mlx5e_priv *priv = vpriv;
2546         struct net_device *netdev = priv->netdev;
2547
2548         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2549
2550         schedule_work(&priv->set_rx_mode_work);
2551         mlx5e_disable_async_events(priv);
2552         flush_scheduled_work();
2553         unregister_netdev(netdev);
2554         mlx5e_vxlan_cleanup(priv);
2555         mlx5e_destroy_flow_tables(priv);
2556         mlx5e_destroy_tirs(priv);
2557         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2558         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2559         mlx5e_close_drop_rq(priv);
2560         mlx5e_destroy_tises(priv);
2561         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
2562         mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
2563         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2564         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2565         free_netdev(netdev);
2566 }
2567
2568 static void *mlx5e_get_netdev(void *vpriv)
2569 {
2570         struct mlx5e_priv *priv = vpriv;
2571
2572         return priv->netdev;
2573 }
2574
2575 static struct mlx5_interface mlx5e_interface = {
2576         .add       = mlx5e_create_netdev,
2577         .remove    = mlx5e_destroy_netdev,
2578         .event     = mlx5e_async_event,
2579         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
2580         .get_dev   = mlx5e_get_netdev,
2581 };
2582
2583 void mlx5e_init(void)
2584 {
2585         mlx5_register_interface(&mlx5e_interface);
2586 }
2587
2588 void mlx5e_cleanup(void)
2589 {
2590         mlx5_unregister_interface(&mlx5e_interface);
2591 }