drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include "en.h"
  39 #include "en_tc.h"
  40 #include "eswitch.h"
  41 #include "vxlan.h"
  42
  43 struct mlx5e_rq_param {
  44         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  45         struct mlx5_wq_param    wq;
  46         bool                    am_enabled;
  47 };
  48
  49 struct mlx5e_sq_param {
  50         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  51         struct mlx5_wq_param       wq;
  52         u16                        max_inline;
  53         u8                         min_inline_mode;
  54         enum mlx5e_sq_type         type;
  55 };
  56
  57 struct mlx5e_cq_param {
  58         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  59         struct mlx5_wq_param       wq;
  60         u16                        eq_ix;
  61         u8                         cq_period_mode;
  62 };
  63
  64 struct mlx5e_channel_param {
  65         struct mlx5e_rq_param      rq;
  66         struct mlx5e_sq_param      sq;
  67         struct mlx5e_sq_param      icosq;
  68         struct mlx5e_cq_param      rx_cq;
  69         struct mlx5e_cq_param      tx_cq;
  70         struct mlx5e_cq_param      icosq_cq;
  71 };
  72
  73 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  74 {
  75         return MLX5_CAP_GEN(mdev, striding_rq) &&
  76                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  77                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  78 }
  79
  80 static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
  81 {
  82         priv->params.rq_wq_type = rq_type;
  83         switch (priv->params.rq_wq_type) {
  84         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
  85                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
  86                 priv->params.mpwqe_log_stride_sz = priv->params.rx_cqe_compress ?
  87                         MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
  88                         MLX5_MPWRQ_LOG_STRIDE_SIZE;
  89                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
  90                         priv->params.mpwqe_log_stride_sz;
  91                 break;
  92         default: /* MLX5_WQ_TYPE_LINKED_LIST */
  93                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
  94         }
  95         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
  96                                                BIT(priv->params.log_rq_size));
  97
  98         mlx5_core_info(priv->mdev,
  99                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 100                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 101                        BIT(priv->params.log_rq_size),
 102                        BIT(priv->params.mpwqe_log_stride_sz),
 103                        priv->params.rx_cqe_compress_admin);
 104 }
 105
 106 static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
 107 {
 108         u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
 109                     !priv->xdp_prog ?
 110                     MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 111                     MLX5_WQ_TYPE_LINKED_LIST;
 112         mlx5e_set_rq_type_params(priv, rq_type);
 113 }
 114
 115 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 116 {
 117         struct mlx5_core_dev *mdev = priv->mdev;
 118         u8 port_state;
 119
 120         port_state = mlx5_query_vport_state(mdev,
 121                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 122
 123         if (port_state == VPORT_STATE_UP) {
 124                 netdev_info(priv->netdev, "Link up\n");
 125                 netif_carrier_on(priv->netdev);
 126         } else {
 127                 netdev_info(priv->netdev, "Link down\n");
 128                 netif_carrier_off(priv->netdev);
 129         }
 130 }
 131
 132 static void mlx5e_update_carrier_work(struct work_struct *work)
 133 {
 134         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 135                                                update_carrier_work);
 136
 137         mutex_lock(&priv->state_lock);
 138         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 139                 mlx5e_update_carrier(priv);
 140         mutex_unlock(&priv->state_lock);
 141 }
 142
 143 static void mlx5e_tx_timeout_work(struct work_struct *work)
 144 {
 145         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 146                                                tx_timeout_work);
 147         int err;
 148
 149         rtnl_lock();
 150         mutex_lock(&priv->state_lock);
 151         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 152                 goto unlock;
 153         mlx5e_close_locked(priv->netdev);
 154         err = mlx5e_open_locked(priv->netdev);
 155         if (err)
 156                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 157                            err);
 158 unlock:
 159         mutex_unlock(&priv->state_lock);
 160         rtnl_unlock();
 161 }
 162
 163 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 164 {
 165         struct mlx5e_sw_stats *s = &priv->stats.sw;
 166         struct mlx5e_rq_stats *rq_stats;
 167         struct mlx5e_sq_stats *sq_stats;
 168         u64 tx_offload_none = 0;
 169         int i, j;
 170
 171         memset(s, 0, sizeof(*s));
 172         for (i = 0; i < priv->params.num_channels; i++) {
 173                 rq_stats = &priv->channel[i]->rq.stats;
 174
 175                 s->rx_packets   += rq_stats->packets;
 176                 s->rx_bytes     += rq_stats->bytes;
 177                 s->rx_lro_packets += rq_stats->lro_packets;
 178                 s->rx_lro_bytes += rq_stats->lro_bytes;
 179                 s->rx_csum_none += rq_stats->csum_none;
 180                 s->rx_csum_complete += rq_stats->csum_complete;
 181                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 182                 s->rx_xdp_drop += rq_stats->xdp_drop;
 183                 s->rx_wqe_err   += rq_stats->wqe_err;
 184                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 185                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 186                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 187                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 188                 s->rx_cache_reuse += rq_stats->cache_reuse;
 189                 s->rx_cache_full  += rq_stats->cache_full;
 190                 s->rx_cache_empty += rq_stats->cache_empty;
 191                 s->rx_cache_busy  += rq_stats->cache_busy;
 192
 193                 for (j = 0; j < priv->params.num_tc; j++) {
 194                         sq_stats = &priv->channel[i]->sq[j].stats;
 195
 196                         s->tx_packets           += sq_stats->packets;
 197                         s->tx_bytes             += sq_stats->bytes;
 198                         s->tx_tso_packets       += sq_stats->tso_packets;
 199                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 200                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 201                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 202                         s->tx_queue_stopped     += sq_stats->stopped;
 203                         s->tx_queue_wake        += sq_stats->wake;
 204                         s->tx_queue_dropped     += sq_stats->dropped;
 205                         s->tx_xmit_more         += sq_stats->xmit_more;
 206                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 207                         tx_offload_none         += sq_stats->csum_none;
 208                 }
 209         }
 210
 211         /* Update calculated offload counters */
 212         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
 213         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 214
 215         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 216                                 priv->stats.pport.phy_counters,
 217                                 counter_set.phys_layer_cntrs.link_down_events);
 218 }
 219
 220 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 221 {
 222         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 223         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 224         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
 225         struct mlx5_core_dev *mdev = priv->mdev;
 226
 227         MLX5_SET(query_vport_counter_in, in, opcode,
 228                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 229         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 230         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 231
 232         memset(out, 0, outlen);
 233         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 234 }
 235
 236 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 237 {
 238         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 239         struct mlx5_core_dev *mdev = priv->mdev;
 240         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 241         int prio;
 242         void *out;
 243         u32 *in;
 244
 245         in = mlx5_vzalloc(sz);
 246         if (!in)
 247                 goto free_out;
 248
 249         MLX5_SET(ppcnt_reg, in, local_port, 1);
 250
 251         out = pstats->IEEE_802_3_counters;
 252         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 253         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 254
 255         out = pstats->RFC_2863_counters;
 256         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 257         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 258
 259         out = pstats->RFC_2819_counters;
 260         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 261         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 262
 263         out = pstats->phy_counters;
 264         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 265         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 266
 267         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 268         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 269                 out = pstats->per_prio_counters[prio];
 270                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 271                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 272                                      MLX5_REG_PPCNT, 0, 0);
 273         }
 274
 275 free_out:
 276         kvfree(in);
 277 }
 278
 279 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 280 {
 281         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 282
 283         if (!priv->q_counter)
 284                 return;
 285
 286         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 287                                       &qcnt->rx_out_of_buffer);
 288 }
 289
 290 void mlx5e_update_stats(struct mlx5e_priv *priv)
 291 {
 292         mlx5e_update_q_counter(priv);
 293         mlx5e_update_vport_counters(priv);
 294         mlx5e_update_pport_counters(priv);
 295         mlx5e_update_sw_counters(priv);
 296 }
 297
 298 void mlx5e_update_stats_work(struct work_struct *work)
 299 {
 300         struct delayed_work *dwork = to_delayed_work(work);
 301         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 302                                                update_stats_work);
 303         mutex_lock(&priv->state_lock);
 304         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 305                 priv->profile->update_stats(priv);
 306                 queue_delayed_work(priv->wq, dwork,
 307                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 308         }
 309         mutex_unlock(&priv->state_lock);
 310 }
 311
 312 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 313                               enum mlx5_dev_event event, unsigned long param)
 314 {
 315         struct mlx5e_priv *priv = vpriv;
 316
 317         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 318                 return;
 319
 320         switch (event) {
 321         case MLX5_DEV_EVENT_PORT_UP:
 322         case MLX5_DEV_EVENT_PORT_DOWN:
 323                 queue_work(priv->wq, &priv->update_carrier_work);
 324                 break;
 325
 326         default:
 327                 break;
 328         }
 329 }
 330
 331 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 332 {
 333         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 334 }
 335
 336 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 337 {
 338         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 339         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 340 }
 341
 342 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 343 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 344
 345 static inline int mlx5e_get_wqe_mtt_sz(void)
 346 {
 347         /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
 348          * To avoid copying garbage after the mtt array, we allocate
 349          * a little more.
 350          */
 351         return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
 352                      MLX5_UMR_MTT_ALIGNMENT);
 353 }
 354
 355 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
 356                                        struct mlx5e_umr_wqe *wqe, u16 ix)
 357 {
 358         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 359         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 360         struct mlx5_wqe_data_seg      *dseg = &wqe->data;
 361         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 362         u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
 363         u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
 364
 365         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 366                                       ds_cnt);
 367         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 368         cseg->imm       = rq->mkey_be;
 369
 370         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
 371         ucseg->klm_octowords =
 372                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 373         ucseg->bsf_octowords =
 374                 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
 375         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 376
 377         dseg->lkey = sq->mkey_be;
 378         dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
 379 }
 380
 381 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 382                                      struct mlx5e_channel *c)
 383 {
 384         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 385         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 386         int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
 387         int i;
 388
 389         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
 390                                       GFP_KERNEL, cpu_to_node(c->cpu));
 391         if (!rq->mpwqe.info)
 392                 goto err_out;
 393
 394         /* We allocate more than mtt_sz as we will align the pointer */
 395         rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
 396                                         cpu_to_node(c->cpu));
 397         if (unlikely(!rq->mpwqe.mtt_no_align))
 398                 goto err_free_wqe_info;
 399
 400         for (i = 0; i < wq_sz; i++) {
 401                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 402
 403                 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
 404                                         MLX5_UMR_ALIGN);
 405                 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
 406                                                   PCI_DMA_TODEVICE);
 407                 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
 408                         goto err_unmap_mtts;
 409
 410                 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
 411         }
 412
 413         return 0;
 414
 415 err_unmap_mtts:
 416         while (--i >= 0) {
 417                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 418
 419                 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
 420                                  PCI_DMA_TODEVICE);
 421         }
 422         kfree(rq->mpwqe.mtt_no_align);
 423 err_free_wqe_info:
 424         kfree(rq->mpwqe.info);
 425
 426 err_out:
 427         return -ENOMEM;
 428 }
 429
 430 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
 431 {
 432         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 433         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 434         int i;
 435
 436         for (i = 0; i < wq_sz; i++) {
 437                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 438
 439                 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
 440                                  PCI_DMA_TODEVICE);
 441         }
 442         kfree(rq->mpwqe.mtt_no_align);
 443         kfree(rq->mpwqe.info);
 444 }
 445
 446 static int mlx5e_create_rq(struct mlx5e_channel *c,
 447                            struct mlx5e_rq_param *param,
 448                            struct mlx5e_rq *rq)
 449 {
 450         struct mlx5e_priv *priv = c->priv;
 451         struct mlx5_core_dev *mdev = priv->mdev;
 452         void *rqc = param->rqc;
 453         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 454         u32 byte_count;
 455         u32 frag_sz;
 456         int npages;
 457         int wq_sz;
 458         int err;
 459         int i;
 460
 461         param->wq.db_numa_node = cpu_to_node(c->cpu);
 462
 463         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 464                                 &rq->wq_ctrl);
 465         if (err)
 466                 return err;
 467
 468         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 469
 470         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 471
 472         rq->wq_type = priv->params.rq_wq_type;
 473         rq->pdev    = c->pdev;
 474         rq->netdev  = c->netdev;
 475         rq->tstamp  = &priv->tstamp;
 476         rq->channel = c;
 477         rq->ix      = c->ix;
 478         rq->priv    = c->priv;
 479         rq->xdp_prog = priv->xdp_prog;
 480
 481         switch (priv->params.rq_wq_type) {
 482         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 483                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 484                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 485                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 486
 487                 rq->mpwqe.mtt_offset = c->ix *
 488                         MLX5E_REQUIRED_MTTS(1, BIT(priv->params.log_rq_size));
 489
 490                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 491                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 492
 493                 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 494                 byte_count = rq->buff.wqe_sz;
 495                 rq->mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 496                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 497                 if (err)
 498                         goto err_rq_wq_destroy;
 499                 break;
 500         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 501                 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
 502                                             GFP_KERNEL, cpu_to_node(c->cpu));
 503                 if (!rq->dma_info) {
 504                         err = -ENOMEM;
 505                         goto err_rq_wq_destroy;
 506                 }
 507
 508                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 509                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 510                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 511
 512                 rq->buff.wqe_sz = (priv->params.lro_en) ?
 513                                 priv->params.lro_wqe_sz :
 514                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 515                 byte_count = rq->buff.wqe_sz;
 516
 517                 /* calc the required page order */
 518                 frag_sz = MLX5_RX_HEADROOM +
 519                           byte_count /* packet data */ +
 520                           SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 521                 frag_sz = SKB_DATA_ALIGN(frag_sz);
 522
 523                 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
 524                 rq->buff.page_order = order_base_2(npages);
 525
 526                 byte_count |= MLX5_HW_START_PADDING;
 527                 rq->mkey_be = c->mkey_be;
 528         }
 529
 530         for (i = 0; i < wq_sz; i++) {
 531                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 532
 533                 wqe->data.byte_count = cpu_to_be32(byte_count);
 534                 wqe->data.lkey = rq->mkey_be;
 535         }
 536
 537         INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
 538         rq->am.mode = priv->params.rx_cq_period_mode;
 539
 540         rq->page_cache.head = 0;
 541         rq->page_cache.tail = 0;
 542
 543         if (rq->xdp_prog)
 544                 bpf_prog_add(rq->xdp_prog, 1);
 545
 546         return 0;
 547
 548 err_rq_wq_destroy:
 549         mlx5_wq_destroy(&rq->wq_ctrl);
 550
 551         return err;
 552 }
 553
 554 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 555 {
 556         int i;
 557
 558         if (rq->xdp_prog)
 559                 bpf_prog_put(rq->xdp_prog);
 560
 561         switch (rq->wq_type) {
 562         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 563                 mlx5e_rq_free_mpwqe_info(rq);
 564                 break;
 565         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 566                 kfree(rq->dma_info);
 567         }
 568
 569         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 570              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 571                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 572
 573                 mlx5e_page_release(rq, dma_info, false);
 574         }
 575         mlx5_wq_destroy(&rq->wq_ctrl);
 576 }
 577
 578 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 579 {
 580         struct mlx5e_priv *priv = rq->priv;
 581         struct mlx5_core_dev *mdev = priv->mdev;
 582
 583         void *in;
 584         void *rqc;
 585         void *wq;
 586         int inlen;
 587         int err;
 588
 589         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 590                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 591         in = mlx5_vzalloc(inlen);
 592         if (!in)
 593                 return -ENOMEM;
 594
 595         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 596         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 597
 598         memcpy(rqc, param->rqc, sizeof(param->rqc));
 599
 600         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 601         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 602         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 603         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 604                                                 MLX5_ADAPTER_PAGE_SHIFT);
 605         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 606
 607         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 608                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 609
 610         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 611
 612         kvfree(in);
 613
 614         return err;
 615 }
 616
 617 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 618                                  int next_state)
 619 {
 620         struct mlx5e_channel *c = rq->channel;
 621         struct mlx5e_priv *priv = c->priv;
 622         struct mlx5_core_dev *mdev = priv->mdev;
 623
 624         void *in;
 625         void *rqc;
 626         int inlen;
 627         int err;
 628
 629         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 630         in = mlx5_vzalloc(inlen);
 631         if (!in)
 632                 return -ENOMEM;
 633
 634         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 635
 636         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 637         MLX5_SET(rqc, rqc, state, next_state);
 638
 639         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 640
 641         kvfree(in);
 642
 643         return err;
 644 }
 645
 646 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 647 {
 648         struct mlx5e_channel *c = rq->channel;
 649         struct mlx5e_priv *priv = c->priv;
 650         struct mlx5_core_dev *mdev = priv->mdev;
 651
 652         void *in;
 653         void *rqc;
 654         int inlen;
 655         int err;
 656
 657         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 658         in = mlx5_vzalloc(inlen);
 659         if (!in)
 660                 return -ENOMEM;
 661
 662         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 663
 664         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 665         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 666                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 667         MLX5_SET(rqc, rqc, vsd, vsd);
 668         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 669
 670         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 671
 672         kvfree(in);
 673
 674         return err;
 675 }
 676
 677 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 678 {
 679         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 680 }
 681
 682 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 683 {
 684         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 685         struct mlx5e_channel *c = rq->channel;
 686         struct mlx5e_priv *priv = c->priv;
 687         struct mlx5_wq_ll *wq = &rq->wq;
 688
 689         while (time_before(jiffies, exp_time)) {
 690                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 691                         return 0;
 692
 693                 msleep(20);
 694         }
 695
 696         return -ETIMEDOUT;
 697 }
 698
 699 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 700 {
 701         struct mlx5_wq_ll *wq = &rq->wq;
 702         struct mlx5e_rx_wqe *wqe;
 703         __be16 wqe_ix_be;
 704         u16 wqe_ix;
 705
 706         /* UMR WQE (if in progress) is always at wq->head */
 707         if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
 708                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 709
 710         while (!mlx5_wq_ll_is_empty(wq)) {
 711                 wqe_ix_be = *wq->tail_next;
 712                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 713                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 714                 rq->dealloc_wqe(rq, wqe_ix);
 715                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 716                                &wqe->next.next_wqe_index);
 717         }
 718 }
 719
 720 static int mlx5e_open_rq(struct mlx5e_channel *c,
 721                          struct mlx5e_rq_param *param,
 722                          struct mlx5e_rq *rq)
 723 {
 724         struct mlx5e_sq *sq = &c->icosq;
 725         u16 pi = sq->pc & sq->wq.sz_m1;
 726         int err;
 727
 728         err = mlx5e_create_rq(c, param, rq);
 729         if (err)
 730                 return err;
 731
 732         err = mlx5e_enable_rq(rq, param);
 733         if (err)
 734                 goto err_destroy_rq;
 735
 736         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 737         if (err)
 738                 goto err_disable_rq;
 739
 740         if (param->am_enabled)
 741                 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 742
 743         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 744         sq->db.ico_wqe[pi].num_wqebbs = 1;
 745         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 746
 747         return 0;
 748
 749 err_disable_rq:
 750         mlx5e_disable_rq(rq);
 751 err_destroy_rq:
 752         mlx5e_destroy_rq(rq);
 753
 754         return err;
 755 }
 756
 757 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 758 {
 759         set_bit(MLX5E_RQ_STATE_FLUSH, &rq->state);
 760         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 761         cancel_work_sync(&rq->am.work);
 762
 763         mlx5e_disable_rq(rq);
 764         mlx5e_free_rx_descs(rq);
 765         mlx5e_destroy_rq(rq);
 766 }
 767
 768 static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
 769 {
 770         kfree(sq->db.ico_wqe);
 771 }
 772
 773 static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
 774 {
 775         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 776
 777         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
 778                                       GFP_KERNEL, numa);
 779         if (!sq->db.ico_wqe)
 780                 return -ENOMEM;
 781
 782         return 0;
 783 }
 784
 785 static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
 786 {
 787         kfree(sq->db.txq.wqe_info);
 788         kfree(sq->db.txq.dma_fifo);
 789         kfree(sq->db.txq.skb);
 790 }
 791
 792 static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
 793 {
 794         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 795         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 796
 797         sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
 798                                       GFP_KERNEL, numa);
 799         sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
 800                                            GFP_KERNEL, numa);
 801         sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
 802                                            GFP_KERNEL, numa);
 803         if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
 804                 mlx5e_free_sq_txq_db(sq);
 805                 return -ENOMEM;
 806         }
 807
 808         sq->dma_fifo_mask = df_sz - 1;
 809
 810         return 0;
 811 }
 812
 813 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 814 {
 815         switch (sq->type) {
 816         case MLX5E_SQ_TXQ:
 817                 mlx5e_free_sq_txq_db(sq);
 818                 break;
 819         case MLX5E_SQ_ICO:
 820                 mlx5e_free_sq_ico_db(sq);
 821                 break;
 822         }
 823 }
 824
 825 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 826 {
 827         switch (sq->type) {
 828         case MLX5E_SQ_TXQ:
 829                 return mlx5e_alloc_sq_txq_db(sq, numa);
 830         case MLX5E_SQ_ICO:
 831                 return mlx5e_alloc_sq_ico_db(sq, numa);
 832         }
 833
 834         return 0;
 835 }
 836
 837 static int mlx5e_create_sq(struct mlx5e_channel *c,
 838                            int tc,
 839                            struct mlx5e_sq_param *param,
 840                            struct mlx5e_sq *sq)
 841 {
 842         struct mlx5e_priv *priv = c->priv;
 843         struct mlx5_core_dev *mdev = priv->mdev;
 844
 845         void *sqc = param->sqc;
 846         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 847         u16 sq_max_wqebbs;
 848         int err;
 849
 850         sq->type      = param->type;
 851         sq->pdev      = c->pdev;
 852         sq->tstamp    = &priv->tstamp;
 853         sq->mkey_be   = c->mkey_be;
 854         sq->channel   = c;
 855         sq->tc        = tc;
 856
 857         err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
 858         if (err)
 859                 return err;
 860
 861         param->wq.db_numa_node = cpu_to_node(c->cpu);
 862
 863         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 864                                  &sq->wq_ctrl);
 865         if (err)
 866                 goto err_unmap_free_uar;
 867
 868         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 869         if (sq->uar.bf_map) {
 870                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 871                 sq->uar_map = sq->uar.bf_map;
 872         } else {
 873                 sq->uar_map = sq->uar.map;
 874         }
 875         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 876         sq->max_inline  = param->max_inline;
 877         sq->min_inline_mode =
 878                 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
 879                 param->min_inline_mode : 0;
 880
 881         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 882         if (err)
 883                 goto err_sq_wq_destroy;
 884
 885         sq_max_wqebbs = MLX5_SEND_WQE_MAX_WQEBBS;
 886         if (sq->type == MLX5E_SQ_TXQ) {
 887                 int txq_ix;
 888
 889                 txq_ix = c->ix + tc * priv->params.num_channels;
 890                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 891                 priv->txq_to_sq_map[txq_ix] = sq;
 892         }
 893
 894         if (sq->type == MLX5E_SQ_ICO)
 895                 sq_max_wqebbs = MLX5E_ICOSQ_MAX_WQEBBS;
 896
 897         sq->edge      = (sq->wq.sz_m1 + 1) - sq_max_wqebbs;
 898         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 899
 900         return 0;
 901
 902 err_sq_wq_destroy:
 903         mlx5_wq_destroy(&sq->wq_ctrl);
 904
 905 err_unmap_free_uar:
 906         mlx5_unmap_free_uar(mdev, &sq->uar);
 907
 908         return err;
 909 }
 910
 911 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 912 {
 913         struct mlx5e_channel *c = sq->channel;
 914         struct mlx5e_priv *priv = c->priv;
 915
 916         mlx5e_free_sq_db(sq);
 917         mlx5_wq_destroy(&sq->wq_ctrl);
 918         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 919 }
 920
 921 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 922 {
 923         struct mlx5e_channel *c = sq->channel;
 924         struct mlx5e_priv *priv = c->priv;
 925         struct mlx5_core_dev *mdev = priv->mdev;
 926
 927         void *in;
 928         void *sqc;
 929         void *wq;
 930         int inlen;
 931         int err;
 932
 933         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 934                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 935         in = mlx5_vzalloc(inlen);
 936         if (!in)
 937                 return -ENOMEM;
 938
 939         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 940         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 941
 942         memcpy(sqc, param->sqc, sizeof(param->sqc));
 943
 944         MLX5_SET(sqc,  sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
 945                                        0 : priv->tisn[sq->tc]);
 946         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
 947         MLX5_SET(sqc,  sqc, min_wqe_inline_mode, sq->min_inline_mode);
 948         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 949         MLX5_SET(sqc,  sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
 950         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 951
 952         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 953         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 954         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 955                                           MLX5_ADAPTER_PAGE_SHIFT);
 956         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 957
 958         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 959                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 960
 961         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 962
 963         kvfree(in);
 964
 965         return err;
 966 }
 967
 968 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
 969                            int next_state, bool update_rl, int rl_index)
 970 {
 971         struct mlx5e_channel *c = sq->channel;
 972         struct mlx5e_priv *priv = c->priv;
 973         struct mlx5_core_dev *mdev = priv->mdev;
 974
 975         void *in;
 976         void *sqc;
 977         int inlen;
 978         int err;
 979
 980         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 981         in = mlx5_vzalloc(inlen);
 982         if (!in)
 983                 return -ENOMEM;
 984
 985         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 986
 987         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 988         MLX5_SET(sqc, sqc, state, next_state);
 989         if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
 990                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
 991                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, rl_index);
 992         }
 993
 994         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 995
 996         kvfree(in);
 997
 998         return err;
 999 }
1000
1001 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1002 {
1003         struct mlx5e_channel *c = sq->channel;
1004         struct mlx5e_priv *priv = c->priv;
1005         struct mlx5_core_dev *mdev = priv->mdev;
1006
1007         mlx5_core_destroy_sq(mdev, sq->sqn);
1008         if (sq->rate_limit)
1009                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1010 }
1011
1012 static int mlx5e_open_sq(struct mlx5e_channel *c,
1013                          int tc,
1014                          struct mlx5e_sq_param *param,
1015                          struct mlx5e_sq *sq)
1016 {
1017         int err;
1018
1019         err = mlx5e_create_sq(c, tc, param, sq);
1020         if (err)
1021                 return err;
1022
1023         err = mlx5e_enable_sq(sq, param);
1024         if (err)
1025                 goto err_destroy_sq;
1026
1027         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1028                               false, 0);
1029         if (err)
1030                 goto err_disable_sq;
1031
1032         if (sq->txq) {
1033                 netdev_tx_reset_queue(sq->txq);
1034                 netif_tx_start_queue(sq->txq);
1035         }
1036
1037         return 0;
1038
1039 err_disable_sq:
1040         mlx5e_disable_sq(sq);
1041 err_destroy_sq:
1042         mlx5e_destroy_sq(sq);
1043
1044         return err;
1045 }
1046
1047 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1048 {
1049         __netif_tx_lock_bh(txq);
1050         netif_tx_stop_queue(txq);
1051         __netif_tx_unlock_bh(txq);
1052 }
1053
1054 static void mlx5e_close_sq(struct mlx5e_sq *sq)
1055 {
1056         set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
1057         /* prevent netif_tx_wake_queue */
1058         napi_synchronize(&sq->channel->napi);
1059
1060         if (sq->txq) {
1061                 netif_tx_disable_queue(sq->txq);
1062
1063                 /* last doorbell out, godspeed .. */
1064                 if (mlx5e_sq_has_room_for(sq, 1)) {
1065                         sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
1066                         mlx5e_send_nop(sq, true);
1067                 }
1068         }
1069
1070         mlx5e_disable_sq(sq);
1071         mlx5e_free_tx_descs(sq);
1072         mlx5e_destroy_sq(sq);
1073 }
1074
1075 static int mlx5e_create_cq(struct mlx5e_channel *c,
1076                            struct mlx5e_cq_param *param,
1077                            struct mlx5e_cq *cq)
1078 {
1079         struct mlx5e_priv *priv = c->priv;
1080         struct mlx5_core_dev *mdev = priv->mdev;
1081         struct mlx5_core_cq *mcq = &cq->mcq;
1082         int eqn_not_used;
1083         unsigned int irqn;
1084         int err;
1085         u32 i;
1086
1087         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1088         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1089         param->eq_ix   = c->ix;
1090
1091         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1092                                &cq->wq_ctrl);
1093         if (err)
1094                 return err;
1095
1096         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1097
1098         cq->napi        = &c->napi;
1099
1100         mcq->cqe_sz     = 64;
1101         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1102         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1103         *mcq->set_ci_db = 0;
1104         *mcq->arm_db    = 0;
1105         mcq->vector     = param->eq_ix;
1106         mcq->comp       = mlx5e_completion_event;
1107         mcq->event      = mlx5e_cq_error_event;
1108         mcq->irqn       = irqn;
1109         mcq->uar        = &mdev->mlx5e_res.cq_uar;
1110
1111         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1112                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1113
1114                 cqe->op_own = 0xf1;
1115         }
1116
1117         cq->channel = c;
1118         cq->priv = priv;
1119
1120         return 0;
1121 }
1122
1123 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1124 {
1125         mlx5_wq_destroy(&cq->wq_ctrl);
1126 }
1127
1128 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1129 {
1130         struct mlx5e_priv *priv = cq->priv;
1131         struct mlx5_core_dev *mdev = priv->mdev;
1132         struct mlx5_core_cq *mcq = &cq->mcq;
1133
1134         void *in;
1135         void *cqc;
1136         int inlen;
1137         unsigned int irqn_not_used;
1138         int eqn;
1139         int err;
1140
1141         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1142                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1143         in = mlx5_vzalloc(inlen);
1144         if (!in)
1145                 return -ENOMEM;
1146
1147         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1148
1149         memcpy(cqc, param->cqc, sizeof(param->cqc));
1150
1151         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1152                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1153
1154         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1155
1156         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1157         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1158         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
1159         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1160                                             MLX5_ADAPTER_PAGE_SHIFT);
1161         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1162
1163         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1164
1165         kvfree(in);
1166
1167         if (err)
1168                 return err;
1169
1170         mlx5e_cq_arm(cq);
1171
1172         return 0;
1173 }
1174
1175 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1176 {
1177         struct mlx5e_priv *priv = cq->priv;
1178         struct mlx5_core_dev *mdev = priv->mdev;
1179
1180         mlx5_core_destroy_cq(mdev, &cq->mcq);
1181 }
1182
1183 static int mlx5e_open_cq(struct mlx5e_channel *c,
1184                          struct mlx5e_cq_param *param,
1185                          struct mlx5e_cq *cq,
1186                          struct mlx5e_cq_moder moderation)
1187 {
1188         int err;
1189         struct mlx5e_priv *priv = c->priv;
1190         struct mlx5_core_dev *mdev = priv->mdev;
1191
1192         err = mlx5e_create_cq(c, param, cq);
1193         if (err)
1194                 return err;
1195
1196         err = mlx5e_enable_cq(cq, param);
1197         if (err)
1198                 goto err_destroy_cq;
1199
1200         if (MLX5_CAP_GEN(mdev, cq_moderation))
1201                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1202                                                moderation.usec,
1203                                                moderation.pkts);
1204         return 0;
1205
1206 err_destroy_cq:
1207         mlx5e_destroy_cq(cq);
1208
1209         return err;
1210 }
1211
1212 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1213 {
1214         mlx5e_disable_cq(cq);
1215         mlx5e_destroy_cq(cq);
1216 }
1217
1218 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1219 {
1220         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1221 }
1222
1223 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1224                              struct mlx5e_channel_param *cparam)
1225 {
1226         struct mlx5e_priv *priv = c->priv;
1227         int err;
1228         int tc;
1229
1230         for (tc = 0; tc < c->num_tc; tc++) {
1231                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1232                                     priv->params.tx_cq_moderation);
1233                 if (err)
1234                         goto err_close_tx_cqs;
1235         }
1236
1237         return 0;
1238
1239 err_close_tx_cqs:
1240         for (tc--; tc >= 0; tc--)
1241                 mlx5e_close_cq(&c->sq[tc].cq);
1242
1243         return err;
1244 }
1245
1246 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1247 {
1248         int tc;
1249
1250         for (tc = 0; tc < c->num_tc; tc++)
1251                 mlx5e_close_cq(&c->sq[tc].cq);
1252 }
1253
1254 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1255                           struct mlx5e_channel_param *cparam)
1256 {
1257         int err;
1258         int tc;
1259
1260         for (tc = 0; tc < c->num_tc; tc++) {
1261                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1262                 if (err)
1263                         goto err_close_sqs;
1264         }
1265
1266         return 0;
1267
1268 err_close_sqs:
1269         for (tc--; tc >= 0; tc--)
1270                 mlx5e_close_sq(&c->sq[tc]);
1271
1272         return err;
1273 }
1274
1275 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1276 {
1277         int tc;
1278
1279         for (tc = 0; tc < c->num_tc; tc++)
1280                 mlx5e_close_sq(&c->sq[tc]);
1281 }
1282
1283 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1284 {
1285         int i;
1286
1287         for (i = 0; i < priv->profile->max_tc; i++)
1288                 priv->channeltc_to_txq_map[ix][i] =
1289                         ix + i * priv->params.num_channels;
1290 }
1291
1292 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1293                                 struct mlx5e_sq *sq, u32 rate)
1294 {
1295         struct mlx5e_priv *priv = netdev_priv(dev);
1296         struct mlx5_core_dev *mdev = priv->mdev;
1297         u16 rl_index = 0;
1298         int err;
1299
1300         if (rate == sq->rate_limit)
1301                 /* nothing to do */
1302                 return 0;
1303
1304         if (sq->rate_limit)
1305                 /* remove current rl index to free space to next ones */
1306                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1307
1308         sq->rate_limit = 0;
1309
1310         if (rate) {
1311                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1312                 if (err) {
1313                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1314                                    rate, err);
1315                         return err;
1316                 }
1317         }
1318
1319         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1320                               MLX5_SQC_STATE_RDY, true, rl_index);
1321         if (err) {
1322                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1323                            rate, err);
1324                 /* remove the rate from the table */
1325                 if (rate)
1326                         mlx5_rl_remove_rate(mdev, rate);
1327                 return err;
1328         }
1329
1330         sq->rate_limit = rate;
1331         return 0;
1332 }
1333
1334 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1335 {
1336         struct mlx5e_priv *priv = netdev_priv(dev);
1337         struct mlx5_core_dev *mdev = priv->mdev;
1338         struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1339         int err = 0;
1340
1341         if (!mlx5_rl_is_supported(mdev)) {
1342                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1343                 return -EINVAL;
1344         }
1345
1346         /* rate is given in Mb/sec, HW config is in Kb/sec */
1347         rate = rate << 10;
1348
1349         /* Check whether rate in valid range, 0 is always valid */
1350         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1351                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1352                 return -ERANGE;
1353         }
1354
1355         mutex_lock(&priv->state_lock);
1356         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1357                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1358         if (!err)
1359                 priv->tx_rates[index] = rate;
1360         mutex_unlock(&priv->state_lock);
1361
1362         return err;
1363 }
1364
1365 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1366                               struct mlx5e_channel_param *cparam,
1367                               struct mlx5e_channel **cp)
1368 {
1369         struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1370         struct net_device *netdev = priv->netdev;
1371         struct mlx5e_cq_moder rx_cq_profile;
1372         int cpu = mlx5e_get_cpu(priv, ix);
1373         struct mlx5e_channel *c;
1374         struct mlx5e_sq *sq;
1375         int err;
1376         int i;
1377
1378         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1379         if (!c)
1380                 return -ENOMEM;
1381
1382         c->priv     = priv;
1383         c->ix       = ix;
1384         c->cpu      = cpu;
1385         c->pdev     = &priv->mdev->pdev->dev;
1386         c->netdev   = priv->netdev;
1387         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1388         c->num_tc   = priv->params.num_tc;
1389
1390         if (priv->params.rx_am_enabled)
1391                 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1392         else
1393                 rx_cq_profile = priv->params.rx_cq_moderation;
1394
1395         mlx5e_build_channeltc_to_txq_map(priv, ix);
1396
1397         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1398
1399         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1400         if (err)
1401                 goto err_napi_del;
1402
1403         err = mlx5e_open_tx_cqs(c, cparam);
1404         if (err)
1405                 goto err_close_icosq_cq;
1406
1407         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1408                             rx_cq_profile);
1409         if (err)
1410                 goto err_close_tx_cqs;
1411
1412         napi_enable(&c->napi);
1413
1414         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1415         if (err)
1416                 goto err_disable_napi;
1417
1418         err = mlx5e_open_sqs(c, cparam);
1419         if (err)
1420                 goto err_close_icosq;
1421
1422         for (i = 0; i < priv->params.num_tc; i++) {
1423                 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1424
1425                 if (priv->tx_rates[txq_ix]) {
1426                         sq = priv->txq_to_sq_map[txq_ix];
1427                         mlx5e_set_sq_maxrate(priv->netdev, sq,
1428                                              priv->tx_rates[txq_ix]);
1429                 }
1430         }
1431
1432         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1433         if (err)
1434                 goto err_close_sqs;
1435
1436         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1437         *cp = c;
1438
1439         return 0;
1440
1441 err_close_sqs:
1442         mlx5e_close_sqs(c);
1443
1444 err_close_icosq:
1445         mlx5e_close_sq(&c->icosq);
1446
1447 err_disable_napi:
1448         napi_disable(&c->napi);
1449         mlx5e_close_cq(&c->rq.cq);
1450
1451 err_close_tx_cqs:
1452         mlx5e_close_tx_cqs(c);
1453
1454 err_close_icosq_cq:
1455         mlx5e_close_cq(&c->icosq.cq);
1456
1457 err_napi_del:
1458         netif_napi_del(&c->napi);
1459         napi_hash_del(&c->napi);
1460         kfree(c);
1461
1462         return err;
1463 }
1464
1465 static void mlx5e_close_channel(struct mlx5e_channel *c)
1466 {
1467         mlx5e_close_rq(&c->rq);
1468         mlx5e_close_sqs(c);
1469         mlx5e_close_sq(&c->icosq);
1470         napi_disable(&c->napi);
1471         mlx5e_close_cq(&c->rq.cq);
1472         mlx5e_close_tx_cqs(c);
1473         mlx5e_close_cq(&c->icosq.cq);
1474         netif_napi_del(&c->napi);
1475
1476         napi_hash_del(&c->napi);
1477         synchronize_rcu();
1478
1479         kfree(c);
1480 }
1481
1482 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1483                                  struct mlx5e_rq_param *param)
1484 {
1485         void *rqc = param->rqc;
1486         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1487
1488         switch (priv->params.rq_wq_type) {
1489         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1490                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1491                          priv->params.mpwqe_log_num_strides - 9);
1492                 MLX5_SET(wq, wq, log_wqe_stride_size,
1493                          priv->params.mpwqe_log_stride_sz - 6);
1494                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1495                 break;
1496         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1497                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1498         }
1499
1500         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1501         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1502         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1503         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1504         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1505
1506         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1507         param->wq.linear = 1;
1508
1509         param->am_enabled = priv->params.rx_am_enabled;
1510 }
1511
1512 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1513 {
1514         void *rqc = param->rqc;
1515         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1516
1517         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1518         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1519 }
1520
1521 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1522                                         struct mlx5e_sq_param *param)
1523 {
1524         void *sqc = param->sqc;
1525         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1526
1527         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1528         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1529
1530         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1531 }
1532
1533 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1534                                  struct mlx5e_sq_param *param)
1535 {
1536         void *sqc = param->sqc;
1537         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1538
1539         mlx5e_build_sq_param_common(priv, param);
1540         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1541
1542         param->max_inline = priv->params.tx_max_inline;
1543         param->min_inline_mode = priv->params.tx_min_inline_mode;
1544         param->type = MLX5E_SQ_TXQ;
1545 }
1546
1547 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1548                                         struct mlx5e_cq_param *param)
1549 {
1550         void *cqc = param->cqc;
1551
1552         MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
1553 }
1554
1555 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1556                                     struct mlx5e_cq_param *param)
1557 {
1558         void *cqc = param->cqc;
1559         u8 log_cq_size;
1560
1561         switch (priv->params.rq_wq_type) {
1562         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1563                 log_cq_size = priv->params.log_rq_size +
1564                         priv->params.mpwqe_log_num_strides;
1565                 break;
1566         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1567                 log_cq_size = priv->params.log_rq_size;
1568         }
1569
1570         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1571         if (priv->params.rx_cqe_compress) {
1572                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1573                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1574         }
1575
1576         mlx5e_build_common_cq_param(priv, param);
1577
1578         param->cq_period_mode = priv->params.rx_cq_period_mode;
1579 }
1580
1581 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1582                                     struct mlx5e_cq_param *param)
1583 {
1584         void *cqc = param->cqc;
1585
1586         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1587
1588         mlx5e_build_common_cq_param(priv, param);
1589
1590         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1591 }
1592
1593 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1594                                      struct mlx5e_cq_param *param,
1595                                      u8 log_wq_size)
1596 {
1597         void *cqc = param->cqc;
1598
1599         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1600
1601         mlx5e_build_common_cq_param(priv, param);
1602
1603         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1604 }
1605
1606 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1607                                     struct mlx5e_sq_param *param,
1608                                     u8 log_wq_size)
1609 {
1610         void *sqc = param->sqc;
1611         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1612
1613         mlx5e_build_sq_param_common(priv, param);
1614
1615         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1616         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1617
1618         param->type = MLX5E_SQ_ICO;
1619 }
1620
1621 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1622 {
1623         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1624
1625         mlx5e_build_rq_param(priv, &cparam->rq);
1626         mlx5e_build_sq_param(priv, &cparam->sq);
1627         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1628         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1629         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1630         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1631 }
1632
1633 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1634 {
1635         struct mlx5e_channel_param *cparam;
1636         int nch = priv->params.num_channels;
1637         int err = -ENOMEM;
1638         int i;
1639         int j;
1640
1641         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1642                                 GFP_KERNEL);
1643
1644         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1645                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1646
1647         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1648
1649         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1650                 goto err_free_txq_to_sq_map;
1651
1652         mlx5e_build_channel_param(priv, cparam);
1653
1654         for (i = 0; i < nch; i++) {
1655                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1656                 if (err)
1657                         goto err_close_channels;
1658         }
1659
1660         for (j = 0; j < nch; j++) {
1661                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1662                 if (err)
1663                         goto err_close_channels;
1664         }
1665
1666         /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1667          * polling for inactive tx queues.
1668          */
1669         netif_tx_start_all_queues(priv->netdev);
1670
1671         kfree(cparam);
1672         return 0;
1673
1674 err_close_channels:
1675         for (i--; i >= 0; i--)
1676                 mlx5e_close_channel(priv->channel[i]);
1677
1678 err_free_txq_to_sq_map:
1679         kfree(priv->txq_to_sq_map);
1680         kfree(priv->channel);
1681         kfree(cparam);
1682
1683         return err;
1684 }
1685
1686 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1687 {
1688         int i;
1689
1690         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1691          * polling for inactive tx queues.
1692          */
1693         netif_tx_stop_all_queues(priv->netdev);
1694         netif_tx_disable(priv->netdev);
1695
1696         for (i = 0; i < priv->params.num_channels; i++)
1697                 mlx5e_close_channel(priv->channel[i]);
1698
1699         kfree(priv->txq_to_sq_map);
1700         kfree(priv->channel);
1701 }
1702
1703 static int mlx5e_rx_hash_fn(int hfunc)
1704 {
1705         return (hfunc == ETH_RSS_HASH_TOP) ?
1706                MLX5_RX_HASH_FN_TOEPLITZ :
1707                MLX5_RX_HASH_FN_INVERTED_XOR8;
1708 }
1709
1710 static int mlx5e_bits_invert(unsigned long a, int size)
1711 {
1712         int inv = 0;
1713         int i;
1714
1715         for (i = 0; i < size; i++)
1716                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1717
1718         return inv;
1719 }
1720
1721 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1722 {
1723         int i;
1724
1725         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1726                 int ix = i;
1727                 u32 rqn;
1728
1729                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1730                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1731
1732                 ix = priv->params.indirection_rqt[ix];
1733                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1734                                 priv->channel[ix]->rq.rqn :
1735                                 priv->drop_rq.rqn;
1736                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1737         }
1738 }
1739
1740 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1741                                       int ix)
1742 {
1743         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1744                         priv->channel[ix]->rq.rqn :
1745                         priv->drop_rq.rqn;
1746
1747         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1748 }
1749
1750 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1751                             int ix, struct mlx5e_rqt *rqt)
1752 {
1753         struct mlx5_core_dev *mdev = priv->mdev;
1754         void *rqtc;
1755         int inlen;
1756         int err;
1757         u32 *in;
1758
1759         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1760         in = mlx5_vzalloc(inlen);
1761         if (!in)
1762                 return -ENOMEM;
1763
1764         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1765
1766         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1767         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1768
1769         if (sz > 1) /* RSS */
1770                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1771         else
1772                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1773
1774         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1775         if (!err)
1776                 rqt->enabled = true;
1777
1778         kvfree(in);
1779         return err;
1780 }
1781
1782 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1783 {
1784         rqt->enabled = false;
1785         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1786 }
1787
1788 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1789 {
1790         struct mlx5e_rqt *rqt = &priv->indir_rqt;
1791
1792         return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1793 }
1794
1795 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1796 {
1797         struct mlx5e_rqt *rqt;
1798         int err;
1799         int ix;
1800
1801         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1802                 rqt = &priv->direct_tir[ix].rqt;
1803                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1804                 if (err)
1805                         goto err_destroy_rqts;
1806         }
1807
1808         return 0;
1809
1810 err_destroy_rqts:
1811         for (ix--; ix >= 0; ix--)
1812                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1813
1814         return err;
1815 }
1816
1817 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1818 {
1819         struct mlx5_core_dev *mdev = priv->mdev;
1820         void *rqtc;
1821         int inlen;
1822         u32 *in;
1823         int err;
1824
1825         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1826         in = mlx5_vzalloc(inlen);
1827         if (!in)
1828                 return -ENOMEM;
1829
1830         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1831
1832         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1833         if (sz > 1) /* RSS */
1834                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1835         else
1836                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1837
1838         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1839
1840         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1841
1842         kvfree(in);
1843
1844         return err;
1845 }
1846
1847 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1848 {
1849         u32 rqtn;
1850         int ix;
1851
1852         if (priv->indir_rqt.enabled) {
1853                 rqtn = priv->indir_rqt.rqtn;
1854                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1855         }
1856
1857         for (ix = 0; ix < priv->params.num_channels; ix++) {
1858                 if (!priv->direct_tir[ix].rqt.enabled)
1859                         continue;
1860                 rqtn = priv->direct_tir[ix].rqt.rqtn;
1861                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1862         }
1863 }
1864
1865 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1866 {
1867         if (!priv->params.lro_en)
1868                 return;
1869
1870 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1871
1872         MLX5_SET(tirc, tirc, lro_enable_mask,
1873                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1874                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1875         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1876                  (priv->params.lro_wqe_sz -
1877                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1878         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1879                  MLX5_CAP_ETH(priv->mdev,
1880                               lro_timer_supported_periods[2]));
1881 }
1882
1883 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1884 {
1885         MLX5_SET(tirc, tirc, rx_hash_fn,
1886                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1887         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1888                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1889                                              rx_hash_toeplitz_key);
1890                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1891                                                rx_hash_toeplitz_key);
1892
1893                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1894                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1895         }
1896 }
1897
1898 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1899 {
1900         struct mlx5_core_dev *mdev = priv->mdev;
1901
1902         void *in;
1903         void *tirc;
1904         int inlen;
1905         int err;
1906         int tt;
1907         int ix;
1908
1909         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1910         in = mlx5_vzalloc(inlen);
1911         if (!in)
1912                 return -ENOMEM;
1913
1914         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1915         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1916
1917         mlx5e_build_tir_ctx_lro(tirc, priv);
1918
1919         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1920                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1921                                            inlen);
1922                 if (err)
1923                         goto free_in;
1924         }
1925
1926         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1927                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1928                                            in, inlen);
1929                 if (err)
1930                         goto free_in;
1931         }
1932
1933 free_in:
1934         kvfree(in);
1935
1936         return err;
1937 }
1938
1939 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1940 {
1941         struct mlx5_core_dev *mdev = priv->mdev;
1942         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1943         int err;
1944
1945         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1946         if (err)
1947                 return err;
1948
1949         /* Update vport context MTU */
1950         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1951         return 0;
1952 }
1953
1954 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1955 {
1956         struct mlx5_core_dev *mdev = priv->mdev;
1957         u16 hw_mtu = 0;
1958         int err;
1959
1960         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1961         if (err || !hw_mtu) /* fallback to port oper mtu */
1962                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1963
1964         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1965 }
1966
1967 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1968 {
1969         struct mlx5e_priv *priv = netdev_priv(netdev);
1970         u16 mtu;
1971         int err;
1972
1973         err = mlx5e_set_mtu(priv, netdev->mtu);
1974         if (err)
1975                 return err;
1976
1977         mlx5e_query_mtu(priv, &mtu);
1978         if (mtu != netdev->mtu)
1979                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1980                             __func__, mtu, netdev->mtu);
1981
1982         netdev->mtu = mtu;
1983         return 0;
1984 }
1985
1986 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1987 {
1988         struct mlx5e_priv *priv = netdev_priv(netdev);
1989         int nch = priv->params.num_channels;
1990         int ntc = priv->params.num_tc;
1991         int tc;
1992
1993         netdev_reset_tc(netdev);
1994
1995         if (ntc == 1)
1996                 return;
1997
1998         netdev_set_num_tc(netdev, ntc);
1999
2000         /* Map netdev TCs to offset 0
2001          * We have our own UP to TXQ mapping for QoS
2002          */
2003         for (tc = 0; tc < ntc; tc++)
2004                 netdev_set_tc_queue(netdev, tc, nch, 0);
2005 }
2006
2007 int mlx5e_open_locked(struct net_device *netdev)
2008 {
2009         struct mlx5e_priv *priv = netdev_priv(netdev);
2010         struct mlx5_core_dev *mdev = priv->mdev;
2011         int num_txqs;
2012         int err;
2013
2014         set_bit(MLX5E_STATE_OPENED, &priv->state);
2015
2016         mlx5e_netdev_set_tcs(netdev);
2017
2018         num_txqs = priv->params.num_channels * priv->params.num_tc;
2019         netif_set_real_num_tx_queues(netdev, num_txqs);
2020         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2021
2022         err = mlx5e_open_channels(priv);
2023         if (err) {
2024                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2025                            __func__, err);
2026                 goto err_clear_state_opened_flag;
2027         }
2028
2029         err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
2030         if (err) {
2031                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2032                            __func__, err);
2033                 goto err_close_channels;
2034         }
2035
2036         mlx5e_redirect_rqts(priv);
2037         mlx5e_update_carrier(priv);
2038         mlx5e_timestamp_init(priv);
2039 #ifdef CONFIG_RFS_ACCEL
2040         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2041 #endif
2042         if (priv->profile->update_stats)
2043                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2044
2045         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2046                 err = mlx5e_add_sqs_fwd_rules(priv);
2047                 if (err)
2048                         goto err_close_channels;
2049         }
2050         return 0;
2051
2052 err_close_channels:
2053         mlx5e_close_channels(priv);
2054 err_clear_state_opened_flag:
2055         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2056         return err;
2057 }
2058
2059 int mlx5e_open(struct net_device *netdev)
2060 {
2061         struct mlx5e_priv *priv = netdev_priv(netdev);
2062         int err;
2063
2064         mutex_lock(&priv->state_lock);
2065         err = mlx5e_open_locked(netdev);
2066         mutex_unlock(&priv->state_lock);
2067
2068         return err;
2069 }
2070
2071 int mlx5e_close_locked(struct net_device *netdev)
2072 {
2073         struct mlx5e_priv *priv = netdev_priv(netdev);
2074         struct mlx5_core_dev *mdev = priv->mdev;
2075
2076         /* May already be CLOSED in case a previous configuration operation
2077          * (e.g RX/TX queue size change) that involves close&open failed.
2078          */
2079         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2080                 return 0;
2081
2082         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2083
2084         if (MLX5_CAP_GEN(mdev, vport_group_manager))
2085                 mlx5e_remove_sqs_fwd_rules(priv);
2086
2087         mlx5e_timestamp_cleanup(priv);
2088         netif_carrier_off(priv->netdev);
2089         mlx5e_redirect_rqts(priv);
2090         mlx5e_close_channels(priv);
2091
2092         return 0;
2093 }
2094
2095 int mlx5e_close(struct net_device *netdev)
2096 {
2097         struct mlx5e_priv *priv = netdev_priv(netdev);
2098         int err;
2099
2100         if (!netif_device_present(netdev))
2101                 return -ENODEV;
2102
2103         mutex_lock(&priv->state_lock);
2104         err = mlx5e_close_locked(netdev);
2105         mutex_unlock(&priv->state_lock);
2106
2107         return err;
2108 }
2109
2110 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2111                                 struct mlx5e_rq *rq,
2112                                 struct mlx5e_rq_param *param)
2113 {
2114         struct mlx5_core_dev *mdev = priv->mdev;
2115         void *rqc = param->rqc;
2116         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2117         int err;
2118
2119         param->wq.db_numa_node = param->wq.buf_numa_node;
2120
2121         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2122                                 &rq->wq_ctrl);
2123         if (err)
2124                 return err;
2125
2126         rq->priv = priv;
2127
2128         return 0;
2129 }
2130
2131 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2132                                 struct mlx5e_cq *cq,
2133                                 struct mlx5e_cq_param *param)
2134 {
2135         struct mlx5_core_dev *mdev = priv->mdev;
2136         struct mlx5_core_cq *mcq = &cq->mcq;
2137         int eqn_not_used;
2138         unsigned int irqn;
2139         int err;
2140
2141         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2142                                &cq->wq_ctrl);
2143         if (err)
2144                 return err;
2145
2146         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2147
2148         mcq->cqe_sz     = 64;
2149         mcq->set_ci_db  = cq->wq_ctrl.db.db;
2150         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
2151         *mcq->set_ci_db = 0;
2152         *mcq->arm_db    = 0;
2153         mcq->vector     = param->eq_ix;
2154         mcq->comp       = mlx5e_completion_event;
2155         mcq->event      = mlx5e_cq_error_event;
2156         mcq->irqn       = irqn;
2157         mcq->uar        = &mdev->mlx5e_res.cq_uar;
2158
2159         cq->priv = priv;
2160
2161         return 0;
2162 }
2163
2164 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2165 {
2166         struct mlx5e_cq_param cq_param;
2167         struct mlx5e_rq_param rq_param;
2168         struct mlx5e_rq *rq = &priv->drop_rq;
2169         struct mlx5e_cq *cq = &priv->drop_rq.cq;
2170         int err;
2171
2172         memset(&cq_param, 0, sizeof(cq_param));
2173         memset(&rq_param, 0, sizeof(rq_param));
2174         mlx5e_build_drop_rq_param(&rq_param);
2175
2176         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2177         if (err)
2178                 return err;
2179
2180         err = mlx5e_enable_cq(cq, &cq_param);
2181         if (err)
2182                 goto err_destroy_cq;
2183
2184         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2185         if (err)
2186                 goto err_disable_cq;
2187
2188         err = mlx5e_enable_rq(rq, &rq_param);
2189         if (err)
2190                 goto err_destroy_rq;
2191
2192         return 0;
2193
2194 err_destroy_rq:
2195         mlx5e_destroy_rq(&priv->drop_rq);
2196
2197 err_disable_cq:
2198         mlx5e_disable_cq(&priv->drop_rq.cq);
2199
2200 err_destroy_cq:
2201         mlx5e_destroy_cq(&priv->drop_rq.cq);
2202
2203         return err;
2204 }
2205
2206 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2207 {
2208         mlx5e_disable_rq(&priv->drop_rq);
2209         mlx5e_destroy_rq(&priv->drop_rq);
2210         mlx5e_disable_cq(&priv->drop_rq.cq);
2211         mlx5e_destroy_cq(&priv->drop_rq.cq);
2212 }
2213
2214 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2215 {
2216         struct mlx5_core_dev *mdev = priv->mdev;
2217         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2218         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2219
2220         MLX5_SET(tisc, tisc, prio, tc << 1);
2221         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2222
2223         if (mlx5_lag_is_lacp_owner(mdev))
2224                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2225
2226         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2227 }
2228
2229 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2230 {
2231         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2232 }
2233
2234 int mlx5e_create_tises(struct mlx5e_priv *priv)
2235 {
2236         int err;
2237         int tc;
2238
2239         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2240                 err = mlx5e_create_tis(priv, tc);
2241                 if (err)
2242                         goto err_close_tises;
2243         }
2244
2245         return 0;
2246
2247 err_close_tises:
2248         for (tc--; tc >= 0; tc--)
2249                 mlx5e_destroy_tis(priv, tc);
2250
2251         return err;
2252 }
2253
2254 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2255 {
2256         int tc;
2257
2258         for (tc = 0; tc < priv->profile->max_tc; tc++)
2259                 mlx5e_destroy_tis(priv, tc);
2260 }
2261
2262 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2263                                       enum mlx5e_traffic_types tt)
2264 {
2265         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2266
2267         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2268
2269 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2270                                  MLX5_HASH_FIELD_SEL_DST_IP)
2271
2272 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2273                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2274                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2275                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2276
2277 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2278                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2279                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2280
2281         mlx5e_build_tir_ctx_lro(tirc, priv);
2282
2283         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2284         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2285         mlx5e_build_tir_ctx_hash(tirc, priv);
2286
2287         switch (tt) {
2288         case MLX5E_TT_IPV4_TCP:
2289                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2290                          MLX5_L3_PROT_TYPE_IPV4);
2291                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2292                          MLX5_L4_PROT_TYPE_TCP);
2293                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2294                          MLX5_HASH_IP_L4PORTS);
2295                 break;
2296
2297         case MLX5E_TT_IPV6_TCP:
2298                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2299                          MLX5_L3_PROT_TYPE_IPV6);
2300                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2301                          MLX5_L4_PROT_TYPE_TCP);
2302                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2303                          MLX5_HASH_IP_L4PORTS);
2304                 break;
2305
2306         case MLX5E_TT_IPV4_UDP:
2307                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2308                          MLX5_L3_PROT_TYPE_IPV4);
2309                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2310                          MLX5_L4_PROT_TYPE_UDP);
2311                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2312                          MLX5_HASH_IP_L4PORTS);
2313                 break;
2314
2315         case MLX5E_TT_IPV6_UDP:
2316                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2317                          MLX5_L3_PROT_TYPE_IPV6);
2318                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2319                          MLX5_L4_PROT_TYPE_UDP);
2320                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2321                          MLX5_HASH_IP_L4PORTS);
2322                 break;
2323
2324         case MLX5E_TT_IPV4_IPSEC_AH:
2325                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2326                          MLX5_L3_PROT_TYPE_IPV4);
2327                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2328                          MLX5_HASH_IP_IPSEC_SPI);
2329                 break;
2330
2331         case MLX5E_TT_IPV6_IPSEC_AH:
2332                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2333                          MLX5_L3_PROT_TYPE_IPV6);
2334                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2335                          MLX5_HASH_IP_IPSEC_SPI);
2336                 break;
2337
2338         case MLX5E_TT_IPV4_IPSEC_ESP:
2339                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2340                          MLX5_L3_PROT_TYPE_IPV4);
2341                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2342                          MLX5_HASH_IP_IPSEC_SPI);
2343                 break;
2344
2345         case MLX5E_TT_IPV6_IPSEC_ESP:
2346                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2347                          MLX5_L3_PROT_TYPE_IPV6);
2348                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2349                          MLX5_HASH_IP_IPSEC_SPI);
2350                 break;
2351
2352         case MLX5E_TT_IPV4:
2353                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2354                          MLX5_L3_PROT_TYPE_IPV4);
2355                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2356                          MLX5_HASH_IP);
2357                 break;
2358
2359         case MLX5E_TT_IPV6:
2360                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2361                          MLX5_L3_PROT_TYPE_IPV6);
2362                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2363                          MLX5_HASH_IP);
2364                 break;
2365         default:
2366                 WARN_ONCE(true,
2367                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2368         }
2369 }
2370
2371 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2372                                        u32 rqtn)
2373 {
2374         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2375
2376         mlx5e_build_tir_ctx_lro(tirc, priv);
2377
2378         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2379         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2380         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2381 }
2382
2383 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2384 {
2385         struct mlx5e_tir *tir;
2386         void *tirc;
2387         int inlen;
2388         int err;
2389         u32 *in;
2390         int tt;
2391
2392         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2393         in = mlx5_vzalloc(inlen);
2394         if (!in)
2395                 return -ENOMEM;
2396
2397         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2398                 memset(in, 0, inlen);
2399                 tir = &priv->indir_tir[tt];
2400                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2401                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2402                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2403                 if (err)
2404                         goto err_destroy_tirs;
2405         }
2406
2407         kvfree(in);
2408
2409         return 0;
2410
2411 err_destroy_tirs:
2412         for (tt--; tt >= 0; tt--)
2413                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2414
2415         kvfree(in);
2416
2417         return err;
2418 }
2419
2420 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2421 {
2422         int nch = priv->profile->max_nch(priv->mdev);
2423         struct mlx5e_tir *tir;
2424         void *tirc;
2425         int inlen;
2426         int err;
2427         u32 *in;
2428         int ix;
2429
2430         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2431         in = mlx5_vzalloc(inlen);
2432         if (!in)
2433                 return -ENOMEM;
2434
2435         for (ix = 0; ix < nch; ix++) {
2436                 memset(in, 0, inlen);
2437                 tir = &priv->direct_tir[ix];
2438                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2439                 mlx5e_build_direct_tir_ctx(priv, tirc,
2440                                            priv->direct_tir[ix].rqt.rqtn);
2441                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2442                 if (err)
2443                         goto err_destroy_ch_tirs;
2444         }
2445
2446         kvfree(in);
2447
2448         return 0;
2449
2450 err_destroy_ch_tirs:
2451         for (ix--; ix >= 0; ix--)
2452                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2453
2454         kvfree(in);
2455
2456         return err;
2457 }
2458
2459 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2460 {
2461         int i;
2462
2463         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2464                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2465 }
2466
2467 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2468 {
2469         int nch = priv->profile->max_nch(priv->mdev);
2470         int i;
2471
2472         for (i = 0; i < nch; i++)
2473                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2474 }
2475
2476 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2477 {
2478         int err = 0;
2479         int i;
2480
2481         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2482                 return 0;
2483
2484         for (i = 0; i < priv->params.num_channels; i++) {
2485                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2486                 if (err)
2487                         return err;
2488         }
2489
2490         return 0;
2491 }
2492
2493 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2494 {
2495         struct mlx5e_priv *priv = netdev_priv(netdev);
2496         bool was_opened;
2497         int err = 0;
2498
2499         if (tc && tc != MLX5E_MAX_NUM_TC)
2500                 return -EINVAL;
2501
2502         mutex_lock(&priv->state_lock);
2503
2504         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2505         if (was_opened)
2506                 mlx5e_close_locked(priv->netdev);
2507
2508         priv->params.num_tc = tc ? tc : 1;
2509
2510         if (was_opened)
2511                 err = mlx5e_open_locked(priv->netdev);
2512
2513         mutex_unlock(&priv->state_lock);
2514
2515         return err;
2516 }
2517
2518 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2519                               __be16 proto, struct tc_to_netdev *tc)
2520 {
2521         struct mlx5e_priv *priv = netdev_priv(dev);
2522
2523         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2524                 goto mqprio;
2525
2526         switch (tc->type) {
2527         case TC_SETUP_CLSFLOWER:
2528                 switch (tc->cls_flower->command) {
2529                 case TC_CLSFLOWER_REPLACE:
2530                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2531                 case TC_CLSFLOWER_DESTROY:
2532                         return mlx5e_delete_flower(priv, tc->cls_flower);
2533                 case TC_CLSFLOWER_STATS:
2534                         return mlx5e_stats_flower(priv, tc->cls_flower);
2535                 }
2536         default:
2537                 return -EOPNOTSUPP;
2538         }
2539
2540 mqprio:
2541         if (tc->type != TC_SETUP_MQPRIO)
2542                 return -EINVAL;
2543
2544         return mlx5e_setup_tc(dev, tc->tc);
2545 }
2546
2547 struct rtnl_link_stats64 *
2548 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2549 {
2550         struct mlx5e_priv *priv = netdev_priv(dev);
2551         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2552         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2553         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2554
2555         stats->rx_packets = sstats->rx_packets;
2556         stats->rx_bytes   = sstats->rx_bytes;
2557         stats->tx_packets = sstats->tx_packets;
2558         stats->tx_bytes   = sstats->tx_bytes;
2559
2560         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2561         stats->tx_dropped = sstats->tx_queue_dropped;
2562
2563         stats->rx_length_errors =
2564                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2565                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2566                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2567         stats->rx_crc_errors =
2568                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2569         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2570         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2571         stats->tx_carrier_errors =
2572                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2573         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2574                            stats->rx_frame_errors;
2575         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2576
2577         /* vport multicast also counts packets that are dropped due to steering
2578          * or rx out of buffer
2579          */
2580         stats->multicast =
2581                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2582
2583         return stats;
2584 }
2585
2586 static void mlx5e_set_rx_mode(struct net_device *dev)
2587 {
2588         struct mlx5e_priv *priv = netdev_priv(dev);
2589
2590         queue_work(priv->wq, &priv->set_rx_mode_work);
2591 }
2592
2593 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2594 {
2595         struct mlx5e_priv *priv = netdev_priv(netdev);
2596         struct sockaddr *saddr = addr;
2597
2598         if (!is_valid_ether_addr(saddr->sa_data))
2599                 return -EADDRNOTAVAIL;
2600
2601         netif_addr_lock_bh(netdev);
2602         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2603         netif_addr_unlock_bh(netdev);
2604
2605         queue_work(priv->wq, &priv->set_rx_mode_work);
2606
2607         return 0;
2608 }
2609
2610 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2611         do {                                            \
2612                 if (enable)                             \
2613                         netdev->features |= feature;    \
2614                 else                                    \
2615                         netdev->features &= ~feature;   \
2616         } while (0)
2617
2618 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2619
2620 static int set_feature_lro(struct net_device *netdev, bool enable)
2621 {
2622         struct mlx5e_priv *priv = netdev_priv(netdev);
2623         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2624         int err;
2625
2626         mutex_lock(&priv->state_lock);
2627
2628         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2629                 mlx5e_close_locked(priv->netdev);
2630
2631         priv->params.lro_en = enable;
2632         err = mlx5e_modify_tirs_lro(priv);
2633         if (err) {
2634                 netdev_err(netdev, "lro modify failed, %d\n", err);
2635                 priv->params.lro_en = !enable;
2636         }
2637
2638         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2639                 mlx5e_open_locked(priv->netdev);
2640
2641         mutex_unlock(&priv->state_lock);
2642
2643         return err;
2644 }
2645
2646 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2647 {
2648         struct mlx5e_priv *priv = netdev_priv(netdev);
2649
2650         if (enable)
2651                 mlx5e_enable_vlan_filter(priv);
2652         else
2653                 mlx5e_disable_vlan_filter(priv);
2654
2655         return 0;
2656 }
2657
2658 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2659 {
2660         struct mlx5e_priv *priv = netdev_priv(netdev);
2661
2662         if (!enable && mlx5e_tc_num_filters(priv)) {
2663                 netdev_err(netdev,
2664                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2665                 return -EINVAL;
2666         }
2667
2668         return 0;
2669 }
2670
2671 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2672 {
2673         struct mlx5e_priv *priv = netdev_priv(netdev);
2674         struct mlx5_core_dev *mdev = priv->mdev;
2675
2676         return mlx5_set_port_fcs(mdev, !enable);
2677 }
2678
2679 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2680 {
2681         struct mlx5e_priv *priv = netdev_priv(netdev);
2682         int err;
2683
2684         mutex_lock(&priv->state_lock);
2685
2686         priv->params.vlan_strip_disable = !enable;
2687         err = mlx5e_modify_rqs_vsd(priv, !enable);
2688         if (err)
2689                 priv->params.vlan_strip_disable = enable;
2690
2691         mutex_unlock(&priv->state_lock);
2692
2693         return err;
2694 }
2695
2696 #ifdef CONFIG_RFS_ACCEL
2697 static int set_feature_arfs(struct net_device *netdev, bool enable)
2698 {
2699         struct mlx5e_priv *priv = netdev_priv(netdev);
2700         int err;
2701
2702         if (enable)
2703                 err = mlx5e_arfs_enable(priv);
2704         else
2705                 err = mlx5e_arfs_disable(priv);
2706
2707         return err;
2708 }
2709 #endif
2710
2711 static int mlx5e_handle_feature(struct net_device *netdev,
2712                                 netdev_features_t wanted_features,
2713                                 netdev_features_t feature,
2714                                 mlx5e_feature_handler feature_handler)
2715 {
2716         netdev_features_t changes = wanted_features ^ netdev->features;
2717         bool enable = !!(wanted_features & feature);
2718         int err;
2719
2720         if (!(changes & feature))
2721                 return 0;
2722
2723         err = feature_handler(netdev, enable);
2724         if (err) {
2725                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2726                            enable ? "Enable" : "Disable", feature, err);
2727                 return err;
2728         }
2729
2730         MLX5E_SET_FEATURE(netdev, feature, enable);
2731         return 0;
2732 }
2733
2734 static int mlx5e_set_features(struct net_device *netdev,
2735                               netdev_features_t features)
2736 {
2737         int err;
2738
2739         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2740                                     set_feature_lro);
2741         err |= mlx5e_handle_feature(netdev, features,
2742                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2743                                     set_feature_vlan_filter);
2744         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2745                                     set_feature_tc_num_filters);
2746         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2747                                     set_feature_rx_all);
2748         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2749                                     set_feature_rx_vlan);
2750 #ifdef CONFIG_RFS_ACCEL
2751         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2752                                     set_feature_arfs);
2753 #endif
2754
2755         return err ? -EINVAL : 0;
2756 }
2757
2758 #define MXL5_HW_MIN_MTU 64
2759 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2760
2761 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2762 {
2763         struct mlx5e_priv *priv = netdev_priv(netdev);
2764         struct mlx5_core_dev *mdev = priv->mdev;
2765         bool was_opened;
2766         u16 max_mtu;
2767         u16 min_mtu;
2768         int err = 0;
2769         bool reset;
2770
2771         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2772
2773         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2774         min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2775
2776         if (new_mtu > max_mtu || new_mtu < min_mtu) {
2777                 netdev_err(netdev,
2778                            "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2779                            __func__, new_mtu, min_mtu, max_mtu);
2780                 return -EINVAL;
2781         }
2782
2783         mutex_lock(&priv->state_lock);
2784
2785         reset = !priv->params.lro_en &&
2786                 (priv->params.rq_wq_type !=
2787                  MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2788
2789         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2790         if (was_opened && reset)
2791                 mlx5e_close_locked(netdev);
2792
2793         netdev->mtu = new_mtu;
2794         mlx5e_set_dev_port_mtu(netdev);
2795
2796         if (was_opened && reset)
2797                 err = mlx5e_open_locked(netdev);
2798
2799         mutex_unlock(&priv->state_lock);
2800
2801         return err;
2802 }
2803
2804 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2805 {
2806         switch (cmd) {
2807         case SIOCSHWTSTAMP:
2808                 return mlx5e_hwstamp_set(dev, ifr);
2809         case SIOCGHWTSTAMP:
2810                 return mlx5e_hwstamp_get(dev, ifr);
2811         default:
2812                 return -EOPNOTSUPP;
2813         }
2814 }
2815
2816 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2817 {
2818         struct mlx5e_priv *priv = netdev_priv(dev);
2819         struct mlx5_core_dev *mdev = priv->mdev;
2820
2821         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2822 }
2823
2824 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2825 {
2826         struct mlx5e_priv *priv = netdev_priv(dev);
2827         struct mlx5_core_dev *mdev = priv->mdev;
2828
2829         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2830                                            vlan, qos);
2831 }
2832
2833 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2834 {
2835         struct mlx5e_priv *priv = netdev_priv(dev);
2836         struct mlx5_core_dev *mdev = priv->mdev;
2837
2838         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2839 }
2840
2841 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2842 {
2843         struct mlx5e_priv *priv = netdev_priv(dev);
2844         struct mlx5_core_dev *mdev = priv->mdev;
2845
2846         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2847 }
2848 static int mlx5_vport_link2ifla(u8 esw_link)
2849 {
2850         switch (esw_link) {
2851         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2852                 return IFLA_VF_LINK_STATE_DISABLE;
2853         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2854                 return IFLA_VF_LINK_STATE_ENABLE;
2855         }
2856         return IFLA_VF_LINK_STATE_AUTO;
2857 }
2858
2859 static int mlx5_ifla_link2vport(u8 ifla_link)
2860 {
2861         switch (ifla_link) {
2862         case IFLA_VF_LINK_STATE_DISABLE:
2863                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2864         case IFLA_VF_LINK_STATE_ENABLE:
2865                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2866         }
2867         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2868 }
2869
2870 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2871                                    int link_state)
2872 {
2873         struct mlx5e_priv *priv = netdev_priv(dev);
2874         struct mlx5_core_dev *mdev = priv->mdev;
2875
2876         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2877                                             mlx5_ifla_link2vport(link_state));
2878 }
2879
2880 static int mlx5e_get_vf_config(struct net_device *dev,
2881                                int vf, struct ifla_vf_info *ivi)
2882 {
2883         struct mlx5e_priv *priv = netdev_priv(dev);
2884         struct mlx5_core_dev *mdev = priv->mdev;
2885         int err;
2886
2887         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2888         if (err)
2889                 return err;
2890         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2891         return 0;
2892 }
2893
2894 static int mlx5e_get_vf_stats(struct net_device *dev,
2895                               int vf, struct ifla_vf_stats *vf_stats)
2896 {
2897         struct mlx5e_priv *priv = netdev_priv(dev);
2898         struct mlx5_core_dev *mdev = priv->mdev;
2899
2900         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2901                                             vf_stats);
2902 }
2903
2904 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2905                                  struct udp_tunnel_info *ti)
2906 {
2907         struct mlx5e_priv *priv = netdev_priv(netdev);
2908
2909         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2910                 return;
2911
2912         if (!mlx5e_vxlan_allowed(priv->mdev))
2913                 return;
2914
2915         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
2916 }
2917
2918 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2919                                  struct udp_tunnel_info *ti)
2920 {
2921         struct mlx5e_priv *priv = netdev_priv(netdev);
2922
2923         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2924                 return;
2925
2926         if (!mlx5e_vxlan_allowed(priv->mdev))
2927                 return;
2928
2929         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
2930 }
2931
2932 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2933                                                     struct sk_buff *skb,
2934                                                     netdev_features_t features)
2935 {
2936         struct udphdr *udph;
2937         u16 proto;
2938         u16 port = 0;
2939
2940         switch (vlan_get_protocol(skb)) {
2941         case htons(ETH_P_IP):
2942                 proto = ip_hdr(skb)->protocol;
2943                 break;
2944         case htons(ETH_P_IPV6):
2945                 proto = ipv6_hdr(skb)->nexthdr;
2946                 break;
2947         default:
2948                 goto out;
2949         }
2950
2951         if (proto == IPPROTO_UDP) {
2952                 udph = udp_hdr(skb);
2953                 port = be16_to_cpu(udph->dest);
2954         }
2955
2956         /* Verify if UDP port is being offloaded by HW */
2957         if (port && mlx5e_vxlan_lookup_port(priv, port))
2958                 return features;
2959
2960 out:
2961         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2962         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2963 }
2964
2965 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2966                                               struct net_device *netdev,
2967                                               netdev_features_t features)
2968 {
2969         struct mlx5e_priv *priv = netdev_priv(netdev);
2970
2971         features = vlan_features_check(skb, features);
2972         features = vxlan_features_check(skb, features);
2973
2974         /* Validate if the tunneled packet is being offloaded by HW */
2975         if (skb->encapsulation &&
2976             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2977                 return mlx5e_vxlan_features_check(priv, skb, features);
2978
2979         return features;
2980 }
2981
2982 static void mlx5e_tx_timeout(struct net_device *dev)
2983 {
2984         struct mlx5e_priv *priv = netdev_priv(dev);
2985         bool sched_work = false;
2986         int i;
2987
2988         netdev_err(dev, "TX timeout detected\n");
2989
2990         for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
2991                 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
2992
2993                 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
2994                         continue;
2995                 sched_work = true;
2996                 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
2997                 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
2998                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
2999         }
3000
3001         if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3002                 schedule_work(&priv->tx_timeout_work);
3003 }
3004
3005 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3006 {
3007         struct mlx5e_priv *priv = netdev_priv(netdev);
3008         struct bpf_prog *old_prog;
3009         int err = 0;
3010         bool reset, was_opened;
3011         int i;
3012
3013         mutex_lock(&priv->state_lock);
3014
3015         if ((netdev->features & NETIF_F_LRO) && prog) {
3016                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3017                 err = -EINVAL;
3018                 goto unlock;
3019         }
3020
3021         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3022         /* no need for full reset when exchanging programs */
3023         reset = (!priv->xdp_prog || !prog);
3024
3025         if (was_opened && reset)
3026                 mlx5e_close_locked(netdev);
3027
3028         /* exchange programs */
3029         old_prog = xchg(&priv->xdp_prog, prog);
3030         if (prog)
3031                 bpf_prog_add(prog, 1);
3032         if (old_prog)
3033                 bpf_prog_put(old_prog);
3034
3035         if (reset) /* change RQ type according to priv->xdp_prog */
3036                 mlx5e_set_rq_priv_params(priv);
3037
3038         if (was_opened && reset)
3039                 mlx5e_open_locked(netdev);
3040
3041         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3042                 goto unlock;
3043
3044         /* exchanging programs w/o reset, we update ref counts on behalf
3045          * of the channels RQs here.
3046          */
3047         bpf_prog_add(prog, priv->params.num_channels);
3048         for (i = 0; i < priv->params.num_channels; i++) {
3049                 struct mlx5e_channel *c = priv->channel[i];
3050
3051                 set_bit(MLX5E_RQ_STATE_FLUSH, &c->rq.state);
3052                 napi_synchronize(&c->napi);
3053                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3054
3055                 old_prog = xchg(&c->rq.xdp_prog, prog);
3056
3057                 clear_bit(MLX5E_RQ_STATE_FLUSH, &c->rq.state);
3058                 /* napi_schedule in case we have missed anything */
3059                 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3060                 napi_schedule(&c->napi);
3061
3062                 if (old_prog)
3063                         bpf_prog_put(old_prog);
3064         }
3065
3066 unlock:
3067         mutex_unlock(&priv->state_lock);
3068         return err;
3069 }
3070
3071 static bool mlx5e_xdp_attached(struct net_device *dev)
3072 {
3073         struct mlx5e_priv *priv = netdev_priv(dev);
3074
3075         return !!priv->xdp_prog;
3076 }
3077
3078 static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3079 {
3080         switch (xdp->command) {
3081         case XDP_SETUP_PROG:
3082                 return mlx5e_xdp_set(dev, xdp->prog);
3083         case XDP_QUERY_PROG:
3084                 xdp->prog_attached = mlx5e_xdp_attached(dev);
3085                 return 0;
3086         default:
3087                 return -EINVAL;
3088         }
3089 }
3090
3091 static const struct net_device_ops mlx5e_netdev_ops_basic = {
3092         .ndo_open                = mlx5e_open,
3093         .ndo_stop                = mlx5e_close,
3094         .ndo_start_xmit          = mlx5e_xmit,
3095         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
3096         .ndo_select_queue        = mlx5e_select_queue,
3097         .ndo_get_stats64         = mlx5e_get_stats,
3098         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
3099         .ndo_set_mac_address     = mlx5e_set_mac,
3100         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
3101         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
3102         .ndo_set_features        = mlx5e_set_features,
3103         .ndo_change_mtu          = mlx5e_change_mtu,
3104         .ndo_do_ioctl            = mlx5e_ioctl,
3105         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
3106 #ifdef CONFIG_RFS_ACCEL
3107         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
3108 #endif
3109         .ndo_tx_timeout          = mlx5e_tx_timeout,
3110         .ndo_xdp                 = mlx5e_xdp,
3111 };
3112
3113 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3114         .ndo_open                = mlx5e_open,
3115         .ndo_stop                = mlx5e_close,
3116         .ndo_start_xmit          = mlx5e_xmit,
3117         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
3118         .ndo_select_queue        = mlx5e_select_queue,
3119         .ndo_get_stats64         = mlx5e_get_stats,
3120         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
3121         .ndo_set_mac_address     = mlx5e_set_mac,
3122         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
3123         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
3124         .ndo_set_features        = mlx5e_set_features,
3125         .ndo_change_mtu          = mlx5e_change_mtu,
3126         .ndo_do_ioctl            = mlx5e_ioctl,
3127         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
3128         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
3129         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
3130         .ndo_features_check      = mlx5e_features_check,
3131 #ifdef CONFIG_RFS_ACCEL
3132         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
3133 #endif
3134         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
3135         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
3136         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
3137         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
3138         .ndo_get_vf_config       = mlx5e_get_vf_config,
3139         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
3140         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
3141         .ndo_tx_timeout          = mlx5e_tx_timeout,
3142         .ndo_xdp                 = mlx5e_xdp,
3143 };
3144
3145 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3146 {
3147         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3148                 return -ENOTSUPP;
3149         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3150             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3151             !MLX5_CAP_ETH(mdev, csum_cap) ||
3152             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3153             !MLX5_CAP_ETH(mdev, vlan_cap) ||
3154             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3155             MLX5_CAP_FLOWTABLE(mdev,
3156                                flow_table_properties_nic_receive.max_ft_level)
3157                                < 3) {
3158                 mlx5_core_warn(mdev,
3159                                "Not creating net device, some required device capabilities are missing\n");
3160                 return -ENOTSUPP;
3161         }
3162         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3163                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3164         if (!MLX5_CAP_GEN(mdev, cq_moderation))
3165                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
3166
3167         return 0;
3168 }
3169
3170 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3171 {
3172         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3173
3174         return bf_buf_size -
3175                sizeof(struct mlx5e_tx_wqe) +
3176                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3177 }
3178
3179 #ifdef CONFIG_MLX5_CORE_EN_DCB
3180 static void mlx5e_ets_init(struct mlx5e_priv *priv)
3181 {
3182         int i;
3183
3184         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
3185         for (i = 0; i < priv->params.ets.ets_cap; i++) {
3186                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
3187                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
3188                 priv->params.ets.prio_tc[i] = i;
3189         }
3190
3191         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
3192         priv->params.ets.prio_tc[0] = 1;
3193         priv->params.ets.prio_tc[1] = 0;
3194 }
3195 #endif
3196
3197 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3198                                    u32 *indirection_rqt, int len,
3199                                    int num_channels)
3200 {
3201         int node = mdev->priv.numa_node;
3202         int node_num_of_cores;
3203         int i;
3204
3205         if (node == -1)
3206                 node = first_online_node;
3207
3208         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3209
3210         if (node_num_of_cores)
3211                 num_channels = min_t(int, num_channels, node_num_of_cores);
3212
3213         for (i = 0; i < len; i++)
3214                 indirection_rqt[i] = i % num_channels;
3215 }
3216
3217 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3218 {
3219         enum pcie_link_width width;
3220         enum pci_bus_speed speed;
3221         int err = 0;
3222
3223         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3224         if (err)
3225                 return err;
3226
3227         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3228                 return -EINVAL;
3229
3230         switch (speed) {
3231         case PCIE_SPEED_2_5GT:
3232                 *pci_bw = 2500 * width;
3233                 break;
3234         case PCIE_SPEED_5_0GT:
3235                 *pci_bw = 5000 * width;
3236                 break;
3237         case PCIE_SPEED_8_0GT:
3238                 *pci_bw = 8000 * width;
3239                 break;
3240         default:
3241                 return -EINVAL;
3242         }
3243
3244         return 0;
3245 }
3246
3247 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3248 {
3249         return (link_speed && pci_bw &&
3250                 (pci_bw < 40000) && (pci_bw < link_speed));
3251 }
3252
3253 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3254 {
3255         params->rx_cq_period_mode = cq_period_mode;
3256
3257         params->rx_cq_moderation.pkts =
3258                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3259         params->rx_cq_moderation.usec =
3260                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3261
3262         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3263                 params->rx_cq_moderation.usec =
3264                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3265 }
3266
3267 static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
3268                                    u8 *min_inline_mode)
3269 {
3270         switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
3271         case MLX5E_INLINE_MODE_L2:
3272                 *min_inline_mode = MLX5_INLINE_MODE_L2;
3273                 break;
3274         case MLX5E_INLINE_MODE_VPORT_CONTEXT:
3275                 mlx5_query_nic_vport_min_inline(mdev,
3276                                                 min_inline_mode);
3277                 break;
3278         case MLX5_INLINE_MODE_NOT_REQUIRED:
3279                 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3280                 break;
3281         }
3282 }
3283
3284 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3285                                         struct net_device *netdev,
3286                                         const struct mlx5e_profile *profile,
3287                                         void *ppriv)
3288 {
3289         struct mlx5e_priv *priv = netdev_priv(netdev);
3290         u32 link_speed = 0;
3291         u32 pci_bw = 0;
3292         u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3293                                          MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3294                                          MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3295
3296         priv->mdev                         = mdev;
3297         priv->netdev                       = netdev;
3298         priv->params.num_channels          = profile->max_nch(mdev);
3299         priv->profile                      = profile;
3300         priv->ppriv                        = ppriv;
3301
3302         priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3303
3304         /* set CQE compression */
3305         priv->params.rx_cqe_compress_admin = false;
3306         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3307             MLX5_CAP_GEN(mdev, vport_group_manager)) {
3308                 mlx5e_get_max_linkspeed(mdev, &link_speed);
3309                 mlx5e_get_pci_bw(mdev, &pci_bw);
3310                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3311                               link_speed, pci_bw);
3312                 priv->params.rx_cqe_compress_admin =
3313                         cqe_compress_heuristic(link_speed, pci_bw);
3314         }
3315         priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3316
3317         mlx5e_set_rq_priv_params(priv);
3318         if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3319                 priv->params.lro_en = true;
3320
3321         priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3322         mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3323
3324         priv->params.tx_cq_moderation.usec =
3325                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3326         priv->params.tx_cq_moderation.pkts =
3327                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3328         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
3329         mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3330         priv->params.num_tc                = 1;
3331         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
3332
3333         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3334                             sizeof(priv->params.toeplitz_hash_key));
3335
3336         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3337                                       MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3338
3339         priv->params.lro_wqe_sz =
3340                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ -
3341                 /* Extra room needed for build_skb */
3342                 MLX5_RX_HEADROOM -
3343                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3344
3345         /* Initialize pflags */
3346         MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3347                             priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3348
3349 #ifdef CONFIG_MLX5_CORE_EN_DCB
3350         mlx5e_ets_init(priv);
3351 #endif
3352
3353         mutex_init(&priv->state_lock);
3354
3355         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3356         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3357         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3358         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3359 }
3360
3361 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3362 {
3363         struct mlx5e_priv *priv = netdev_priv(netdev);
3364
3365         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3366         if (is_zero_ether_addr(netdev->dev_addr) &&
3367             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3368                 eth_hw_addr_random(netdev);
3369                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3370         }
3371 }
3372
3373 static const struct switchdev_ops mlx5e_switchdev_ops = {
3374         .switchdev_port_attr_get        = mlx5e_attr_get,
3375 };
3376
3377 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3378 {
3379         struct mlx5e_priv *priv = netdev_priv(netdev);
3380         struct mlx5_core_dev *mdev = priv->mdev;
3381         bool fcs_supported;
3382         bool fcs_enabled;
3383
3384         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3385
3386         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3387                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3388 #ifdef CONFIG_MLX5_CORE_EN_DCB
3389                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3390 #endif
3391         } else {
3392                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3393         }
3394
3395         netdev->watchdog_timeo    = 15 * HZ;
3396
3397         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
3398
3399         netdev->vlan_features    |= NETIF_F_SG;
3400         netdev->vlan_features    |= NETIF_F_IP_CSUM;
3401         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
3402         netdev->vlan_features    |= NETIF_F_GRO;
3403         netdev->vlan_features    |= NETIF_F_TSO;
3404         netdev->vlan_features    |= NETIF_F_TSO6;
3405         netdev->vlan_features    |= NETIF_F_RXCSUM;
3406         netdev->vlan_features    |= NETIF_F_RXHASH;
3407
3408         if (!!MLX5_CAP_ETH(mdev, lro_cap))
3409                 netdev->vlan_features    |= NETIF_F_LRO;
3410
3411         netdev->hw_features       = netdev->vlan_features;
3412         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
3413         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
3414         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
3415
3416         if (mlx5e_vxlan_allowed(mdev)) {
3417                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
3418                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
3419                                            NETIF_F_GSO_PARTIAL;
3420                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3421                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3422                 netdev->hw_enc_features |= NETIF_F_TSO;
3423                 netdev->hw_enc_features |= NETIF_F_TSO6;
3424                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3425                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3426                                            NETIF_F_GSO_PARTIAL;
3427                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3428         }
3429
3430         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3431
3432         if (fcs_supported)
3433                 netdev->hw_features |= NETIF_F_RXALL;
3434
3435         netdev->features          = netdev->hw_features;
3436         if (!priv->params.lro_en)
3437                 netdev->features  &= ~NETIF_F_LRO;
3438
3439         if (fcs_enabled)
3440                 netdev->features  &= ~NETIF_F_RXALL;
3441
3442 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3443         if (FT_CAP(flow_modify_en) &&
3444             FT_CAP(modify_root) &&
3445             FT_CAP(identified_miss_table_mode) &&
3446             FT_CAP(flow_table_modify)) {
3447                 netdev->hw_features      |= NETIF_F_HW_TC;
3448 #ifdef CONFIG_RFS_ACCEL
3449                 netdev->hw_features      |= NETIF_F_NTUPLE;
3450 #endif
3451         }
3452
3453         netdev->features         |= NETIF_F_HIGHDMA;
3454
3455         netdev->priv_flags       |= IFF_UNICAST_FLT;
3456
3457         mlx5e_set_netdev_dev_addr(netdev);
3458
3459 #ifdef CONFIG_NET_SWITCHDEV
3460         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3461                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3462 #endif
3463 }
3464
3465 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3466 {
3467         struct mlx5_core_dev *mdev = priv->mdev;
3468         int err;
3469
3470         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3471         if (err) {
3472                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3473                 priv->q_counter = 0;
3474         }
3475 }
3476
3477 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3478 {
3479         if (!priv->q_counter)
3480                 return;
3481
3482         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3483 }
3484
3485 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3486 {
3487         struct mlx5_core_dev *mdev = priv->mdev;
3488         u64 npages = MLX5E_REQUIRED_MTTS(priv->profile->max_nch(mdev),
3489                                          BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW));
3490         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3491         void *mkc;
3492         u32 *in;
3493         int err;
3494
3495         in = mlx5_vzalloc(inlen);
3496         if (!in)
3497                 return -ENOMEM;
3498
3499         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3500
3501         npages = min_t(u32, ALIGN(U16_MAX, 4) * 2, npages);
3502
3503         MLX5_SET(mkc, mkc, free, 1);
3504         MLX5_SET(mkc, mkc, umr_en, 1);
3505         MLX5_SET(mkc, mkc, lw, 1);
3506         MLX5_SET(mkc, mkc, lr, 1);
3507         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
3508
3509         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3510         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
3511         MLX5_SET64(mkc, mkc, len, npages << PAGE_SHIFT);
3512         MLX5_SET(mkc, mkc, translations_octword_size,
3513                  MLX5_MTT_OCTW(npages));
3514         MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
3515
3516         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen);
3517
3518         kvfree(in);
3519         return err;
3520 }
3521
3522 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3523                            struct net_device *netdev,
3524                            const struct mlx5e_profile *profile,
3525                            void *ppriv)
3526 {
3527         struct mlx5e_priv *priv = netdev_priv(netdev);
3528
3529         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3530         mlx5e_build_nic_netdev(netdev);
3531         mlx5e_vxlan_init(priv);
3532 }
3533
3534 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3535 {
3536         struct mlx5_core_dev *mdev = priv->mdev;
3537         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3538
3539         mlx5e_vxlan_cleanup(priv);
3540
3541         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3542                 mlx5_eswitch_unregister_vport_rep(esw, 0);
3543 }
3544
3545 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3546 {
3547         struct mlx5_core_dev *mdev = priv->mdev;
3548         int err;
3549         int i;
3550
3551         err = mlx5e_create_indirect_rqts(priv);
3552         if (err) {
3553                 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3554                 return err;
3555         }
3556
3557         err = mlx5e_create_direct_rqts(priv);
3558         if (err) {
3559                 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3560                 goto err_destroy_indirect_rqts;
3561         }
3562
3563         err = mlx5e_create_indirect_tirs(priv);
3564         if (err) {
3565                 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3566                 goto err_destroy_direct_rqts;
3567         }
3568
3569         err = mlx5e_create_direct_tirs(priv);
3570         if (err) {
3571                 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3572                 goto err_destroy_indirect_tirs;
3573         }
3574
3575         err = mlx5e_create_flow_steering(priv);
3576         if (err) {
3577                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3578                 goto err_destroy_direct_tirs;
3579         }
3580
3581         err = mlx5e_tc_init(priv);
3582         if (err)
3583                 goto err_destroy_flow_steering;
3584
3585         return 0;
3586
3587 err_destroy_flow_steering:
3588         mlx5e_destroy_flow_steering(priv);
3589 err_destroy_direct_tirs:
3590         mlx5e_destroy_direct_tirs(priv);
3591 err_destroy_indirect_tirs:
3592         mlx5e_destroy_indirect_tirs(priv);
3593 err_destroy_direct_rqts:
3594         for (i = 0; i < priv->profile->max_nch(mdev); i++)
3595                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3596 err_destroy_indirect_rqts:
3597         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3598         return err;
3599 }
3600
3601 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3602 {
3603         int i;
3604
3605         mlx5e_tc_cleanup(priv);
3606         mlx5e_destroy_flow_steering(priv);
3607         mlx5e_destroy_direct_tirs(priv);
3608         mlx5e_destroy_indirect_tirs(priv);
3609         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3610                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3611         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3612 }
3613
3614 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3615 {
3616         int err;
3617
3618         err = mlx5e_create_tises(priv);
3619         if (err) {
3620                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3621                 return err;
3622         }
3623
3624 #ifdef CONFIG_MLX5_CORE_EN_DCB
3625         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3626 #endif
3627         return 0;
3628 }
3629
3630 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3631 {
3632         struct net_device *netdev = priv->netdev;
3633         struct mlx5_core_dev *mdev = priv->mdev;
3634         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3635         struct mlx5_eswitch_rep rep;
3636
3637         mlx5_lag_add(mdev, netdev);
3638
3639         if (mlx5e_vxlan_allowed(mdev)) {
3640                 rtnl_lock();
3641                 udp_tunnel_get_rx_info(netdev);
3642                 rtnl_unlock();
3643         }
3644
3645         mlx5e_enable_async_events(priv);
3646         queue_work(priv->wq, &priv->set_rx_mode_work);
3647
3648         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3649                 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
3650                 rep.load = mlx5e_nic_rep_load;
3651                 rep.unload = mlx5e_nic_rep_unload;
3652                 rep.vport = 0;
3653                 rep.priv_data = priv;
3654                 mlx5_eswitch_register_vport_rep(esw, &rep);
3655         }
3656 }
3657
3658 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3659 {
3660         queue_work(priv->wq, &priv->set_rx_mode_work);
3661         mlx5e_disable_async_events(priv);
3662         mlx5_lag_remove(priv->mdev);
3663 }
3664
3665 static const struct mlx5e_profile mlx5e_nic_profile = {
3666         .init              = mlx5e_nic_init,
3667         .cleanup           = mlx5e_nic_cleanup,
3668         .init_rx           = mlx5e_init_nic_rx,
3669         .cleanup_rx        = mlx5e_cleanup_nic_rx,
3670         .init_tx           = mlx5e_init_nic_tx,
3671         .cleanup_tx        = mlx5e_cleanup_nic_tx,
3672         .enable            = mlx5e_nic_enable,
3673         .disable           = mlx5e_nic_disable,
3674         .update_stats      = mlx5e_update_stats,
3675         .max_nch           = mlx5e_get_max_num_channels,
3676         .max_tc            = MLX5E_MAX_NUM_TC,
3677 };
3678
3679 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3680                                        const struct mlx5e_profile *profile,
3681                                        void *ppriv)
3682 {
3683         int nch = profile->max_nch(mdev);
3684         struct net_device *netdev;
3685         struct mlx5e_priv *priv;
3686
3687         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3688                                     nch * profile->max_tc,
3689                                     nch);
3690         if (!netdev) {
3691                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3692                 return NULL;
3693         }
3694
3695         profile->init(mdev, netdev, profile, ppriv);
3696
3697         netif_carrier_off(netdev);
3698
3699         priv = netdev_priv(netdev);
3700
3701         priv->wq = create_singlethread_workqueue("mlx5e");
3702         if (!priv->wq)
3703                 goto err_cleanup_nic;
3704
3705         return netdev;
3706
3707 err_cleanup_nic:
3708         profile->cleanup(priv);
3709         free_netdev(netdev);
3710
3711         return NULL;
3712 }
3713
3714 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3715 {
3716         const struct mlx5e_profile *profile;
3717         struct mlx5e_priv *priv;
3718         int err;
3719
3720         priv = netdev_priv(netdev);
3721         profile = priv->profile;
3722         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
3723
3724         err = mlx5e_create_umr_mkey(priv);
3725         if (err) {
3726                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3727                 goto out;
3728         }
3729
3730         err = profile->init_tx(priv);
3731         if (err)
3732                 goto err_destroy_umr_mkey;
3733
3734         err = mlx5e_open_drop_rq(priv);
3735         if (err) {
3736                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3737                 goto err_cleanup_tx;
3738         }
3739
3740         err = profile->init_rx(priv);
3741         if (err)
3742                 goto err_close_drop_rq;
3743
3744         mlx5e_create_q_counter(priv);
3745
3746         mlx5e_init_l2_addr(priv);
3747
3748         mlx5e_set_dev_port_mtu(netdev);
3749
3750         if (profile->enable)
3751                 profile->enable(priv);
3752
3753         rtnl_lock();
3754         if (netif_running(netdev))
3755                 mlx5e_open(netdev);
3756         netif_device_attach(netdev);
3757         rtnl_unlock();
3758
3759         return 0;
3760
3761 err_close_drop_rq:
3762         mlx5e_close_drop_rq(priv);
3763
3764 err_cleanup_tx:
3765         profile->cleanup_tx(priv);
3766
3767 err_destroy_umr_mkey:
3768         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3769
3770 out:
3771         return err;
3772 }
3773
3774 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3775 {
3776         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3777         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3778         int vport;
3779         u8 mac[ETH_ALEN];
3780
3781         if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3782                 return;
3783
3784         mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3785
3786         for (vport = 1; vport < total_vfs; vport++) {
3787                 struct mlx5_eswitch_rep rep;
3788
3789                 rep.load = mlx5e_vport_rep_load;
3790                 rep.unload = mlx5e_vport_rep_unload;
3791                 rep.vport = vport;
3792                 ether_addr_copy(rep.hw_id, mac);
3793                 mlx5_eswitch_register_vport_rep(esw, &rep);
3794         }
3795 }
3796
3797 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3798 {
3799         struct mlx5e_priv *priv = netdev_priv(netdev);
3800         const struct mlx5e_profile *profile = priv->profile;
3801
3802         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3803         if (profile->disable)
3804                 profile->disable(priv);
3805
3806         flush_workqueue(priv->wq);
3807
3808         rtnl_lock();
3809         if (netif_running(netdev))
3810                 mlx5e_close(netdev);
3811         netif_device_detach(netdev);
3812         rtnl_unlock();
3813
3814         mlx5e_destroy_q_counter(priv);
3815         profile->cleanup_rx(priv);
3816         mlx5e_close_drop_rq(priv);
3817         profile->cleanup_tx(priv);
3818         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3819         cancel_delayed_work_sync(&priv->update_stats_work);
3820 }
3821
3822 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3823  * hardware contexts and to connect it to the current netdev.
3824  */
3825 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
3826 {
3827         struct mlx5e_priv *priv = vpriv;
3828         struct net_device *netdev = priv->netdev;
3829         int err;
3830
3831         if (netif_device_present(netdev))
3832                 return 0;
3833
3834         err = mlx5e_create_mdev_resources(mdev);
3835         if (err)
3836                 return err;
3837
3838         err = mlx5e_attach_netdev(mdev, netdev);
3839         if (err) {
3840                 mlx5e_destroy_mdev_resources(mdev);
3841                 return err;
3842         }
3843
3844         return 0;
3845 }
3846
3847 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
3848 {
3849         struct mlx5e_priv *priv = vpriv;
3850         struct net_device *netdev = priv->netdev;
3851
3852         if (!netif_device_present(netdev))
3853                 return;
3854
3855         mlx5e_detach_netdev(mdev, netdev);
3856         mlx5e_destroy_mdev_resources(mdev);
3857 }
3858
3859 static void *mlx5e_add(struct mlx5_core_dev *mdev)
3860 {
3861         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3862         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3863         void *ppriv = NULL;
3864         void *priv;
3865         int vport;
3866         int err;
3867         struct net_device *netdev;
3868
3869         err = mlx5e_check_required_hca_cap(mdev);
3870         if (err)
3871                 return NULL;
3872
3873         mlx5e_register_vport_rep(mdev);
3874
3875         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3876                 ppriv = &esw->offloads.vport_reps[0];
3877
3878         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
3879         if (!netdev) {
3880                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
3881                 goto err_unregister_reps;
3882         }
3883
3884         priv = netdev_priv(netdev);
3885
3886         err = mlx5e_attach(mdev, priv);
3887         if (err) {
3888                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
3889                 goto err_destroy_netdev;
3890         }
3891
3892         err = register_netdev(netdev);
3893         if (err) {
3894                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3895                 goto err_detach;
3896         }
3897
3898         return priv;
3899
3900 err_detach:
3901         mlx5e_detach(mdev, priv);
3902
3903 err_destroy_netdev:
3904         mlx5e_destroy_netdev(mdev, priv);
3905
3906 err_unregister_reps:
3907         for (vport = 1; vport < total_vfs; vport++)
3908                 mlx5_eswitch_unregister_vport_rep(esw, vport);
3909
3910         return NULL;
3911 }
3912
3913 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
3914 {
3915         const struct mlx5e_profile *profile = priv->profile;
3916         struct net_device *netdev = priv->netdev;
3917
3918         unregister_netdev(netdev);
3919         destroy_workqueue(priv->wq);
3920         if (profile->cleanup)
3921                 profile->cleanup(priv);
3922         free_netdev(netdev);
3923 }
3924
3925 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
3926 {
3927         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3928         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3929         struct mlx5e_priv *priv = vpriv;
3930         int vport;
3931
3932         for (vport = 1; vport < total_vfs; vport++)
3933                 mlx5_eswitch_unregister_vport_rep(esw, vport);
3934
3935         mlx5e_detach(mdev, vpriv);
3936         mlx5e_destroy_netdev(mdev, priv);
3937 }
3938
3939 static void *mlx5e_get_netdev(void *vpriv)
3940 {
3941         struct mlx5e_priv *priv = vpriv;
3942
3943         return priv->netdev;
3944 }
3945
3946 static struct mlx5_interface mlx5e_interface = {
3947         .add       = mlx5e_add,
3948         .remove    = mlx5e_remove,
3949         .attach    = mlx5e_attach,
3950         .detach    = mlx5e_detach,
3951         .event     = mlx5e_async_event,
3952         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
3953         .get_dev   = mlx5e_get_netdev,
3954 };
3955
3956 void mlx5e_init(void)
3957 {
3958         mlx5e_build_ptys2ethtool_map();
3959         mlx5_register_interface(&mlx5e_interface);
3960 }
3961
3962 void mlx5e_cleanup(void)
3963 {
3964         mlx5_unregister_interface(&mlx5e_interface);
3965 }