drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 enum {
  43         MLX5_EN_QP_FLUSH_TIMEOUT_MS     = 5000,
  44         MLX5_EN_QP_FLUSH_MSLEEP_QUANT   = 20,
  45         MLX5_EN_QP_FLUSH_MAX_ITER       = MLX5_EN_QP_FLUSH_TIMEOUT_MS /
  46                                           MLX5_EN_QP_FLUSH_MSLEEP_QUANT,
  47 };
  48
  49 struct mlx5e_rq_param {
  50         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  51         struct mlx5_wq_param    wq;
  52         bool                    am_enabled;
  53 };
  54
  55 struct mlx5e_sq_param {
  56         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  57         struct mlx5_wq_param       wq;
  58         u16                        max_inline;
  59         u8                         min_inline_mode;
  60         bool                       icosq;
  61 };
  62
  63 struct mlx5e_cq_param {
  64         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  65         struct mlx5_wq_param       wq;
  66         u16                        eq_ix;
  67         u8                         cq_period_mode;
  68 };
  69
  70 struct mlx5e_channel_param {
  71         struct mlx5e_rq_param      rq;
  72         struct mlx5e_sq_param      sq;
  73         struct mlx5e_sq_param      icosq;
  74         struct mlx5e_cq_param      rx_cq;
  75         struct mlx5e_cq_param      tx_cq;
  76         struct mlx5e_cq_param      icosq_cq;
  77 };
  78
  79 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  80 {
  81         struct mlx5_core_dev *mdev = priv->mdev;
  82         u8 port_state;
  83
  84         port_state = mlx5_query_vport_state(mdev,
  85                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  86
  87         if (port_state == VPORT_STATE_UP) {
  88                 netdev_info(priv->netdev, "Link up\n");
  89                 netif_carrier_on(priv->netdev);
  90         } else {
  91                 netdev_info(priv->netdev, "Link down\n");
  92                 netif_carrier_off(priv->netdev);
  93         }
  94 }
  95
  96 static void mlx5e_update_carrier_work(struct work_struct *work)
  97 {
  98         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  99                                                update_carrier_work);
 100
 101         mutex_lock(&priv->state_lock);
 102         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 103                 mlx5e_update_carrier(priv);
 104         mutex_unlock(&priv->state_lock);
 105 }
 106
 107 static void mlx5e_tx_timeout_work(struct work_struct *work)
 108 {
 109         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 110                                                tx_timeout_work);
 111         int err;
 112
 113         rtnl_lock();
 114         mutex_lock(&priv->state_lock);
 115         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 116                 goto unlock;
 117         mlx5e_close_locked(priv->netdev);
 118         err = mlx5e_open_locked(priv->netdev);
 119         if (err)
 120                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 121                            err);
 122 unlock:
 123         mutex_unlock(&priv->state_lock);
 124         rtnl_unlock();
 125 }
 126
 127 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 128 {
 129         struct mlx5e_sw_stats *s = &priv->stats.sw;
 130         struct mlx5e_rq_stats *rq_stats;
 131         struct mlx5e_sq_stats *sq_stats;
 132         u64 tx_offload_none = 0;
 133         int i, j;
 134
 135         memset(s, 0, sizeof(*s));
 136         for (i = 0; i < priv->params.num_channels; i++) {
 137                 rq_stats = &priv->channel[i]->rq.stats;
 138
 139                 s->rx_packets   += rq_stats->packets;
 140                 s->rx_bytes     += rq_stats->bytes;
 141                 s->rx_lro_packets += rq_stats->lro_packets;
 142                 s->rx_lro_bytes += rq_stats->lro_bytes;
 143                 s->rx_csum_none += rq_stats->csum_none;
 144                 s->rx_csum_complete += rq_stats->csum_complete;
 145                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 146                 s->rx_wqe_err   += rq_stats->wqe_err;
 147                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 148                 s->rx_mpwqe_frag   += rq_stats->mpwqe_frag;
 149                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 150                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 151                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 152
 153                 for (j = 0; j < priv->params.num_tc; j++) {
 154                         sq_stats = &priv->channel[i]->sq[j].stats;
 155
 156                         s->tx_packets           += sq_stats->packets;
 157                         s->tx_bytes             += sq_stats->bytes;
 158                         s->tx_tso_packets       += sq_stats->tso_packets;
 159                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 160                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 161                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 162                         s->tx_queue_stopped     += sq_stats->stopped;
 163                         s->tx_queue_wake        += sq_stats->wake;
 164                         s->tx_queue_dropped     += sq_stats->dropped;
 165                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 166                         tx_offload_none         += sq_stats->csum_none;
 167                 }
 168         }
 169
 170         /* Update calculated offload counters */
 171         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
 172         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 173
 174         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 175                                 priv->stats.pport.phy_counters,
 176                                 counter_set.phys_layer_cntrs.link_down_events);
 177 }
 178
 179 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 180 {
 181         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 182         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 183         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 184         struct mlx5_core_dev *mdev = priv->mdev;
 185
 186         memset(in, 0, sizeof(in));
 187
 188         MLX5_SET(query_vport_counter_in, in, opcode,
 189                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 190         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 191         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 192
 193         memset(out, 0, outlen);
 194
 195         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 196 }
 197
 198 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 199 {
 200         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 201         struct mlx5_core_dev *mdev = priv->mdev;
 202         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 203         int prio;
 204         void *out;
 205         u32 *in;
 206
 207         in = mlx5_vzalloc(sz);
 208         if (!in)
 209                 goto free_out;
 210
 211         MLX5_SET(ppcnt_reg, in, local_port, 1);
 212
 213         out = pstats->IEEE_802_3_counters;
 214         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 215         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 216
 217         out = pstats->RFC_2863_counters;
 218         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 219         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 220
 221         out = pstats->RFC_2819_counters;
 222         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 223         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 224
 225         out = pstats->phy_counters;
 226         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 227         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 228
 229         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 230         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 231                 out = pstats->per_prio_counters[prio];
 232                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 233                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 234                                      MLX5_REG_PPCNT, 0, 0);
 235         }
 236
 237 free_out:
 238         kvfree(in);
 239 }
 240
 241 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 242 {
 243         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 244
 245         if (!priv->q_counter)
 246                 return;
 247
 248         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 249                                       &qcnt->rx_out_of_buffer);
 250 }
 251
 252 void mlx5e_update_stats(struct mlx5e_priv *priv)
 253 {
 254         mlx5e_update_q_counter(priv);
 255         mlx5e_update_vport_counters(priv);
 256         mlx5e_update_pport_counters(priv);
 257         mlx5e_update_sw_counters(priv);
 258 }
 259
 260 void mlx5e_update_stats_work(struct work_struct *work)
 261 {
 262         struct delayed_work *dwork = to_delayed_work(work);
 263         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 264                                                update_stats_work);
 265         mutex_lock(&priv->state_lock);
 266         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 267                 priv->profile->update_stats(priv);
 268                 queue_delayed_work(priv->wq, dwork,
 269                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 270         }
 271         mutex_unlock(&priv->state_lock);
 272 }
 273
 274 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 275                               enum mlx5_dev_event event, unsigned long param)
 276 {
 277         struct mlx5e_priv *priv = vpriv;
 278
 279         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 280                 return;
 281
 282         switch (event) {
 283         case MLX5_DEV_EVENT_PORT_UP:
 284         case MLX5_DEV_EVENT_PORT_DOWN:
 285                 queue_work(priv->wq, &priv->update_carrier_work);
 286                 break;
 287
 288         default:
 289                 break;
 290         }
 291 }
 292
 293 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 294 {
 295         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 296 }
 297
 298 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 299 {
 300         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 301         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 302 }
 303
 304 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 305 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 306
 307 static int mlx5e_create_rq(struct mlx5e_channel *c,
 308                            struct mlx5e_rq_param *param,
 309                            struct mlx5e_rq *rq)
 310 {
 311         struct mlx5e_priv *priv = c->priv;
 312         struct mlx5_core_dev *mdev = priv->mdev;
 313         void *rqc = param->rqc;
 314         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 315         u32 byte_count;
 316         int wq_sz;
 317         int err;
 318         int i;
 319
 320         param->wq.db_numa_node = cpu_to_node(c->cpu);
 321
 322         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 323                                 &rq->wq_ctrl);
 324         if (err)
 325                 return err;
 326
 327         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 328
 329         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 330
 331         switch (priv->params.rq_wq_type) {
 332         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 333                 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
 334                                             GFP_KERNEL, cpu_to_node(c->cpu));
 335                 if (!rq->wqe_info) {
 336                         err = -ENOMEM;
 337                         goto err_rq_wq_destroy;
 338                 }
 339                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 340                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 341                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 342
 343                 rq->mpwqe_mtt_offset = c->ix *
 344                         MLX5E_REQUIRED_MTTS(1, BIT(priv->params.log_rq_size));
 345
 346                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 347                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 348                 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 349                 byte_count = rq->wqe_sz;
 350                 break;
 351         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 352                 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 353                                        cpu_to_node(c->cpu));
 354                 if (!rq->skb) {
 355                         err = -ENOMEM;
 356                         goto err_rq_wq_destroy;
 357                 }
 358                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 359                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 360                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 361
 362                 rq->wqe_sz = (priv->params.lro_en) ?
 363                                 priv->params.lro_wqe_sz :
 364                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 365                 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
 366                 byte_count = rq->wqe_sz;
 367                 byte_count |= MLX5_HW_START_PADDING;
 368         }
 369
 370         for (i = 0; i < wq_sz; i++) {
 371                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 372
 373                 wqe->data.byte_count = cpu_to_be32(byte_count);
 374         }
 375
 376         INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
 377         rq->am.mode = priv->params.rx_cq_period_mode;
 378
 379         rq->wq_type = priv->params.rq_wq_type;
 380         rq->pdev    = c->pdev;
 381         rq->netdev  = c->netdev;
 382         rq->tstamp  = &priv->tstamp;
 383         rq->channel = c;
 384         rq->ix      = c->ix;
 385         rq->priv    = c->priv;
 386         rq->mkey_be = c->mkey_be;
 387         rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 388
 389         return 0;
 390
 391 err_rq_wq_destroy:
 392         mlx5_wq_destroy(&rq->wq_ctrl);
 393
 394         return err;
 395 }
 396
 397 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 398 {
 399         switch (rq->wq_type) {
 400         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 401                 kfree(rq->wqe_info);
 402                 break;
 403         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 404                 kfree(rq->skb);
 405         }
 406
 407         mlx5_wq_destroy(&rq->wq_ctrl);
 408 }
 409
 410 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 411 {
 412         struct mlx5e_priv *priv = rq->priv;
 413         struct mlx5_core_dev *mdev = priv->mdev;
 414
 415         void *in;
 416         void *rqc;
 417         void *wq;
 418         int inlen;
 419         int err;
 420
 421         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 422                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 423         in = mlx5_vzalloc(inlen);
 424         if (!in)
 425                 return -ENOMEM;
 426
 427         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 428         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 429
 430         memcpy(rqc, param->rqc, sizeof(param->rqc));
 431
 432         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 433         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 434         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 435         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 436         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 437                                                 MLX5_ADAPTER_PAGE_SHIFT);
 438         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 439
 440         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 441                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 442
 443         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 444
 445         kvfree(in);
 446
 447         return err;
 448 }
 449
 450 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 451                                  int next_state)
 452 {
 453         struct mlx5e_channel *c = rq->channel;
 454         struct mlx5e_priv *priv = c->priv;
 455         struct mlx5_core_dev *mdev = priv->mdev;
 456
 457         void *in;
 458         void *rqc;
 459         int inlen;
 460         int err;
 461
 462         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 463         in = mlx5_vzalloc(inlen);
 464         if (!in)
 465                 return -ENOMEM;
 466
 467         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 468
 469         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 470         MLX5_SET(rqc, rqc, state, next_state);
 471
 472         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 473
 474         kvfree(in);
 475
 476         return err;
 477 }
 478
 479 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 480 {
 481         struct mlx5e_channel *c = rq->channel;
 482         struct mlx5e_priv *priv = c->priv;
 483         struct mlx5_core_dev *mdev = priv->mdev;
 484
 485         void *in;
 486         void *rqc;
 487         int inlen;
 488         int err;
 489
 490         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 491         in = mlx5_vzalloc(inlen);
 492         if (!in)
 493                 return -ENOMEM;
 494
 495         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 496
 497         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 498         MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
 499         MLX5_SET(rqc, rqc, vsd, vsd);
 500         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 501
 502         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 503
 504         kvfree(in);
 505
 506         return err;
 507 }
 508
 509 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 510 {
 511         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 512 }
 513
 514 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 515 {
 516         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 517         struct mlx5e_channel *c = rq->channel;
 518         struct mlx5e_priv *priv = c->priv;
 519         struct mlx5_wq_ll *wq = &rq->wq;
 520
 521         while (time_before(jiffies, exp_time)) {
 522                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 523                         return 0;
 524
 525                 msleep(20);
 526         }
 527
 528         return -ETIMEDOUT;
 529 }
 530
 531 static int mlx5e_open_rq(struct mlx5e_channel *c,
 532                          struct mlx5e_rq_param *param,
 533                          struct mlx5e_rq *rq)
 534 {
 535         struct mlx5e_sq *sq = &c->icosq;
 536         u16 pi = sq->pc & sq->wq.sz_m1;
 537         int err;
 538
 539         err = mlx5e_create_rq(c, param, rq);
 540         if (err)
 541                 return err;
 542
 543         err = mlx5e_enable_rq(rq, param);
 544         if (err)
 545                 goto err_destroy_rq;
 546
 547         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 548         if (err)
 549                 goto err_disable_rq;
 550
 551         if (param->am_enabled)
 552                 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 553
 554         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 555
 556         sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
 557         sq->ico_wqe_info[pi].num_wqebbs = 1;
 558         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 559
 560         return 0;
 561
 562 err_disable_rq:
 563         mlx5e_disable_rq(rq);
 564 err_destroy_rq:
 565         mlx5e_destroy_rq(rq);
 566
 567         return err;
 568 }
 569
 570 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 571 {
 572         int tout = 0;
 573         int err;
 574
 575         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 576         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 577
 578         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 579         while (!mlx5_wq_ll_is_empty(&rq->wq) && !err &&
 580                tout++ < MLX5_EN_QP_FLUSH_MAX_ITER)
 581                 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
 582
 583         if (err || tout == MLX5_EN_QP_FLUSH_MAX_ITER)
 584                 set_bit(MLX5E_RQ_STATE_FLUSH_TIMEOUT, &rq->state);
 585
 586         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 587         napi_synchronize(&rq->channel->napi);
 588
 589         cancel_work_sync(&rq->am.work);
 590
 591         mlx5e_disable_rq(rq);
 592         mlx5e_free_rx_descs(rq);
 593         mlx5e_destroy_rq(rq);
 594 }
 595
 596 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 597 {
 598         kfree(sq->wqe_info);
 599         kfree(sq->dma_fifo);
 600         kfree(sq->skb);
 601 }
 602
 603 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 604 {
 605         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 606         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 607
 608         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 609         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 610                                     numa);
 611         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 612                                     numa);
 613
 614         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 615                 mlx5e_free_sq_db(sq);
 616                 return -ENOMEM;
 617         }
 618
 619         sq->dma_fifo_mask = df_sz - 1;
 620
 621         return 0;
 622 }
 623
 624 static int mlx5e_create_sq(struct mlx5e_channel *c,
 625                            int tc,
 626                            struct mlx5e_sq_param *param,
 627                            struct mlx5e_sq *sq)
 628 {
 629         struct mlx5e_priv *priv = c->priv;
 630         struct mlx5_core_dev *mdev = priv->mdev;
 631
 632         void *sqc = param->sqc;
 633         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 634         int err;
 635
 636         err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
 637         if (err)
 638                 return err;
 639
 640         param->wq.db_numa_node = cpu_to_node(c->cpu);
 641
 642         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 643                                  &sq->wq_ctrl);
 644         if (err)
 645                 goto err_unmap_free_uar;
 646
 647         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 648         if (sq->uar.bf_map) {
 649                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 650                 sq->uar_map = sq->uar.bf_map;
 651         } else {
 652                 sq->uar_map = sq->uar.map;
 653         }
 654         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 655         sq->max_inline  = param->max_inline;
 656         sq->min_inline_mode =
 657                 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
 658                 param->min_inline_mode : 0;
 659
 660         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 661         if (err)
 662                 goto err_sq_wq_destroy;
 663
 664         if (param->icosq) {
 665                 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 666
 667                 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
 668                                                 wq_sz,
 669                                                 GFP_KERNEL,
 670                                                 cpu_to_node(c->cpu));
 671                 if (!sq->ico_wqe_info) {
 672                         err = -ENOMEM;
 673                         goto err_free_sq_db;
 674                 }
 675         } else {
 676                 int txq_ix;
 677
 678                 txq_ix = c->ix + tc * priv->params.num_channels;
 679                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 680                 priv->txq_to_sq_map[txq_ix] = sq;
 681         }
 682
 683         sq->pdev      = c->pdev;
 684         sq->tstamp    = &priv->tstamp;
 685         sq->mkey_be   = c->mkey_be;
 686         sq->channel   = c;
 687         sq->tc        = tc;
 688         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 689         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 690
 691         return 0;
 692
 693 err_free_sq_db:
 694         mlx5e_free_sq_db(sq);
 695
 696 err_sq_wq_destroy:
 697         mlx5_wq_destroy(&sq->wq_ctrl);
 698
 699 err_unmap_free_uar:
 700         mlx5_unmap_free_uar(mdev, &sq->uar);
 701
 702         return err;
 703 }
 704
 705 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 706 {
 707         struct mlx5e_channel *c = sq->channel;
 708         struct mlx5e_priv *priv = c->priv;
 709
 710         kfree(sq->ico_wqe_info);
 711         mlx5e_free_sq_db(sq);
 712         mlx5_wq_destroy(&sq->wq_ctrl);
 713         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 714 }
 715
 716 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 717 {
 718         struct mlx5e_channel *c = sq->channel;
 719         struct mlx5e_priv *priv = c->priv;
 720         struct mlx5_core_dev *mdev = priv->mdev;
 721
 722         void *in;
 723         void *sqc;
 724         void *wq;
 725         int inlen;
 726         int err;
 727
 728         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 729                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 730         in = mlx5_vzalloc(inlen);
 731         if (!in)
 732                 return -ENOMEM;
 733
 734         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 735         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 736
 737         memcpy(sqc, param->sqc, sizeof(param->sqc));
 738
 739         MLX5_SET(sqc,  sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
 740         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
 741         MLX5_SET(sqc,  sqc, min_wqe_inline_mode, sq->min_inline_mode);
 742         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 743         MLX5_SET(sqc,  sqc, tis_lst_sz,         param->icosq ? 0 : 1);
 744         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 745
 746         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 747         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 748         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 749                                           MLX5_ADAPTER_PAGE_SHIFT);
 750         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 751
 752         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 753                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 754
 755         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 756
 757         kvfree(in);
 758
 759         return err;
 760 }
 761
 762 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
 763                            int next_state, bool update_rl, int rl_index)
 764 {
 765         struct mlx5e_channel *c = sq->channel;
 766         struct mlx5e_priv *priv = c->priv;
 767         struct mlx5_core_dev *mdev = priv->mdev;
 768
 769         void *in;
 770         void *sqc;
 771         int inlen;
 772         int err;
 773
 774         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 775         in = mlx5_vzalloc(inlen);
 776         if (!in)
 777                 return -ENOMEM;
 778
 779         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 780
 781         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 782         MLX5_SET(sqc, sqc, state, next_state);
 783         if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
 784                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
 785                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, rl_index);
 786         }
 787
 788         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 789
 790         kvfree(in);
 791
 792         return err;
 793 }
 794
 795 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 796 {
 797         struct mlx5e_channel *c = sq->channel;
 798         struct mlx5e_priv *priv = c->priv;
 799         struct mlx5_core_dev *mdev = priv->mdev;
 800
 801         mlx5_core_destroy_sq(mdev, sq->sqn);
 802         if (sq->rate_limit)
 803                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
 804 }
 805
 806 static int mlx5e_open_sq(struct mlx5e_channel *c,
 807                          int tc,
 808                          struct mlx5e_sq_param *param,
 809                          struct mlx5e_sq *sq)
 810 {
 811         int err;
 812
 813         err = mlx5e_create_sq(c, tc, param, sq);
 814         if (err)
 815                 return err;
 816
 817         err = mlx5e_enable_sq(sq, param);
 818         if (err)
 819                 goto err_destroy_sq;
 820
 821         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
 822                               false, 0);
 823         if (err)
 824                 goto err_disable_sq;
 825
 826         if (sq->txq) {
 827                 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 828                 netdev_tx_reset_queue(sq->txq);
 829                 netif_tx_start_queue(sq->txq);
 830         }
 831
 832         return 0;
 833
 834 err_disable_sq:
 835         mlx5e_disable_sq(sq);
 836 err_destroy_sq:
 837         mlx5e_destroy_sq(sq);
 838
 839         return err;
 840 }
 841
 842 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 843 {
 844         __netif_tx_lock_bh(txq);
 845         netif_tx_stop_queue(txq);
 846         __netif_tx_unlock_bh(txq);
 847 }
 848
 849 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 850 {
 851         int tout = 0;
 852         int err;
 853
 854         if (sq->txq) {
 855                 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 856                 /* prevent netif_tx_wake_queue */
 857                 napi_synchronize(&sq->channel->napi);
 858                 netif_tx_disable_queue(sq->txq);
 859
 860                 /* ensure hw is notified of all pending wqes */
 861                 if (mlx5e_sq_has_room_for(sq, 1))
 862                         mlx5e_send_nop(sq, true);
 863
 864                 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
 865                                       MLX5_SQC_STATE_ERR, false, 0);
 866                 if (err)
 867                         set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
 868         }
 869
 870         /* wait till sq is empty, unless a TX timeout occurred on this SQ */
 871         while (sq->cc != sq->pc &&
 872                !test_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state)) {
 873                 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
 874                 if (tout++ > MLX5_EN_QP_FLUSH_MAX_ITER)
 875                         set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
 876         }
 877
 878         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 879         napi_synchronize(&sq->channel->napi);
 880
 881         mlx5e_free_tx_descs(sq);
 882         mlx5e_disable_sq(sq);
 883         mlx5e_destroy_sq(sq);
 884 }
 885
 886 static int mlx5e_create_cq(struct mlx5e_channel *c,
 887                            struct mlx5e_cq_param *param,
 888                            struct mlx5e_cq *cq)
 889 {
 890         struct mlx5e_priv *priv = c->priv;
 891         struct mlx5_core_dev *mdev = priv->mdev;
 892         struct mlx5_core_cq *mcq = &cq->mcq;
 893         int eqn_not_used;
 894         unsigned int irqn;
 895         int err;
 896         u32 i;
 897
 898         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 899         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 900         param->eq_ix   = c->ix;
 901
 902         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 903                                &cq->wq_ctrl);
 904         if (err)
 905                 return err;
 906
 907         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 908
 909         cq->napi        = &c->napi;
 910
 911         mcq->cqe_sz     = 64;
 912         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 913         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 914         *mcq->set_ci_db = 0;
 915         *mcq->arm_db    = 0;
 916         mcq->vector     = param->eq_ix;
 917         mcq->comp       = mlx5e_completion_event;
 918         mcq->event      = mlx5e_cq_error_event;
 919         mcq->irqn       = irqn;
 920         mcq->uar        = &mdev->mlx5e_res.cq_uar;
 921
 922         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 923                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 924
 925                 cqe->op_own = 0xf1;
 926         }
 927
 928         cq->channel = c;
 929         cq->priv = priv;
 930
 931         return 0;
 932 }
 933
 934 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 935 {
 936         mlx5_wq_destroy(&cq->wq_ctrl);
 937 }
 938
 939 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 940 {
 941         struct mlx5e_priv *priv = cq->priv;
 942         struct mlx5_core_dev *mdev = priv->mdev;
 943         struct mlx5_core_cq *mcq = &cq->mcq;
 944
 945         void *in;
 946         void *cqc;
 947         int inlen;
 948         unsigned int irqn_not_used;
 949         int eqn;
 950         int err;
 951
 952         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 953                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 954         in = mlx5_vzalloc(inlen);
 955         if (!in)
 956                 return -ENOMEM;
 957
 958         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 959
 960         memcpy(cqc, param->cqc, sizeof(param->cqc));
 961
 962         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 963                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 964
 965         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 966
 967         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
 968         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 969         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 970         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 971                                             MLX5_ADAPTER_PAGE_SHIFT);
 972         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 973
 974         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 975
 976         kvfree(in);
 977
 978         if (err)
 979                 return err;
 980
 981         mlx5e_cq_arm(cq);
 982
 983         return 0;
 984 }
 985
 986 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 987 {
 988         struct mlx5e_priv *priv = cq->priv;
 989         struct mlx5_core_dev *mdev = priv->mdev;
 990
 991         mlx5_core_destroy_cq(mdev, &cq->mcq);
 992 }
 993
 994 static int mlx5e_open_cq(struct mlx5e_channel *c,
 995                          struct mlx5e_cq_param *param,
 996                          struct mlx5e_cq *cq,
 997                          struct mlx5e_cq_moder moderation)
 998 {
 999         int err;
1000         struct mlx5e_priv *priv = c->priv;
1001         struct mlx5_core_dev *mdev = priv->mdev;
1002
1003         err = mlx5e_create_cq(c, param, cq);
1004         if (err)
1005                 return err;
1006
1007         err = mlx5e_enable_cq(cq, param);
1008         if (err)
1009                 goto err_destroy_cq;
1010
1011         if (MLX5_CAP_GEN(mdev, cq_moderation))
1012                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1013                                                moderation.usec,
1014                                                moderation.pkts);
1015         return 0;
1016
1017 err_destroy_cq:
1018         mlx5e_destroy_cq(cq);
1019
1020         return err;
1021 }
1022
1023 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1024 {
1025         mlx5e_disable_cq(cq);
1026         mlx5e_destroy_cq(cq);
1027 }
1028
1029 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1030 {
1031         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1032 }
1033
1034 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1035                              struct mlx5e_channel_param *cparam)
1036 {
1037         struct mlx5e_priv *priv = c->priv;
1038         int err;
1039         int tc;
1040
1041         for (tc = 0; tc < c->num_tc; tc++) {
1042                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1043                                     priv->params.tx_cq_moderation);
1044                 if (err)
1045                         goto err_close_tx_cqs;
1046         }
1047
1048         return 0;
1049
1050 err_close_tx_cqs:
1051         for (tc--; tc >= 0; tc--)
1052                 mlx5e_close_cq(&c->sq[tc].cq);
1053
1054         return err;
1055 }
1056
1057 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1058 {
1059         int tc;
1060
1061         for (tc = 0; tc < c->num_tc; tc++)
1062                 mlx5e_close_cq(&c->sq[tc].cq);
1063 }
1064
1065 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1066                           struct mlx5e_channel_param *cparam)
1067 {
1068         int err;
1069         int tc;
1070
1071         for (tc = 0; tc < c->num_tc; tc++) {
1072                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1073                 if (err)
1074                         goto err_close_sqs;
1075         }
1076
1077         return 0;
1078
1079 err_close_sqs:
1080         for (tc--; tc >= 0; tc--)
1081                 mlx5e_close_sq(&c->sq[tc]);
1082
1083         return err;
1084 }
1085
1086 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1087 {
1088         int tc;
1089
1090         for (tc = 0; tc < c->num_tc; tc++)
1091                 mlx5e_close_sq(&c->sq[tc]);
1092 }
1093
1094 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1095 {
1096         int i;
1097
1098         for (i = 0; i < priv->profile->max_tc; i++)
1099                 priv->channeltc_to_txq_map[ix][i] =
1100                         ix + i * priv->params.num_channels;
1101 }
1102
1103 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1104                                 struct mlx5e_sq *sq, u32 rate)
1105 {
1106         struct mlx5e_priv *priv = netdev_priv(dev);
1107         struct mlx5_core_dev *mdev = priv->mdev;
1108         u16 rl_index = 0;
1109         int err;
1110
1111         if (rate == sq->rate_limit)
1112                 /* nothing to do */
1113                 return 0;
1114
1115         if (sq->rate_limit)
1116                 /* remove current rl index to free space to next ones */
1117                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1118
1119         sq->rate_limit = 0;
1120
1121         if (rate) {
1122                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1123                 if (err) {
1124                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1125                                    rate, err);
1126                         return err;
1127                 }
1128         }
1129
1130         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1131                               MLX5_SQC_STATE_RDY, true, rl_index);
1132         if (err) {
1133                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1134                            rate, err);
1135                 /* remove the rate from the table */
1136                 if (rate)
1137                         mlx5_rl_remove_rate(mdev, rate);
1138                 return err;
1139         }
1140
1141         sq->rate_limit = rate;
1142         return 0;
1143 }
1144
1145 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1146 {
1147         struct mlx5e_priv *priv = netdev_priv(dev);
1148         struct mlx5_core_dev *mdev = priv->mdev;
1149         struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1150         int err = 0;
1151
1152         if (!mlx5_rl_is_supported(mdev)) {
1153                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1154                 return -EINVAL;
1155         }
1156
1157         /* rate is given in Mb/sec, HW config is in Kb/sec */
1158         rate = rate << 10;
1159
1160         /* Check whether rate in valid range, 0 is always valid */
1161         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1162                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1163                 return -ERANGE;
1164         }
1165
1166         mutex_lock(&priv->state_lock);
1167         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1168                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1169         if (!err)
1170                 priv->tx_rates[index] = rate;
1171         mutex_unlock(&priv->state_lock);
1172
1173         return err;
1174 }
1175
1176 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1177                               struct mlx5e_channel_param *cparam,
1178                               struct mlx5e_channel **cp)
1179 {
1180         struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1181         struct net_device *netdev = priv->netdev;
1182         struct mlx5e_cq_moder rx_cq_profile;
1183         int cpu = mlx5e_get_cpu(priv, ix);
1184         struct mlx5e_channel *c;
1185         struct mlx5e_sq *sq;
1186         int err;
1187         int i;
1188
1189         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1190         if (!c)
1191                 return -ENOMEM;
1192
1193         c->priv     = priv;
1194         c->ix       = ix;
1195         c->cpu      = cpu;
1196         c->pdev     = &priv->mdev->pdev->dev;
1197         c->netdev   = priv->netdev;
1198         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1199         c->num_tc   = priv->params.num_tc;
1200
1201         if (priv->params.rx_am_enabled)
1202                 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1203         else
1204                 rx_cq_profile = priv->params.rx_cq_moderation;
1205
1206         mlx5e_build_channeltc_to_txq_map(priv, ix);
1207
1208         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1209
1210         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1211         if (err)
1212                 goto err_napi_del;
1213
1214         err = mlx5e_open_tx_cqs(c, cparam);
1215         if (err)
1216                 goto err_close_icosq_cq;
1217
1218         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1219                             rx_cq_profile);
1220         if (err)
1221                 goto err_close_tx_cqs;
1222
1223         napi_enable(&c->napi);
1224
1225         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1226         if (err)
1227                 goto err_disable_napi;
1228
1229         err = mlx5e_open_sqs(c, cparam);
1230         if (err)
1231                 goto err_close_icosq;
1232
1233         for (i = 0; i < priv->params.num_tc; i++) {
1234                 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1235
1236                 if (priv->tx_rates[txq_ix]) {
1237                         sq = priv->txq_to_sq_map[txq_ix];
1238                         mlx5e_set_sq_maxrate(priv->netdev, sq,
1239                                              priv->tx_rates[txq_ix]);
1240                 }
1241         }
1242
1243         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1244         if (err)
1245                 goto err_close_sqs;
1246
1247         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1248         *cp = c;
1249
1250         return 0;
1251
1252 err_close_sqs:
1253         mlx5e_close_sqs(c);
1254
1255 err_close_icosq:
1256         mlx5e_close_sq(&c->icosq);
1257
1258 err_disable_napi:
1259         napi_disable(&c->napi);
1260         mlx5e_close_cq(&c->rq.cq);
1261
1262 err_close_tx_cqs:
1263         mlx5e_close_tx_cqs(c);
1264
1265 err_close_icosq_cq:
1266         mlx5e_close_cq(&c->icosq.cq);
1267
1268 err_napi_del:
1269         netif_napi_del(&c->napi);
1270         napi_hash_del(&c->napi);
1271         kfree(c);
1272
1273         return err;
1274 }
1275
1276 static void mlx5e_close_channel(struct mlx5e_channel *c)
1277 {
1278         mlx5e_close_rq(&c->rq);
1279         mlx5e_close_sqs(c);
1280         mlx5e_close_sq(&c->icosq);
1281         napi_disable(&c->napi);
1282         mlx5e_close_cq(&c->rq.cq);
1283         mlx5e_close_tx_cqs(c);
1284         mlx5e_close_cq(&c->icosq.cq);
1285         netif_napi_del(&c->napi);
1286
1287         napi_hash_del(&c->napi);
1288         synchronize_rcu();
1289
1290         kfree(c);
1291 }
1292
1293 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1294                                  struct mlx5e_rq_param *param)
1295 {
1296         void *rqc = param->rqc;
1297         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1298
1299         switch (priv->params.rq_wq_type) {
1300         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1301                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1302                          priv->params.mpwqe_log_num_strides - 9);
1303                 MLX5_SET(wq, wq, log_wqe_stride_size,
1304                          priv->params.mpwqe_log_stride_sz - 6);
1305                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1306                 break;
1307         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1308                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1309         }
1310
1311         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1312         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1313         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1314         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1315         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1316
1317         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1318         param->wq.linear = 1;
1319
1320         param->am_enabled = priv->params.rx_am_enabled;
1321 }
1322
1323 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1324 {
1325         void *rqc = param->rqc;
1326         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1327
1328         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1329         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1330 }
1331
1332 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1333                                         struct mlx5e_sq_param *param)
1334 {
1335         void *sqc = param->sqc;
1336         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1337
1338         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1339         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1340
1341         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1342 }
1343
1344 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1345                                  struct mlx5e_sq_param *param)
1346 {
1347         void *sqc = param->sqc;
1348         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1349
1350         mlx5e_build_sq_param_common(priv, param);
1351         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1352
1353         param->max_inline = priv->params.tx_max_inline;
1354         param->min_inline_mode = priv->params.tx_min_inline_mode;
1355 }
1356
1357 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1358                                         struct mlx5e_cq_param *param)
1359 {
1360         void *cqc = param->cqc;
1361
1362         MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
1363 }
1364
1365 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1366                                     struct mlx5e_cq_param *param)
1367 {
1368         void *cqc = param->cqc;
1369         u8 log_cq_size;
1370
1371         switch (priv->params.rq_wq_type) {
1372         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1373                 log_cq_size = priv->params.log_rq_size +
1374                         priv->params.mpwqe_log_num_strides;
1375                 break;
1376         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1377                 log_cq_size = priv->params.log_rq_size;
1378         }
1379
1380         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1381         if (priv->params.rx_cqe_compress) {
1382                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1383                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1384         }
1385
1386         mlx5e_build_common_cq_param(priv, param);
1387
1388         param->cq_period_mode = priv->params.rx_cq_period_mode;
1389 }
1390
1391 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1392                                     struct mlx5e_cq_param *param)
1393 {
1394         void *cqc = param->cqc;
1395
1396         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1397
1398         mlx5e_build_common_cq_param(priv, param);
1399
1400         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1401 }
1402
1403 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1404                                      struct mlx5e_cq_param *param,
1405                                      u8 log_wq_size)
1406 {
1407         void *cqc = param->cqc;
1408
1409         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1410
1411         mlx5e_build_common_cq_param(priv, param);
1412
1413         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1414 }
1415
1416 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1417                                     struct mlx5e_sq_param *param,
1418                                     u8 log_wq_size)
1419 {
1420         void *sqc = param->sqc;
1421         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1422
1423         mlx5e_build_sq_param_common(priv, param);
1424
1425         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1426         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1427
1428         param->icosq = true;
1429 }
1430
1431 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1432 {
1433         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1434
1435         mlx5e_build_rq_param(priv, &cparam->rq);
1436         mlx5e_build_sq_param(priv, &cparam->sq);
1437         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1438         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1439         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1440         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1441 }
1442
1443 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1444 {
1445         struct mlx5e_channel_param *cparam;
1446         int nch = priv->params.num_channels;
1447         int err = -ENOMEM;
1448         int i;
1449         int j;
1450
1451         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1452                                 GFP_KERNEL);
1453
1454         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1455                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1456
1457         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1458
1459         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1460                 goto err_free_txq_to_sq_map;
1461
1462         mlx5e_build_channel_param(priv, cparam);
1463
1464         for (i = 0; i < nch; i++) {
1465                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1466                 if (err)
1467                         goto err_close_channels;
1468         }
1469
1470         for (j = 0; j < nch; j++) {
1471                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1472                 if (err)
1473                         goto err_close_channels;
1474         }
1475
1476         /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1477          * polling for inactive tx queues.
1478          */
1479         netif_tx_start_all_queues(priv->netdev);
1480
1481         kfree(cparam);
1482         return 0;
1483
1484 err_close_channels:
1485         for (i--; i >= 0; i--)
1486                 mlx5e_close_channel(priv->channel[i]);
1487
1488 err_free_txq_to_sq_map:
1489         kfree(priv->txq_to_sq_map);
1490         kfree(priv->channel);
1491         kfree(cparam);
1492
1493         return err;
1494 }
1495
1496 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1497 {
1498         int i;
1499
1500         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1501          * polling for inactive tx queues.
1502          */
1503         netif_tx_stop_all_queues(priv->netdev);
1504         netif_tx_disable(priv->netdev);
1505
1506         for (i = 0; i < priv->params.num_channels; i++)
1507                 mlx5e_close_channel(priv->channel[i]);
1508
1509         kfree(priv->txq_to_sq_map);
1510         kfree(priv->channel);
1511 }
1512
1513 static int mlx5e_rx_hash_fn(int hfunc)
1514 {
1515         return (hfunc == ETH_RSS_HASH_TOP) ?
1516                MLX5_RX_HASH_FN_TOEPLITZ :
1517                MLX5_RX_HASH_FN_INVERTED_XOR8;
1518 }
1519
1520 static int mlx5e_bits_invert(unsigned long a, int size)
1521 {
1522         int inv = 0;
1523         int i;
1524
1525         for (i = 0; i < size; i++)
1526                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1527
1528         return inv;
1529 }
1530
1531 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1532 {
1533         int i;
1534
1535         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1536                 int ix = i;
1537                 u32 rqn;
1538
1539                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1540                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1541
1542                 ix = priv->params.indirection_rqt[ix];
1543                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1544                                 priv->channel[ix]->rq.rqn :
1545                                 priv->drop_rq.rqn;
1546                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1547         }
1548 }
1549
1550 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1551                                       int ix)
1552 {
1553         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1554                         priv->channel[ix]->rq.rqn :
1555                         priv->drop_rq.rqn;
1556
1557         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1558 }
1559
1560 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1561                             int ix, struct mlx5e_rqt *rqt)
1562 {
1563         struct mlx5_core_dev *mdev = priv->mdev;
1564         void *rqtc;
1565         int inlen;
1566         int err;
1567         u32 *in;
1568
1569         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1570         in = mlx5_vzalloc(inlen);
1571         if (!in)
1572                 return -ENOMEM;
1573
1574         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1575
1576         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1577         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1578
1579         if (sz > 1) /* RSS */
1580                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1581         else
1582                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1583
1584         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1585         if (!err)
1586                 rqt->enabled = true;
1587
1588         kvfree(in);
1589         return err;
1590 }
1591
1592 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1593 {
1594         rqt->enabled = false;
1595         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1596 }
1597
1598 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1599 {
1600         struct mlx5e_rqt *rqt = &priv->indir_rqt;
1601
1602         return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1603 }
1604
1605 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1606 {
1607         struct mlx5e_rqt *rqt;
1608         int err;
1609         int ix;
1610
1611         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1612                 rqt = &priv->direct_tir[ix].rqt;
1613                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1614                 if (err)
1615                         goto err_destroy_rqts;
1616         }
1617
1618         return 0;
1619
1620 err_destroy_rqts:
1621         for (ix--; ix >= 0; ix--)
1622                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1623
1624         return err;
1625 }
1626
1627 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1628 {
1629         struct mlx5_core_dev *mdev = priv->mdev;
1630         void *rqtc;
1631         int inlen;
1632         u32 *in;
1633         int err;
1634
1635         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1636         in = mlx5_vzalloc(inlen);
1637         if (!in)
1638                 return -ENOMEM;
1639
1640         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1641
1642         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1643         if (sz > 1) /* RSS */
1644                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1645         else
1646                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1647
1648         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1649
1650         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1651
1652         kvfree(in);
1653
1654         return err;
1655 }
1656
1657 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1658 {
1659         u32 rqtn;
1660         int ix;
1661
1662         if (priv->indir_rqt.enabled) {
1663                 rqtn = priv->indir_rqt.rqtn;
1664                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1665         }
1666
1667         for (ix = 0; ix < priv->params.num_channels; ix++) {
1668                 if (!priv->direct_tir[ix].rqt.enabled)
1669                         continue;
1670                 rqtn = priv->direct_tir[ix].rqt.rqtn;
1671                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1672         }
1673 }
1674
1675 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1676 {
1677         if (!priv->params.lro_en)
1678                 return;
1679
1680 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1681
1682         MLX5_SET(tirc, tirc, lro_enable_mask,
1683                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1684                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1685         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1686                  (priv->params.lro_wqe_sz -
1687                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1688         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1689                  MLX5_CAP_ETH(priv->mdev,
1690                               lro_timer_supported_periods[2]));
1691 }
1692
1693 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1694 {
1695         MLX5_SET(tirc, tirc, rx_hash_fn,
1696                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1697         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1698                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1699                                              rx_hash_toeplitz_key);
1700                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1701                                                rx_hash_toeplitz_key);
1702
1703                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1704                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1705         }
1706 }
1707
1708 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1709 {
1710         struct mlx5_core_dev *mdev = priv->mdev;
1711
1712         void *in;
1713         void *tirc;
1714         int inlen;
1715         int err;
1716         int tt;
1717         int ix;
1718
1719         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1720         in = mlx5_vzalloc(inlen);
1721         if (!in)
1722                 return -ENOMEM;
1723
1724         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1725         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1726
1727         mlx5e_build_tir_ctx_lro(tirc, priv);
1728
1729         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1730                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1731                                            inlen);
1732                 if (err)
1733                         goto free_in;
1734         }
1735
1736         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1737                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1738                                            in, inlen);
1739                 if (err)
1740                         goto free_in;
1741         }
1742
1743 free_in:
1744         kvfree(in);
1745
1746         return err;
1747 }
1748
1749 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1750 {
1751         struct mlx5_core_dev *mdev = priv->mdev;
1752         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1753         int err;
1754
1755         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1756         if (err)
1757                 return err;
1758
1759         /* Update vport context MTU */
1760         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1761         return 0;
1762 }
1763
1764 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1765 {
1766         struct mlx5_core_dev *mdev = priv->mdev;
1767         u16 hw_mtu = 0;
1768         int err;
1769
1770         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1771         if (err || !hw_mtu) /* fallback to port oper mtu */
1772                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1773
1774         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1775 }
1776
1777 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1778 {
1779         struct mlx5e_priv *priv = netdev_priv(netdev);
1780         u16 mtu;
1781         int err;
1782
1783         err = mlx5e_set_mtu(priv, netdev->mtu);
1784         if (err)
1785                 return err;
1786
1787         mlx5e_query_mtu(priv, &mtu);
1788         if (mtu != netdev->mtu)
1789                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1790                             __func__, mtu, netdev->mtu);
1791
1792         netdev->mtu = mtu;
1793         return 0;
1794 }
1795
1796 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1797 {
1798         struct mlx5e_priv *priv = netdev_priv(netdev);
1799         int nch = priv->params.num_channels;
1800         int ntc = priv->params.num_tc;
1801         int tc;
1802
1803         netdev_reset_tc(netdev);
1804
1805         if (ntc == 1)
1806                 return;
1807
1808         netdev_set_num_tc(netdev, ntc);
1809
1810         /* Map netdev TCs to offset 0
1811          * We have our own UP to TXQ mapping for QoS
1812          */
1813         for (tc = 0; tc < ntc; tc++)
1814                 netdev_set_tc_queue(netdev, tc, nch, 0);
1815 }
1816
1817 int mlx5e_open_locked(struct net_device *netdev)
1818 {
1819         struct mlx5e_priv *priv = netdev_priv(netdev);
1820         struct mlx5_core_dev *mdev = priv->mdev;
1821         int num_txqs;
1822         int err;
1823
1824         set_bit(MLX5E_STATE_OPENED, &priv->state);
1825
1826         mlx5e_netdev_set_tcs(netdev);
1827
1828         num_txqs = priv->params.num_channels * priv->params.num_tc;
1829         netif_set_real_num_tx_queues(netdev, num_txqs);
1830         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1831
1832         err = mlx5e_open_channels(priv);
1833         if (err) {
1834                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1835                            __func__, err);
1836                 goto err_clear_state_opened_flag;
1837         }
1838
1839         err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
1840         if (err) {
1841                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1842                            __func__, err);
1843                 goto err_close_channels;
1844         }
1845
1846         mlx5e_redirect_rqts(priv);
1847         mlx5e_update_carrier(priv);
1848         mlx5e_timestamp_init(priv);
1849 #ifdef CONFIG_RFS_ACCEL
1850         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1851 #endif
1852         if (priv->profile->update_stats)
1853                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1854
1855         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
1856                 err = mlx5e_add_sqs_fwd_rules(priv);
1857                 if (err)
1858                         goto err_close_channels;
1859         }
1860         return 0;
1861
1862 err_close_channels:
1863         mlx5e_close_channels(priv);
1864 err_clear_state_opened_flag:
1865         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1866         return err;
1867 }
1868
1869 int mlx5e_open(struct net_device *netdev)
1870 {
1871         struct mlx5e_priv *priv = netdev_priv(netdev);
1872         int err;
1873
1874         mutex_lock(&priv->state_lock);
1875         err = mlx5e_open_locked(netdev);
1876         mutex_unlock(&priv->state_lock);
1877
1878         return err;
1879 }
1880
1881 int mlx5e_close_locked(struct net_device *netdev)
1882 {
1883         struct mlx5e_priv *priv = netdev_priv(netdev);
1884         struct mlx5_core_dev *mdev = priv->mdev;
1885
1886         /* May already be CLOSED in case a previous configuration operation
1887          * (e.g RX/TX queue size change) that involves close&open failed.
1888          */
1889         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1890                 return 0;
1891
1892         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1893
1894         if (MLX5_CAP_GEN(mdev, vport_group_manager))
1895                 mlx5e_remove_sqs_fwd_rules(priv);
1896
1897         mlx5e_timestamp_cleanup(priv);
1898         netif_carrier_off(priv->netdev);
1899         mlx5e_redirect_rqts(priv);
1900         mlx5e_close_channels(priv);
1901
1902         return 0;
1903 }
1904
1905 int mlx5e_close(struct net_device *netdev)
1906 {
1907         struct mlx5e_priv *priv = netdev_priv(netdev);
1908         int err;
1909
1910         mutex_lock(&priv->state_lock);
1911         err = mlx5e_close_locked(netdev);
1912         mutex_unlock(&priv->state_lock);
1913
1914         return err;
1915 }
1916
1917 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1918                                 struct mlx5e_rq *rq,
1919                                 struct mlx5e_rq_param *param)
1920 {
1921         struct mlx5_core_dev *mdev = priv->mdev;
1922         void *rqc = param->rqc;
1923         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1924         int err;
1925
1926         param->wq.db_numa_node = param->wq.buf_numa_node;
1927
1928         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1929                                 &rq->wq_ctrl);
1930         if (err)
1931                 return err;
1932
1933         rq->priv = priv;
1934
1935         return 0;
1936 }
1937
1938 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1939                                 struct mlx5e_cq *cq,
1940                                 struct mlx5e_cq_param *param)
1941 {
1942         struct mlx5_core_dev *mdev = priv->mdev;
1943         struct mlx5_core_cq *mcq = &cq->mcq;
1944         int eqn_not_used;
1945         unsigned int irqn;
1946         int err;
1947
1948         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1949                                &cq->wq_ctrl);
1950         if (err)
1951                 return err;
1952
1953         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1954
1955         mcq->cqe_sz     = 64;
1956         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1957         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1958         *mcq->set_ci_db = 0;
1959         *mcq->arm_db    = 0;
1960         mcq->vector     = param->eq_ix;
1961         mcq->comp       = mlx5e_completion_event;
1962         mcq->event      = mlx5e_cq_error_event;
1963         mcq->irqn       = irqn;
1964         mcq->uar        = &mdev->mlx5e_res.cq_uar;
1965
1966         cq->priv = priv;
1967
1968         return 0;
1969 }
1970
1971 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1972 {
1973         struct mlx5e_cq_param cq_param;
1974         struct mlx5e_rq_param rq_param;
1975         struct mlx5e_rq *rq = &priv->drop_rq;
1976         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1977         int err;
1978
1979         memset(&cq_param, 0, sizeof(cq_param));
1980         memset(&rq_param, 0, sizeof(rq_param));
1981         mlx5e_build_drop_rq_param(&rq_param);
1982
1983         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1984         if (err)
1985                 return err;
1986
1987         err = mlx5e_enable_cq(cq, &cq_param);
1988         if (err)
1989                 goto err_destroy_cq;
1990
1991         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1992         if (err)
1993                 goto err_disable_cq;
1994
1995         err = mlx5e_enable_rq(rq, &rq_param);
1996         if (err)
1997                 goto err_destroy_rq;
1998
1999         return 0;
2000
2001 err_destroy_rq:
2002         mlx5e_destroy_rq(&priv->drop_rq);
2003
2004 err_disable_cq:
2005         mlx5e_disable_cq(&priv->drop_rq.cq);
2006
2007 err_destroy_cq:
2008         mlx5e_destroy_cq(&priv->drop_rq.cq);
2009
2010         return err;
2011 }
2012
2013 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2014 {
2015         mlx5e_disable_rq(&priv->drop_rq);
2016         mlx5e_destroy_rq(&priv->drop_rq);
2017         mlx5e_disable_cq(&priv->drop_rq.cq);
2018         mlx5e_destroy_cq(&priv->drop_rq.cq);
2019 }
2020
2021 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2022 {
2023         struct mlx5_core_dev *mdev = priv->mdev;
2024         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2025         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2026
2027         memset(in, 0, sizeof(in));
2028
2029         MLX5_SET(tisc, tisc, prio, tc << 1);
2030         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2031
2032         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2033 }
2034
2035 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2036 {
2037         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2038 }
2039
2040 int mlx5e_create_tises(struct mlx5e_priv *priv)
2041 {
2042         int err;
2043         int tc;
2044
2045         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2046                 err = mlx5e_create_tis(priv, tc);
2047                 if (err)
2048                         goto err_close_tises;
2049         }
2050
2051         return 0;
2052
2053 err_close_tises:
2054         for (tc--; tc >= 0; tc--)
2055                 mlx5e_destroy_tis(priv, tc);
2056
2057         return err;
2058 }
2059
2060 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2061 {
2062         int tc;
2063
2064         for (tc = 0; tc < priv->profile->max_tc; tc++)
2065                 mlx5e_destroy_tis(priv, tc);
2066 }
2067
2068 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2069                                       enum mlx5e_traffic_types tt)
2070 {
2071         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2072
2073         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2074
2075 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2076                                  MLX5_HASH_FIELD_SEL_DST_IP)
2077
2078 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2079                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2080                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2081                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2082
2083 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2084                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2085                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2086
2087         mlx5e_build_tir_ctx_lro(tirc, priv);
2088
2089         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2090         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2091         mlx5e_build_tir_ctx_hash(tirc, priv);
2092
2093         switch (tt) {
2094         case MLX5E_TT_IPV4_TCP:
2095                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2096                          MLX5_L3_PROT_TYPE_IPV4);
2097                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2098                          MLX5_L4_PROT_TYPE_TCP);
2099                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2100                          MLX5_HASH_IP_L4PORTS);
2101                 break;
2102
2103         case MLX5E_TT_IPV6_TCP:
2104                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2105                          MLX5_L3_PROT_TYPE_IPV6);
2106                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2107                          MLX5_L4_PROT_TYPE_TCP);
2108                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2109                          MLX5_HASH_IP_L4PORTS);
2110                 break;
2111
2112         case MLX5E_TT_IPV4_UDP:
2113                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2114                          MLX5_L3_PROT_TYPE_IPV4);
2115                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2116                          MLX5_L4_PROT_TYPE_UDP);
2117                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2118                          MLX5_HASH_IP_L4PORTS);
2119                 break;
2120
2121         case MLX5E_TT_IPV6_UDP:
2122                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2123                          MLX5_L3_PROT_TYPE_IPV6);
2124                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2125                          MLX5_L4_PROT_TYPE_UDP);
2126                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2127                          MLX5_HASH_IP_L4PORTS);
2128                 break;
2129
2130         case MLX5E_TT_IPV4_IPSEC_AH:
2131                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2132                          MLX5_L3_PROT_TYPE_IPV4);
2133                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2134                          MLX5_HASH_IP_IPSEC_SPI);
2135                 break;
2136
2137         case MLX5E_TT_IPV6_IPSEC_AH:
2138                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2139                          MLX5_L3_PROT_TYPE_IPV6);
2140                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2141                          MLX5_HASH_IP_IPSEC_SPI);
2142                 break;
2143
2144         case MLX5E_TT_IPV4_IPSEC_ESP:
2145                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2146                          MLX5_L3_PROT_TYPE_IPV4);
2147                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2148                          MLX5_HASH_IP_IPSEC_SPI);
2149                 break;
2150
2151         case MLX5E_TT_IPV6_IPSEC_ESP:
2152                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2153                          MLX5_L3_PROT_TYPE_IPV6);
2154                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2155                          MLX5_HASH_IP_IPSEC_SPI);
2156                 break;
2157
2158         case MLX5E_TT_IPV4:
2159                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2160                          MLX5_L3_PROT_TYPE_IPV4);
2161                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2162                          MLX5_HASH_IP);
2163                 break;
2164
2165         case MLX5E_TT_IPV6:
2166                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2167                          MLX5_L3_PROT_TYPE_IPV6);
2168                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2169                          MLX5_HASH_IP);
2170                 break;
2171         default:
2172                 WARN_ONCE(true,
2173                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2174         }
2175 }
2176
2177 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2178                                        u32 rqtn)
2179 {
2180         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2181
2182         mlx5e_build_tir_ctx_lro(tirc, priv);
2183
2184         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2185         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2186         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2187 }
2188
2189 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2190 {
2191         struct mlx5e_tir *tir;
2192         void *tirc;
2193         int inlen;
2194         int err;
2195         u32 *in;
2196         int tt;
2197
2198         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2199         in = mlx5_vzalloc(inlen);
2200         if (!in)
2201                 return -ENOMEM;
2202
2203         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2204                 memset(in, 0, inlen);
2205                 tir = &priv->indir_tir[tt];
2206                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2207                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2208                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2209                 if (err)
2210                         goto err_destroy_tirs;
2211         }
2212
2213         kvfree(in);
2214
2215         return 0;
2216
2217 err_destroy_tirs:
2218         for (tt--; tt >= 0; tt--)
2219                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2220
2221         kvfree(in);
2222
2223         return err;
2224 }
2225
2226 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2227 {
2228         int nch = priv->profile->max_nch(priv->mdev);
2229         struct mlx5e_tir *tir;
2230         void *tirc;
2231         int inlen;
2232         int err;
2233         u32 *in;
2234         int ix;
2235
2236         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2237         in = mlx5_vzalloc(inlen);
2238         if (!in)
2239                 return -ENOMEM;
2240
2241         for (ix = 0; ix < nch; ix++) {
2242                 memset(in, 0, inlen);
2243                 tir = &priv->direct_tir[ix];
2244                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2245                 mlx5e_build_direct_tir_ctx(priv, tirc,
2246                                            priv->direct_tir[ix].rqt.rqtn);
2247                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2248                 if (err)
2249                         goto err_destroy_ch_tirs;
2250         }
2251
2252         kvfree(in);
2253
2254         return 0;
2255
2256 err_destroy_ch_tirs:
2257         for (ix--; ix >= 0; ix--)
2258                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2259
2260         kvfree(in);
2261
2262         return err;
2263 }
2264
2265 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2266 {
2267         int i;
2268
2269         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2270                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2271 }
2272
2273 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2274 {
2275         int nch = priv->profile->max_nch(priv->mdev);
2276         int i;
2277
2278         for (i = 0; i < nch; i++)
2279                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2280 }
2281
2282 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2283 {
2284         int err = 0;
2285         int i;
2286
2287         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2288                 return 0;
2289
2290         for (i = 0; i < priv->params.num_channels; i++) {
2291                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2292                 if (err)
2293                         return err;
2294         }
2295
2296         return 0;
2297 }
2298
2299 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2300 {
2301         struct mlx5e_priv *priv = netdev_priv(netdev);
2302         bool was_opened;
2303         int err = 0;
2304
2305         if (tc && tc != MLX5E_MAX_NUM_TC)
2306                 return -EINVAL;
2307
2308         mutex_lock(&priv->state_lock);
2309
2310         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2311         if (was_opened)
2312                 mlx5e_close_locked(priv->netdev);
2313
2314         priv->params.num_tc = tc ? tc : 1;
2315
2316         if (was_opened)
2317                 err = mlx5e_open_locked(priv->netdev);
2318
2319         mutex_unlock(&priv->state_lock);
2320
2321         return err;
2322 }
2323
2324 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2325                               __be16 proto, struct tc_to_netdev *tc)
2326 {
2327         struct mlx5e_priv *priv = netdev_priv(dev);
2328
2329         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2330                 goto mqprio;
2331
2332         switch (tc->type) {
2333         case TC_SETUP_CLSFLOWER:
2334                 switch (tc->cls_flower->command) {
2335                 case TC_CLSFLOWER_REPLACE:
2336                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2337                 case TC_CLSFLOWER_DESTROY:
2338                         return mlx5e_delete_flower(priv, tc->cls_flower);
2339                 case TC_CLSFLOWER_STATS:
2340                         return mlx5e_stats_flower(priv, tc->cls_flower);
2341                 }
2342         default:
2343                 return -EOPNOTSUPP;
2344         }
2345
2346 mqprio:
2347         if (tc->type != TC_SETUP_MQPRIO)
2348                 return -EINVAL;
2349
2350         return mlx5e_setup_tc(dev, tc->tc);
2351 }
2352
2353 struct rtnl_link_stats64 *
2354 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2355 {
2356         struct mlx5e_priv *priv = netdev_priv(dev);
2357         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2358         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2359         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2360
2361         stats->rx_packets = sstats->rx_packets;
2362         stats->rx_bytes   = sstats->rx_bytes;
2363         stats->tx_packets = sstats->tx_packets;
2364         stats->tx_bytes   = sstats->tx_bytes;
2365
2366         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2367         stats->tx_dropped = sstats->tx_queue_dropped;
2368
2369         stats->rx_length_errors =
2370                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2371                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2372                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2373         stats->rx_crc_errors =
2374                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2375         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2376         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2377         stats->tx_carrier_errors =
2378                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2379         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2380                            stats->rx_frame_errors;
2381         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2382
2383         /* vport multicast also counts packets that are dropped due to steering
2384          * or rx out of buffer
2385          */
2386         stats->multicast =
2387                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2388
2389         return stats;
2390 }
2391
2392 static void mlx5e_set_rx_mode(struct net_device *dev)
2393 {
2394         struct mlx5e_priv *priv = netdev_priv(dev);
2395
2396         queue_work(priv->wq, &priv->set_rx_mode_work);
2397 }
2398
2399 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2400 {
2401         struct mlx5e_priv *priv = netdev_priv(netdev);
2402         struct sockaddr *saddr = addr;
2403
2404         if (!is_valid_ether_addr(saddr->sa_data))
2405                 return -EADDRNOTAVAIL;
2406
2407         netif_addr_lock_bh(netdev);
2408         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2409         netif_addr_unlock_bh(netdev);
2410
2411         queue_work(priv->wq, &priv->set_rx_mode_work);
2412
2413         return 0;
2414 }
2415
2416 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2417         do {                                            \
2418                 if (enable)                             \
2419                         netdev->features |= feature;    \
2420                 else                                    \
2421                         netdev->features &= ~feature;   \
2422         } while (0)
2423
2424 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2425
2426 static int set_feature_lro(struct net_device *netdev, bool enable)
2427 {
2428         struct mlx5e_priv *priv = netdev_priv(netdev);
2429         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2430         int err;
2431
2432         mutex_lock(&priv->state_lock);
2433
2434         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2435                 mlx5e_close_locked(priv->netdev);
2436
2437         priv->params.lro_en = enable;
2438         err = mlx5e_modify_tirs_lro(priv);
2439         if (err) {
2440                 netdev_err(netdev, "lro modify failed, %d\n", err);
2441                 priv->params.lro_en = !enable;
2442         }
2443
2444         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2445                 mlx5e_open_locked(priv->netdev);
2446
2447         mutex_unlock(&priv->state_lock);
2448
2449         return err;
2450 }
2451
2452 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2453 {
2454         struct mlx5e_priv *priv = netdev_priv(netdev);
2455
2456         if (enable)
2457                 mlx5e_enable_vlan_filter(priv);
2458         else
2459                 mlx5e_disable_vlan_filter(priv);
2460
2461         return 0;
2462 }
2463
2464 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2465 {
2466         struct mlx5e_priv *priv = netdev_priv(netdev);
2467
2468         if (!enable && mlx5e_tc_num_filters(priv)) {
2469                 netdev_err(netdev,
2470                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2471                 return -EINVAL;
2472         }
2473
2474         return 0;
2475 }
2476
2477 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2478 {
2479         struct mlx5e_priv *priv = netdev_priv(netdev);
2480         struct mlx5_core_dev *mdev = priv->mdev;
2481
2482         return mlx5_set_port_fcs(mdev, !enable);
2483 }
2484
2485 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2486 {
2487         struct mlx5e_priv *priv = netdev_priv(netdev);
2488         int err;
2489
2490         mutex_lock(&priv->state_lock);
2491
2492         priv->params.vlan_strip_disable = !enable;
2493         err = mlx5e_modify_rqs_vsd(priv, !enable);
2494         if (err)
2495                 priv->params.vlan_strip_disable = enable;
2496
2497         mutex_unlock(&priv->state_lock);
2498
2499         return err;
2500 }
2501
2502 #ifdef CONFIG_RFS_ACCEL
2503 static int set_feature_arfs(struct net_device *netdev, bool enable)
2504 {
2505         struct mlx5e_priv *priv = netdev_priv(netdev);
2506         int err;
2507
2508         if (enable)
2509                 err = mlx5e_arfs_enable(priv);
2510         else
2511                 err = mlx5e_arfs_disable(priv);
2512
2513         return err;
2514 }
2515 #endif
2516
2517 static int mlx5e_handle_feature(struct net_device *netdev,
2518                                 netdev_features_t wanted_features,
2519                                 netdev_features_t feature,
2520                                 mlx5e_feature_handler feature_handler)
2521 {
2522         netdev_features_t changes = wanted_features ^ netdev->features;
2523         bool enable = !!(wanted_features & feature);
2524         int err;
2525
2526         if (!(changes & feature))
2527                 return 0;
2528
2529         err = feature_handler(netdev, enable);
2530         if (err) {
2531                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2532                            enable ? "Enable" : "Disable", feature, err);
2533                 return err;
2534         }
2535
2536         MLX5E_SET_FEATURE(netdev, feature, enable);
2537         return 0;
2538 }
2539
2540 static int mlx5e_set_features(struct net_device *netdev,
2541                               netdev_features_t features)
2542 {
2543         int err;
2544
2545         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2546                                     set_feature_lro);
2547         err |= mlx5e_handle_feature(netdev, features,
2548                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2549                                     set_feature_vlan_filter);
2550         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2551                                     set_feature_tc_num_filters);
2552         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2553                                     set_feature_rx_all);
2554         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2555                                     set_feature_rx_vlan);
2556 #ifdef CONFIG_RFS_ACCEL
2557         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2558                                     set_feature_arfs);
2559 #endif
2560
2561         return err ? -EINVAL : 0;
2562 }
2563
2564 #define MXL5_HW_MIN_MTU 64
2565 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2566
2567 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2568 {
2569         struct mlx5e_priv *priv = netdev_priv(netdev);
2570         struct mlx5_core_dev *mdev = priv->mdev;
2571         bool was_opened;
2572         u16 max_mtu;
2573         u16 min_mtu;
2574         int err = 0;
2575         bool reset;
2576
2577         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2578
2579         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2580         min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2581
2582         if (new_mtu > max_mtu || new_mtu < min_mtu) {
2583                 netdev_err(netdev,
2584                            "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2585                            __func__, new_mtu, min_mtu, max_mtu);
2586                 return -EINVAL;
2587         }
2588
2589         mutex_lock(&priv->state_lock);
2590
2591         reset = !priv->params.lro_en &&
2592                 (priv->params.rq_wq_type !=
2593                  MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2594
2595         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2596         if (was_opened && reset)
2597                 mlx5e_close_locked(netdev);
2598
2599         netdev->mtu = new_mtu;
2600         mlx5e_set_dev_port_mtu(netdev);
2601
2602         if (was_opened && reset)
2603                 err = mlx5e_open_locked(netdev);
2604
2605         mutex_unlock(&priv->state_lock);
2606
2607         return err;
2608 }
2609
2610 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2611 {
2612         switch (cmd) {
2613         case SIOCSHWTSTAMP:
2614                 return mlx5e_hwstamp_set(dev, ifr);
2615         case SIOCGHWTSTAMP:
2616                 return mlx5e_hwstamp_get(dev, ifr);
2617         default:
2618                 return -EOPNOTSUPP;
2619         }
2620 }
2621
2622 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2623 {
2624         struct mlx5e_priv *priv = netdev_priv(dev);
2625         struct mlx5_core_dev *mdev = priv->mdev;
2626
2627         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2628 }
2629
2630 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2631 {
2632         struct mlx5e_priv *priv = netdev_priv(dev);
2633         struct mlx5_core_dev *mdev = priv->mdev;
2634
2635         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2636                                            vlan, qos);
2637 }
2638
2639 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2640 {
2641         struct mlx5e_priv *priv = netdev_priv(dev);
2642         struct mlx5_core_dev *mdev = priv->mdev;
2643
2644         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2645 }
2646
2647 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2648 {
2649         struct mlx5e_priv *priv = netdev_priv(dev);
2650         struct mlx5_core_dev *mdev = priv->mdev;
2651
2652         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2653 }
2654 static int mlx5_vport_link2ifla(u8 esw_link)
2655 {
2656         switch (esw_link) {
2657         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2658                 return IFLA_VF_LINK_STATE_DISABLE;
2659         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2660                 return IFLA_VF_LINK_STATE_ENABLE;
2661         }
2662         return IFLA_VF_LINK_STATE_AUTO;
2663 }
2664
2665 static int mlx5_ifla_link2vport(u8 ifla_link)
2666 {
2667         switch (ifla_link) {
2668         case IFLA_VF_LINK_STATE_DISABLE:
2669                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2670         case IFLA_VF_LINK_STATE_ENABLE:
2671                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2672         }
2673         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2674 }
2675
2676 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2677                                    int link_state)
2678 {
2679         struct mlx5e_priv *priv = netdev_priv(dev);
2680         struct mlx5_core_dev *mdev = priv->mdev;
2681
2682         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2683                                             mlx5_ifla_link2vport(link_state));
2684 }
2685
2686 static int mlx5e_get_vf_config(struct net_device *dev,
2687                                int vf, struct ifla_vf_info *ivi)
2688 {
2689         struct mlx5e_priv *priv = netdev_priv(dev);
2690         struct mlx5_core_dev *mdev = priv->mdev;
2691         int err;
2692
2693         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2694         if (err)
2695                 return err;
2696         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2697         return 0;
2698 }
2699
2700 static int mlx5e_get_vf_stats(struct net_device *dev,
2701                               int vf, struct ifla_vf_stats *vf_stats)
2702 {
2703         struct mlx5e_priv *priv = netdev_priv(dev);
2704         struct mlx5_core_dev *mdev = priv->mdev;
2705
2706         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2707                                             vf_stats);
2708 }
2709
2710 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2711                                  struct udp_tunnel_info *ti)
2712 {
2713         struct mlx5e_priv *priv = netdev_priv(netdev);
2714
2715         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2716                 return;
2717
2718         if (!mlx5e_vxlan_allowed(priv->mdev))
2719                 return;
2720
2721         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
2722 }
2723
2724 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2725                                  struct udp_tunnel_info *ti)
2726 {
2727         struct mlx5e_priv *priv = netdev_priv(netdev);
2728
2729         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2730                 return;
2731
2732         if (!mlx5e_vxlan_allowed(priv->mdev))
2733                 return;
2734
2735         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
2736 }
2737
2738 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2739                                                     struct sk_buff *skb,
2740                                                     netdev_features_t features)
2741 {
2742         struct udphdr *udph;
2743         u16 proto;
2744         u16 port = 0;
2745
2746         switch (vlan_get_protocol(skb)) {
2747         case htons(ETH_P_IP):
2748                 proto = ip_hdr(skb)->protocol;
2749                 break;
2750         case htons(ETH_P_IPV6):
2751                 proto = ipv6_hdr(skb)->nexthdr;
2752                 break;
2753         default:
2754                 goto out;
2755         }
2756
2757         if (proto == IPPROTO_UDP) {
2758                 udph = udp_hdr(skb);
2759                 port = be16_to_cpu(udph->dest);
2760         }
2761
2762         /* Verify if UDP port is being offloaded by HW */
2763         if (port && mlx5e_vxlan_lookup_port(priv, port))
2764                 return features;
2765
2766 out:
2767         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2768         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2769 }
2770
2771 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2772                                               struct net_device *netdev,
2773                                               netdev_features_t features)
2774 {
2775         struct mlx5e_priv *priv = netdev_priv(netdev);
2776
2777         features = vlan_features_check(skb, features);
2778         features = vxlan_features_check(skb, features);
2779
2780         /* Validate if the tunneled packet is being offloaded by HW */
2781         if (skb->encapsulation &&
2782             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2783                 return mlx5e_vxlan_features_check(priv, skb, features);
2784
2785         return features;
2786 }
2787
2788 static void mlx5e_tx_timeout(struct net_device *dev)
2789 {
2790         struct mlx5e_priv *priv = netdev_priv(dev);
2791         bool sched_work = false;
2792         int i;
2793
2794         netdev_err(dev, "TX timeout detected\n");
2795
2796         for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
2797                 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
2798
2799                 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
2800                         continue;
2801                 sched_work = true;
2802                 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
2803                 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
2804                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
2805         }
2806
2807         if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
2808                 schedule_work(&priv->tx_timeout_work);
2809 }
2810
2811 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2812         .ndo_open                = mlx5e_open,
2813         .ndo_stop                = mlx5e_close,
2814         .ndo_start_xmit          = mlx5e_xmit,
2815         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2816         .ndo_select_queue        = mlx5e_select_queue,
2817         .ndo_get_stats64         = mlx5e_get_stats,
2818         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2819         .ndo_set_mac_address     = mlx5e_set_mac,
2820         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2821         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2822         .ndo_set_features        = mlx5e_set_features,
2823         .ndo_change_mtu          = mlx5e_change_mtu,
2824         .ndo_do_ioctl            = mlx5e_ioctl,
2825         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
2826 #ifdef CONFIG_RFS_ACCEL
2827         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2828 #endif
2829         .ndo_tx_timeout          = mlx5e_tx_timeout,
2830 };
2831
2832 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2833         .ndo_open                = mlx5e_open,
2834         .ndo_stop                = mlx5e_close,
2835         .ndo_start_xmit          = mlx5e_xmit,
2836         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2837         .ndo_select_queue        = mlx5e_select_queue,
2838         .ndo_get_stats64         = mlx5e_get_stats,
2839         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2840         .ndo_set_mac_address     = mlx5e_set_mac,
2841         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2842         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2843         .ndo_set_features        = mlx5e_set_features,
2844         .ndo_change_mtu          = mlx5e_change_mtu,
2845         .ndo_do_ioctl            = mlx5e_ioctl,
2846         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
2847         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
2848         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
2849         .ndo_features_check      = mlx5e_features_check,
2850 #ifdef CONFIG_RFS_ACCEL
2851         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2852 #endif
2853         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2854         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2855         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
2856         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
2857         .ndo_get_vf_config       = mlx5e_get_vf_config,
2858         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2859         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2860         .ndo_tx_timeout          = mlx5e_tx_timeout,
2861 };
2862
2863 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2864 {
2865         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2866                 return -ENOTSUPP;
2867         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2868             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2869             !MLX5_CAP_ETH(mdev, csum_cap) ||
2870             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2871             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2872             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2873             MLX5_CAP_FLOWTABLE(mdev,
2874                                flow_table_properties_nic_receive.max_ft_level)
2875                                < 3) {
2876                 mlx5_core_warn(mdev,
2877                                "Not creating net device, some required device capabilities are missing\n");
2878                 return -ENOTSUPP;
2879         }
2880         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2881                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2882         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2883                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2884
2885         return 0;
2886 }
2887
2888 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2889 {
2890         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2891
2892         return bf_buf_size -
2893                sizeof(struct mlx5e_tx_wqe) +
2894                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2895 }
2896
2897 #ifdef CONFIG_MLX5_CORE_EN_DCB
2898 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2899 {
2900         int i;
2901
2902         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2903         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2904                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2905                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2906                 priv->params.ets.prio_tc[i] = i;
2907         }
2908
2909         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2910         priv->params.ets.prio_tc[0] = 1;
2911         priv->params.ets.prio_tc[1] = 0;
2912 }
2913 #endif
2914
2915 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2916                                    u32 *indirection_rqt, int len,
2917                                    int num_channels)
2918 {
2919         int node = mdev->priv.numa_node;
2920         int node_num_of_cores;
2921         int i;
2922
2923         if (node == -1)
2924                 node = first_online_node;
2925
2926         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2927
2928         if (node_num_of_cores)
2929                 num_channels = min_t(int, num_channels, node_num_of_cores);
2930
2931         for (i = 0; i < len; i++)
2932                 indirection_rqt[i] = i % num_channels;
2933 }
2934
2935 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2936 {
2937         return MLX5_CAP_GEN(mdev, striding_rq) &&
2938                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2939                 MLX5_CAP_ETH(mdev, reg_umr_sq);
2940 }
2941
2942 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2943 {
2944         enum pcie_link_width width;
2945         enum pci_bus_speed speed;
2946         int err = 0;
2947
2948         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2949         if (err)
2950                 return err;
2951
2952         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2953                 return -EINVAL;
2954
2955         switch (speed) {
2956         case PCIE_SPEED_2_5GT:
2957                 *pci_bw = 2500 * width;
2958                 break;
2959         case PCIE_SPEED_5_0GT:
2960                 *pci_bw = 5000 * width;
2961                 break;
2962         case PCIE_SPEED_8_0GT:
2963                 *pci_bw = 8000 * width;
2964                 break;
2965         default:
2966                 return -EINVAL;
2967         }
2968
2969         return 0;
2970 }
2971
2972 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2973 {
2974         return (link_speed && pci_bw &&
2975                 (pci_bw < 40000) && (pci_bw < link_speed));
2976 }
2977
2978 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
2979 {
2980         params->rx_cq_period_mode = cq_period_mode;
2981
2982         params->rx_cq_moderation.pkts =
2983                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2984         params->rx_cq_moderation.usec =
2985                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2986
2987         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
2988                 params->rx_cq_moderation.usec =
2989                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
2990 }
2991
2992 static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
2993                                    u8 *min_inline_mode)
2994 {
2995         switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
2996         case MLX5E_INLINE_MODE_L2:
2997                 *min_inline_mode = MLX5_INLINE_MODE_L2;
2998                 break;
2999         case MLX5E_INLINE_MODE_VPORT_CONTEXT:
3000                 mlx5_query_nic_vport_min_inline(mdev,
3001                                                 min_inline_mode);
3002                 break;
3003         case MLX5_INLINE_MODE_NOT_REQUIRED:
3004                 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3005                 break;
3006         }
3007 }
3008
3009 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3010                                         struct net_device *netdev,
3011                                         const struct mlx5e_profile *profile,
3012                                         void *ppriv)
3013 {
3014         struct mlx5e_priv *priv = netdev_priv(netdev);
3015         u32 link_speed = 0;
3016         u32 pci_bw = 0;
3017         u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3018                                          MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3019                                          MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3020
3021         priv->params.log_sq_size           =
3022                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3023         priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
3024                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
3025                 MLX5_WQ_TYPE_LINKED_LIST;
3026
3027         /* set CQE compression */
3028         priv->params.rx_cqe_compress_admin = false;
3029         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3030             MLX5_CAP_GEN(mdev, vport_group_manager)) {
3031                 mlx5e_get_max_linkspeed(mdev, &link_speed);
3032                 mlx5e_get_pci_bw(mdev, &pci_bw);
3033                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3034                               link_speed, pci_bw);
3035                 priv->params.rx_cqe_compress_admin =
3036                         cqe_compress_heuristic(link_speed, pci_bw);
3037         }
3038
3039         priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3040
3041         switch (priv->params.rq_wq_type) {
3042         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
3043                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
3044                 priv->params.mpwqe_log_stride_sz =
3045                         priv->params.rx_cqe_compress ?
3046                         MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
3047                         MLX5_MPWRQ_LOG_STRIDE_SIZE;
3048                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
3049                         priv->params.mpwqe_log_stride_sz;
3050                 priv->params.lro_en = true;
3051                 break;
3052         default: /* MLX5_WQ_TYPE_LINKED_LIST */
3053                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3054         }
3055
3056         mlx5_core_info(mdev,
3057                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
3058                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
3059                        BIT(priv->params.log_rq_size),
3060                        BIT(priv->params.mpwqe_log_stride_sz),
3061                        priv->params.rx_cqe_compress_admin);
3062
3063         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
3064                                             BIT(priv->params.log_rq_size));
3065
3066         priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3067         mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3068
3069         priv->params.tx_cq_moderation.usec =
3070                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3071         priv->params.tx_cq_moderation.pkts =
3072                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3073         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
3074         mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3075         priv->params.num_tc                = 1;
3076         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
3077
3078         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3079                             sizeof(priv->params.toeplitz_hash_key));
3080
3081         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3082                                       MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3083
3084         priv->params.lro_wqe_sz            =
3085                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3086
3087         /* Initialize pflags */
3088         MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3089                             priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3090
3091         priv->mdev                         = mdev;
3092         priv->netdev                       = netdev;
3093         priv->params.num_channels          = profile->max_nch(mdev);
3094         priv->profile                      = profile;
3095         priv->ppriv                        = ppriv;
3096
3097 #ifdef CONFIG_MLX5_CORE_EN_DCB
3098         mlx5e_ets_init(priv);
3099 #endif
3100
3101         mutex_init(&priv->state_lock);
3102
3103         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3104         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3105         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3106         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3107 }
3108
3109 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3110 {
3111         struct mlx5e_priv *priv = netdev_priv(netdev);
3112
3113         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3114         if (is_zero_ether_addr(netdev->dev_addr) &&
3115             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3116                 eth_hw_addr_random(netdev);
3117                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3118         }
3119 }
3120
3121 static const struct switchdev_ops mlx5e_switchdev_ops = {
3122         .switchdev_port_attr_get        = mlx5e_attr_get,
3123 };
3124
3125 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3126 {
3127         struct mlx5e_priv *priv = netdev_priv(netdev);
3128         struct mlx5_core_dev *mdev = priv->mdev;
3129         bool fcs_supported;
3130         bool fcs_enabled;
3131
3132         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3133
3134         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3135                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3136 #ifdef CONFIG_MLX5_CORE_EN_DCB
3137                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3138 #endif
3139         } else {
3140                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3141         }
3142
3143         netdev->watchdog_timeo    = 15 * HZ;
3144
3145         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
3146
3147         netdev->vlan_features    |= NETIF_F_SG;
3148         netdev->vlan_features    |= NETIF_F_IP_CSUM;
3149         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
3150         netdev->vlan_features    |= NETIF_F_GRO;
3151         netdev->vlan_features    |= NETIF_F_TSO;
3152         netdev->vlan_features    |= NETIF_F_TSO6;
3153         netdev->vlan_features    |= NETIF_F_RXCSUM;
3154         netdev->vlan_features    |= NETIF_F_RXHASH;
3155
3156         if (!!MLX5_CAP_ETH(mdev, lro_cap))
3157                 netdev->vlan_features    |= NETIF_F_LRO;
3158
3159         netdev->hw_features       = netdev->vlan_features;
3160         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
3161         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
3162         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
3163
3164         if (mlx5e_vxlan_allowed(mdev)) {
3165                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
3166                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
3167                                            NETIF_F_GSO_PARTIAL;
3168                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3169                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3170                 netdev->hw_enc_features |= NETIF_F_TSO;
3171                 netdev->hw_enc_features |= NETIF_F_TSO6;
3172                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3173                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3174                                            NETIF_F_GSO_PARTIAL;
3175                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3176         }
3177
3178         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3179
3180         if (fcs_supported)
3181                 netdev->hw_features |= NETIF_F_RXALL;
3182
3183         netdev->features          = netdev->hw_features;
3184         if (!priv->params.lro_en)
3185                 netdev->features  &= ~NETIF_F_LRO;
3186
3187         if (fcs_enabled)
3188                 netdev->features  &= ~NETIF_F_RXALL;
3189
3190 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3191         if (FT_CAP(flow_modify_en) &&
3192             FT_CAP(modify_root) &&
3193             FT_CAP(identified_miss_table_mode) &&
3194             FT_CAP(flow_table_modify)) {
3195                 netdev->hw_features      |= NETIF_F_HW_TC;
3196 #ifdef CONFIG_RFS_ACCEL
3197                 netdev->hw_features      |= NETIF_F_NTUPLE;
3198 #endif
3199         }
3200
3201         netdev->features         |= NETIF_F_HIGHDMA;
3202
3203         netdev->priv_flags       |= IFF_UNICAST_FLT;
3204
3205         mlx5e_set_netdev_dev_addr(netdev);
3206
3207 #ifdef CONFIG_NET_SWITCHDEV
3208         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3209                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3210 #endif
3211 }
3212
3213 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3214 {
3215         struct mlx5_core_dev *mdev = priv->mdev;
3216         int err;
3217
3218         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3219         if (err) {
3220                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3221                 priv->q_counter = 0;
3222         }
3223 }
3224
3225 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3226 {
3227         if (!priv->q_counter)
3228                 return;
3229
3230         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3231 }
3232
3233 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3234 {
3235         struct mlx5_core_dev *mdev = priv->mdev;
3236         struct mlx5_create_mkey_mbox_in *in;
3237         struct mlx5_mkey_seg *mkc;
3238         int inlen = sizeof(*in);
3239         u64 npages = MLX5E_REQUIRED_MTTS(priv->profile->max_nch(mdev),
3240                                          BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW));
3241         int err;
3242
3243         in = mlx5_vzalloc(inlen);
3244         if (!in)
3245                 return -ENOMEM;
3246
3247         mkc = &in->seg;
3248         mkc->status = MLX5_MKEY_STATUS_FREE;
3249         mkc->flags = MLX5_PERM_UMR_EN |
3250                      MLX5_PERM_LOCAL_READ |
3251                      MLX5_PERM_LOCAL_WRITE |
3252                      MLX5_ACCESS_MODE_MTT;
3253
3254         npages = min_t(u32, ALIGN(U16_MAX, 4) * 2, npages);
3255
3256         mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3257         mkc->flags_pd = cpu_to_be32(mdev->mlx5e_res.pdn);
3258         mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
3259         mkc->xlt_oct_size = cpu_to_be32(MLX5_MTT_OCTW(npages));
3260         mkc->log2_page_size = PAGE_SHIFT;
3261
3262         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
3263                                     NULL, NULL);
3264
3265         kvfree(in);
3266
3267         return err;
3268 }
3269
3270 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3271                            struct net_device *netdev,
3272                            const struct mlx5e_profile *profile,
3273                            void *ppriv)
3274 {
3275         struct mlx5e_priv *priv = netdev_priv(netdev);
3276
3277         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3278         mlx5e_build_nic_netdev(netdev);
3279         mlx5e_vxlan_init(priv);
3280 }
3281
3282 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3283 {
3284         struct mlx5_core_dev *mdev = priv->mdev;
3285         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3286
3287         mlx5e_vxlan_cleanup(priv);
3288
3289         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3290                 mlx5_eswitch_unregister_vport_rep(esw, 0);
3291 }
3292
3293 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3294 {
3295         struct mlx5_core_dev *mdev = priv->mdev;
3296         int err;
3297         int i;
3298
3299         err = mlx5e_create_indirect_rqts(priv);
3300         if (err) {
3301                 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3302                 return err;
3303         }
3304
3305         err = mlx5e_create_direct_rqts(priv);
3306         if (err) {
3307                 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3308                 goto err_destroy_indirect_rqts;
3309         }
3310
3311         err = mlx5e_create_indirect_tirs(priv);
3312         if (err) {
3313                 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3314                 goto err_destroy_direct_rqts;
3315         }
3316
3317         err = mlx5e_create_direct_tirs(priv);
3318         if (err) {
3319                 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3320                 goto err_destroy_indirect_tirs;
3321         }
3322
3323         err = mlx5e_create_flow_steering(priv);
3324         if (err) {
3325                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3326                 goto err_destroy_direct_tirs;
3327         }
3328
3329         err = mlx5e_tc_init(priv);
3330         if (err)
3331                 goto err_destroy_flow_steering;
3332
3333         return 0;
3334
3335 err_destroy_flow_steering:
3336         mlx5e_destroy_flow_steering(priv);
3337 err_destroy_direct_tirs:
3338         mlx5e_destroy_direct_tirs(priv);
3339 err_destroy_indirect_tirs:
3340         mlx5e_destroy_indirect_tirs(priv);
3341 err_destroy_direct_rqts:
3342         for (i = 0; i < priv->profile->max_nch(mdev); i++)
3343                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3344 err_destroy_indirect_rqts:
3345         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3346         return err;
3347 }
3348
3349 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3350 {
3351         int i;
3352
3353         mlx5e_tc_cleanup(priv);
3354         mlx5e_destroy_flow_steering(priv);
3355         mlx5e_destroy_direct_tirs(priv);
3356         mlx5e_destroy_indirect_tirs(priv);
3357         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3358                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3359         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3360 }
3361
3362 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3363 {
3364         int err;
3365
3366         err = mlx5e_create_tises(priv);
3367         if (err) {
3368                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3369                 return err;
3370         }
3371
3372 #ifdef CONFIG_MLX5_CORE_EN_DCB
3373         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3374 #endif
3375         return 0;
3376 }
3377
3378 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3379 {
3380         struct net_device *netdev = priv->netdev;
3381         struct mlx5_core_dev *mdev = priv->mdev;
3382         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3383         struct mlx5_eswitch_rep rep;
3384
3385         if (mlx5e_vxlan_allowed(mdev)) {
3386                 rtnl_lock();
3387                 udp_tunnel_get_rx_info(netdev);
3388                 rtnl_unlock();
3389         }
3390
3391         mlx5e_enable_async_events(priv);
3392         queue_work(priv->wq, &priv->set_rx_mode_work);
3393
3394         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3395                 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
3396                 rep.load = mlx5e_nic_rep_load;
3397                 rep.unload = mlx5e_nic_rep_unload;
3398                 rep.vport = 0;
3399                 rep.priv_data = priv;
3400                 mlx5_eswitch_register_vport_rep(esw, &rep);
3401         }
3402 }
3403
3404 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3405 {
3406         queue_work(priv->wq, &priv->set_rx_mode_work);
3407         mlx5e_disable_async_events(priv);
3408 }
3409
3410 static const struct mlx5e_profile mlx5e_nic_profile = {
3411         .init              = mlx5e_nic_init,
3412         .cleanup           = mlx5e_nic_cleanup,
3413         .init_rx           = mlx5e_init_nic_rx,
3414         .cleanup_rx        = mlx5e_cleanup_nic_rx,
3415         .init_tx           = mlx5e_init_nic_tx,
3416         .cleanup_tx        = mlx5e_cleanup_nic_tx,
3417         .enable            = mlx5e_nic_enable,
3418         .disable           = mlx5e_nic_disable,
3419         .update_stats      = mlx5e_update_stats,
3420         .max_nch           = mlx5e_get_max_num_channels,
3421         .max_tc            = MLX5E_MAX_NUM_TC,
3422 };
3423
3424 void *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3425                           const struct mlx5e_profile *profile, void *ppriv)
3426 {
3427         struct net_device *netdev;
3428         struct mlx5e_priv *priv;
3429         int nch = profile->max_nch(mdev);
3430         int err;
3431
3432         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3433                                     nch * profile->max_tc,
3434                                     nch);
3435         if (!netdev) {
3436                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3437                 return NULL;
3438         }
3439
3440         profile->init(mdev, netdev, profile, ppriv);
3441
3442         netif_carrier_off(netdev);
3443
3444         priv = netdev_priv(netdev);
3445
3446         priv->wq = create_singlethread_workqueue("mlx5e");
3447         if (!priv->wq)
3448                 goto err_free_netdev;
3449
3450         err = mlx5e_create_umr_mkey(priv);
3451         if (err) {
3452                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3453                 goto err_destroy_wq;
3454         }
3455
3456         err = profile->init_tx(priv);
3457         if (err)
3458                 goto err_destroy_umr_mkey;
3459
3460         err = mlx5e_open_drop_rq(priv);
3461         if (err) {
3462                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3463                 goto err_cleanup_tx;
3464         }
3465
3466         err = profile->init_rx(priv);
3467         if (err)
3468                 goto err_close_drop_rq;
3469
3470         mlx5e_create_q_counter(priv);
3471
3472         mlx5e_init_l2_addr(priv);
3473
3474         mlx5e_set_dev_port_mtu(netdev);
3475
3476         err = register_netdev(netdev);
3477         if (err) {
3478                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3479                 goto err_dealloc_q_counters;
3480         }
3481
3482         if (profile->enable)
3483                 profile->enable(priv);
3484
3485         return priv;
3486
3487 err_dealloc_q_counters:
3488         mlx5e_destroy_q_counter(priv);
3489         profile->cleanup_rx(priv);
3490
3491 err_close_drop_rq:
3492         mlx5e_close_drop_rq(priv);
3493
3494 err_cleanup_tx:
3495         profile->cleanup_tx(priv);
3496
3497 err_destroy_umr_mkey:
3498         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3499
3500 err_destroy_wq:
3501         destroy_workqueue(priv->wq);
3502
3503 err_free_netdev:
3504         free_netdev(netdev);
3505
3506         return NULL;
3507 }
3508
3509 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3510 {
3511         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3512         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3513         int vport;
3514         u8 mac[ETH_ALEN];
3515
3516         if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3517                 return;
3518
3519         mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3520
3521         for (vport = 1; vport < total_vfs; vport++) {
3522                 struct mlx5_eswitch_rep rep;
3523
3524                 rep.load = mlx5e_vport_rep_load;
3525                 rep.unload = mlx5e_vport_rep_unload;
3526                 rep.vport = vport;
3527                 ether_addr_copy(rep.hw_id, mac);
3528                 mlx5_eswitch_register_vport_rep(esw, &rep);
3529         }
3530 }
3531
3532 static void *mlx5e_add(struct mlx5_core_dev *mdev)
3533 {
3534         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3535         void *ppriv = NULL;
3536         void *ret;
3537
3538         if (mlx5e_check_required_hca_cap(mdev))
3539                 return NULL;
3540
3541         if (mlx5e_create_mdev_resources(mdev))
3542                 return NULL;
3543
3544         mlx5e_register_vport_rep(mdev);
3545
3546         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3547                 ppriv = &esw->offloads.vport_reps[0];
3548
3549         ret = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
3550         if (!ret) {
3551                 mlx5e_destroy_mdev_resources(mdev);
3552                 return NULL;
3553         }
3554         return ret;
3555 }
3556
3557 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
3558 {
3559         const struct mlx5e_profile *profile = priv->profile;
3560         struct net_device *netdev = priv->netdev;
3561
3562         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3563         if (profile->disable)
3564                 profile->disable(priv);
3565
3566         flush_workqueue(priv->wq);
3567         if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3568                 netif_device_detach(netdev);
3569                 mlx5e_close(netdev);
3570         } else {
3571                 unregister_netdev(netdev);
3572         }
3573
3574         mlx5e_destroy_q_counter(priv);
3575         profile->cleanup_rx(priv);
3576         mlx5e_close_drop_rq(priv);
3577         profile->cleanup_tx(priv);
3578         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3579         cancel_delayed_work_sync(&priv->update_stats_work);
3580         destroy_workqueue(priv->wq);
3581         if (profile->cleanup)
3582                 profile->cleanup(priv);
3583
3584         if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3585                 free_netdev(netdev);
3586 }
3587
3588 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
3589 {
3590         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3591         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3592         struct mlx5e_priv *priv = vpriv;
3593         int vport;
3594
3595         mlx5e_destroy_netdev(mdev, priv);
3596
3597         for (vport = 1; vport < total_vfs; vport++)
3598                 mlx5_eswitch_unregister_vport_rep(esw, vport);
3599
3600         mlx5e_destroy_mdev_resources(mdev);
3601 }
3602
3603 static void *mlx5e_get_netdev(void *vpriv)
3604 {
3605         struct mlx5e_priv *priv = vpriv;
3606
3607         return priv->netdev;
3608 }
3609
3610 static struct mlx5_interface mlx5e_interface = {
3611         .add       = mlx5e_add,
3612         .remove    = mlx5e_remove,
3613         .event     = mlx5e_async_event,
3614         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
3615         .get_dev   = mlx5e_get_netdev,
3616 };
3617
3618 void mlx5e_init(void)
3619 {
3620         mlx5e_build_ptys2ethtool_map();
3621         mlx5_register_interface(&mlx5e_interface);
3622 }
3623
3624 void mlx5e_cleanup(void)
3625 {
3626         mlx5_unregister_interface(&mlx5e_interface);
3627 }