drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 struct mlx5e_rq_param {
  43         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  44         struct mlx5_wq_param       wq;
  45 };
  46
  47 struct mlx5e_sq_param {
  48         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  49         struct mlx5_wq_param       wq;
  50         u16                        max_inline;
  51 };
  52
  53 struct mlx5e_cq_param {
  54         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  55         struct mlx5_wq_param       wq;
  56         u16                        eq_ix;
  57 };
  58
  59 struct mlx5e_channel_param {
  60         struct mlx5e_rq_param      rq;
  61         struct mlx5e_sq_param      sq;
  62         struct mlx5e_cq_param      rx_cq;
  63         struct mlx5e_cq_param      tx_cq;
  64 };
  65
  66 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  67 {
  68         struct mlx5_core_dev *mdev = priv->mdev;
  69         u8 port_state;
  70
  71         port_state = mlx5_query_vport_state(mdev,
  72                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  73
  74         if (port_state == VPORT_STATE_UP)
  75                 netif_carrier_on(priv->netdev);
  76         else
  77                 netif_carrier_off(priv->netdev);
  78 }
  79
  80 static void mlx5e_update_carrier_work(struct work_struct *work)
  81 {
  82         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  83                                                update_carrier_work);
  84
  85         mutex_lock(&priv->state_lock);
  86         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  87                 mlx5e_update_carrier(priv);
  88         mutex_unlock(&priv->state_lock);
  89 }
  90
  91 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
  92 {
  93         struct mlx5_core_dev *mdev = priv->mdev;
  94         struct mlx5e_pport_stats *s = &priv->stats.pport;
  95         u32 *in;
  96         u32 *out;
  97         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
  98
  99         in  = mlx5_vzalloc(sz);
 100         out = mlx5_vzalloc(sz);
 101         if (!in || !out)
 102                 goto free_out;
 103
 104         MLX5_SET(ppcnt_reg, in, local_port, 1);
 105
 106         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 107         mlx5_core_access_reg(mdev, in, sz, out,
 108                              sz, MLX5_REG_PPCNT, 0, 0);
 109         memcpy(s->IEEE_802_3_counters,
 110                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 111                sizeof(s->IEEE_802_3_counters));
 112
 113         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 114         mlx5_core_access_reg(mdev, in, sz, out,
 115                              sz, MLX5_REG_PPCNT, 0, 0);
 116         memcpy(s->RFC_2863_counters,
 117                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 118                sizeof(s->RFC_2863_counters));
 119
 120         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 121         mlx5_core_access_reg(mdev, in, sz, out,
 122                              sz, MLX5_REG_PPCNT, 0, 0);
 123         memcpy(s->RFC_2819_counters,
 124                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 125                sizeof(s->RFC_2819_counters));
 126
 127 free_out:
 128         kvfree(in);
 129         kvfree(out);
 130 }
 131
 132 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 133 {
 134         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 135
 136         if (!priv->q_counter)
 137                 return;
 138
 139         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 140                                       &qcnt->rx_out_of_buffer);
 141 }
 142
 143 void mlx5e_update_stats(struct mlx5e_priv *priv)
 144 {
 145         struct mlx5_core_dev *mdev = priv->mdev;
 146         struct mlx5e_vport_stats *s = &priv->stats.vport;
 147         struct mlx5e_rq_stats *rq_stats;
 148         struct mlx5e_sq_stats *sq_stats;
 149         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 150         u32 *out;
 151         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 152         u64 tx_offload_none;
 153         int i, j;
 154
 155         out = mlx5_vzalloc(outlen);
 156         if (!out)
 157                 return;
 158
 159         /* Collect firts the SW counters and then HW for consistency */
 160         s->rx_packets           = 0;
 161         s->rx_bytes             = 0;
 162         s->tx_packets           = 0;
 163         s->tx_bytes             = 0;
 164         s->tso_packets          = 0;
 165         s->tso_bytes            = 0;
 166         s->tso_inner_packets    = 0;
 167         s->tso_inner_bytes      = 0;
 168         s->tx_queue_stopped     = 0;
 169         s->tx_queue_wake        = 0;
 170         s->tx_queue_dropped     = 0;
 171         s->tx_csum_inner        = 0;
 172         tx_offload_none         = 0;
 173         s->lro_packets          = 0;
 174         s->lro_bytes            = 0;
 175         s->rx_csum_none         = 0;
 176         s->rx_csum_sw           = 0;
 177         s->rx_wqe_err           = 0;
 178         s->rx_mpwqe_filler      = 0;
 179         for (i = 0; i < priv->params.num_channels; i++) {
 180                 rq_stats = &priv->channel[i]->rq.stats;
 181
 182                 s->rx_packets   += rq_stats->packets;
 183                 s->rx_bytes     += rq_stats->bytes;
 184                 s->lro_packets  += rq_stats->lro_packets;
 185                 s->lro_bytes    += rq_stats->lro_bytes;
 186                 s->rx_csum_none += rq_stats->csum_none;
 187                 s->rx_csum_sw   += rq_stats->csum_sw;
 188                 s->rx_wqe_err   += rq_stats->wqe_err;
 189                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 190
 191                 for (j = 0; j < priv->params.num_tc; j++) {
 192                         sq_stats = &priv->channel[i]->sq[j].stats;
 193
 194                         s->tx_packets           += sq_stats->packets;
 195                         s->tx_bytes             += sq_stats->bytes;
 196                         s->tso_packets          += sq_stats->tso_packets;
 197                         s->tso_bytes            += sq_stats->tso_bytes;
 198                         s->tso_inner_packets    += sq_stats->tso_inner_packets;
 199                         s->tso_inner_bytes      += sq_stats->tso_inner_bytes;
 200                         s->tx_queue_stopped     += sq_stats->stopped;
 201                         s->tx_queue_wake        += sq_stats->wake;
 202                         s->tx_queue_dropped     += sq_stats->dropped;
 203                         s->tx_csum_inner        += sq_stats->csum_offload_inner;
 204                         tx_offload_none         += sq_stats->csum_offload_none;
 205                 }
 206         }
 207
 208         /* HW counters */
 209         memset(in, 0, sizeof(in));
 210
 211         MLX5_SET(query_vport_counter_in, in, opcode,
 212                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 213         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 214         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 215
 216         memset(out, 0, outlen);
 217
 218         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 219                 goto free_out;
 220
 221 #define MLX5_GET_CTR(p, x) \
 222         MLX5_GET64(query_vport_counter_out, p, x)
 223
 224         s->rx_error_packets     =
 225                 MLX5_GET_CTR(out, received_errors.packets);
 226         s->rx_error_bytes       =
 227                 MLX5_GET_CTR(out, received_errors.octets);
 228         s->tx_error_packets     =
 229                 MLX5_GET_CTR(out, transmit_errors.packets);
 230         s->tx_error_bytes       =
 231                 MLX5_GET_CTR(out, transmit_errors.octets);
 232
 233         s->rx_unicast_packets   =
 234                 MLX5_GET_CTR(out, received_eth_unicast.packets);
 235         s->rx_unicast_bytes     =
 236                 MLX5_GET_CTR(out, received_eth_unicast.octets);
 237         s->tx_unicast_packets   =
 238                 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 239         s->tx_unicast_bytes     =
 240                 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 241
 242         s->rx_multicast_packets =
 243                 MLX5_GET_CTR(out, received_eth_multicast.packets);
 244         s->rx_multicast_bytes   =
 245                 MLX5_GET_CTR(out, received_eth_multicast.octets);
 246         s->tx_multicast_packets =
 247                 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 248         s->tx_multicast_bytes   =
 249                 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 250
 251         s->rx_broadcast_packets =
 252                 MLX5_GET_CTR(out, received_eth_broadcast.packets);
 253         s->rx_broadcast_bytes   =
 254                 MLX5_GET_CTR(out, received_eth_broadcast.octets);
 255         s->tx_broadcast_packets =
 256                 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 257         s->tx_broadcast_bytes   =
 258                 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 259
 260         /* Update calculated offload counters */
 261         s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
 262         s->rx_csum_good    = s->rx_packets - s->rx_csum_none -
 263                                s->rx_csum_sw;
 264
 265         mlx5e_update_pport_counters(priv);
 266         mlx5e_update_q_counter(priv);
 267
 268 free_out:
 269         kvfree(out);
 270 }
 271
 272 static void mlx5e_update_stats_work(struct work_struct *work)
 273 {
 274         struct delayed_work *dwork = to_delayed_work(work);
 275         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 276                                                update_stats_work);
 277         mutex_lock(&priv->state_lock);
 278         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 279                 mlx5e_update_stats(priv);
 280                 schedule_delayed_work(dwork,
 281                                       msecs_to_jiffies(
 282                                               MLX5E_UPDATE_STATS_INTERVAL));
 283         }
 284         mutex_unlock(&priv->state_lock);
 285 }
 286
 287 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 288                               enum mlx5_dev_event event, unsigned long param)
 289 {
 290         struct mlx5e_priv *priv = vpriv;
 291
 292         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 293                 return;
 294
 295         switch (event) {
 296         case MLX5_DEV_EVENT_PORT_UP:
 297         case MLX5_DEV_EVENT_PORT_DOWN:
 298                 schedule_work(&priv->update_carrier_work);
 299                 break;
 300
 301         default:
 302                 break;
 303         }
 304 }
 305
 306 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 307 {
 308         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 309 }
 310
 311 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 312 {
 313         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 314         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 315 }
 316
 317 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 318 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 319
 320 static int mlx5e_create_rq(struct mlx5e_channel *c,
 321                            struct mlx5e_rq_param *param,
 322                            struct mlx5e_rq *rq)
 323 {
 324         struct mlx5e_priv *priv = c->priv;
 325         struct mlx5_core_dev *mdev = priv->mdev;
 326         void *rqc = param->rqc;
 327         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 328         u32 byte_count;
 329         int wq_sz;
 330         int err;
 331         int i;
 332
 333         param->wq.db_numa_node = cpu_to_node(c->cpu);
 334
 335         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 336                                 &rq->wq_ctrl);
 337         if (err)
 338                 return err;
 339
 340         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 341
 342         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 343
 344         switch (priv->params.rq_wq_type) {
 345         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 346                 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
 347                                             GFP_KERNEL, cpu_to_node(c->cpu));
 348                 if (!rq->wqe_info) {
 349                         err = -ENOMEM;
 350                         goto err_rq_wq_destroy;
 351                 }
 352                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 353                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 354
 355                 rq->wqe_sz = MLX5_MPWRQ_NUM_STRIDES * MLX5_MPWRQ_STRIDE_SIZE;
 356                 byte_count = rq->wqe_sz;
 357                 break;
 358         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 359                 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 360                                        cpu_to_node(c->cpu));
 361                 if (!rq->skb) {
 362                         err = -ENOMEM;
 363                         goto err_rq_wq_destroy;
 364                 }
 365                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 366                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 367
 368                 rq->wqe_sz = (priv->params.lro_en) ?
 369                                 priv->params.lro_wqe_sz :
 370                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 371                 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
 372                 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 373                 byte_count |= MLX5_HW_START_PADDING;
 374         }
 375
 376         for (i = 0; i < wq_sz; i++) {
 377                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 378
 379                 wqe->data.lkey       = c->mkey_be;
 380                 wqe->data.byte_count = cpu_to_be32(byte_count);
 381         }
 382
 383         rq->wq_type = priv->params.rq_wq_type;
 384         rq->pdev    = c->pdev;
 385         rq->netdev  = c->netdev;
 386         rq->tstamp  = &priv->tstamp;
 387         rq->channel = c;
 388         rq->ix      = c->ix;
 389         rq->priv    = c->priv;
 390
 391         return 0;
 392
 393 err_rq_wq_destroy:
 394         mlx5_wq_destroy(&rq->wq_ctrl);
 395
 396         return err;
 397 }
 398
 399 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 400 {
 401         switch (rq->wq_type) {
 402         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 403                 kfree(rq->wqe_info);
 404                 break;
 405         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 406                 kfree(rq->skb);
 407         }
 408
 409         mlx5_wq_destroy(&rq->wq_ctrl);
 410 }
 411
 412 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 413 {
 414         struct mlx5e_priv *priv = rq->priv;
 415         struct mlx5_core_dev *mdev = priv->mdev;
 416
 417         void *in;
 418         void *rqc;
 419         void *wq;
 420         int inlen;
 421         int err;
 422
 423         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 424                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 425         in = mlx5_vzalloc(inlen);
 426         if (!in)
 427                 return -ENOMEM;
 428
 429         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 430         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 431
 432         memcpy(rqc, param->rqc, sizeof(param->rqc));
 433
 434         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 435         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 436         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 437         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 438                                                 MLX5_ADAPTER_PAGE_SHIFT);
 439         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 440
 441         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 442                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 443
 444         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 445
 446         kvfree(in);
 447
 448         return err;
 449 }
 450
 451 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 452 {
 453         struct mlx5e_channel *c = rq->channel;
 454         struct mlx5e_priv *priv = c->priv;
 455         struct mlx5_core_dev *mdev = priv->mdev;
 456
 457         void *in;
 458         void *rqc;
 459         int inlen;
 460         int err;
 461
 462         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 463         in = mlx5_vzalloc(inlen);
 464         if (!in)
 465                 return -ENOMEM;
 466
 467         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 468
 469         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 470         MLX5_SET(rqc, rqc, state, next_state);
 471
 472         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 473
 474         kvfree(in);
 475
 476         return err;
 477 }
 478
 479 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 480 {
 481         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 482 }
 483
 484 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 485 {
 486         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 487         struct mlx5e_channel *c = rq->channel;
 488         struct mlx5e_priv *priv = c->priv;
 489         struct mlx5_wq_ll *wq = &rq->wq;
 490
 491         while (time_before(jiffies, exp_time)) {
 492                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 493                         return 0;
 494
 495                 msleep(20);
 496         }
 497
 498         return -ETIMEDOUT;
 499 }
 500
 501 static int mlx5e_open_rq(struct mlx5e_channel *c,
 502                          struct mlx5e_rq_param *param,
 503                          struct mlx5e_rq *rq)
 504 {
 505         int err;
 506
 507         err = mlx5e_create_rq(c, param, rq);
 508         if (err)
 509                 return err;
 510
 511         err = mlx5e_enable_rq(rq, param);
 512         if (err)
 513                 goto err_destroy_rq;
 514
 515         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 516         if (err)
 517                 goto err_disable_rq;
 518
 519         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 520         mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
 521
 522         return 0;
 523
 524 err_disable_rq:
 525         mlx5e_disable_rq(rq);
 526 err_destroy_rq:
 527         mlx5e_destroy_rq(rq);
 528
 529         return err;
 530 }
 531
 532 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 533 {
 534         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 535         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 536
 537         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 538         while (!mlx5_wq_ll_is_empty(&rq->wq))
 539                 msleep(20);
 540
 541         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 542         napi_synchronize(&rq->channel->napi);
 543
 544         mlx5e_disable_rq(rq);
 545         mlx5e_destroy_rq(rq);
 546 }
 547
 548 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 549 {
 550         kfree(sq->wqe_info);
 551         kfree(sq->dma_fifo);
 552         kfree(sq->skb);
 553 }
 554
 555 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 556 {
 557         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 558         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 559
 560         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 561         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 562                                     numa);
 563         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 564                                     numa);
 565
 566         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 567                 mlx5e_free_sq_db(sq);
 568                 return -ENOMEM;
 569         }
 570
 571         sq->dma_fifo_mask = df_sz - 1;
 572
 573         return 0;
 574 }
 575
 576 static int mlx5e_create_sq(struct mlx5e_channel *c,
 577                            int tc,
 578                            struct mlx5e_sq_param *param,
 579                            struct mlx5e_sq *sq)
 580 {
 581         struct mlx5e_priv *priv = c->priv;
 582         struct mlx5_core_dev *mdev = priv->mdev;
 583
 584         void *sqc = param->sqc;
 585         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 586         int txq_ix;
 587         int err;
 588
 589         err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
 590         if (err)
 591                 return err;
 592
 593         param->wq.db_numa_node = cpu_to_node(c->cpu);
 594
 595         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 596                                  &sq->wq_ctrl);
 597         if (err)
 598                 goto err_unmap_free_uar;
 599
 600         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 601         if (sq->uar.bf_map) {
 602                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 603                 sq->uar_map = sq->uar.bf_map;
 604         } else {
 605                 sq->uar_map = sq->uar.map;
 606         }
 607         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 608         sq->max_inline  = param->max_inline;
 609
 610         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 611         if (err)
 612                 goto err_sq_wq_destroy;
 613
 614         txq_ix = c->ix + tc * priv->params.num_channels;
 615         sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 616
 617         sq->pdev      = c->pdev;
 618         sq->tstamp    = &priv->tstamp;
 619         sq->mkey_be   = c->mkey_be;
 620         sq->channel   = c;
 621         sq->tc        = tc;
 622         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 623         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 624         priv->txq_to_sq_map[txq_ix] = sq;
 625
 626         return 0;
 627
 628 err_sq_wq_destroy:
 629         mlx5_wq_destroy(&sq->wq_ctrl);
 630
 631 err_unmap_free_uar:
 632         mlx5_unmap_free_uar(mdev, &sq->uar);
 633
 634         return err;
 635 }
 636
 637 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 638 {
 639         struct mlx5e_channel *c = sq->channel;
 640         struct mlx5e_priv *priv = c->priv;
 641
 642         mlx5e_free_sq_db(sq);
 643         mlx5_wq_destroy(&sq->wq_ctrl);
 644         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 645 }
 646
 647 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 648 {
 649         struct mlx5e_channel *c = sq->channel;
 650         struct mlx5e_priv *priv = c->priv;
 651         struct mlx5_core_dev *mdev = priv->mdev;
 652
 653         void *in;
 654         void *sqc;
 655         void *wq;
 656         int inlen;
 657         int err;
 658
 659         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 660                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 661         in = mlx5_vzalloc(inlen);
 662         if (!in)
 663                 return -ENOMEM;
 664
 665         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 666         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 667
 668         memcpy(sqc, param->sqc, sizeof(param->sqc));
 669
 670         MLX5_SET(sqc,  sqc, tis_num_0,          priv->tisn[sq->tc]);
 671         MLX5_SET(sqc,  sqc, cqn,                c->sq[sq->tc].cq.mcq.cqn);
 672         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 673         MLX5_SET(sqc,  sqc, tis_lst_sz,         1);
 674         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 675
 676         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 677         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 678         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 679                                           MLX5_ADAPTER_PAGE_SHIFT);
 680         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 681
 682         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 683                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 684
 685         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 686
 687         kvfree(in);
 688
 689         return err;
 690 }
 691
 692 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 693 {
 694         struct mlx5e_channel *c = sq->channel;
 695         struct mlx5e_priv *priv = c->priv;
 696         struct mlx5_core_dev *mdev = priv->mdev;
 697
 698         void *in;
 699         void *sqc;
 700         int inlen;
 701         int err;
 702
 703         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 704         in = mlx5_vzalloc(inlen);
 705         if (!in)
 706                 return -ENOMEM;
 707
 708         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 709
 710         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 711         MLX5_SET(sqc, sqc, state, next_state);
 712
 713         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 714
 715         kvfree(in);
 716
 717         return err;
 718 }
 719
 720 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 721 {
 722         struct mlx5e_channel *c = sq->channel;
 723         struct mlx5e_priv *priv = c->priv;
 724         struct mlx5_core_dev *mdev = priv->mdev;
 725
 726         mlx5_core_destroy_sq(mdev, sq->sqn);
 727 }
 728
 729 static int mlx5e_open_sq(struct mlx5e_channel *c,
 730                          int tc,
 731                          struct mlx5e_sq_param *param,
 732                          struct mlx5e_sq *sq)
 733 {
 734         int err;
 735
 736         err = mlx5e_create_sq(c, tc, param, sq);
 737         if (err)
 738                 return err;
 739
 740         err = mlx5e_enable_sq(sq, param);
 741         if (err)
 742                 goto err_destroy_sq;
 743
 744         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 745         if (err)
 746                 goto err_disable_sq;
 747
 748         set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 749         netdev_tx_reset_queue(sq->txq);
 750         netif_tx_start_queue(sq->txq);
 751
 752         return 0;
 753
 754 err_disable_sq:
 755         mlx5e_disable_sq(sq);
 756 err_destroy_sq:
 757         mlx5e_destroy_sq(sq);
 758
 759         return err;
 760 }
 761
 762 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 763 {
 764         __netif_tx_lock_bh(txq);
 765         netif_tx_stop_queue(txq);
 766         __netif_tx_unlock_bh(txq);
 767 }
 768
 769 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 770 {
 771         clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 772         napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
 773         netif_tx_disable_queue(sq->txq);
 774
 775         /* ensure hw is notified of all pending wqes */
 776         if (mlx5e_sq_has_room_for(sq, 1))
 777                 mlx5e_send_nop(sq, true);
 778
 779         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 780         while (sq->cc != sq->pc) /* wait till sq is empty */
 781                 msleep(20);
 782
 783         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 784         napi_synchronize(&sq->channel->napi);
 785
 786         mlx5e_disable_sq(sq);
 787         mlx5e_destroy_sq(sq);
 788 }
 789
 790 static int mlx5e_create_cq(struct mlx5e_channel *c,
 791                            struct mlx5e_cq_param *param,
 792                            struct mlx5e_cq *cq)
 793 {
 794         struct mlx5e_priv *priv = c->priv;
 795         struct mlx5_core_dev *mdev = priv->mdev;
 796         struct mlx5_core_cq *mcq = &cq->mcq;
 797         int eqn_not_used;
 798         unsigned int irqn;
 799         int err;
 800         u32 i;
 801
 802         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 803         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 804         param->eq_ix   = c->ix;
 805
 806         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 807                                &cq->wq_ctrl);
 808         if (err)
 809                 return err;
 810
 811         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 812
 813         cq->napi        = &c->napi;
 814
 815         mcq->cqe_sz     = 64;
 816         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 817         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 818         *mcq->set_ci_db = 0;
 819         *mcq->arm_db    = 0;
 820         mcq->vector     = param->eq_ix;
 821         mcq->comp       = mlx5e_completion_event;
 822         mcq->event      = mlx5e_cq_error_event;
 823         mcq->irqn       = irqn;
 824         mcq->uar        = &priv->cq_uar;
 825
 826         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 827                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 828
 829                 cqe->op_own = 0xf1;
 830         }
 831
 832         cq->channel = c;
 833         cq->priv = priv;
 834
 835         return 0;
 836 }
 837
 838 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 839 {
 840         mlx5_wq_destroy(&cq->wq_ctrl);
 841 }
 842
 843 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 844 {
 845         struct mlx5e_priv *priv = cq->priv;
 846         struct mlx5_core_dev *mdev = priv->mdev;
 847         struct mlx5_core_cq *mcq = &cq->mcq;
 848
 849         void *in;
 850         void *cqc;
 851         int inlen;
 852         unsigned int irqn_not_used;
 853         int eqn;
 854         int err;
 855
 856         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 857                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 858         in = mlx5_vzalloc(inlen);
 859         if (!in)
 860                 return -ENOMEM;
 861
 862         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 863
 864         memcpy(cqc, param->cqc, sizeof(param->cqc));
 865
 866         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 867                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 868
 869         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 870
 871         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 872         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 873         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 874                                             MLX5_ADAPTER_PAGE_SHIFT);
 875         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 876
 877         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 878
 879         kvfree(in);
 880
 881         if (err)
 882                 return err;
 883
 884         mlx5e_cq_arm(cq);
 885
 886         return 0;
 887 }
 888
 889 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 890 {
 891         struct mlx5e_priv *priv = cq->priv;
 892         struct mlx5_core_dev *mdev = priv->mdev;
 893
 894         mlx5_core_destroy_cq(mdev, &cq->mcq);
 895 }
 896
 897 static int mlx5e_open_cq(struct mlx5e_channel *c,
 898                          struct mlx5e_cq_param *param,
 899                          struct mlx5e_cq *cq,
 900                          u16 moderation_usecs,
 901                          u16 moderation_frames)
 902 {
 903         int err;
 904         struct mlx5e_priv *priv = c->priv;
 905         struct mlx5_core_dev *mdev = priv->mdev;
 906
 907         err = mlx5e_create_cq(c, param, cq);
 908         if (err)
 909                 return err;
 910
 911         err = mlx5e_enable_cq(cq, param);
 912         if (err)
 913                 goto err_destroy_cq;
 914
 915         if (MLX5_CAP_GEN(mdev, cq_moderation))
 916                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 917                                                moderation_usecs,
 918                                                moderation_frames);
 919         return 0;
 920
 921 err_destroy_cq:
 922         mlx5e_destroy_cq(cq);
 923
 924         return err;
 925 }
 926
 927 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 928 {
 929         mlx5e_disable_cq(cq);
 930         mlx5e_destroy_cq(cq);
 931 }
 932
 933 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 934 {
 935         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 936 }
 937
 938 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 939                              struct mlx5e_channel_param *cparam)
 940 {
 941         struct mlx5e_priv *priv = c->priv;
 942         int err;
 943         int tc;
 944
 945         for (tc = 0; tc < c->num_tc; tc++) {
 946                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 947                                     priv->params.tx_cq_moderation_usec,
 948                                     priv->params.tx_cq_moderation_pkts);
 949                 if (err)
 950                         goto err_close_tx_cqs;
 951         }
 952
 953         return 0;
 954
 955 err_close_tx_cqs:
 956         for (tc--; tc >= 0; tc--)
 957                 mlx5e_close_cq(&c->sq[tc].cq);
 958
 959         return err;
 960 }
 961
 962 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 963 {
 964         int tc;
 965
 966         for (tc = 0; tc < c->num_tc; tc++)
 967                 mlx5e_close_cq(&c->sq[tc].cq);
 968 }
 969
 970 static int mlx5e_open_sqs(struct mlx5e_channel *c,
 971                           struct mlx5e_channel_param *cparam)
 972 {
 973         int err;
 974         int tc;
 975
 976         for (tc = 0; tc < c->num_tc; tc++) {
 977                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
 978                 if (err)
 979                         goto err_close_sqs;
 980         }
 981
 982         return 0;
 983
 984 err_close_sqs:
 985         for (tc--; tc >= 0; tc--)
 986                 mlx5e_close_sq(&c->sq[tc]);
 987
 988         return err;
 989 }
 990
 991 static void mlx5e_close_sqs(struct mlx5e_channel *c)
 992 {
 993         int tc;
 994
 995         for (tc = 0; tc < c->num_tc; tc++)
 996                 mlx5e_close_sq(&c->sq[tc]);
 997 }
 998
 999 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1000 {
1001         int i;
1002
1003         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
1004                 priv->channeltc_to_txq_map[ix][i] =
1005                         ix + i * priv->params.num_channels;
1006 }
1007
1008 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1009                               struct mlx5e_channel_param *cparam,
1010                               struct mlx5e_channel **cp)
1011 {
1012         struct net_device *netdev = priv->netdev;
1013         int cpu = mlx5e_get_cpu(priv, ix);
1014         struct mlx5e_channel *c;
1015         int err;
1016
1017         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1018         if (!c)
1019                 return -ENOMEM;
1020
1021         c->priv     = priv;
1022         c->ix       = ix;
1023         c->cpu      = cpu;
1024         c->pdev     = &priv->mdev->pdev->dev;
1025         c->netdev   = priv->netdev;
1026         c->mkey_be  = cpu_to_be32(priv->mkey.key);
1027         c->num_tc   = priv->params.num_tc;
1028
1029         mlx5e_build_channeltc_to_txq_map(priv, ix);
1030
1031         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1032
1033         err = mlx5e_open_tx_cqs(c, cparam);
1034         if (err)
1035                 goto err_napi_del;
1036
1037         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1038                             priv->params.rx_cq_moderation_usec,
1039                             priv->params.rx_cq_moderation_pkts);
1040         if (err)
1041                 goto err_close_tx_cqs;
1042
1043         napi_enable(&c->napi);
1044
1045         err = mlx5e_open_sqs(c, cparam);
1046         if (err)
1047                 goto err_disable_napi;
1048
1049         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1050         if (err)
1051                 goto err_close_sqs;
1052
1053         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1054         *cp = c;
1055
1056         return 0;
1057
1058 err_close_sqs:
1059         mlx5e_close_sqs(c);
1060
1061 err_disable_napi:
1062         napi_disable(&c->napi);
1063         mlx5e_close_cq(&c->rq.cq);
1064
1065 err_close_tx_cqs:
1066         mlx5e_close_tx_cqs(c);
1067
1068 err_napi_del:
1069         netif_napi_del(&c->napi);
1070         napi_hash_del(&c->napi);
1071         kfree(c);
1072
1073         return err;
1074 }
1075
1076 static void mlx5e_close_channel(struct mlx5e_channel *c)
1077 {
1078         mlx5e_close_rq(&c->rq);
1079         mlx5e_close_sqs(c);
1080         napi_disable(&c->napi);
1081         mlx5e_close_cq(&c->rq.cq);
1082         mlx5e_close_tx_cqs(c);
1083         netif_napi_del(&c->napi);
1084
1085         napi_hash_del(&c->napi);
1086         synchronize_rcu();
1087
1088         kfree(c);
1089 }
1090
1091 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1092                                  struct mlx5e_rq_param *param)
1093 {
1094         void *rqc = param->rqc;
1095         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1096
1097         switch (priv->params.rq_wq_type) {
1098         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1099                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1100                          MLX5_MPWRQ_LOG_NUM_STRIDES - 9);
1101                 MLX5_SET(wq, wq, log_wqe_stride_size,
1102                          MLX5_MPWRQ_LOG_STRIDE_SIZE - 6);
1103                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1104                 break;
1105         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1106                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1107         }
1108
1109         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1110         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1111         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1112         MLX5_SET(wq, wq, pd,               priv->pdn);
1113         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1114
1115         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1116         param->wq.linear = 1;
1117 }
1118
1119 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1120 {
1121         void *rqc = param->rqc;
1122         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1123
1124         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1125         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1126 }
1127
1128 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1129                                  struct mlx5e_sq_param *param)
1130 {
1131         void *sqc = param->sqc;
1132         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1133
1134         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1135         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1136         MLX5_SET(wq, wq, pd,            priv->pdn);
1137
1138         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1139         param->max_inline = priv->params.tx_max_inline;
1140 }
1141
1142 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1143                                         struct mlx5e_cq_param *param)
1144 {
1145         void *cqc = param->cqc;
1146
1147         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1148 }
1149
1150 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1151                                     struct mlx5e_cq_param *param)
1152 {
1153         void *cqc = param->cqc;
1154         u8 log_cq_size;
1155
1156         switch (priv->params.rq_wq_type) {
1157         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1158                 log_cq_size = priv->params.log_rq_size +
1159                         MLX5_MPWRQ_LOG_NUM_STRIDES;
1160                 break;
1161         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1162                 log_cq_size = priv->params.log_rq_size;
1163         }
1164
1165         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1166
1167         mlx5e_build_common_cq_param(priv, param);
1168 }
1169
1170 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1171                                     struct mlx5e_cq_param *param)
1172 {
1173         void *cqc = param->cqc;
1174
1175         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_sq_size);
1176
1177         mlx5e_build_common_cq_param(priv, param);
1178 }
1179
1180 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1181                                       struct mlx5e_channel_param *cparam)
1182 {
1183         memset(cparam, 0, sizeof(*cparam));
1184
1185         mlx5e_build_rq_param(priv, &cparam->rq);
1186         mlx5e_build_sq_param(priv, &cparam->sq);
1187         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1188         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1189 }
1190
1191 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1192 {
1193         struct mlx5e_channel_param cparam;
1194         int nch = priv->params.num_channels;
1195         int err = -ENOMEM;
1196         int i;
1197         int j;
1198
1199         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1200                                 GFP_KERNEL);
1201
1202         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1203                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1204
1205         if (!priv->channel || !priv->txq_to_sq_map)
1206                 goto err_free_txq_to_sq_map;
1207
1208         mlx5e_build_channel_param(priv, &cparam);
1209         for (i = 0; i < nch; i++) {
1210                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1211                 if (err)
1212                         goto err_close_channels;
1213         }
1214
1215         for (j = 0; j < nch; j++) {
1216                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1217                 if (err)
1218                         goto err_close_channels;
1219         }
1220
1221         return 0;
1222
1223 err_close_channels:
1224         for (i--; i >= 0; i--)
1225                 mlx5e_close_channel(priv->channel[i]);
1226
1227 err_free_txq_to_sq_map:
1228         kfree(priv->txq_to_sq_map);
1229         kfree(priv->channel);
1230
1231         return err;
1232 }
1233
1234 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1235 {
1236         int i;
1237
1238         for (i = 0; i < priv->params.num_channels; i++)
1239                 mlx5e_close_channel(priv->channel[i]);
1240
1241         kfree(priv->txq_to_sq_map);
1242         kfree(priv->channel);
1243 }
1244
1245 static int mlx5e_rx_hash_fn(int hfunc)
1246 {
1247         return (hfunc == ETH_RSS_HASH_TOP) ?
1248                MLX5_RX_HASH_FN_TOEPLITZ :
1249                MLX5_RX_HASH_FN_INVERTED_XOR8;
1250 }
1251
1252 static int mlx5e_bits_invert(unsigned long a, int size)
1253 {
1254         int inv = 0;
1255         int i;
1256
1257         for (i = 0; i < size; i++)
1258                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1259
1260         return inv;
1261 }
1262
1263 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1264 {
1265         int i;
1266
1267         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1268                 int ix = i;
1269
1270                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1271                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1272
1273                 ix = priv->params.indirection_rqt[ix];
1274                 MLX5_SET(rqtc, rqtc, rq_num[i],
1275                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1276                          priv->channel[ix]->rq.rqn :
1277                          priv->drop_rq.rqn);
1278         }
1279 }
1280
1281 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1282                                 enum mlx5e_rqt_ix rqt_ix)
1283 {
1284
1285         switch (rqt_ix) {
1286         case MLX5E_INDIRECTION_RQT:
1287                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1288
1289                 break;
1290
1291         default: /* MLX5E_SINGLE_RQ_RQT */
1292                 MLX5_SET(rqtc, rqtc, rq_num[0],
1293                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1294                          priv->channel[0]->rq.rqn :
1295                          priv->drop_rq.rqn);
1296
1297                 break;
1298         }
1299 }
1300
1301 static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1302 {
1303         struct mlx5_core_dev *mdev = priv->mdev;
1304         u32 *in;
1305         void *rqtc;
1306         int inlen;
1307         int sz;
1308         int err;
1309
1310         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1311
1312         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1313         in = mlx5_vzalloc(inlen);
1314         if (!in)
1315                 return -ENOMEM;
1316
1317         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1318
1319         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1320         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1321
1322         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1323
1324         err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
1325
1326         kvfree(in);
1327
1328         return err;
1329 }
1330
1331 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1332 {
1333         struct mlx5_core_dev *mdev = priv->mdev;
1334         u32 *in;
1335         void *rqtc;
1336         int inlen;
1337         int sz;
1338         int err;
1339
1340         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1341
1342         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1343         in = mlx5_vzalloc(inlen);
1344         if (!in)
1345                 return -ENOMEM;
1346
1347         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1348
1349         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1350
1351         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1352
1353         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1354
1355         err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1356
1357         kvfree(in);
1358
1359         return err;
1360 }
1361
1362 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1363 {
1364         mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
1365 }
1366
1367 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1368 {
1369         mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1370         mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1371 }
1372
1373 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1374 {
1375         if (!priv->params.lro_en)
1376                 return;
1377
1378 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1379
1380         MLX5_SET(tirc, tirc, lro_enable_mask,
1381                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1382                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1383         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1384                  (priv->params.lro_wqe_sz -
1385                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1386         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1387                  MLX5_CAP_ETH(priv->mdev,
1388                               lro_timer_supported_periods[2]));
1389 }
1390
1391 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1392 {
1393         MLX5_SET(tirc, tirc, rx_hash_fn,
1394                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1395         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1396                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1397                                              rx_hash_toeplitz_key);
1398                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1399                                                rx_hash_toeplitz_key);
1400
1401                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1402                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1403         }
1404 }
1405
1406 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1407 {
1408         struct mlx5_core_dev *mdev = priv->mdev;
1409
1410         void *in;
1411         void *tirc;
1412         int inlen;
1413         int err;
1414         int tt;
1415
1416         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1417         in = mlx5_vzalloc(inlen);
1418         if (!in)
1419                 return -ENOMEM;
1420
1421         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1422         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1423
1424         mlx5e_build_tir_ctx_lro(tirc, priv);
1425
1426         for (tt = 0; tt < MLX5E_NUM_TT; tt++) {
1427                 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1428                 if (err)
1429                         break;
1430         }
1431
1432         kvfree(in);
1433
1434         return err;
1435 }
1436
1437 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1438                                                   u32 tirn)
1439 {
1440         void *in;
1441         int inlen;
1442         int err;
1443
1444         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1445         in = mlx5_vzalloc(inlen);
1446         if (!in)
1447                 return -ENOMEM;
1448
1449         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1450
1451         err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1452
1453         kvfree(in);
1454
1455         return err;
1456 }
1457
1458 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1459 {
1460         int err;
1461         int i;
1462
1463         for (i = 0; i < MLX5E_NUM_TT; i++) {
1464                 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1465                                                              priv->tirn[i]);
1466                 if (err)
1467                         return err;
1468         }
1469
1470         return 0;
1471 }
1472
1473 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1474 {
1475         struct mlx5e_priv *priv = netdev_priv(netdev);
1476         struct mlx5_core_dev *mdev = priv->mdev;
1477         int hw_mtu;
1478         int err;
1479
1480         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1481         if (err)
1482                 return err;
1483
1484         mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1485
1486         if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1487                 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1488                             __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1489
1490         netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1491         return 0;
1492 }
1493
1494 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1495 {
1496         struct mlx5e_priv *priv = netdev_priv(netdev);
1497         int nch = priv->params.num_channels;
1498         int ntc = priv->params.num_tc;
1499         int tc;
1500
1501         netdev_reset_tc(netdev);
1502
1503         if (ntc == 1)
1504                 return;
1505
1506         netdev_set_num_tc(netdev, ntc);
1507
1508         for (tc = 0; tc < ntc; tc++)
1509                 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1510 }
1511
1512 int mlx5e_open_locked(struct net_device *netdev)
1513 {
1514         struct mlx5e_priv *priv = netdev_priv(netdev);
1515         int num_txqs;
1516         int err;
1517
1518         set_bit(MLX5E_STATE_OPENED, &priv->state);
1519
1520         mlx5e_netdev_set_tcs(netdev);
1521
1522         num_txqs = priv->params.num_channels * priv->params.num_tc;
1523         netif_set_real_num_tx_queues(netdev, num_txqs);
1524         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1525
1526         err = mlx5e_set_dev_port_mtu(netdev);
1527         if (err)
1528                 goto err_clear_state_opened_flag;
1529
1530         err = mlx5e_open_channels(priv);
1531         if (err) {
1532                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1533                            __func__, err);
1534                 goto err_clear_state_opened_flag;
1535         }
1536
1537         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1538         if (err) {
1539                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1540                            __func__, err);
1541                 goto err_close_channels;
1542         }
1543
1544         mlx5e_redirect_rqts(priv);
1545         mlx5e_update_carrier(priv);
1546         mlx5e_timestamp_init(priv);
1547
1548         schedule_delayed_work(&priv->update_stats_work, 0);
1549
1550         return 0;
1551
1552 err_close_channels:
1553         mlx5e_close_channels(priv);
1554 err_clear_state_opened_flag:
1555         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1556         return err;
1557 }
1558
1559 static int mlx5e_open(struct net_device *netdev)
1560 {
1561         struct mlx5e_priv *priv = netdev_priv(netdev);
1562         int err;
1563
1564         mutex_lock(&priv->state_lock);
1565         err = mlx5e_open_locked(netdev);
1566         mutex_unlock(&priv->state_lock);
1567
1568         return err;
1569 }
1570
1571 int mlx5e_close_locked(struct net_device *netdev)
1572 {
1573         struct mlx5e_priv *priv = netdev_priv(netdev);
1574
1575         /* May already be CLOSED in case a previous configuration operation
1576          * (e.g RX/TX queue size change) that involves close&open failed.
1577          */
1578         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1579                 return 0;
1580
1581         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1582
1583         mlx5e_timestamp_cleanup(priv);
1584         netif_carrier_off(priv->netdev);
1585         mlx5e_redirect_rqts(priv);
1586         mlx5e_close_channels(priv);
1587
1588         return 0;
1589 }
1590
1591 static int mlx5e_close(struct net_device *netdev)
1592 {
1593         struct mlx5e_priv *priv = netdev_priv(netdev);
1594         int err;
1595
1596         mutex_lock(&priv->state_lock);
1597         err = mlx5e_close_locked(netdev);
1598         mutex_unlock(&priv->state_lock);
1599
1600         return err;
1601 }
1602
1603 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1604                                 struct mlx5e_rq *rq,
1605                                 struct mlx5e_rq_param *param)
1606 {
1607         struct mlx5_core_dev *mdev = priv->mdev;
1608         void *rqc = param->rqc;
1609         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1610         int err;
1611
1612         param->wq.db_numa_node = param->wq.buf_numa_node;
1613
1614         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1615                                 &rq->wq_ctrl);
1616         if (err)
1617                 return err;
1618
1619         rq->priv = priv;
1620
1621         return 0;
1622 }
1623
1624 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1625                                 struct mlx5e_cq *cq,
1626                                 struct mlx5e_cq_param *param)
1627 {
1628         struct mlx5_core_dev *mdev = priv->mdev;
1629         struct mlx5_core_cq *mcq = &cq->mcq;
1630         int eqn_not_used;
1631         unsigned int irqn;
1632         int err;
1633
1634         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1635                                &cq->wq_ctrl);
1636         if (err)
1637                 return err;
1638
1639         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1640
1641         mcq->cqe_sz     = 64;
1642         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1643         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1644         *mcq->set_ci_db = 0;
1645         *mcq->arm_db    = 0;
1646         mcq->vector     = param->eq_ix;
1647         mcq->comp       = mlx5e_completion_event;
1648         mcq->event      = mlx5e_cq_error_event;
1649         mcq->irqn       = irqn;
1650         mcq->uar        = &priv->cq_uar;
1651
1652         cq->priv = priv;
1653
1654         return 0;
1655 }
1656
1657 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1658 {
1659         struct mlx5e_cq_param cq_param;
1660         struct mlx5e_rq_param rq_param;
1661         struct mlx5e_rq *rq = &priv->drop_rq;
1662         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1663         int err;
1664
1665         memset(&cq_param, 0, sizeof(cq_param));
1666         memset(&rq_param, 0, sizeof(rq_param));
1667         mlx5e_build_drop_rq_param(&rq_param);
1668
1669         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1670         if (err)
1671                 return err;
1672
1673         err = mlx5e_enable_cq(cq, &cq_param);
1674         if (err)
1675                 goto err_destroy_cq;
1676
1677         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1678         if (err)
1679                 goto err_disable_cq;
1680
1681         err = mlx5e_enable_rq(rq, &rq_param);
1682         if (err)
1683                 goto err_destroy_rq;
1684
1685         return 0;
1686
1687 err_destroy_rq:
1688         mlx5e_destroy_rq(&priv->drop_rq);
1689
1690 err_disable_cq:
1691         mlx5e_disable_cq(&priv->drop_rq.cq);
1692
1693 err_destroy_cq:
1694         mlx5e_destroy_cq(&priv->drop_rq.cq);
1695
1696         return err;
1697 }
1698
1699 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1700 {
1701         mlx5e_disable_rq(&priv->drop_rq);
1702         mlx5e_destroy_rq(&priv->drop_rq);
1703         mlx5e_disable_cq(&priv->drop_rq.cq);
1704         mlx5e_destroy_cq(&priv->drop_rq.cq);
1705 }
1706
1707 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1708 {
1709         struct mlx5_core_dev *mdev = priv->mdev;
1710         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1711         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1712
1713         memset(in, 0, sizeof(in));
1714
1715         MLX5_SET(tisc, tisc, prio, tc << 1);
1716         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1717
1718         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1719 }
1720
1721 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1722 {
1723         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1724 }
1725
1726 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1727 {
1728         int err;
1729         int tc;
1730
1731         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1732                 err = mlx5e_create_tis(priv, tc);
1733                 if (err)
1734                         goto err_close_tises;
1735         }
1736
1737         return 0;
1738
1739 err_close_tises:
1740         for (tc--; tc >= 0; tc--)
1741                 mlx5e_destroy_tis(priv, tc);
1742
1743         return err;
1744 }
1745
1746 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1747 {
1748         int tc;
1749
1750         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1751                 mlx5e_destroy_tis(priv, tc);
1752 }
1753
1754 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1755 {
1756         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1757
1758         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1759
1760 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1761                                  MLX5_HASH_FIELD_SEL_DST_IP)
1762
1763 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1764                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1765                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1766                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1767
1768 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1769                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1770                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1771
1772         mlx5e_build_tir_ctx_lro(tirc, priv);
1773
1774         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1775
1776         switch (tt) {
1777         case MLX5E_TT_ANY:
1778                 MLX5_SET(tirc, tirc, indirect_table,
1779                          priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1780                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
1781                 break;
1782         default:
1783                 MLX5_SET(tirc, tirc, indirect_table,
1784                          priv->rqtn[MLX5E_INDIRECTION_RQT]);
1785                 mlx5e_build_tir_ctx_hash(tirc, priv);
1786                 break;
1787         }
1788
1789         switch (tt) {
1790         case MLX5E_TT_IPV4_TCP:
1791                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1792                          MLX5_L3_PROT_TYPE_IPV4);
1793                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1794                          MLX5_L4_PROT_TYPE_TCP);
1795                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1796                          MLX5_HASH_IP_L4PORTS);
1797                 break;
1798
1799         case MLX5E_TT_IPV6_TCP:
1800                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1801                          MLX5_L3_PROT_TYPE_IPV6);
1802                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1803                          MLX5_L4_PROT_TYPE_TCP);
1804                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1805                          MLX5_HASH_IP_L4PORTS);
1806                 break;
1807
1808         case MLX5E_TT_IPV4_UDP:
1809                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1810                          MLX5_L3_PROT_TYPE_IPV4);
1811                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1812                          MLX5_L4_PROT_TYPE_UDP);
1813                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1814                          MLX5_HASH_IP_L4PORTS);
1815                 break;
1816
1817         case MLX5E_TT_IPV6_UDP:
1818                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1819                          MLX5_L3_PROT_TYPE_IPV6);
1820                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1821                          MLX5_L4_PROT_TYPE_UDP);
1822                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1823                          MLX5_HASH_IP_L4PORTS);
1824                 break;
1825
1826         case MLX5E_TT_IPV4_IPSEC_AH:
1827                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1828                          MLX5_L3_PROT_TYPE_IPV4);
1829                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1830                          MLX5_HASH_IP_IPSEC_SPI);
1831                 break;
1832
1833         case MLX5E_TT_IPV6_IPSEC_AH:
1834                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1835                          MLX5_L3_PROT_TYPE_IPV6);
1836                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1837                          MLX5_HASH_IP_IPSEC_SPI);
1838                 break;
1839
1840         case MLX5E_TT_IPV4_IPSEC_ESP:
1841                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1842                          MLX5_L3_PROT_TYPE_IPV4);
1843                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1844                          MLX5_HASH_IP_IPSEC_SPI);
1845                 break;
1846
1847         case MLX5E_TT_IPV6_IPSEC_ESP:
1848                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1849                          MLX5_L3_PROT_TYPE_IPV6);
1850                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1851                          MLX5_HASH_IP_IPSEC_SPI);
1852                 break;
1853
1854         case MLX5E_TT_IPV4:
1855                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1856                          MLX5_L3_PROT_TYPE_IPV4);
1857                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1858                          MLX5_HASH_IP);
1859                 break;
1860
1861         case MLX5E_TT_IPV6:
1862                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1863                          MLX5_L3_PROT_TYPE_IPV6);
1864                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1865                          MLX5_HASH_IP);
1866                 break;
1867         }
1868 }
1869
1870 static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
1871 {
1872         struct mlx5_core_dev *mdev = priv->mdev;
1873         u32 *in;
1874         void *tirc;
1875         int inlen;
1876         int err;
1877
1878         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1879         in = mlx5_vzalloc(inlen);
1880         if (!in)
1881                 return -ENOMEM;
1882
1883         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1884
1885         mlx5e_build_tir_ctx(priv, tirc, tt);
1886
1887         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1888
1889         kvfree(in);
1890
1891         return err;
1892 }
1893
1894 static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
1895 {
1896         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1897 }
1898
1899 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
1900 {
1901         int err;
1902         int i;
1903
1904         for (i = 0; i < MLX5E_NUM_TT; i++) {
1905                 err = mlx5e_create_tir(priv, i);
1906                 if (err)
1907                         goto err_destroy_tirs;
1908         }
1909
1910         return 0;
1911
1912 err_destroy_tirs:
1913         for (i--; i >= 0; i--)
1914                 mlx5e_destroy_tir(priv, i);
1915
1916         return err;
1917 }
1918
1919 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
1920 {
1921         int i;
1922
1923         for (i = 0; i < MLX5E_NUM_TT; i++)
1924                 mlx5e_destroy_tir(priv, i);
1925 }
1926
1927 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
1928 {
1929         struct mlx5e_priv *priv = netdev_priv(netdev);
1930         bool was_opened;
1931         int err = 0;
1932
1933         if (tc && tc != MLX5E_MAX_NUM_TC)
1934                 return -EINVAL;
1935
1936         mutex_lock(&priv->state_lock);
1937
1938         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1939         if (was_opened)
1940                 mlx5e_close_locked(priv->netdev);
1941
1942         priv->params.num_tc = tc ? tc : 1;
1943
1944         if (was_opened)
1945                 err = mlx5e_open_locked(priv->netdev);
1946
1947         mutex_unlock(&priv->state_lock);
1948
1949         return err;
1950 }
1951
1952 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
1953                               __be16 proto, struct tc_to_netdev *tc)
1954 {
1955         struct mlx5e_priv *priv = netdev_priv(dev);
1956
1957         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
1958                 goto mqprio;
1959
1960         switch (tc->type) {
1961         case TC_SETUP_CLSFLOWER:
1962                 switch (tc->cls_flower->command) {
1963                 case TC_CLSFLOWER_REPLACE:
1964                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
1965                 case TC_CLSFLOWER_DESTROY:
1966                         return mlx5e_delete_flower(priv, tc->cls_flower);
1967                 }
1968         default:
1969                 return -EOPNOTSUPP;
1970         }
1971
1972 mqprio:
1973         if (tc->type != TC_SETUP_MQPRIO)
1974                 return -EINVAL;
1975
1976         return mlx5e_setup_tc(dev, tc->tc);
1977 }
1978
1979 static struct rtnl_link_stats64 *
1980 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1981 {
1982         struct mlx5e_priv *priv = netdev_priv(dev);
1983         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1984
1985         stats->rx_packets = vstats->rx_packets;
1986         stats->rx_bytes   = vstats->rx_bytes;
1987         stats->tx_packets = vstats->tx_packets;
1988         stats->tx_bytes   = vstats->tx_bytes;
1989         stats->multicast  = vstats->rx_multicast_packets +
1990                             vstats->tx_multicast_packets;
1991         stats->tx_errors  = vstats->tx_error_packets;
1992         stats->rx_errors  = vstats->rx_error_packets;
1993         stats->tx_dropped = vstats->tx_queue_dropped;
1994         stats->rx_crc_errors = 0;
1995         stats->rx_length_errors = 0;
1996
1997         return stats;
1998 }
1999
2000 static void mlx5e_set_rx_mode(struct net_device *dev)
2001 {
2002         struct mlx5e_priv *priv = netdev_priv(dev);
2003
2004         schedule_work(&priv->set_rx_mode_work);
2005 }
2006
2007 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2008 {
2009         struct mlx5e_priv *priv = netdev_priv(netdev);
2010         struct sockaddr *saddr = addr;
2011
2012         if (!is_valid_ether_addr(saddr->sa_data))
2013                 return -EADDRNOTAVAIL;
2014
2015         netif_addr_lock_bh(netdev);
2016         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2017         netif_addr_unlock_bh(netdev);
2018
2019         schedule_work(&priv->set_rx_mode_work);
2020
2021         return 0;
2022 }
2023
2024 static int mlx5e_set_features(struct net_device *netdev,
2025                               netdev_features_t features)
2026 {
2027         struct mlx5e_priv *priv = netdev_priv(netdev);
2028         int err = 0;
2029         netdev_features_t changes = features ^ netdev->features;
2030
2031         mutex_lock(&priv->state_lock);
2032
2033         if (changes & NETIF_F_LRO) {
2034                 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2035
2036                 if (was_opened && (priv->params.rq_wq_type ==
2037                                    MLX5_WQ_TYPE_LINKED_LIST))
2038                         mlx5e_close_locked(priv->netdev);
2039
2040                 priv->params.lro_en = !!(features & NETIF_F_LRO);
2041                 err = mlx5e_modify_tirs_lro(priv);
2042                 if (err)
2043                         mlx5_core_warn(priv->mdev, "lro modify failed, %d\n",
2044                                        err);
2045
2046                 if (was_opened && (priv->params.rq_wq_type ==
2047                                    MLX5_WQ_TYPE_LINKED_LIST))
2048                         err = mlx5e_open_locked(priv->netdev);
2049         }
2050
2051         mutex_unlock(&priv->state_lock);
2052
2053         if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
2054                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
2055                         mlx5e_enable_vlan_filter(priv);
2056                 else
2057                         mlx5e_disable_vlan_filter(priv);
2058         }
2059
2060         if ((changes & NETIF_F_HW_TC) && !(features & NETIF_F_HW_TC) &&
2061             mlx5e_tc_num_filters(priv)) {
2062                 netdev_err(netdev,
2063                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2064                 return -EINVAL;
2065         }
2066
2067         return err;
2068 }
2069
2070 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2071 {
2072         struct mlx5e_priv *priv = netdev_priv(netdev);
2073         struct mlx5_core_dev *mdev = priv->mdev;
2074         bool was_opened;
2075         int max_mtu;
2076         int err = 0;
2077
2078         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2079
2080         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2081
2082         if (new_mtu > max_mtu) {
2083                 netdev_err(netdev,
2084                            "%s: Bad MTU (%d) > (%d) Max\n",
2085                            __func__, new_mtu, max_mtu);
2086                 return -EINVAL;
2087         }
2088
2089         mutex_lock(&priv->state_lock);
2090
2091         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2092         if (was_opened)
2093                 mlx5e_close_locked(netdev);
2094
2095         netdev->mtu = new_mtu;
2096
2097         if (was_opened)
2098                 err = mlx5e_open_locked(netdev);
2099
2100         mutex_unlock(&priv->state_lock);
2101
2102         return err;
2103 }
2104
2105 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2106 {
2107         switch (cmd) {
2108         case SIOCSHWTSTAMP:
2109                 return mlx5e_hwstamp_set(dev, ifr);
2110         case SIOCGHWTSTAMP:
2111                 return mlx5e_hwstamp_get(dev, ifr);
2112         default:
2113                 return -EOPNOTSUPP;
2114         }
2115 }
2116
2117 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2118 {
2119         struct mlx5e_priv *priv = netdev_priv(dev);
2120         struct mlx5_core_dev *mdev = priv->mdev;
2121
2122         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2123 }
2124
2125 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2126 {
2127         struct mlx5e_priv *priv = netdev_priv(dev);
2128         struct mlx5_core_dev *mdev = priv->mdev;
2129
2130         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2131                                            vlan, qos);
2132 }
2133
2134 static int mlx5_vport_link2ifla(u8 esw_link)
2135 {
2136         switch (esw_link) {
2137         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2138                 return IFLA_VF_LINK_STATE_DISABLE;
2139         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2140                 return IFLA_VF_LINK_STATE_ENABLE;
2141         }
2142         return IFLA_VF_LINK_STATE_AUTO;
2143 }
2144
2145 static int mlx5_ifla_link2vport(u8 ifla_link)
2146 {
2147         switch (ifla_link) {
2148         case IFLA_VF_LINK_STATE_DISABLE:
2149                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2150         case IFLA_VF_LINK_STATE_ENABLE:
2151                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2152         }
2153         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2154 }
2155
2156 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2157                                    int link_state)
2158 {
2159         struct mlx5e_priv *priv = netdev_priv(dev);
2160         struct mlx5_core_dev *mdev = priv->mdev;
2161
2162         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2163                                             mlx5_ifla_link2vport(link_state));
2164 }
2165
2166 static int mlx5e_get_vf_config(struct net_device *dev,
2167                                int vf, struct ifla_vf_info *ivi)
2168 {
2169         struct mlx5e_priv *priv = netdev_priv(dev);
2170         struct mlx5_core_dev *mdev = priv->mdev;
2171         int err;
2172
2173         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2174         if (err)
2175                 return err;
2176         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2177         return 0;
2178 }
2179
2180 static int mlx5e_get_vf_stats(struct net_device *dev,
2181                               int vf, struct ifla_vf_stats *vf_stats)
2182 {
2183         struct mlx5e_priv *priv = netdev_priv(dev);
2184         struct mlx5_core_dev *mdev = priv->mdev;
2185
2186         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2187                                             vf_stats);
2188 }
2189
2190 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2191                                  sa_family_t sa_family, __be16 port)
2192 {
2193         struct mlx5e_priv *priv = netdev_priv(netdev);
2194
2195         if (!mlx5e_vxlan_allowed(priv->mdev))
2196                 return;
2197
2198         mlx5e_vxlan_add_port(priv, be16_to_cpu(port));
2199 }
2200
2201 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2202                                  sa_family_t sa_family, __be16 port)
2203 {
2204         struct mlx5e_priv *priv = netdev_priv(netdev);
2205
2206         if (!mlx5e_vxlan_allowed(priv->mdev))
2207                 return;
2208
2209         mlx5e_vxlan_del_port(priv, be16_to_cpu(port));
2210 }
2211
2212 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2213                                                     struct sk_buff *skb,
2214                                                     netdev_features_t features)
2215 {
2216         struct udphdr *udph;
2217         u16 proto;
2218         u16 port = 0;
2219
2220         switch (vlan_get_protocol(skb)) {
2221         case htons(ETH_P_IP):
2222                 proto = ip_hdr(skb)->protocol;
2223                 break;
2224         case htons(ETH_P_IPV6):
2225                 proto = ipv6_hdr(skb)->nexthdr;
2226                 break;
2227         default:
2228                 goto out;
2229         }
2230
2231         if (proto == IPPROTO_UDP) {
2232                 udph = udp_hdr(skb);
2233                 port = be16_to_cpu(udph->dest);
2234         }
2235
2236         /* Verify if UDP port is being offloaded by HW */
2237         if (port && mlx5e_vxlan_lookup_port(priv, port))
2238                 return features;
2239
2240 out:
2241         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2242         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2243 }
2244
2245 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2246                                               struct net_device *netdev,
2247                                               netdev_features_t features)
2248 {
2249         struct mlx5e_priv *priv = netdev_priv(netdev);
2250
2251         features = vlan_features_check(skb, features);
2252         features = vxlan_features_check(skb, features);
2253
2254         /* Validate if the tunneled packet is being offloaded by HW */
2255         if (skb->encapsulation &&
2256             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2257                 return mlx5e_vxlan_features_check(priv, skb, features);
2258
2259         return features;
2260 }
2261
2262 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2263         .ndo_open                = mlx5e_open,
2264         .ndo_stop                = mlx5e_close,
2265         .ndo_start_xmit          = mlx5e_xmit,
2266         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2267         .ndo_select_queue        = mlx5e_select_queue,
2268         .ndo_get_stats64         = mlx5e_get_stats,
2269         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2270         .ndo_set_mac_address     = mlx5e_set_mac,
2271         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2272         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2273         .ndo_set_features        = mlx5e_set_features,
2274         .ndo_change_mtu          = mlx5e_change_mtu,
2275         .ndo_do_ioctl            = mlx5e_ioctl,
2276 };
2277
2278 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2279         .ndo_open                = mlx5e_open,
2280         .ndo_stop                = mlx5e_close,
2281         .ndo_start_xmit          = mlx5e_xmit,
2282         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2283         .ndo_select_queue        = mlx5e_select_queue,
2284         .ndo_get_stats64         = mlx5e_get_stats,
2285         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2286         .ndo_set_mac_address     = mlx5e_set_mac,
2287         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2288         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2289         .ndo_set_features        = mlx5e_set_features,
2290         .ndo_change_mtu          = mlx5e_change_mtu,
2291         .ndo_do_ioctl            = mlx5e_ioctl,
2292         .ndo_add_vxlan_port      = mlx5e_add_vxlan_port,
2293         .ndo_del_vxlan_port      = mlx5e_del_vxlan_port,
2294         .ndo_features_check      = mlx5e_features_check,
2295         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2296         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2297         .ndo_get_vf_config       = mlx5e_get_vf_config,
2298         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2299         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2300 };
2301
2302 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2303 {
2304         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2305                 return -ENOTSUPP;
2306         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2307             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2308             !MLX5_CAP_ETH(mdev, csum_cap) ||
2309             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2310             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2311             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2312             MLX5_CAP_FLOWTABLE(mdev,
2313                                flow_table_properties_nic_receive.max_ft_level)
2314                                < 3) {
2315                 mlx5_core_warn(mdev,
2316                                "Not creating net device, some required device capabilities are missing\n");
2317                 return -ENOTSUPP;
2318         }
2319         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2320                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2321         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2322                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2323
2324         return 0;
2325 }
2326
2327 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2328 {
2329         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2330
2331         return bf_buf_size -
2332                sizeof(struct mlx5e_tx_wqe) +
2333                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2334 }
2335
2336 #ifdef CONFIG_MLX5_CORE_EN_DCB
2337 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2338 {
2339         int i;
2340
2341         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2342         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2343                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2344                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2345                 priv->params.ets.prio_tc[i] = i;
2346         }
2347
2348         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2349         priv->params.ets.prio_tc[0] = 1;
2350         priv->params.ets.prio_tc[1] = 0;
2351 }
2352 #endif
2353
2354 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2355                                    u32 *indirection_rqt, int len,
2356                                    int num_channels)
2357 {
2358         int node = mdev->priv.numa_node;
2359         int node_num_of_cores;
2360         int i;
2361
2362         if (node == -1)
2363                 node = first_online_node;
2364
2365         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2366
2367         if (node_num_of_cores)
2368                 num_channels = min_t(int, num_channels, node_num_of_cores);
2369
2370         for (i = 0; i < len; i++)
2371                 indirection_rqt[i] = i % num_channels;
2372 }
2373
2374 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2375                                     struct net_device *netdev,
2376                                     int num_channels)
2377 {
2378         struct mlx5e_priv *priv = netdev_priv(netdev);
2379
2380         priv->params.log_sq_size           =
2381                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2382         priv->params.rq_wq_type = MLX5_CAP_GEN(mdev, striding_rq) ?
2383                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2384                 MLX5_WQ_TYPE_LINKED_LIST;
2385
2386         switch (priv->params.rq_wq_type) {
2387         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2388                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2389                 priv->params.lro_en = true;
2390                 break;
2391         default: /* MLX5_WQ_TYPE_LINKED_LIST */
2392                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2393         }
2394
2395         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2396                                             BIT(priv->params.log_rq_size));
2397         priv->params.rx_cq_moderation_usec =
2398                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2399         priv->params.rx_cq_moderation_pkts =
2400                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2401         priv->params.tx_cq_moderation_usec =
2402                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2403         priv->params.tx_cq_moderation_pkts =
2404                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2405         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
2406         priv->params.num_tc                = 1;
2407         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2408
2409         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2410                             sizeof(priv->params.toeplitz_hash_key));
2411
2412         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2413                                       MLX5E_INDIR_RQT_SIZE, num_channels);
2414
2415         priv->params.lro_wqe_sz            =
2416                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2417
2418         priv->mdev                         = mdev;
2419         priv->netdev                       = netdev;
2420         priv->params.num_channels          = num_channels;
2421
2422 #ifdef CONFIG_MLX5_CORE_EN_DCB
2423         mlx5e_ets_init(priv);
2424 #endif
2425
2426         mutex_init(&priv->state_lock);
2427
2428         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2429         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2430         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2431 }
2432
2433 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2434 {
2435         struct mlx5e_priv *priv = netdev_priv(netdev);
2436
2437         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2438         if (is_zero_ether_addr(netdev->dev_addr) &&
2439             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2440                 eth_hw_addr_random(netdev);
2441                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2442         }
2443 }
2444
2445 static void mlx5e_build_netdev(struct net_device *netdev)
2446 {
2447         struct mlx5e_priv *priv = netdev_priv(netdev);
2448         struct mlx5_core_dev *mdev = priv->mdev;
2449
2450         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2451
2452         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2453                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2454 #ifdef CONFIG_MLX5_CORE_EN_DCB
2455                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2456 #endif
2457         } else {
2458                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2459         }
2460
2461         netdev->watchdog_timeo    = 15 * HZ;
2462
2463         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
2464
2465         netdev->vlan_features    |= NETIF_F_SG;
2466         netdev->vlan_features    |= NETIF_F_IP_CSUM;
2467         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
2468         netdev->vlan_features    |= NETIF_F_GRO;
2469         netdev->vlan_features    |= NETIF_F_TSO;
2470         netdev->vlan_features    |= NETIF_F_TSO6;
2471         netdev->vlan_features    |= NETIF_F_RXCSUM;
2472         netdev->vlan_features    |= NETIF_F_RXHASH;
2473
2474         if (!!MLX5_CAP_ETH(mdev, lro_cap))
2475                 netdev->vlan_features    |= NETIF_F_LRO;
2476
2477         netdev->hw_features       = netdev->vlan_features;
2478         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
2479         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
2480         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
2481
2482         if (mlx5e_vxlan_allowed(mdev)) {
2483                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL;
2484                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2485                 netdev->hw_enc_features |= NETIF_F_RXCSUM;
2486                 netdev->hw_enc_features |= NETIF_F_TSO;
2487                 netdev->hw_enc_features |= NETIF_F_TSO6;
2488                 netdev->hw_enc_features |= NETIF_F_RXHASH;
2489                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2490         }
2491
2492         netdev->features          = netdev->hw_features;
2493         if (!priv->params.lro_en)
2494                 netdev->features  &= ~NETIF_F_LRO;
2495
2496 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2497         if (FT_CAP(flow_modify_en) &&
2498             FT_CAP(modify_root) &&
2499             FT_CAP(identified_miss_table_mode) &&
2500             FT_CAP(flow_table_modify))
2501                 priv->netdev->hw_features      |= NETIF_F_HW_TC;
2502
2503         netdev->features         |= NETIF_F_HIGHDMA;
2504
2505         netdev->priv_flags       |= IFF_UNICAST_FLT;
2506
2507         mlx5e_set_netdev_dev_addr(netdev);
2508 }
2509
2510 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2511                              struct mlx5_core_mkey *mkey)
2512 {
2513         struct mlx5_core_dev *mdev = priv->mdev;
2514         struct mlx5_create_mkey_mbox_in *in;
2515         int err;
2516
2517         in = mlx5_vzalloc(sizeof(*in));
2518         if (!in)
2519                 return -ENOMEM;
2520
2521         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2522                         MLX5_PERM_LOCAL_READ  |
2523                         MLX5_ACCESS_MODE_PA;
2524         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2525         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2526
2527         err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
2528                                     NULL);
2529
2530         kvfree(in);
2531
2532         return err;
2533 }
2534
2535 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2536 {
2537         struct mlx5_core_dev *mdev = priv->mdev;
2538         int err;
2539
2540         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2541         if (err) {
2542                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2543                 priv->q_counter = 0;
2544         }
2545 }
2546
2547 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2548 {
2549         if (!priv->q_counter)
2550                 return;
2551
2552         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2553 }
2554
2555 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2556 {
2557         struct net_device *netdev;
2558         struct mlx5e_priv *priv;
2559         int nch = mlx5e_get_max_num_channels(mdev);
2560         int err;
2561
2562         if (mlx5e_check_required_hca_cap(mdev))
2563                 return NULL;
2564
2565         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2566                                     nch * MLX5E_MAX_NUM_TC,
2567                                     nch);
2568         if (!netdev) {
2569                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2570                 return NULL;
2571         }
2572
2573         mlx5e_build_netdev_priv(mdev, netdev, nch);
2574         mlx5e_build_netdev(netdev);
2575
2576         netif_carrier_off(netdev);
2577
2578         priv = netdev_priv(netdev);
2579
2580         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
2581         if (err) {
2582                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2583                 goto err_free_netdev;
2584         }
2585
2586         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2587         if (err) {
2588                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2589                 goto err_unmap_free_uar;
2590         }
2591
2592         err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
2593         if (err) {
2594                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2595                 goto err_dealloc_pd;
2596         }
2597
2598         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
2599         if (err) {
2600                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2601                 goto err_dealloc_transport_domain;
2602         }
2603
2604         err = mlx5e_create_tises(priv);
2605         if (err) {
2606                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2607                 goto err_destroy_mkey;
2608         }
2609
2610         err = mlx5e_open_drop_rq(priv);
2611         if (err) {
2612                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2613                 goto err_destroy_tises;
2614         }
2615
2616         err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
2617         if (err) {
2618                 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
2619                 goto err_close_drop_rq;
2620         }
2621
2622         err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2623         if (err) {
2624                 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2625                 goto err_destroy_rqt_indir;
2626         }
2627
2628         err = mlx5e_create_tirs(priv);
2629         if (err) {
2630                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2631                 goto err_destroy_rqt_single;
2632         }
2633
2634         err = mlx5e_create_flow_tables(priv);
2635         if (err) {
2636                 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2637                 goto err_destroy_tirs;
2638         }
2639
2640         mlx5e_create_q_counter(priv);
2641
2642         mlx5e_init_eth_addr(priv);
2643
2644         mlx5e_vxlan_init(priv);
2645
2646         err = mlx5e_tc_init(priv);
2647         if (err)
2648                 goto err_dealloc_q_counters;
2649
2650 #ifdef CONFIG_MLX5_CORE_EN_DCB
2651         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2652 #endif
2653
2654         err = register_netdev(netdev);
2655         if (err) {
2656                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2657                 goto err_tc_cleanup;
2658         }
2659
2660         if (mlx5e_vxlan_allowed(mdev))
2661                 vxlan_get_rx_port(netdev);
2662
2663         mlx5e_enable_async_events(priv);
2664         schedule_work(&priv->set_rx_mode_work);
2665
2666         return priv;
2667
2668 err_tc_cleanup:
2669         mlx5e_tc_cleanup(priv);
2670
2671 err_dealloc_q_counters:
2672         mlx5e_destroy_q_counter(priv);
2673         mlx5e_destroy_flow_tables(priv);
2674
2675 err_destroy_tirs:
2676         mlx5e_destroy_tirs(priv);
2677
2678 err_destroy_rqt_single:
2679         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2680
2681 err_destroy_rqt_indir:
2682         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2683
2684 err_close_drop_rq:
2685         mlx5e_close_drop_rq(priv);
2686
2687 err_destroy_tises:
2688         mlx5e_destroy_tises(priv);
2689
2690 err_destroy_mkey:
2691         mlx5_core_destroy_mkey(mdev, &priv->mkey);
2692
2693 err_dealloc_transport_domain:
2694         mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
2695
2696 err_dealloc_pd:
2697         mlx5_core_dealloc_pd(mdev, priv->pdn);
2698
2699 err_unmap_free_uar:
2700         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2701
2702 err_free_netdev:
2703         free_netdev(netdev);
2704
2705         return NULL;
2706 }
2707
2708 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2709 {
2710         struct mlx5e_priv *priv = vpriv;
2711         struct net_device *netdev = priv->netdev;
2712
2713         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2714
2715         schedule_work(&priv->set_rx_mode_work);
2716         mlx5e_disable_async_events(priv);
2717         flush_scheduled_work();
2718         unregister_netdev(netdev);
2719         mlx5e_tc_cleanup(priv);
2720         mlx5e_vxlan_cleanup(priv);
2721         mlx5e_destroy_q_counter(priv);
2722         mlx5e_destroy_flow_tables(priv);
2723         mlx5e_destroy_tirs(priv);
2724         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2725         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2726         mlx5e_close_drop_rq(priv);
2727         mlx5e_destroy_tises(priv);
2728         mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
2729         mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
2730         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2731         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2732         free_netdev(netdev);
2733 }
2734
2735 static void *mlx5e_get_netdev(void *vpriv)
2736 {
2737         struct mlx5e_priv *priv = vpriv;
2738
2739         return priv->netdev;
2740 }
2741
2742 static struct mlx5_interface mlx5e_interface = {
2743         .add       = mlx5e_create_netdev,
2744         .remove    = mlx5e_destroy_netdev,
2745         .event     = mlx5e_async_event,
2746         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
2747         .get_dev   = mlx5e_get_netdev,
2748 };
2749
2750 void mlx5e_init(void)
2751 {
2752         mlx5_register_interface(&mlx5e_interface);
2753 }
2754
2755 void mlx5e_cleanup(void)
2756 {
2757         mlx5_unregister_interface(&mlx5e_interface);
2758 }