drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 struct mlx5e_rq_param {
  43         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  44         struct mlx5_wq_param       wq;
  45 };
  46
  47 struct mlx5e_sq_param {
  48         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  49         struct mlx5_wq_param       wq;
  50         u16                        max_inline;
  51 };
  52
  53 struct mlx5e_cq_param {
  54         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  55         struct mlx5_wq_param       wq;
  56         u16                        eq_ix;
  57 };
  58
  59 struct mlx5e_channel_param {
  60         struct mlx5e_rq_param      rq;
  61         struct mlx5e_sq_param      sq;
  62         struct mlx5e_cq_param      rx_cq;
  63         struct mlx5e_cq_param      tx_cq;
  64 };
  65
  66 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  67 {
  68         struct mlx5_core_dev *mdev = priv->mdev;
  69         u8 port_state;
  70
  71         port_state = mlx5_query_vport_state(mdev,
  72                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  73
  74         if (port_state == VPORT_STATE_UP)
  75                 netif_carrier_on(priv->netdev);
  76         else
  77                 netif_carrier_off(priv->netdev);
  78 }
  79
  80 static void mlx5e_update_carrier_work(struct work_struct *work)
  81 {
  82         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  83                                                update_carrier_work);
  84
  85         mutex_lock(&priv->state_lock);
  86         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  87                 mlx5e_update_carrier(priv);
  88         mutex_unlock(&priv->state_lock);
  89 }
  90
  91 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
  92 {
  93         struct mlx5_core_dev *mdev = priv->mdev;
  94         struct mlx5e_pport_stats *s = &priv->stats.pport;
  95         u32 *in;
  96         u32 *out;
  97         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
  98
  99         in  = mlx5_vzalloc(sz);
 100         out = mlx5_vzalloc(sz);
 101         if (!in || !out)
 102                 goto free_out;
 103
 104         MLX5_SET(ppcnt_reg, in, local_port, 1);
 105
 106         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 107         mlx5_core_access_reg(mdev, in, sz, out,
 108                              sz, MLX5_REG_PPCNT, 0, 0);
 109         memcpy(s->IEEE_802_3_counters,
 110                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 111                sizeof(s->IEEE_802_3_counters));
 112
 113         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 114         mlx5_core_access_reg(mdev, in, sz, out,
 115                              sz, MLX5_REG_PPCNT, 0, 0);
 116         memcpy(s->RFC_2863_counters,
 117                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 118                sizeof(s->RFC_2863_counters));
 119
 120         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 121         mlx5_core_access_reg(mdev, in, sz, out,
 122                              sz, MLX5_REG_PPCNT, 0, 0);
 123         memcpy(s->RFC_2819_counters,
 124                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 125                sizeof(s->RFC_2819_counters));
 126
 127 free_out:
 128         kvfree(in);
 129         kvfree(out);
 130 }
 131
 132 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 133 {
 134         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 135
 136         if (!priv->q_counter)
 137                 return;
 138
 139         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 140                                       &qcnt->rx_out_of_buffer);
 141 }
 142
 143 void mlx5e_update_stats(struct mlx5e_priv *priv)
 144 {
 145         struct mlx5_core_dev *mdev = priv->mdev;
 146         struct mlx5e_vport_stats *s = &priv->stats.vport;
 147         struct mlx5e_rq_stats *rq_stats;
 148         struct mlx5e_sq_stats *sq_stats;
 149         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 150         u32 *out;
 151         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 152         u64 tx_offload_none;
 153         int i, j;
 154
 155         out = mlx5_vzalloc(outlen);
 156         if (!out)
 157                 return;
 158
 159         /* Collect firts the SW counters and then HW for consistency */
 160         s->rx_packets           = 0;
 161         s->rx_bytes             = 0;
 162         s->tx_packets           = 0;
 163         s->tx_bytes             = 0;
 164         s->tso_packets          = 0;
 165         s->tso_bytes            = 0;
 166         s->tso_inner_packets    = 0;
 167         s->tso_inner_bytes      = 0;
 168         s->tx_queue_stopped     = 0;
 169         s->tx_queue_wake        = 0;
 170         s->tx_queue_dropped     = 0;
 171         s->tx_csum_inner        = 0;
 172         tx_offload_none         = 0;
 173         s->lro_packets          = 0;
 174         s->lro_bytes            = 0;
 175         s->rx_csum_none         = 0;
 176         s->rx_csum_sw           = 0;
 177         s->rx_wqe_err           = 0;
 178         for (i = 0; i < priv->params.num_channels; i++) {
 179                 rq_stats = &priv->channel[i]->rq.stats;
 180
 181                 s->rx_packets   += rq_stats->packets;
 182                 s->rx_bytes     += rq_stats->bytes;
 183                 s->lro_packets  += rq_stats->lro_packets;
 184                 s->lro_bytes    += rq_stats->lro_bytes;
 185                 s->rx_csum_none += rq_stats->csum_none;
 186                 s->rx_csum_sw   += rq_stats->csum_sw;
 187                 s->rx_wqe_err   += rq_stats->wqe_err;
 188
 189                 for (j = 0; j < priv->params.num_tc; j++) {
 190                         sq_stats = &priv->channel[i]->sq[j].stats;
 191
 192                         s->tx_packets           += sq_stats->packets;
 193                         s->tx_bytes             += sq_stats->bytes;
 194                         s->tso_packets          += sq_stats->tso_packets;
 195                         s->tso_bytes            += sq_stats->tso_bytes;
 196                         s->tso_inner_packets    += sq_stats->tso_inner_packets;
 197                         s->tso_inner_bytes      += sq_stats->tso_inner_bytes;
 198                         s->tx_queue_stopped     += sq_stats->stopped;
 199                         s->tx_queue_wake        += sq_stats->wake;
 200                         s->tx_queue_dropped     += sq_stats->dropped;
 201                         s->tx_csum_inner        += sq_stats->csum_offload_inner;
 202                         tx_offload_none         += sq_stats->csum_offload_none;
 203                 }
 204         }
 205
 206         /* HW counters */
 207         memset(in, 0, sizeof(in));
 208
 209         MLX5_SET(query_vport_counter_in, in, opcode,
 210                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 211         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 212         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 213
 214         memset(out, 0, outlen);
 215
 216         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 217                 goto free_out;
 218
 219 #define MLX5_GET_CTR(p, x) \
 220         MLX5_GET64(query_vport_counter_out, p, x)
 221
 222         s->rx_error_packets     =
 223                 MLX5_GET_CTR(out, received_errors.packets);
 224         s->rx_error_bytes       =
 225                 MLX5_GET_CTR(out, received_errors.octets);
 226         s->tx_error_packets     =
 227                 MLX5_GET_CTR(out, transmit_errors.packets);
 228         s->tx_error_bytes       =
 229                 MLX5_GET_CTR(out, transmit_errors.octets);
 230
 231         s->rx_unicast_packets   =
 232                 MLX5_GET_CTR(out, received_eth_unicast.packets);
 233         s->rx_unicast_bytes     =
 234                 MLX5_GET_CTR(out, received_eth_unicast.octets);
 235         s->tx_unicast_packets   =
 236                 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 237         s->tx_unicast_bytes     =
 238                 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 239
 240         s->rx_multicast_packets =
 241                 MLX5_GET_CTR(out, received_eth_multicast.packets);
 242         s->rx_multicast_bytes   =
 243                 MLX5_GET_CTR(out, received_eth_multicast.octets);
 244         s->tx_multicast_packets =
 245                 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 246         s->tx_multicast_bytes   =
 247                 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 248
 249         s->rx_broadcast_packets =
 250                 MLX5_GET_CTR(out, received_eth_broadcast.packets);
 251         s->rx_broadcast_bytes   =
 252                 MLX5_GET_CTR(out, received_eth_broadcast.octets);
 253         s->tx_broadcast_packets =
 254                 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 255         s->tx_broadcast_bytes   =
 256                 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 257
 258         /* Update calculated offload counters */
 259         s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
 260         s->rx_csum_good    = s->rx_packets - s->rx_csum_none -
 261                                s->rx_csum_sw;
 262
 263         mlx5e_update_pport_counters(priv);
 264         mlx5e_update_q_counter(priv);
 265
 266 free_out:
 267         kvfree(out);
 268 }
 269
 270 static void mlx5e_update_stats_work(struct work_struct *work)
 271 {
 272         struct delayed_work *dwork = to_delayed_work(work);
 273         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 274                                                update_stats_work);
 275         mutex_lock(&priv->state_lock);
 276         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 277                 mlx5e_update_stats(priv);
 278                 schedule_delayed_work(dwork,
 279                                       msecs_to_jiffies(
 280                                               MLX5E_UPDATE_STATS_INTERVAL));
 281         }
 282         mutex_unlock(&priv->state_lock);
 283 }
 284
 285 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 286                               enum mlx5_dev_event event, unsigned long param)
 287 {
 288         struct mlx5e_priv *priv = vpriv;
 289
 290         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 291                 return;
 292
 293         switch (event) {
 294         case MLX5_DEV_EVENT_PORT_UP:
 295         case MLX5_DEV_EVENT_PORT_DOWN:
 296                 schedule_work(&priv->update_carrier_work);
 297                 break;
 298
 299         default:
 300                 break;
 301         }
 302 }
 303
 304 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 305 {
 306         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 307 }
 308
 309 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 310 {
 311         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 312         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 313 }
 314
 315 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 316 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 317
 318 static int mlx5e_create_rq(struct mlx5e_channel *c,
 319                            struct mlx5e_rq_param *param,
 320                            struct mlx5e_rq *rq)
 321 {
 322         struct mlx5e_priv *priv = c->priv;
 323         struct mlx5_core_dev *mdev = priv->mdev;
 324         void *rqc = param->rqc;
 325         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 326         int wq_sz;
 327         int err;
 328         int i;
 329
 330         param->wq.db_numa_node = cpu_to_node(c->cpu);
 331
 332         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 333                                 &rq->wq_ctrl);
 334         if (err)
 335                 return err;
 336
 337         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 338
 339         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 340         rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 341                                cpu_to_node(c->cpu));
 342         if (!rq->skb) {
 343                 err = -ENOMEM;
 344                 goto err_rq_wq_destroy;
 345         }
 346
 347         rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
 348                                              MLX5E_SW2HW_MTU(priv->netdev->mtu);
 349         rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
 350
 351         for (i = 0; i < wq_sz; i++) {
 352                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 353                 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 354
 355                 wqe->data.lkey       = c->mkey_be;
 356                 wqe->data.byte_count =
 357                         cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 358         }
 359
 360         rq->pdev    = c->pdev;
 361         rq->netdev  = c->netdev;
 362         rq->tstamp  = &priv->tstamp;
 363         rq->channel = c;
 364         rq->ix      = c->ix;
 365         rq->priv    = c->priv;
 366
 367         return 0;
 368
 369 err_rq_wq_destroy:
 370         mlx5_wq_destroy(&rq->wq_ctrl);
 371
 372         return err;
 373 }
 374
 375 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 376 {
 377         kfree(rq->skb);
 378         mlx5_wq_destroy(&rq->wq_ctrl);
 379 }
 380
 381 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 382 {
 383         struct mlx5e_priv *priv = rq->priv;
 384         struct mlx5_core_dev *mdev = priv->mdev;
 385
 386         void *in;
 387         void *rqc;
 388         void *wq;
 389         int inlen;
 390         int err;
 391
 392         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 393                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 394         in = mlx5_vzalloc(inlen);
 395         if (!in)
 396                 return -ENOMEM;
 397
 398         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 399         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 400
 401         memcpy(rqc, param->rqc, sizeof(param->rqc));
 402
 403         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 404         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 405         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 406         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 407                                                 MLX5_ADAPTER_PAGE_SHIFT);
 408         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 409
 410         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 411                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 412
 413         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 414
 415         kvfree(in);
 416
 417         return err;
 418 }
 419
 420 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 421 {
 422         struct mlx5e_channel *c = rq->channel;
 423         struct mlx5e_priv *priv = c->priv;
 424         struct mlx5_core_dev *mdev = priv->mdev;
 425
 426         void *in;
 427         void *rqc;
 428         int inlen;
 429         int err;
 430
 431         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 432         in = mlx5_vzalloc(inlen);
 433         if (!in)
 434                 return -ENOMEM;
 435
 436         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 437
 438         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 439         MLX5_SET(rqc, rqc, state, next_state);
 440
 441         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 442
 443         kvfree(in);
 444
 445         return err;
 446 }
 447
 448 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 449 {
 450         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 451 }
 452
 453 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 454 {
 455         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 456         struct mlx5e_channel *c = rq->channel;
 457         struct mlx5e_priv *priv = c->priv;
 458         struct mlx5_wq_ll *wq = &rq->wq;
 459
 460         while (time_before(jiffies, exp_time)) {
 461                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 462                         return 0;
 463
 464                 msleep(20);
 465         }
 466
 467         return -ETIMEDOUT;
 468 }
 469
 470 static int mlx5e_open_rq(struct mlx5e_channel *c,
 471                          struct mlx5e_rq_param *param,
 472                          struct mlx5e_rq *rq)
 473 {
 474         int err;
 475
 476         err = mlx5e_create_rq(c, param, rq);
 477         if (err)
 478                 return err;
 479
 480         err = mlx5e_enable_rq(rq, param);
 481         if (err)
 482                 goto err_destroy_rq;
 483
 484         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 485         if (err)
 486                 goto err_disable_rq;
 487
 488         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 489         mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
 490
 491         return 0;
 492
 493 err_disable_rq:
 494         mlx5e_disable_rq(rq);
 495 err_destroy_rq:
 496         mlx5e_destroy_rq(rq);
 497
 498         return err;
 499 }
 500
 501 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 502 {
 503         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 504         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 505
 506         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 507         while (!mlx5_wq_ll_is_empty(&rq->wq))
 508                 msleep(20);
 509
 510         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 511         napi_synchronize(&rq->channel->napi);
 512
 513         mlx5e_disable_rq(rq);
 514         mlx5e_destroy_rq(rq);
 515 }
 516
 517 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 518 {
 519         kfree(sq->wqe_info);
 520         kfree(sq->dma_fifo);
 521         kfree(sq->skb);
 522 }
 523
 524 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 525 {
 526         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 527         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 528
 529         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 530         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 531                                     numa);
 532         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 533                                     numa);
 534
 535         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 536                 mlx5e_free_sq_db(sq);
 537                 return -ENOMEM;
 538         }
 539
 540         sq->dma_fifo_mask = df_sz - 1;
 541
 542         return 0;
 543 }
 544
 545 static int mlx5e_create_sq(struct mlx5e_channel *c,
 546                            int tc,
 547                            struct mlx5e_sq_param *param,
 548                            struct mlx5e_sq *sq)
 549 {
 550         struct mlx5e_priv *priv = c->priv;
 551         struct mlx5_core_dev *mdev = priv->mdev;
 552
 553         void *sqc = param->sqc;
 554         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 555         int txq_ix;
 556         int err;
 557
 558         err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
 559         if (err)
 560                 return err;
 561
 562         param->wq.db_numa_node = cpu_to_node(c->cpu);
 563
 564         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 565                                  &sq->wq_ctrl);
 566         if (err)
 567                 goto err_unmap_free_uar;
 568
 569         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 570         if (sq->uar.bf_map) {
 571                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 572                 sq->uar_map = sq->uar.bf_map;
 573         } else {
 574                 sq->uar_map = sq->uar.map;
 575         }
 576         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 577         sq->max_inline  = param->max_inline;
 578
 579         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 580         if (err)
 581                 goto err_sq_wq_destroy;
 582
 583         txq_ix = c->ix + tc * priv->params.num_channels;
 584         sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 585
 586         sq->pdev      = c->pdev;
 587         sq->tstamp    = &priv->tstamp;
 588         sq->mkey_be   = c->mkey_be;
 589         sq->channel   = c;
 590         sq->tc        = tc;
 591         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 592         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 593         priv->txq_to_sq_map[txq_ix] = sq;
 594
 595         return 0;
 596
 597 err_sq_wq_destroy:
 598         mlx5_wq_destroy(&sq->wq_ctrl);
 599
 600 err_unmap_free_uar:
 601         mlx5_unmap_free_uar(mdev, &sq->uar);
 602
 603         return err;
 604 }
 605
 606 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 607 {
 608         struct mlx5e_channel *c = sq->channel;
 609         struct mlx5e_priv *priv = c->priv;
 610
 611         mlx5e_free_sq_db(sq);
 612         mlx5_wq_destroy(&sq->wq_ctrl);
 613         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 614 }
 615
 616 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 617 {
 618         struct mlx5e_channel *c = sq->channel;
 619         struct mlx5e_priv *priv = c->priv;
 620         struct mlx5_core_dev *mdev = priv->mdev;
 621
 622         void *in;
 623         void *sqc;
 624         void *wq;
 625         int inlen;
 626         int err;
 627
 628         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 629                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 630         in = mlx5_vzalloc(inlen);
 631         if (!in)
 632                 return -ENOMEM;
 633
 634         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 635         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 636
 637         memcpy(sqc, param->sqc, sizeof(param->sqc));
 638
 639         MLX5_SET(sqc,  sqc, tis_num_0,          priv->tisn[sq->tc]);
 640         MLX5_SET(sqc,  sqc, cqn,                c->sq[sq->tc].cq.mcq.cqn);
 641         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 642         MLX5_SET(sqc,  sqc, tis_lst_sz,         1);
 643         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 644
 645         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 646         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 647         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 648                                           MLX5_ADAPTER_PAGE_SHIFT);
 649         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 650
 651         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 652                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 653
 654         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 655
 656         kvfree(in);
 657
 658         return err;
 659 }
 660
 661 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 662 {
 663         struct mlx5e_channel *c = sq->channel;
 664         struct mlx5e_priv *priv = c->priv;
 665         struct mlx5_core_dev *mdev = priv->mdev;
 666
 667         void *in;
 668         void *sqc;
 669         int inlen;
 670         int err;
 671
 672         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 673         in = mlx5_vzalloc(inlen);
 674         if (!in)
 675                 return -ENOMEM;
 676
 677         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 678
 679         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 680         MLX5_SET(sqc, sqc, state, next_state);
 681
 682         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 683
 684         kvfree(in);
 685
 686         return err;
 687 }
 688
 689 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 690 {
 691         struct mlx5e_channel *c = sq->channel;
 692         struct mlx5e_priv *priv = c->priv;
 693         struct mlx5_core_dev *mdev = priv->mdev;
 694
 695         mlx5_core_destroy_sq(mdev, sq->sqn);
 696 }
 697
 698 static int mlx5e_open_sq(struct mlx5e_channel *c,
 699                          int tc,
 700                          struct mlx5e_sq_param *param,
 701                          struct mlx5e_sq *sq)
 702 {
 703         int err;
 704
 705         err = mlx5e_create_sq(c, tc, param, sq);
 706         if (err)
 707                 return err;
 708
 709         err = mlx5e_enable_sq(sq, param);
 710         if (err)
 711                 goto err_destroy_sq;
 712
 713         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 714         if (err)
 715                 goto err_disable_sq;
 716
 717         set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 718         netdev_tx_reset_queue(sq->txq);
 719         netif_tx_start_queue(sq->txq);
 720
 721         return 0;
 722
 723 err_disable_sq:
 724         mlx5e_disable_sq(sq);
 725 err_destroy_sq:
 726         mlx5e_destroy_sq(sq);
 727
 728         return err;
 729 }
 730
 731 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 732 {
 733         __netif_tx_lock_bh(txq);
 734         netif_tx_stop_queue(txq);
 735         __netif_tx_unlock_bh(txq);
 736 }
 737
 738 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 739 {
 740         clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 741         napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
 742         netif_tx_disable_queue(sq->txq);
 743
 744         /* ensure hw is notified of all pending wqes */
 745         if (mlx5e_sq_has_room_for(sq, 1))
 746                 mlx5e_send_nop(sq, true);
 747
 748         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 749         while (sq->cc != sq->pc) /* wait till sq is empty */
 750                 msleep(20);
 751
 752         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 753         napi_synchronize(&sq->channel->napi);
 754
 755         mlx5e_disable_sq(sq);
 756         mlx5e_destroy_sq(sq);
 757 }
 758
 759 static int mlx5e_create_cq(struct mlx5e_channel *c,
 760                            struct mlx5e_cq_param *param,
 761                            struct mlx5e_cq *cq)
 762 {
 763         struct mlx5e_priv *priv = c->priv;
 764         struct mlx5_core_dev *mdev = priv->mdev;
 765         struct mlx5_core_cq *mcq = &cq->mcq;
 766         int eqn_not_used;
 767         unsigned int irqn;
 768         int err;
 769         u32 i;
 770
 771         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 772         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 773         param->eq_ix   = c->ix;
 774
 775         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 776                                &cq->wq_ctrl);
 777         if (err)
 778                 return err;
 779
 780         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 781
 782         cq->napi        = &c->napi;
 783
 784         mcq->cqe_sz     = 64;
 785         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 786         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 787         *mcq->set_ci_db = 0;
 788         *mcq->arm_db    = 0;
 789         mcq->vector     = param->eq_ix;
 790         mcq->comp       = mlx5e_completion_event;
 791         mcq->event      = mlx5e_cq_error_event;
 792         mcq->irqn       = irqn;
 793         mcq->uar        = &priv->cq_uar;
 794
 795         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 796                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 797
 798                 cqe->op_own = 0xf1;
 799         }
 800
 801         cq->channel = c;
 802         cq->priv = priv;
 803
 804         return 0;
 805 }
 806
 807 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 808 {
 809         mlx5_wq_destroy(&cq->wq_ctrl);
 810 }
 811
 812 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 813 {
 814         struct mlx5e_priv *priv = cq->priv;
 815         struct mlx5_core_dev *mdev = priv->mdev;
 816         struct mlx5_core_cq *mcq = &cq->mcq;
 817
 818         void *in;
 819         void *cqc;
 820         int inlen;
 821         unsigned int irqn_not_used;
 822         int eqn;
 823         int err;
 824
 825         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 826                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 827         in = mlx5_vzalloc(inlen);
 828         if (!in)
 829                 return -ENOMEM;
 830
 831         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 832
 833         memcpy(cqc, param->cqc, sizeof(param->cqc));
 834
 835         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 836                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 837
 838         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 839
 840         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 841         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 842         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 843                                             MLX5_ADAPTER_PAGE_SHIFT);
 844         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 845
 846         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 847
 848         kvfree(in);
 849
 850         if (err)
 851                 return err;
 852
 853         mlx5e_cq_arm(cq);
 854
 855         return 0;
 856 }
 857
 858 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 859 {
 860         struct mlx5e_priv *priv = cq->priv;
 861         struct mlx5_core_dev *mdev = priv->mdev;
 862
 863         mlx5_core_destroy_cq(mdev, &cq->mcq);
 864 }
 865
 866 static int mlx5e_open_cq(struct mlx5e_channel *c,
 867                          struct mlx5e_cq_param *param,
 868                          struct mlx5e_cq *cq,
 869                          u16 moderation_usecs,
 870                          u16 moderation_frames)
 871 {
 872         int err;
 873         struct mlx5e_priv *priv = c->priv;
 874         struct mlx5_core_dev *mdev = priv->mdev;
 875
 876         err = mlx5e_create_cq(c, param, cq);
 877         if (err)
 878                 return err;
 879
 880         err = mlx5e_enable_cq(cq, param);
 881         if (err)
 882                 goto err_destroy_cq;
 883
 884         if (MLX5_CAP_GEN(mdev, cq_moderation))
 885                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 886                                                moderation_usecs,
 887                                                moderation_frames);
 888         return 0;
 889
 890 err_destroy_cq:
 891         mlx5e_destroy_cq(cq);
 892
 893         return err;
 894 }
 895
 896 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 897 {
 898         mlx5e_disable_cq(cq);
 899         mlx5e_destroy_cq(cq);
 900 }
 901
 902 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 903 {
 904         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 905 }
 906
 907 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 908                              struct mlx5e_channel_param *cparam)
 909 {
 910         struct mlx5e_priv *priv = c->priv;
 911         int err;
 912         int tc;
 913
 914         for (tc = 0; tc < c->num_tc; tc++) {
 915                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 916                                     priv->params.tx_cq_moderation_usec,
 917                                     priv->params.tx_cq_moderation_pkts);
 918                 if (err)
 919                         goto err_close_tx_cqs;
 920         }
 921
 922         return 0;
 923
 924 err_close_tx_cqs:
 925         for (tc--; tc >= 0; tc--)
 926                 mlx5e_close_cq(&c->sq[tc].cq);
 927
 928         return err;
 929 }
 930
 931 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 932 {
 933         int tc;
 934
 935         for (tc = 0; tc < c->num_tc; tc++)
 936                 mlx5e_close_cq(&c->sq[tc].cq);
 937 }
 938
 939 static int mlx5e_open_sqs(struct mlx5e_channel *c,
 940                           struct mlx5e_channel_param *cparam)
 941 {
 942         int err;
 943         int tc;
 944
 945         for (tc = 0; tc < c->num_tc; tc++) {
 946                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
 947                 if (err)
 948                         goto err_close_sqs;
 949         }
 950
 951         return 0;
 952
 953 err_close_sqs:
 954         for (tc--; tc >= 0; tc--)
 955                 mlx5e_close_sq(&c->sq[tc]);
 956
 957         return err;
 958 }
 959
 960 static void mlx5e_close_sqs(struct mlx5e_channel *c)
 961 {
 962         int tc;
 963
 964         for (tc = 0; tc < c->num_tc; tc++)
 965                 mlx5e_close_sq(&c->sq[tc]);
 966 }
 967
 968 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
 969 {
 970         int i;
 971
 972         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
 973                 priv->channeltc_to_txq_map[ix][i] =
 974                         ix + i * priv->params.num_channels;
 975 }
 976
 977 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
 978                               struct mlx5e_channel_param *cparam,
 979                               struct mlx5e_channel **cp)
 980 {
 981         struct net_device *netdev = priv->netdev;
 982         int cpu = mlx5e_get_cpu(priv, ix);
 983         struct mlx5e_channel *c;
 984         int err;
 985
 986         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
 987         if (!c)
 988                 return -ENOMEM;
 989
 990         c->priv     = priv;
 991         c->ix       = ix;
 992         c->cpu      = cpu;
 993         c->pdev     = &priv->mdev->pdev->dev;
 994         c->netdev   = priv->netdev;
 995         c->mkey_be  = cpu_to_be32(priv->mkey.key);
 996         c->num_tc   = priv->params.num_tc;
 997
 998         mlx5e_build_channeltc_to_txq_map(priv, ix);
 999
1000         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1001
1002         err = mlx5e_open_tx_cqs(c, cparam);
1003         if (err)
1004                 goto err_napi_del;
1005
1006         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1007                             priv->params.rx_cq_moderation_usec,
1008                             priv->params.rx_cq_moderation_pkts);
1009         if (err)
1010                 goto err_close_tx_cqs;
1011
1012         napi_enable(&c->napi);
1013
1014         err = mlx5e_open_sqs(c, cparam);
1015         if (err)
1016                 goto err_disable_napi;
1017
1018         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1019         if (err)
1020                 goto err_close_sqs;
1021
1022         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1023         *cp = c;
1024
1025         return 0;
1026
1027 err_close_sqs:
1028         mlx5e_close_sqs(c);
1029
1030 err_disable_napi:
1031         napi_disable(&c->napi);
1032         mlx5e_close_cq(&c->rq.cq);
1033
1034 err_close_tx_cqs:
1035         mlx5e_close_tx_cqs(c);
1036
1037 err_napi_del:
1038         netif_napi_del(&c->napi);
1039         napi_hash_del(&c->napi);
1040         kfree(c);
1041
1042         return err;
1043 }
1044
1045 static void mlx5e_close_channel(struct mlx5e_channel *c)
1046 {
1047         mlx5e_close_rq(&c->rq);
1048         mlx5e_close_sqs(c);
1049         napi_disable(&c->napi);
1050         mlx5e_close_cq(&c->rq.cq);
1051         mlx5e_close_tx_cqs(c);
1052         netif_napi_del(&c->napi);
1053
1054         napi_hash_del(&c->napi);
1055         synchronize_rcu();
1056
1057         kfree(c);
1058 }
1059
1060 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1061                                  struct mlx5e_rq_param *param)
1062 {
1063         void *rqc = param->rqc;
1064         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1065
1066         MLX5_SET(wq, wq, wq_type,          MLX5_WQ_TYPE_LINKED_LIST);
1067         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1068         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1069         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1070         MLX5_SET(wq, wq, pd,               priv->pdn);
1071         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1072
1073         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1074         param->wq.linear = 1;
1075 }
1076
1077 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1078 {
1079         void *rqc = param->rqc;
1080         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1081
1082         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1083         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1084 }
1085
1086 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1087                                  struct mlx5e_sq_param *param)
1088 {
1089         void *sqc = param->sqc;
1090         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1091
1092         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1093         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1094         MLX5_SET(wq, wq, pd,            priv->pdn);
1095
1096         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1097         param->max_inline = priv->params.tx_max_inline;
1098 }
1099
1100 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1101                                         struct mlx5e_cq_param *param)
1102 {
1103         void *cqc = param->cqc;
1104
1105         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1106 }
1107
1108 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1109                                     struct mlx5e_cq_param *param)
1110 {
1111         void *cqc = param->cqc;
1112
1113         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_rq_size);
1114
1115         mlx5e_build_common_cq_param(priv, param);
1116 }
1117
1118 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1119                                     struct mlx5e_cq_param *param)
1120 {
1121         void *cqc = param->cqc;
1122
1123         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_sq_size);
1124
1125         mlx5e_build_common_cq_param(priv, param);
1126 }
1127
1128 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1129                                       struct mlx5e_channel_param *cparam)
1130 {
1131         memset(cparam, 0, sizeof(*cparam));
1132
1133         mlx5e_build_rq_param(priv, &cparam->rq);
1134         mlx5e_build_sq_param(priv, &cparam->sq);
1135         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1136         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1137 }
1138
1139 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1140 {
1141         struct mlx5e_channel_param cparam;
1142         int nch = priv->params.num_channels;
1143         int err = -ENOMEM;
1144         int i;
1145         int j;
1146
1147         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1148                                 GFP_KERNEL);
1149
1150         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1151                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1152
1153         if (!priv->channel || !priv->txq_to_sq_map)
1154                 goto err_free_txq_to_sq_map;
1155
1156         mlx5e_build_channel_param(priv, &cparam);
1157         for (i = 0; i < nch; i++) {
1158                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1159                 if (err)
1160                         goto err_close_channels;
1161         }
1162
1163         for (j = 0; j < nch; j++) {
1164                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1165                 if (err)
1166                         goto err_close_channels;
1167         }
1168
1169         return 0;
1170
1171 err_close_channels:
1172         for (i--; i >= 0; i--)
1173                 mlx5e_close_channel(priv->channel[i]);
1174
1175 err_free_txq_to_sq_map:
1176         kfree(priv->txq_to_sq_map);
1177         kfree(priv->channel);
1178
1179         return err;
1180 }
1181
1182 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1183 {
1184         int i;
1185
1186         for (i = 0; i < priv->params.num_channels; i++)
1187                 mlx5e_close_channel(priv->channel[i]);
1188
1189         kfree(priv->txq_to_sq_map);
1190         kfree(priv->channel);
1191 }
1192
1193 static int mlx5e_rx_hash_fn(int hfunc)
1194 {
1195         return (hfunc == ETH_RSS_HASH_TOP) ?
1196                MLX5_RX_HASH_FN_TOEPLITZ :
1197                MLX5_RX_HASH_FN_INVERTED_XOR8;
1198 }
1199
1200 static int mlx5e_bits_invert(unsigned long a, int size)
1201 {
1202         int inv = 0;
1203         int i;
1204
1205         for (i = 0; i < size; i++)
1206                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1207
1208         return inv;
1209 }
1210
1211 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1212 {
1213         int i;
1214
1215         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1216                 int ix = i;
1217
1218                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1219                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1220
1221                 ix = priv->params.indirection_rqt[ix];
1222                 MLX5_SET(rqtc, rqtc, rq_num[i],
1223                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1224                          priv->channel[ix]->rq.rqn :
1225                          priv->drop_rq.rqn);
1226         }
1227 }
1228
1229 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1230                                 enum mlx5e_rqt_ix rqt_ix)
1231 {
1232
1233         switch (rqt_ix) {
1234         case MLX5E_INDIRECTION_RQT:
1235                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1236
1237                 break;
1238
1239         default: /* MLX5E_SINGLE_RQ_RQT */
1240                 MLX5_SET(rqtc, rqtc, rq_num[0],
1241                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1242                          priv->channel[0]->rq.rqn :
1243                          priv->drop_rq.rqn);
1244
1245                 break;
1246         }
1247 }
1248
1249 static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1250 {
1251         struct mlx5_core_dev *mdev = priv->mdev;
1252         u32 *in;
1253         void *rqtc;
1254         int inlen;
1255         int sz;
1256         int err;
1257
1258         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1259
1260         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1261         in = mlx5_vzalloc(inlen);
1262         if (!in)
1263                 return -ENOMEM;
1264
1265         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1266
1267         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1268         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1269
1270         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1271
1272         err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
1273
1274         kvfree(in);
1275
1276         return err;
1277 }
1278
1279 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1280 {
1281         struct mlx5_core_dev *mdev = priv->mdev;
1282         u32 *in;
1283         void *rqtc;
1284         int inlen;
1285         int sz;
1286         int err;
1287
1288         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1289
1290         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1291         in = mlx5_vzalloc(inlen);
1292         if (!in)
1293                 return -ENOMEM;
1294
1295         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1296
1297         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1298
1299         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1300
1301         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1302
1303         err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1304
1305         kvfree(in);
1306
1307         return err;
1308 }
1309
1310 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1311 {
1312         mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
1313 }
1314
1315 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1316 {
1317         mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1318         mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1319 }
1320
1321 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1322 {
1323         if (!priv->params.lro_en)
1324                 return;
1325
1326 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1327
1328         MLX5_SET(tirc, tirc, lro_enable_mask,
1329                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1330                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1331         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1332                  (priv->params.lro_wqe_sz -
1333                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1334         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1335                  MLX5_CAP_ETH(priv->mdev,
1336                               lro_timer_supported_periods[2]));
1337 }
1338
1339 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1340 {
1341         MLX5_SET(tirc, tirc, rx_hash_fn,
1342                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1343         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1344                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1345                                              rx_hash_toeplitz_key);
1346                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1347                                                rx_hash_toeplitz_key);
1348
1349                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1350                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1351         }
1352 }
1353
1354 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1355 {
1356         struct mlx5_core_dev *mdev = priv->mdev;
1357
1358         void *in;
1359         void *tirc;
1360         int inlen;
1361         int err;
1362         int tt;
1363
1364         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1365         in = mlx5_vzalloc(inlen);
1366         if (!in)
1367                 return -ENOMEM;
1368
1369         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1370         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1371
1372         mlx5e_build_tir_ctx_lro(tirc, priv);
1373
1374         for (tt = 0; tt < MLX5E_NUM_TT; tt++) {
1375                 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1376                 if (err)
1377                         break;
1378         }
1379
1380         kvfree(in);
1381
1382         return err;
1383 }
1384
1385 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1386                                                   u32 tirn)
1387 {
1388         void *in;
1389         int inlen;
1390         int err;
1391
1392         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1393         in = mlx5_vzalloc(inlen);
1394         if (!in)
1395                 return -ENOMEM;
1396
1397         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1398
1399         err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1400
1401         kvfree(in);
1402
1403         return err;
1404 }
1405
1406 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1407 {
1408         int err;
1409         int i;
1410
1411         for (i = 0; i < MLX5E_NUM_TT; i++) {
1412                 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1413                                                              priv->tirn[i]);
1414                 if (err)
1415                         return err;
1416         }
1417
1418         return 0;
1419 }
1420
1421 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1422 {
1423         struct mlx5e_priv *priv = netdev_priv(netdev);
1424         struct mlx5_core_dev *mdev = priv->mdev;
1425         int hw_mtu;
1426         int err;
1427
1428         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1429         if (err)
1430                 return err;
1431
1432         mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1433
1434         if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1435                 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1436                             __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1437
1438         netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1439         return 0;
1440 }
1441
1442 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1443 {
1444         struct mlx5e_priv *priv = netdev_priv(netdev);
1445         int nch = priv->params.num_channels;
1446         int ntc = priv->params.num_tc;
1447         int tc;
1448
1449         netdev_reset_tc(netdev);
1450
1451         if (ntc == 1)
1452                 return;
1453
1454         netdev_set_num_tc(netdev, ntc);
1455
1456         for (tc = 0; tc < ntc; tc++)
1457                 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1458 }
1459
1460 int mlx5e_open_locked(struct net_device *netdev)
1461 {
1462         struct mlx5e_priv *priv = netdev_priv(netdev);
1463         int num_txqs;
1464         int err;
1465
1466         set_bit(MLX5E_STATE_OPENED, &priv->state);
1467
1468         mlx5e_netdev_set_tcs(netdev);
1469
1470         num_txqs = priv->params.num_channels * priv->params.num_tc;
1471         netif_set_real_num_tx_queues(netdev, num_txqs);
1472         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1473
1474         err = mlx5e_set_dev_port_mtu(netdev);
1475         if (err)
1476                 goto err_clear_state_opened_flag;
1477
1478         err = mlx5e_open_channels(priv);
1479         if (err) {
1480                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1481                            __func__, err);
1482                 goto err_clear_state_opened_flag;
1483         }
1484
1485         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1486         if (err) {
1487                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1488                            __func__, err);
1489                 goto err_close_channels;
1490         }
1491
1492         mlx5e_redirect_rqts(priv);
1493         mlx5e_update_carrier(priv);
1494         mlx5e_timestamp_init(priv);
1495
1496         schedule_delayed_work(&priv->update_stats_work, 0);
1497
1498         return 0;
1499
1500 err_close_channels:
1501         mlx5e_close_channels(priv);
1502 err_clear_state_opened_flag:
1503         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1504         return err;
1505 }
1506
1507 static int mlx5e_open(struct net_device *netdev)
1508 {
1509         struct mlx5e_priv *priv = netdev_priv(netdev);
1510         int err;
1511
1512         mutex_lock(&priv->state_lock);
1513         err = mlx5e_open_locked(netdev);
1514         mutex_unlock(&priv->state_lock);
1515
1516         return err;
1517 }
1518
1519 int mlx5e_close_locked(struct net_device *netdev)
1520 {
1521         struct mlx5e_priv *priv = netdev_priv(netdev);
1522
1523         /* May already be CLOSED in case a previous configuration operation
1524          * (e.g RX/TX queue size change) that involves close&open failed.
1525          */
1526         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1527                 return 0;
1528
1529         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1530
1531         mlx5e_timestamp_cleanup(priv);
1532         netif_carrier_off(priv->netdev);
1533         mlx5e_redirect_rqts(priv);
1534         mlx5e_close_channels(priv);
1535
1536         return 0;
1537 }
1538
1539 static int mlx5e_close(struct net_device *netdev)
1540 {
1541         struct mlx5e_priv *priv = netdev_priv(netdev);
1542         int err;
1543
1544         mutex_lock(&priv->state_lock);
1545         err = mlx5e_close_locked(netdev);
1546         mutex_unlock(&priv->state_lock);
1547
1548         return err;
1549 }
1550
1551 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1552                                 struct mlx5e_rq *rq,
1553                                 struct mlx5e_rq_param *param)
1554 {
1555         struct mlx5_core_dev *mdev = priv->mdev;
1556         void *rqc = param->rqc;
1557         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1558         int err;
1559
1560         param->wq.db_numa_node = param->wq.buf_numa_node;
1561
1562         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1563                                 &rq->wq_ctrl);
1564         if (err)
1565                 return err;
1566
1567         rq->priv = priv;
1568
1569         return 0;
1570 }
1571
1572 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1573                                 struct mlx5e_cq *cq,
1574                                 struct mlx5e_cq_param *param)
1575 {
1576         struct mlx5_core_dev *mdev = priv->mdev;
1577         struct mlx5_core_cq *mcq = &cq->mcq;
1578         int eqn_not_used;
1579         unsigned int irqn;
1580         int err;
1581
1582         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1583                                &cq->wq_ctrl);
1584         if (err)
1585                 return err;
1586
1587         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1588
1589         mcq->cqe_sz     = 64;
1590         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1591         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1592         *mcq->set_ci_db = 0;
1593         *mcq->arm_db    = 0;
1594         mcq->vector     = param->eq_ix;
1595         mcq->comp       = mlx5e_completion_event;
1596         mcq->event      = mlx5e_cq_error_event;
1597         mcq->irqn       = irqn;
1598         mcq->uar        = &priv->cq_uar;
1599
1600         cq->priv = priv;
1601
1602         return 0;
1603 }
1604
1605 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1606 {
1607         struct mlx5e_cq_param cq_param;
1608         struct mlx5e_rq_param rq_param;
1609         struct mlx5e_rq *rq = &priv->drop_rq;
1610         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1611         int err;
1612
1613         memset(&cq_param, 0, sizeof(cq_param));
1614         memset(&rq_param, 0, sizeof(rq_param));
1615         mlx5e_build_drop_rq_param(&rq_param);
1616
1617         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1618         if (err)
1619                 return err;
1620
1621         err = mlx5e_enable_cq(cq, &cq_param);
1622         if (err)
1623                 goto err_destroy_cq;
1624
1625         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1626         if (err)
1627                 goto err_disable_cq;
1628
1629         err = mlx5e_enable_rq(rq, &rq_param);
1630         if (err)
1631                 goto err_destroy_rq;
1632
1633         return 0;
1634
1635 err_destroy_rq:
1636         mlx5e_destroy_rq(&priv->drop_rq);
1637
1638 err_disable_cq:
1639         mlx5e_disable_cq(&priv->drop_rq.cq);
1640
1641 err_destroy_cq:
1642         mlx5e_destroy_cq(&priv->drop_rq.cq);
1643
1644         return err;
1645 }
1646
1647 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1648 {
1649         mlx5e_disable_rq(&priv->drop_rq);
1650         mlx5e_destroy_rq(&priv->drop_rq);
1651         mlx5e_disable_cq(&priv->drop_rq.cq);
1652         mlx5e_destroy_cq(&priv->drop_rq.cq);
1653 }
1654
1655 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1656 {
1657         struct mlx5_core_dev *mdev = priv->mdev;
1658         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1659         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1660
1661         memset(in, 0, sizeof(in));
1662
1663         MLX5_SET(tisc, tisc, prio, tc << 1);
1664         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1665
1666         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1667 }
1668
1669 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1670 {
1671         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1672 }
1673
1674 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1675 {
1676         int err;
1677         int tc;
1678
1679         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1680                 err = mlx5e_create_tis(priv, tc);
1681                 if (err)
1682                         goto err_close_tises;
1683         }
1684
1685         return 0;
1686
1687 err_close_tises:
1688         for (tc--; tc >= 0; tc--)
1689                 mlx5e_destroy_tis(priv, tc);
1690
1691         return err;
1692 }
1693
1694 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1695 {
1696         int tc;
1697
1698         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1699                 mlx5e_destroy_tis(priv, tc);
1700 }
1701
1702 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1703 {
1704         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1705
1706         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1707
1708 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1709                                  MLX5_HASH_FIELD_SEL_DST_IP)
1710
1711 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1712                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1713                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1714                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1715
1716 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1717                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1718                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1719
1720         mlx5e_build_tir_ctx_lro(tirc, priv);
1721
1722         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1723
1724         switch (tt) {
1725         case MLX5E_TT_ANY:
1726                 MLX5_SET(tirc, tirc, indirect_table,
1727                          priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1728                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
1729                 break;
1730         default:
1731                 MLX5_SET(tirc, tirc, indirect_table,
1732                          priv->rqtn[MLX5E_INDIRECTION_RQT]);
1733                 mlx5e_build_tir_ctx_hash(tirc, priv);
1734                 break;
1735         }
1736
1737         switch (tt) {
1738         case MLX5E_TT_IPV4_TCP:
1739                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1740                          MLX5_L3_PROT_TYPE_IPV4);
1741                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1742                          MLX5_L4_PROT_TYPE_TCP);
1743                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1744                          MLX5_HASH_IP_L4PORTS);
1745                 break;
1746
1747         case MLX5E_TT_IPV6_TCP:
1748                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1749                          MLX5_L3_PROT_TYPE_IPV6);
1750                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1751                          MLX5_L4_PROT_TYPE_TCP);
1752                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1753                          MLX5_HASH_IP_L4PORTS);
1754                 break;
1755
1756         case MLX5E_TT_IPV4_UDP:
1757                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1758                          MLX5_L3_PROT_TYPE_IPV4);
1759                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1760                          MLX5_L4_PROT_TYPE_UDP);
1761                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1762                          MLX5_HASH_IP_L4PORTS);
1763                 break;
1764
1765         case MLX5E_TT_IPV6_UDP:
1766                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1767                          MLX5_L3_PROT_TYPE_IPV6);
1768                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1769                          MLX5_L4_PROT_TYPE_UDP);
1770                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1771                          MLX5_HASH_IP_L4PORTS);
1772                 break;
1773
1774         case MLX5E_TT_IPV4_IPSEC_AH:
1775                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1776                          MLX5_L3_PROT_TYPE_IPV4);
1777                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1778                          MLX5_HASH_IP_IPSEC_SPI);
1779                 break;
1780
1781         case MLX5E_TT_IPV6_IPSEC_AH:
1782                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1783                          MLX5_L3_PROT_TYPE_IPV6);
1784                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1785                          MLX5_HASH_IP_IPSEC_SPI);
1786                 break;
1787
1788         case MLX5E_TT_IPV4_IPSEC_ESP:
1789                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1790                          MLX5_L3_PROT_TYPE_IPV4);
1791                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1792                          MLX5_HASH_IP_IPSEC_SPI);
1793                 break;
1794
1795         case MLX5E_TT_IPV6_IPSEC_ESP:
1796                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1797                          MLX5_L3_PROT_TYPE_IPV6);
1798                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1799                          MLX5_HASH_IP_IPSEC_SPI);
1800                 break;
1801
1802         case MLX5E_TT_IPV4:
1803                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1804                          MLX5_L3_PROT_TYPE_IPV4);
1805                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1806                          MLX5_HASH_IP);
1807                 break;
1808
1809         case MLX5E_TT_IPV6:
1810                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1811                          MLX5_L3_PROT_TYPE_IPV6);
1812                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1813                          MLX5_HASH_IP);
1814                 break;
1815         }
1816 }
1817
1818 static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
1819 {
1820         struct mlx5_core_dev *mdev = priv->mdev;
1821         u32 *in;
1822         void *tirc;
1823         int inlen;
1824         int err;
1825
1826         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1827         in = mlx5_vzalloc(inlen);
1828         if (!in)
1829                 return -ENOMEM;
1830
1831         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1832
1833         mlx5e_build_tir_ctx(priv, tirc, tt);
1834
1835         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1836
1837         kvfree(in);
1838
1839         return err;
1840 }
1841
1842 static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
1843 {
1844         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1845 }
1846
1847 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
1848 {
1849         int err;
1850         int i;
1851
1852         for (i = 0; i < MLX5E_NUM_TT; i++) {
1853                 err = mlx5e_create_tir(priv, i);
1854                 if (err)
1855                         goto err_destroy_tirs;
1856         }
1857
1858         return 0;
1859
1860 err_destroy_tirs:
1861         for (i--; i >= 0; i--)
1862                 mlx5e_destroy_tir(priv, i);
1863
1864         return err;
1865 }
1866
1867 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
1868 {
1869         int i;
1870
1871         for (i = 0; i < MLX5E_NUM_TT; i++)
1872                 mlx5e_destroy_tir(priv, i);
1873 }
1874
1875 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
1876 {
1877         struct mlx5e_priv *priv = netdev_priv(netdev);
1878         bool was_opened;
1879         int err = 0;
1880
1881         if (tc && tc != MLX5E_MAX_NUM_TC)
1882                 return -EINVAL;
1883
1884         mutex_lock(&priv->state_lock);
1885
1886         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1887         if (was_opened)
1888                 mlx5e_close_locked(priv->netdev);
1889
1890         priv->params.num_tc = tc ? tc : 1;
1891
1892         if (was_opened)
1893                 err = mlx5e_open_locked(priv->netdev);
1894
1895         mutex_unlock(&priv->state_lock);
1896
1897         return err;
1898 }
1899
1900 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
1901                               __be16 proto, struct tc_to_netdev *tc)
1902 {
1903         struct mlx5e_priv *priv = netdev_priv(dev);
1904
1905         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
1906                 goto mqprio;
1907
1908         switch (tc->type) {
1909         case TC_SETUP_CLSFLOWER:
1910                 switch (tc->cls_flower->command) {
1911                 case TC_CLSFLOWER_REPLACE:
1912                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
1913                 case TC_CLSFLOWER_DESTROY:
1914                         return mlx5e_delete_flower(priv, tc->cls_flower);
1915                 }
1916         default:
1917                 return -EOPNOTSUPP;
1918         }
1919
1920 mqprio:
1921         if (tc->type != TC_SETUP_MQPRIO)
1922                 return -EINVAL;
1923
1924         return mlx5e_setup_tc(dev, tc->tc);
1925 }
1926
1927 static struct rtnl_link_stats64 *
1928 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1929 {
1930         struct mlx5e_priv *priv = netdev_priv(dev);
1931         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1932
1933         stats->rx_packets = vstats->rx_packets;
1934         stats->rx_bytes   = vstats->rx_bytes;
1935         stats->tx_packets = vstats->tx_packets;
1936         stats->tx_bytes   = vstats->tx_bytes;
1937         stats->multicast  = vstats->rx_multicast_packets +
1938                             vstats->tx_multicast_packets;
1939         stats->tx_errors  = vstats->tx_error_packets;
1940         stats->rx_errors  = vstats->rx_error_packets;
1941         stats->tx_dropped = vstats->tx_queue_dropped;
1942         stats->rx_crc_errors = 0;
1943         stats->rx_length_errors = 0;
1944
1945         return stats;
1946 }
1947
1948 static void mlx5e_set_rx_mode(struct net_device *dev)
1949 {
1950         struct mlx5e_priv *priv = netdev_priv(dev);
1951
1952         schedule_work(&priv->set_rx_mode_work);
1953 }
1954
1955 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1956 {
1957         struct mlx5e_priv *priv = netdev_priv(netdev);
1958         struct sockaddr *saddr = addr;
1959
1960         if (!is_valid_ether_addr(saddr->sa_data))
1961                 return -EADDRNOTAVAIL;
1962
1963         netif_addr_lock_bh(netdev);
1964         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1965         netif_addr_unlock_bh(netdev);
1966
1967         schedule_work(&priv->set_rx_mode_work);
1968
1969         return 0;
1970 }
1971
1972 static int mlx5e_set_features(struct net_device *netdev,
1973                               netdev_features_t features)
1974 {
1975         struct mlx5e_priv *priv = netdev_priv(netdev);
1976         int err = 0;
1977         netdev_features_t changes = features ^ netdev->features;
1978
1979         mutex_lock(&priv->state_lock);
1980
1981         if (changes & NETIF_F_LRO) {
1982                 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1983
1984                 if (was_opened)
1985                         mlx5e_close_locked(priv->netdev);
1986
1987                 priv->params.lro_en = !!(features & NETIF_F_LRO);
1988                 err = mlx5e_modify_tirs_lro(priv);
1989                 if (err)
1990                         mlx5_core_warn(priv->mdev, "lro modify failed, %d\n",
1991                                        err);
1992
1993                 if (was_opened)
1994                         err = mlx5e_open_locked(priv->netdev);
1995         }
1996
1997         mutex_unlock(&priv->state_lock);
1998
1999         if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
2000                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
2001                         mlx5e_enable_vlan_filter(priv);
2002                 else
2003                         mlx5e_disable_vlan_filter(priv);
2004         }
2005
2006         if ((changes & NETIF_F_HW_TC) && !(features & NETIF_F_HW_TC) &&
2007             mlx5e_tc_num_filters(priv)) {
2008                 netdev_err(netdev,
2009                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2010                 return -EINVAL;
2011         }
2012
2013         return err;
2014 }
2015
2016 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2017 {
2018         struct mlx5e_priv *priv = netdev_priv(netdev);
2019         struct mlx5_core_dev *mdev = priv->mdev;
2020         bool was_opened;
2021         int max_mtu;
2022         int err = 0;
2023
2024         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2025
2026         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2027
2028         if (new_mtu > max_mtu) {
2029                 netdev_err(netdev,
2030                            "%s: Bad MTU (%d) > (%d) Max\n",
2031                            __func__, new_mtu, max_mtu);
2032                 return -EINVAL;
2033         }
2034
2035         mutex_lock(&priv->state_lock);
2036
2037         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2038         if (was_opened)
2039                 mlx5e_close_locked(netdev);
2040
2041         netdev->mtu = new_mtu;
2042
2043         if (was_opened)
2044                 err = mlx5e_open_locked(netdev);
2045
2046         mutex_unlock(&priv->state_lock);
2047
2048         return err;
2049 }
2050
2051 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2052 {
2053         switch (cmd) {
2054         case SIOCSHWTSTAMP:
2055                 return mlx5e_hwstamp_set(dev, ifr);
2056         case SIOCGHWTSTAMP:
2057                 return mlx5e_hwstamp_get(dev, ifr);
2058         default:
2059                 return -EOPNOTSUPP;
2060         }
2061 }
2062
2063 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2064 {
2065         struct mlx5e_priv *priv = netdev_priv(dev);
2066         struct mlx5_core_dev *mdev = priv->mdev;
2067
2068         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2069 }
2070
2071 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2072 {
2073         struct mlx5e_priv *priv = netdev_priv(dev);
2074         struct mlx5_core_dev *mdev = priv->mdev;
2075
2076         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2077                                            vlan, qos);
2078 }
2079
2080 static int mlx5_vport_link2ifla(u8 esw_link)
2081 {
2082         switch (esw_link) {
2083         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2084                 return IFLA_VF_LINK_STATE_DISABLE;
2085         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2086                 return IFLA_VF_LINK_STATE_ENABLE;
2087         }
2088         return IFLA_VF_LINK_STATE_AUTO;
2089 }
2090
2091 static int mlx5_ifla_link2vport(u8 ifla_link)
2092 {
2093         switch (ifla_link) {
2094         case IFLA_VF_LINK_STATE_DISABLE:
2095                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2096         case IFLA_VF_LINK_STATE_ENABLE:
2097                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2098         }
2099         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2100 }
2101
2102 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2103                                    int link_state)
2104 {
2105         struct mlx5e_priv *priv = netdev_priv(dev);
2106         struct mlx5_core_dev *mdev = priv->mdev;
2107
2108         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2109                                             mlx5_ifla_link2vport(link_state));
2110 }
2111
2112 static int mlx5e_get_vf_config(struct net_device *dev,
2113                                int vf, struct ifla_vf_info *ivi)
2114 {
2115         struct mlx5e_priv *priv = netdev_priv(dev);
2116         struct mlx5_core_dev *mdev = priv->mdev;
2117         int err;
2118
2119         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2120         if (err)
2121                 return err;
2122         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2123         return 0;
2124 }
2125
2126 static int mlx5e_get_vf_stats(struct net_device *dev,
2127                               int vf, struct ifla_vf_stats *vf_stats)
2128 {
2129         struct mlx5e_priv *priv = netdev_priv(dev);
2130         struct mlx5_core_dev *mdev = priv->mdev;
2131
2132         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2133                                             vf_stats);
2134 }
2135
2136 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2137                                  sa_family_t sa_family, __be16 port)
2138 {
2139         struct mlx5e_priv *priv = netdev_priv(netdev);
2140
2141         if (!mlx5e_vxlan_allowed(priv->mdev))
2142                 return;
2143
2144         mlx5e_vxlan_add_port(priv, be16_to_cpu(port));
2145 }
2146
2147 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2148                                  sa_family_t sa_family, __be16 port)
2149 {
2150         struct mlx5e_priv *priv = netdev_priv(netdev);
2151
2152         if (!mlx5e_vxlan_allowed(priv->mdev))
2153                 return;
2154
2155         mlx5e_vxlan_del_port(priv, be16_to_cpu(port));
2156 }
2157
2158 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2159                                                     struct sk_buff *skb,
2160                                                     netdev_features_t features)
2161 {
2162         struct udphdr *udph;
2163         u16 proto;
2164         u16 port = 0;
2165
2166         switch (vlan_get_protocol(skb)) {
2167         case htons(ETH_P_IP):
2168                 proto = ip_hdr(skb)->protocol;
2169                 break;
2170         case htons(ETH_P_IPV6):
2171                 proto = ipv6_hdr(skb)->nexthdr;
2172                 break;
2173         default:
2174                 goto out;
2175         }
2176
2177         if (proto == IPPROTO_UDP) {
2178                 udph = udp_hdr(skb);
2179                 port = be16_to_cpu(udph->dest);
2180         }
2181
2182         /* Verify if UDP port is being offloaded by HW */
2183         if (port && mlx5e_vxlan_lookup_port(priv, port))
2184                 return features;
2185
2186 out:
2187         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2188         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2189 }
2190
2191 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2192                                               struct net_device *netdev,
2193                                               netdev_features_t features)
2194 {
2195         struct mlx5e_priv *priv = netdev_priv(netdev);
2196
2197         features = vlan_features_check(skb, features);
2198         features = vxlan_features_check(skb, features);
2199
2200         /* Validate if the tunneled packet is being offloaded by HW */
2201         if (skb->encapsulation &&
2202             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2203                 return mlx5e_vxlan_features_check(priv, skb, features);
2204
2205         return features;
2206 }
2207
2208 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2209         .ndo_open                = mlx5e_open,
2210         .ndo_stop                = mlx5e_close,
2211         .ndo_start_xmit          = mlx5e_xmit,
2212         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2213         .ndo_select_queue        = mlx5e_select_queue,
2214         .ndo_get_stats64         = mlx5e_get_stats,
2215         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2216         .ndo_set_mac_address     = mlx5e_set_mac,
2217         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2218         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2219         .ndo_set_features        = mlx5e_set_features,
2220         .ndo_change_mtu          = mlx5e_change_mtu,
2221         .ndo_do_ioctl            = mlx5e_ioctl,
2222 };
2223
2224 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2225         .ndo_open                = mlx5e_open,
2226         .ndo_stop                = mlx5e_close,
2227         .ndo_start_xmit          = mlx5e_xmit,
2228         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2229         .ndo_select_queue        = mlx5e_select_queue,
2230         .ndo_get_stats64         = mlx5e_get_stats,
2231         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2232         .ndo_set_mac_address     = mlx5e_set_mac,
2233         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2234         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2235         .ndo_set_features        = mlx5e_set_features,
2236         .ndo_change_mtu          = mlx5e_change_mtu,
2237         .ndo_do_ioctl            = mlx5e_ioctl,
2238         .ndo_add_vxlan_port      = mlx5e_add_vxlan_port,
2239         .ndo_del_vxlan_port      = mlx5e_del_vxlan_port,
2240         .ndo_features_check      = mlx5e_features_check,
2241         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2242         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2243         .ndo_get_vf_config       = mlx5e_get_vf_config,
2244         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2245         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2246 };
2247
2248 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2249 {
2250         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2251                 return -ENOTSUPP;
2252         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2253             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2254             !MLX5_CAP_ETH(mdev, csum_cap) ||
2255             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2256             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2257             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2258             MLX5_CAP_FLOWTABLE(mdev,
2259                                flow_table_properties_nic_receive.max_ft_level)
2260                                < 3) {
2261                 mlx5_core_warn(mdev,
2262                                "Not creating net device, some required device capabilities are missing\n");
2263                 return -ENOTSUPP;
2264         }
2265         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2266                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2267         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2268                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2269
2270         return 0;
2271 }
2272
2273 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2274 {
2275         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2276
2277         return bf_buf_size -
2278                sizeof(struct mlx5e_tx_wqe) +
2279                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2280 }
2281
2282 #ifdef CONFIG_MLX5_CORE_EN_DCB
2283 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2284 {
2285         int i;
2286
2287         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2288         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2289                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2290                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2291                 priv->params.ets.prio_tc[i] = i;
2292         }
2293
2294         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2295         priv->params.ets.prio_tc[0] = 1;
2296         priv->params.ets.prio_tc[1] = 0;
2297 }
2298 #endif
2299
2300 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2301                                    u32 *indirection_rqt, int len,
2302                                    int num_channels)
2303 {
2304         int node = mdev->priv.numa_node;
2305         int node_num_of_cores;
2306         int i;
2307
2308         if (node == -1)
2309                 node = first_online_node;
2310
2311         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2312
2313         if (node_num_of_cores)
2314                 num_channels = min_t(int, num_channels, node_num_of_cores);
2315
2316         for (i = 0; i < len; i++)
2317                 indirection_rqt[i] = i % num_channels;
2318 }
2319
2320 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2321                                     struct net_device *netdev,
2322                                     int num_channels)
2323 {
2324         struct mlx5e_priv *priv = netdev_priv(netdev);
2325
2326         priv->params.log_sq_size           =
2327                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2328         priv->params.log_rq_size           =
2329                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2330         priv->params.rx_cq_moderation_usec =
2331                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2332         priv->params.rx_cq_moderation_pkts =
2333                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2334         priv->params.tx_cq_moderation_usec =
2335                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2336         priv->params.tx_cq_moderation_pkts =
2337                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2338         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
2339         priv->params.min_rx_wqes           =
2340                 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2341         priv->params.num_tc                = 1;
2342         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2343
2344         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2345                             sizeof(priv->params.toeplitz_hash_key));
2346
2347         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2348                                       MLX5E_INDIR_RQT_SIZE, num_channels);
2349
2350         priv->params.lro_wqe_sz            =
2351                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2352
2353         priv->mdev                         = mdev;
2354         priv->netdev                       = netdev;
2355         priv->params.num_channels          = num_channels;
2356
2357 #ifdef CONFIG_MLX5_CORE_EN_DCB
2358         mlx5e_ets_init(priv);
2359 #endif
2360
2361         mutex_init(&priv->state_lock);
2362
2363         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2364         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2365         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2366 }
2367
2368 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2369 {
2370         struct mlx5e_priv *priv = netdev_priv(netdev);
2371
2372         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2373         if (is_zero_ether_addr(netdev->dev_addr) &&
2374             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2375                 eth_hw_addr_random(netdev);
2376                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2377         }
2378 }
2379
2380 static void mlx5e_build_netdev(struct net_device *netdev)
2381 {
2382         struct mlx5e_priv *priv = netdev_priv(netdev);
2383         struct mlx5_core_dev *mdev = priv->mdev;
2384
2385         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2386
2387         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2388                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2389 #ifdef CONFIG_MLX5_CORE_EN_DCB
2390                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2391 #endif
2392         } else {
2393                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2394         }
2395
2396         netdev->watchdog_timeo    = 15 * HZ;
2397
2398         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
2399
2400         netdev->vlan_features    |= NETIF_F_SG;
2401         netdev->vlan_features    |= NETIF_F_IP_CSUM;
2402         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
2403         netdev->vlan_features    |= NETIF_F_GRO;
2404         netdev->vlan_features    |= NETIF_F_TSO;
2405         netdev->vlan_features    |= NETIF_F_TSO6;
2406         netdev->vlan_features    |= NETIF_F_RXCSUM;
2407         netdev->vlan_features    |= NETIF_F_RXHASH;
2408
2409         if (!!MLX5_CAP_ETH(mdev, lro_cap))
2410                 netdev->vlan_features    |= NETIF_F_LRO;
2411
2412         netdev->hw_features       = netdev->vlan_features;
2413         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
2414         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
2415         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
2416
2417         if (mlx5e_vxlan_allowed(mdev)) {
2418                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL;
2419                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2420                 netdev->hw_enc_features |= NETIF_F_RXCSUM;
2421                 netdev->hw_enc_features |= NETIF_F_TSO;
2422                 netdev->hw_enc_features |= NETIF_F_TSO6;
2423                 netdev->hw_enc_features |= NETIF_F_RXHASH;
2424                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2425         }
2426
2427         netdev->features          = netdev->hw_features;
2428         if (!priv->params.lro_en)
2429                 netdev->features  &= ~NETIF_F_LRO;
2430
2431 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2432         if (FT_CAP(flow_modify_en) &&
2433             FT_CAP(modify_root) &&
2434             FT_CAP(identified_miss_table_mode) &&
2435             FT_CAP(flow_table_modify))
2436                 priv->netdev->hw_features      |= NETIF_F_HW_TC;
2437
2438         netdev->features         |= NETIF_F_HIGHDMA;
2439
2440         netdev->priv_flags       |= IFF_UNICAST_FLT;
2441
2442         mlx5e_set_netdev_dev_addr(netdev);
2443 }
2444
2445 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2446                              struct mlx5_core_mkey *mkey)
2447 {
2448         struct mlx5_core_dev *mdev = priv->mdev;
2449         struct mlx5_create_mkey_mbox_in *in;
2450         int err;
2451
2452         in = mlx5_vzalloc(sizeof(*in));
2453         if (!in)
2454                 return -ENOMEM;
2455
2456         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2457                         MLX5_PERM_LOCAL_READ  |
2458                         MLX5_ACCESS_MODE_PA;
2459         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2460         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2461
2462         err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
2463                                     NULL);
2464
2465         kvfree(in);
2466
2467         return err;
2468 }
2469
2470 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2471 {
2472         struct mlx5_core_dev *mdev = priv->mdev;
2473         int err;
2474
2475         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2476         if (err) {
2477                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2478                 priv->q_counter = 0;
2479         }
2480 }
2481
2482 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2483 {
2484         if (!priv->q_counter)
2485                 return;
2486
2487         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2488 }
2489
2490 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2491 {
2492         struct net_device *netdev;
2493         struct mlx5e_priv *priv;
2494         int nch = mlx5e_get_max_num_channels(mdev);
2495         int err;
2496
2497         if (mlx5e_check_required_hca_cap(mdev))
2498                 return NULL;
2499
2500         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2501                                     nch * MLX5E_MAX_NUM_TC,
2502                                     nch);
2503         if (!netdev) {
2504                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2505                 return NULL;
2506         }
2507
2508         mlx5e_build_netdev_priv(mdev, netdev, nch);
2509         mlx5e_build_netdev(netdev);
2510
2511         netif_carrier_off(netdev);
2512
2513         priv = netdev_priv(netdev);
2514
2515         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
2516         if (err) {
2517                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2518                 goto err_free_netdev;
2519         }
2520
2521         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2522         if (err) {
2523                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2524                 goto err_unmap_free_uar;
2525         }
2526
2527         err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
2528         if (err) {
2529                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2530                 goto err_dealloc_pd;
2531         }
2532
2533         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
2534         if (err) {
2535                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2536                 goto err_dealloc_transport_domain;
2537         }
2538
2539         err = mlx5e_create_tises(priv);
2540         if (err) {
2541                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2542                 goto err_destroy_mkey;
2543         }
2544
2545         err = mlx5e_open_drop_rq(priv);
2546         if (err) {
2547                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2548                 goto err_destroy_tises;
2549         }
2550
2551         err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
2552         if (err) {
2553                 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
2554                 goto err_close_drop_rq;
2555         }
2556
2557         err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2558         if (err) {
2559                 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2560                 goto err_destroy_rqt_indir;
2561         }
2562
2563         err = mlx5e_create_tirs(priv);
2564         if (err) {
2565                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2566                 goto err_destroy_rqt_single;
2567         }
2568
2569         err = mlx5e_create_flow_tables(priv);
2570         if (err) {
2571                 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2572                 goto err_destroy_tirs;
2573         }
2574
2575         mlx5e_create_q_counter(priv);
2576
2577         mlx5e_init_eth_addr(priv);
2578
2579         mlx5e_vxlan_init(priv);
2580
2581         err = mlx5e_tc_init(priv);
2582         if (err)
2583                 goto err_dealloc_q_counters;
2584
2585 #ifdef CONFIG_MLX5_CORE_EN_DCB
2586         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2587 #endif
2588
2589         err = register_netdev(netdev);
2590         if (err) {
2591                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2592                 goto err_tc_cleanup;
2593         }
2594
2595         if (mlx5e_vxlan_allowed(mdev))
2596                 vxlan_get_rx_port(netdev);
2597
2598         mlx5e_enable_async_events(priv);
2599         schedule_work(&priv->set_rx_mode_work);
2600
2601         return priv;
2602
2603 err_tc_cleanup:
2604         mlx5e_tc_cleanup(priv);
2605
2606 err_dealloc_q_counters:
2607         mlx5e_destroy_q_counter(priv);
2608         mlx5e_destroy_flow_tables(priv);
2609
2610 err_destroy_tirs:
2611         mlx5e_destroy_tirs(priv);
2612
2613 err_destroy_rqt_single:
2614         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2615
2616 err_destroy_rqt_indir:
2617         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2618
2619 err_close_drop_rq:
2620         mlx5e_close_drop_rq(priv);
2621
2622 err_destroy_tises:
2623         mlx5e_destroy_tises(priv);
2624
2625 err_destroy_mkey:
2626         mlx5_core_destroy_mkey(mdev, &priv->mkey);
2627
2628 err_dealloc_transport_domain:
2629         mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
2630
2631 err_dealloc_pd:
2632         mlx5_core_dealloc_pd(mdev, priv->pdn);
2633
2634 err_unmap_free_uar:
2635         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2636
2637 err_free_netdev:
2638         free_netdev(netdev);
2639
2640         return NULL;
2641 }
2642
2643 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2644 {
2645         struct mlx5e_priv *priv = vpriv;
2646         struct net_device *netdev = priv->netdev;
2647
2648         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2649
2650         schedule_work(&priv->set_rx_mode_work);
2651         mlx5e_disable_async_events(priv);
2652         flush_scheduled_work();
2653         unregister_netdev(netdev);
2654         mlx5e_tc_cleanup(priv);
2655         mlx5e_vxlan_cleanup(priv);
2656         mlx5e_destroy_q_counter(priv);
2657         mlx5e_destroy_flow_tables(priv);
2658         mlx5e_destroy_tirs(priv);
2659         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2660         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2661         mlx5e_close_drop_rq(priv);
2662         mlx5e_destroy_tises(priv);
2663         mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
2664         mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
2665         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2666         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2667         free_netdev(netdev);
2668 }
2669
2670 static void *mlx5e_get_netdev(void *vpriv)
2671 {
2672         struct mlx5e_priv *priv = vpriv;
2673
2674         return priv->netdev;
2675 }
2676
2677 static struct mlx5_interface mlx5e_interface = {
2678         .add       = mlx5e_create_netdev,
2679         .remove    = mlx5e_destroy_netdev,
2680         .event     = mlx5e_async_event,
2681         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
2682         .get_dev   = mlx5e_get_netdev,
2683 };
2684
2685 void mlx5e_init(void)
2686 {
2687         mlx5_register_interface(&mlx5e_interface);
2688 }
2689
2690 void mlx5e_cleanup(void)
2691 {
2692         mlx5_unregister_interface(&mlx5e_interface);
2693 }