drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/mlx5/flow_table.h>
  34 #include "en.h"
  35
  36 struct mlx5e_rq_param {
  37         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  38         struct mlx5_wq_param       wq;
  39 };
  40
  41 struct mlx5e_sq_param {
  42         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  43         struct mlx5_wq_param       wq;
  44 };
  45
  46 struct mlx5e_cq_param {
  47         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  48         struct mlx5_wq_param       wq;
  49         u16                        eq_ix;
  50 };
  51
  52 struct mlx5e_channel_param {
  53         struct mlx5e_rq_param      rq;
  54         struct mlx5e_sq_param      sq;
  55         struct mlx5e_cq_param      rx_cq;
  56         struct mlx5e_cq_param      tx_cq;
  57 };
  58
  59 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  60 {
  61         struct mlx5_core_dev *mdev = priv->mdev;
  62         u8 port_state;
  63
  64         port_state = mlx5_query_vport_state(mdev,
  65                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT);
  66
  67         if (port_state == VPORT_STATE_UP)
  68                 netif_carrier_on(priv->netdev);
  69         else
  70                 netif_carrier_off(priv->netdev);
  71 }
  72
  73 static void mlx5e_update_carrier_work(struct work_struct *work)
  74 {
  75         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  76                                                update_carrier_work);
  77
  78         mutex_lock(&priv->state_lock);
  79         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  80                 mlx5e_update_carrier(priv);
  81         mutex_unlock(&priv->state_lock);
  82 }
  83
  84 void mlx5e_update_stats(struct mlx5e_priv *priv)
  85 {
  86         struct mlx5_core_dev *mdev = priv->mdev;
  87         struct mlx5e_vport_stats *s = &priv->stats.vport;
  88         struct mlx5e_rq_stats *rq_stats;
  89         struct mlx5e_sq_stats *sq_stats;
  90         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
  91         u32 *out;
  92         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
  93         u64 tx_offload_none;
  94         int i, j;
  95
  96         out = mlx5_vzalloc(outlen);
  97         if (!out)
  98                 return;
  99
 100         /* Collect firts the SW counters and then HW for consistency */
 101         s->tso_packets          = 0;
 102         s->tso_bytes            = 0;
 103         s->tx_queue_stopped     = 0;
 104         s->tx_queue_wake        = 0;
 105         s->tx_queue_dropped     = 0;
 106         tx_offload_none         = 0;
 107         s->lro_packets          = 0;
 108         s->lro_bytes            = 0;
 109         s->rx_csum_none         = 0;
 110         s->rx_wqe_err           = 0;
 111         for (i = 0; i < priv->params.num_channels; i++) {
 112                 rq_stats = &priv->channel[i]->rq.stats;
 113
 114                 s->lro_packets  += rq_stats->lro_packets;
 115                 s->lro_bytes    += rq_stats->lro_bytes;
 116                 s->rx_csum_none += rq_stats->csum_none;
 117                 s->rx_wqe_err   += rq_stats->wqe_err;
 118
 119                 for (j = 0; j < priv->num_tc; j++) {
 120                         sq_stats = &priv->channel[i]->sq[j].stats;
 121
 122                         s->tso_packets          += sq_stats->tso_packets;
 123                         s->tso_bytes            += sq_stats->tso_bytes;
 124                         s->tx_queue_stopped     += sq_stats->stopped;
 125                         s->tx_queue_wake        += sq_stats->wake;
 126                         s->tx_queue_dropped     += sq_stats->dropped;
 127                         tx_offload_none         += sq_stats->csum_offload_none;
 128                 }
 129         }
 130
 131         /* HW counters */
 132         memset(in, 0, sizeof(in));
 133
 134         MLX5_SET(query_vport_counter_in, in, opcode,
 135                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 136         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 137         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 138
 139         memset(out, 0, outlen);
 140
 141         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 142                 goto free_out;
 143
 144 #define MLX5_GET_CTR(p, x) \
 145         MLX5_GET64(query_vport_counter_out, p, x)
 146
 147         s->rx_error_packets     =
 148                 MLX5_GET_CTR(out, received_errors.packets);
 149         s->rx_error_bytes       =
 150                 MLX5_GET_CTR(out, received_errors.octets);
 151         s->tx_error_packets     =
 152                 MLX5_GET_CTR(out, transmit_errors.packets);
 153         s->tx_error_bytes       =
 154                 MLX5_GET_CTR(out, transmit_errors.octets);
 155
 156         s->rx_unicast_packets   =
 157                 MLX5_GET_CTR(out, received_eth_unicast.packets);
 158         s->rx_unicast_bytes     =
 159                 MLX5_GET_CTR(out, received_eth_unicast.octets);
 160         s->tx_unicast_packets   =
 161                 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 162         s->tx_unicast_bytes     =
 163                 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 164
 165         s->rx_multicast_packets =
 166                 MLX5_GET_CTR(out, received_eth_multicast.packets);
 167         s->rx_multicast_bytes   =
 168                 MLX5_GET_CTR(out, received_eth_multicast.octets);
 169         s->tx_multicast_packets =
 170                 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 171         s->tx_multicast_bytes   =
 172                 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 173
 174         s->rx_broadcast_packets =
 175                 MLX5_GET_CTR(out, received_eth_broadcast.packets);
 176         s->rx_broadcast_bytes   =
 177                 MLX5_GET_CTR(out, received_eth_broadcast.octets);
 178         s->tx_broadcast_packets =
 179                 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 180         s->tx_broadcast_bytes   =
 181                 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 182
 183         s->rx_packets =
 184                 s->rx_unicast_packets +
 185                 s->rx_multicast_packets +
 186                 s->rx_broadcast_packets;
 187         s->rx_bytes =
 188                 s->rx_unicast_bytes +
 189                 s->rx_multicast_bytes +
 190                 s->rx_broadcast_bytes;
 191         s->tx_packets =
 192                 s->tx_unicast_packets +
 193                 s->tx_multicast_packets +
 194                 s->tx_broadcast_packets;
 195         s->tx_bytes =
 196                 s->tx_unicast_bytes +
 197                 s->tx_multicast_bytes +
 198                 s->tx_broadcast_bytes;
 199
 200         /* Update calculated offload counters */
 201         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 202         s->rx_csum_good    = s->rx_packets - s->rx_csum_none;
 203
 204 free_out:
 205         kvfree(out);
 206 }
 207
 208 static void mlx5e_update_stats_work(struct work_struct *work)
 209 {
 210         struct delayed_work *dwork = to_delayed_work(work);
 211         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 212                                                update_stats_work);
 213         mutex_lock(&priv->state_lock);
 214         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 215                 mlx5e_update_stats(priv);
 216                 schedule_delayed_work(dwork,
 217                                       msecs_to_jiffies(
 218                                               MLX5E_UPDATE_STATS_INTERVAL));
 219         }
 220         mutex_unlock(&priv->state_lock);
 221 }
 222
 223 static void __mlx5e_async_event(struct mlx5e_priv *priv,
 224                                 enum mlx5_dev_event event)
 225 {
 226         switch (event) {
 227         case MLX5_DEV_EVENT_PORT_UP:
 228         case MLX5_DEV_EVENT_PORT_DOWN:
 229                 schedule_work(&priv->update_carrier_work);
 230                 break;
 231
 232         default:
 233                 break;
 234         }
 235 }
 236
 237 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 238                               enum mlx5_dev_event event, unsigned long param)
 239 {
 240         struct mlx5e_priv *priv = vpriv;
 241
 242         spin_lock(&priv->async_events_spinlock);
 243         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 244                 __mlx5e_async_event(priv, event);
 245         spin_unlock(&priv->async_events_spinlock);
 246 }
 247
 248 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 249 {
 250         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 251 }
 252
 253 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 254 {
 255         spin_lock_irq(&priv->async_events_spinlock);
 256         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 257         spin_unlock_irq(&priv->async_events_spinlock);
 258 }
 259
 260 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 261 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 262
 263 static int mlx5e_create_rq(struct mlx5e_channel *c,
 264                            struct mlx5e_rq_param *param,
 265                            struct mlx5e_rq *rq)
 266 {
 267         struct mlx5e_priv *priv = c->priv;
 268         struct mlx5_core_dev *mdev = priv->mdev;
 269         void *rqc = param->rqc;
 270         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 271         int wq_sz;
 272         int err;
 273         int i;
 274
 275         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 276                                 &rq->wq_ctrl);
 277         if (err)
 278                 return err;
 279
 280         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 281
 282         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 283         rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 284                                cpu_to_node(c->cpu));
 285         if (!rq->skb) {
 286                 err = -ENOMEM;
 287                 goto err_rq_wq_destroy;
 288         }
 289
 290         rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
 291                                              MLX5E_SW2HW_MTU(priv->netdev->mtu);
 292         rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
 293
 294         for (i = 0; i < wq_sz; i++) {
 295                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 296                 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 297
 298                 wqe->data.lkey       = c->mkey_be;
 299                 wqe->data.byte_count =
 300                         cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 301         }
 302
 303         rq->pdev    = c->pdev;
 304         rq->netdev  = c->netdev;
 305         rq->channel = c;
 306         rq->ix      = c->ix;
 307
 308         return 0;
 309
 310 err_rq_wq_destroy:
 311         mlx5_wq_destroy(&rq->wq_ctrl);
 312
 313         return err;
 314 }
 315
 316 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 317 {
 318         kfree(rq->skb);
 319         mlx5_wq_destroy(&rq->wq_ctrl);
 320 }
 321
 322 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 323 {
 324         struct mlx5e_channel *c = rq->channel;
 325         struct mlx5e_priv *priv = c->priv;
 326         struct mlx5_core_dev *mdev = priv->mdev;
 327
 328         void *in;
 329         void *rqc;
 330         void *wq;
 331         int inlen;
 332         int err;
 333
 334         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 335                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 336         in = mlx5_vzalloc(inlen);
 337         if (!in)
 338                 return -ENOMEM;
 339
 340         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 341         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 342
 343         memcpy(rqc, param->rqc, sizeof(param->rqc));
 344
 345         MLX5_SET(rqc,  rqc, cqn,                c->rq.cq.mcq.cqn);
 346         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 347         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 348         MLX5_SET(wq,   wq,  wq_type,            MLX5_WQ_TYPE_LINKED_LIST);
 349         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 350                                                 PAGE_SHIFT);
 351         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 352
 353         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 354                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 355
 356         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 357
 358         kvfree(in);
 359
 360         return err;
 361 }
 362
 363 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 364 {
 365         struct mlx5e_channel *c = rq->channel;
 366         struct mlx5e_priv *priv = c->priv;
 367         struct mlx5_core_dev *mdev = priv->mdev;
 368
 369         void *in;
 370         void *rqc;
 371         int inlen;
 372         int err;
 373
 374         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 375         in = mlx5_vzalloc(inlen);
 376         if (!in)
 377                 return -ENOMEM;
 378
 379         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 380
 381         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 382         MLX5_SET(rqc, rqc, state, next_state);
 383
 384         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 385
 386         kvfree(in);
 387
 388         return err;
 389 }
 390
 391 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 392 {
 393         struct mlx5e_channel *c = rq->channel;
 394         struct mlx5e_priv *priv = c->priv;
 395         struct mlx5_core_dev *mdev = priv->mdev;
 396
 397         mlx5_core_destroy_rq(mdev, rq->rqn);
 398 }
 399
 400 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 401 {
 402         struct mlx5e_channel *c = rq->channel;
 403         struct mlx5e_priv *priv = c->priv;
 404         struct mlx5_wq_ll *wq = &rq->wq;
 405         int i;
 406
 407         for (i = 0; i < 1000; i++) {
 408                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 409                         return 0;
 410
 411                 msleep(20);
 412         }
 413
 414         return -ETIMEDOUT;
 415 }
 416
 417 static int mlx5e_open_rq(struct mlx5e_channel *c,
 418                          struct mlx5e_rq_param *param,
 419                          struct mlx5e_rq *rq)
 420 {
 421         int err;
 422
 423         err = mlx5e_create_rq(c, param, rq);
 424         if (err)
 425                 return err;
 426
 427         err = mlx5e_enable_rq(rq, param);
 428         if (err)
 429                 goto err_destroy_rq;
 430
 431         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 432         if (err)
 433                 goto err_disable_rq;
 434
 435         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 436         mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
 437
 438         return 0;
 439
 440 err_disable_rq:
 441         mlx5e_disable_rq(rq);
 442 err_destroy_rq:
 443         mlx5e_destroy_rq(rq);
 444
 445         return err;
 446 }
 447
 448 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 449 {
 450         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 451         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 452
 453         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 454         while (!mlx5_wq_ll_is_empty(&rq->wq))
 455                 msleep(20);
 456
 457         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 458         napi_synchronize(&rq->channel->napi);
 459
 460         mlx5e_disable_rq(rq);
 461         mlx5e_destroy_rq(rq);
 462 }
 463
 464 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 465 {
 466         kfree(sq->dma_fifo);
 467         kfree(sq->skb);
 468 }
 469
 470 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 471 {
 472         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 473         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 474
 475         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 476         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 477                                     numa);
 478
 479         if (!sq->skb || !sq->dma_fifo) {
 480                 mlx5e_free_sq_db(sq);
 481                 return -ENOMEM;
 482         }
 483
 484         sq->dma_fifo_mask = df_sz - 1;
 485
 486         return 0;
 487 }
 488
 489 static int mlx5e_create_sq(struct mlx5e_channel *c,
 490                            int tc,
 491                            struct mlx5e_sq_param *param,
 492                            struct mlx5e_sq *sq)
 493 {
 494         struct mlx5e_priv *priv = c->priv;
 495         struct mlx5_core_dev *mdev = priv->mdev;
 496
 497         void *sqc = param->sqc;
 498         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 499         int txq_ix;
 500         int err;
 501
 502         err = mlx5_alloc_map_uar(mdev, &sq->uar);
 503         if (err)
 504                 return err;
 505
 506         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 507                                  &sq->wq_ctrl);
 508         if (err)
 509                 goto err_unmap_free_uar;
 510
 511         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 512         sq->uar_map     = sq->uar.map;
 513         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 514
 515         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 516         if (err)
 517                 goto err_sq_wq_destroy;
 518
 519         txq_ix = c->ix + tc * priv->params.num_channels;
 520         sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 521
 522         sq->pdev    = c->pdev;
 523         sq->mkey_be = c->mkey_be;
 524         sq->channel = c;
 525         sq->tc      = tc;
 526         sq->edge    = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 527         priv->txq_to_sq_map[txq_ix] = sq;
 528
 529         return 0;
 530
 531 err_sq_wq_destroy:
 532         mlx5_wq_destroy(&sq->wq_ctrl);
 533
 534 err_unmap_free_uar:
 535         mlx5_unmap_free_uar(mdev, &sq->uar);
 536
 537         return err;
 538 }
 539
 540 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 541 {
 542         struct mlx5e_channel *c = sq->channel;
 543         struct mlx5e_priv *priv = c->priv;
 544
 545         mlx5e_free_sq_db(sq);
 546         mlx5_wq_destroy(&sq->wq_ctrl);
 547         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 548 }
 549
 550 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 551 {
 552         struct mlx5e_channel *c = sq->channel;
 553         struct mlx5e_priv *priv = c->priv;
 554         struct mlx5_core_dev *mdev = priv->mdev;
 555
 556         void *in;
 557         void *sqc;
 558         void *wq;
 559         int inlen;
 560         int err;
 561
 562         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 563                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 564         in = mlx5_vzalloc(inlen);
 565         if (!in)
 566                 return -ENOMEM;
 567
 568         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 569         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 570
 571         memcpy(sqc, param->sqc, sizeof(param->sqc));
 572
 573         MLX5_SET(sqc,  sqc, user_index,         sq->tc);
 574         MLX5_SET(sqc,  sqc, tis_num_0,          priv->tisn[sq->tc]);
 575         MLX5_SET(sqc,  sqc, cqn,                c->sq[sq->tc].cq.mcq.cqn);
 576         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 577         MLX5_SET(sqc,  sqc, tis_lst_sz,         1);
 578         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 579
 580         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 581         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 582         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 583                                           PAGE_SHIFT);
 584         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 585
 586         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 587                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 588
 589         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 590
 591         kvfree(in);
 592
 593         return err;
 594 }
 595
 596 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 597 {
 598         struct mlx5e_channel *c = sq->channel;
 599         struct mlx5e_priv *priv = c->priv;
 600         struct mlx5_core_dev *mdev = priv->mdev;
 601
 602         void *in;
 603         void *sqc;
 604         int inlen;
 605         int err;
 606
 607         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 608         in = mlx5_vzalloc(inlen);
 609         if (!in)
 610                 return -ENOMEM;
 611
 612         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 613
 614         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 615         MLX5_SET(sqc, sqc, state, next_state);
 616
 617         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 618
 619         kvfree(in);
 620
 621         return err;
 622 }
 623
 624 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 625 {
 626         struct mlx5e_channel *c = sq->channel;
 627         struct mlx5e_priv *priv = c->priv;
 628         struct mlx5_core_dev *mdev = priv->mdev;
 629
 630         mlx5_core_destroy_sq(mdev, sq->sqn);
 631 }
 632
 633 static int mlx5e_open_sq(struct mlx5e_channel *c,
 634                          int tc,
 635                          struct mlx5e_sq_param *param,
 636                          struct mlx5e_sq *sq)
 637 {
 638         int err;
 639
 640         err = mlx5e_create_sq(c, tc, param, sq);
 641         if (err)
 642                 return err;
 643
 644         err = mlx5e_enable_sq(sq, param);
 645         if (err)
 646                 goto err_destroy_sq;
 647
 648         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 649         if (err)
 650                 goto err_disable_sq;
 651
 652         set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 653         netdev_tx_reset_queue(sq->txq);
 654         netif_tx_start_queue(sq->txq);
 655
 656         return 0;
 657
 658 err_disable_sq:
 659         mlx5e_disable_sq(sq);
 660 err_destroy_sq:
 661         mlx5e_destroy_sq(sq);
 662
 663         return err;
 664 }
 665
 666 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 667 {
 668         __netif_tx_lock_bh(txq);
 669         netif_tx_stop_queue(txq);
 670         __netif_tx_unlock_bh(txq);
 671 }
 672
 673 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 674 {
 675         clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 676         napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
 677         netif_tx_disable_queue(sq->txq);
 678
 679         /* ensure hw is notified of all pending wqes */
 680         if (mlx5e_sq_has_room_for(sq, 1))
 681                 mlx5e_send_nop(sq, true);
 682
 683         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 684         while (sq->cc != sq->pc) /* wait till sq is empty */
 685                 msleep(20);
 686
 687         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 688         napi_synchronize(&sq->channel->napi);
 689
 690         mlx5e_disable_sq(sq);
 691         mlx5e_destroy_sq(sq);
 692 }
 693
 694 static int mlx5e_create_cq(struct mlx5e_channel *c,
 695                            struct mlx5e_cq_param *param,
 696                            struct mlx5e_cq *cq)
 697 {
 698         struct mlx5e_priv *priv = c->priv;
 699         struct mlx5_core_dev *mdev = priv->mdev;
 700         struct mlx5_core_cq *mcq = &cq->mcq;
 701         int eqn_not_used;
 702         int irqn;
 703         int err;
 704         u32 i;
 705
 706         param->wq.numa = cpu_to_node(c->cpu);
 707         param->eq_ix   = c->ix;
 708
 709         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 710                                &cq->wq_ctrl);
 711         if (err)
 712                 return err;
 713
 714         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 715
 716         cq->napi        = &c->napi;
 717
 718         mcq->cqe_sz     = 64;
 719         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 720         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 721         *mcq->set_ci_db = 0;
 722         *mcq->arm_db    = 0;
 723         mcq->vector     = param->eq_ix;
 724         mcq->comp       = mlx5e_completion_event;
 725         mcq->event      = mlx5e_cq_error_event;
 726         mcq->irqn       = irqn;
 727         mcq->uar        = &priv->cq_uar;
 728
 729         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 730                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 731
 732                 cqe->op_own = 0xf1;
 733         }
 734
 735         cq->channel = c;
 736
 737         return 0;
 738 }
 739
 740 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 741 {
 742         mlx5_wq_destroy(&cq->wq_ctrl);
 743 }
 744
 745 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 746 {
 747         struct mlx5e_channel *c = cq->channel;
 748         struct mlx5e_priv *priv = c->priv;
 749         struct mlx5_core_dev *mdev = priv->mdev;
 750         struct mlx5_core_cq *mcq = &cq->mcq;
 751
 752         void *in;
 753         void *cqc;
 754         int inlen;
 755         int irqn_not_used;
 756         int eqn;
 757         int err;
 758
 759         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 760                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 761         in = mlx5_vzalloc(inlen);
 762         if (!in)
 763                 return -ENOMEM;
 764
 765         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 766
 767         memcpy(cqc, param->cqc, sizeof(param->cqc));
 768
 769         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 770                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 771
 772         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 773
 774         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 775         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 776         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 777                                             PAGE_SHIFT);
 778         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 779
 780         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 781
 782         kvfree(in);
 783
 784         if (err)
 785                 return err;
 786
 787         mlx5e_cq_arm(cq);
 788
 789         return 0;
 790 }
 791
 792 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 793 {
 794         struct mlx5e_channel *c = cq->channel;
 795         struct mlx5e_priv *priv = c->priv;
 796         struct mlx5_core_dev *mdev = priv->mdev;
 797
 798         mlx5_core_destroy_cq(mdev, &cq->mcq);
 799 }
 800
 801 static int mlx5e_open_cq(struct mlx5e_channel *c,
 802                          struct mlx5e_cq_param *param,
 803                          struct mlx5e_cq *cq,
 804                          u16 moderation_usecs,
 805                          u16 moderation_frames)
 806 {
 807         int err;
 808         struct mlx5e_priv *priv = c->priv;
 809         struct mlx5_core_dev *mdev = priv->mdev;
 810
 811         err = mlx5e_create_cq(c, param, cq);
 812         if (err)
 813                 return err;
 814
 815         err = mlx5e_enable_cq(cq, param);
 816         if (err)
 817                 goto err_destroy_cq;
 818
 819         err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 820                                              moderation_usecs,
 821                                              moderation_frames);
 822         if (err)
 823                 goto err_destroy_cq;
 824
 825         return 0;
 826
 827 err_destroy_cq:
 828         mlx5e_destroy_cq(cq);
 829
 830         return err;
 831 }
 832
 833 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 834 {
 835         mlx5e_disable_cq(cq);
 836         mlx5e_destroy_cq(cq);
 837 }
 838
 839 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 840 {
 841         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 842 }
 843
 844 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 845                              struct mlx5e_channel_param *cparam)
 846 {
 847         struct mlx5e_priv *priv = c->priv;
 848         int err;
 849         int tc;
 850
 851         for (tc = 0; tc < c->num_tc; tc++) {
 852                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 853                                     priv->params.tx_cq_moderation_usec,
 854                                     priv->params.tx_cq_moderation_pkts);
 855                 if (err)
 856                         goto err_close_tx_cqs;
 857
 858                 c->sq[tc].cq.sqrq = &c->sq[tc];
 859         }
 860
 861         return 0;
 862
 863 err_close_tx_cqs:
 864         for (tc--; tc >= 0; tc--)
 865                 mlx5e_close_cq(&c->sq[tc].cq);
 866
 867         return err;
 868 }
 869
 870 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 871 {
 872         int tc;
 873
 874         for (tc = 0; tc < c->num_tc; tc++)
 875                 mlx5e_close_cq(&c->sq[tc].cq);
 876 }
 877
 878 static int mlx5e_open_sqs(struct mlx5e_channel *c,
 879                           struct mlx5e_channel_param *cparam)
 880 {
 881         int err;
 882         int tc;
 883
 884         for (tc = 0; tc < c->num_tc; tc++) {
 885                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
 886                 if (err)
 887                         goto err_close_sqs;
 888         }
 889
 890         return 0;
 891
 892 err_close_sqs:
 893         for (tc--; tc >= 0; tc--)
 894                 mlx5e_close_sq(&c->sq[tc]);
 895
 896         return err;
 897 }
 898
 899 static void mlx5e_close_sqs(struct mlx5e_channel *c)
 900 {
 901         int tc;
 902
 903         for (tc = 0; tc < c->num_tc; tc++)
 904                 mlx5e_close_sq(&c->sq[tc]);
 905 }
 906
 907 static void mlx5e_build_tc_to_txq_map(struct mlx5e_channel *c,
 908                                       int num_channels)
 909 {
 910         int i;
 911
 912         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
 913                 c->tc_to_txq_map[i] = c->ix + i * num_channels;
 914 }
 915
 916 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
 917                               struct mlx5e_channel_param *cparam,
 918                               struct mlx5e_channel **cp)
 919 {
 920         struct net_device *netdev = priv->netdev;
 921         int cpu = mlx5e_get_cpu(priv, ix);
 922         struct mlx5e_channel *c;
 923         int err;
 924
 925         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
 926         if (!c)
 927                 return -ENOMEM;
 928
 929         c->priv     = priv;
 930         c->ix       = ix;
 931         c->cpu      = cpu;
 932         c->pdev     = &priv->mdev->pdev->dev;
 933         c->netdev   = priv->netdev;
 934         c->mkey_be  = cpu_to_be32(priv->mr.key);
 935         c->num_tc   = priv->num_tc;
 936
 937         mlx5e_build_tc_to_txq_map(c, priv->params.num_channels);
 938
 939         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
 940
 941         err = mlx5e_open_tx_cqs(c, cparam);
 942         if (err)
 943                 goto err_napi_del;
 944
 945         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
 946                             priv->params.rx_cq_moderation_usec,
 947                             priv->params.rx_cq_moderation_pkts);
 948         if (err)
 949                 goto err_close_tx_cqs;
 950         c->rq.cq.sqrq = &c->rq;
 951
 952         napi_enable(&c->napi);
 953
 954         err = mlx5e_open_sqs(c, cparam);
 955         if (err)
 956                 goto err_disable_napi;
 957
 958         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
 959         if (err)
 960                 goto err_close_sqs;
 961
 962         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
 963         *cp = c;
 964
 965         return 0;
 966
 967 err_close_sqs:
 968         mlx5e_close_sqs(c);
 969
 970 err_disable_napi:
 971         napi_disable(&c->napi);
 972         mlx5e_close_cq(&c->rq.cq);
 973
 974 err_close_tx_cqs:
 975         mlx5e_close_tx_cqs(c);
 976
 977 err_napi_del:
 978         netif_napi_del(&c->napi);
 979         kfree(c);
 980
 981         return err;
 982 }
 983
 984 static void mlx5e_close_channel(struct mlx5e_channel *c)
 985 {
 986         mlx5e_close_rq(&c->rq);
 987         mlx5e_close_sqs(c);
 988         napi_disable(&c->napi);
 989         mlx5e_close_cq(&c->rq.cq);
 990         mlx5e_close_tx_cqs(c);
 991         netif_napi_del(&c->napi);
 992         kfree(c);
 993 }
 994
 995 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
 996                                  struct mlx5e_rq_param *param)
 997 {
 998         void *rqc = param->rqc;
 999         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1000
1001         MLX5_SET(wq, wq, wq_type,          MLX5_WQ_TYPE_LINKED_LIST);
1002         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1003         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1004         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1005         MLX5_SET(wq, wq, pd,               priv->pdn);
1006
1007         param->wq.numa   = dev_to_node(&priv->mdev->pdev->dev);
1008         param->wq.linear = 1;
1009 }
1010
1011 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1012                                  struct mlx5e_sq_param *param)
1013 {
1014         void *sqc = param->sqc;
1015         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1016
1017         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1018         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1019         MLX5_SET(wq, wq, pd,            priv->pdn);
1020
1021         param->wq.numa = dev_to_node(&priv->mdev->pdev->dev);
1022 }
1023
1024 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1025                                         struct mlx5e_cq_param *param)
1026 {
1027         void *cqc = param->cqc;
1028
1029         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1030 }
1031
1032 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1033                                     struct mlx5e_cq_param *param)
1034 {
1035         void *cqc = param->cqc;
1036
1037         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_rq_size);
1038
1039         mlx5e_build_common_cq_param(priv, param);
1040 }
1041
1042 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1043                                     struct mlx5e_cq_param *param)
1044 {
1045         void *cqc = param->cqc;
1046
1047         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_sq_size);
1048
1049         mlx5e_build_common_cq_param(priv, param);
1050 }
1051
1052 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1053                                       struct mlx5e_channel_param *cparam)
1054 {
1055         memset(cparam, 0, sizeof(*cparam));
1056
1057         mlx5e_build_rq_param(priv, &cparam->rq);
1058         mlx5e_build_sq_param(priv, &cparam->sq);
1059         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1060         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1061 }
1062
1063 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1064 {
1065         struct mlx5e_channel_param cparam;
1066         int err = -ENOMEM;
1067         int i;
1068         int j;
1069
1070         priv->channel = kcalloc(priv->params.num_channels,
1071                                 sizeof(struct mlx5e_channel *), GFP_KERNEL);
1072
1073         priv->txq_to_sq_map = kcalloc(priv->params.num_channels * priv->num_tc,
1074                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1075
1076         if (!priv->channel || !priv->txq_to_sq_map)
1077                 goto err_free_txq_to_sq_map;
1078
1079         mlx5e_build_channel_param(priv, &cparam);
1080         for (i = 0; i < priv->params.num_channels; i++) {
1081                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1082                 if (err)
1083                         goto err_close_channels;
1084         }
1085
1086         for (j = 0; j < priv->params.num_channels; j++) {
1087                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1088                 if (err)
1089                         goto err_close_channels;
1090         }
1091
1092         return 0;
1093
1094 err_close_channels:
1095         for (i--; i >= 0; i--)
1096                 mlx5e_close_channel(priv->channel[i]);
1097
1098 err_free_txq_to_sq_map:
1099         kfree(priv->txq_to_sq_map);
1100         kfree(priv->channel);
1101
1102         return err;
1103 }
1104
1105 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1106 {
1107         int i;
1108
1109         for (i = 0; i < priv->params.num_channels; i++)
1110                 mlx5e_close_channel(priv->channel[i]);
1111
1112         kfree(priv->txq_to_sq_map);
1113         kfree(priv->channel);
1114 }
1115
1116 static int mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1117 {
1118         struct mlx5_core_dev *mdev = priv->mdev;
1119         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1120         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1121
1122         memset(in, 0, sizeof(in));
1123
1124         MLX5_SET(tisc, tisc, prio,  tc);
1125         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1126
1127         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1128 }
1129
1130 static void mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1131 {
1132         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1133 }
1134
1135 static int mlx5e_open_tises(struct mlx5e_priv *priv)
1136 {
1137         int num_tc = priv->num_tc;
1138         int err;
1139         int tc;
1140
1141         for (tc = 0; tc < num_tc; tc++) {
1142                 err = mlx5e_open_tis(priv, tc);
1143                 if (err)
1144                         goto err_close_tises;
1145         }
1146
1147         return 0;
1148
1149 err_close_tises:
1150         for (tc--; tc >= 0; tc--)
1151                 mlx5e_close_tis(priv, tc);
1152
1153         return err;
1154 }
1155
1156 static void mlx5e_close_tises(struct mlx5e_priv *priv)
1157 {
1158         int num_tc = priv->num_tc;
1159         int tc;
1160
1161         for (tc = 0; tc < num_tc; tc++)
1162                 mlx5e_close_tis(priv, tc);
1163 }
1164
1165 static int mlx5e_open_rqt(struct mlx5e_priv *priv)
1166 {
1167         struct mlx5_core_dev *mdev = priv->mdev;
1168         u32 *in;
1169         u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1170         void *rqtc;
1171         int inlen;
1172         int err;
1173         int sz;
1174         int i;
1175
1176         sz = 1 << priv->params.rx_hash_log_tbl_sz;
1177
1178         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1179         in = mlx5_vzalloc(inlen);
1180         if (!in)
1181                 return -ENOMEM;
1182
1183         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1184
1185         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1186         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1187
1188         for (i = 0; i < sz; i++) {
1189                 int ix = i % priv->params.num_channels;
1190
1191                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
1192         }
1193
1194         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1195
1196         memset(out, 0, sizeof(out));
1197         err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
1198         if (!err)
1199                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
1200
1201         kvfree(in);
1202
1203         return err;
1204 }
1205
1206 static void mlx5e_close_rqt(struct mlx5e_priv *priv)
1207 {
1208         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
1209         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
1210
1211         memset(in, 0, sizeof(in));
1212
1213         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
1214         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
1215
1216         mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
1217                                    sizeof(out));
1218 }
1219
1220 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1221 {
1222         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1223
1224         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1225
1226 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1227
1228 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1229                           MLX5_HASH_FIELD_SEL_DST_IP)
1230
1231 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1232                           MLX5_HASH_FIELD_SEL_DST_IP   |\
1233                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
1234                           MLX5_HASH_FIELD_SEL_L4_DPORT)
1235
1236         if (priv->params.lro_en) {
1237                 MLX5_SET(tirc, tirc, lro_enable_mask,
1238                          MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1239                          MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1240                 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1241                          (priv->params.lro_wqe_sz -
1242                           ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1243                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1244                          MLX5_CAP_ETH(priv->mdev,
1245                                       lro_timer_supported_periods[3]));
1246         }
1247
1248         switch (tt) {
1249         case MLX5E_TT_ANY:
1250                 MLX5_SET(tirc, tirc, disp_type,
1251                          MLX5_TIRC_DISP_TYPE_DIRECT);
1252                 MLX5_SET(tirc, tirc, inline_rqn,
1253                          priv->channel[0]->rq.rqn);
1254                 break;
1255         default:
1256                 MLX5_SET(tirc, tirc, disp_type,
1257                          MLX5_TIRC_DISP_TYPE_INDIRECT);
1258                 MLX5_SET(tirc, tirc, indirect_table,
1259                          priv->rqtn);
1260                 MLX5_SET(tirc, tirc, rx_hash_fn,
1261                          MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
1262                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1263                 netdev_rss_key_fill(MLX5_ADDR_OF(tirc, tirc,
1264                                                  rx_hash_toeplitz_key),
1265                                     MLX5_FLD_SZ_BYTES(tirc,
1266                                                       rx_hash_toeplitz_key));
1267                 break;
1268         }
1269
1270         switch (tt) {
1271         case MLX5E_TT_IPV4_TCP:
1272                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1273                          MLX5_L3_PROT_TYPE_IPV4);
1274                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1275                          MLX5_L4_PROT_TYPE_TCP);
1276                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1277                          MLX5_HASH_ALL);
1278                 break;
1279
1280         case MLX5E_TT_IPV6_TCP:
1281                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1282                          MLX5_L3_PROT_TYPE_IPV6);
1283                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1284                          MLX5_L4_PROT_TYPE_TCP);
1285                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1286                          MLX5_HASH_ALL);
1287                 break;
1288
1289         case MLX5E_TT_IPV4_UDP:
1290                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1291                          MLX5_L3_PROT_TYPE_IPV4);
1292                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1293                          MLX5_L4_PROT_TYPE_UDP);
1294                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1295                          MLX5_HASH_ALL);
1296                 break;
1297
1298         case MLX5E_TT_IPV6_UDP:
1299                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1300                          MLX5_L3_PROT_TYPE_IPV6);
1301                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1302                          MLX5_L4_PROT_TYPE_UDP);
1303                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1304                          MLX5_HASH_ALL);
1305                 break;
1306
1307         case MLX5E_TT_IPV4:
1308                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1309                          MLX5_L3_PROT_TYPE_IPV4);
1310                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1311                          MLX5_HASH_IP);
1312                 break;
1313
1314         case MLX5E_TT_IPV6:
1315                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1316                          MLX5_L3_PROT_TYPE_IPV6);
1317                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1318                          MLX5_HASH_IP);
1319                 break;
1320         }
1321 }
1322
1323 static int mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
1324 {
1325         struct mlx5_core_dev *mdev = priv->mdev;
1326         u32 *in;
1327         void *tirc;
1328         int inlen;
1329         int err;
1330
1331         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1332         in = mlx5_vzalloc(inlen);
1333         if (!in)
1334                 return -ENOMEM;
1335
1336         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1337
1338         mlx5e_build_tir_ctx(priv, tirc, tt);
1339
1340         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1341
1342         kvfree(in);
1343
1344         return err;
1345 }
1346
1347 static void mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
1348 {
1349         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1350 }
1351
1352 static int mlx5e_open_tirs(struct mlx5e_priv *priv)
1353 {
1354         int err;
1355         int i;
1356
1357         for (i = 0; i < MLX5E_NUM_TT; i++) {
1358                 err = mlx5e_open_tir(priv, i);
1359                 if (err)
1360                         goto err_close_tirs;
1361         }
1362
1363         return 0;
1364
1365 err_close_tirs:
1366         for (i--; i >= 0; i--)
1367                 mlx5e_close_tir(priv, i);
1368
1369         return err;
1370 }
1371
1372 static void mlx5e_close_tirs(struct mlx5e_priv *priv)
1373 {
1374         int i;
1375
1376         for (i = 0; i < MLX5E_NUM_TT; i++)
1377                 mlx5e_close_tir(priv, i);
1378 }
1379
1380 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1381 {
1382         struct mlx5e_priv *priv = netdev_priv(netdev);
1383         struct mlx5_core_dev *mdev = priv->mdev;
1384         int hw_mtu;
1385         int err;
1386
1387         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1388         if (err)
1389                 return err;
1390
1391         mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1392
1393         if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1394                 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1395                             __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1396
1397         netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1398         return 0;
1399 }
1400
1401 int mlx5e_open_locked(struct net_device *netdev)
1402 {
1403         struct mlx5e_priv *priv = netdev_priv(netdev);
1404         int num_txqs;
1405         int err;
1406
1407         num_txqs = priv->params.num_channels * priv->params.num_tc;
1408         netif_set_real_num_tx_queues(netdev, num_txqs);
1409         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1410
1411         err = mlx5e_set_dev_port_mtu(netdev);
1412         if (err)
1413                 return err;
1414
1415         err = mlx5e_open_tises(priv);
1416         if (err) {
1417                 netdev_err(netdev, "%s: mlx5e_open_tises failed, %d\n",
1418                            __func__, err);
1419                 return err;
1420         }
1421
1422         err = mlx5e_open_channels(priv);
1423         if (err) {
1424                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1425                            __func__, err);
1426                 goto err_close_tises;
1427         }
1428
1429         err = mlx5e_open_rqt(priv);
1430         if (err) {
1431                 netdev_err(netdev, "%s: mlx5e_open_rqt failed, %d\n",
1432                            __func__, err);
1433                 goto err_close_channels;
1434         }
1435
1436         err = mlx5e_open_tirs(priv);
1437         if (err) {
1438                 netdev_err(netdev, "%s: mlx5e_open_tir failed, %d\n",
1439                            __func__, err);
1440                 goto err_close_rqls;
1441         }
1442
1443         err = mlx5e_open_flow_table(priv);
1444         if (err) {
1445                 netdev_err(netdev, "%s: mlx5e_open_flow_table failed, %d\n",
1446                            __func__, err);
1447                 goto err_close_tirs;
1448         }
1449
1450         err = mlx5e_add_all_vlan_rules(priv);
1451         if (err) {
1452                 netdev_err(netdev, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
1453                            __func__, err);
1454                 goto err_close_flow_table;
1455         }
1456
1457         mlx5e_init_eth_addr(priv);
1458
1459         set_bit(MLX5E_STATE_OPENED, &priv->state);
1460
1461         mlx5e_update_carrier(priv);
1462         mlx5e_set_rx_mode_core(priv);
1463
1464         schedule_delayed_work(&priv->update_stats_work, 0);
1465         return 0;
1466
1467 err_close_flow_table:
1468         mlx5e_close_flow_table(priv);
1469
1470 err_close_tirs:
1471         mlx5e_close_tirs(priv);
1472
1473 err_close_rqls:
1474         mlx5e_close_rqt(priv);
1475
1476 err_close_channels:
1477         mlx5e_close_channels(priv);
1478
1479 err_close_tises:
1480         mlx5e_close_tises(priv);
1481
1482         return err;
1483 }
1484
1485 static int mlx5e_open(struct net_device *netdev)
1486 {
1487         struct mlx5e_priv *priv = netdev_priv(netdev);
1488         int err;
1489
1490         mutex_lock(&priv->state_lock);
1491         err = mlx5e_open_locked(netdev);
1492         mutex_unlock(&priv->state_lock);
1493
1494         return err;
1495 }
1496
1497 int mlx5e_close_locked(struct net_device *netdev)
1498 {
1499         struct mlx5e_priv *priv = netdev_priv(netdev);
1500
1501         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1502
1503         mlx5e_set_rx_mode_core(priv);
1504         mlx5e_del_all_vlan_rules(priv);
1505         netif_carrier_off(priv->netdev);
1506         mlx5e_close_flow_table(priv);
1507         mlx5e_close_tirs(priv);
1508         mlx5e_close_rqt(priv);
1509         mlx5e_close_channels(priv);
1510         mlx5e_close_tises(priv);
1511
1512         return 0;
1513 }
1514
1515 static int mlx5e_close(struct net_device *netdev)
1516 {
1517         struct mlx5e_priv *priv = netdev_priv(netdev);
1518         int err;
1519
1520         mutex_lock(&priv->state_lock);
1521         err = mlx5e_close_locked(netdev);
1522         mutex_unlock(&priv->state_lock);
1523
1524         return err;
1525 }
1526
1527 int mlx5e_update_priv_params(struct mlx5e_priv *priv,
1528                              struct mlx5e_params *new_params)
1529 {
1530         int err = 0;
1531         int was_opened;
1532
1533         WARN_ON(!mutex_is_locked(&priv->state_lock));
1534
1535         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1536         if (was_opened)
1537                 mlx5e_close_locked(priv->netdev);
1538
1539         priv->params = *new_params;
1540
1541         if (was_opened)
1542                 err = mlx5e_open_locked(priv->netdev);
1543
1544         return err;
1545 }
1546
1547 static struct rtnl_link_stats64 *
1548 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1549 {
1550         struct mlx5e_priv *priv = netdev_priv(dev);
1551         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1552
1553         stats->rx_packets = vstats->rx_packets;
1554         stats->rx_bytes   = vstats->rx_bytes;
1555         stats->tx_packets = vstats->tx_packets;
1556         stats->tx_bytes   = vstats->tx_bytes;
1557         stats->multicast  = vstats->rx_multicast_packets +
1558                             vstats->tx_multicast_packets;
1559         stats->tx_errors  = vstats->tx_error_packets;
1560         stats->rx_errors  = vstats->rx_error_packets;
1561         stats->tx_dropped = vstats->tx_queue_dropped;
1562         stats->rx_crc_errors = 0;
1563         stats->rx_length_errors = 0;
1564
1565         return stats;
1566 }
1567
1568 static void mlx5e_set_rx_mode(struct net_device *dev)
1569 {
1570         struct mlx5e_priv *priv = netdev_priv(dev);
1571
1572         schedule_work(&priv->set_rx_mode_work);
1573 }
1574
1575 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1576 {
1577         struct mlx5e_priv *priv = netdev_priv(netdev);
1578         struct sockaddr *saddr = addr;
1579
1580         if (!is_valid_ether_addr(saddr->sa_data))
1581                 return -EADDRNOTAVAIL;
1582
1583         netif_addr_lock_bh(netdev);
1584         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1585         netif_addr_unlock_bh(netdev);
1586
1587         schedule_work(&priv->set_rx_mode_work);
1588
1589         return 0;
1590 }
1591
1592 static int mlx5e_set_features(struct net_device *netdev,
1593                               netdev_features_t features)
1594 {
1595         struct mlx5e_priv *priv = netdev_priv(netdev);
1596         netdev_features_t changes = features ^ netdev->features;
1597         struct mlx5e_params new_params;
1598         bool update_params = false;
1599
1600         mutex_lock(&priv->state_lock);
1601         new_params = priv->params;
1602
1603         if (changes & NETIF_F_LRO) {
1604                 new_params.lro_en = !!(features & NETIF_F_LRO);
1605                 update_params = true;
1606         }
1607
1608         if (update_params)
1609                 mlx5e_update_priv_params(priv, &new_params);
1610
1611         if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1612                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1613                         mlx5e_enable_vlan_filter(priv);
1614                 else
1615                         mlx5e_disable_vlan_filter(priv);
1616         }
1617
1618         mutex_unlock(&priv->state_lock);
1619
1620         return 0;
1621 }
1622
1623 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1624 {
1625         struct mlx5e_priv *priv = netdev_priv(netdev);
1626         struct mlx5_core_dev *mdev = priv->mdev;
1627         int max_mtu;
1628         int err;
1629
1630         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
1631
1632         if (new_mtu > max_mtu) {
1633                 netdev_err(netdev,
1634                            "%s: Bad MTU (%d) > (%d) Max\n",
1635                            __func__, new_mtu, max_mtu);
1636                 return -EINVAL;
1637         }
1638
1639         mutex_lock(&priv->state_lock);
1640         netdev->mtu = new_mtu;
1641         err = mlx5e_update_priv_params(priv, &priv->params);
1642         mutex_unlock(&priv->state_lock);
1643
1644         return err;
1645 }
1646
1647 static struct net_device_ops mlx5e_netdev_ops = {
1648         .ndo_open                = mlx5e_open,
1649         .ndo_stop                = mlx5e_close,
1650         .ndo_start_xmit          = mlx5e_xmit,
1651         .ndo_get_stats64         = mlx5e_get_stats,
1652         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
1653         .ndo_set_mac_address     = mlx5e_set_mac,
1654         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
1655         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
1656         .ndo_set_features        = mlx5e_set_features,
1657         .ndo_change_mtu          = mlx5e_change_mtu,
1658 };
1659
1660 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
1661 {
1662         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1663                 return -ENOTSUPP;
1664         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
1665             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
1666             !MLX5_CAP_ETH(mdev, csum_cap) ||
1667             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
1668             !MLX5_CAP_ETH(mdev, vlan_cap) ||
1669             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
1670             MLX5_CAP_FLOWTABLE(mdev,
1671                                flow_table_properties_nic_receive.max_ft_level)
1672                                < 3) {
1673                 mlx5_core_warn(mdev,
1674                                "Not creating net device, some required device capabilities are missing\n");
1675                 return -ENOTSUPP;
1676         }
1677         return 0;
1678 }
1679
1680 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
1681                                     struct net_device *netdev,
1682                                     int num_comp_vectors)
1683 {
1684         struct mlx5e_priv *priv = netdev_priv(netdev);
1685
1686         priv->params.log_sq_size           =
1687                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
1688         priv->params.log_rq_size           =
1689                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
1690         priv->params.rx_cq_moderation_usec =
1691                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
1692         priv->params.rx_cq_moderation_pkts =
1693                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
1694         priv->params.tx_cq_moderation_usec =
1695                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
1696         priv->params.tx_cq_moderation_pkts =
1697                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
1698         priv->params.min_rx_wqes           =
1699                 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
1700         priv->params.rx_hash_log_tbl_sz    =
1701                 (order_base_2(num_comp_vectors) >
1702                  MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
1703                 order_base_2(num_comp_vectors)           :
1704                 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
1705         priv->params.num_tc                = 1;
1706         priv->params.default_vlan_prio     = 0;
1707
1708         priv->params.lro_en = false && !!MLX5_CAP_ETH(priv->mdev, lro_cap);
1709         priv->params.lro_wqe_sz            =
1710                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
1711
1712         priv->mdev                         = mdev;
1713         priv->netdev                       = netdev;
1714         priv->params.num_channels          = num_comp_vectors;
1715         priv->num_tc                       = priv->params.num_tc;
1716         priv->default_vlan_prio            = priv->params.default_vlan_prio;
1717
1718         spin_lock_init(&priv->async_events_spinlock);
1719         mutex_init(&priv->state_lock);
1720
1721         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
1722         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
1723         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
1724 }
1725
1726 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
1727 {
1728         struct mlx5e_priv *priv = netdev_priv(netdev);
1729
1730         mlx5_query_nic_vport_mac_address(priv->mdev, netdev->dev_addr);
1731 }
1732
1733 static void mlx5e_build_netdev(struct net_device *netdev)
1734 {
1735         struct mlx5e_priv *priv = netdev_priv(netdev);
1736         struct mlx5_core_dev *mdev = priv->mdev;
1737
1738         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
1739
1740         if (priv->num_tc > 1) {
1741                 mlx5e_netdev_ops.ndo_select_queue = mlx5e_select_queue;
1742         }
1743
1744         netdev->netdev_ops        = &mlx5e_netdev_ops;
1745         netdev->watchdog_timeo    = 15 * HZ;
1746
1747         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
1748
1749         netdev->vlan_features    |= NETIF_F_SG;
1750         netdev->vlan_features    |= NETIF_F_IP_CSUM;
1751         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
1752         netdev->vlan_features    |= NETIF_F_GRO;
1753         netdev->vlan_features    |= NETIF_F_TSO;
1754         netdev->vlan_features    |= NETIF_F_TSO6;
1755         netdev->vlan_features    |= NETIF_F_RXCSUM;
1756         netdev->vlan_features    |= NETIF_F_RXHASH;
1757
1758         if (!!MLX5_CAP_ETH(mdev, lro_cap))
1759                 netdev->vlan_features    |= NETIF_F_LRO;
1760
1761         netdev->hw_features       = netdev->vlan_features;
1762         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
1763         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
1764
1765         netdev->features          = netdev->hw_features;
1766         if (!priv->params.lro_en)
1767                 netdev->features  &= ~NETIF_F_LRO;
1768
1769         netdev->features         |= NETIF_F_HIGHDMA;
1770
1771         netdev->priv_flags       |= IFF_UNICAST_FLT;
1772
1773         mlx5e_set_netdev_dev_addr(netdev);
1774 }
1775
1776 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
1777                              struct mlx5_core_mr *mr)
1778 {
1779         struct mlx5_core_dev *mdev = priv->mdev;
1780         struct mlx5_create_mkey_mbox_in *in;
1781         int err;
1782
1783         in = mlx5_vzalloc(sizeof(*in));
1784         if (!in)
1785                 return -ENOMEM;
1786
1787         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
1788                         MLX5_PERM_LOCAL_READ  |
1789                         MLX5_ACCESS_MODE_PA;
1790         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
1791         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
1792
1793         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
1794                                     NULL);
1795
1796         kvfree(in);
1797
1798         return err;
1799 }
1800
1801 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
1802 {
1803         struct net_device *netdev;
1804         struct mlx5e_priv *priv;
1805         int ncv = mdev->priv.eq_table.num_comp_vectors;
1806         int err;
1807
1808         if (mlx5e_check_required_hca_cap(mdev))
1809                 return NULL;
1810
1811         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), ncv, ncv);
1812         if (!netdev) {
1813                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
1814                 return NULL;
1815         }
1816
1817         mlx5e_build_netdev_priv(mdev, netdev, ncv);
1818         mlx5e_build_netdev(netdev);
1819
1820         netif_carrier_off(netdev);
1821
1822         priv = netdev_priv(netdev);
1823
1824         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
1825         if (err) {
1826                 netdev_err(netdev, "%s: mlx5_alloc_map_uar failed, %d\n",
1827                            __func__, err);
1828                 goto err_free_netdev;
1829         }
1830
1831         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
1832         if (err) {
1833                 netdev_err(netdev, "%s: mlx5_core_alloc_pd failed, %d\n",
1834                            __func__, err);
1835                 goto err_unmap_free_uar;
1836         }
1837
1838         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
1839         if (err) {
1840                 netdev_err(netdev, "%s: mlx5_alloc_transport_domain failed, %d\n",
1841                            __func__, err);
1842                 goto err_dealloc_pd;
1843         }
1844
1845         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
1846         if (err) {
1847                 netdev_err(netdev, "%s: mlx5e_create_mkey failed, %d\n",
1848                            __func__, err);
1849                 goto err_dealloc_transport_domain;
1850         }
1851
1852         err = register_netdev(netdev);
1853         if (err) {
1854                 netdev_err(netdev, "%s: register_netdev failed, %d\n",
1855                            __func__, err);
1856                 goto err_destroy_mkey;
1857         }
1858
1859         mlx5e_enable_async_events(priv);
1860
1861         return priv;
1862
1863 err_destroy_mkey:
1864         mlx5_core_destroy_mkey(mdev, &priv->mr);
1865
1866 err_dealloc_transport_domain:
1867         mlx5_dealloc_transport_domain(mdev, priv->tdn);
1868
1869 err_dealloc_pd:
1870         mlx5_core_dealloc_pd(mdev, priv->pdn);
1871
1872 err_unmap_free_uar:
1873         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
1874
1875 err_free_netdev:
1876         free_netdev(netdev);
1877
1878         return NULL;
1879 }
1880
1881 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
1882 {
1883         struct mlx5e_priv *priv = vpriv;
1884         struct net_device *netdev = priv->netdev;
1885
1886         unregister_netdev(netdev);
1887         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
1888         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
1889         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
1890         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
1891         mlx5e_disable_async_events(priv);
1892         flush_scheduled_work();
1893         free_netdev(netdev);
1894 }
1895
1896 static void *mlx5e_get_netdev(void *vpriv)
1897 {
1898         struct mlx5e_priv *priv = vpriv;
1899
1900         return priv->netdev;
1901 }
1902
1903 static struct mlx5_interface mlx5e_interface = {
1904         .add       = mlx5e_create_netdev,
1905         .remove    = mlx5e_destroy_netdev,
1906         .event     = mlx5e_async_event,
1907         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
1908         .get_dev   = mlx5e_get_netdev,
1909 };
1910
1911 void mlx5e_init(void)
1912 {
1913         mlx5_register_interface(&mlx5e_interface);
1914 }
1915
1916 void mlx5e_cleanup(void)
1917 {
1918         mlx5_unregister_interface(&mlx5e_interface);
1919 }