drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 struct mlx5e_rq_param {
  43         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  44         struct mlx5_wq_param       wq;
  45 };
  46
  47 struct mlx5e_sq_param {
  48         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  49         struct mlx5_wq_param       wq;
  50         u16                        max_inline;
  51         bool                       icosq;
  52 };
  53
  54 struct mlx5e_cq_param {
  55         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  56         struct mlx5_wq_param       wq;
  57         u16                        eq_ix;
  58 };
  59
  60 struct mlx5e_channel_param {
  61         struct mlx5e_rq_param      rq;
  62         struct mlx5e_sq_param      sq;
  63         struct mlx5e_sq_param      icosq;
  64         struct mlx5e_cq_param      rx_cq;
  65         struct mlx5e_cq_param      tx_cq;
  66         struct mlx5e_cq_param      icosq_cq;
  67 };
  68
  69 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  70 {
  71         struct mlx5_core_dev *mdev = priv->mdev;
  72         u8 port_state;
  73
  74         port_state = mlx5_query_vport_state(mdev,
  75                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  76
  77         if (port_state == VPORT_STATE_UP)
  78                 netif_carrier_on(priv->netdev);
  79         else
  80                 netif_carrier_off(priv->netdev);
  81 }
  82
  83 static void mlx5e_update_carrier_work(struct work_struct *work)
  84 {
  85         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  86                                                update_carrier_work);
  87
  88         mutex_lock(&priv->state_lock);
  89         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  90                 mlx5e_update_carrier(priv);
  91         mutex_unlock(&priv->state_lock);
  92 }
  93
  94 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
  95 {
  96         struct mlx5_core_dev *mdev = priv->mdev;
  97         struct mlx5e_pport_stats *s = &priv->stats.pport;
  98         u32 *in;
  99         u32 *out;
 100         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 101
 102         in  = mlx5_vzalloc(sz);
 103         out = mlx5_vzalloc(sz);
 104         if (!in || !out)
 105                 goto free_out;
 106
 107         MLX5_SET(ppcnt_reg, in, local_port, 1);
 108
 109         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 110         mlx5_core_access_reg(mdev, in, sz, out,
 111                              sz, MLX5_REG_PPCNT, 0, 0);
 112         memcpy(s->IEEE_802_3_counters,
 113                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 114                sizeof(s->IEEE_802_3_counters));
 115
 116         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 117         mlx5_core_access_reg(mdev, in, sz, out,
 118                              sz, MLX5_REG_PPCNT, 0, 0);
 119         memcpy(s->RFC_2863_counters,
 120                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 121                sizeof(s->RFC_2863_counters));
 122
 123         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 124         mlx5_core_access_reg(mdev, in, sz, out,
 125                              sz, MLX5_REG_PPCNT, 0, 0);
 126         memcpy(s->RFC_2819_counters,
 127                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 128                sizeof(s->RFC_2819_counters));
 129
 130 free_out:
 131         kvfree(in);
 132         kvfree(out);
 133 }
 134
 135 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 136 {
 137         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 138
 139         if (!priv->q_counter)
 140                 return;
 141
 142         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 143                                       &qcnt->rx_out_of_buffer);
 144 }
 145
 146 void mlx5e_update_stats(struct mlx5e_priv *priv)
 147 {
 148         struct mlx5_core_dev *mdev = priv->mdev;
 149         struct mlx5e_vport_stats *s = &priv->stats.vport;
 150         struct mlx5e_rq_stats *rq_stats;
 151         struct mlx5e_sq_stats *sq_stats;
 152         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 153         u32 *out;
 154         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 155         u64 tx_offload_none;
 156         int i, j;
 157
 158         out = mlx5_vzalloc(outlen);
 159         if (!out)
 160                 return;
 161
 162         /* Collect firts the SW counters and then HW for consistency */
 163         s->rx_packets           = 0;
 164         s->rx_bytes             = 0;
 165         s->tx_packets           = 0;
 166         s->tx_bytes             = 0;
 167         s->tso_packets          = 0;
 168         s->tso_bytes            = 0;
 169         s->tso_inner_packets    = 0;
 170         s->tso_inner_bytes      = 0;
 171         s->tx_queue_stopped     = 0;
 172         s->tx_queue_wake        = 0;
 173         s->tx_queue_dropped     = 0;
 174         s->tx_csum_inner        = 0;
 175         tx_offload_none         = 0;
 176         s->lro_packets          = 0;
 177         s->lro_bytes            = 0;
 178         s->rx_csum_none         = 0;
 179         s->rx_csum_sw           = 0;
 180         s->rx_wqe_err           = 0;
 181         s->rx_mpwqe_filler      = 0;
 182         s->rx_mpwqe_frag        = 0;
 183         s->rx_buff_alloc_err    = 0;
 184         for (i = 0; i < priv->params.num_channels; i++) {
 185                 rq_stats = &priv->channel[i]->rq.stats;
 186
 187                 s->rx_packets   += rq_stats->packets;
 188                 s->rx_bytes     += rq_stats->bytes;
 189                 s->lro_packets  += rq_stats->lro_packets;
 190                 s->lro_bytes    += rq_stats->lro_bytes;
 191                 s->rx_csum_none += rq_stats->csum_none;
 192                 s->rx_csum_sw   += rq_stats->csum_sw;
 193                 s->rx_wqe_err   += rq_stats->wqe_err;
 194                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 195                 s->rx_mpwqe_frag   += rq_stats->mpwqe_frag;
 196                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 197
 198                 for (j = 0; j < priv->params.num_tc; j++) {
 199                         sq_stats = &priv->channel[i]->sq[j].stats;
 200
 201                         s->tx_packets           += sq_stats->packets;
 202                         s->tx_bytes             += sq_stats->bytes;
 203                         s->tso_packets          += sq_stats->tso_packets;
 204                         s->tso_bytes            += sq_stats->tso_bytes;
 205                         s->tso_inner_packets    += sq_stats->tso_inner_packets;
 206                         s->tso_inner_bytes      += sq_stats->tso_inner_bytes;
 207                         s->tx_queue_stopped     += sq_stats->stopped;
 208                         s->tx_queue_wake        += sq_stats->wake;
 209                         s->tx_queue_dropped     += sq_stats->dropped;
 210                         s->tx_csum_inner        += sq_stats->csum_offload_inner;
 211                         tx_offload_none         += sq_stats->csum_offload_none;
 212                 }
 213         }
 214
 215         /* HW counters */
 216         memset(in, 0, sizeof(in));
 217
 218         MLX5_SET(query_vport_counter_in, in, opcode,
 219                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 220         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 221         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 222
 223         memset(out, 0, outlen);
 224
 225         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 226                 goto free_out;
 227
 228 #define MLX5_GET_CTR(p, x) \
 229         MLX5_GET64(query_vport_counter_out, p, x)
 230
 231         s->rx_error_packets     =
 232                 MLX5_GET_CTR(out, received_errors.packets);
 233         s->rx_error_bytes       =
 234                 MLX5_GET_CTR(out, received_errors.octets);
 235         s->tx_error_packets     =
 236                 MLX5_GET_CTR(out, transmit_errors.packets);
 237         s->tx_error_bytes       =
 238                 MLX5_GET_CTR(out, transmit_errors.octets);
 239
 240         s->rx_unicast_packets   =
 241                 MLX5_GET_CTR(out, received_eth_unicast.packets);
 242         s->rx_unicast_bytes     =
 243                 MLX5_GET_CTR(out, received_eth_unicast.octets);
 244         s->tx_unicast_packets   =
 245                 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 246         s->tx_unicast_bytes     =
 247                 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 248
 249         s->rx_multicast_packets =
 250                 MLX5_GET_CTR(out, received_eth_multicast.packets);
 251         s->rx_multicast_bytes   =
 252                 MLX5_GET_CTR(out, received_eth_multicast.octets);
 253         s->tx_multicast_packets =
 254                 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 255         s->tx_multicast_bytes   =
 256                 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 257
 258         s->rx_broadcast_packets =
 259                 MLX5_GET_CTR(out, received_eth_broadcast.packets);
 260         s->rx_broadcast_bytes   =
 261                 MLX5_GET_CTR(out, received_eth_broadcast.octets);
 262         s->tx_broadcast_packets =
 263                 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 264         s->tx_broadcast_bytes   =
 265                 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 266
 267         /* Update calculated offload counters */
 268         s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
 269         s->rx_csum_good    = s->rx_packets - s->rx_csum_none -
 270                                s->rx_csum_sw;
 271
 272         mlx5e_update_pport_counters(priv);
 273         mlx5e_update_q_counter(priv);
 274
 275 free_out:
 276         kvfree(out);
 277 }
 278
 279 static void mlx5e_update_stats_work(struct work_struct *work)
 280 {
 281         struct delayed_work *dwork = to_delayed_work(work);
 282         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 283                                                update_stats_work);
 284         mutex_lock(&priv->state_lock);
 285         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 286                 mlx5e_update_stats(priv);
 287                 schedule_delayed_work(dwork,
 288                                       msecs_to_jiffies(
 289                                               MLX5E_UPDATE_STATS_INTERVAL));
 290         }
 291         mutex_unlock(&priv->state_lock);
 292 }
 293
 294 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 295                               enum mlx5_dev_event event, unsigned long param)
 296 {
 297         struct mlx5e_priv *priv = vpriv;
 298
 299         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 300                 return;
 301
 302         switch (event) {
 303         case MLX5_DEV_EVENT_PORT_UP:
 304         case MLX5_DEV_EVENT_PORT_DOWN:
 305                 schedule_work(&priv->update_carrier_work);
 306                 break;
 307
 308         default:
 309                 break;
 310         }
 311 }
 312
 313 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 314 {
 315         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 316 }
 317
 318 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 319 {
 320         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 321         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 322 }
 323
 324 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 325 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 326
 327 static int mlx5e_create_rq(struct mlx5e_channel *c,
 328                            struct mlx5e_rq_param *param,
 329                            struct mlx5e_rq *rq)
 330 {
 331         struct mlx5e_priv *priv = c->priv;
 332         struct mlx5_core_dev *mdev = priv->mdev;
 333         void *rqc = param->rqc;
 334         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 335         u32 byte_count;
 336         int wq_sz;
 337         int err;
 338         int i;
 339
 340         param->wq.db_numa_node = cpu_to_node(c->cpu);
 341
 342         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 343                                 &rq->wq_ctrl);
 344         if (err)
 345                 return err;
 346
 347         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 348
 349         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 350
 351         switch (priv->params.rq_wq_type) {
 352         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 353                 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
 354                                             GFP_KERNEL, cpu_to_node(c->cpu));
 355                 if (!rq->wqe_info) {
 356                         err = -ENOMEM;
 357                         goto err_rq_wq_destroy;
 358                 }
 359                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 360                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 361
 362                 rq->wqe_sz = MLX5_MPWRQ_NUM_STRIDES * MLX5_MPWRQ_STRIDE_SIZE;
 363                 byte_count = rq->wqe_sz;
 364                 break;
 365         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 366                 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 367                                        cpu_to_node(c->cpu));
 368                 if (!rq->skb) {
 369                         err = -ENOMEM;
 370                         goto err_rq_wq_destroy;
 371                 }
 372                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 373                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 374
 375                 rq->wqe_sz = (priv->params.lro_en) ?
 376                                 priv->params.lro_wqe_sz :
 377                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 378                 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
 379                 byte_count = rq->wqe_sz;
 380                 byte_count |= MLX5_HW_START_PADDING;
 381         }
 382
 383         for (i = 0; i < wq_sz; i++) {
 384                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 385
 386                 wqe->data.byte_count = cpu_to_be32(byte_count);
 387         }
 388
 389         rq->wq_type = priv->params.rq_wq_type;
 390         rq->pdev    = c->pdev;
 391         rq->netdev  = c->netdev;
 392         rq->tstamp  = &priv->tstamp;
 393         rq->channel = c;
 394         rq->ix      = c->ix;
 395         rq->priv    = c->priv;
 396         rq->mkey_be = c->mkey_be;
 397         rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 398
 399         return 0;
 400
 401 err_rq_wq_destroy:
 402         mlx5_wq_destroy(&rq->wq_ctrl);
 403
 404         return err;
 405 }
 406
 407 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 408 {
 409         switch (rq->wq_type) {
 410         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 411                 kfree(rq->wqe_info);
 412                 break;
 413         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 414                 kfree(rq->skb);
 415         }
 416
 417         mlx5_wq_destroy(&rq->wq_ctrl);
 418 }
 419
 420 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 421 {
 422         struct mlx5e_priv *priv = rq->priv;
 423         struct mlx5_core_dev *mdev = priv->mdev;
 424
 425         void *in;
 426         void *rqc;
 427         void *wq;
 428         int inlen;
 429         int err;
 430
 431         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 432                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 433         in = mlx5_vzalloc(inlen);
 434         if (!in)
 435                 return -ENOMEM;
 436
 437         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 438         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 439
 440         memcpy(rqc, param->rqc, sizeof(param->rqc));
 441
 442         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 443         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 444         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 445         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 446                                                 MLX5_ADAPTER_PAGE_SHIFT);
 447         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 448
 449         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 450                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 451
 452         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 453
 454         kvfree(in);
 455
 456         return err;
 457 }
 458
 459 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 460 {
 461         struct mlx5e_channel *c = rq->channel;
 462         struct mlx5e_priv *priv = c->priv;
 463         struct mlx5_core_dev *mdev = priv->mdev;
 464
 465         void *in;
 466         void *rqc;
 467         int inlen;
 468         int err;
 469
 470         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 471         in = mlx5_vzalloc(inlen);
 472         if (!in)
 473                 return -ENOMEM;
 474
 475         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 476
 477         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 478         MLX5_SET(rqc, rqc, state, next_state);
 479
 480         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 481
 482         kvfree(in);
 483
 484         return err;
 485 }
 486
 487 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 488 {
 489         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 490 }
 491
 492 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 493 {
 494         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 495         struct mlx5e_channel *c = rq->channel;
 496         struct mlx5e_priv *priv = c->priv;
 497         struct mlx5_wq_ll *wq = &rq->wq;
 498
 499         while (time_before(jiffies, exp_time)) {
 500                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 501                         return 0;
 502
 503                 msleep(20);
 504         }
 505
 506         return -ETIMEDOUT;
 507 }
 508
 509 static int mlx5e_open_rq(struct mlx5e_channel *c,
 510                          struct mlx5e_rq_param *param,
 511                          struct mlx5e_rq *rq)
 512 {
 513         struct mlx5e_sq *sq = &c->icosq;
 514         u16 pi = sq->pc & sq->wq.sz_m1;
 515         int err;
 516
 517         err = mlx5e_create_rq(c, param, rq);
 518         if (err)
 519                 return err;
 520
 521         err = mlx5e_enable_rq(rq, param);
 522         if (err)
 523                 goto err_destroy_rq;
 524
 525         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 526         if (err)
 527                 goto err_disable_rq;
 528
 529         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 530
 531         sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
 532         sq->ico_wqe_info[pi].num_wqebbs = 1;
 533         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 534
 535         return 0;
 536
 537 err_disable_rq:
 538         mlx5e_disable_rq(rq);
 539 err_destroy_rq:
 540         mlx5e_destroy_rq(rq);
 541
 542         return err;
 543 }
 544
 545 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 546 {
 547         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 548         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 549
 550         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 551         while (!mlx5_wq_ll_is_empty(&rq->wq))
 552                 msleep(20);
 553
 554         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 555         napi_synchronize(&rq->channel->napi);
 556
 557         mlx5e_disable_rq(rq);
 558         mlx5e_destroy_rq(rq);
 559 }
 560
 561 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 562 {
 563         kfree(sq->wqe_info);
 564         kfree(sq->dma_fifo);
 565         kfree(sq->skb);
 566 }
 567
 568 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 569 {
 570         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 571         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 572
 573         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 574         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 575                                     numa);
 576         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 577                                     numa);
 578
 579         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 580                 mlx5e_free_sq_db(sq);
 581                 return -ENOMEM;
 582         }
 583
 584         sq->dma_fifo_mask = df_sz - 1;
 585
 586         return 0;
 587 }
 588
 589 static int mlx5e_create_sq(struct mlx5e_channel *c,
 590                            int tc,
 591                            struct mlx5e_sq_param *param,
 592                            struct mlx5e_sq *sq)
 593 {
 594         struct mlx5e_priv *priv = c->priv;
 595         struct mlx5_core_dev *mdev = priv->mdev;
 596
 597         void *sqc = param->sqc;
 598         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 599         int err;
 600
 601         err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
 602         if (err)
 603                 return err;
 604
 605         param->wq.db_numa_node = cpu_to_node(c->cpu);
 606
 607         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 608                                  &sq->wq_ctrl);
 609         if (err)
 610                 goto err_unmap_free_uar;
 611
 612         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 613         if (sq->uar.bf_map) {
 614                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 615                 sq->uar_map = sq->uar.bf_map;
 616         } else {
 617                 sq->uar_map = sq->uar.map;
 618         }
 619         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 620         sq->max_inline  = param->max_inline;
 621
 622         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 623         if (err)
 624                 goto err_sq_wq_destroy;
 625
 626         if (param->icosq) {
 627                 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 628
 629                 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
 630                                                 wq_sz,
 631                                                 GFP_KERNEL,
 632                                                 cpu_to_node(c->cpu));
 633                 if (!sq->ico_wqe_info) {
 634                         err = -ENOMEM;
 635                         goto err_free_sq_db;
 636                 }
 637         } else {
 638                 int txq_ix;
 639
 640                 txq_ix = c->ix + tc * priv->params.num_channels;
 641                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 642                 priv->txq_to_sq_map[txq_ix] = sq;
 643         }
 644
 645         sq->pdev      = c->pdev;
 646         sq->tstamp    = &priv->tstamp;
 647         sq->mkey_be   = c->mkey_be;
 648         sq->channel   = c;
 649         sq->tc        = tc;
 650         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 651         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 652
 653         return 0;
 654
 655 err_free_sq_db:
 656         mlx5e_free_sq_db(sq);
 657
 658 err_sq_wq_destroy:
 659         mlx5_wq_destroy(&sq->wq_ctrl);
 660
 661 err_unmap_free_uar:
 662         mlx5_unmap_free_uar(mdev, &sq->uar);
 663
 664         return err;
 665 }
 666
 667 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 668 {
 669         struct mlx5e_channel *c = sq->channel;
 670         struct mlx5e_priv *priv = c->priv;
 671
 672         kfree(sq->ico_wqe_info);
 673         mlx5e_free_sq_db(sq);
 674         mlx5_wq_destroy(&sq->wq_ctrl);
 675         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 676 }
 677
 678 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 679 {
 680         struct mlx5e_channel *c = sq->channel;
 681         struct mlx5e_priv *priv = c->priv;
 682         struct mlx5_core_dev *mdev = priv->mdev;
 683
 684         void *in;
 685         void *sqc;
 686         void *wq;
 687         int inlen;
 688         int err;
 689
 690         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 691                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 692         in = mlx5_vzalloc(inlen);
 693         if (!in)
 694                 return -ENOMEM;
 695
 696         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 697         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 698
 699         memcpy(sqc, param->sqc, sizeof(param->sqc));
 700
 701         MLX5_SET(sqc,  sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
 702         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
 703         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 704         MLX5_SET(sqc,  sqc, tis_lst_sz,         param->icosq ? 0 : 1);
 705         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 706
 707         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 708         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 709         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 710                                           MLX5_ADAPTER_PAGE_SHIFT);
 711         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 712
 713         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 714                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 715
 716         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 717
 718         kvfree(in);
 719
 720         return err;
 721 }
 722
 723 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 724 {
 725         struct mlx5e_channel *c = sq->channel;
 726         struct mlx5e_priv *priv = c->priv;
 727         struct mlx5_core_dev *mdev = priv->mdev;
 728
 729         void *in;
 730         void *sqc;
 731         int inlen;
 732         int err;
 733
 734         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 735         in = mlx5_vzalloc(inlen);
 736         if (!in)
 737                 return -ENOMEM;
 738
 739         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 740
 741         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 742         MLX5_SET(sqc, sqc, state, next_state);
 743
 744         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 745
 746         kvfree(in);
 747
 748         return err;
 749 }
 750
 751 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 752 {
 753         struct mlx5e_channel *c = sq->channel;
 754         struct mlx5e_priv *priv = c->priv;
 755         struct mlx5_core_dev *mdev = priv->mdev;
 756
 757         mlx5_core_destroy_sq(mdev, sq->sqn);
 758 }
 759
 760 static int mlx5e_open_sq(struct mlx5e_channel *c,
 761                          int tc,
 762                          struct mlx5e_sq_param *param,
 763                          struct mlx5e_sq *sq)
 764 {
 765         int err;
 766
 767         err = mlx5e_create_sq(c, tc, param, sq);
 768         if (err)
 769                 return err;
 770
 771         err = mlx5e_enable_sq(sq, param);
 772         if (err)
 773                 goto err_destroy_sq;
 774
 775         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 776         if (err)
 777                 goto err_disable_sq;
 778
 779         if (sq->txq) {
 780                 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 781                 netdev_tx_reset_queue(sq->txq);
 782                 netif_tx_start_queue(sq->txq);
 783         }
 784
 785         return 0;
 786
 787 err_disable_sq:
 788         mlx5e_disable_sq(sq);
 789 err_destroy_sq:
 790         mlx5e_destroy_sq(sq);
 791
 792         return err;
 793 }
 794
 795 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 796 {
 797         __netif_tx_lock_bh(txq);
 798         netif_tx_stop_queue(txq);
 799         __netif_tx_unlock_bh(txq);
 800 }
 801
 802 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 803 {
 804         if (sq->txq) {
 805                 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 806                 /* prevent netif_tx_wake_queue */
 807                 napi_synchronize(&sq->channel->napi);
 808                 netif_tx_disable_queue(sq->txq);
 809
 810                 /* ensure hw is notified of all pending wqes */
 811                 if (mlx5e_sq_has_room_for(sq, 1))
 812                         mlx5e_send_nop(sq, true);
 813
 814                 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 815         }
 816
 817         while (sq->cc != sq->pc) /* wait till sq is empty */
 818                 msleep(20);
 819
 820         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 821         napi_synchronize(&sq->channel->napi);
 822
 823         mlx5e_disable_sq(sq);
 824         mlx5e_destroy_sq(sq);
 825 }
 826
 827 static int mlx5e_create_cq(struct mlx5e_channel *c,
 828                            struct mlx5e_cq_param *param,
 829                            struct mlx5e_cq *cq)
 830 {
 831         struct mlx5e_priv *priv = c->priv;
 832         struct mlx5_core_dev *mdev = priv->mdev;
 833         struct mlx5_core_cq *mcq = &cq->mcq;
 834         int eqn_not_used;
 835         unsigned int irqn;
 836         int err;
 837         u32 i;
 838
 839         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 840         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 841         param->eq_ix   = c->ix;
 842
 843         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 844                                &cq->wq_ctrl);
 845         if (err)
 846                 return err;
 847
 848         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 849
 850         cq->napi        = &c->napi;
 851
 852         mcq->cqe_sz     = 64;
 853         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 854         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 855         *mcq->set_ci_db = 0;
 856         *mcq->arm_db    = 0;
 857         mcq->vector     = param->eq_ix;
 858         mcq->comp       = mlx5e_completion_event;
 859         mcq->event      = mlx5e_cq_error_event;
 860         mcq->irqn       = irqn;
 861         mcq->uar        = &priv->cq_uar;
 862
 863         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 864                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 865
 866                 cqe->op_own = 0xf1;
 867         }
 868
 869         cq->channel = c;
 870         cq->priv = priv;
 871
 872         return 0;
 873 }
 874
 875 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 876 {
 877         mlx5_wq_destroy(&cq->wq_ctrl);
 878 }
 879
 880 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 881 {
 882         struct mlx5e_priv *priv = cq->priv;
 883         struct mlx5_core_dev *mdev = priv->mdev;
 884         struct mlx5_core_cq *mcq = &cq->mcq;
 885
 886         void *in;
 887         void *cqc;
 888         int inlen;
 889         unsigned int irqn_not_used;
 890         int eqn;
 891         int err;
 892
 893         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 894                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 895         in = mlx5_vzalloc(inlen);
 896         if (!in)
 897                 return -ENOMEM;
 898
 899         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 900
 901         memcpy(cqc, param->cqc, sizeof(param->cqc));
 902
 903         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 904                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 905
 906         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 907
 908         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 909         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 910         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 911                                             MLX5_ADAPTER_PAGE_SHIFT);
 912         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 913
 914         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 915
 916         kvfree(in);
 917
 918         if (err)
 919                 return err;
 920
 921         mlx5e_cq_arm(cq);
 922
 923         return 0;
 924 }
 925
 926 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 927 {
 928         struct mlx5e_priv *priv = cq->priv;
 929         struct mlx5_core_dev *mdev = priv->mdev;
 930
 931         mlx5_core_destroy_cq(mdev, &cq->mcq);
 932 }
 933
 934 static int mlx5e_open_cq(struct mlx5e_channel *c,
 935                          struct mlx5e_cq_param *param,
 936                          struct mlx5e_cq *cq,
 937                          u16 moderation_usecs,
 938                          u16 moderation_frames)
 939 {
 940         int err;
 941         struct mlx5e_priv *priv = c->priv;
 942         struct mlx5_core_dev *mdev = priv->mdev;
 943
 944         err = mlx5e_create_cq(c, param, cq);
 945         if (err)
 946                 return err;
 947
 948         err = mlx5e_enable_cq(cq, param);
 949         if (err)
 950                 goto err_destroy_cq;
 951
 952         if (MLX5_CAP_GEN(mdev, cq_moderation))
 953                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 954                                                moderation_usecs,
 955                                                moderation_frames);
 956         return 0;
 957
 958 err_destroy_cq:
 959         mlx5e_destroy_cq(cq);
 960
 961         return err;
 962 }
 963
 964 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 965 {
 966         mlx5e_disable_cq(cq);
 967         mlx5e_destroy_cq(cq);
 968 }
 969
 970 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 971 {
 972         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 973 }
 974
 975 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 976                              struct mlx5e_channel_param *cparam)
 977 {
 978         struct mlx5e_priv *priv = c->priv;
 979         int err;
 980         int tc;
 981
 982         for (tc = 0; tc < c->num_tc; tc++) {
 983                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 984                                     priv->params.tx_cq_moderation_usec,
 985                                     priv->params.tx_cq_moderation_pkts);
 986                 if (err)
 987                         goto err_close_tx_cqs;
 988         }
 989
 990         return 0;
 991
 992 err_close_tx_cqs:
 993         for (tc--; tc >= 0; tc--)
 994                 mlx5e_close_cq(&c->sq[tc].cq);
 995
 996         return err;
 997 }
 998
 999 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1000 {
1001         int tc;
1002
1003         for (tc = 0; tc < c->num_tc; tc++)
1004                 mlx5e_close_cq(&c->sq[tc].cq);
1005 }
1006
1007 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1008                           struct mlx5e_channel_param *cparam)
1009 {
1010         int err;
1011         int tc;
1012
1013         for (tc = 0; tc < c->num_tc; tc++) {
1014                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1015                 if (err)
1016                         goto err_close_sqs;
1017         }
1018
1019         return 0;
1020
1021 err_close_sqs:
1022         for (tc--; tc >= 0; tc--)
1023                 mlx5e_close_sq(&c->sq[tc]);
1024
1025         return err;
1026 }
1027
1028 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1029 {
1030         int tc;
1031
1032         for (tc = 0; tc < c->num_tc; tc++)
1033                 mlx5e_close_sq(&c->sq[tc]);
1034 }
1035
1036 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1037 {
1038         int i;
1039
1040         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
1041                 priv->channeltc_to_txq_map[ix][i] =
1042                         ix + i * priv->params.num_channels;
1043 }
1044
1045 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1046                               struct mlx5e_channel_param *cparam,
1047                               struct mlx5e_channel **cp)
1048 {
1049         struct net_device *netdev = priv->netdev;
1050         int cpu = mlx5e_get_cpu(priv, ix);
1051         struct mlx5e_channel *c;
1052         int err;
1053
1054         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1055         if (!c)
1056                 return -ENOMEM;
1057
1058         c->priv     = priv;
1059         c->ix       = ix;
1060         c->cpu      = cpu;
1061         c->pdev     = &priv->mdev->pdev->dev;
1062         c->netdev   = priv->netdev;
1063         c->mkey_be  = cpu_to_be32(priv->mkey.key);
1064         c->num_tc   = priv->params.num_tc;
1065
1066         mlx5e_build_channeltc_to_txq_map(priv, ix);
1067
1068         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1069
1070         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
1071         if (err)
1072                 goto err_napi_del;
1073
1074         err = mlx5e_open_tx_cqs(c, cparam);
1075         if (err)
1076                 goto err_close_icosq_cq;
1077
1078         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1079                             priv->params.rx_cq_moderation_usec,
1080                             priv->params.rx_cq_moderation_pkts);
1081         if (err)
1082                 goto err_close_tx_cqs;
1083
1084         napi_enable(&c->napi);
1085
1086         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1087         if (err)
1088                 goto err_disable_napi;
1089
1090         err = mlx5e_open_sqs(c, cparam);
1091         if (err)
1092                 goto err_close_icosq;
1093
1094         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1095         if (err)
1096                 goto err_close_sqs;
1097
1098         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1099         *cp = c;
1100
1101         return 0;
1102
1103 err_close_sqs:
1104         mlx5e_close_sqs(c);
1105
1106 err_close_icosq:
1107         mlx5e_close_sq(&c->icosq);
1108
1109 err_disable_napi:
1110         napi_disable(&c->napi);
1111         mlx5e_close_cq(&c->rq.cq);
1112
1113 err_close_tx_cqs:
1114         mlx5e_close_tx_cqs(c);
1115
1116 err_close_icosq_cq:
1117         mlx5e_close_cq(&c->icosq.cq);
1118
1119 err_napi_del:
1120         netif_napi_del(&c->napi);
1121         napi_hash_del(&c->napi);
1122         kfree(c);
1123
1124         return err;
1125 }
1126
1127 static void mlx5e_close_channel(struct mlx5e_channel *c)
1128 {
1129         mlx5e_close_rq(&c->rq);
1130         mlx5e_close_sqs(c);
1131         mlx5e_close_sq(&c->icosq);
1132         napi_disable(&c->napi);
1133         mlx5e_close_cq(&c->rq.cq);
1134         mlx5e_close_tx_cqs(c);
1135         mlx5e_close_cq(&c->icosq.cq);
1136         netif_napi_del(&c->napi);
1137
1138         napi_hash_del(&c->napi);
1139         synchronize_rcu();
1140
1141         kfree(c);
1142 }
1143
1144 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1145                                  struct mlx5e_rq_param *param)
1146 {
1147         void *rqc = param->rqc;
1148         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1149
1150         switch (priv->params.rq_wq_type) {
1151         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1152                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1153                          MLX5_MPWRQ_LOG_NUM_STRIDES - 9);
1154                 MLX5_SET(wq, wq, log_wqe_stride_size,
1155                          MLX5_MPWRQ_LOG_STRIDE_SIZE - 6);
1156                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1157                 break;
1158         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1159                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1160         }
1161
1162         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1163         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1164         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1165         MLX5_SET(wq, wq, pd,               priv->pdn);
1166         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1167
1168         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1169         param->wq.linear = 1;
1170 }
1171
1172 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1173 {
1174         void *rqc = param->rqc;
1175         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1176
1177         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1178         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1179 }
1180
1181 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1182                                         struct mlx5e_sq_param *param)
1183 {
1184         void *sqc = param->sqc;
1185         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1186
1187         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1188         MLX5_SET(wq, wq, pd,            priv->pdn);
1189
1190         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1191 }
1192
1193 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1194                                  struct mlx5e_sq_param *param)
1195 {
1196         void *sqc = param->sqc;
1197         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1198
1199         mlx5e_build_sq_param_common(priv, param);
1200         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1201
1202         param->max_inline = priv->params.tx_max_inline;
1203 }
1204
1205 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1206                                         struct mlx5e_cq_param *param)
1207 {
1208         void *cqc = param->cqc;
1209
1210         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1211 }
1212
1213 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1214                                     struct mlx5e_cq_param *param)
1215 {
1216         void *cqc = param->cqc;
1217         u8 log_cq_size;
1218
1219         switch (priv->params.rq_wq_type) {
1220         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1221                 log_cq_size = priv->params.log_rq_size +
1222                         MLX5_MPWRQ_LOG_NUM_STRIDES;
1223                 break;
1224         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1225                 log_cq_size = priv->params.log_rq_size;
1226         }
1227
1228         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1229
1230         mlx5e_build_common_cq_param(priv, param);
1231 }
1232
1233 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1234                                     struct mlx5e_cq_param *param)
1235 {
1236         void *cqc = param->cqc;
1237
1238         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1239
1240         mlx5e_build_common_cq_param(priv, param);
1241 }
1242
1243 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1244                                      struct mlx5e_cq_param *param,
1245                                      u8 log_wq_size)
1246 {
1247         void *cqc = param->cqc;
1248
1249         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1250
1251         mlx5e_build_common_cq_param(priv, param);
1252 }
1253
1254 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1255                                     struct mlx5e_sq_param *param,
1256                                     u8 log_wq_size)
1257 {
1258         void *sqc = param->sqc;
1259         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1260
1261         mlx5e_build_sq_param_common(priv, param);
1262
1263         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1264         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1265
1266         param->icosq = true;
1267 }
1268
1269 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1270                                       struct mlx5e_channel_param *cparam)
1271 {
1272         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1273
1274         memset(cparam, 0, sizeof(*cparam));
1275
1276         mlx5e_build_rq_param(priv, &cparam->rq);
1277         mlx5e_build_sq_param(priv, &cparam->sq);
1278         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1279         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1280         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1281         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1282 }
1283
1284 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1285 {
1286         struct mlx5e_channel_param cparam;
1287         int nch = priv->params.num_channels;
1288         int err = -ENOMEM;
1289         int i;
1290         int j;
1291
1292         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1293                                 GFP_KERNEL);
1294
1295         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1296                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1297
1298         if (!priv->channel || !priv->txq_to_sq_map)
1299                 goto err_free_txq_to_sq_map;
1300
1301         mlx5e_build_channel_param(priv, &cparam);
1302         for (i = 0; i < nch; i++) {
1303                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1304                 if (err)
1305                         goto err_close_channels;
1306         }
1307
1308         for (j = 0; j < nch; j++) {
1309                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1310                 if (err)
1311                         goto err_close_channels;
1312         }
1313
1314         return 0;
1315
1316 err_close_channels:
1317         for (i--; i >= 0; i--)
1318                 mlx5e_close_channel(priv->channel[i]);
1319
1320 err_free_txq_to_sq_map:
1321         kfree(priv->txq_to_sq_map);
1322         kfree(priv->channel);
1323
1324         return err;
1325 }
1326
1327 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1328 {
1329         int i;
1330
1331         for (i = 0; i < priv->params.num_channels; i++)
1332                 mlx5e_close_channel(priv->channel[i]);
1333
1334         kfree(priv->txq_to_sq_map);
1335         kfree(priv->channel);
1336 }
1337
1338 static int mlx5e_rx_hash_fn(int hfunc)
1339 {
1340         return (hfunc == ETH_RSS_HASH_TOP) ?
1341                MLX5_RX_HASH_FN_TOEPLITZ :
1342                MLX5_RX_HASH_FN_INVERTED_XOR8;
1343 }
1344
1345 static int mlx5e_bits_invert(unsigned long a, int size)
1346 {
1347         int inv = 0;
1348         int i;
1349
1350         for (i = 0; i < size; i++)
1351                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1352
1353         return inv;
1354 }
1355
1356 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1357 {
1358         int i;
1359
1360         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1361                 int ix = i;
1362
1363                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1364                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1365
1366                 ix = priv->params.indirection_rqt[ix];
1367                 MLX5_SET(rqtc, rqtc, rq_num[i],
1368                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1369                          priv->channel[ix]->rq.rqn :
1370                          priv->drop_rq.rqn);
1371         }
1372 }
1373
1374 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1375                                 enum mlx5e_rqt_ix rqt_ix)
1376 {
1377
1378         switch (rqt_ix) {
1379         case MLX5E_INDIRECTION_RQT:
1380                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1381
1382                 break;
1383
1384         default: /* MLX5E_SINGLE_RQ_RQT */
1385                 MLX5_SET(rqtc, rqtc, rq_num[0],
1386                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1387                          priv->channel[0]->rq.rqn :
1388                          priv->drop_rq.rqn);
1389
1390                 break;
1391         }
1392 }
1393
1394 static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1395 {
1396         struct mlx5_core_dev *mdev = priv->mdev;
1397         u32 *in;
1398         void *rqtc;
1399         int inlen;
1400         int sz;
1401         int err;
1402
1403         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1404
1405         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1406         in = mlx5_vzalloc(inlen);
1407         if (!in)
1408                 return -ENOMEM;
1409
1410         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1411
1412         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1413         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1414
1415         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1416
1417         err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
1418
1419         kvfree(in);
1420
1421         return err;
1422 }
1423
1424 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1425 {
1426         struct mlx5_core_dev *mdev = priv->mdev;
1427         u32 *in;
1428         void *rqtc;
1429         int inlen;
1430         int sz;
1431         int err;
1432
1433         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1434
1435         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1436         in = mlx5_vzalloc(inlen);
1437         if (!in)
1438                 return -ENOMEM;
1439
1440         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1441
1442         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1443
1444         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1445
1446         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1447
1448         err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1449
1450         kvfree(in);
1451
1452         return err;
1453 }
1454
1455 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1456 {
1457         mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
1458 }
1459
1460 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1461 {
1462         mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1463         mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1464 }
1465
1466 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1467 {
1468         if (!priv->params.lro_en)
1469                 return;
1470
1471 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1472
1473         MLX5_SET(tirc, tirc, lro_enable_mask,
1474                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1475                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1476         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1477                  (priv->params.lro_wqe_sz -
1478                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1479         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1480                  MLX5_CAP_ETH(priv->mdev,
1481                               lro_timer_supported_periods[2]));
1482 }
1483
1484 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1485 {
1486         MLX5_SET(tirc, tirc, rx_hash_fn,
1487                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1488         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1489                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1490                                              rx_hash_toeplitz_key);
1491                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1492                                                rx_hash_toeplitz_key);
1493
1494                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1495                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1496         }
1497 }
1498
1499 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1500 {
1501         struct mlx5_core_dev *mdev = priv->mdev;
1502
1503         void *in;
1504         void *tirc;
1505         int inlen;
1506         int err;
1507         int tt;
1508
1509         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1510         in = mlx5_vzalloc(inlen);
1511         if (!in)
1512                 return -ENOMEM;
1513
1514         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1515         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1516
1517         mlx5e_build_tir_ctx_lro(tirc, priv);
1518
1519         for (tt = 0; tt < MLX5E_NUM_TT; tt++) {
1520                 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1521                 if (err)
1522                         break;
1523         }
1524
1525         kvfree(in);
1526
1527         return err;
1528 }
1529
1530 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1531                                                   u32 tirn)
1532 {
1533         void *in;
1534         int inlen;
1535         int err;
1536
1537         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1538         in = mlx5_vzalloc(inlen);
1539         if (!in)
1540                 return -ENOMEM;
1541
1542         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1543
1544         err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1545
1546         kvfree(in);
1547
1548         return err;
1549 }
1550
1551 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1552 {
1553         int err;
1554         int i;
1555
1556         for (i = 0; i < MLX5E_NUM_TT; i++) {
1557                 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1558                                                              priv->tirn[i]);
1559                 if (err)
1560                         return err;
1561         }
1562
1563         return 0;
1564 }
1565
1566 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1567 {
1568         struct mlx5e_priv *priv = netdev_priv(netdev);
1569         struct mlx5_core_dev *mdev = priv->mdev;
1570         int hw_mtu;
1571         int err;
1572
1573         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1574         if (err)
1575                 return err;
1576
1577         mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1578
1579         if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1580                 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1581                             __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1582
1583         netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1584         return 0;
1585 }
1586
1587 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1588 {
1589         struct mlx5e_priv *priv = netdev_priv(netdev);
1590         int nch = priv->params.num_channels;
1591         int ntc = priv->params.num_tc;
1592         int tc;
1593
1594         netdev_reset_tc(netdev);
1595
1596         if (ntc == 1)
1597                 return;
1598
1599         netdev_set_num_tc(netdev, ntc);
1600
1601         for (tc = 0; tc < ntc; tc++)
1602                 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1603 }
1604
1605 int mlx5e_open_locked(struct net_device *netdev)
1606 {
1607         struct mlx5e_priv *priv = netdev_priv(netdev);
1608         int num_txqs;
1609         int err;
1610
1611         set_bit(MLX5E_STATE_OPENED, &priv->state);
1612
1613         mlx5e_netdev_set_tcs(netdev);
1614
1615         num_txqs = priv->params.num_channels * priv->params.num_tc;
1616         netif_set_real_num_tx_queues(netdev, num_txqs);
1617         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1618
1619         err = mlx5e_set_dev_port_mtu(netdev);
1620         if (err)
1621                 goto err_clear_state_opened_flag;
1622
1623         err = mlx5e_open_channels(priv);
1624         if (err) {
1625                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1626                            __func__, err);
1627                 goto err_clear_state_opened_flag;
1628         }
1629
1630         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1631         if (err) {
1632                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1633                            __func__, err);
1634                 goto err_close_channels;
1635         }
1636
1637         mlx5e_redirect_rqts(priv);
1638         mlx5e_update_carrier(priv);
1639         mlx5e_timestamp_init(priv);
1640
1641         schedule_delayed_work(&priv->update_stats_work, 0);
1642
1643         return 0;
1644
1645 err_close_channels:
1646         mlx5e_close_channels(priv);
1647 err_clear_state_opened_flag:
1648         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1649         return err;
1650 }
1651
1652 static int mlx5e_open(struct net_device *netdev)
1653 {
1654         struct mlx5e_priv *priv = netdev_priv(netdev);
1655         int err;
1656
1657         mutex_lock(&priv->state_lock);
1658         err = mlx5e_open_locked(netdev);
1659         mutex_unlock(&priv->state_lock);
1660
1661         return err;
1662 }
1663
1664 int mlx5e_close_locked(struct net_device *netdev)
1665 {
1666         struct mlx5e_priv *priv = netdev_priv(netdev);
1667
1668         /* May already be CLOSED in case a previous configuration operation
1669          * (e.g RX/TX queue size change) that involves close&open failed.
1670          */
1671         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1672                 return 0;
1673
1674         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1675
1676         mlx5e_timestamp_cleanup(priv);
1677         netif_carrier_off(priv->netdev);
1678         mlx5e_redirect_rqts(priv);
1679         mlx5e_close_channels(priv);
1680
1681         return 0;
1682 }
1683
1684 static int mlx5e_close(struct net_device *netdev)
1685 {
1686         struct mlx5e_priv *priv = netdev_priv(netdev);
1687         int err;
1688
1689         mutex_lock(&priv->state_lock);
1690         err = mlx5e_close_locked(netdev);
1691         mutex_unlock(&priv->state_lock);
1692
1693         return err;
1694 }
1695
1696 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1697                                 struct mlx5e_rq *rq,
1698                                 struct mlx5e_rq_param *param)
1699 {
1700         struct mlx5_core_dev *mdev = priv->mdev;
1701         void *rqc = param->rqc;
1702         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1703         int err;
1704
1705         param->wq.db_numa_node = param->wq.buf_numa_node;
1706
1707         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1708                                 &rq->wq_ctrl);
1709         if (err)
1710                 return err;
1711
1712         rq->priv = priv;
1713
1714         return 0;
1715 }
1716
1717 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1718                                 struct mlx5e_cq *cq,
1719                                 struct mlx5e_cq_param *param)
1720 {
1721         struct mlx5_core_dev *mdev = priv->mdev;
1722         struct mlx5_core_cq *mcq = &cq->mcq;
1723         int eqn_not_used;
1724         unsigned int irqn;
1725         int err;
1726
1727         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1728                                &cq->wq_ctrl);
1729         if (err)
1730                 return err;
1731
1732         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1733
1734         mcq->cqe_sz     = 64;
1735         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1736         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1737         *mcq->set_ci_db = 0;
1738         *mcq->arm_db    = 0;
1739         mcq->vector     = param->eq_ix;
1740         mcq->comp       = mlx5e_completion_event;
1741         mcq->event      = mlx5e_cq_error_event;
1742         mcq->irqn       = irqn;
1743         mcq->uar        = &priv->cq_uar;
1744
1745         cq->priv = priv;
1746
1747         return 0;
1748 }
1749
1750 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1751 {
1752         struct mlx5e_cq_param cq_param;
1753         struct mlx5e_rq_param rq_param;
1754         struct mlx5e_rq *rq = &priv->drop_rq;
1755         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1756         int err;
1757
1758         memset(&cq_param, 0, sizeof(cq_param));
1759         memset(&rq_param, 0, sizeof(rq_param));
1760         mlx5e_build_drop_rq_param(&rq_param);
1761
1762         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1763         if (err)
1764                 return err;
1765
1766         err = mlx5e_enable_cq(cq, &cq_param);
1767         if (err)
1768                 goto err_destroy_cq;
1769
1770         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1771         if (err)
1772                 goto err_disable_cq;
1773
1774         err = mlx5e_enable_rq(rq, &rq_param);
1775         if (err)
1776                 goto err_destroy_rq;
1777
1778         return 0;
1779
1780 err_destroy_rq:
1781         mlx5e_destroy_rq(&priv->drop_rq);
1782
1783 err_disable_cq:
1784         mlx5e_disable_cq(&priv->drop_rq.cq);
1785
1786 err_destroy_cq:
1787         mlx5e_destroy_cq(&priv->drop_rq.cq);
1788
1789         return err;
1790 }
1791
1792 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1793 {
1794         mlx5e_disable_rq(&priv->drop_rq);
1795         mlx5e_destroy_rq(&priv->drop_rq);
1796         mlx5e_disable_cq(&priv->drop_rq.cq);
1797         mlx5e_destroy_cq(&priv->drop_rq.cq);
1798 }
1799
1800 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1801 {
1802         struct mlx5_core_dev *mdev = priv->mdev;
1803         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1804         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1805
1806         memset(in, 0, sizeof(in));
1807
1808         MLX5_SET(tisc, tisc, prio, tc << 1);
1809         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1810
1811         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1812 }
1813
1814 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1815 {
1816         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1817 }
1818
1819 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1820 {
1821         int err;
1822         int tc;
1823
1824         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1825                 err = mlx5e_create_tis(priv, tc);
1826                 if (err)
1827                         goto err_close_tises;
1828         }
1829
1830         return 0;
1831
1832 err_close_tises:
1833         for (tc--; tc >= 0; tc--)
1834                 mlx5e_destroy_tis(priv, tc);
1835
1836         return err;
1837 }
1838
1839 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1840 {
1841         int tc;
1842
1843         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1844                 mlx5e_destroy_tis(priv, tc);
1845 }
1846
1847 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1848 {
1849         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1850
1851         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1852
1853 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1854                                  MLX5_HASH_FIELD_SEL_DST_IP)
1855
1856 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1857                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1858                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1859                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1860
1861 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1862                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1863                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1864
1865         mlx5e_build_tir_ctx_lro(tirc, priv);
1866
1867         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1868
1869         switch (tt) {
1870         case MLX5E_TT_ANY:
1871                 MLX5_SET(tirc, tirc, indirect_table,
1872                          priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1873                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
1874                 break;
1875         default:
1876                 MLX5_SET(tirc, tirc, indirect_table,
1877                          priv->rqtn[MLX5E_INDIRECTION_RQT]);
1878                 mlx5e_build_tir_ctx_hash(tirc, priv);
1879                 break;
1880         }
1881
1882         switch (tt) {
1883         case MLX5E_TT_IPV4_TCP:
1884                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1885                          MLX5_L3_PROT_TYPE_IPV4);
1886                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1887                          MLX5_L4_PROT_TYPE_TCP);
1888                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1889                          MLX5_HASH_IP_L4PORTS);
1890                 break;
1891
1892         case MLX5E_TT_IPV6_TCP:
1893                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1894                          MLX5_L3_PROT_TYPE_IPV6);
1895                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1896                          MLX5_L4_PROT_TYPE_TCP);
1897                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1898                          MLX5_HASH_IP_L4PORTS);
1899                 break;
1900
1901         case MLX5E_TT_IPV4_UDP:
1902                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1903                          MLX5_L3_PROT_TYPE_IPV4);
1904                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1905                          MLX5_L4_PROT_TYPE_UDP);
1906                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1907                          MLX5_HASH_IP_L4PORTS);
1908                 break;
1909
1910         case MLX5E_TT_IPV6_UDP:
1911                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1912                          MLX5_L3_PROT_TYPE_IPV6);
1913                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1914                          MLX5_L4_PROT_TYPE_UDP);
1915                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1916                          MLX5_HASH_IP_L4PORTS);
1917                 break;
1918
1919         case MLX5E_TT_IPV4_IPSEC_AH:
1920                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1921                          MLX5_L3_PROT_TYPE_IPV4);
1922                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1923                          MLX5_HASH_IP_IPSEC_SPI);
1924                 break;
1925
1926         case MLX5E_TT_IPV6_IPSEC_AH:
1927                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1928                          MLX5_L3_PROT_TYPE_IPV6);
1929                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1930                          MLX5_HASH_IP_IPSEC_SPI);
1931                 break;
1932
1933         case MLX5E_TT_IPV4_IPSEC_ESP:
1934                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1935                          MLX5_L3_PROT_TYPE_IPV4);
1936                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1937                          MLX5_HASH_IP_IPSEC_SPI);
1938                 break;
1939
1940         case MLX5E_TT_IPV6_IPSEC_ESP:
1941                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1942                          MLX5_L3_PROT_TYPE_IPV6);
1943                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1944                          MLX5_HASH_IP_IPSEC_SPI);
1945                 break;
1946
1947         case MLX5E_TT_IPV4:
1948                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1949                          MLX5_L3_PROT_TYPE_IPV4);
1950                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1951                          MLX5_HASH_IP);
1952                 break;
1953
1954         case MLX5E_TT_IPV6:
1955                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1956                          MLX5_L3_PROT_TYPE_IPV6);
1957                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1958                          MLX5_HASH_IP);
1959                 break;
1960         }
1961 }
1962
1963 static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
1964 {
1965         struct mlx5_core_dev *mdev = priv->mdev;
1966         u32 *in;
1967         void *tirc;
1968         int inlen;
1969         int err;
1970
1971         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1972         in = mlx5_vzalloc(inlen);
1973         if (!in)
1974                 return -ENOMEM;
1975
1976         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1977
1978         mlx5e_build_tir_ctx(priv, tirc, tt);
1979
1980         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1981
1982         kvfree(in);
1983
1984         return err;
1985 }
1986
1987 static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
1988 {
1989         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1990 }
1991
1992 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
1993 {
1994         int err;
1995         int i;
1996
1997         for (i = 0; i < MLX5E_NUM_TT; i++) {
1998                 err = mlx5e_create_tir(priv, i);
1999                 if (err)
2000                         goto err_destroy_tirs;
2001         }
2002
2003         return 0;
2004
2005 err_destroy_tirs:
2006         for (i--; i >= 0; i--)
2007                 mlx5e_destroy_tir(priv, i);
2008
2009         return err;
2010 }
2011
2012 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
2013 {
2014         int i;
2015
2016         for (i = 0; i < MLX5E_NUM_TT; i++)
2017                 mlx5e_destroy_tir(priv, i);
2018 }
2019
2020 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2021 {
2022         struct mlx5e_priv *priv = netdev_priv(netdev);
2023         bool was_opened;
2024         int err = 0;
2025
2026         if (tc && tc != MLX5E_MAX_NUM_TC)
2027                 return -EINVAL;
2028
2029         mutex_lock(&priv->state_lock);
2030
2031         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2032         if (was_opened)
2033                 mlx5e_close_locked(priv->netdev);
2034
2035         priv->params.num_tc = tc ? tc : 1;
2036
2037         if (was_opened)
2038                 err = mlx5e_open_locked(priv->netdev);
2039
2040         mutex_unlock(&priv->state_lock);
2041
2042         return err;
2043 }
2044
2045 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2046                               __be16 proto, struct tc_to_netdev *tc)
2047 {
2048         struct mlx5e_priv *priv = netdev_priv(dev);
2049
2050         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2051                 goto mqprio;
2052
2053         switch (tc->type) {
2054         case TC_SETUP_CLSFLOWER:
2055                 switch (tc->cls_flower->command) {
2056                 case TC_CLSFLOWER_REPLACE:
2057                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2058                 case TC_CLSFLOWER_DESTROY:
2059                         return mlx5e_delete_flower(priv, tc->cls_flower);
2060                 }
2061         default:
2062                 return -EOPNOTSUPP;
2063         }
2064
2065 mqprio:
2066         if (tc->type != TC_SETUP_MQPRIO)
2067                 return -EINVAL;
2068
2069         return mlx5e_setup_tc(dev, tc->tc);
2070 }
2071
2072 static struct rtnl_link_stats64 *
2073 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2074 {
2075         struct mlx5e_priv *priv = netdev_priv(dev);
2076         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2077
2078         stats->rx_packets = vstats->rx_packets;
2079         stats->rx_bytes   = vstats->rx_bytes;
2080         stats->tx_packets = vstats->tx_packets;
2081         stats->tx_bytes   = vstats->tx_bytes;
2082         stats->multicast  = vstats->rx_multicast_packets +
2083                             vstats->tx_multicast_packets;
2084         stats->tx_errors  = vstats->tx_error_packets;
2085         stats->rx_errors  = vstats->rx_error_packets;
2086         stats->tx_dropped = vstats->tx_queue_dropped;
2087         stats->rx_crc_errors = 0;
2088         stats->rx_length_errors = 0;
2089
2090         return stats;
2091 }
2092
2093 static void mlx5e_set_rx_mode(struct net_device *dev)
2094 {
2095         struct mlx5e_priv *priv = netdev_priv(dev);
2096
2097         schedule_work(&priv->set_rx_mode_work);
2098 }
2099
2100 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2101 {
2102         struct mlx5e_priv *priv = netdev_priv(netdev);
2103         struct sockaddr *saddr = addr;
2104
2105         if (!is_valid_ether_addr(saddr->sa_data))
2106                 return -EADDRNOTAVAIL;
2107
2108         netif_addr_lock_bh(netdev);
2109         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2110         netif_addr_unlock_bh(netdev);
2111
2112         schedule_work(&priv->set_rx_mode_work);
2113
2114         return 0;
2115 }
2116
2117 static int mlx5e_set_features(struct net_device *netdev,
2118                               netdev_features_t features)
2119 {
2120         struct mlx5e_priv *priv = netdev_priv(netdev);
2121         int err = 0;
2122         netdev_features_t changes = features ^ netdev->features;
2123
2124         mutex_lock(&priv->state_lock);
2125
2126         if (changes & NETIF_F_LRO) {
2127                 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2128
2129                 if (was_opened && (priv->params.rq_wq_type ==
2130                                    MLX5_WQ_TYPE_LINKED_LIST))
2131                         mlx5e_close_locked(priv->netdev);
2132
2133                 priv->params.lro_en = !!(features & NETIF_F_LRO);
2134                 err = mlx5e_modify_tirs_lro(priv);
2135                 if (err)
2136                         mlx5_core_warn(priv->mdev, "lro modify failed, %d\n",
2137                                        err);
2138
2139                 if (was_opened && (priv->params.rq_wq_type ==
2140                                    MLX5_WQ_TYPE_LINKED_LIST))
2141                         err = mlx5e_open_locked(priv->netdev);
2142         }
2143
2144         mutex_unlock(&priv->state_lock);
2145
2146         if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
2147                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
2148                         mlx5e_enable_vlan_filter(priv);
2149                 else
2150                         mlx5e_disable_vlan_filter(priv);
2151         }
2152
2153         if ((changes & NETIF_F_HW_TC) && !(features & NETIF_F_HW_TC) &&
2154             mlx5e_tc_num_filters(priv)) {
2155                 netdev_err(netdev,
2156                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2157                 return -EINVAL;
2158         }
2159
2160         return err;
2161 }
2162
2163 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2164 {
2165         struct mlx5e_priv *priv = netdev_priv(netdev);
2166         struct mlx5_core_dev *mdev = priv->mdev;
2167         bool was_opened;
2168         int max_mtu;
2169         int err = 0;
2170
2171         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2172
2173         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2174
2175         if (new_mtu > max_mtu) {
2176                 netdev_err(netdev,
2177                            "%s: Bad MTU (%d) > (%d) Max\n",
2178                            __func__, new_mtu, max_mtu);
2179                 return -EINVAL;
2180         }
2181
2182         mutex_lock(&priv->state_lock);
2183
2184         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2185         if (was_opened)
2186                 mlx5e_close_locked(netdev);
2187
2188         netdev->mtu = new_mtu;
2189
2190         if (was_opened)
2191                 err = mlx5e_open_locked(netdev);
2192
2193         mutex_unlock(&priv->state_lock);
2194
2195         return err;
2196 }
2197
2198 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2199 {
2200         switch (cmd) {
2201         case SIOCSHWTSTAMP:
2202                 return mlx5e_hwstamp_set(dev, ifr);
2203         case SIOCGHWTSTAMP:
2204                 return mlx5e_hwstamp_get(dev, ifr);
2205         default:
2206                 return -EOPNOTSUPP;
2207         }
2208 }
2209
2210 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2211 {
2212         struct mlx5e_priv *priv = netdev_priv(dev);
2213         struct mlx5_core_dev *mdev = priv->mdev;
2214
2215         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2216 }
2217
2218 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2219 {
2220         struct mlx5e_priv *priv = netdev_priv(dev);
2221         struct mlx5_core_dev *mdev = priv->mdev;
2222
2223         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2224                                            vlan, qos);
2225 }
2226
2227 static int mlx5_vport_link2ifla(u8 esw_link)
2228 {
2229         switch (esw_link) {
2230         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2231                 return IFLA_VF_LINK_STATE_DISABLE;
2232         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2233                 return IFLA_VF_LINK_STATE_ENABLE;
2234         }
2235         return IFLA_VF_LINK_STATE_AUTO;
2236 }
2237
2238 static int mlx5_ifla_link2vport(u8 ifla_link)
2239 {
2240         switch (ifla_link) {
2241         case IFLA_VF_LINK_STATE_DISABLE:
2242                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2243         case IFLA_VF_LINK_STATE_ENABLE:
2244                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2245         }
2246         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2247 }
2248
2249 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2250                                    int link_state)
2251 {
2252         struct mlx5e_priv *priv = netdev_priv(dev);
2253         struct mlx5_core_dev *mdev = priv->mdev;
2254
2255         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2256                                             mlx5_ifla_link2vport(link_state));
2257 }
2258
2259 static int mlx5e_get_vf_config(struct net_device *dev,
2260                                int vf, struct ifla_vf_info *ivi)
2261 {
2262         struct mlx5e_priv *priv = netdev_priv(dev);
2263         struct mlx5_core_dev *mdev = priv->mdev;
2264         int err;
2265
2266         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2267         if (err)
2268                 return err;
2269         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2270         return 0;
2271 }
2272
2273 static int mlx5e_get_vf_stats(struct net_device *dev,
2274                               int vf, struct ifla_vf_stats *vf_stats)
2275 {
2276         struct mlx5e_priv *priv = netdev_priv(dev);
2277         struct mlx5_core_dev *mdev = priv->mdev;
2278
2279         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2280                                             vf_stats);
2281 }
2282
2283 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2284                                  sa_family_t sa_family, __be16 port)
2285 {
2286         struct mlx5e_priv *priv = netdev_priv(netdev);
2287
2288         if (!mlx5e_vxlan_allowed(priv->mdev))
2289                 return;
2290
2291         mlx5e_vxlan_add_port(priv, be16_to_cpu(port));
2292 }
2293
2294 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2295                                  sa_family_t sa_family, __be16 port)
2296 {
2297         struct mlx5e_priv *priv = netdev_priv(netdev);
2298
2299         if (!mlx5e_vxlan_allowed(priv->mdev))
2300                 return;
2301
2302         mlx5e_vxlan_del_port(priv, be16_to_cpu(port));
2303 }
2304
2305 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2306                                                     struct sk_buff *skb,
2307                                                     netdev_features_t features)
2308 {
2309         struct udphdr *udph;
2310         u16 proto;
2311         u16 port = 0;
2312
2313         switch (vlan_get_protocol(skb)) {
2314         case htons(ETH_P_IP):
2315                 proto = ip_hdr(skb)->protocol;
2316                 break;
2317         case htons(ETH_P_IPV6):
2318                 proto = ipv6_hdr(skb)->nexthdr;
2319                 break;
2320         default:
2321                 goto out;
2322         }
2323
2324         if (proto == IPPROTO_UDP) {
2325                 udph = udp_hdr(skb);
2326                 port = be16_to_cpu(udph->dest);
2327         }
2328
2329         /* Verify if UDP port is being offloaded by HW */
2330         if (port && mlx5e_vxlan_lookup_port(priv, port))
2331                 return features;
2332
2333 out:
2334         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2335         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2336 }
2337
2338 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2339                                               struct net_device *netdev,
2340                                               netdev_features_t features)
2341 {
2342         struct mlx5e_priv *priv = netdev_priv(netdev);
2343
2344         features = vlan_features_check(skb, features);
2345         features = vxlan_features_check(skb, features);
2346
2347         /* Validate if the tunneled packet is being offloaded by HW */
2348         if (skb->encapsulation &&
2349             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2350                 return mlx5e_vxlan_features_check(priv, skb, features);
2351
2352         return features;
2353 }
2354
2355 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2356         .ndo_open                = mlx5e_open,
2357         .ndo_stop                = mlx5e_close,
2358         .ndo_start_xmit          = mlx5e_xmit,
2359         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2360         .ndo_select_queue        = mlx5e_select_queue,
2361         .ndo_get_stats64         = mlx5e_get_stats,
2362         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2363         .ndo_set_mac_address     = mlx5e_set_mac,
2364         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2365         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2366         .ndo_set_features        = mlx5e_set_features,
2367         .ndo_change_mtu          = mlx5e_change_mtu,
2368         .ndo_do_ioctl            = mlx5e_ioctl,
2369 };
2370
2371 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2372         .ndo_open                = mlx5e_open,
2373         .ndo_stop                = mlx5e_close,
2374         .ndo_start_xmit          = mlx5e_xmit,
2375         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2376         .ndo_select_queue        = mlx5e_select_queue,
2377         .ndo_get_stats64         = mlx5e_get_stats,
2378         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2379         .ndo_set_mac_address     = mlx5e_set_mac,
2380         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2381         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2382         .ndo_set_features        = mlx5e_set_features,
2383         .ndo_change_mtu          = mlx5e_change_mtu,
2384         .ndo_do_ioctl            = mlx5e_ioctl,
2385         .ndo_add_vxlan_port      = mlx5e_add_vxlan_port,
2386         .ndo_del_vxlan_port      = mlx5e_del_vxlan_port,
2387         .ndo_features_check      = mlx5e_features_check,
2388         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2389         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2390         .ndo_get_vf_config       = mlx5e_get_vf_config,
2391         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2392         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2393 };
2394
2395 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2396 {
2397         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2398                 return -ENOTSUPP;
2399         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2400             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2401             !MLX5_CAP_ETH(mdev, csum_cap) ||
2402             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2403             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2404             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2405             MLX5_CAP_FLOWTABLE(mdev,
2406                                flow_table_properties_nic_receive.max_ft_level)
2407                                < 3) {
2408                 mlx5_core_warn(mdev,
2409                                "Not creating net device, some required device capabilities are missing\n");
2410                 return -ENOTSUPP;
2411         }
2412         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2413                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2414         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2415                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2416
2417         return 0;
2418 }
2419
2420 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2421 {
2422         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2423
2424         return bf_buf_size -
2425                sizeof(struct mlx5e_tx_wqe) +
2426                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2427 }
2428
2429 #ifdef CONFIG_MLX5_CORE_EN_DCB
2430 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2431 {
2432         int i;
2433
2434         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2435         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2436                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2437                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2438                 priv->params.ets.prio_tc[i] = i;
2439         }
2440
2441         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2442         priv->params.ets.prio_tc[0] = 1;
2443         priv->params.ets.prio_tc[1] = 0;
2444 }
2445 #endif
2446
2447 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2448                                    u32 *indirection_rqt, int len,
2449                                    int num_channels)
2450 {
2451         int node = mdev->priv.numa_node;
2452         int node_num_of_cores;
2453         int i;
2454
2455         if (node == -1)
2456                 node = first_online_node;
2457
2458         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2459
2460         if (node_num_of_cores)
2461                 num_channels = min_t(int, num_channels, node_num_of_cores);
2462
2463         for (i = 0; i < len; i++)
2464                 indirection_rqt[i] = i % num_channels;
2465 }
2466
2467 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2468 {
2469         return MLX5_CAP_GEN(mdev, striding_rq) &&
2470                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2471                 MLX5_CAP_ETH(mdev, reg_umr_sq);
2472 }
2473
2474 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2475                                     struct net_device *netdev,
2476                                     int num_channels)
2477 {
2478         struct mlx5e_priv *priv = netdev_priv(netdev);
2479
2480         priv->params.log_sq_size           =
2481                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2482         priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
2483                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2484                 MLX5_WQ_TYPE_LINKED_LIST;
2485
2486         switch (priv->params.rq_wq_type) {
2487         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2488                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2489                 priv->params.lro_en = true;
2490                 break;
2491         default: /* MLX5_WQ_TYPE_LINKED_LIST */
2492                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2493         }
2494
2495         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2496                                             BIT(priv->params.log_rq_size));
2497         priv->params.rx_cq_moderation_usec =
2498                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2499         priv->params.rx_cq_moderation_pkts =
2500                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2501         priv->params.tx_cq_moderation_usec =
2502                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2503         priv->params.tx_cq_moderation_pkts =
2504                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2505         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
2506         priv->params.num_tc                = 1;
2507         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2508
2509         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2510                             sizeof(priv->params.toeplitz_hash_key));
2511
2512         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2513                                       MLX5E_INDIR_RQT_SIZE, num_channels);
2514
2515         priv->params.lro_wqe_sz            =
2516                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2517
2518         priv->mdev                         = mdev;
2519         priv->netdev                       = netdev;
2520         priv->params.num_channels          = num_channels;
2521
2522 #ifdef CONFIG_MLX5_CORE_EN_DCB
2523         mlx5e_ets_init(priv);
2524 #endif
2525
2526         mutex_init(&priv->state_lock);
2527
2528         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2529         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2530         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2531 }
2532
2533 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2534 {
2535         struct mlx5e_priv *priv = netdev_priv(netdev);
2536
2537         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2538         if (is_zero_ether_addr(netdev->dev_addr) &&
2539             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2540                 eth_hw_addr_random(netdev);
2541                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2542         }
2543 }
2544
2545 static void mlx5e_build_netdev(struct net_device *netdev)
2546 {
2547         struct mlx5e_priv *priv = netdev_priv(netdev);
2548         struct mlx5_core_dev *mdev = priv->mdev;
2549
2550         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2551
2552         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2553                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2554 #ifdef CONFIG_MLX5_CORE_EN_DCB
2555                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2556 #endif
2557         } else {
2558                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2559         }
2560
2561         netdev->watchdog_timeo    = 15 * HZ;
2562
2563         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
2564
2565         netdev->vlan_features    |= NETIF_F_SG;
2566         netdev->vlan_features    |= NETIF_F_IP_CSUM;
2567         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
2568         netdev->vlan_features    |= NETIF_F_GRO;
2569         netdev->vlan_features    |= NETIF_F_TSO;
2570         netdev->vlan_features    |= NETIF_F_TSO6;
2571         netdev->vlan_features    |= NETIF_F_RXCSUM;
2572         netdev->vlan_features    |= NETIF_F_RXHASH;
2573
2574         if (!!MLX5_CAP_ETH(mdev, lro_cap))
2575                 netdev->vlan_features    |= NETIF_F_LRO;
2576
2577         netdev->hw_features       = netdev->vlan_features;
2578         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
2579         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
2580         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
2581
2582         if (mlx5e_vxlan_allowed(mdev)) {
2583                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL;
2584                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2585                 netdev->hw_enc_features |= NETIF_F_RXCSUM;
2586                 netdev->hw_enc_features |= NETIF_F_TSO;
2587                 netdev->hw_enc_features |= NETIF_F_TSO6;
2588                 netdev->hw_enc_features |= NETIF_F_RXHASH;
2589                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2590         }
2591
2592         netdev->features          = netdev->hw_features;
2593         if (!priv->params.lro_en)
2594                 netdev->features  &= ~NETIF_F_LRO;
2595
2596 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2597         if (FT_CAP(flow_modify_en) &&
2598             FT_CAP(modify_root) &&
2599             FT_CAP(identified_miss_table_mode) &&
2600             FT_CAP(flow_table_modify))
2601                 priv->netdev->hw_features      |= NETIF_F_HW_TC;
2602
2603         netdev->features         |= NETIF_F_HIGHDMA;
2604
2605         netdev->priv_flags       |= IFF_UNICAST_FLT;
2606
2607         mlx5e_set_netdev_dev_addr(netdev);
2608 }
2609
2610 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2611                              struct mlx5_core_mkey *mkey)
2612 {
2613         struct mlx5_core_dev *mdev = priv->mdev;
2614         struct mlx5_create_mkey_mbox_in *in;
2615         int err;
2616
2617         in = mlx5_vzalloc(sizeof(*in));
2618         if (!in)
2619                 return -ENOMEM;
2620
2621         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2622                         MLX5_PERM_LOCAL_READ  |
2623                         MLX5_ACCESS_MODE_PA;
2624         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2625         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2626
2627         err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
2628                                     NULL);
2629
2630         kvfree(in);
2631
2632         return err;
2633 }
2634
2635 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2636 {
2637         struct mlx5_core_dev *mdev = priv->mdev;
2638         int err;
2639
2640         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2641         if (err) {
2642                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2643                 priv->q_counter = 0;
2644         }
2645 }
2646
2647 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2648 {
2649         if (!priv->q_counter)
2650                 return;
2651
2652         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2653 }
2654
2655 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
2656 {
2657         struct mlx5_core_dev *mdev = priv->mdev;
2658         struct mlx5_create_mkey_mbox_in *in;
2659         struct mlx5_mkey_seg *mkc;
2660         int inlen = sizeof(*in);
2661         u64 npages =
2662                 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
2663         int err;
2664
2665         in = mlx5_vzalloc(inlen);
2666         if (!in)
2667                 return -ENOMEM;
2668
2669         mkc = &in->seg;
2670         mkc->status = MLX5_MKEY_STATUS_FREE;
2671         mkc->flags = MLX5_PERM_UMR_EN |
2672                      MLX5_PERM_LOCAL_READ |
2673                      MLX5_PERM_LOCAL_WRITE |
2674                      MLX5_ACCESS_MODE_MTT;
2675
2676         mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2677         mkc->flags_pd = cpu_to_be32(priv->pdn);
2678         mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
2679         mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
2680         mkc->log2_page_size = PAGE_SHIFT;
2681
2682         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
2683                                     NULL, NULL);
2684
2685         kvfree(in);
2686
2687         return err;
2688 }
2689
2690 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2691 {
2692         struct net_device *netdev;
2693         struct mlx5e_priv *priv;
2694         int nch = mlx5e_get_max_num_channels(mdev);
2695         int err;
2696
2697         if (mlx5e_check_required_hca_cap(mdev))
2698                 return NULL;
2699
2700         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2701                                     nch * MLX5E_MAX_NUM_TC,
2702                                     nch);
2703         if (!netdev) {
2704                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2705                 return NULL;
2706         }
2707
2708         mlx5e_build_netdev_priv(mdev, netdev, nch);
2709         mlx5e_build_netdev(netdev);
2710
2711         netif_carrier_off(netdev);
2712
2713         priv = netdev_priv(netdev);
2714
2715         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
2716         if (err) {
2717                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2718                 goto err_free_netdev;
2719         }
2720
2721         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2722         if (err) {
2723                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2724                 goto err_unmap_free_uar;
2725         }
2726
2727         err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
2728         if (err) {
2729                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2730                 goto err_dealloc_pd;
2731         }
2732
2733         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
2734         if (err) {
2735                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2736                 goto err_dealloc_transport_domain;
2737         }
2738
2739         err = mlx5e_create_umr_mkey(priv);
2740         if (err) {
2741                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
2742                 goto err_destroy_mkey;
2743         }
2744
2745         err = mlx5e_create_tises(priv);
2746         if (err) {
2747                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2748                 goto err_destroy_umr_mkey;
2749         }
2750
2751         err = mlx5e_open_drop_rq(priv);
2752         if (err) {
2753                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2754                 goto err_destroy_tises;
2755         }
2756
2757         err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
2758         if (err) {
2759                 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
2760                 goto err_close_drop_rq;
2761         }
2762
2763         err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2764         if (err) {
2765                 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2766                 goto err_destroy_rqt_indir;
2767         }
2768
2769         err = mlx5e_create_tirs(priv);
2770         if (err) {
2771                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2772                 goto err_destroy_rqt_single;
2773         }
2774
2775         err = mlx5e_create_flow_tables(priv);
2776         if (err) {
2777                 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2778                 goto err_destroy_tirs;
2779         }
2780
2781         mlx5e_create_q_counter(priv);
2782
2783         mlx5e_init_eth_addr(priv);
2784
2785         mlx5e_vxlan_init(priv);
2786
2787         err = mlx5e_tc_init(priv);
2788         if (err)
2789                 goto err_dealloc_q_counters;
2790
2791 #ifdef CONFIG_MLX5_CORE_EN_DCB
2792         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2793 #endif
2794
2795         err = register_netdev(netdev);
2796         if (err) {
2797                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2798                 goto err_tc_cleanup;
2799         }
2800
2801         if (mlx5e_vxlan_allowed(mdev))
2802                 vxlan_get_rx_port(netdev);
2803
2804         mlx5e_enable_async_events(priv);
2805         schedule_work(&priv->set_rx_mode_work);
2806
2807         return priv;
2808
2809 err_tc_cleanup:
2810         mlx5e_tc_cleanup(priv);
2811
2812 err_dealloc_q_counters:
2813         mlx5e_destroy_q_counter(priv);
2814         mlx5e_destroy_flow_tables(priv);
2815
2816 err_destroy_tirs:
2817         mlx5e_destroy_tirs(priv);
2818
2819 err_destroy_rqt_single:
2820         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2821
2822 err_destroy_rqt_indir:
2823         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2824
2825 err_close_drop_rq:
2826         mlx5e_close_drop_rq(priv);
2827
2828 err_destroy_tises:
2829         mlx5e_destroy_tises(priv);
2830
2831 err_destroy_umr_mkey:
2832         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
2833
2834 err_destroy_mkey:
2835         mlx5_core_destroy_mkey(mdev, &priv->mkey);
2836
2837 err_dealloc_transport_domain:
2838         mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
2839
2840 err_dealloc_pd:
2841         mlx5_core_dealloc_pd(mdev, priv->pdn);
2842
2843 err_unmap_free_uar:
2844         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2845
2846 err_free_netdev:
2847         free_netdev(netdev);
2848
2849         return NULL;
2850 }
2851
2852 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2853 {
2854         struct mlx5e_priv *priv = vpriv;
2855         struct net_device *netdev = priv->netdev;
2856
2857         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2858
2859         schedule_work(&priv->set_rx_mode_work);
2860         mlx5e_disable_async_events(priv);
2861         flush_scheduled_work();
2862         unregister_netdev(netdev);
2863         mlx5e_tc_cleanup(priv);
2864         mlx5e_vxlan_cleanup(priv);
2865         mlx5e_destroy_q_counter(priv);
2866         mlx5e_destroy_flow_tables(priv);
2867         mlx5e_destroy_tirs(priv);
2868         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2869         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2870         mlx5e_close_drop_rq(priv);
2871         mlx5e_destroy_tises(priv);
2872         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
2873         mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
2874         mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
2875         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2876         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2877         free_netdev(netdev);
2878 }
2879
2880 static void *mlx5e_get_netdev(void *vpriv)
2881 {
2882         struct mlx5e_priv *priv = vpriv;
2883
2884         return priv->netdev;
2885 }
2886
2887 static struct mlx5_interface mlx5e_interface = {
2888         .add       = mlx5e_create_netdev,
2889         .remove    = mlx5e_destroy_netdev,
2890         .event     = mlx5e_async_event,
2891         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
2892         .get_dev   = mlx5e_get_netdev,
2893 };
2894
2895 void mlx5e_init(void)
2896 {
2897         mlx5_register_interface(&mlx5e_interface);
2898 }
2899
2900 void mlx5e_cleanup(void)
2901 {
2902         mlx5_unregister_interface(&mlx5e_interface);
2903 }