2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/ipv6.h>
35 #include <linux/tcp.h>
36 #include <net/busy_poll.h>
40 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp)
42 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL;
45 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
48 u32 ci = cqcc & cq->wq.sz_m1;
50 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
53 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
54 struct mlx5e_cq *cq, u32 cqcc)
56 mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
57 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt);
58 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
59 rq->stats.cqe_compress_blks++;
62 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
64 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
68 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
70 u8 op_own = (cqcc >> cq->wq.log_sz) & 1;
71 u32 wq_sz = 1 << cq->wq.log_sz;
72 u32 ci = cqcc & cq->wq.sz_m1;
73 u32 ci_top = min_t(u32, wq_sz, ci + n);
75 for (; ci < ci_top; ci++, n--) {
76 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
81 if (unlikely(ci == wq_sz)) {
83 for (ci = 0; ci < n; ci++) {
84 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
91 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
92 struct mlx5e_cq *cq, u32 cqcc)
96 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
97 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum;
98 cq->title.op_own &= 0xf0;
99 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz);
100 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter);
103 rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
104 mpwrq_get_cqe_consumed_strides(&cq->title) : 1;
105 cq->decmprs_wqe_counter =
106 (cq->decmprs_wqe_counter + wqe_cnt_step) & rq->wq.sz_m1;
109 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
110 struct mlx5e_cq *cq, u32 cqcc)
112 mlx5e_decompress_cqe(rq, cq, cqcc);
113 cq->title.rss_hash_type = 0;
114 cq->title.rss_hash_result = 0;
117 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
119 int update_owner_only,
122 u32 cqcc = cq->wq.cc + update_owner_only;
126 cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
128 for (i = update_owner_only; i < cqe_count;
129 i++, cq->mini_arr_idx++, cqcc++) {
130 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
131 mlx5e_read_mini_arr_slot(cq, cqcc);
133 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
134 rq->handle_rx_cqe(rq, &cq->title);
136 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
138 cq->decmprs_left -= cqe_count;
139 rq->stats.cqe_compress_pkts += cqe_count;
144 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
148 mlx5e_read_title_slot(rq, cq, cq->wq.cc);
149 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
150 mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
151 rq->handle_rx_cqe(rq, &cq->title);
154 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
157 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val)
161 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
164 mutex_lock(&priv->state_lock);
166 if (priv->params.rx_cqe_compress == val)
169 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
171 mlx5e_close_locked(priv->netdev);
173 priv->params.rx_cqe_compress = val;
176 mlx5e_open_locked(priv->netdev);
179 mutex_unlock(&priv->state_lock);
182 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
187 skb = napi_alloc_skb(rq->cq.napi, rq->wqe_sz);
191 dma_addr = dma_map_single(rq->pdev,
192 /* hw start padding */
198 if (unlikely(dma_mapping_error(rq->pdev, dma_addr)))
201 *((dma_addr_t *)skb->cb) = dma_addr;
202 wqe->data.addr = cpu_to_be64(dma_addr);
214 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
216 struct sk_buff *skb = rq->skb[ix];
220 dma_unmap_single(rq->pdev,
221 *((dma_addr_t *)skb->cb),
228 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq)
230 return rq->mpwqe_num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER;
233 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq,
235 struct mlx5e_mpw_info *wi,
236 u32 page_idx, u32 frag_offset,
239 unsigned int truesize = ALIGN(len, rq->mpwqe_stride_sz);
241 dma_sync_single_for_cpu(rq->pdev,
242 wi->umr.dma_info[page_idx].addr + frag_offset,
243 len, DMA_FROM_DEVICE);
244 wi->skbs_frags[page_idx]++;
245 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
246 wi->umr.dma_info[page_idx].page, frag_offset,
251 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
253 struct mlx5e_mpw_info *wi,
254 u32 page_idx, u32 offset,
257 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
258 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx];
261 /* Aligning len to sizeof(long) optimizes memcpy performance */
262 len = ALIGN(headlen_pg, sizeof(long));
263 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
265 skb_copy_to_linear_data_offset(skb, 0,
266 page_address(dma_info->page) + offset,
268 if (unlikely(offset + headlen > PAGE_SIZE)) {
271 len = ALIGN(headlen - headlen_pg, sizeof(long));
272 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
274 skb_copy_to_linear_data_offset(skb, headlen_pg,
275 page_address(dma_info->page),
280 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix)
282 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
283 struct mlx5e_sq *sq = &rq->channel->icosq;
284 struct mlx5_wq_cyc *wq = &sq->wq;
285 struct mlx5e_umr_wqe *wqe;
286 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB);
289 /* fill sq edge with nops to avoid wqe wrap around */
290 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
291 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
292 sq->ico_wqe_info[pi].num_wqebbs = 1;
293 mlx5e_send_nop(sq, true);
296 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
297 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe));
298 wqe->ctrl.opmod_idx_opcode =
299 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
302 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_UMR;
303 sq->ico_wqe_info[pi].num_wqebbs = num_wqebbs;
304 sq->pc += num_wqebbs;
305 mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0);
308 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
309 struct mlx5e_dma_info *dma_info)
311 struct page *page = dev_alloc_page();
316 dma_info->page = page;
317 dma_info->addr = dma_map_page(rq->pdev, page, 0, PAGE_SIZE,
319 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
327 static inline void mlx5e_page_release(struct mlx5e_rq *rq,
328 struct mlx5e_dma_info *dma_info)
330 dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, DMA_FROM_DEVICE);
331 put_page(dma_info->page);
334 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq,
335 struct mlx5e_rx_wqe *wqe,
338 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
339 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, ix) << PAGE_SHIFT;
340 int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
344 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
345 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i];
347 err = mlx5e_page_alloc_mapped(rq, dma_info);
350 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
351 page_ref_add(dma_info->page, pg_strides);
352 wi->skbs_frags[i] = 0;
355 wi->consumed_strides = 0;
356 wqe->data.addr = cpu_to_be64(dma_offset);
362 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i];
364 page_ref_sub(dma_info->page, pg_strides);
365 mlx5e_page_release(rq, dma_info);
371 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
373 int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
376 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
377 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i];
379 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]);
380 mlx5e_page_release(rq, dma_info);
384 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
386 struct mlx5_wq_ll *wq = &rq->wq;
387 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
389 clear_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
391 if (unlikely(test_bit(MLX5E_RQ_STATE_FLUSH, &rq->state))) {
392 mlx5e_free_rx_mpwqe(rq, &rq->wqe_info[wq->head]);
396 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
398 /* ensure wqes are visible to device before updating doorbell record */
401 mlx5_wq_ll_update_db_record(wq);
404 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
408 err = mlx5e_alloc_rx_umr_mpwqe(rq, wqe, ix);
411 set_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
412 mlx5e_post_umr_wqe(rq, ix);
416 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
418 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
420 mlx5e_free_rx_mpwqe(rq, wi);
423 #define RQ_CANNOT_POST(rq) \
424 (test_bit(MLX5E_RQ_STATE_FLUSH, &rq->state) || \
425 test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
427 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
429 struct mlx5_wq_ll *wq = &rq->wq;
431 if (unlikely(RQ_CANNOT_POST(rq)))
434 while (!mlx5_wq_ll_is_full(wq)) {
435 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
438 err = rq->alloc_wqe(rq, wqe, wq->head);
442 rq->stats.buff_alloc_err++;
446 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
449 /* ensure wqes are visible to device before updating doorbell record */
452 mlx5_wq_ll_update_db_record(wq);
454 return !mlx5_wq_ll_is_full(wq);
457 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
460 struct ethhdr *eth = (struct ethhdr *)(skb->data);
462 struct ipv6hdr *ipv6;
464 int network_depth = 0;
468 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
469 int tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) ||
470 (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type));
472 skb->mac_len = ETH_HLEN;
473 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
475 ipv4 = (struct iphdr *)(skb->data + network_depth);
476 ipv6 = (struct ipv6hdr *)(skb->data + network_depth);
477 tot_len = cqe_bcnt - network_depth;
479 if (proto == htons(ETH_P_IP)) {
480 tcp = (struct tcphdr *)(skb->data + network_depth +
481 sizeof(struct iphdr));
483 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
485 tcp = (struct tcphdr *)(skb->data + network_depth +
486 sizeof(struct ipv6hdr));
488 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
491 if (get_cqe_lro_tcppsh(cqe))
496 tcp->ack_seq = cqe->lro_ack_seq_num;
497 tcp->window = cqe->lro_tcp_win;
501 ipv4->ttl = cqe->lro_min_ttl;
502 ipv4->tot_len = cpu_to_be16(tot_len);
504 ipv4->check = ip_fast_csum((unsigned char *)ipv4,
507 ipv6->hop_limit = cqe->lro_min_ttl;
508 ipv6->payload_len = cpu_to_be16(tot_len -
509 sizeof(struct ipv6hdr));
513 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
516 u8 cht = cqe->rss_hash_type;
517 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
518 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
520 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
523 static inline bool is_first_ethertype_ip(struct sk_buff *skb)
525 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
527 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
530 static inline void mlx5e_handle_csum(struct net_device *netdev,
531 struct mlx5_cqe64 *cqe,
536 if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
540 skb->ip_summed = CHECKSUM_UNNECESSARY;
544 if (is_first_ethertype_ip(skb)) {
545 skb->ip_summed = CHECKSUM_COMPLETE;
546 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
547 rq->stats.csum_complete++;
551 if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
552 (cqe->hds_ip_ext & CQE_L4_OK))) {
553 skb->ip_summed = CHECKSUM_UNNECESSARY;
554 if (cqe_is_tunneled(cqe)) {
556 skb->encapsulation = 1;
557 rq->stats.csum_unnecessary_inner++;
562 skb->ip_summed = CHECKSUM_NONE;
563 rq->stats.csum_none++;
566 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
571 struct net_device *netdev = rq->netdev;
572 struct mlx5e_tstamp *tstamp = rq->tstamp;
575 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
576 if (lro_num_seg > 1) {
577 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
578 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
579 rq->stats.lro_packets++;
580 rq->stats.lro_bytes += cqe_bcnt;
583 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
584 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb));
586 skb_record_rx_queue(skb, rq->ix);
588 if (likely(netdev->features & NETIF_F_RXHASH))
589 mlx5e_skb_set_hash(cqe, skb);
591 if (cqe_has_vlan(cqe))
592 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
593 be16_to_cpu(cqe->vlan_info));
595 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
597 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
598 skb->protocol = eth_type_trans(skb, netdev);
601 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
602 struct mlx5_cqe64 *cqe,
607 rq->stats.bytes += cqe_bcnt;
608 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
609 napi_gro_receive(rq->cq.napi, skb);
612 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
614 struct mlx5e_rx_wqe *wqe;
616 __be16 wqe_counter_be;
620 wqe_counter_be = cqe->wqe_counter;
621 wqe_counter = be16_to_cpu(wqe_counter_be);
622 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
623 skb = rq->skb[wqe_counter];
625 rq->skb[wqe_counter] = NULL;
627 dma_unmap_single(rq->pdev,
628 *((dma_addr_t *)skb->cb),
632 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
638 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
639 skb_put(skb, cqe_bcnt);
641 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
644 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
645 &wqe->next.next_wqe_index);
648 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq,
649 struct mlx5_cqe64 *cqe,
650 struct mlx5e_mpw_info *wi,
654 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
655 u32 wqe_offset = stride_ix * rq->mpwqe_stride_sz;
656 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
657 u32 page_idx = wqe_offset >> PAGE_SHIFT;
658 u32 head_page_idx = page_idx;
659 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
660 u32 frag_offset = head_offset + headlen;
661 u16 byte_cnt = cqe_bcnt - headlen;
663 if (unlikely(frag_offset >= PAGE_SIZE)) {
665 frag_offset -= PAGE_SIZE;
669 u32 pg_consumed_bytes =
670 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
672 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset,
674 byte_cnt -= pg_consumed_bytes;
679 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx,
680 head_offset, headlen);
681 /* skb linear part was allocated with headlen and aligned to long */
682 skb->tail += headlen;
686 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
688 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
689 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
690 struct mlx5e_mpw_info *wi = &rq->wqe_info[wqe_id];
691 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
695 wi->consumed_strides += cstrides;
697 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
702 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
703 rq->stats.mpwqe_filler++;
707 skb = napi_alloc_skb(rq->cq.napi,
708 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD,
710 if (unlikely(!skb)) {
711 rq->stats.buff_alloc_err++;
716 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
718 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb);
719 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
722 if (likely(wi->consumed_strides < rq->mpwqe_num_strides))
725 mlx5e_free_rx_mpwqe(rq, wi);
726 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
729 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
731 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
734 if (unlikely(test_bit(MLX5E_RQ_STATE_FLUSH, &rq->state)))
737 if (cq->decmprs_left)
738 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
740 for (; work_done < budget; work_done++) {
741 struct mlx5_cqe64 *cqe = mlx5e_get_cqe(cq);
746 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
748 mlx5e_decompress_cqes_start(rq, cq,
753 mlx5_cqwq_pop(&cq->wq);
755 rq->handle_rx_cqe(rq, cqe);
758 mlx5_cqwq_update_db_record(&cq->wq);
760 /* ensure cq space is freed before enabling more cqes */