2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/etherdevice.h>
34 #include <linux/mlx5/driver.h>
35 #include <linux/mlx5/mlx5_ifc.h>
36 #include <linux/mlx5/vport.h>
37 #include <linux/mlx5/flow_table.h>
38 #include "mlx5_core.h"
41 #define UPLINK_VPORT 0xFFFF
43 #define MLX5_DEBUG_ESWITCH_MASK BIT(3)
45 #define esw_info(dev, format, ...) \
46 pr_info("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)
48 #define esw_warn(dev, format, ...) \
49 pr_warn("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)
51 #define esw_debug(dev, format, ...) \
52 mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
60 /* E-Switch UC L2 table hash node */
62 struct l2addr_node node;
67 /* E-Switch MC FDB table hash node */
68 struct esw_mc_addr { /* SRIOV only */
69 struct l2addr_node node;
70 struct mlx5_flow_rule *uplink_rule; /* Forward to uplink rule */
74 /* Vport UC/MC hash node */
76 struct l2addr_node node;
79 struct mlx5_flow_rule *flow_rule; /* SRIOV only */
83 UC_ADDR_CHANGE = BIT(0),
84 MC_ADDR_CHANGE = BIT(1),
87 /* Vport context events */
88 #define SRIOV_VPORT_EVENTS (UC_ADDR_CHANGE | \
91 static int arm_vport_context_events_cmd(struct mlx5_core_dev *dev, u16 vport,
94 int in[MLX5_ST_SZ_DW(modify_nic_vport_context_in)];
95 int out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)];
99 memset(out, 0, sizeof(out));
100 memset(in, 0, sizeof(in));
102 MLX5_SET(modify_nic_vport_context_in, in,
103 opcode, MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT);
104 MLX5_SET(modify_nic_vport_context_in, in, field_select.change_event, 1);
105 MLX5_SET(modify_nic_vport_context_in, in, vport_number, vport);
107 MLX5_SET(modify_nic_vport_context_in, in, other_vport, 1);
108 nic_vport_ctx = MLX5_ADDR_OF(modify_nic_vport_context_in,
109 in, nic_vport_context);
111 MLX5_SET(nic_vport_context, nic_vport_ctx, arm_change_event, 1);
113 if (events_mask & UC_ADDR_CHANGE)
114 MLX5_SET(nic_vport_context, nic_vport_ctx,
115 event_on_uc_address_change, 1);
116 if (events_mask & MC_ADDR_CHANGE)
117 MLX5_SET(nic_vport_context, nic_vport_ctx,
118 event_on_mc_address_change, 1);
120 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
123 err = mlx5_cmd_status_to_err_v2(out);
131 /* HW L2 Table (MPFS) management */
132 static int set_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index,
133 u8 *mac, u8 vlan_valid, u16 vlan)
135 u32 in[MLX5_ST_SZ_DW(set_l2_table_entry_in)];
136 u32 out[MLX5_ST_SZ_DW(set_l2_table_entry_out)];
139 memset(in, 0, sizeof(in));
140 memset(out, 0, sizeof(out));
142 MLX5_SET(set_l2_table_entry_in, in, opcode,
143 MLX5_CMD_OP_SET_L2_TABLE_ENTRY);
144 MLX5_SET(set_l2_table_entry_in, in, table_index, index);
145 MLX5_SET(set_l2_table_entry_in, in, vlan_valid, vlan_valid);
146 MLX5_SET(set_l2_table_entry_in, in, vlan, vlan);
148 in_mac_addr = MLX5_ADDR_OF(set_l2_table_entry_in, in, mac_address);
149 ether_addr_copy(&in_mac_addr[2], mac);
151 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
155 static int del_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index)
157 u32 in[MLX5_ST_SZ_DW(delete_l2_table_entry_in)];
158 u32 out[MLX5_ST_SZ_DW(delete_l2_table_entry_out)];
160 memset(in, 0, sizeof(in));
161 memset(out, 0, sizeof(out));
163 MLX5_SET(delete_l2_table_entry_in, in, opcode,
164 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY);
165 MLX5_SET(delete_l2_table_entry_in, in, table_index, index);
166 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
170 static int alloc_l2_table_index(struct mlx5_l2_table *l2_table, u32 *ix)
174 *ix = find_first_zero_bit(l2_table->bitmap, l2_table->size);
175 if (*ix >= l2_table->size)
178 __set_bit(*ix, l2_table->bitmap);
183 static void free_l2_table_index(struct mlx5_l2_table *l2_table, u32 ix)
185 __clear_bit(ix, l2_table->bitmap);
188 static int set_l2_table_entry(struct mlx5_core_dev *dev, u8 *mac,
189 u8 vlan_valid, u16 vlan,
192 struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table;
195 err = alloc_l2_table_index(l2_table, index);
199 err = set_l2_table_entry_cmd(dev, *index, mac, vlan_valid, vlan);
201 free_l2_table_index(l2_table, *index);
206 static void del_l2_table_entry(struct mlx5_core_dev *dev, u32 index)
208 struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table;
210 del_l2_table_entry_cmd(dev, index);
211 free_l2_table_index(l2_table, index);
214 /* E-Switch FDB flow steering */
216 struct list_head list;
217 struct mlx5_flow_destination dest;
220 static int _mlx5_flow_rule_apply(struct mlx5_flow_rule *fr)
222 bool was_valid = fr->valid;
223 struct dest_node *dest_n;
224 u32 dest_list_size = 0;
225 void *in_match_value;
231 if (list_empty(&fr->dest_list)) {
233 mlx5_del_flow_table_entry(fr->ft, fr->fi);
238 list_for_each_entry(dest_n, &fr->dest_list, list)
241 flow_context = mlx5_vzalloc(MLX5_ST_SZ_BYTES(flow_context) +
242 MLX5_ST_SZ_BYTES(dest_format_struct) *
247 MLX5_SET(flow_context, flow_context, flow_tag, fr->flow_tag);
248 MLX5_SET(flow_context, flow_context, action, fr->action);
249 MLX5_SET(flow_context, flow_context, destination_list_size,
253 list_for_each_entry(dest_n, &fr->dest_list, list) {
254 void *dest_addr = MLX5_ADDR_OF(flow_context, flow_context,
257 MLX5_SET(dest_format_struct, dest_addr, destination_type,
259 MLX5_SET(dest_format_struct, dest_addr, destination_id,
260 dest_n->dest.vport_num);
263 in_match_value = MLX5_ADDR_OF(flow_context, flow_context, match_value);
264 memcpy(in_match_value, fr->match_value, MLX5_ST_SZ_BYTES(fte_match_param));
266 err = mlx5_add_flow_table_entry(fr->ft, fr->match_criteria_enable,
267 fr->match_criteria, flow_context,
271 mlx5_del_flow_table_entry(fr->ft, fr->fi);
279 static int mlx5_flow_rule_add_dest(struct mlx5_flow_rule *fr,
280 struct mlx5_flow_destination *new_dest)
282 struct dest_node *dest_n;
285 dest_n = kzalloc(sizeof(*dest_n), GFP_KERNEL);
289 memcpy(&dest_n->dest, new_dest, sizeof(dest_n->dest));
290 mutex_lock(&fr->mutex);
291 list_add(&dest_n->list, &fr->dest_list);
292 err = _mlx5_flow_rule_apply(fr);
294 list_del(&dest_n->list);
297 mutex_unlock(&fr->mutex);
301 static int mlx5_flow_rule_del_dest(struct mlx5_flow_rule *fr,
302 struct mlx5_flow_destination *dest)
304 struct dest_node *dest_n;
308 mutex_lock(&fr->mutex);
309 list_for_each_entry_safe(dest_n, n, &fr->dest_list, list) {
310 if (dest->vport_num == dest_n->dest.vport_num)
313 mutex_unlock(&fr->mutex);
317 list_del(&dest_n->list);
318 err = _mlx5_flow_rule_apply(fr);
319 mutex_unlock(&fr->mutex);
325 static struct mlx5_flow_rule *find_fr(struct mlx5_eswitch *esw,
326 u8 match_criteria_enable,
329 struct hlist_head *hash = esw->mc_table;
330 struct esw_mc_addr *esw_mc;
333 dmac_v = MLX5_ADDR_OF(fte_match_param, match_value,
334 outer_headers.dmac_47_16);
336 /* UNICAST FULL MATCH */
337 if (!is_multicast_ether_addr(dmac_v))
340 /* MULTICAST FULL MATCH */
341 esw_mc = l2addr_hash_find(hash, dmac_v, struct esw_mc_addr);
343 return esw_mc ? esw_mc->uplink_rule : NULL;
346 static struct mlx5_flow_rule *alloc_fr(void *ft,
347 u8 match_criteria_enable,
353 struct mlx5_flow_rule *fr = kzalloc(sizeof(*fr), GFP_KERNEL);
358 fr->match_criteria = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
359 fr->match_value = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
360 if (!fr->match_criteria || !fr->match_value) {
361 kfree(fr->match_criteria);
362 kfree(fr->match_value);
367 memcpy(fr->match_criteria, match_criteria, MLX5_ST_SZ_BYTES(fte_match_param));
368 memcpy(fr->match_value, match_value, MLX5_ST_SZ_BYTES(fte_match_param));
369 fr->match_criteria_enable = match_criteria_enable;
370 fr->flow_tag = flow_tag;
373 mutex_init(&fr->mutex);
374 INIT_LIST_HEAD(&fr->dest_list);
375 atomic_set(&fr->refcount, 0);
380 static void deref_fr(struct mlx5_flow_rule *fr)
382 if (!atomic_dec_and_test(&fr->refcount))
385 kfree(fr->match_criteria);
386 kfree(fr->match_value);
390 static struct mlx5_flow_rule *
391 mlx5_add_flow_rule(struct mlx5_eswitch *esw,
392 u8 match_criteria_enable,
397 struct mlx5_flow_destination *dest)
399 struct mlx5_flow_rule *fr;
402 fr = find_fr(esw, match_criteria_enable, match_value);
403 fr = fr ? fr : alloc_fr(esw->fdb_table.fdb, match_criteria_enable, match_criteria,
404 match_value, action, flow_tag);
408 atomic_inc(&fr->refcount);
410 err = mlx5_flow_rule_add_dest(fr, dest);
419 static void mlx5_del_flow_rule(struct mlx5_flow_rule *fr, u32 vport)
421 struct mlx5_flow_destination dest;
423 dest.vport_num = vport;
424 mlx5_flow_rule_del_dest(fr, &dest);
429 static struct mlx5_flow_rule *
430 esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u8 mac[ETH_ALEN], u32 vport)
432 int match_header = MLX5_MATCH_OUTER_HEADERS;
433 struct mlx5_flow_destination dest;
434 struct mlx5_flow_rule *flow_rule = NULL;
440 match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
441 match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
442 if (!match_v || !match_c) {
443 pr_warn("FDB: Failed to alloc match parameters\n");
446 dmac_v = MLX5_ADDR_OF(fte_match_param, match_v,
447 outer_headers.dmac_47_16);
448 dmac_c = MLX5_ADDR_OF(fte_match_param, match_c,
449 outer_headers.dmac_47_16);
451 ether_addr_copy(dmac_v, mac);
452 /* Match criteria mask */
453 memset(dmac_c, 0xff, 6);
455 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
456 dest.vport_num = vport;
459 "\tFDB add rule dmac_v(%pM) dmac_c(%pM) -> vport(%d)\n",
460 dmac_v, dmac_c, vport);
462 mlx5_add_flow_rule(esw,
466 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
468 if (IS_ERR_OR_NULL(flow_rule)) {
470 "FDB: Failed to add flow rule: dmac_v(%pM) dmac_c(%pM) -> vport(%d), err(%ld)\n",
471 dmac_v, dmac_c, vport, PTR_ERR(flow_rule));
480 static int esw_create_fdb_table(struct mlx5_eswitch *esw, int nvports)
482 struct mlx5_core_dev *dev = esw->dev;
483 struct mlx5_flow_table_group g;
484 struct mlx5_flow_table *fdb;
487 esw_debug(dev, "Create FDB log_max_size(%d)\n",
488 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size));
490 memset(&g, 0, sizeof(g));
491 /* UC MC Full match rules*/
492 g.log_sz = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size);
493 g.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
494 dmac = MLX5_ADDR_OF(fte_match_param, g.match_criteria,
495 outer_headers.dmac_47_16);
496 /* Match criteria mask */
497 memset(dmac, 0xff, 6);
499 fdb = mlx5_create_flow_table(dev, 0,
500 MLX5_FLOW_TABLE_TYPE_ESWITCH,
503 esw_debug(dev, "ESW: FDB Table created fdb->id %d\n", mlx5_get_flow_table_id(fdb));
505 esw_warn(dev, "ESW: Failed to create FDB Table\n");
507 esw->fdb_table.fdb = fdb;
508 return fdb ? 0 : -ENOMEM;
511 static void esw_destroy_fdb_table(struct mlx5_eswitch *esw)
513 if (!esw->fdb_table.fdb)
516 esw_debug(esw->dev, "Destroy FDB Table fdb(%d)\n",
517 mlx5_get_flow_table_id(esw->fdb_table.fdb));
518 mlx5_destroy_flow_table(esw->fdb_table.fdb);
519 esw->fdb_table.fdb = NULL;
522 /* E-Switch vport UC/MC lists management */
523 typedef int (*vport_addr_action)(struct mlx5_eswitch *esw,
524 struct vport_addr *vaddr);
526 static int esw_add_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
528 struct hlist_head *hash = esw->l2_table.l2_hash;
529 struct esw_uc_addr *esw_uc;
530 u8 *mac = vaddr->node.addr;
531 u32 vport = vaddr->vport;
534 esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr);
537 "Failed to set L2 mac(%pM) for vport(%d), mac is already in use by vport(%d)\n",
538 mac, vport, esw_uc->vport);
542 esw_uc = l2addr_hash_add(hash, mac, struct esw_uc_addr, GFP_KERNEL);
545 esw_uc->vport = vport;
547 err = set_l2_table_entry(esw->dev, mac, 0, 0, &esw_uc->table_index);
551 if (esw->fdb_table.fdb) /* SRIOV is enabled: Forward UC MAC to vport */
552 vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport);
554 esw_debug(esw->dev, "\tADDED UC MAC: vport[%d] %pM index:%d fr(%p)\n",
555 vport, mac, esw_uc->table_index, vaddr->flow_rule);
558 l2addr_hash_del(esw_uc);
562 static int esw_del_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
564 struct hlist_head *hash = esw->l2_table.l2_hash;
565 struct esw_uc_addr *esw_uc;
566 u8 *mac = vaddr->node.addr;
567 u32 vport = vaddr->vport;
569 esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr);
570 if (!esw_uc || esw_uc->vport != vport) {
572 "MAC(%pM) doesn't belong to vport (%d)\n",
576 esw_debug(esw->dev, "\tDELETE UC MAC: vport[%d] %pM index:%d fr(%p)\n",
577 vport, mac, esw_uc->table_index, vaddr->flow_rule);
579 del_l2_table_entry(esw->dev, esw_uc->table_index);
581 if (vaddr->flow_rule)
582 mlx5_del_flow_rule(vaddr->flow_rule, vport);
583 vaddr->flow_rule = NULL;
585 l2addr_hash_del(esw_uc);
589 static int esw_add_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
591 struct hlist_head *hash = esw->mc_table;
592 struct esw_mc_addr *esw_mc;
593 u8 *mac = vaddr->node.addr;
594 u32 vport = vaddr->vport;
596 if (!esw->fdb_table.fdb)
599 esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr);
603 esw_mc = l2addr_hash_add(hash, mac, struct esw_mc_addr, GFP_KERNEL);
607 esw_mc->uplink_rule = /* Forward MC MAC to Uplink */
608 esw_fdb_set_vport_rule(esw, mac, UPLINK_VPORT);
611 /* Forward MC MAC to vport */
612 vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport);
614 "\tADDED MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n",
615 vport, mac, vaddr->flow_rule,
616 esw_mc->refcnt, esw_mc->uplink_rule);
620 static int esw_del_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
622 struct hlist_head *hash = esw->mc_table;
623 struct esw_mc_addr *esw_mc;
624 u8 *mac = vaddr->node.addr;
625 u32 vport = vaddr->vport;
627 if (!esw->fdb_table.fdb)
630 esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr);
633 "Failed to find eswitch MC addr for MAC(%pM) vport(%d)",
638 "\tDELETE MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n",
639 vport, mac, vaddr->flow_rule, esw_mc->refcnt,
640 esw_mc->uplink_rule);
642 if (vaddr->flow_rule)
643 mlx5_del_flow_rule(vaddr->flow_rule, vport);
644 vaddr->flow_rule = NULL;
646 if (--esw_mc->refcnt)
649 if (esw_mc->uplink_rule)
650 mlx5_del_flow_rule(esw_mc->uplink_rule, UPLINK_VPORT);
652 l2addr_hash_del(esw_mc);
656 /* Apply vport UC/MC list to HW l2 table and FDB table */
657 static void esw_apply_vport_addr_list(struct mlx5_eswitch *esw,
658 u32 vport_num, int list_type)
660 struct mlx5_vport *vport = &esw->vports[vport_num];
661 bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC;
662 vport_addr_action vport_addr_add;
663 vport_addr_action vport_addr_del;
664 struct vport_addr *addr;
665 struct l2addr_node *node;
666 struct hlist_head *hash;
667 struct hlist_node *tmp;
670 vport_addr_add = is_uc ? esw_add_uc_addr :
672 vport_addr_del = is_uc ? esw_del_uc_addr :
675 hash = is_uc ? vport->uc_list : vport->mc_list;
676 for_each_l2hash_node(node, tmp, hash, hi) {
677 addr = container_of(node, struct vport_addr, node);
678 switch (addr->action) {
679 case MLX5_ACTION_ADD:
680 vport_addr_add(esw, addr);
681 addr->action = MLX5_ACTION_NONE;
683 case MLX5_ACTION_DEL:
684 vport_addr_del(esw, addr);
685 l2addr_hash_del(addr);
691 /* Sync vport UC/MC list from vport context */
692 static void esw_update_vport_addr_list(struct mlx5_eswitch *esw,
693 u32 vport_num, int list_type)
695 struct mlx5_vport *vport = &esw->vports[vport_num];
696 bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC;
697 u8 (*mac_list)[ETH_ALEN];
698 struct l2addr_node *node;
699 struct vport_addr *addr;
700 struct hlist_head *hash;
701 struct hlist_node *tmp;
707 size = is_uc ? MLX5_MAX_UC_PER_VPORT(esw->dev) :
708 MLX5_MAX_MC_PER_VPORT(esw->dev);
710 mac_list = kcalloc(size, ETH_ALEN, GFP_KERNEL);
714 hash = is_uc ? vport->uc_list : vport->mc_list;
716 for_each_l2hash_node(node, tmp, hash, hi) {
717 addr = container_of(node, struct vport_addr, node);
718 addr->action = MLX5_ACTION_DEL;
721 err = mlx5_query_nic_vport_mac_list(esw->dev, vport_num, list_type,
725 esw_debug(esw->dev, "vport[%d] context update %s list size (%d)\n",
726 vport_num, is_uc ? "UC" : "MC", size);
728 for (i = 0; i < size; i++) {
729 if (is_uc && !is_valid_ether_addr(mac_list[i]))
732 if (!is_uc && !is_multicast_ether_addr(mac_list[i]))
735 addr = l2addr_hash_find(hash, mac_list[i], struct vport_addr);
737 addr->action = MLX5_ACTION_NONE;
741 addr = l2addr_hash_add(hash, mac_list[i], struct vport_addr,
745 "Failed to add MAC(%pM) to vport[%d] DB\n",
746 mac_list[i], vport_num);
749 addr->vport = vport_num;
750 addr->action = MLX5_ACTION_ADD;
755 static void esw_vport_change_handler(struct work_struct *work)
757 struct mlx5_vport *vport =
758 container_of(work, struct mlx5_vport, vport_change_handler);
759 struct mlx5_core_dev *dev = vport->dev;
760 struct mlx5_eswitch *esw = dev->priv.eswitch;
763 mlx5_query_nic_vport_mac_address(dev, vport->vport, mac);
764 esw_debug(dev, "vport[%d] Context Changed: perm mac: %pM\n",
767 if (vport->enabled_events & UC_ADDR_CHANGE) {
768 esw_update_vport_addr_list(esw, vport->vport,
769 MLX5_NVPRT_LIST_TYPE_UC);
770 esw_apply_vport_addr_list(esw, vport->vport,
771 MLX5_NVPRT_LIST_TYPE_UC);
774 if (vport->enabled_events & MC_ADDR_CHANGE) {
775 esw_update_vport_addr_list(esw, vport->vport,
776 MLX5_NVPRT_LIST_TYPE_MC);
777 esw_apply_vport_addr_list(esw, vport->vport,
778 MLX5_NVPRT_LIST_TYPE_MC);
781 esw_debug(esw->dev, "vport[%d] Context Changed: Done\n", vport->vport);
783 arm_vport_context_events_cmd(dev, vport->vport,
784 vport->enabled_events);
787 static void esw_enable_vport(struct mlx5_eswitch *esw, int vport_num,
790 struct mlx5_vport *vport = &esw->vports[vport_num];
793 WARN_ON(vport->enabled);
795 esw_debug(esw->dev, "Enabling VPORT(%d)\n", vport_num);
796 mlx5_modify_vport_admin_state(esw->dev,
797 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
799 MLX5_ESW_VPORT_ADMIN_STATE_AUTO);
801 /* Sync with current vport context */
802 vport->enabled_events = enable_events;
803 esw_vport_change_handler(&vport->vport_change_handler);
805 spin_lock_irqsave(&vport->lock, flags);
806 vport->enabled = true;
807 spin_unlock_irqrestore(&vport->lock, flags);
809 arm_vport_context_events_cmd(esw->dev, vport_num, enable_events);
811 esw->enabled_vports++;
812 esw_debug(esw->dev, "Enabled VPORT(%d)\n", vport_num);
815 static void esw_cleanup_vport(struct mlx5_eswitch *esw, u16 vport_num)
817 struct mlx5_vport *vport = &esw->vports[vport_num];
818 struct l2addr_node *node;
819 struct vport_addr *addr;
820 struct hlist_node *tmp;
823 for_each_l2hash_node(node, tmp, vport->uc_list, hi) {
824 addr = container_of(node, struct vport_addr, node);
825 addr->action = MLX5_ACTION_DEL;
827 esw_apply_vport_addr_list(esw, vport_num, MLX5_NVPRT_LIST_TYPE_UC);
829 for_each_l2hash_node(node, tmp, vport->mc_list, hi) {
830 addr = container_of(node, struct vport_addr, node);
831 addr->action = MLX5_ACTION_DEL;
833 esw_apply_vport_addr_list(esw, vport_num, MLX5_NVPRT_LIST_TYPE_MC);
836 static void esw_disable_vport(struct mlx5_eswitch *esw, int vport_num)
838 struct mlx5_vport *vport = &esw->vports[vport_num];
844 esw_debug(esw->dev, "Disabling vport(%d)\n", vport_num);
845 /* Mark this vport as disabled to discard new events */
846 spin_lock_irqsave(&vport->lock, flags);
847 vport->enabled = false;
848 vport->enabled_events = 0;
849 spin_unlock_irqrestore(&vport->lock, flags);
851 mlx5_modify_vport_admin_state(esw->dev,
852 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
854 MLX5_ESW_VPORT_ADMIN_STATE_DOWN);
855 /* Wait for current already scheduled events to complete */
856 flush_workqueue(esw->work_queue);
857 /* Disable events from this vport */
858 arm_vport_context_events_cmd(esw->dev, vport->vport, 0);
859 /* We don't assume VFs will cleanup after themselves */
860 esw_cleanup_vport(esw, vport_num);
861 esw->enabled_vports--;
864 /* Public E-Switch API */
865 int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs)
870 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
871 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
874 if (!MLX5_CAP_GEN(esw->dev, eswitch_flow_table) ||
875 !MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ft_support)) {
876 esw_warn(esw->dev, "E-Switch FDB is not supported, aborting ...\n");
880 esw_info(esw->dev, "E-Switch enable SRIOV: nvfs(%d)\n", nvfs);
882 esw_disable_vport(esw, 0);
884 err = esw_create_fdb_table(esw, nvfs + 1);
888 for (i = 0; i <= nvfs; i++)
889 esw_enable_vport(esw, i, SRIOV_VPORT_EVENTS);
891 esw_info(esw->dev, "SRIOV enabled: active vports(%d)\n",
892 esw->enabled_vports);
896 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
900 void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw)
904 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
905 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
908 esw_info(esw->dev, "disable SRIOV: active vports(%d)\n",
909 esw->enabled_vports);
911 for (i = 0; i < esw->total_vports; i++)
912 esw_disable_vport(esw, i);
914 esw_destroy_fdb_table(esw);
916 /* VPORT 0 (PF) must be enabled back with non-sriov configuration */
917 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
920 int mlx5_eswitch_init(struct mlx5_core_dev *dev)
922 int l2_table_size = 1 << MLX5_CAP_GEN(dev, log_max_l2_table);
923 int total_vports = 1 + pci_sriov_get_totalvfs(dev->pdev);
924 struct mlx5_eswitch *esw;
928 if (!MLX5_CAP_GEN(dev, vport_group_manager) ||
929 MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
933 "Total vports %d, l2 table size(%d), per vport: max uc(%d) max mc(%d)\n",
934 total_vports, l2_table_size,
935 MLX5_MAX_UC_PER_VPORT(dev),
936 MLX5_MAX_MC_PER_VPORT(dev));
938 esw = kzalloc(sizeof(*esw), GFP_KERNEL);
944 esw->l2_table.bitmap = kcalloc(BITS_TO_LONGS(l2_table_size),
945 sizeof(uintptr_t), GFP_KERNEL);
946 if (!esw->l2_table.bitmap) {
950 esw->l2_table.size = l2_table_size;
952 esw->work_queue = create_singlethread_workqueue("mlx5_esw_wq");
953 if (!esw->work_queue) {
958 esw->vports = kcalloc(total_vports, sizeof(struct mlx5_vport),
965 for (vport_num = 0; vport_num < total_vports; vport_num++) {
966 struct mlx5_vport *vport = &esw->vports[vport_num];
968 vport->vport = vport_num;
970 INIT_WORK(&vport->vport_change_handler,
971 esw_vport_change_handler);
972 spin_lock_init(&vport->lock);
975 esw->total_vports = total_vports;
976 esw->enabled_vports = 0;
978 dev->priv.eswitch = esw;
979 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
980 /* VF Vports will be enabled when SRIOV is enabled */
984 destroy_workqueue(esw->work_queue);
985 kfree(esw->l2_table.bitmap);
991 void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw)
993 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
994 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
997 esw_info(esw->dev, "cleanup\n");
998 esw_disable_vport(esw, 0);
1000 esw->dev->priv.eswitch = NULL;
1001 destroy_workqueue(esw->work_queue);
1002 kfree(esw->l2_table.bitmap);
1007 void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe)
1009 struct mlx5_eqe_vport_change *vc_eqe = &eqe->data.vport_change;
1010 u16 vport_num = be16_to_cpu(vc_eqe->vport_num);
1011 struct mlx5_vport *vport;
1014 pr_warn("MLX5 E-Switch: vport %d got an event while eswitch is not initialized\n",
1019 vport = &esw->vports[vport_num];
1020 spin_lock(&vport->lock);
1022 queue_work(esw->work_queue, &vport->vport_change_handler);
1023 spin_unlock(&vport->lock);