2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/delay.h>
50 #include <linux/mlx5/mlx5_ifc.h>
51 #ifdef CONFIG_RFS_ACCEL
52 #include <linux/cpu_rmap.h>
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
57 #ifdef CONFIG_MLX5_CORE_EN
61 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
62 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
63 MODULE_LICENSE("Dual BSD/GPL");
64 MODULE_VERSION(DRIVER_VERSION);
66 int mlx5_core_debug_mask;
67 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
68 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
70 #define MLX5_DEFAULT_PROF 2
71 static int prof_sel = MLX5_DEFAULT_PROF;
72 module_param_named(prof_sel, prof_sel, int, 0444);
73 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
75 static LIST_HEAD(intf_list);
77 LIST_HEAD(mlx5_dev_list);
78 DEFINE_MUTEX(mlx5_intf_mutex);
80 struct mlx5_device_context {
81 struct list_head list;
82 struct mlx5_interface *intf;
88 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
89 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
92 static struct mlx5_profile profile[] = {
97 .mask = MLX5_PROF_MASK_QP_SIZE,
101 .mask = MLX5_PROF_MASK_QP_SIZE |
102 MLX5_PROF_MASK_MR_CACHE,
171 #define FW_INIT_TIMEOUT_MILI 2000
172 #define FW_INIT_WAIT_MS 2
174 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
176 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
179 while (fw_initializing(dev)) {
180 if (time_after(jiffies, end)) {
184 msleep(FW_INIT_WAIT_MS);
190 static int set_dma_caps(struct pci_dev *pdev)
194 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
196 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
197 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
199 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
204 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
207 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
208 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
211 "Can't set consistent PCI DMA mask, aborting\n");
216 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
220 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
222 struct pci_dev *pdev = dev->pdev;
225 mutex_lock(&dev->pci_status_mutex);
226 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
227 err = pci_enable_device(pdev);
229 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
231 mutex_unlock(&dev->pci_status_mutex);
236 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
238 struct pci_dev *pdev = dev->pdev;
240 mutex_lock(&dev->pci_status_mutex);
241 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
242 pci_disable_device(pdev);
243 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
245 mutex_unlock(&dev->pci_status_mutex);
248 static int request_bar(struct pci_dev *pdev)
252 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
253 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
257 err = pci_request_regions(pdev, DRIVER_NAME);
259 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
264 static void release_bar(struct pci_dev *pdev)
266 pci_release_regions(pdev);
269 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
271 struct mlx5_priv *priv = &dev->priv;
272 struct mlx5_eq_table *table = &priv->eq_table;
273 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
277 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
278 MLX5_EQ_VEC_COMP_BASE;
279 nvec = min_t(int, nvec, num_eqs);
280 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
283 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
285 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
286 if (!priv->msix_arr || !priv->irq_info)
289 for (i = 0; i < nvec; i++)
290 priv->msix_arr[i].entry = i;
292 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
293 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
297 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
302 kfree(priv->irq_info);
303 kfree(priv->msix_arr);
307 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
309 struct mlx5_priv *priv = &dev->priv;
311 pci_disable_msix(dev->pdev);
312 kfree(priv->irq_info);
313 kfree(priv->msix_arr);
316 struct mlx5_reg_host_endianess {
322 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
325 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
326 MLX5_DEV_CAP_FLAG_DCT,
329 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
345 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
350 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
351 enum mlx5_cap_type cap_type,
352 enum mlx5_cap_mode cap_mode)
354 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
355 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
356 void *out, *hca_caps;
357 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
360 memset(in, 0, sizeof(in));
361 out = kzalloc(out_sz, GFP_KERNEL);
365 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
366 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
367 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
370 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
371 cap_type, cap_mode, err);
375 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
378 case HCA_CAP_OPMOD_GET_MAX:
379 memcpy(dev->hca_caps_max[cap_type], hca_caps,
380 MLX5_UN_SZ_BYTES(hca_cap_union));
382 case HCA_CAP_OPMOD_GET_CUR:
383 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
384 MLX5_UN_SZ_BYTES(hca_cap_union));
388 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
398 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
402 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
405 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
408 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
410 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
412 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
413 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
414 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
417 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
421 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
425 if (MLX5_CAP_GEN(dev, atomic)) {
426 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
435 supported_atomic_req_8B_endianess_mode_1);
437 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
440 set_ctx = kzalloc(set_sz, GFP_KERNEL);
444 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
446 /* Set requestor to host endianness */
447 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
448 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
450 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
456 static int handle_hca_cap(struct mlx5_core_dev *dev)
458 void *set_ctx = NULL;
459 struct mlx5_profile *prof = dev->profile;
461 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
464 set_ctx = kzalloc(set_sz, GFP_KERNEL);
468 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
472 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
474 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
475 MLX5_ST_SZ_BYTES(cmd_hca_cap));
477 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
478 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
480 /* we limit the size of the pkey table to 128 entries for now */
481 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
482 to_fw_pkey_sz(dev, 128));
484 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
485 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
488 /* disable cmdif checksum */
489 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
491 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
493 err = set_caps(dev, set_ctx, set_sz,
494 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
501 static int set_hca_ctrl(struct mlx5_core_dev *dev)
503 struct mlx5_reg_host_endianess he_in;
504 struct mlx5_reg_host_endianess he_out;
507 if (!mlx5_core_is_pf(dev))
510 memset(&he_in, 0, sizeof(he_in));
511 he_in.he = MLX5_SET_HOST_ENDIANNESS;
512 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
513 &he_out, sizeof(he_out),
514 MLX5_REG_HOST_ENDIANNESS, 0, 1);
518 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
520 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
521 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
523 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
524 MLX5_SET(enable_hca_in, in, function_id, func_id);
525 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
528 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
530 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
531 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
533 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
534 MLX5_SET(disable_hca_in, in, function_id, func_id);
535 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
538 cycle_t mlx5_read_internal_timer(struct mlx5_core_dev *dev)
540 u32 timer_h, timer_h1, timer_l;
542 timer_h = ioread32be(&dev->iseg->internal_timer_h);
543 timer_l = ioread32be(&dev->iseg->internal_timer_l);
544 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
545 if (timer_h != timer_h1) /* wrap around */
546 timer_l = ioread32be(&dev->iseg->internal_timer_l);
548 return (cycle_t)timer_l | (cycle_t)timer_h1 << 32;
551 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
553 struct mlx5_priv *priv = &mdev->priv;
554 struct msix_entry *msix = priv->msix_arr;
555 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
556 int numa_node = priv->numa_node;
559 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
560 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
564 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
565 priv->irq_info[i].mask);
567 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
569 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
577 free_cpumask_var(priv->irq_info[i].mask);
581 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
583 struct mlx5_priv *priv = &mdev->priv;
584 struct msix_entry *msix = priv->msix_arr;
585 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
587 irq_set_affinity_hint(irq, NULL);
588 free_cpumask_var(priv->irq_info[i].mask);
591 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
596 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
597 err = mlx5_irq_set_affinity_hint(mdev, i);
605 for (i--; i >= 0; i--)
606 mlx5_irq_clear_affinity_hint(mdev, i);
611 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
615 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
616 mlx5_irq_clear_affinity_hint(mdev, i);
619 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
622 struct mlx5_eq_table *table = &dev->priv.eq_table;
623 struct mlx5_eq *eq, *n;
626 spin_lock(&table->lock);
627 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
628 if (eq->index == vector) {
635 spin_unlock(&table->lock);
639 EXPORT_SYMBOL(mlx5_vector2eqn);
641 struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn)
643 struct mlx5_eq_table *table = &dev->priv.eq_table;
646 spin_lock(&table->lock);
647 list_for_each_entry(eq, &table->comp_eqs_list, list)
648 if (eq->eqn == eqn) {
649 spin_unlock(&table->lock);
653 spin_unlock(&table->lock);
655 return ERR_PTR(-ENOENT);
658 static void free_comp_eqs(struct mlx5_core_dev *dev)
660 struct mlx5_eq_table *table = &dev->priv.eq_table;
661 struct mlx5_eq *eq, *n;
663 #ifdef CONFIG_RFS_ACCEL
665 free_irq_cpu_rmap(dev->rmap);
669 spin_lock(&table->lock);
670 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
672 spin_unlock(&table->lock);
673 if (mlx5_destroy_unmap_eq(dev, eq))
674 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
677 spin_lock(&table->lock);
679 spin_unlock(&table->lock);
682 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
684 struct mlx5_eq_table *table = &dev->priv.eq_table;
685 char name[MLX5_MAX_IRQ_NAME];
692 INIT_LIST_HEAD(&table->comp_eqs_list);
693 ncomp_vec = table->num_comp_vectors;
694 nent = MLX5_COMP_EQ_SIZE;
695 #ifdef CONFIG_RFS_ACCEL
696 dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
700 for (i = 0; i < ncomp_vec; i++) {
701 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
707 #ifdef CONFIG_RFS_ACCEL
708 irq_cpu_rmap_add(dev->rmap,
709 dev->priv.msix_arr[i + MLX5_EQ_VEC_COMP_BASE].vector);
711 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
712 err = mlx5_create_map_eq(dev, eq,
713 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
714 name, &dev->priv.uuari.uars[0]);
719 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
721 spin_lock(&table->lock);
722 list_add_tail(&eq->list, &table->comp_eqs_list);
723 spin_unlock(&table->lock);
733 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
735 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
736 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
740 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
741 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
742 query_out, sizeof(query_out));
747 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
748 if (status == MLX5_CMD_STAT_BAD_OP_ERR) {
749 pr_debug("Only ISSI 0 is supported\n");
753 pr_err("failed to query ISSI err(%d)\n", err);
757 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
759 if (sup_issi & (1 << 1)) {
760 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
761 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
763 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
764 MLX5_SET(set_issi_in, set_in, current_issi, 1);
765 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
766 set_out, sizeof(set_out));
768 pr_err("failed to set ISSI=1 err(%d)\n", err);
775 } else if (sup_issi & (1 << 0) || !sup_issi) {
783 MLX5_INTERFACE_ADDED,
784 MLX5_INTERFACE_ATTACHED,
787 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
789 struct mlx5_device_context *dev_ctx;
790 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
792 if (!mlx5_lag_intf_add(intf, priv))
795 dev_ctx = kzalloc(sizeof(*dev_ctx), GFP_KERNEL);
799 dev_ctx->intf = intf;
800 dev_ctx->context = intf->add(dev);
801 set_bit(MLX5_INTERFACE_ADDED, &dev_ctx->state);
803 set_bit(MLX5_INTERFACE_ATTACHED, &dev_ctx->state);
805 if (dev_ctx->context) {
806 spin_lock_irq(&priv->ctx_lock);
807 list_add_tail(&dev_ctx->list, &priv->ctx_list);
808 spin_unlock_irq(&priv->ctx_lock);
814 static struct mlx5_device_context *mlx5_get_device(struct mlx5_interface *intf,
815 struct mlx5_priv *priv)
817 struct mlx5_device_context *dev_ctx;
819 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
820 if (dev_ctx->intf == intf)
825 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
827 struct mlx5_device_context *dev_ctx;
828 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
830 dev_ctx = mlx5_get_device(intf, priv);
834 spin_lock_irq(&priv->ctx_lock);
835 list_del(&dev_ctx->list);
836 spin_unlock_irq(&priv->ctx_lock);
838 if (test_bit(MLX5_INTERFACE_ADDED, &dev_ctx->state))
839 intf->remove(dev, dev_ctx->context);
844 static void mlx5_attach_interface(struct mlx5_interface *intf, struct mlx5_priv *priv)
846 struct mlx5_device_context *dev_ctx;
847 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
849 dev_ctx = mlx5_get_device(intf, priv);
854 if (test_bit(MLX5_INTERFACE_ATTACHED, &dev_ctx->state))
856 intf->attach(dev, dev_ctx->context);
857 set_bit(MLX5_INTERFACE_ATTACHED, &dev_ctx->state);
859 if (test_bit(MLX5_INTERFACE_ADDED, &dev_ctx->state))
861 dev_ctx->context = intf->add(dev);
862 set_bit(MLX5_INTERFACE_ADDED, &dev_ctx->state);
866 static void mlx5_attach_device(struct mlx5_core_dev *dev)
868 struct mlx5_priv *priv = &dev->priv;
869 struct mlx5_interface *intf;
871 mutex_lock(&mlx5_intf_mutex);
872 list_for_each_entry(intf, &intf_list, list)
873 mlx5_attach_interface(intf, priv);
874 mutex_unlock(&mlx5_intf_mutex);
877 static void mlx5_detach_interface(struct mlx5_interface *intf, struct mlx5_priv *priv)
879 struct mlx5_device_context *dev_ctx;
880 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
882 dev_ctx = mlx5_get_device(intf, priv);
887 if (!test_bit(MLX5_INTERFACE_ATTACHED, &dev_ctx->state))
889 intf->detach(dev, dev_ctx->context);
890 clear_bit(MLX5_INTERFACE_ATTACHED, &dev_ctx->state);
892 if (!test_bit(MLX5_INTERFACE_ADDED, &dev_ctx->state))
894 intf->remove(dev, dev_ctx->context);
895 clear_bit(MLX5_INTERFACE_ADDED, &dev_ctx->state);
899 static void mlx5_detach_device(struct mlx5_core_dev *dev)
901 struct mlx5_priv *priv = &dev->priv;
902 struct mlx5_interface *intf;
904 mutex_lock(&mlx5_intf_mutex);
905 list_for_each_entry(intf, &intf_list, list)
906 mlx5_detach_interface(intf, priv);
907 mutex_unlock(&mlx5_intf_mutex);
910 static bool mlx5_device_registered(struct mlx5_core_dev *dev)
912 struct mlx5_priv *priv;
915 mutex_lock(&mlx5_intf_mutex);
916 list_for_each_entry(priv, &mlx5_dev_list, dev_list)
917 if (priv == &dev->priv)
919 mutex_unlock(&mlx5_intf_mutex);
924 static int mlx5_register_device(struct mlx5_core_dev *dev)
926 struct mlx5_priv *priv = &dev->priv;
927 struct mlx5_interface *intf;
929 mutex_lock(&mlx5_intf_mutex);
930 list_add_tail(&priv->dev_list, &mlx5_dev_list);
931 list_for_each_entry(intf, &intf_list, list)
932 mlx5_add_device(intf, priv);
933 mutex_unlock(&mlx5_intf_mutex);
938 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
940 struct mlx5_priv *priv = &dev->priv;
941 struct mlx5_interface *intf;
943 mutex_lock(&mlx5_intf_mutex);
944 list_for_each_entry(intf, &intf_list, list)
945 mlx5_remove_device(intf, priv);
946 list_del(&priv->dev_list);
947 mutex_unlock(&mlx5_intf_mutex);
950 int mlx5_register_interface(struct mlx5_interface *intf)
952 struct mlx5_priv *priv;
954 if (!intf->add || !intf->remove)
957 mutex_lock(&mlx5_intf_mutex);
958 list_add_tail(&intf->list, &intf_list);
959 list_for_each_entry(priv, &mlx5_dev_list, dev_list)
960 mlx5_add_device(intf, priv);
961 mutex_unlock(&mlx5_intf_mutex);
965 EXPORT_SYMBOL(mlx5_register_interface);
967 void mlx5_unregister_interface(struct mlx5_interface *intf)
969 struct mlx5_priv *priv;
971 mutex_lock(&mlx5_intf_mutex);
972 list_for_each_entry(priv, &mlx5_dev_list, dev_list)
973 mlx5_remove_device(intf, priv);
974 list_del(&intf->list);
975 mutex_unlock(&mlx5_intf_mutex);
977 EXPORT_SYMBOL(mlx5_unregister_interface);
979 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
981 struct mlx5_priv *priv = &mdev->priv;
982 struct mlx5_device_context *dev_ctx;
986 spin_lock_irqsave(&priv->ctx_lock, flags);
988 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
989 if ((dev_ctx->intf->protocol == protocol) &&
990 dev_ctx->intf->get_dev) {
991 result = dev_ctx->intf->get_dev(dev_ctx->context);
995 spin_unlock_irqrestore(&priv->ctx_lock, flags);
999 EXPORT_SYMBOL(mlx5_get_protocol_dev);
1001 /* Must be called with intf_mutex held */
1002 void mlx5_add_dev_by_protocol(struct mlx5_core_dev *dev, int protocol)
1004 struct mlx5_interface *intf;
1006 list_for_each_entry(intf, &intf_list, list)
1007 if (intf->protocol == protocol) {
1008 mlx5_add_device(intf, &dev->priv);
1013 /* Must be called with intf_mutex held */
1014 void mlx5_remove_dev_by_protocol(struct mlx5_core_dev *dev, int protocol)
1016 struct mlx5_interface *intf;
1018 list_for_each_entry(intf, &intf_list, list)
1019 if (intf->protocol == protocol) {
1020 mlx5_remove_device(intf, &dev->priv);
1025 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
1027 struct pci_dev *pdev = dev->pdev;
1030 pci_set_drvdata(dev->pdev, dev);
1031 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
1032 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
1034 mutex_init(&priv->pgdir_mutex);
1035 INIT_LIST_HEAD(&priv->pgdir_list);
1036 spin_lock_init(&priv->mkey_lock);
1038 mutex_init(&priv->alloc_mutex);
1040 priv->numa_node = dev_to_node(&dev->pdev->dev);
1042 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
1043 if (!priv->dbg_root)
1046 err = mlx5_pci_enable_device(dev);
1048 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
1052 err = request_bar(pdev);
1054 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
1058 pci_set_master(pdev);
1060 err = set_dma_caps(pdev);
1062 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
1063 goto err_clr_master;
1066 dev->iseg_base = pci_resource_start(dev->pdev, 0);
1067 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
1070 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
1071 goto err_clr_master;
1077 pci_clear_master(dev->pdev);
1078 release_bar(dev->pdev);
1080 mlx5_pci_disable_device(dev);
1083 debugfs_remove(priv->dbg_root);
1087 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
1090 pci_clear_master(dev->pdev);
1091 release_bar(dev->pdev);
1092 mlx5_pci_disable_device(dev);
1093 debugfs_remove(priv->dbg_root);
1096 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
1098 struct pci_dev *pdev = dev->pdev;
1101 err = mlx5_query_hca_caps(dev);
1103 dev_err(&pdev->dev, "query hca failed\n");
1107 err = mlx5_query_board_id(dev);
1109 dev_err(&pdev->dev, "query board id failed\n");
1113 err = mlx5_eq_init(dev);
1115 dev_err(&pdev->dev, "failed to initialize eq\n");
1119 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1121 err = mlx5_init_cq_table(dev);
1123 dev_err(&pdev->dev, "failed to initialize cq table\n");
1124 goto err_eq_cleanup;
1127 mlx5_init_qp_table(dev);
1129 mlx5_init_srq_table(dev);
1131 mlx5_init_mkey_table(dev);
1133 err = mlx5_init_rl_table(dev);
1135 dev_err(&pdev->dev, "Failed to init rate limiting\n");
1136 goto err_tables_cleanup;
1142 mlx5_cleanup_mkey_table(dev);
1143 mlx5_cleanup_srq_table(dev);
1144 mlx5_cleanup_qp_table(dev);
1145 mlx5_cleanup_cq_table(dev);
1148 mlx5_eq_cleanup(dev);
1154 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1156 mlx5_cleanup_rl_table(dev);
1157 mlx5_cleanup_mkey_table(dev);
1158 mlx5_cleanup_srq_table(dev);
1159 mlx5_cleanup_qp_table(dev);
1160 mlx5_cleanup_cq_table(dev);
1161 mlx5_eq_cleanup(dev);
1164 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1167 struct pci_dev *pdev = dev->pdev;
1170 mutex_lock(&dev->intf_state_mutex);
1171 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1172 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
1177 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1178 fw_rev_min(dev), fw_rev_sub(dev));
1180 /* on load removing any previous indication of internal error, device is
1183 dev->state = MLX5_DEVICE_STATE_UP;
1185 err = mlx5_cmd_init(dev);
1187 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
1191 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
1193 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
1194 FW_INIT_TIMEOUT_MILI);
1198 err = mlx5_core_enable_hca(dev, 0);
1200 dev_err(&pdev->dev, "enable hca failed\n");
1201 goto err_cmd_cleanup;
1204 err = mlx5_core_set_issi(dev);
1206 dev_err(&pdev->dev, "failed to set issi\n");
1207 goto err_disable_hca;
1210 err = mlx5_satisfy_startup_pages(dev, 1);
1212 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1213 goto err_disable_hca;
1216 err = set_hca_ctrl(dev);
1218 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
1219 goto reclaim_boot_pages;
1222 err = handle_hca_cap(dev);
1224 dev_err(&pdev->dev, "handle_hca_cap failed\n");
1225 goto reclaim_boot_pages;
1228 err = handle_hca_cap_atomic(dev);
1230 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1231 goto reclaim_boot_pages;
1234 err = mlx5_satisfy_startup_pages(dev, 0);
1236 dev_err(&pdev->dev, "failed to allocate init pages\n");
1237 goto reclaim_boot_pages;
1240 err = mlx5_pagealloc_start(dev);
1242 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
1243 goto reclaim_boot_pages;
1246 err = mlx5_cmd_init_hca(dev);
1248 dev_err(&pdev->dev, "init hca failed\n");
1249 goto err_pagealloc_stop;
1252 mlx5_start_health_poll(dev);
1254 if (boot && mlx5_init_once(dev, priv)) {
1255 dev_err(&pdev->dev, "sw objs init failed\n");
1259 err = mlx5_enable_msix(dev);
1261 dev_err(&pdev->dev, "enable msix failed\n");
1262 goto err_cleanup_once;
1265 err = mlx5_alloc_uuars(dev, &priv->uuari);
1267 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1268 goto err_disable_msix;
1271 err = mlx5_start_eqs(dev);
1273 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1277 err = alloc_comp_eqs(dev);
1279 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1283 err = mlx5_irq_set_affinity_hints(dev);
1285 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1286 goto err_affinity_hints;
1289 err = mlx5_init_fs(dev);
1291 dev_err(&pdev->dev, "Failed to init flow steering\n");
1295 #ifdef CONFIG_MLX5_CORE_EN
1296 err = mlx5_eswitch_init(dev);
1298 dev_err(&pdev->dev, "eswitch init failed %d\n", err);
1303 err = mlx5_sriov_init(dev);
1305 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1309 if (mlx5_device_registered(dev)) {
1310 mlx5_attach_device(dev);
1312 err = mlx5_register_device(dev);
1314 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1319 clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1320 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1322 mutex_unlock(&dev->intf_state_mutex);
1327 mlx5_sriov_cleanup(dev);
1330 #ifdef CONFIG_MLX5_CORE_EN
1331 mlx5_eswitch_cleanup(dev->priv.eswitch);
1333 mlx5_cleanup_fs(dev);
1336 mlx5_irq_clear_affinity_hints(dev);
1345 mlx5_free_uuars(dev, &priv->uuari);
1348 mlx5_disable_msix(dev);
1352 mlx5_cleanup_once(dev);
1355 mlx5_stop_health_poll(dev);
1356 if (mlx5_cmd_teardown_hca(dev)) {
1357 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1362 mlx5_pagealloc_stop(dev);
1365 mlx5_reclaim_startup_pages(dev);
1368 mlx5_core_disable_hca(dev, 0);
1371 mlx5_cmd_cleanup(dev);
1374 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1375 mutex_unlock(&dev->intf_state_mutex);
1380 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1385 mutex_lock(&dev->intf_state_mutex);
1386 if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) {
1387 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1390 mlx5_cleanup_once(dev);
1394 if (mlx5_device_registered(dev))
1395 mlx5_detach_device(dev);
1397 mlx5_sriov_cleanup(dev);
1398 #ifdef CONFIG_MLX5_CORE_EN
1399 mlx5_eswitch_cleanup(dev->priv.eswitch);
1401 mlx5_cleanup_fs(dev);
1402 mlx5_irq_clear_affinity_hints(dev);
1405 mlx5_free_uuars(dev, &priv->uuari);
1406 mlx5_disable_msix(dev);
1408 mlx5_cleanup_once(dev);
1409 mlx5_stop_health_poll(dev);
1410 err = mlx5_cmd_teardown_hca(dev);
1412 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1415 mlx5_pagealloc_stop(dev);
1416 mlx5_reclaim_startup_pages(dev);
1417 mlx5_core_disable_hca(dev, 0);
1418 mlx5_cmd_cleanup(dev);
1421 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1422 set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1423 mutex_unlock(&dev->intf_state_mutex);
1427 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1428 unsigned long param)
1430 struct mlx5_priv *priv = &dev->priv;
1431 struct mlx5_device_context *dev_ctx;
1432 unsigned long flags;
1434 spin_lock_irqsave(&priv->ctx_lock, flags);
1436 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1437 if (dev_ctx->intf->event)
1438 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1440 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1443 struct mlx5_core_event_handler {
1444 void (*event)(struct mlx5_core_dev *dev,
1445 enum mlx5_dev_event event,
1449 static const struct devlink_ops mlx5_devlink_ops = {
1450 #ifdef CONFIG_MLX5_CORE_EN
1451 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1452 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
1456 #define MLX5_IB_MOD "mlx5_ib"
1457 static int init_one(struct pci_dev *pdev,
1458 const struct pci_device_id *id)
1460 struct mlx5_core_dev *dev;
1461 struct devlink *devlink;
1462 struct mlx5_priv *priv;
1465 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1467 dev_err(&pdev->dev, "kzalloc failed\n");
1471 dev = devlink_priv(devlink);
1473 priv->pci_dev_data = id->driver_data;
1475 pci_set_drvdata(pdev, dev);
1477 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1479 "selected profile out of range, selecting default (%d)\n",
1481 prof_sel = MLX5_DEFAULT_PROF;
1483 dev->profile = &profile[prof_sel];
1485 dev->event = mlx5_core_event;
1487 INIT_LIST_HEAD(&priv->ctx_list);
1488 spin_lock_init(&priv->ctx_lock);
1489 mutex_init(&dev->pci_status_mutex);
1490 mutex_init(&dev->intf_state_mutex);
1491 err = mlx5_pci_init(dev, priv);
1493 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1497 err = mlx5_health_init(dev);
1499 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1503 mlx5_pagealloc_init(dev);
1505 err = mlx5_load_one(dev, priv, true);
1507 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1511 err = request_module_nowait(MLX5_IB_MOD);
1513 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1515 err = devlink_register(devlink, &pdev->dev);
1522 mlx5_unload_one(dev, priv, true);
1524 mlx5_pagealloc_cleanup(dev);
1525 mlx5_health_cleanup(dev);
1527 mlx5_pci_close(dev, priv);
1529 pci_set_drvdata(pdev, NULL);
1530 devlink_free(devlink);
1535 static void remove_one(struct pci_dev *pdev)
1537 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1538 struct devlink *devlink = priv_to_devlink(dev);
1539 struct mlx5_priv *priv = &dev->priv;
1541 devlink_unregister(devlink);
1542 mlx5_unregister_device(dev);
1544 if (mlx5_unload_one(dev, priv, true)) {
1545 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1546 mlx5_health_cleanup(dev);
1550 mlx5_pagealloc_cleanup(dev);
1551 mlx5_health_cleanup(dev);
1552 mlx5_pci_close(dev, priv);
1553 pci_set_drvdata(pdev, NULL);
1554 devlink_free(devlink);
1557 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1558 pci_channel_state_t state)
1560 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1561 struct mlx5_priv *priv = &dev->priv;
1563 dev_info(&pdev->dev, "%s was called\n", __func__);
1564 mlx5_enter_error_state(dev);
1565 mlx5_unload_one(dev, priv, false);
1566 pci_save_state(pdev);
1567 mlx5_pci_disable_device(dev);
1568 return state == pci_channel_io_perm_failure ?
1569 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1572 /* wait for the device to show vital signs by waiting
1573 * for the health counter to start counting.
1575 static int wait_vital(struct pci_dev *pdev)
1577 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1578 struct mlx5_core_health *health = &dev->priv.health;
1579 const int niter = 100;
1584 for (i = 0; i < niter; i++) {
1585 count = ioread32be(health->health_counter);
1586 if (count && count != 0xffffffff) {
1587 if (last_count && last_count != count) {
1588 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1599 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1601 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1604 dev_info(&pdev->dev, "%s was called\n", __func__);
1606 err = mlx5_pci_enable_device(dev);
1608 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1610 return PCI_ERS_RESULT_DISCONNECT;
1613 pci_set_master(pdev);
1614 pci_restore_state(pdev);
1616 if (wait_vital(pdev)) {
1617 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1618 return PCI_ERS_RESULT_DISCONNECT;
1621 return PCI_ERS_RESULT_RECOVERED;
1624 void mlx5_disable_device(struct mlx5_core_dev *dev)
1626 mlx5_pci_err_detected(dev->pdev, 0);
1629 static void mlx5_pci_resume(struct pci_dev *pdev)
1631 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1632 struct mlx5_priv *priv = &dev->priv;
1635 dev_info(&pdev->dev, "%s was called\n", __func__);
1637 err = mlx5_load_one(dev, priv, false);
1639 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1642 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1645 static const struct pci_error_handlers mlx5_err_handler = {
1646 .error_detected = mlx5_pci_err_detected,
1647 .slot_reset = mlx5_pci_slot_reset,
1648 .resume = mlx5_pci_resume
1651 static void shutdown(struct pci_dev *pdev)
1653 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1654 struct mlx5_priv *priv = &dev->priv;
1656 dev_info(&pdev->dev, "Shutdown was called\n");
1657 /* Notify mlx5 clients that the kernel is being shut down */
1658 set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state);
1659 mlx5_unload_one(dev, priv, false);
1660 mlx5_pci_disable_device(dev);
1663 static const struct pci_device_id mlx5_core_pci_table[] = {
1664 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1665 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1666 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1667 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1668 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1669 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1670 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1671 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1672 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5, PCIe 4.0 */
1676 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1678 static struct pci_driver mlx5_core_driver = {
1679 .name = DRIVER_NAME,
1680 .id_table = mlx5_core_pci_table,
1682 .remove = remove_one,
1683 .shutdown = shutdown,
1684 .err_handler = &mlx5_err_handler,
1685 .sriov_configure = mlx5_core_sriov_configure,
1688 static int __init init(void)
1692 mlx5_register_debugfs();
1694 err = pci_register_driver(&mlx5_core_driver);
1698 #ifdef CONFIG_MLX5_CORE_EN
1705 mlx5_unregister_debugfs();
1709 static void __exit cleanup(void)
1711 #ifdef CONFIG_MLX5_CORE_EN
1714 pci_unregister_driver(&mlx5_core_driver);
1715 mlx5_unregister_debugfs();
1719 module_exit(cleanup);