2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <asm-generic/kmap_types.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/qp.h>
45 #include <linux/mlx5/srq.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/delay.h>
49 #include <linux/mlx5/mlx5_ifc.h>
50 #include "mlx5_core.h"
52 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
53 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
54 MODULE_LICENSE("Dual BSD/GPL");
55 MODULE_VERSION(DRIVER_VERSION);
57 int mlx5_core_debug_mask;
58 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
59 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
61 #define MLX5_DEFAULT_PROF 2
62 static int prof_sel = MLX5_DEFAULT_PROF;
63 module_param_named(prof_sel, prof_sel, int, 0444);
64 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
66 static LIST_HEAD(intf_list);
67 static LIST_HEAD(dev_list);
68 static DEFINE_MUTEX(intf_mutex);
70 struct mlx5_device_context {
71 struct list_head list;
72 struct mlx5_interface *intf;
76 static struct mlx5_profile profile[] = {
81 .mask = MLX5_PROF_MASK_QP_SIZE,
85 .mask = MLX5_PROF_MASK_QP_SIZE |
86 MLX5_PROF_MASK_MR_CACHE,
155 static int set_dma_caps(struct pci_dev *pdev)
159 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
161 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
162 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
164 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
169 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
172 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
173 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
176 "Can't set consistent PCI DMA mask, aborting\n");
181 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
185 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
187 struct pci_dev *pdev = dev->pdev;
190 mutex_lock(&dev->pci_status_mutex);
191 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
192 err = pci_enable_device(pdev);
194 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
196 mutex_unlock(&dev->pci_status_mutex);
201 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
203 struct pci_dev *pdev = dev->pdev;
205 mutex_lock(&dev->pci_status_mutex);
206 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
207 pci_disable_device(pdev);
208 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
210 mutex_unlock(&dev->pci_status_mutex);
213 static int request_bar(struct pci_dev *pdev)
217 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
218 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
222 err = pci_request_regions(pdev, DRIVER_NAME);
224 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
229 static void release_bar(struct pci_dev *pdev)
231 pci_release_regions(pdev);
234 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
236 struct mlx5_priv *priv = &dev->priv;
237 struct mlx5_eq_table *table = &priv->eq_table;
238 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
242 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
243 MLX5_EQ_VEC_COMP_BASE;
244 nvec = min_t(int, nvec, num_eqs);
245 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
248 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
250 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
251 if (!priv->msix_arr || !priv->irq_info)
254 for (i = 0; i < nvec; i++)
255 priv->msix_arr[i].entry = i;
257 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
258 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
262 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
267 kfree(priv->irq_info);
268 kfree(priv->msix_arr);
272 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
274 struct mlx5_priv *priv = &dev->priv;
276 pci_disable_msix(dev->pdev);
277 kfree(priv->irq_info);
278 kfree(priv->msix_arr);
281 struct mlx5_reg_host_endianess {
287 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
290 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
291 MLX5_DEV_CAP_FLAG_DCT,
294 static u16 to_fw_pkey_sz(u32 size)
310 pr_warn("invalid pkey table size %d\n", size);
315 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
316 enum mlx5_cap_mode cap_mode)
318 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
319 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
320 void *out, *hca_caps;
321 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
324 memset(in, 0, sizeof(in));
325 out = kzalloc(out_sz, GFP_KERNEL);
329 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
330 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
331 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
335 err = mlx5_cmd_status_to_err_v2(out);
338 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
339 cap_type, cap_mode, err);
343 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
346 case HCA_CAP_OPMOD_GET_MAX:
347 memcpy(dev->hca_caps_max[cap_type], hca_caps,
348 MLX5_UN_SZ_BYTES(hca_cap_union));
350 case HCA_CAP_OPMOD_GET_CUR:
351 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
352 MLX5_UN_SZ_BYTES(hca_cap_union));
356 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
366 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
368 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
371 memset(out, 0, sizeof(out));
373 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
374 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
378 err = mlx5_cmd_status_to_err_v2(out);
383 static int handle_hca_cap(struct mlx5_core_dev *dev)
385 void *set_ctx = NULL;
386 struct mlx5_profile *prof = dev->profile;
388 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
391 set_ctx = kzalloc(set_sz, GFP_KERNEL);
395 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
399 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
403 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
405 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
406 MLX5_ST_SZ_BYTES(cmd_hca_cap));
408 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
409 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
411 /* we limit the size of the pkey table to 128 entries for now */
412 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
415 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
416 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
419 /* disable cmdif checksum */
420 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
422 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
424 err = set_caps(dev, set_ctx, set_sz);
431 static int set_hca_ctrl(struct mlx5_core_dev *dev)
433 struct mlx5_reg_host_endianess he_in;
434 struct mlx5_reg_host_endianess he_out;
437 memset(&he_in, 0, sizeof(he_in));
438 he_in.he = MLX5_SET_HOST_ENDIANNESS;
439 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
440 &he_out, sizeof(he_out),
441 MLX5_REG_HOST_ENDIANNESS, 0, 1);
445 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
448 struct mlx5_enable_hca_mbox_in in;
449 struct mlx5_enable_hca_mbox_out out;
451 memset(&in, 0, sizeof(in));
452 memset(&out, 0, sizeof(out));
453 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
454 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
459 return mlx5_cmd_status_to_err(&out.hdr);
464 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
467 struct mlx5_disable_hca_mbox_in in;
468 struct mlx5_disable_hca_mbox_out out;
470 memset(&in, 0, sizeof(in));
471 memset(&out, 0, sizeof(out));
472 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
473 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
478 return mlx5_cmd_status_to_err(&out.hdr);
483 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
485 struct mlx5_priv *priv = &mdev->priv;
486 struct msix_entry *msix = priv->msix_arr;
487 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
488 int numa_node = priv->numa_node;
491 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
492 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
496 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
497 priv->irq_info[i].mask);
499 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
501 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
509 free_cpumask_var(priv->irq_info[i].mask);
513 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
515 struct mlx5_priv *priv = &mdev->priv;
516 struct msix_entry *msix = priv->msix_arr;
517 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
519 irq_set_affinity_hint(irq, NULL);
520 free_cpumask_var(priv->irq_info[i].mask);
523 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
528 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
529 err = mlx5_irq_set_affinity_hint(mdev, i);
537 for (i--; i >= 0; i--)
538 mlx5_irq_clear_affinity_hint(mdev, i);
543 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
547 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
548 mlx5_irq_clear_affinity_hint(mdev, i);
551 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
553 struct mlx5_eq_table *table = &dev->priv.eq_table;
554 struct mlx5_eq *eq, *n;
557 spin_lock(&table->lock);
558 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
559 if (eq->index == vector) {
566 spin_unlock(&table->lock);
570 EXPORT_SYMBOL(mlx5_vector2eqn);
572 static void free_comp_eqs(struct mlx5_core_dev *dev)
574 struct mlx5_eq_table *table = &dev->priv.eq_table;
575 struct mlx5_eq *eq, *n;
577 spin_lock(&table->lock);
578 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
580 spin_unlock(&table->lock);
581 if (mlx5_destroy_unmap_eq(dev, eq))
582 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
585 spin_lock(&table->lock);
587 spin_unlock(&table->lock);
590 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
592 struct mlx5_eq_table *table = &dev->priv.eq_table;
593 char name[MLX5_MAX_IRQ_NAME];
600 INIT_LIST_HEAD(&table->comp_eqs_list);
601 ncomp_vec = table->num_comp_vectors;
602 nent = MLX5_COMP_EQ_SIZE;
603 for (i = 0; i < ncomp_vec; i++) {
604 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
610 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
611 err = mlx5_create_map_eq(dev, eq,
612 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
613 name, &dev->priv.uuari.uars[0]);
618 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
620 spin_lock(&table->lock);
621 list_add_tail(&eq->list, &table->comp_eqs_list);
622 spin_unlock(&table->lock);
632 #ifdef CONFIG_MLX5_CORE_EN
633 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
635 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
636 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
637 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
638 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
642 memset(query_in, 0, sizeof(query_in));
643 memset(query_out, 0, sizeof(query_out));
645 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
647 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
648 query_out, sizeof(query_out));
650 if (((struct mlx5_outbox_hdr *)query_out)->status ==
651 MLX5_CMD_STAT_BAD_OP_ERR) {
652 pr_debug("Only ISSI 0 is supported\n");
656 pr_err("failed to query ISSI\n");
660 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
662 if (sup_issi & (1 << 1)) {
663 memset(set_in, 0, sizeof(set_in));
664 memset(set_out, 0, sizeof(set_out));
666 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
667 MLX5_SET(set_issi_in, set_in, current_issi, 1);
669 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
670 set_out, sizeof(set_out));
672 pr_err("failed to set ISSI=1\n");
679 } else if (sup_issi & (1 << 0) || !sup_issi) {
687 static int map_bf_area(struct mlx5_core_dev *dev)
689 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
690 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
692 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
694 return dev->priv.bf_mapping ? 0 : -ENOMEM;
697 static void unmap_bf_area(struct mlx5_core_dev *dev)
699 if (dev->priv.bf_mapping)
700 io_mapping_free(dev->priv.bf_mapping);
703 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
705 struct mlx5_device_context *dev_ctx;
706 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
708 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
712 dev_ctx->intf = intf;
713 dev_ctx->context = intf->add(dev);
715 if (dev_ctx->context) {
716 spin_lock_irq(&priv->ctx_lock);
717 list_add_tail(&dev_ctx->list, &priv->ctx_list);
718 spin_unlock_irq(&priv->ctx_lock);
724 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
726 struct mlx5_device_context *dev_ctx;
727 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
729 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
730 if (dev_ctx->intf == intf) {
731 spin_lock_irq(&priv->ctx_lock);
732 list_del(&dev_ctx->list);
733 spin_unlock_irq(&priv->ctx_lock);
735 intf->remove(dev, dev_ctx->context);
741 static int mlx5_register_device(struct mlx5_core_dev *dev)
743 struct mlx5_priv *priv = &dev->priv;
744 struct mlx5_interface *intf;
746 mutex_lock(&intf_mutex);
747 list_add_tail(&priv->dev_list, &dev_list);
748 list_for_each_entry(intf, &intf_list, list)
749 mlx5_add_device(intf, priv);
750 mutex_unlock(&intf_mutex);
755 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
757 struct mlx5_priv *priv = &dev->priv;
758 struct mlx5_interface *intf;
760 mutex_lock(&intf_mutex);
761 list_for_each_entry(intf, &intf_list, list)
762 mlx5_remove_device(intf, priv);
763 list_del(&priv->dev_list);
764 mutex_unlock(&intf_mutex);
767 int mlx5_register_interface(struct mlx5_interface *intf)
769 struct mlx5_priv *priv;
771 if (!intf->add || !intf->remove)
774 mutex_lock(&intf_mutex);
775 list_add_tail(&intf->list, &intf_list);
776 list_for_each_entry(priv, &dev_list, dev_list)
777 mlx5_add_device(intf, priv);
778 mutex_unlock(&intf_mutex);
782 EXPORT_SYMBOL(mlx5_register_interface);
784 void mlx5_unregister_interface(struct mlx5_interface *intf)
786 struct mlx5_priv *priv;
788 mutex_lock(&intf_mutex);
789 list_for_each_entry(priv, &dev_list, dev_list)
790 mlx5_remove_device(intf, priv);
791 list_del(&intf->list);
792 mutex_unlock(&intf_mutex);
794 EXPORT_SYMBOL(mlx5_unregister_interface);
796 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
798 struct mlx5_priv *priv = &mdev->priv;
799 struct mlx5_device_context *dev_ctx;
803 spin_lock_irqsave(&priv->ctx_lock, flags);
805 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
806 if ((dev_ctx->intf->protocol == protocol) &&
807 dev_ctx->intf->get_dev) {
808 result = dev_ctx->intf->get_dev(dev_ctx->context);
812 spin_unlock_irqrestore(&priv->ctx_lock, flags);
816 EXPORT_SYMBOL(mlx5_get_protocol_dev);
818 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
820 struct pci_dev *pdev = dev->pdev;
823 pci_set_drvdata(dev->pdev, dev);
824 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
825 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
827 mutex_init(&priv->pgdir_mutex);
828 INIT_LIST_HEAD(&priv->pgdir_list);
829 spin_lock_init(&priv->mkey_lock);
831 mutex_init(&priv->alloc_mutex);
833 priv->numa_node = dev_to_node(&dev->pdev->dev);
835 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
839 err = mlx5_pci_enable_device(dev);
841 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
845 err = request_bar(pdev);
847 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
851 pci_set_master(pdev);
853 err = set_dma_caps(pdev);
855 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
859 dev->iseg_base = pci_resource_start(dev->pdev, 0);
860 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
863 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
870 pci_clear_master(dev->pdev);
871 release_bar(dev->pdev);
873 mlx5_pci_disable_device(dev);
876 debugfs_remove(priv->dbg_root);
880 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
883 pci_clear_master(dev->pdev);
884 release_bar(dev->pdev);
885 mlx5_pci_disable_device(dev);
886 debugfs_remove(priv->dbg_root);
889 #define MLX5_IB_MOD "mlx5_ib"
890 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
892 struct pci_dev *pdev = dev->pdev;
895 mutex_lock(&dev->intf_state_mutex);
896 if (dev->interface_state == MLX5_INTERFACE_STATE_UP) {
897 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
902 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
903 fw_rev_min(dev), fw_rev_sub(dev));
905 /* on load removing any previous indication of internal error, device is
908 dev->state = MLX5_DEVICE_STATE_UP;
910 err = mlx5_cmd_init(dev);
912 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
916 mlx5_pagealloc_init(dev);
918 err = mlx5_core_enable_hca(dev);
920 dev_err(&pdev->dev, "enable hca failed\n");
921 goto err_pagealloc_cleanup;
924 #ifdef CONFIG_MLX5_CORE_EN
925 err = mlx5_core_set_issi(dev);
927 dev_err(&pdev->dev, "failed to set issi\n");
928 goto err_disable_hca;
932 err = mlx5_satisfy_startup_pages(dev, 1);
934 dev_err(&pdev->dev, "failed to allocate boot pages\n");
935 goto err_disable_hca;
938 err = set_hca_ctrl(dev);
940 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
941 goto reclaim_boot_pages;
944 err = handle_hca_cap(dev);
946 dev_err(&pdev->dev, "handle_hca_cap failed\n");
947 goto reclaim_boot_pages;
950 err = mlx5_satisfy_startup_pages(dev, 0);
952 dev_err(&pdev->dev, "failed to allocate init pages\n");
953 goto reclaim_boot_pages;
956 err = mlx5_pagealloc_start(dev);
958 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
959 goto reclaim_boot_pages;
962 err = mlx5_cmd_init_hca(dev);
964 dev_err(&pdev->dev, "init hca failed\n");
965 goto err_pagealloc_stop;
968 mlx5_start_health_poll(dev);
970 err = mlx5_query_hca_caps(dev);
972 dev_err(&pdev->dev, "query hca failed\n");
976 err = mlx5_query_board_id(dev);
978 dev_err(&pdev->dev, "query board id failed\n");
982 err = mlx5_enable_msix(dev);
984 dev_err(&pdev->dev, "enable msix failed\n");
988 err = mlx5_eq_init(dev);
990 dev_err(&pdev->dev, "failed to initialize eq\n");
994 err = mlx5_alloc_uuars(dev, &priv->uuari);
996 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1000 err = mlx5_start_eqs(dev);
1002 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1006 err = alloc_comp_eqs(dev);
1008 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1012 if (map_bf_area(dev))
1013 dev_err(&pdev->dev, "Failed to map blue flame area\n");
1015 err = mlx5_irq_set_affinity_hints(dev);
1017 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1018 goto err_unmap_bf_area;
1021 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1023 mlx5_init_cq_table(dev);
1024 mlx5_init_qp_table(dev);
1025 mlx5_init_srq_table(dev);
1026 mlx5_init_mr_table(dev);
1028 err = mlx5_register_device(dev);
1030 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1034 err = request_module_nowait(MLX5_IB_MOD);
1036 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1038 dev->interface_state = MLX5_INTERFACE_STATE_UP;
1040 mutex_unlock(&dev->intf_state_mutex);
1045 mlx5_cleanup_mr_table(dev);
1046 mlx5_cleanup_srq_table(dev);
1047 mlx5_cleanup_qp_table(dev);
1048 mlx5_cleanup_cq_table(dev);
1049 mlx5_irq_clear_affinity_hints(dev);
1060 mlx5_free_uuars(dev, &priv->uuari);
1063 mlx5_eq_cleanup(dev);
1066 mlx5_disable_msix(dev);
1069 mlx5_stop_health_poll(dev);
1070 if (mlx5_cmd_teardown_hca(dev)) {
1071 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1076 mlx5_pagealloc_stop(dev);
1079 mlx5_reclaim_startup_pages(dev);
1082 mlx5_core_disable_hca(dev);
1084 err_pagealloc_cleanup:
1085 mlx5_pagealloc_cleanup(dev);
1086 mlx5_cmd_cleanup(dev);
1089 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1090 mutex_unlock(&dev->intf_state_mutex);
1095 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
1099 mutex_lock(&dev->intf_state_mutex);
1100 if (dev->interface_state == MLX5_INTERFACE_STATE_DOWN) {
1101 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1105 mlx5_unregister_device(dev);
1106 mlx5_cleanup_mr_table(dev);
1107 mlx5_cleanup_srq_table(dev);
1108 mlx5_cleanup_qp_table(dev);
1109 mlx5_cleanup_cq_table(dev);
1110 mlx5_irq_clear_affinity_hints(dev);
1114 mlx5_free_uuars(dev, &priv->uuari);
1115 mlx5_eq_cleanup(dev);
1116 mlx5_disable_msix(dev);
1117 mlx5_stop_health_poll(dev);
1118 err = mlx5_cmd_teardown_hca(dev);
1120 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1123 mlx5_pagealloc_stop(dev);
1124 mlx5_reclaim_startup_pages(dev);
1125 mlx5_core_disable_hca(dev);
1126 mlx5_pagealloc_cleanup(dev);
1127 mlx5_cmd_cleanup(dev);
1130 dev->interface_state = MLX5_INTERFACE_STATE_DOWN;
1131 mutex_unlock(&dev->intf_state_mutex);
1135 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1136 unsigned long param)
1138 struct mlx5_priv *priv = &dev->priv;
1139 struct mlx5_device_context *dev_ctx;
1140 unsigned long flags;
1142 spin_lock_irqsave(&priv->ctx_lock, flags);
1144 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1145 if (dev_ctx->intf->event)
1146 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1148 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1151 struct mlx5_core_event_handler {
1152 void (*event)(struct mlx5_core_dev *dev,
1153 enum mlx5_dev_event event,
1158 static int init_one(struct pci_dev *pdev,
1159 const struct pci_device_id *id)
1161 struct mlx5_core_dev *dev;
1162 struct mlx5_priv *priv;
1165 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1167 dev_err(&pdev->dev, "kzalloc failed\n");
1172 pci_set_drvdata(pdev, dev);
1174 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1175 pr_warn("selected profile out of range, selecting default (%d)\n",
1177 prof_sel = MLX5_DEFAULT_PROF;
1179 dev->profile = &profile[prof_sel];
1181 dev->event = mlx5_core_event;
1183 INIT_LIST_HEAD(&priv->ctx_list);
1184 spin_lock_init(&priv->ctx_lock);
1185 mutex_init(&dev->pci_status_mutex);
1186 mutex_init(&dev->intf_state_mutex);
1187 err = mlx5_pci_init(dev, priv);
1189 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1193 err = mlx5_health_init(dev);
1195 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1199 err = mlx5_load_one(dev, priv);
1201 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1208 mlx5_health_cleanup(dev);
1210 mlx5_pci_close(dev, priv);
1212 pci_set_drvdata(pdev, NULL);
1218 static void remove_one(struct pci_dev *pdev)
1220 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1221 struct mlx5_priv *priv = &dev->priv;
1223 if (mlx5_unload_one(dev, priv)) {
1224 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1225 mlx5_health_cleanup(dev);
1228 mlx5_health_cleanup(dev);
1229 mlx5_pci_close(dev, priv);
1230 pci_set_drvdata(pdev, NULL);
1234 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1235 pci_channel_state_t state)
1237 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1238 struct mlx5_priv *priv = &dev->priv;
1240 dev_info(&pdev->dev, "%s was called\n", __func__);
1241 mlx5_enter_error_state(dev);
1242 mlx5_unload_one(dev, priv);
1243 mlx5_pci_disable_device(dev);
1244 return state == pci_channel_io_perm_failure ?
1245 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1248 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1250 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1253 dev_info(&pdev->dev, "%s was called\n", __func__);
1255 err = mlx5_pci_enable_device(dev);
1257 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1259 return PCI_ERS_RESULT_DISCONNECT;
1261 pci_set_master(pdev);
1262 pci_set_power_state(pdev, PCI_D0);
1263 pci_restore_state(pdev);
1265 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1268 void mlx5_disable_device(struct mlx5_core_dev *dev)
1270 mlx5_pci_err_detected(dev->pdev, 0);
1273 /* wait for the device to show vital signs. For now we check
1274 * that we can read the device ID and that the health buffer
1275 * shows a non zero value which is different than 0xffffffff
1277 static void wait_vital(struct pci_dev *pdev)
1279 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1280 struct mlx5_core_health *health = &dev->priv.health;
1281 const int niter = 100;
1286 /* Wait for firmware to be ready after reset */
1288 for (i = 0; i < niter; i++) {
1289 if (pci_read_config_word(pdev, 2, &did)) {
1290 dev_warn(&pdev->dev, "failed reading config word\n");
1293 if (did == pdev->device) {
1294 dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i);
1300 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1302 for (i = 0; i < niter; i++) {
1303 count = ioread32be(health->health_counter);
1304 if (count && count != 0xffffffff) {
1305 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1312 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1315 static void mlx5_pci_resume(struct pci_dev *pdev)
1317 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1318 struct mlx5_priv *priv = &dev->priv;
1321 dev_info(&pdev->dev, "%s was called\n", __func__);
1323 pci_save_state(pdev);
1326 err = mlx5_load_one(dev, priv);
1328 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1331 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1334 static const struct pci_error_handlers mlx5_err_handler = {
1335 .error_detected = mlx5_pci_err_detected,
1336 .slot_reset = mlx5_pci_slot_reset,
1337 .resume = mlx5_pci_resume
1340 static const struct pci_device_id mlx5_core_pci_table[] = {
1341 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1342 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
1343 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1344 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
1345 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1346 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
1350 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1352 static struct pci_driver mlx5_core_driver = {
1353 .name = DRIVER_NAME,
1354 .id_table = mlx5_core_pci_table,
1356 .remove = remove_one,
1357 .err_handler = &mlx5_err_handler
1360 static int __init init(void)
1364 mlx5_register_debugfs();
1366 err = pci_register_driver(&mlx5_core_driver);
1370 #ifdef CONFIG_MLX5_CORE_EN
1377 mlx5_unregister_debugfs();
1381 static void __exit cleanup(void)
1383 #ifdef CONFIG_MLX5_CORE_EN
1386 pci_unregister_driver(&mlx5_core_driver);
1387 mlx5_unregister_debugfs();
1391 module_exit(cleanup);