2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <asm-generic/kmap_types.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/qp.h>
45 #include <linux/mlx5/srq.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include "mlx5_core.h"
51 #define DRIVER_NAME "mlx5_core"
52 #define DRIVER_VERSION "3.0"
53 #define DRIVER_RELDATE "January 2015"
55 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
56 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
57 MODULE_LICENSE("Dual BSD/GPL");
58 MODULE_VERSION(DRIVER_VERSION);
60 int mlx5_core_debug_mask;
61 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
62 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
64 #define MLX5_DEFAULT_PROF 2
65 static int prof_sel = MLX5_DEFAULT_PROF;
66 module_param_named(prof_sel, prof_sel, int, 0444);
67 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
69 struct workqueue_struct *mlx5_core_wq;
70 static LIST_HEAD(intf_list);
71 static LIST_HEAD(dev_list);
72 static DEFINE_MUTEX(intf_mutex);
74 struct mlx5_device_context {
75 struct list_head list;
76 struct mlx5_interface *intf;
80 static struct mlx5_profile profile[] = {
85 .mask = MLX5_PROF_MASK_QP_SIZE,
89 .mask = MLX5_PROF_MASK_QP_SIZE |
90 MLX5_PROF_MASK_MR_CACHE,
159 static int set_dma_caps(struct pci_dev *pdev)
163 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
165 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
166 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
168 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
173 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
176 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
177 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
180 "Can't set consistent PCI DMA mask, aborting\n");
185 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
189 static int request_bar(struct pci_dev *pdev)
193 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
194 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
198 err = pci_request_regions(pdev, DRIVER_NAME);
200 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
205 static void release_bar(struct pci_dev *pdev)
207 pci_release_regions(pdev);
210 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
212 struct mlx5_priv *priv = &dev->priv;
213 struct mlx5_eq_table *table = &priv->eq_table;
214 int num_eqs = 1 << dev->caps.gen.log_max_eq;
218 nvec = dev->caps.gen.num_ports * num_online_cpus() + MLX5_EQ_VEC_COMP_BASE;
219 nvec = min_t(int, nvec, num_eqs);
220 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
223 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
225 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
226 if (!priv->msix_arr || !priv->irq_info)
229 for (i = 0; i < nvec; i++)
230 priv->msix_arr[i].entry = i;
232 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
233 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
237 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
242 kfree(priv->irq_info);
243 kfree(priv->msix_arr);
247 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
249 struct mlx5_priv *priv = &dev->priv;
251 pci_disable_msix(dev->pdev);
252 kfree(priv->irq_info);
253 kfree(priv->msix_arr);
256 struct mlx5_reg_host_endianess {
262 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
265 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
266 MLX5_DEV_CAP_FLAG_DCT,
269 static u16 to_fw_pkey_sz(u32 size)
285 pr_warn("invalid pkey table size %d\n", size);
290 /* selectively copy writable fields clearing any reserved area
292 static void copy_rw_fields(void *to, struct mlx5_caps *from)
294 __be64 *flags_off = (__be64 *)MLX5_ADDR_OF(cmd_hca_cap, to, reserved_22);
297 MLX5_SET(cmd_hca_cap, to, log_max_qp, from->gen.log_max_qp);
298 MLX5_SET(cmd_hca_cap, to, log_max_ra_req_qp, from->gen.log_max_ra_req_qp);
299 MLX5_SET(cmd_hca_cap, to, log_max_ra_res_qp, from->gen.log_max_ra_res_qp);
300 MLX5_SET(cmd_hca_cap, to, pkey_table_size, from->gen.pkey_table_size);
301 MLX5_SET(cmd_hca_cap, to, pkey_table_size, to_fw_pkey_sz(from->gen.pkey_table_size));
302 MLX5_SET(cmd_hca_cap, to, log_uar_page_sz, PAGE_SHIFT - 12);
303 v64 = from->gen.flags & MLX5_CAP_BITS_RW_MASK;
304 *flags_off = cpu_to_be64(v64);
307 static u16 get_pkey_table_size(int pkey)
309 if (pkey > MLX5_MAX_LOG_PKEY_TABLE)
312 return MLX5_MIN_PKEY_TABLE_SIZE << pkey;
315 static void fw2drv_caps(struct mlx5_caps *caps, void *out)
317 struct mlx5_general_caps *gen = &caps->gen;
319 gen->max_srq_wqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_srq_sz);
320 gen->max_wqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_qp_sz);
321 gen->log_max_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_qp);
322 gen->log_max_srq = MLX5_GET_PR(cmd_hca_cap, out, log_max_srq);
323 gen->max_cqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_cq_sz);
324 gen->log_max_cq = MLX5_GET_PR(cmd_hca_cap, out, log_max_cq);
325 gen->max_eqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_eq_sz);
326 gen->log_max_mkey = MLX5_GET_PR(cmd_hca_cap, out, log_max_mkey);
327 gen->log_max_eq = MLX5_GET_PR(cmd_hca_cap, out, log_max_eq);
328 gen->max_indirection = MLX5_GET_PR(cmd_hca_cap, out, max_indirection);
329 gen->log_max_mrw_sz = MLX5_GET_PR(cmd_hca_cap, out, log_max_mrw_sz);
330 gen->log_max_bsf_list_size = MLX5_GET_PR(cmd_hca_cap, out, log_max_bsf_list_size);
331 gen->log_max_klm_list_size = MLX5_GET_PR(cmd_hca_cap, out, log_max_klm_list_size);
332 gen->log_max_ra_req_dc = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_req_dc);
333 gen->log_max_ra_res_dc = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_res_dc);
334 gen->log_max_ra_req_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_req_qp);
335 gen->log_max_ra_res_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_res_qp);
336 gen->max_qp_counters = MLX5_GET_PR(cmd_hca_cap, out, max_qp_cnt);
337 gen->pkey_table_size = get_pkey_table_size(MLX5_GET_PR(cmd_hca_cap, out, pkey_table_size));
338 gen->local_ca_ack_delay = MLX5_GET_PR(cmd_hca_cap, out, local_ca_ack_delay);
339 gen->num_ports = MLX5_GET_PR(cmd_hca_cap, out, num_ports);
340 gen->log_max_msg = MLX5_GET_PR(cmd_hca_cap, out, log_max_msg);
341 gen->stat_rate_support = MLX5_GET_PR(cmd_hca_cap, out, stat_rate_support);
342 gen->flags = be64_to_cpu(*(__be64 *)MLX5_ADDR_OF(cmd_hca_cap, out, reserved_22));
343 pr_debug("flags = 0x%llx\n", gen->flags);
344 gen->uar_sz = MLX5_GET_PR(cmd_hca_cap, out, uar_sz);
345 gen->min_log_pg_sz = MLX5_GET_PR(cmd_hca_cap, out, log_pg_sz);
346 gen->bf_reg_size = MLX5_GET_PR(cmd_hca_cap, out, bf);
347 gen->bf_reg_size = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_bf_reg_size);
348 gen->max_sq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_sq);
349 gen->max_rq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_rq);
350 gen->max_dc_sq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_sq_dc);
351 gen->max_qp_mcg = MLX5_GET_PR(cmd_hca_cap, out, max_qp_mcg);
352 gen->log_max_pd = MLX5_GET_PR(cmd_hca_cap, out, log_max_pd);
353 gen->log_max_xrcd = MLX5_GET_PR(cmd_hca_cap, out, log_max_xrcd);
354 gen->log_uar_page_sz = MLX5_GET_PR(cmd_hca_cap, out, log_uar_page_sz);
357 static const char *caps_opmod_str(u16 opmod)
360 case HCA_CAP_OPMOD_GET_MAX:
362 case HCA_CAP_OPMOD_GET_CUR:
369 int mlx5_core_get_caps(struct mlx5_core_dev *dev, struct mlx5_caps *caps,
372 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
373 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
377 memset(in, 0, sizeof(in));
378 out = kzalloc(out_sz, GFP_KERNEL);
381 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
382 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
383 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
387 err = mlx5_cmd_status_to_err_v2(out);
389 mlx5_core_warn(dev, "query max hca cap failed, %d\n", err);
392 mlx5_core_dbg(dev, "%s\n", caps_opmod_str(opmod));
393 fw2drv_caps(caps, MLX5_ADDR_OF(query_hca_cap_out, out, capability));
400 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
402 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
405 memset(out, 0, sizeof(out));
407 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
408 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
412 err = mlx5_cmd_status_to_err_v2(out);
417 static int handle_hca_cap(struct mlx5_core_dev *dev)
419 void *set_ctx = NULL;
420 struct mlx5_profile *prof = dev->profile;
421 struct mlx5_caps *cur_caps = NULL;
422 struct mlx5_caps *max_caps = NULL;
424 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
426 set_ctx = kzalloc(set_sz, GFP_KERNEL);
430 max_caps = kzalloc(sizeof(*max_caps), GFP_KERNEL);
434 cur_caps = kzalloc(sizeof(*cur_caps), GFP_KERNEL);
438 err = mlx5_core_get_caps(dev, max_caps, HCA_CAP_OPMOD_GET_MAX);
442 err = mlx5_core_get_caps(dev, cur_caps, HCA_CAP_OPMOD_GET_CUR);
446 /* we limit the size of the pkey table to 128 entries for now */
447 cur_caps->gen.pkey_table_size = 128;
449 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
450 cur_caps->gen.log_max_qp = prof->log_max_qp;
452 /* disable checksum */
453 cur_caps->gen.flags &= ~MLX5_DEV_CAP_FLAG_CMDIF_CSUM;
455 copy_rw_fields(MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability),
457 err = set_caps(dev, set_ctx, set_sz);
467 static int set_hca_ctrl(struct mlx5_core_dev *dev)
469 struct mlx5_reg_host_endianess he_in;
470 struct mlx5_reg_host_endianess he_out;
473 memset(&he_in, 0, sizeof(he_in));
474 he_in.he = MLX5_SET_HOST_ENDIANNESS;
475 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
476 &he_out, sizeof(he_out),
477 MLX5_REG_HOST_ENDIANNESS, 0, 1);
481 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
484 struct mlx5_enable_hca_mbox_in in;
485 struct mlx5_enable_hca_mbox_out out;
487 memset(&in, 0, sizeof(in));
488 memset(&out, 0, sizeof(out));
489 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
490 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
495 return mlx5_cmd_status_to_err(&out.hdr);
500 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
503 struct mlx5_disable_hca_mbox_in in;
504 struct mlx5_disable_hca_mbox_out out;
506 memset(&in, 0, sizeof(in));
507 memset(&out, 0, sizeof(out));
508 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
509 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
514 return mlx5_cmd_status_to_err(&out.hdr);
519 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
521 struct mlx5_priv *priv = &mdev->priv;
522 struct msix_entry *msix = priv->msix_arr;
523 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
524 int numa_node = dev_to_node(&mdev->pdev->dev);
527 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
528 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
532 err = cpumask_set_cpu_local_first(i, numa_node, priv->irq_info[i].mask);
534 mlx5_core_warn(mdev, "cpumask_set_cpu_local_first failed");
538 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
540 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
548 free_cpumask_var(priv->irq_info[i].mask);
552 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
554 struct mlx5_priv *priv = &mdev->priv;
555 struct msix_entry *msix = priv->msix_arr;
556 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
558 irq_set_affinity_hint(irq, NULL);
559 free_cpumask_var(priv->irq_info[i].mask);
562 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
567 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
568 err = mlx5_irq_set_affinity_hint(mdev, i);
576 for (i--; i >= 0; i--)
577 mlx5_irq_clear_affinity_hint(mdev, i);
582 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
586 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
587 mlx5_irq_clear_affinity_hint(mdev, i);
590 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
592 struct mlx5_eq_table *table = &dev->priv.eq_table;
593 struct mlx5_eq *eq, *n;
596 spin_lock(&table->lock);
597 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
598 if (eq->index == vector) {
605 spin_unlock(&table->lock);
609 EXPORT_SYMBOL(mlx5_vector2eqn);
611 static void free_comp_eqs(struct mlx5_core_dev *dev)
613 struct mlx5_eq_table *table = &dev->priv.eq_table;
614 struct mlx5_eq *eq, *n;
616 spin_lock(&table->lock);
617 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
619 spin_unlock(&table->lock);
620 if (mlx5_destroy_unmap_eq(dev, eq))
621 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
624 spin_lock(&table->lock);
626 spin_unlock(&table->lock);
629 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
631 struct mlx5_eq_table *table = &dev->priv.eq_table;
632 char name[MLX5_MAX_IRQ_NAME];
639 INIT_LIST_HEAD(&table->comp_eqs_list);
640 ncomp_vec = table->num_comp_vectors;
641 nent = MLX5_COMP_EQ_SIZE;
642 for (i = 0; i < ncomp_vec; i++) {
643 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
649 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
650 err = mlx5_create_map_eq(dev, eq,
651 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
652 name, &dev->priv.uuari.uars[0]);
657 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
659 spin_lock(&table->lock);
660 list_add_tail(&eq->list, &table->comp_eqs_list);
661 spin_unlock(&table->lock);
671 static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
673 struct mlx5_priv *priv = &dev->priv;
677 pci_set_drvdata(dev->pdev, dev);
678 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
679 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
681 mutex_init(&priv->pgdir_mutex);
682 INIT_LIST_HEAD(&priv->pgdir_list);
683 spin_lock_init(&priv->mkey_lock);
685 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
689 err = pci_enable_device(pdev);
691 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
695 err = request_bar(pdev);
697 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
701 pci_set_master(pdev);
703 err = set_dma_caps(pdev);
705 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
709 dev->iseg_base = pci_resource_start(dev->pdev, 0);
710 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
713 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
716 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
717 fw_rev_min(dev), fw_rev_sub(dev));
719 err = mlx5_cmd_init(dev);
721 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
725 mlx5_pagealloc_init(dev);
727 err = mlx5_core_enable_hca(dev);
729 dev_err(&pdev->dev, "enable hca failed\n");
730 goto err_pagealloc_cleanup;
733 err = mlx5_satisfy_startup_pages(dev, 1);
735 dev_err(&pdev->dev, "failed to allocate boot pages\n");
736 goto err_disable_hca;
739 err = set_hca_ctrl(dev);
741 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
742 goto reclaim_boot_pages;
745 err = handle_hca_cap(dev);
747 dev_err(&pdev->dev, "handle_hca_cap failed\n");
748 goto reclaim_boot_pages;
751 err = mlx5_satisfy_startup_pages(dev, 0);
753 dev_err(&pdev->dev, "failed to allocate init pages\n");
754 goto reclaim_boot_pages;
757 err = mlx5_pagealloc_start(dev);
759 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
760 goto reclaim_boot_pages;
763 err = mlx5_cmd_init_hca(dev);
765 dev_err(&pdev->dev, "init hca failed\n");
766 goto err_pagealloc_stop;
769 mlx5_start_health_poll(dev);
771 err = mlx5_cmd_query_hca_cap(dev, &dev->caps);
773 dev_err(&pdev->dev, "query hca failed\n");
777 err = mlx5_cmd_query_adapter(dev);
779 dev_err(&pdev->dev, "query adapter failed\n");
783 err = mlx5_enable_msix(dev);
785 dev_err(&pdev->dev, "enable msix failed\n");
789 err = mlx5_eq_init(dev);
791 dev_err(&pdev->dev, "failed to initialize eq\n");
795 err = mlx5_alloc_uuars(dev, &priv->uuari);
797 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
801 err = mlx5_start_eqs(dev);
803 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
807 err = alloc_comp_eqs(dev);
809 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
813 err = mlx5_irq_set_affinity_hints(dev);
815 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
816 goto err_free_comp_eqs;
819 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
821 mlx5_init_cq_table(dev);
822 mlx5_init_qp_table(dev);
823 mlx5_init_srq_table(dev);
824 mlx5_init_mr_table(dev);
835 mlx5_free_uuars(dev, &priv->uuari);
838 mlx5_eq_cleanup(dev);
841 mlx5_disable_msix(dev);
844 mlx5_stop_health_poll(dev);
845 if (mlx5_cmd_teardown_hca(dev)) {
846 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
851 mlx5_pagealloc_stop(dev);
854 mlx5_reclaim_startup_pages(dev);
857 mlx5_core_disable_hca(dev);
859 err_pagealloc_cleanup:
860 mlx5_pagealloc_cleanup(dev);
861 mlx5_cmd_cleanup(dev);
867 pci_clear_master(dev->pdev);
868 release_bar(dev->pdev);
871 pci_disable_device(dev->pdev);
874 debugfs_remove(priv->dbg_root);
878 static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
880 struct mlx5_priv *priv = &dev->priv;
882 mlx5_cleanup_srq_table(dev);
883 mlx5_cleanup_qp_table(dev);
884 mlx5_cleanup_cq_table(dev);
885 mlx5_irq_clear_affinity_hints(dev);
888 mlx5_free_uuars(dev, &priv->uuari);
889 mlx5_eq_cleanup(dev);
890 mlx5_disable_msix(dev);
891 mlx5_stop_health_poll(dev);
892 if (mlx5_cmd_teardown_hca(dev)) {
893 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
896 mlx5_pagealloc_stop(dev);
897 mlx5_reclaim_startup_pages(dev);
898 mlx5_core_disable_hca(dev);
899 mlx5_pagealloc_cleanup(dev);
900 mlx5_cmd_cleanup(dev);
902 pci_clear_master(dev->pdev);
903 release_bar(dev->pdev);
904 pci_disable_device(dev->pdev);
905 debugfs_remove(priv->dbg_root);
908 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
910 struct mlx5_device_context *dev_ctx;
911 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
913 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
915 pr_warn("mlx5_add_device: alloc context failed\n");
919 dev_ctx->intf = intf;
920 dev_ctx->context = intf->add(dev);
922 if (dev_ctx->context) {
923 spin_lock_irq(&priv->ctx_lock);
924 list_add_tail(&dev_ctx->list, &priv->ctx_list);
925 spin_unlock_irq(&priv->ctx_lock);
931 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
933 struct mlx5_device_context *dev_ctx;
934 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
936 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
937 if (dev_ctx->intf == intf) {
938 spin_lock_irq(&priv->ctx_lock);
939 list_del(&dev_ctx->list);
940 spin_unlock_irq(&priv->ctx_lock);
942 intf->remove(dev, dev_ctx->context);
947 static int mlx5_register_device(struct mlx5_core_dev *dev)
949 struct mlx5_priv *priv = &dev->priv;
950 struct mlx5_interface *intf;
952 mutex_lock(&intf_mutex);
953 list_add_tail(&priv->dev_list, &dev_list);
954 list_for_each_entry(intf, &intf_list, list)
955 mlx5_add_device(intf, priv);
956 mutex_unlock(&intf_mutex);
960 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
962 struct mlx5_priv *priv = &dev->priv;
963 struct mlx5_interface *intf;
965 mutex_lock(&intf_mutex);
966 list_for_each_entry(intf, &intf_list, list)
967 mlx5_remove_device(intf, priv);
968 list_del(&priv->dev_list);
969 mutex_unlock(&intf_mutex);
972 int mlx5_register_interface(struct mlx5_interface *intf)
974 struct mlx5_priv *priv;
976 if (!intf->add || !intf->remove)
979 mutex_lock(&intf_mutex);
980 list_add_tail(&intf->list, &intf_list);
981 list_for_each_entry(priv, &dev_list, dev_list)
982 mlx5_add_device(intf, priv);
983 mutex_unlock(&intf_mutex);
987 EXPORT_SYMBOL(mlx5_register_interface);
989 void mlx5_unregister_interface(struct mlx5_interface *intf)
991 struct mlx5_priv *priv;
993 mutex_lock(&intf_mutex);
994 list_for_each_entry(priv, &dev_list, dev_list)
995 mlx5_remove_device(intf, priv);
996 list_del(&intf->list);
997 mutex_unlock(&intf_mutex);
999 EXPORT_SYMBOL(mlx5_unregister_interface);
1001 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
1003 struct mlx5_priv *priv = &mdev->priv;
1004 struct mlx5_device_context *dev_ctx;
1005 unsigned long flags;
1006 void *result = NULL;
1008 spin_lock_irqsave(&priv->ctx_lock, flags);
1010 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
1011 if ((dev_ctx->intf->protocol == protocol) &&
1012 dev_ctx->intf->get_dev) {
1013 result = dev_ctx->intf->get_dev(dev_ctx->context);
1017 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1021 EXPORT_SYMBOL(mlx5_get_protocol_dev);
1023 static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1024 unsigned long param)
1026 struct mlx5_priv *priv = &dev->priv;
1027 struct mlx5_device_context *dev_ctx;
1028 unsigned long flags;
1030 spin_lock_irqsave(&priv->ctx_lock, flags);
1032 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1033 if (dev_ctx->intf->event)
1034 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1036 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1039 struct mlx5_core_event_handler {
1040 void (*event)(struct mlx5_core_dev *dev,
1041 enum mlx5_dev_event event,
1045 #define MLX5_IB_MOD "mlx5_ib"
1047 static int init_one(struct pci_dev *pdev,
1048 const struct pci_device_id *id)
1050 struct mlx5_core_dev *dev;
1051 struct mlx5_priv *priv;
1054 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1056 dev_err(&pdev->dev, "kzalloc failed\n");
1061 pci_set_drvdata(pdev, dev);
1063 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1064 pr_warn("selected profile out of range, selecting default (%d)\n",
1066 prof_sel = MLX5_DEFAULT_PROF;
1068 dev->profile = &profile[prof_sel];
1069 dev->event = mlx5_core_event;
1071 INIT_LIST_HEAD(&priv->ctx_list);
1072 spin_lock_init(&priv->ctx_lock);
1073 err = mlx5_dev_init(dev, pdev);
1075 dev_err(&pdev->dev, "mlx5_dev_init failed %d\n", err);
1079 err = mlx5_register_device(dev);
1081 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1085 err = request_module_nowait(MLX5_IB_MOD);
1087 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1092 mlx5_dev_cleanup(dev);
1097 static void remove_one(struct pci_dev *pdev)
1099 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1101 mlx5_unregister_device(dev);
1102 mlx5_dev_cleanup(dev);
1106 static const struct pci_device_id mlx5_core_pci_table[] = {
1107 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1108 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
1109 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1110 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
1111 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1112 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
1116 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1118 static struct pci_driver mlx5_core_driver = {
1119 .name = DRIVER_NAME,
1120 .id_table = mlx5_core_pci_table,
1122 .remove = remove_one
1125 static int __init init(void)
1129 mlx5_register_debugfs();
1130 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
1131 if (!mlx5_core_wq) {
1137 err = pci_register_driver(&mlx5_core_driver);
1144 mlx5_health_cleanup();
1145 destroy_workqueue(mlx5_core_wq);
1147 mlx5_unregister_debugfs();
1151 static void __exit cleanup(void)
1153 pci_unregister_driver(&mlx5_core_driver);
1154 mlx5_health_cleanup();
1155 destroy_workqueue(mlx5_core_wq);
1156 mlx5_unregister_debugfs();
1160 module_exit(cleanup);