2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/delay.h>
50 #include <linux/mlx5/mlx5_ifc.h>
51 #ifdef CONFIG_RFS_ACCEL
52 #include <linux/cpu_rmap.h>
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
57 #ifdef CONFIG_MLX5_CORE_EN
61 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
62 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
63 MODULE_LICENSE("Dual BSD/GPL");
64 MODULE_VERSION(DRIVER_VERSION);
66 int mlx5_core_debug_mask;
67 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
68 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
70 #define MLX5_DEFAULT_PROF 2
71 static int prof_sel = MLX5_DEFAULT_PROF;
72 module_param_named(prof_sel, prof_sel, int, 0444);
73 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
75 static LIST_HEAD(intf_list);
77 LIST_HEAD(mlx5_dev_list);
78 DEFINE_MUTEX(mlx5_intf_mutex);
80 struct mlx5_device_context {
81 struct list_head list;
82 struct mlx5_interface *intf;
87 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
88 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
91 static struct mlx5_profile profile[] = {
96 .mask = MLX5_PROF_MASK_QP_SIZE,
100 .mask = MLX5_PROF_MASK_QP_SIZE |
101 MLX5_PROF_MASK_MR_CACHE,
170 #define FW_INIT_TIMEOUT_MILI 2000
171 #define FW_INIT_WAIT_MS 2
173 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
175 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
178 while (fw_initializing(dev)) {
179 if (time_after(jiffies, end)) {
183 msleep(FW_INIT_WAIT_MS);
189 static int set_dma_caps(struct pci_dev *pdev)
193 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
195 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
196 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
198 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
203 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
206 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
207 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
210 "Can't set consistent PCI DMA mask, aborting\n");
215 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
219 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
221 struct pci_dev *pdev = dev->pdev;
224 mutex_lock(&dev->pci_status_mutex);
225 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
226 err = pci_enable_device(pdev);
228 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
230 mutex_unlock(&dev->pci_status_mutex);
235 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
237 struct pci_dev *pdev = dev->pdev;
239 mutex_lock(&dev->pci_status_mutex);
240 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
241 pci_disable_device(pdev);
242 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
244 mutex_unlock(&dev->pci_status_mutex);
247 static int request_bar(struct pci_dev *pdev)
251 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
252 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
256 err = pci_request_regions(pdev, DRIVER_NAME);
258 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
263 static void release_bar(struct pci_dev *pdev)
265 pci_release_regions(pdev);
268 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
270 struct mlx5_priv *priv = &dev->priv;
271 struct mlx5_eq_table *table = &priv->eq_table;
272 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
276 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
277 MLX5_EQ_VEC_COMP_BASE;
278 nvec = min_t(int, nvec, num_eqs);
279 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
282 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
284 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
285 if (!priv->msix_arr || !priv->irq_info)
288 for (i = 0; i < nvec; i++)
289 priv->msix_arr[i].entry = i;
291 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
292 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
296 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
301 kfree(priv->irq_info);
302 kfree(priv->msix_arr);
306 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
308 struct mlx5_priv *priv = &dev->priv;
310 pci_disable_msix(dev->pdev);
311 kfree(priv->irq_info);
312 kfree(priv->msix_arr);
315 struct mlx5_reg_host_endianess {
321 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
324 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
325 MLX5_DEV_CAP_FLAG_DCT,
328 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
344 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
349 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
350 enum mlx5_cap_type cap_type,
351 enum mlx5_cap_mode cap_mode)
353 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
354 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
355 void *out, *hca_caps;
356 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
359 memset(in, 0, sizeof(in));
360 out = kzalloc(out_sz, GFP_KERNEL);
364 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
365 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
366 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
369 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
370 cap_type, cap_mode, err);
374 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
377 case HCA_CAP_OPMOD_GET_MAX:
378 memcpy(dev->hca_caps_max[cap_type], hca_caps,
379 MLX5_UN_SZ_BYTES(hca_cap_union));
381 case HCA_CAP_OPMOD_GET_CUR:
382 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
383 MLX5_UN_SZ_BYTES(hca_cap_union));
387 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
397 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
401 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
404 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
407 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
409 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
411 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
412 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
413 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
416 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
420 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
424 if (MLX5_CAP_GEN(dev, atomic)) {
425 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
434 supported_atomic_req_8B_endianess_mode_1);
436 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
439 set_ctx = kzalloc(set_sz, GFP_KERNEL);
443 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
445 /* Set requestor to host endianness */
446 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
447 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
449 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
455 static int handle_hca_cap(struct mlx5_core_dev *dev)
457 void *set_ctx = NULL;
458 struct mlx5_profile *prof = dev->profile;
460 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
463 set_ctx = kzalloc(set_sz, GFP_KERNEL);
467 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
471 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
473 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
474 MLX5_ST_SZ_BYTES(cmd_hca_cap));
476 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
477 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
479 /* we limit the size of the pkey table to 128 entries for now */
480 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
481 to_fw_pkey_sz(dev, 128));
483 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
484 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
487 /* disable cmdif checksum */
488 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
490 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
492 err = set_caps(dev, set_ctx, set_sz,
493 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
500 static int set_hca_ctrl(struct mlx5_core_dev *dev)
502 struct mlx5_reg_host_endianess he_in;
503 struct mlx5_reg_host_endianess he_out;
506 if (!mlx5_core_is_pf(dev))
509 memset(&he_in, 0, sizeof(he_in));
510 he_in.he = MLX5_SET_HOST_ENDIANNESS;
511 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
512 &he_out, sizeof(he_out),
513 MLX5_REG_HOST_ENDIANNESS, 0, 1);
517 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
519 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
520 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
522 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
523 MLX5_SET(enable_hca_in, in, function_id, func_id);
524 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
527 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
529 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
530 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
532 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
533 MLX5_SET(disable_hca_in, in, function_id, func_id);
534 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
537 cycle_t mlx5_read_internal_timer(struct mlx5_core_dev *dev)
539 u32 timer_h, timer_h1, timer_l;
541 timer_h = ioread32be(&dev->iseg->internal_timer_h);
542 timer_l = ioread32be(&dev->iseg->internal_timer_l);
543 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
544 if (timer_h != timer_h1) /* wrap around */
545 timer_l = ioread32be(&dev->iseg->internal_timer_l);
547 return (cycle_t)timer_l | (cycle_t)timer_h1 << 32;
550 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
552 struct mlx5_priv *priv = &mdev->priv;
553 struct msix_entry *msix = priv->msix_arr;
554 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
555 int numa_node = priv->numa_node;
558 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
559 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
563 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
564 priv->irq_info[i].mask);
566 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
568 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
576 free_cpumask_var(priv->irq_info[i].mask);
580 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
582 struct mlx5_priv *priv = &mdev->priv;
583 struct msix_entry *msix = priv->msix_arr;
584 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
586 irq_set_affinity_hint(irq, NULL);
587 free_cpumask_var(priv->irq_info[i].mask);
590 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
595 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
596 err = mlx5_irq_set_affinity_hint(mdev, i);
604 for (i--; i >= 0; i--)
605 mlx5_irq_clear_affinity_hint(mdev, i);
610 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
614 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
615 mlx5_irq_clear_affinity_hint(mdev, i);
618 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
621 struct mlx5_eq_table *table = &dev->priv.eq_table;
622 struct mlx5_eq *eq, *n;
625 spin_lock(&table->lock);
626 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
627 if (eq->index == vector) {
634 spin_unlock(&table->lock);
638 EXPORT_SYMBOL(mlx5_vector2eqn);
640 struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn)
642 struct mlx5_eq_table *table = &dev->priv.eq_table;
645 spin_lock(&table->lock);
646 list_for_each_entry(eq, &table->comp_eqs_list, list)
647 if (eq->eqn == eqn) {
648 spin_unlock(&table->lock);
652 spin_unlock(&table->lock);
654 return ERR_PTR(-ENOENT);
657 static void free_comp_eqs(struct mlx5_core_dev *dev)
659 struct mlx5_eq_table *table = &dev->priv.eq_table;
660 struct mlx5_eq *eq, *n;
662 #ifdef CONFIG_RFS_ACCEL
664 free_irq_cpu_rmap(dev->rmap);
668 spin_lock(&table->lock);
669 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
671 spin_unlock(&table->lock);
672 if (mlx5_destroy_unmap_eq(dev, eq))
673 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
676 spin_lock(&table->lock);
678 spin_unlock(&table->lock);
681 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
683 struct mlx5_eq_table *table = &dev->priv.eq_table;
684 char name[MLX5_MAX_IRQ_NAME];
691 INIT_LIST_HEAD(&table->comp_eqs_list);
692 ncomp_vec = table->num_comp_vectors;
693 nent = MLX5_COMP_EQ_SIZE;
694 #ifdef CONFIG_RFS_ACCEL
695 dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
699 for (i = 0; i < ncomp_vec; i++) {
700 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
706 #ifdef CONFIG_RFS_ACCEL
707 irq_cpu_rmap_add(dev->rmap,
708 dev->priv.msix_arr[i + MLX5_EQ_VEC_COMP_BASE].vector);
710 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
711 err = mlx5_create_map_eq(dev, eq,
712 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
713 name, &dev->priv.uuari.uars[0]);
718 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
720 spin_lock(&table->lock);
721 list_add_tail(&eq->list, &table->comp_eqs_list);
722 spin_unlock(&table->lock);
732 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
734 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
735 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
739 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
740 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
741 query_out, sizeof(query_out));
746 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
747 if (status == MLX5_CMD_STAT_BAD_OP_ERR) {
748 pr_debug("Only ISSI 0 is supported\n");
752 pr_err("failed to query ISSI err(%d)\n", err);
756 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
758 if (sup_issi & (1 << 1)) {
759 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
760 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
762 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
763 MLX5_SET(set_issi_in, set_in, current_issi, 1);
764 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
765 set_out, sizeof(set_out));
767 pr_err("failed to set ISSI=1 err(%d)\n", err);
774 } else if (sup_issi & (1 << 0) || !sup_issi) {
781 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
783 struct mlx5_device_context *dev_ctx;
784 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
786 if (!mlx5_lag_intf_add(intf, priv))
789 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
793 dev_ctx->intf = intf;
794 dev_ctx->context = intf->add(dev);
796 if (dev_ctx->context) {
797 spin_lock_irq(&priv->ctx_lock);
798 list_add_tail(&dev_ctx->list, &priv->ctx_list);
799 spin_unlock_irq(&priv->ctx_lock);
805 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
807 struct mlx5_device_context *dev_ctx;
808 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
810 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
811 if (dev_ctx->intf == intf) {
812 spin_lock_irq(&priv->ctx_lock);
813 list_del(&dev_ctx->list);
814 spin_unlock_irq(&priv->ctx_lock);
816 intf->remove(dev, dev_ctx->context);
822 static int mlx5_register_device(struct mlx5_core_dev *dev)
824 struct mlx5_priv *priv = &dev->priv;
825 struct mlx5_interface *intf;
827 mutex_lock(&mlx5_intf_mutex);
828 list_add_tail(&priv->dev_list, &mlx5_dev_list);
829 list_for_each_entry(intf, &intf_list, list)
830 mlx5_add_device(intf, priv);
831 mutex_unlock(&mlx5_intf_mutex);
836 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
838 struct mlx5_priv *priv = &dev->priv;
839 struct mlx5_interface *intf;
841 mutex_lock(&mlx5_intf_mutex);
842 list_for_each_entry(intf, &intf_list, list)
843 mlx5_remove_device(intf, priv);
844 list_del(&priv->dev_list);
845 mutex_unlock(&mlx5_intf_mutex);
848 int mlx5_register_interface(struct mlx5_interface *intf)
850 struct mlx5_priv *priv;
852 if (!intf->add || !intf->remove)
855 mutex_lock(&mlx5_intf_mutex);
856 list_add_tail(&intf->list, &intf_list);
857 list_for_each_entry(priv, &mlx5_dev_list, dev_list)
858 mlx5_add_device(intf, priv);
859 mutex_unlock(&mlx5_intf_mutex);
863 EXPORT_SYMBOL(mlx5_register_interface);
865 void mlx5_unregister_interface(struct mlx5_interface *intf)
867 struct mlx5_priv *priv;
869 mutex_lock(&mlx5_intf_mutex);
870 list_for_each_entry(priv, &mlx5_dev_list, dev_list)
871 mlx5_remove_device(intf, priv);
872 list_del(&intf->list);
873 mutex_unlock(&mlx5_intf_mutex);
875 EXPORT_SYMBOL(mlx5_unregister_interface);
877 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
879 struct mlx5_priv *priv = &mdev->priv;
880 struct mlx5_device_context *dev_ctx;
884 spin_lock_irqsave(&priv->ctx_lock, flags);
886 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
887 if ((dev_ctx->intf->protocol == protocol) &&
888 dev_ctx->intf->get_dev) {
889 result = dev_ctx->intf->get_dev(dev_ctx->context);
893 spin_unlock_irqrestore(&priv->ctx_lock, flags);
897 EXPORT_SYMBOL(mlx5_get_protocol_dev);
899 /* Must be called with intf_mutex held */
900 void mlx5_add_dev_by_protocol(struct mlx5_core_dev *dev, int protocol)
902 struct mlx5_interface *intf;
904 list_for_each_entry(intf, &intf_list, list)
905 if (intf->protocol == protocol) {
906 mlx5_add_device(intf, &dev->priv);
911 /* Must be called with intf_mutex held */
912 void mlx5_remove_dev_by_protocol(struct mlx5_core_dev *dev, int protocol)
914 struct mlx5_interface *intf;
916 list_for_each_entry(intf, &intf_list, list)
917 if (intf->protocol == protocol) {
918 mlx5_remove_device(intf, &dev->priv);
923 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
925 struct pci_dev *pdev = dev->pdev;
928 pci_set_drvdata(dev->pdev, dev);
929 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
930 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
932 mutex_init(&priv->pgdir_mutex);
933 INIT_LIST_HEAD(&priv->pgdir_list);
934 spin_lock_init(&priv->mkey_lock);
936 mutex_init(&priv->alloc_mutex);
938 priv->numa_node = dev_to_node(&dev->pdev->dev);
940 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
944 err = mlx5_pci_enable_device(dev);
946 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
950 err = request_bar(pdev);
952 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
956 pci_set_master(pdev);
958 err = set_dma_caps(pdev);
960 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
964 dev->iseg_base = pci_resource_start(dev->pdev, 0);
965 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
968 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
975 pci_clear_master(dev->pdev);
976 release_bar(dev->pdev);
978 mlx5_pci_disable_device(dev);
981 debugfs_remove(priv->dbg_root);
985 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
988 pci_clear_master(dev->pdev);
989 release_bar(dev->pdev);
990 mlx5_pci_disable_device(dev);
991 debugfs_remove(priv->dbg_root);
994 #define MLX5_IB_MOD "mlx5_ib"
995 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
997 struct pci_dev *pdev = dev->pdev;
1000 mutex_lock(&dev->intf_state_mutex);
1001 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1002 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
1007 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1008 fw_rev_min(dev), fw_rev_sub(dev));
1010 /* on load removing any previous indication of internal error, device is
1013 dev->state = MLX5_DEVICE_STATE_UP;
1015 err = mlx5_cmd_init(dev);
1017 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
1021 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
1023 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
1024 FW_INIT_TIMEOUT_MILI);
1028 mlx5_pagealloc_init(dev);
1030 err = mlx5_core_enable_hca(dev, 0);
1032 dev_err(&pdev->dev, "enable hca failed\n");
1033 goto err_pagealloc_cleanup;
1036 err = mlx5_core_set_issi(dev);
1038 dev_err(&pdev->dev, "failed to set issi\n");
1039 goto err_disable_hca;
1042 err = mlx5_satisfy_startup_pages(dev, 1);
1044 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1045 goto err_disable_hca;
1048 err = set_hca_ctrl(dev);
1050 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
1051 goto reclaim_boot_pages;
1054 err = handle_hca_cap(dev);
1056 dev_err(&pdev->dev, "handle_hca_cap failed\n");
1057 goto reclaim_boot_pages;
1060 err = handle_hca_cap_atomic(dev);
1062 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1063 goto reclaim_boot_pages;
1066 err = mlx5_satisfy_startup_pages(dev, 0);
1068 dev_err(&pdev->dev, "failed to allocate init pages\n");
1069 goto reclaim_boot_pages;
1072 err = mlx5_pagealloc_start(dev);
1074 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
1075 goto reclaim_boot_pages;
1078 err = mlx5_cmd_init_hca(dev);
1080 dev_err(&pdev->dev, "init hca failed\n");
1081 goto err_pagealloc_stop;
1084 mlx5_start_health_poll(dev);
1086 err = mlx5_query_hca_caps(dev);
1088 dev_err(&pdev->dev, "query hca failed\n");
1092 err = mlx5_query_board_id(dev);
1094 dev_err(&pdev->dev, "query board id failed\n");
1098 err = mlx5_enable_msix(dev);
1100 dev_err(&pdev->dev, "enable msix failed\n");
1104 err = mlx5_eq_init(dev);
1106 dev_err(&pdev->dev, "failed to initialize eq\n");
1110 err = mlx5_alloc_uuars(dev, &priv->uuari);
1112 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1113 goto err_eq_cleanup;
1116 err = mlx5_start_eqs(dev);
1118 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1122 err = alloc_comp_eqs(dev);
1124 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1128 err = mlx5_irq_set_affinity_hints(dev);
1130 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1132 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1134 mlx5_init_cq_table(dev);
1135 mlx5_init_qp_table(dev);
1136 mlx5_init_srq_table(dev);
1137 mlx5_init_mkey_table(dev);
1139 err = mlx5_init_fs(dev);
1141 dev_err(&pdev->dev, "Failed to init flow steering\n");
1145 err = mlx5_init_rl_table(dev);
1147 dev_err(&pdev->dev, "Failed to init rate limiting\n");
1151 #ifdef CONFIG_MLX5_CORE_EN
1152 err = mlx5_eswitch_init(dev);
1154 dev_err(&pdev->dev, "eswitch init failed %d\n", err);
1159 err = mlx5_sriov_init(dev);
1161 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1165 err = mlx5_register_device(dev);
1167 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1171 err = request_module_nowait(MLX5_IB_MOD);
1173 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1175 clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1176 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1178 mutex_unlock(&dev->intf_state_mutex);
1183 if (mlx5_sriov_cleanup(dev))
1184 dev_err(&dev->pdev->dev, "sriov cleanup failed\n");
1186 #ifdef CONFIG_MLX5_CORE_EN
1187 mlx5_eswitch_cleanup(dev->priv.eswitch);
1190 mlx5_cleanup_rl_table(dev);
1192 mlx5_cleanup_fs(dev);
1194 mlx5_cleanup_mkey_table(dev);
1195 mlx5_cleanup_srq_table(dev);
1196 mlx5_cleanup_qp_table(dev);
1197 mlx5_cleanup_cq_table(dev);
1198 mlx5_irq_clear_affinity_hints(dev);
1205 mlx5_free_uuars(dev, &priv->uuari);
1208 mlx5_eq_cleanup(dev);
1211 mlx5_disable_msix(dev);
1214 mlx5_stop_health_poll(dev);
1215 if (mlx5_cmd_teardown_hca(dev)) {
1216 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1221 mlx5_pagealloc_stop(dev);
1224 mlx5_reclaim_startup_pages(dev);
1227 mlx5_core_disable_hca(dev, 0);
1229 err_pagealloc_cleanup:
1230 mlx5_pagealloc_cleanup(dev);
1231 mlx5_cmd_cleanup(dev);
1234 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1235 mutex_unlock(&dev->intf_state_mutex);
1240 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
1244 err = mlx5_sriov_cleanup(dev);
1246 dev_warn(&dev->pdev->dev, "%s: sriov cleanup failed - abort\n",
1251 mutex_lock(&dev->intf_state_mutex);
1252 if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) {
1253 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1257 mlx5_unregister_device(dev);
1258 #ifdef CONFIG_MLX5_CORE_EN
1259 mlx5_eswitch_cleanup(dev->priv.eswitch);
1262 mlx5_cleanup_rl_table(dev);
1263 mlx5_cleanup_fs(dev);
1264 mlx5_cleanup_mkey_table(dev);
1265 mlx5_cleanup_srq_table(dev);
1266 mlx5_cleanup_qp_table(dev);
1267 mlx5_cleanup_cq_table(dev);
1268 mlx5_irq_clear_affinity_hints(dev);
1271 mlx5_free_uuars(dev, &priv->uuari);
1272 mlx5_eq_cleanup(dev);
1273 mlx5_disable_msix(dev);
1274 mlx5_stop_health_poll(dev);
1275 err = mlx5_cmd_teardown_hca(dev);
1277 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1280 mlx5_pagealloc_stop(dev);
1281 mlx5_reclaim_startup_pages(dev);
1282 mlx5_core_disable_hca(dev, 0);
1283 mlx5_pagealloc_cleanup(dev);
1284 mlx5_cmd_cleanup(dev);
1287 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1288 set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1289 mutex_unlock(&dev->intf_state_mutex);
1293 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1294 unsigned long param)
1296 struct mlx5_priv *priv = &dev->priv;
1297 struct mlx5_device_context *dev_ctx;
1298 unsigned long flags;
1300 spin_lock_irqsave(&priv->ctx_lock, flags);
1302 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1303 if (dev_ctx->intf->event)
1304 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1306 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1309 struct mlx5_core_event_handler {
1310 void (*event)(struct mlx5_core_dev *dev,
1311 enum mlx5_dev_event event,
1315 static const struct devlink_ops mlx5_devlink_ops = {
1316 #ifdef CONFIG_MLX5_CORE_EN
1317 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1318 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
1322 static int init_one(struct pci_dev *pdev,
1323 const struct pci_device_id *id)
1325 struct mlx5_core_dev *dev;
1326 struct devlink *devlink;
1327 struct mlx5_priv *priv;
1330 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1332 dev_err(&pdev->dev, "kzalloc failed\n");
1336 dev = devlink_priv(devlink);
1338 priv->pci_dev_data = id->driver_data;
1340 pci_set_drvdata(pdev, dev);
1342 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1344 "selected profile out of range, selecting default (%d)\n",
1346 prof_sel = MLX5_DEFAULT_PROF;
1348 dev->profile = &profile[prof_sel];
1350 dev->event = mlx5_core_event;
1352 INIT_LIST_HEAD(&priv->ctx_list);
1353 spin_lock_init(&priv->ctx_lock);
1354 mutex_init(&dev->pci_status_mutex);
1355 mutex_init(&dev->intf_state_mutex);
1356 err = mlx5_pci_init(dev, priv);
1358 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1362 err = mlx5_health_init(dev);
1364 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1368 err = mlx5_load_one(dev, priv);
1370 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1374 err = devlink_register(devlink, &pdev->dev);
1381 mlx5_unload_one(dev, priv);
1383 mlx5_health_cleanup(dev);
1385 mlx5_pci_close(dev, priv);
1387 pci_set_drvdata(pdev, NULL);
1388 devlink_free(devlink);
1393 static void remove_one(struct pci_dev *pdev)
1395 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1396 struct devlink *devlink = priv_to_devlink(dev);
1397 struct mlx5_priv *priv = &dev->priv;
1399 devlink_unregister(devlink);
1400 if (mlx5_unload_one(dev, priv)) {
1401 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1402 mlx5_health_cleanup(dev);
1405 mlx5_health_cleanup(dev);
1406 mlx5_pci_close(dev, priv);
1407 pci_set_drvdata(pdev, NULL);
1408 devlink_free(devlink);
1411 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1412 pci_channel_state_t state)
1414 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1415 struct mlx5_priv *priv = &dev->priv;
1417 dev_info(&pdev->dev, "%s was called\n", __func__);
1418 mlx5_enter_error_state(dev);
1419 mlx5_unload_one(dev, priv);
1420 pci_save_state(pdev);
1421 mlx5_pci_disable_device(dev);
1422 return state == pci_channel_io_perm_failure ?
1423 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1426 /* wait for the device to show vital signs by waiting
1427 * for the health counter to start counting.
1429 static int wait_vital(struct pci_dev *pdev)
1431 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1432 struct mlx5_core_health *health = &dev->priv.health;
1433 const int niter = 100;
1438 for (i = 0; i < niter; i++) {
1439 count = ioread32be(health->health_counter);
1440 if (count && count != 0xffffffff) {
1441 if (last_count && last_count != count) {
1442 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1453 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1455 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1458 dev_info(&pdev->dev, "%s was called\n", __func__);
1460 err = mlx5_pci_enable_device(dev);
1462 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1464 return PCI_ERS_RESULT_DISCONNECT;
1467 pci_set_master(pdev);
1468 pci_restore_state(pdev);
1470 if (wait_vital(pdev)) {
1471 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1472 return PCI_ERS_RESULT_DISCONNECT;
1475 return PCI_ERS_RESULT_RECOVERED;
1478 void mlx5_disable_device(struct mlx5_core_dev *dev)
1480 mlx5_pci_err_detected(dev->pdev, 0);
1483 static void mlx5_pci_resume(struct pci_dev *pdev)
1485 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1486 struct mlx5_priv *priv = &dev->priv;
1489 dev_info(&pdev->dev, "%s was called\n", __func__);
1491 err = mlx5_load_one(dev, priv);
1493 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1496 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1499 static const struct pci_error_handlers mlx5_err_handler = {
1500 .error_detected = mlx5_pci_err_detected,
1501 .slot_reset = mlx5_pci_slot_reset,
1502 .resume = mlx5_pci_resume
1505 static void shutdown(struct pci_dev *pdev)
1507 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1508 struct mlx5_priv *priv = &dev->priv;
1510 dev_info(&pdev->dev, "Shutdown was called\n");
1511 /* Notify mlx5 clients that the kernel is being shut down */
1512 set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state);
1513 mlx5_unload_one(dev, priv);
1514 mlx5_pci_disable_device(dev);
1517 static const struct pci_device_id mlx5_core_pci_table[] = {
1518 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1519 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1520 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1521 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1522 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1523 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1524 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1525 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1526 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5, PCIe 4.0 */
1530 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1532 static struct pci_driver mlx5_core_driver = {
1533 .name = DRIVER_NAME,
1534 .id_table = mlx5_core_pci_table,
1536 .remove = remove_one,
1537 .shutdown = shutdown,
1538 .err_handler = &mlx5_err_handler,
1539 .sriov_configure = mlx5_core_sriov_configure,
1542 static int __init init(void)
1546 mlx5_register_debugfs();
1548 err = pci_register_driver(&mlx5_core_driver);
1552 #ifdef CONFIG_MLX5_CORE_EN
1559 mlx5_unregister_debugfs();
1563 static void __exit cleanup(void)
1565 #ifdef CONFIG_MLX5_CORE_EN
1568 pci_unregister_driver(&mlx5_core_driver);
1569 mlx5_unregister_debugfs();
1573 module_exit(cleanup);