2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <asm-generic/kmap_types.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/qp.h>
45 #include <linux/mlx5/srq.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include "mlx5_core.h"
51 #define DRIVER_NAME "mlx5_core"
52 #define DRIVER_VERSION "3.0"
53 #define DRIVER_RELDATE "January 2015"
55 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
56 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
57 MODULE_LICENSE("Dual BSD/GPL");
58 MODULE_VERSION(DRIVER_VERSION);
60 int mlx5_core_debug_mask;
61 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
62 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
64 #define MLX5_DEFAULT_PROF 2
65 static int prof_sel = MLX5_DEFAULT_PROF;
66 module_param_named(prof_sel, prof_sel, int, 0444);
67 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
69 struct workqueue_struct *mlx5_core_wq;
70 static LIST_HEAD(intf_list);
71 static LIST_HEAD(dev_list);
72 static DEFINE_MUTEX(intf_mutex);
74 struct mlx5_device_context {
75 struct list_head list;
76 struct mlx5_interface *intf;
80 static struct mlx5_profile profile[] = {
85 .mask = MLX5_PROF_MASK_QP_SIZE,
89 .mask = MLX5_PROF_MASK_QP_SIZE |
90 MLX5_PROF_MASK_MR_CACHE,
159 static int set_dma_caps(struct pci_dev *pdev)
163 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
165 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
166 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
168 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
173 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
176 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
177 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
180 "Can't set consistent PCI DMA mask, aborting\n");
185 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
189 static int request_bar(struct pci_dev *pdev)
193 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
194 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
198 err = pci_request_regions(pdev, DRIVER_NAME);
200 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
205 static void release_bar(struct pci_dev *pdev)
207 pci_release_regions(pdev);
210 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
212 struct mlx5_priv *priv = &dev->priv;
213 struct mlx5_eq_table *table = &priv->eq_table;
214 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
218 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
219 MLX5_EQ_VEC_COMP_BASE;
220 nvec = min_t(int, nvec, num_eqs);
221 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
224 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
226 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
227 if (!priv->msix_arr || !priv->irq_info)
230 for (i = 0; i < nvec; i++)
231 priv->msix_arr[i].entry = i;
233 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
234 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
238 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
243 kfree(priv->irq_info);
244 kfree(priv->msix_arr);
248 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
250 struct mlx5_priv *priv = &dev->priv;
252 pci_disable_msix(dev->pdev);
253 kfree(priv->irq_info);
254 kfree(priv->msix_arr);
257 struct mlx5_reg_host_endianess {
263 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
266 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
267 MLX5_DEV_CAP_FLAG_DCT,
270 static u16 to_fw_pkey_sz(u32 size)
286 pr_warn("invalid pkey table size %d\n", size);
291 static u16 to_sw_pkey_sz(int pkey_sz)
293 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
296 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
299 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
300 enum mlx5_cap_mode cap_mode)
302 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
303 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
304 void *out, *hca_caps;
305 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
308 memset(in, 0, sizeof(in));
309 out = kzalloc(out_sz, GFP_KERNEL);
313 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
314 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
315 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
319 err = mlx5_cmd_status_to_err_v2(out);
322 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
323 cap_type, cap_mode, err);
327 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
330 case HCA_CAP_OPMOD_GET_MAX:
331 memcpy(dev->hca_caps_max[cap_type], hca_caps,
332 MLX5_UN_SZ_BYTES(hca_cap_union));
334 case HCA_CAP_OPMOD_GET_CUR:
335 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
336 MLX5_UN_SZ_BYTES(hca_cap_union));
340 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
350 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
352 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
355 memset(out, 0, sizeof(out));
357 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
358 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
362 err = mlx5_cmd_status_to_err_v2(out);
367 static int handle_hca_cap(struct mlx5_core_dev *dev)
369 void *set_ctx = NULL;
370 struct mlx5_profile *prof = dev->profile;
372 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
375 set_ctx = kzalloc(set_sz, GFP_KERNEL);
379 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
383 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
387 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
389 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
390 MLX5_ST_SZ_BYTES(cmd_hca_cap));
392 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
393 to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
395 /* we limit the size of the pkey table to 128 entries for now */
396 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
399 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
400 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
403 /* disable cmdif checksum */
404 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
406 err = set_caps(dev, set_ctx, set_sz);
413 static int set_hca_ctrl(struct mlx5_core_dev *dev)
415 struct mlx5_reg_host_endianess he_in;
416 struct mlx5_reg_host_endianess he_out;
419 memset(&he_in, 0, sizeof(he_in));
420 he_in.he = MLX5_SET_HOST_ENDIANNESS;
421 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
422 &he_out, sizeof(he_out),
423 MLX5_REG_HOST_ENDIANNESS, 0, 1);
427 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
430 struct mlx5_enable_hca_mbox_in in;
431 struct mlx5_enable_hca_mbox_out out;
433 memset(&in, 0, sizeof(in));
434 memset(&out, 0, sizeof(out));
435 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
436 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
441 return mlx5_cmd_status_to_err(&out.hdr);
446 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
449 struct mlx5_disable_hca_mbox_in in;
450 struct mlx5_disable_hca_mbox_out out;
452 memset(&in, 0, sizeof(in));
453 memset(&out, 0, sizeof(out));
454 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
455 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
460 return mlx5_cmd_status_to_err(&out.hdr);
465 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
467 struct mlx5_priv *priv = &mdev->priv;
468 struct msix_entry *msix = priv->msix_arr;
469 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
470 int numa_node = dev_to_node(&mdev->pdev->dev);
473 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
474 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
478 err = cpumask_set_cpu_local_first(i, numa_node, priv->irq_info[i].mask);
480 mlx5_core_warn(mdev, "cpumask_set_cpu_local_first failed");
484 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
486 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
494 free_cpumask_var(priv->irq_info[i].mask);
498 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
500 struct mlx5_priv *priv = &mdev->priv;
501 struct msix_entry *msix = priv->msix_arr;
502 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
504 irq_set_affinity_hint(irq, NULL);
505 free_cpumask_var(priv->irq_info[i].mask);
508 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
513 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
514 err = mlx5_irq_set_affinity_hint(mdev, i);
522 for (i--; i >= 0; i--)
523 mlx5_irq_clear_affinity_hint(mdev, i);
528 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
532 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
533 mlx5_irq_clear_affinity_hint(mdev, i);
536 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
538 struct mlx5_eq_table *table = &dev->priv.eq_table;
539 struct mlx5_eq *eq, *n;
542 spin_lock(&table->lock);
543 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
544 if (eq->index == vector) {
551 spin_unlock(&table->lock);
555 EXPORT_SYMBOL(mlx5_vector2eqn);
557 static void free_comp_eqs(struct mlx5_core_dev *dev)
559 struct mlx5_eq_table *table = &dev->priv.eq_table;
560 struct mlx5_eq *eq, *n;
562 spin_lock(&table->lock);
563 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
565 spin_unlock(&table->lock);
566 if (mlx5_destroy_unmap_eq(dev, eq))
567 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
570 spin_lock(&table->lock);
572 spin_unlock(&table->lock);
575 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
577 struct mlx5_eq_table *table = &dev->priv.eq_table;
578 char name[MLX5_MAX_IRQ_NAME];
585 INIT_LIST_HEAD(&table->comp_eqs_list);
586 ncomp_vec = table->num_comp_vectors;
587 nent = MLX5_COMP_EQ_SIZE;
588 for (i = 0; i < ncomp_vec; i++) {
589 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
595 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
596 err = mlx5_create_map_eq(dev, eq,
597 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
598 name, &dev->priv.uuari.uars[0]);
603 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
605 spin_lock(&table->lock);
606 list_add_tail(&eq->list, &table->comp_eqs_list);
607 spin_unlock(&table->lock);
617 static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
619 struct mlx5_priv *priv = &dev->priv;
623 pci_set_drvdata(dev->pdev, dev);
624 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
625 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
627 mutex_init(&priv->pgdir_mutex);
628 INIT_LIST_HEAD(&priv->pgdir_list);
629 spin_lock_init(&priv->mkey_lock);
631 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
635 err = pci_enable_device(pdev);
637 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
641 err = request_bar(pdev);
643 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
647 pci_set_master(pdev);
649 err = set_dma_caps(pdev);
651 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
655 dev->iseg_base = pci_resource_start(dev->pdev, 0);
656 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
659 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
662 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
663 fw_rev_min(dev), fw_rev_sub(dev));
665 err = mlx5_cmd_init(dev);
667 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
671 mlx5_pagealloc_init(dev);
673 err = mlx5_core_enable_hca(dev);
675 dev_err(&pdev->dev, "enable hca failed\n");
676 goto err_pagealloc_cleanup;
679 err = mlx5_satisfy_startup_pages(dev, 1);
681 dev_err(&pdev->dev, "failed to allocate boot pages\n");
682 goto err_disable_hca;
685 err = set_hca_ctrl(dev);
687 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
688 goto reclaim_boot_pages;
691 err = handle_hca_cap(dev);
693 dev_err(&pdev->dev, "handle_hca_cap failed\n");
694 goto reclaim_boot_pages;
697 err = mlx5_satisfy_startup_pages(dev, 0);
699 dev_err(&pdev->dev, "failed to allocate init pages\n");
700 goto reclaim_boot_pages;
703 err = mlx5_pagealloc_start(dev);
705 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
706 goto reclaim_boot_pages;
709 err = mlx5_cmd_init_hca(dev);
711 dev_err(&pdev->dev, "init hca failed\n");
712 goto err_pagealloc_stop;
715 mlx5_start_health_poll(dev);
717 err = mlx5_query_hca_caps(dev);
719 dev_err(&pdev->dev, "query hca failed\n");
723 err = mlx5_cmd_query_adapter(dev);
725 dev_err(&pdev->dev, "query adapter failed\n");
729 err = mlx5_enable_msix(dev);
731 dev_err(&pdev->dev, "enable msix failed\n");
735 err = mlx5_eq_init(dev);
737 dev_err(&pdev->dev, "failed to initialize eq\n");
741 err = mlx5_alloc_uuars(dev, &priv->uuari);
743 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
747 err = mlx5_start_eqs(dev);
749 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
753 err = alloc_comp_eqs(dev);
755 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
759 err = mlx5_irq_set_affinity_hints(dev);
761 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
762 goto err_free_comp_eqs;
765 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
767 mlx5_init_cq_table(dev);
768 mlx5_init_qp_table(dev);
769 mlx5_init_srq_table(dev);
770 mlx5_init_mr_table(dev);
781 mlx5_free_uuars(dev, &priv->uuari);
784 mlx5_eq_cleanup(dev);
787 mlx5_disable_msix(dev);
790 mlx5_stop_health_poll(dev);
791 if (mlx5_cmd_teardown_hca(dev)) {
792 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
797 mlx5_pagealloc_stop(dev);
800 mlx5_reclaim_startup_pages(dev);
803 mlx5_core_disable_hca(dev);
805 err_pagealloc_cleanup:
806 mlx5_pagealloc_cleanup(dev);
807 mlx5_cmd_cleanup(dev);
813 pci_clear_master(dev->pdev);
814 release_bar(dev->pdev);
817 pci_disable_device(dev->pdev);
820 debugfs_remove(priv->dbg_root);
824 static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
826 struct mlx5_priv *priv = &dev->priv;
828 mlx5_cleanup_srq_table(dev);
829 mlx5_cleanup_qp_table(dev);
830 mlx5_cleanup_cq_table(dev);
831 mlx5_irq_clear_affinity_hints(dev);
834 mlx5_free_uuars(dev, &priv->uuari);
835 mlx5_eq_cleanup(dev);
836 mlx5_disable_msix(dev);
837 mlx5_stop_health_poll(dev);
838 if (mlx5_cmd_teardown_hca(dev)) {
839 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
842 mlx5_pagealloc_stop(dev);
843 mlx5_reclaim_startup_pages(dev);
844 mlx5_core_disable_hca(dev);
845 mlx5_pagealloc_cleanup(dev);
846 mlx5_cmd_cleanup(dev);
848 pci_clear_master(dev->pdev);
849 release_bar(dev->pdev);
850 pci_disable_device(dev->pdev);
851 debugfs_remove(priv->dbg_root);
854 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
856 struct mlx5_device_context *dev_ctx;
857 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
859 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
861 pr_warn("mlx5_add_device: alloc context failed\n");
865 dev_ctx->intf = intf;
866 dev_ctx->context = intf->add(dev);
868 if (dev_ctx->context) {
869 spin_lock_irq(&priv->ctx_lock);
870 list_add_tail(&dev_ctx->list, &priv->ctx_list);
871 spin_unlock_irq(&priv->ctx_lock);
877 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
879 struct mlx5_device_context *dev_ctx;
880 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
882 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
883 if (dev_ctx->intf == intf) {
884 spin_lock_irq(&priv->ctx_lock);
885 list_del(&dev_ctx->list);
886 spin_unlock_irq(&priv->ctx_lock);
888 intf->remove(dev, dev_ctx->context);
893 static int mlx5_register_device(struct mlx5_core_dev *dev)
895 struct mlx5_priv *priv = &dev->priv;
896 struct mlx5_interface *intf;
898 mutex_lock(&intf_mutex);
899 list_add_tail(&priv->dev_list, &dev_list);
900 list_for_each_entry(intf, &intf_list, list)
901 mlx5_add_device(intf, priv);
902 mutex_unlock(&intf_mutex);
906 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
908 struct mlx5_priv *priv = &dev->priv;
909 struct mlx5_interface *intf;
911 mutex_lock(&intf_mutex);
912 list_for_each_entry(intf, &intf_list, list)
913 mlx5_remove_device(intf, priv);
914 list_del(&priv->dev_list);
915 mutex_unlock(&intf_mutex);
918 int mlx5_register_interface(struct mlx5_interface *intf)
920 struct mlx5_priv *priv;
922 if (!intf->add || !intf->remove)
925 mutex_lock(&intf_mutex);
926 list_add_tail(&intf->list, &intf_list);
927 list_for_each_entry(priv, &dev_list, dev_list)
928 mlx5_add_device(intf, priv);
929 mutex_unlock(&intf_mutex);
933 EXPORT_SYMBOL(mlx5_register_interface);
935 void mlx5_unregister_interface(struct mlx5_interface *intf)
937 struct mlx5_priv *priv;
939 mutex_lock(&intf_mutex);
940 list_for_each_entry(priv, &dev_list, dev_list)
941 mlx5_remove_device(intf, priv);
942 list_del(&intf->list);
943 mutex_unlock(&intf_mutex);
945 EXPORT_SYMBOL(mlx5_unregister_interface);
947 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
949 struct mlx5_priv *priv = &mdev->priv;
950 struct mlx5_device_context *dev_ctx;
954 spin_lock_irqsave(&priv->ctx_lock, flags);
956 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
957 if ((dev_ctx->intf->protocol == protocol) &&
958 dev_ctx->intf->get_dev) {
959 result = dev_ctx->intf->get_dev(dev_ctx->context);
963 spin_unlock_irqrestore(&priv->ctx_lock, flags);
967 EXPORT_SYMBOL(mlx5_get_protocol_dev);
969 static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
972 struct mlx5_priv *priv = &dev->priv;
973 struct mlx5_device_context *dev_ctx;
976 spin_lock_irqsave(&priv->ctx_lock, flags);
978 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
979 if (dev_ctx->intf->event)
980 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
982 spin_unlock_irqrestore(&priv->ctx_lock, flags);
985 struct mlx5_core_event_handler {
986 void (*event)(struct mlx5_core_dev *dev,
987 enum mlx5_dev_event event,
991 #define MLX5_IB_MOD "mlx5_ib"
993 static int init_one(struct pci_dev *pdev,
994 const struct pci_device_id *id)
996 struct mlx5_core_dev *dev;
997 struct mlx5_priv *priv;
1000 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1002 dev_err(&pdev->dev, "kzalloc failed\n");
1007 pci_set_drvdata(pdev, dev);
1009 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1010 pr_warn("selected profile out of range, selecting default (%d)\n",
1012 prof_sel = MLX5_DEFAULT_PROF;
1014 dev->profile = &profile[prof_sel];
1015 dev->event = mlx5_core_event;
1017 INIT_LIST_HEAD(&priv->ctx_list);
1018 spin_lock_init(&priv->ctx_lock);
1019 err = mlx5_dev_init(dev, pdev);
1021 dev_err(&pdev->dev, "mlx5_dev_init failed %d\n", err);
1025 err = mlx5_register_device(dev);
1027 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1031 err = request_module_nowait(MLX5_IB_MOD);
1033 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1038 mlx5_dev_cleanup(dev);
1043 static void remove_one(struct pci_dev *pdev)
1045 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1047 mlx5_unregister_device(dev);
1048 mlx5_dev_cleanup(dev);
1052 static const struct pci_device_id mlx5_core_pci_table[] = {
1053 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1054 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
1055 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1056 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
1057 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1058 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
1062 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1064 static struct pci_driver mlx5_core_driver = {
1065 .name = DRIVER_NAME,
1066 .id_table = mlx5_core_pci_table,
1068 .remove = remove_one
1071 static int __init init(void)
1075 mlx5_register_debugfs();
1076 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
1077 if (!mlx5_core_wq) {
1083 err = pci_register_driver(&mlx5_core_driver);
1090 mlx5_health_cleanup();
1091 destroy_workqueue(mlx5_core_wq);
1093 mlx5_unregister_debugfs();
1097 static void __exit cleanup(void)
1099 pci_unregister_driver(&mlx5_core_driver);
1100 mlx5_health_cleanup();
1101 destroy_workqueue(mlx5_core_wq);
1102 mlx5_unregister_debugfs();
1106 module_exit(cleanup);