2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
34 #include <linux/mlx5/driver.h>
35 #include <linux/mlx5/port.h>
36 #include <linux/mlx5/cmd.h>
37 #include "mlx5_core.h"
39 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
40 int size_in, void *data_out, int size_out,
41 u16 reg_num, int arg, int write)
43 struct mlx5_access_reg_mbox_in *in = NULL;
44 struct mlx5_access_reg_mbox_out *out = NULL;
47 in = mlx5_vzalloc(sizeof(*in) + size_in);
51 out = mlx5_vzalloc(sizeof(*out) + size_out);
55 memcpy(in->data, data_in, size_in);
56 in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ACCESS_REG);
57 in->hdr.opmod = cpu_to_be16(!write);
58 in->arg = cpu_to_be32(arg);
59 in->register_id = cpu_to_be16(reg_num);
60 err = mlx5_cmd_exec(dev, in, sizeof(*in) + size_in, out,
61 sizeof(*out) + size_out);
66 err = mlx5_cmd_status_to_err(&out->hdr);
69 memcpy(data_out, out->data, size_out);
77 EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
80 struct mlx5_reg_pcap {
90 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
92 struct mlx5_reg_pcap in;
93 struct mlx5_reg_pcap out;
95 memset(&in, 0, sizeof(in));
96 in.caps_127_96 = cpu_to_be32(caps);
97 in.port_num = port_num;
99 return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
100 sizeof(out), MLX5_REG_PCAP, 0, 1);
102 EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
104 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
105 int ptys_size, int proto_mask, u8 local_port)
107 u32 in[MLX5_ST_SZ_DW(ptys_reg)];
109 memset(in, 0, sizeof(in));
110 MLX5_SET(ptys_reg, in, local_port, local_port);
111 MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
113 return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
114 ptys_size, MLX5_REG_PTYS, 0, 0);
116 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
118 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
119 u32 *proto_cap, int proto_mask)
121 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
124 err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
128 if (proto_mask == MLX5_PTYS_EN)
129 *proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
131 *proto_cap = MLX5_GET(ptys_reg, out, ib_proto_capability);
135 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap);
137 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
138 u32 *proto_admin, int proto_mask)
140 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
143 err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
147 if (proto_mask == MLX5_PTYS_EN)
148 *proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
150 *proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin);
154 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin);
156 int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
157 u8 *link_width_oper, u8 local_port)
159 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
162 err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB, local_port);
166 *link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);
170 EXPORT_SYMBOL_GPL(mlx5_query_port_link_width_oper);
172 int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
173 u8 *proto_oper, int proto_mask,
176 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
179 err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, local_port);
183 if (proto_mask == MLX5_PTYS_EN)
184 *proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
186 *proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
190 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_oper);
192 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
195 u32 in[MLX5_ST_SZ_DW(ptys_reg)];
196 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
198 memset(in, 0, sizeof(in));
200 MLX5_SET(ptys_reg, in, local_port, 1);
201 MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
202 if (proto_mask == MLX5_PTYS_EN)
203 MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
205 MLX5_SET(ptys_reg, in, ib_proto_admin, proto_admin);
207 return mlx5_core_access_reg(dev, in, sizeof(in), out,
208 sizeof(out), MLX5_REG_PTYS, 0, 1);
210 EXPORT_SYMBOL_GPL(mlx5_set_port_proto);
212 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
213 enum mlx5_port_status status)
215 u32 in[MLX5_ST_SZ_DW(paos_reg)];
216 u32 out[MLX5_ST_SZ_DW(paos_reg)];
218 memset(in, 0, sizeof(in));
220 MLX5_SET(paos_reg, in, local_port, 1);
221 MLX5_SET(paos_reg, in, admin_status, status);
222 MLX5_SET(paos_reg, in, ase, 1);
224 return mlx5_core_access_reg(dev, in, sizeof(in), out,
225 sizeof(out), MLX5_REG_PAOS, 0, 1);
227 EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);
229 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
230 enum mlx5_port_status *status)
232 u32 in[MLX5_ST_SZ_DW(paos_reg)];
233 u32 out[MLX5_ST_SZ_DW(paos_reg)];
236 memset(in, 0, sizeof(in));
238 MLX5_SET(paos_reg, in, local_port, 1);
240 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
241 sizeof(out), MLX5_REG_PAOS, 0, 0);
245 *status = MLX5_GET(paos_reg, out, admin_status);
248 EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
250 static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, int *admin_mtu,
251 int *max_mtu, int *oper_mtu, u8 port)
253 u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
254 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
256 memset(in, 0, sizeof(in));
258 MLX5_SET(pmtu_reg, in, local_port, port);
260 mlx5_core_access_reg(dev, in, sizeof(in), out,
261 sizeof(out), MLX5_REG_PMTU, 0, 0);
264 *max_mtu = MLX5_GET(pmtu_reg, out, max_mtu);
266 *oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
268 *admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
271 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port)
273 u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
274 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
276 memset(in, 0, sizeof(in));
278 MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
279 MLX5_SET(pmtu_reg, in, local_port, port);
281 return mlx5_core_access_reg(dev, in, sizeof(in), out,
282 sizeof(out), MLX5_REG_PMTU, 0, 1);
284 EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
286 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu,
289 mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
291 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
293 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu,
296 mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
298 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
300 static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc,
301 int pvlc_size, u8 local_port)
303 u32 in[MLX5_ST_SZ_DW(pvlc_reg)];
305 memset(in, 0, sizeof(in));
306 MLX5_SET(pvlc_reg, in, local_port, local_port);
308 return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
309 pvlc_size, MLX5_REG_PVLC, 0, 0);
312 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
313 u8 *vl_hw_cap, u8 local_port)
315 u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
318 err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
322 *vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
326 EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);
328 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
330 u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
331 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
333 memset(in, 0, sizeof(in));
334 MLX5_SET(pfcc_reg, in, local_port, 1);
335 MLX5_SET(pfcc_reg, in, pptx, tx_pause);
336 MLX5_SET(pfcc_reg, in, pprx, rx_pause);
338 return mlx5_core_access_reg(dev, in, sizeof(in), out,
339 sizeof(out), MLX5_REG_PFCC, 0, 1);
341 EXPORT_SYMBOL_GPL(mlx5_set_port_pause);
343 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
344 u32 *rx_pause, u32 *tx_pause)
346 u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
347 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
350 memset(in, 0, sizeof(in));
351 MLX5_SET(pfcc_reg, in, local_port, 1);
353 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
354 sizeof(out), MLX5_REG_PFCC, 0, 0);
359 *rx_pause = MLX5_GET(pfcc_reg, out, pprx);
362 *tx_pause = MLX5_GET(pfcc_reg, out, pptx);
366 EXPORT_SYMBOL_GPL(mlx5_query_port_pause);
368 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx)
370 u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
371 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
373 memset(in, 0, sizeof(in));
374 MLX5_SET(pfcc_reg, in, local_port, 1);
375 MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
376 MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
377 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
378 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);
380 return mlx5_core_access_reg(dev, in, sizeof(in), out,
381 sizeof(out), MLX5_REG_PFCC, 0, 1);
383 EXPORT_SYMBOL_GPL(mlx5_set_port_pfc);
385 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx)
387 u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
388 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
391 memset(in, 0, sizeof(in));
392 MLX5_SET(pfcc_reg, in, local_port, 1);
394 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
395 sizeof(out), MLX5_REG_PFCC, 0, 0);
400 *pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);
403 *pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);
407 EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);
409 int mlx5_max_tc(struct mlx5_core_dev *mdev)
411 u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;
416 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc)
418 u32 in[MLX5_ST_SZ_DW(qtct_reg)];
419 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
423 memset(in, 0, sizeof(in));
424 for (i = 0; i < 8; i++) {
425 if (prio_tc[i] > mlx5_max_tc(mdev))
428 MLX5_SET(qtct_reg, in, prio, i);
429 MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);
431 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
432 sizeof(out), MLX5_REG_QTCT, 0, 1);
439 EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);
441 static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in,
444 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
446 if (!MLX5_CAP_GEN(mdev, ets))
449 return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
450 MLX5_REG_QETCR, 0, 1);
453 static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *out,
456 u32 in[MLX5_ST_SZ_DW(qtct_reg)];
458 if (!MLX5_CAP_GEN(mdev, ets))
461 memset(in, 0, sizeof(in));
462 return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen,
463 MLX5_REG_QETCR, 0, 0);
466 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group)
468 u32 in[MLX5_ST_SZ_DW(qetc_reg)];
471 memset(in, 0, sizeof(in));
473 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
474 MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
475 MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
478 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
480 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);
482 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw)
484 u32 in[MLX5_ST_SZ_DW(qetc_reg)];
487 memset(in, 0, sizeof(in));
489 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
490 MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
491 MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
494 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
496 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);
498 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
502 u32 in[MLX5_ST_SZ_DW(qetc_reg)];
506 memset(in, 0, sizeof(in));
508 MLX5_SET(qetc_reg, in, port_number, 1);
510 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
511 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]);
513 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, r, 1);
514 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_units,
516 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_value,
520 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
522 EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit);
524 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
528 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
533 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
537 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
538 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, tc_configuration[i]);
540 max_bw_value[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
542 max_bw_units[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
548 EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit);