drivers/net/ethernet/qlogic/qed/qed_dev.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #include <linux/types.h>
  10 #include <asm/byteorder.h>
  11 #include <linux/io.h>
  12 #include <linux/delay.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/errno.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mutex.h>
  17 #include <linux/pci.h>
  18 #include <linux/slab.h>
  19 #include <linux/string.h>
  20 #include <linux/vmalloc.h>
  21 #include <linux/etherdevice.h>
  22 #include <linux/qed/qed_chain.h>
  23 #include <linux/qed/qed_if.h>
  24 #include "qed.h"
  25 #include "qed_cxt.h"
  26 #include "qed_dcbx.h"
  27 #include "qed_dev_api.h"
  28 #include "qed_hsi.h"
  29 #include "qed_hw.h"
  30 #include "qed_init_ops.h"
  31 #include "qed_int.h"
  32 #include "qed_ll2.h"
  33 #include "qed_mcp.h"
  34 #include "qed_reg_addr.h"
  35 #include "qed_sp.h"
  36 #include "qed_sriov.h"
  37 #include "qed_vf.h"
  38 #include "qed_roce.h"
  39
  40 static DEFINE_SPINLOCK(qm_lock);
  41
  42 #define QED_MIN_DPIS            (4)
  43 #define QED_MIN_PWM_REGION      (QED_WID_SIZE * QED_MIN_DPIS)
  44
  45 /* API common to all protocols */
  46 enum BAR_ID {
  47         BAR_ID_0,       /* used for GRC */
  48         BAR_ID_1        /* Used for doorbells */
  49 };
  50
  51 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, enum BAR_ID bar_id)
  52 {
  53         u32 bar_reg = (bar_id == BAR_ID_0 ?
  54                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  55         u32 val;
  56
  57         if (IS_VF(p_hwfn->cdev))
  58                 return 1 << 17;
  59
  60         val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  61         if (val)
  62                 return 1 << (val + 15);
  63
  64         /* Old MFW initialized above registered only conditionally */
  65         if (p_hwfn->cdev->num_hwfns > 1) {
  66                 DP_INFO(p_hwfn,
  67                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
  68                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  69         } else {
  70                 DP_INFO(p_hwfn,
  71                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
  72                         return 512 * 1024;
  73         }
  74 }
  75
  76 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
  77 {
  78         u32 i;
  79
  80         cdev->dp_level = dp_level;
  81         cdev->dp_module = dp_module;
  82         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
  83                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  84
  85                 p_hwfn->dp_level = dp_level;
  86                 p_hwfn->dp_module = dp_module;
  87         }
  88 }
  89
  90 void qed_init_struct(struct qed_dev *cdev)
  91 {
  92         u8 i;
  93
  94         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
  95                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  96
  97                 p_hwfn->cdev = cdev;
  98                 p_hwfn->my_id = i;
  99                 p_hwfn->b_active = false;
 100
 101                 mutex_init(&p_hwfn->dmae_info.mutex);
 102         }
 103
 104         /* hwfn 0 is always active */
 105         cdev->hwfns[0].b_active = true;
 106
 107         /* set the default cache alignment to 128 */
 108         cdev->cache_shift = 7;
 109 }
 110
 111 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
 112 {
 113         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 114
 115         kfree(qm_info->qm_pq_params);
 116         qm_info->qm_pq_params = NULL;
 117         kfree(qm_info->qm_vport_params);
 118         qm_info->qm_vport_params = NULL;
 119         kfree(qm_info->qm_port_params);
 120         qm_info->qm_port_params = NULL;
 121         kfree(qm_info->wfq_data);
 122         qm_info->wfq_data = NULL;
 123 }
 124
 125 void qed_resc_free(struct qed_dev *cdev)
 126 {
 127         int i;
 128
 129         if (IS_VF(cdev))
 130                 return;
 131
 132         kfree(cdev->fw_data);
 133         cdev->fw_data = NULL;
 134
 135         kfree(cdev->reset_stats);
 136
 137         for_each_hwfn(cdev, i) {
 138                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 139
 140                 kfree(p_hwfn->p_tx_cids);
 141                 p_hwfn->p_tx_cids = NULL;
 142                 kfree(p_hwfn->p_rx_cids);
 143                 p_hwfn->p_rx_cids = NULL;
 144         }
 145
 146         for_each_hwfn(cdev, i) {
 147                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 148
 149                 qed_cxt_mngr_free(p_hwfn);
 150                 qed_qm_info_free(p_hwfn);
 151                 qed_spq_free(p_hwfn);
 152                 qed_eq_free(p_hwfn, p_hwfn->p_eq);
 153                 qed_consq_free(p_hwfn, p_hwfn->p_consq);
 154                 qed_int_free(p_hwfn);
 155 #ifdef CONFIG_QED_LL2
 156                 qed_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
 157 #endif
 158                 qed_iov_free(p_hwfn);
 159                 qed_dmae_info_free(p_hwfn);
 160                 qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 161         }
 162 }
 163
 164 static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
 165 {
 166         u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0;
 167         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 168         struct init_qm_port_params *p_qm_port;
 169         bool init_rdma_offload_pq = false;
 170         bool init_pure_ack_pq = false;
 171         bool init_ooo_pq = false;
 172         u16 num_pqs, multi_cos_tcs = 1;
 173         u8 pf_wfq = qm_info->pf_wfq;
 174         u32 pf_rl = qm_info->pf_rl;
 175         u16 num_pf_rls = 0;
 176         u16 num_vfs = 0;
 177
 178 #ifdef CONFIG_QED_SRIOV
 179         if (p_hwfn->cdev->p_iov_info)
 180                 num_vfs = p_hwfn->cdev->p_iov_info->total_vfs;
 181 #endif
 182         memset(qm_info, 0, sizeof(*qm_info));
 183
 184         num_pqs = multi_cos_tcs + num_vfs + 1;  /* The '1' is for pure-LB */
 185         num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT);
 186
 187         if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
 188                 num_pqs++;      /* for RoCE queue */
 189                 init_rdma_offload_pq = true;
 190                 /* we subtract num_vfs because each require a rate limiter,
 191                  * and one default rate limiter
 192                  */
 193                 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn)
 194                         num_pf_rls = RESC_NUM(p_hwfn, QED_RL) - num_vfs - 1;
 195
 196                 num_pqs += num_pf_rls;
 197                 qm_info->num_pf_rls = (u8) num_pf_rls;
 198         }
 199
 200         if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 201                 num_pqs += 2;   /* for iSCSI pure-ACK / OOO queue */
 202                 init_pure_ack_pq = true;
 203                 init_ooo_pq = true;
 204         }
 205
 206         /* Sanity checking that setup requires legal number of resources */
 207         if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) {
 208                 DP_ERR(p_hwfn,
 209                        "Need too many Physical queues - 0x%04x when only %04x are available\n",
 210                        num_pqs, RESC_NUM(p_hwfn, QED_PQ));
 211                 return -EINVAL;
 212         }
 213
 214         /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete.
 215          */
 216         qm_info->qm_pq_params = kcalloc(num_pqs,
 217                                         sizeof(struct init_qm_pq_params),
 218                                         b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
 219         if (!qm_info->qm_pq_params)
 220                 goto alloc_err;
 221
 222         qm_info->qm_vport_params = kcalloc(num_vports,
 223                                            sizeof(struct init_qm_vport_params),
 224                                            b_sleepable ? GFP_KERNEL
 225                                                        : GFP_ATOMIC);
 226         if (!qm_info->qm_vport_params)
 227                 goto alloc_err;
 228
 229         qm_info->qm_port_params = kcalloc(MAX_NUM_PORTS,
 230                                           sizeof(struct init_qm_port_params),
 231                                           b_sleepable ? GFP_KERNEL
 232                                                       : GFP_ATOMIC);
 233         if (!qm_info->qm_port_params)
 234                 goto alloc_err;
 235
 236         qm_info->wfq_data = kcalloc(num_vports, sizeof(struct qed_wfq_data),
 237                                     b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
 238         if (!qm_info->wfq_data)
 239                 goto alloc_err;
 240
 241         vport_id = (u8)RESC_START(p_hwfn, QED_VPORT);
 242
 243         /* First init rate limited queues */
 244         for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
 245                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
 246                 qm_info->qm_pq_params[curr_queue].tc_id =
 247                     p_hwfn->hw_info.non_offload_tc;
 248                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 249                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 250         }
 251
 252         /* First init per-TC PQs */
 253         for (i = 0; i < multi_cos_tcs; i++) {
 254                 struct init_qm_pq_params *params =
 255                     &qm_info->qm_pq_params[curr_queue++];
 256
 257                 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE ||
 258                     p_hwfn->hw_info.personality == QED_PCI_ETH) {
 259                         params->vport_id = vport_id;
 260                         params->tc_id = p_hwfn->hw_info.non_offload_tc;
 261                         params->wrr_group = 1;
 262                 } else {
 263                         params->vport_id = vport_id;
 264                         params->tc_id = p_hwfn->hw_info.offload_tc;
 265                         params->wrr_group = 1;
 266                 }
 267         }
 268
 269         /* Then init pure-LB PQ */
 270         qm_info->pure_lb_pq = curr_queue;
 271         qm_info->qm_pq_params[curr_queue].vport_id =
 272             (u8) RESC_START(p_hwfn, QED_VPORT);
 273         qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
 274         qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 275         curr_queue++;
 276
 277         qm_info->offload_pq = 0;
 278         if (init_rdma_offload_pq) {
 279                 qm_info->offload_pq = curr_queue;
 280                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 281                 qm_info->qm_pq_params[curr_queue].tc_id =
 282                     p_hwfn->hw_info.offload_tc;
 283                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 284                 curr_queue++;
 285         }
 286
 287         if (init_pure_ack_pq) {
 288                 qm_info->pure_ack_pq = curr_queue;
 289                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 290                 qm_info->qm_pq_params[curr_queue].tc_id =
 291                     p_hwfn->hw_info.offload_tc;
 292                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 293                 curr_queue++;
 294         }
 295
 296         if (init_ooo_pq) {
 297                 qm_info->ooo_pq = curr_queue;
 298                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 299                 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
 300                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 301                 curr_queue++;
 302         }
 303
 304         /* Then init per-VF PQs */
 305         vf_offset = curr_queue;
 306         for (i = 0; i < num_vfs; i++) {
 307                 /* First vport is used by the PF */
 308                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
 309                 qm_info->qm_pq_params[curr_queue].tc_id =
 310                     p_hwfn->hw_info.non_offload_tc;
 311                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 312                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 313                 curr_queue++;
 314         }
 315
 316         qm_info->vf_queues_offset = vf_offset;
 317         qm_info->num_pqs = num_pqs;
 318         qm_info->num_vports = num_vports;
 319
 320         /* Initialize qm port parameters */
 321         num_ports = p_hwfn->cdev->num_ports_in_engines;
 322         for (i = 0; i < num_ports; i++) {
 323                 p_qm_port = &qm_info->qm_port_params[i];
 324                 p_qm_port->active = 1;
 325                 if (num_ports == 4)
 326                         p_qm_port->active_phys_tcs = 0x7;
 327                 else
 328                         p_qm_port->active_phys_tcs = 0x9f;
 329                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 330                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 331         }
 332
 333         qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
 334
 335         qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ);
 336
 337         qm_info->num_vf_pqs = num_vfs;
 338         qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
 339
 340         for (i = 0; i < qm_info->num_vports; i++)
 341                 qm_info->qm_vport_params[i].vport_wfq = 1;
 342
 343         qm_info->vport_rl_en = 1;
 344         qm_info->vport_wfq_en = 1;
 345         qm_info->pf_rl = pf_rl;
 346         qm_info->pf_wfq = pf_wfq;
 347
 348         return 0;
 349
 350 alloc_err:
 351         qed_qm_info_free(p_hwfn);
 352         return -ENOMEM;
 353 }
 354
 355 /* This function reconfigures the QM pf on the fly.
 356  * For this purpose we:
 357  * 1. reconfigure the QM database
 358  * 2. set new values to runtime arrat
 359  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 360  * 4. activate init tool in QM_PF stage
 361  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 362  */
 363 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 364 {
 365         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 366         bool b_rc;
 367         int rc;
 368
 369         /* qm_info is allocated in qed_init_qm_info() which is already called
 370          * from qed_resc_alloc() or previous call of qed_qm_reconf().
 371          * The allocated size may change each init, so we free it before next
 372          * allocation.
 373          */
 374         qed_qm_info_free(p_hwfn);
 375
 376         /* initialize qed's qm data structure */
 377         rc = qed_init_qm_info(p_hwfn, false);
 378         if (rc)
 379                 return rc;
 380
 381         /* stop PF's qm queues */
 382         spin_lock_bh(&qm_lock);
 383         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 384                                     qm_info->start_pq, qm_info->num_pqs);
 385         spin_unlock_bh(&qm_lock);
 386         if (!b_rc)
 387                 return -EINVAL;
 388
 389         /* clear the QM_PF runtime phase leftovers from previous init */
 390         qed_init_clear_rt_data(p_hwfn);
 391
 392         /* prepare QM portion of runtime array */
 393         qed_qm_init_pf(p_hwfn);
 394
 395         /* activate init tool on runtime array */
 396         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 397                           p_hwfn->hw_info.hw_mode);
 398         if (rc)
 399                 return rc;
 400
 401         /* start PF's qm queues */
 402         spin_lock_bh(&qm_lock);
 403         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 404                                     qm_info->start_pq, qm_info->num_pqs);
 405         spin_unlock_bh(&qm_lock);
 406         if (!b_rc)
 407                 return -EINVAL;
 408
 409         return 0;
 410 }
 411
 412 int qed_resc_alloc(struct qed_dev *cdev)
 413 {
 414 #ifdef CONFIG_QED_LL2
 415         struct qed_ll2_info *p_ll2_info;
 416 #endif
 417         struct qed_consq *p_consq;
 418         struct qed_eq *p_eq;
 419         int i, rc = 0;
 420
 421         if (IS_VF(cdev))
 422                 return rc;
 423
 424         cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
 425         if (!cdev->fw_data)
 426                 return -ENOMEM;
 427
 428         /* Allocate Memory for the Queue->CID mapping */
 429         for_each_hwfn(cdev, i) {
 430                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 431                 int tx_size = sizeof(struct qed_hw_cid_data) *
 432                                      RESC_NUM(p_hwfn, QED_L2_QUEUE);
 433                 int rx_size = sizeof(struct qed_hw_cid_data) *
 434                                      RESC_NUM(p_hwfn, QED_L2_QUEUE);
 435
 436                 p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL);
 437                 if (!p_hwfn->p_tx_cids)
 438                         goto alloc_no_mem;
 439
 440                 p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL);
 441                 if (!p_hwfn->p_rx_cids)
 442                         goto alloc_no_mem;
 443         }
 444
 445         for_each_hwfn(cdev, i) {
 446                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 447                 u32 n_eqes, num_cons;
 448
 449                 /* First allocate the context manager structure */
 450                 rc = qed_cxt_mngr_alloc(p_hwfn);
 451                 if (rc)
 452                         goto alloc_err;
 453
 454                 /* Set the HW cid/tid numbers (in the contest manager)
 455                  * Must be done prior to any further computations.
 456                  */
 457                 rc = qed_cxt_set_pf_params(p_hwfn);
 458                 if (rc)
 459                         goto alloc_err;
 460
 461                 /* Prepare and process QM requirements */
 462                 rc = qed_init_qm_info(p_hwfn, true);
 463                 if (rc)
 464                         goto alloc_err;
 465
 466                 /* Compute the ILT client partition */
 467                 rc = qed_cxt_cfg_ilt_compute(p_hwfn);
 468                 if (rc)
 469                         goto alloc_err;
 470
 471                 /* CID map / ILT shadow table / T2
 472                  * The talbes sizes are determined by the computations above
 473                  */
 474                 rc = qed_cxt_tables_alloc(p_hwfn);
 475                 if (rc)
 476                         goto alloc_err;
 477
 478                 /* SPQ, must follow ILT because initializes SPQ context */
 479                 rc = qed_spq_alloc(p_hwfn);
 480                 if (rc)
 481                         goto alloc_err;
 482
 483                 /* SP status block allocation */
 484                 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
 485                                                          RESERVED_PTT_DPC);
 486
 487                 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 488                 if (rc)
 489                         goto alloc_err;
 490
 491                 rc = qed_iov_alloc(p_hwfn);
 492                 if (rc)
 493                         goto alloc_err;
 494
 495                 /* EQ */
 496                 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
 497                 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
 498                         num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
 499                                                                PROTOCOLID_ROCE,
 500                                                                0) * 2;
 501                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 502                 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 503                         num_cons =
 504                             qed_cxt_get_proto_cid_count(p_hwfn,
 505                                                         PROTOCOLID_ISCSI, 0);
 506                         n_eqes += 2 * num_cons;
 507                 }
 508
 509                 if (n_eqes > 0xFFFF) {
 510                         DP_ERR(p_hwfn,
 511                                "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
 512                                n_eqes, 0xFFFF);
 513                         rc = -EINVAL;
 514                         goto alloc_err;
 515                 }
 516
 517                 p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes);
 518                 if (!p_eq)
 519                         goto alloc_no_mem;
 520                 p_hwfn->p_eq = p_eq;
 521
 522                 p_consq = qed_consq_alloc(p_hwfn);
 523                 if (!p_consq)
 524                         goto alloc_no_mem;
 525                 p_hwfn->p_consq = p_consq;
 526
 527 #ifdef CONFIG_QED_LL2
 528                 if (p_hwfn->using_ll2) {
 529                         p_ll2_info = qed_ll2_alloc(p_hwfn);
 530                         if (!p_ll2_info)
 531                                 goto alloc_no_mem;
 532                         p_hwfn->p_ll2_info = p_ll2_info;
 533                 }
 534 #endif
 535
 536                 /* DMA info initialization */
 537                 rc = qed_dmae_info_alloc(p_hwfn);
 538                 if (rc)
 539                         goto alloc_err;
 540
 541                 /* DCBX initialization */
 542                 rc = qed_dcbx_info_alloc(p_hwfn);
 543                 if (rc)
 544                         goto alloc_err;
 545         }
 546
 547         cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
 548         if (!cdev->reset_stats)
 549                 goto alloc_no_mem;
 550
 551         return 0;
 552
 553 alloc_no_mem:
 554         rc = -ENOMEM;
 555 alloc_err:
 556         qed_resc_free(cdev);
 557         return rc;
 558 }
 559
 560 void qed_resc_setup(struct qed_dev *cdev)
 561 {
 562         int i;
 563
 564         if (IS_VF(cdev))
 565                 return;
 566
 567         for_each_hwfn(cdev, i) {
 568                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 569
 570                 qed_cxt_mngr_setup(p_hwfn);
 571                 qed_spq_setup(p_hwfn);
 572                 qed_eq_setup(p_hwfn, p_hwfn->p_eq);
 573                 qed_consq_setup(p_hwfn, p_hwfn->p_consq);
 574
 575                 /* Read shadow of current MFW mailbox */
 576                 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
 577                 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
 578                        p_hwfn->mcp_info->mfw_mb_cur,
 579                        p_hwfn->mcp_info->mfw_mb_length);
 580
 581                 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
 582
 583                 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
 584 #ifdef CONFIG_QED_LL2
 585                 if (p_hwfn->using_ll2)
 586                         qed_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
 587 #endif
 588         }
 589 }
 590
 591 #define FINAL_CLEANUP_POLL_CNT          (100)
 592 #define FINAL_CLEANUP_POLL_TIME         (10)
 593 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
 594                       struct qed_ptt *p_ptt, u16 id, bool is_vf)
 595 {
 596         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
 597         int rc = -EBUSY;
 598
 599         addr = GTT_BAR0_MAP_REG_USDM_RAM +
 600                 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
 601
 602         if (is_vf)
 603                 id += 0x10;
 604
 605         command |= X_FINAL_CLEANUP_AGG_INT <<
 606                 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
 607         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
 608         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
 609         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
 610
 611         /* Make sure notification is not set before initiating final cleanup */
 612         if (REG_RD(p_hwfn, addr)) {
 613                 DP_NOTICE(p_hwfn,
 614                           "Unexpected; Found final cleanup notification before initiating final cleanup\n");
 615                 REG_WR(p_hwfn, addr, 0);
 616         }
 617
 618         DP_VERBOSE(p_hwfn, QED_MSG_IOV,
 619                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
 620                    id, command);
 621
 622         qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
 623
 624         /* Poll until completion */
 625         while (!REG_RD(p_hwfn, addr) && count--)
 626                 msleep(FINAL_CLEANUP_POLL_TIME);
 627
 628         if (REG_RD(p_hwfn, addr))
 629                 rc = 0;
 630         else
 631                 DP_NOTICE(p_hwfn,
 632                           "Failed to receive FW final cleanup notification\n");
 633
 634         /* Cleanup afterwards */
 635         REG_WR(p_hwfn, addr, 0);
 636
 637         return rc;
 638 }
 639
 640 static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
 641 {
 642         int hw_mode = 0;
 643
 644         hw_mode = (1 << MODE_BB_B0);
 645
 646         switch (p_hwfn->cdev->num_ports_in_engines) {
 647         case 1:
 648                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
 649                 break;
 650         case 2:
 651                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
 652                 break;
 653         case 4:
 654                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
 655                 break;
 656         default:
 657                 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
 658                           p_hwfn->cdev->num_ports_in_engines);
 659                 return;
 660         }
 661
 662         switch (p_hwfn->cdev->mf_mode) {
 663         case QED_MF_DEFAULT:
 664         case QED_MF_NPAR:
 665                 hw_mode |= 1 << MODE_MF_SI;
 666                 break;
 667         case QED_MF_OVLAN:
 668                 hw_mode |= 1 << MODE_MF_SD;
 669                 break;
 670         default:
 671                 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
 672                 hw_mode |= 1 << MODE_MF_SI;
 673         }
 674
 675         hw_mode |= 1 << MODE_ASIC;
 676
 677         if (p_hwfn->cdev->num_hwfns > 1)
 678                 hw_mode |= 1 << MODE_100G;
 679
 680         p_hwfn->hw_info.hw_mode = hw_mode;
 681
 682         DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
 683                    "Configuring function for hw_mode: 0x%08x\n",
 684                    p_hwfn->hw_info.hw_mode);
 685 }
 686
 687 /* Init run time data for all PFs on an engine. */
 688 static void qed_init_cau_rt_data(struct qed_dev *cdev)
 689 {
 690         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
 691         int i, sb_id;
 692
 693         for_each_hwfn(cdev, i) {
 694                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 695                 struct qed_igu_info *p_igu_info;
 696                 struct qed_igu_block *p_block;
 697                 struct cau_sb_entry sb_entry;
 698
 699                 p_igu_info = p_hwfn->hw_info.p_igu_info;
 700
 701                 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev);
 702                      sb_id++) {
 703                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
 704                         if (!p_block->is_pf)
 705                                 continue;
 706
 707                         qed_init_cau_sb_entry(p_hwfn, &sb_entry,
 708                                               p_block->function_id, 0, 0);
 709                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
 710                 }
 711         }
 712 }
 713
 714 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
 715                               struct qed_ptt *p_ptt, int hw_mode)
 716 {
 717         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 718         struct qed_qm_common_rt_init_params params;
 719         struct qed_dev *cdev = p_hwfn->cdev;
 720         u16 num_pfs, pf_id;
 721         u32 concrete_fid;
 722         int rc = 0;
 723         u8 vf_id;
 724
 725         qed_init_cau_rt_data(cdev);
 726
 727         /* Program GTT windows */
 728         qed_gtt_init(p_hwfn);
 729
 730         if (p_hwfn->mcp_info) {
 731                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
 732                         qm_info->pf_rl_en = 1;
 733                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
 734                         qm_info->pf_wfq_en = 1;
 735         }
 736
 737         memset(&params, 0, sizeof(params));
 738         params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines;
 739         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
 740         params.pf_rl_en = qm_info->pf_rl_en;
 741         params.pf_wfq_en = qm_info->pf_wfq_en;
 742         params.vport_rl_en = qm_info->vport_rl_en;
 743         params.vport_wfq_en = qm_info->vport_wfq_en;
 744         params.port_params = qm_info->qm_port_params;
 745
 746         qed_qm_common_rt_init(p_hwfn, &params);
 747
 748         qed_cxt_hw_init_common(p_hwfn);
 749
 750         /* Close gate from NIG to BRB/Storm; By default they are open, but
 751          * we close them to prevent NIG from passing data to reset blocks.
 752          * Should have been done in the ENGINE phase, but init-tool lacks
 753          * proper port-pretend capabilities.
 754          */
 755         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
 756         qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
 757         qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
 758         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
 759         qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
 760         qed_port_unpretend(p_hwfn, p_ptt);
 761
 762         rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
 763         if (rc)
 764                 return rc;
 765
 766         qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
 767         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
 768
 769         if (QED_IS_BB(p_hwfn->cdev)) {
 770                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
 771                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
 772                         qed_fid_pretend(p_hwfn, p_ptt, pf_id);
 773                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
 774                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
 775                 }
 776                 /* pretend to original PF */
 777                 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
 778         }
 779
 780         for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) {
 781                 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
 782                 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
 783                 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
 784                 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
 785                 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
 786                 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
 787         }
 788         /* pretend to original PF */
 789         qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
 790
 791         return rc;
 792 }
 793
 794 static int
 795 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
 796                      struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
 797 {
 798         u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
 799         u32 dpi_bit_shift, dpi_count;
 800         u32 min_dpis;
 801
 802         /* Calculate DPI size */
 803         dpi_page_size_1 = QED_WID_SIZE * n_cpus;
 804         dpi_page_size_2 = max_t(u32, QED_WID_SIZE, PAGE_SIZE);
 805         dpi_page_size = max_t(u32, dpi_page_size_1, dpi_page_size_2);
 806         dpi_page_size = roundup_pow_of_two(dpi_page_size);
 807         dpi_bit_shift = ilog2(dpi_page_size / 4096);
 808
 809         dpi_count = pwm_region_size / dpi_page_size;
 810
 811         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
 812         min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
 813
 814         p_hwfn->dpi_size = dpi_page_size;
 815         p_hwfn->dpi_count = dpi_count;
 816
 817         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
 818
 819         if (dpi_count < min_dpis)
 820                 return -EINVAL;
 821
 822         return 0;
 823 }
 824
 825 enum QED_ROCE_EDPM_MODE {
 826         QED_ROCE_EDPM_MODE_ENABLE = 0,
 827         QED_ROCE_EDPM_MODE_FORCE_ON = 1,
 828         QED_ROCE_EDPM_MODE_DISABLE = 2,
 829 };
 830
 831 static int
 832 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 833 {
 834         u32 pwm_regsize, norm_regsize;
 835         u32 non_pwm_conn, min_addr_reg1;
 836         u32 db_bar_size, n_cpus;
 837         u32 roce_edpm_mode;
 838         u32 pf_dems_shift;
 839         int rc = 0;
 840         u8 cond;
 841
 842         db_bar_size = qed_hw_bar_size(p_hwfn, BAR_ID_1);
 843         if (p_hwfn->cdev->num_hwfns > 1)
 844                 db_bar_size /= 2;
 845
 846         /* Calculate doorbell regions */
 847         non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
 848                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
 849                                                    NULL) +
 850                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
 851                                                    NULL);
 852         norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, 4096);
 853         min_addr_reg1 = norm_regsize / 4096;
 854         pwm_regsize = db_bar_size - norm_regsize;
 855
 856         /* Check that the normal and PWM sizes are valid */
 857         if (db_bar_size < norm_regsize) {
 858                 DP_ERR(p_hwfn->cdev,
 859                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
 860                        db_bar_size, norm_regsize);
 861                 return -EINVAL;
 862         }
 863
 864         if (pwm_regsize < QED_MIN_PWM_REGION) {
 865                 DP_ERR(p_hwfn->cdev,
 866                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
 867                        pwm_regsize,
 868                        QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
 869                 return -EINVAL;
 870         }
 871
 872         /* Calculate number of DPIs */
 873         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
 874         if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
 875             ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
 876                 /* Either EDPM is mandatory, or we are attempting to allocate a
 877                  * WID per CPU.
 878                  */
 879                 n_cpus = num_active_cpus();
 880                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
 881         }
 882
 883         cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
 884                (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
 885         if (cond || p_hwfn->dcbx_no_edpm) {
 886                 /* Either EDPM is disabled from user configuration, or it is
 887                  * disabled via DCBx, or it is not mandatory and we failed to
 888                  * allocated a WID per CPU.
 889                  */
 890                 n_cpus = 1;
 891                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
 892
 893                 if (cond)
 894                         qed_rdma_dpm_bar(p_hwfn, p_ptt);
 895         }
 896
 897         DP_INFO(p_hwfn,
 898                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
 899                 norm_regsize,
 900                 pwm_regsize,
 901                 p_hwfn->dpi_size,
 902                 p_hwfn->dpi_count,
 903                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
 904                 "disabled" : "enabled");
 905
 906         if (rc) {
 907                 DP_ERR(p_hwfn,
 908                        "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
 909                        p_hwfn->dpi_count,
 910                        p_hwfn->pf_params.rdma_pf_params.min_dpis);
 911                 return -EINVAL;
 912         }
 913
 914         p_hwfn->dpi_start_offset = norm_regsize;
 915
 916         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
 917         pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
 918         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
 919         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
 920
 921         return 0;
 922 }
 923
 924 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
 925                             struct qed_ptt *p_ptt, int hw_mode)
 926 {
 927         return qed_init_run(p_hwfn, p_ptt, PHASE_PORT,
 928                             p_hwfn->port_id, hw_mode);
 929 }
 930
 931 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
 932                           struct qed_ptt *p_ptt,
 933                           struct qed_tunn_start_params *p_tunn,
 934                           int hw_mode,
 935                           bool b_hw_start,
 936                           enum qed_int_mode int_mode,
 937                           bool allow_npar_tx_switch)
 938 {
 939         u8 rel_pf_id = p_hwfn->rel_pf_id;
 940         int rc = 0;
 941
 942         if (p_hwfn->mcp_info) {
 943                 struct qed_mcp_function_info *p_info;
 944
 945                 p_info = &p_hwfn->mcp_info->func_info;
 946                 if (p_info->bandwidth_min)
 947                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
 948
 949                 /* Update rate limit once we'll actually have a link */
 950                 p_hwfn->qm_info.pf_rl = 100000;
 951         }
 952
 953         qed_cxt_hw_init_pf(p_hwfn);
 954
 955         qed_int_igu_init_rt(p_hwfn);
 956
 957         /* Set VLAN in NIG if needed */
 958         if (hw_mode & BIT(MODE_MF_SD)) {
 959                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
 960                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
 961                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
 962                              p_hwfn->hw_info.ovlan);
 963         }
 964
 965         /* Enable classification by MAC if needed */
 966         if (hw_mode & BIT(MODE_MF_SI)) {
 967                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
 968                            "Configuring TAGMAC_CLS_TYPE\n");
 969                 STORE_RT_REG(p_hwfn,
 970                              NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
 971         }
 972
 973         /* Protocl Configuration  */
 974         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
 975                      (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
 976         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0);
 977         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
 978
 979         /* Cleanup chip from previous driver if such remains exist */
 980         rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
 981         if (rc)
 982                 return rc;
 983
 984         /* PF Init sequence */
 985         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
 986         if (rc)
 987                 return rc;
 988
 989         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
 990         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
 991         if (rc)
 992                 return rc;
 993
 994         /* Pure runtime initializations - directly to the HW  */
 995         qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
 996
 997         rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
 998         if (rc)
 999                 return rc;
1000
1001         if (b_hw_start) {
1002                 /* enable interrupts */
1003                 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1004
1005                 /* send function start command */
1006                 rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode,
1007                                      allow_npar_tx_switch);
1008                 if (rc)
1009                         DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1010         }
1011         return rc;
1012 }
1013
1014 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1015                                struct qed_ptt *p_ptt,
1016                                u8 enable)
1017 {
1018         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1019
1020         /* Change PF in PXP */
1021         qed_wr(p_hwfn, p_ptt,
1022                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1023
1024         /* wait until value is set - try for 1 second every 50us */
1025         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1026                 val = qed_rd(p_hwfn, p_ptt,
1027                              PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1028                 if (val == set_val)
1029                         break;
1030
1031                 usleep_range(50, 60);
1032         }
1033
1034         if (val != set_val) {
1035                 DP_NOTICE(p_hwfn,
1036                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1037                 return -EAGAIN;
1038         }
1039
1040         return 0;
1041 }
1042
1043 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1044                                 struct qed_ptt *p_main_ptt)
1045 {
1046         /* Read shadow of current MFW mailbox */
1047         qed_mcp_read_mb(p_hwfn, p_main_ptt);
1048         memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1049                p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
1050 }
1051
1052 int qed_hw_init(struct qed_dev *cdev,
1053                 struct qed_tunn_start_params *p_tunn,
1054                 bool b_hw_start,
1055                 enum qed_int_mode int_mode,
1056                 bool allow_npar_tx_switch,
1057                 const u8 *bin_fw_data)
1058 {
1059         u32 load_code, param;
1060         int rc, mfw_rc, i;
1061
1062         if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
1063                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1064                 return -EINVAL;
1065         }
1066
1067         if (IS_PF(cdev)) {
1068                 rc = qed_init_fw_data(cdev, bin_fw_data);
1069                 if (rc)
1070                         return rc;
1071         }
1072
1073         for_each_hwfn(cdev, i) {
1074                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1075
1076                 if (IS_VF(cdev)) {
1077                         p_hwfn->b_int_enabled = 1;
1078                         continue;
1079                 }
1080
1081                 /* Enable DMAE in PXP */
1082                 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1083
1084                 qed_calc_hw_mode(p_hwfn);
1085
1086                 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1087                 if (rc) {
1088                         DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n");
1089                         return rc;
1090                 }
1091
1092                 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1093
1094                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1095                            "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1096                            rc, load_code);
1097
1098                 p_hwfn->first_on_engine = (load_code ==
1099                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1100
1101                 switch (load_code) {
1102                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1103                         rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1104                                                 p_hwfn->hw_info.hw_mode);
1105                         if (rc)
1106                                 break;
1107                 /* Fall into */
1108                 case FW_MSG_CODE_DRV_LOAD_PORT:
1109                         rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1110                                               p_hwfn->hw_info.hw_mode);
1111                         if (rc)
1112                                 break;
1113
1114                 /* Fall into */
1115                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1116                         rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1117                                             p_tunn, p_hwfn->hw_info.hw_mode,
1118                                             b_hw_start, int_mode,
1119                                             allow_npar_tx_switch);
1120                         break;
1121                 default:
1122                         rc = -EINVAL;
1123                         break;
1124                 }
1125
1126                 if (rc)
1127                         DP_NOTICE(p_hwfn,
1128                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1129                                    load_code, rc);
1130
1131                 /* ACK mfw regardless of success or failure of initialization */
1132                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1133                                      DRV_MSG_CODE_LOAD_DONE,
1134                                      0, &load_code, &param);
1135                 if (rc)
1136                         return rc;
1137                 if (mfw_rc) {
1138                         DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1139                         return mfw_rc;
1140                 }
1141
1142                 /* send DCBX attention request command */
1143                 DP_VERBOSE(p_hwfn,
1144                            QED_MSG_DCB,
1145                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1146                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1147                                      DRV_MSG_CODE_SET_DCBX,
1148                                      1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1149                                      &load_code, &param);
1150                 if (mfw_rc) {
1151                         DP_NOTICE(p_hwfn,
1152                                   "Failed to send DCBX attention request\n");
1153                         return mfw_rc;
1154                 }
1155
1156                 p_hwfn->hw_init_done = true;
1157         }
1158
1159         return 0;
1160 }
1161
1162 #define QED_HW_STOP_RETRY_LIMIT (10)
1163 static void qed_hw_timers_stop(struct qed_dev *cdev,
1164                                struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1165 {
1166         int i;
1167
1168         /* close timers */
1169         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1170         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1171
1172         for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1173                 if ((!qed_rd(p_hwfn, p_ptt,
1174                              TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1175                     (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1176                         break;
1177
1178                 /* Dependent on number of connection/tasks, possibly
1179                  * 1ms sleep is required between polls
1180                  */
1181                 usleep_range(1000, 2000);
1182         }
1183
1184         if (i < QED_HW_STOP_RETRY_LIMIT)
1185                 return;
1186
1187         DP_NOTICE(p_hwfn,
1188                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1189                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1190                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1191 }
1192
1193 void qed_hw_timers_stop_all(struct qed_dev *cdev)
1194 {
1195         int j;
1196
1197         for_each_hwfn(cdev, j) {
1198                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1199                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1200
1201                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1202         }
1203 }
1204
1205 int qed_hw_stop(struct qed_dev *cdev)
1206 {
1207         int rc = 0, t_rc;
1208         int j;
1209
1210         for_each_hwfn(cdev, j) {
1211                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1212                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1213
1214                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1215
1216                 if (IS_VF(cdev)) {
1217                         qed_vf_pf_int_cleanup(p_hwfn);
1218                         continue;
1219                 }
1220
1221                 /* mark the hw as uninitialized... */
1222                 p_hwfn->hw_init_done = false;
1223
1224                 rc = qed_sp_pf_stop(p_hwfn);
1225                 if (rc)
1226                         DP_NOTICE(p_hwfn,
1227                                   "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1228
1229                 qed_wr(p_hwfn, p_ptt,
1230                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1231
1232                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1233                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1234                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1235                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1236                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1237
1238                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1239
1240                 /* Disable Attention Generation */
1241                 qed_int_igu_disable_int(p_hwfn, p_ptt);
1242
1243                 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1244                 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1245
1246                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1247
1248                 /* Need to wait 1ms to guarantee SBs are cleared */
1249                 usleep_range(1000, 2000);
1250         }
1251
1252         if (IS_PF(cdev)) {
1253                 /* Disable DMAE in PXP - in CMT, this should only be done for
1254                  * first hw-function, and only after all transactions have
1255                  * stopped for all active hw-functions.
1256                  */
1257                 t_rc = qed_change_pci_hwfn(&cdev->hwfns[0],
1258                                            cdev->hwfns[0].p_main_ptt, false);
1259                 if (t_rc != 0)
1260                         rc = t_rc;
1261         }
1262
1263         return rc;
1264 }
1265
1266 void qed_hw_stop_fastpath(struct qed_dev *cdev)
1267 {
1268         int j;
1269
1270         for_each_hwfn(cdev, j) {
1271                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1272                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1273
1274                 if (IS_VF(cdev)) {
1275                         qed_vf_pf_int_cleanup(p_hwfn);
1276                         continue;
1277                 }
1278
1279                 DP_VERBOSE(p_hwfn,
1280                            NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
1281
1282                 qed_wr(p_hwfn, p_ptt,
1283                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1284
1285                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1286                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1287                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1288                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1289                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1290
1291                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1292
1293                 /* Need to wait 1ms to guarantee SBs are cleared */
1294                 usleep_range(1000, 2000);
1295         }
1296 }
1297
1298 void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
1299 {
1300         if (IS_VF(p_hwfn->cdev))
1301                 return;
1302
1303         /* Re-open incoming traffic */
1304         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1305                NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1306 }
1307
1308 static int qed_reg_assert(struct qed_hwfn *p_hwfn,
1309                           struct qed_ptt *p_ptt, u32 reg, bool expected)
1310 {
1311         u32 assert_val = qed_rd(p_hwfn, p_ptt, reg);
1312
1313         if (assert_val != expected) {
1314                 DP_NOTICE(p_hwfn, "Value at address 0x%08x != 0x%08x\n",
1315                           reg, expected);
1316                 return -EINVAL;
1317         }
1318
1319         return 0;
1320 }
1321
1322 int qed_hw_reset(struct qed_dev *cdev)
1323 {
1324         int rc = 0;
1325         u32 unload_resp, unload_param;
1326         int i;
1327
1328         for_each_hwfn(cdev, i) {
1329                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1330
1331                 if (IS_VF(cdev)) {
1332                         rc = qed_vf_pf_reset(p_hwfn);
1333                         if (rc)
1334                                 return rc;
1335                         continue;
1336                 }
1337
1338                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n");
1339
1340                 /* Check for incorrect states */
1341                 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1342                                QM_REG_USG_CNT_PF_TX, 0);
1343                 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1344                                QM_REG_USG_CNT_PF_OTHER, 0);
1345
1346                 /* Disable PF in HW blocks */
1347                 qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1348                 qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1349                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1350                        TCFC_REG_STRONG_ENABLE_PF, 0);
1351                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1352                        CCFC_REG_STRONG_ENABLE_PF, 0);
1353
1354                 /* Send unload command to MCP */
1355                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1356                                  DRV_MSG_CODE_UNLOAD_REQ,
1357                                  DRV_MB_PARAM_UNLOAD_WOL_MCP,
1358                                  &unload_resp, &unload_param);
1359                 if (rc) {
1360                         DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n");
1361                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
1362                 }
1363
1364                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1365                                  DRV_MSG_CODE_UNLOAD_DONE,
1366                                  0, &unload_resp, &unload_param);
1367                 if (rc) {
1368                         DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n");
1369                         return rc;
1370                 }
1371         }
1372
1373         return rc;
1374 }
1375
1376 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1377 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
1378 {
1379         qed_ptt_pool_free(p_hwfn);
1380         kfree(p_hwfn->hw_info.p_igu_info);
1381 }
1382
1383 /* Setup bar access */
1384 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
1385 {
1386         /* clear indirect access */
1387         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0);
1388         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
1389         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0);
1390         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0);
1391
1392         /* Clean Previous errors if such exist */
1393         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1394                PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
1395
1396         /* enable internal target-read */
1397         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1398                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1399 }
1400
1401 static void get_function_id(struct qed_hwfn *p_hwfn)
1402 {
1403         /* ME Register */
1404         p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
1405                                                   PXP_PF_ME_OPAQUE_ADDR);
1406
1407         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
1408
1409         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
1410         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1411                                       PXP_CONCRETE_FID_PFID);
1412         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1413                                     PXP_CONCRETE_FID_PORT);
1414
1415         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1416                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
1417                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
1418 }
1419
1420 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
1421 {
1422         u32 *feat_num = p_hwfn->hw_info.feat_num;
1423         int num_features = 1;
1424
1425 #if IS_ENABLED(CONFIG_INFINIBAND_QEDR)
1426         /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide the
1427          * status blocks equally between L2 / RoCE but with consideration as
1428          * to how many l2 queues / cnqs we have
1429          */
1430         if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
1431                 num_features++;
1432
1433                 feat_num[QED_RDMA_CNQ] =
1434                         min_t(u32, RESC_NUM(p_hwfn, QED_SB) / num_features,
1435                               RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
1436         }
1437 #endif
1438         feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) /
1439                                                 num_features,
1440                                         RESC_NUM(p_hwfn, QED_L2_QUEUE));
1441         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1442                    "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
1443                    feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB),
1444                    num_features);
1445 }
1446
1447 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
1448 {
1449         u8 enabled_func_idx = p_hwfn->enabled_func_idx;
1450         u32 *resc_start = p_hwfn->hw_info.resc_start;
1451         u8 num_funcs = p_hwfn->num_funcs_on_engine;
1452         u32 *resc_num = p_hwfn->hw_info.resc_num;
1453         struct qed_sb_cnt_info sb_cnt_info;
1454         int i, max_vf_vlan_filters;
1455
1456         memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
1457
1458 #ifdef CONFIG_QED_SRIOV
1459         max_vf_vlan_filters = QED_ETH_MAX_VF_NUM_VLAN_FILTERS;
1460 #else
1461         max_vf_vlan_filters = 0;
1462 #endif
1463
1464         qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1465
1466         resc_num[QED_SB] = min_t(u32,
1467                                  (MAX_SB_PER_PATH_BB / num_funcs),
1468                                  sb_cnt_info.sb_cnt);
1469         resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs;
1470         resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs;
1471         resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs;
1472         resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs;
1473         resc_num[QED_RL] = min_t(u32, 64, resc_num[QED_VPORT]);
1474         resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
1475         resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) /
1476                              num_funcs;
1477         resc_num[QED_ILT] = PXP_NUM_ILT_RECORDS_BB / num_funcs;
1478         resc_num[QED_LL2_QUEUE] = MAX_NUM_LL2_RX_QUEUES / num_funcs;
1479         resc_num[QED_RDMA_CNQ_RAM] = NUM_OF_CMDQS_CQS / num_funcs;
1480         resc_num[QED_RDMA_STATS_QUEUE] = RDMA_NUM_STATISTIC_COUNTERS_BB /
1481                                          num_funcs;
1482
1483         for (i = 0; i < QED_MAX_RESC; i++)
1484                 resc_start[i] = resc_num[i] * enabled_func_idx;
1485
1486         /* Sanity for ILT */
1487         if (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB) {
1488                 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
1489                           RESC_START(p_hwfn, QED_ILT),
1490                           RESC_END(p_hwfn, QED_ILT) - 1);
1491                 return -EINVAL;
1492         }
1493
1494         qed_hw_set_feat(p_hwfn);
1495
1496         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1497                    "The numbers for each resource are:\n"
1498                    "SB = %d start = %d\n"
1499                    "L2_QUEUE = %d start = %d\n"
1500                    "VPORT = %d start = %d\n"
1501                    "PQ = %d start = %d\n"
1502                    "RL = %d start = %d\n"
1503                    "MAC = %d start = %d\n"
1504                    "VLAN = %d start = %d\n"
1505                    "ILT = %d start = %d\n"
1506                    "LL2_QUEUE = %d start = %d\n",
1507                    p_hwfn->hw_info.resc_num[QED_SB],
1508                    p_hwfn->hw_info.resc_start[QED_SB],
1509                    p_hwfn->hw_info.resc_num[QED_L2_QUEUE],
1510                    p_hwfn->hw_info.resc_start[QED_L2_QUEUE],
1511                    p_hwfn->hw_info.resc_num[QED_VPORT],
1512                    p_hwfn->hw_info.resc_start[QED_VPORT],
1513                    p_hwfn->hw_info.resc_num[QED_PQ],
1514                    p_hwfn->hw_info.resc_start[QED_PQ],
1515                    p_hwfn->hw_info.resc_num[QED_RL],
1516                    p_hwfn->hw_info.resc_start[QED_RL],
1517                    p_hwfn->hw_info.resc_num[QED_MAC],
1518                    p_hwfn->hw_info.resc_start[QED_MAC],
1519                    p_hwfn->hw_info.resc_num[QED_VLAN],
1520                    p_hwfn->hw_info.resc_start[QED_VLAN],
1521                    p_hwfn->hw_info.resc_num[QED_ILT],
1522                    p_hwfn->hw_info.resc_start[QED_ILT],
1523                    RESC_NUM(p_hwfn, QED_LL2_QUEUE),
1524                    RESC_START(p_hwfn, QED_LL2_QUEUE));
1525
1526         return 0;
1527 }
1528
1529 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1530 {
1531         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
1532         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
1533         struct qed_mcp_link_params *link;
1534
1535         /* Read global nvm_cfg address */
1536         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1537
1538         /* Verify MCP has initialized it */
1539         if (!nvm_cfg_addr) {
1540                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
1541                 return -EINVAL;
1542         }
1543
1544         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
1545         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1546
1547         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1548                offsetof(struct nvm_cfg1, glob) +
1549                offsetof(struct nvm_cfg1_glob, core_cfg);
1550
1551         core_cfg = qed_rd(p_hwfn, p_ptt, addr);
1552
1553         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
1554                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
1555         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
1556                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
1557                 break;
1558         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
1559                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
1560                 break;
1561         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
1562                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
1563                 break;
1564         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
1565                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
1566                 break;
1567         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
1568                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
1569                 break;
1570         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
1571                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
1572                 break;
1573         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
1574                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
1575                 break;
1576         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
1577                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
1578                 break;
1579         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
1580                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
1581                 break;
1582         default:
1583                 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
1584                 break;
1585         }
1586
1587         /* Read default link configuration */
1588         link = &p_hwfn->mcp_info->link_input;
1589         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1590                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
1591         link_temp = qed_rd(p_hwfn, p_ptt,
1592                            port_cfg_addr +
1593                            offsetof(struct nvm_cfg1_port, speed_cap_mask));
1594         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
1595         link->speed.advertised_speeds = link_temp;
1596
1597         link_temp = link->speed.advertised_speeds;
1598         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
1599
1600         link_temp = qed_rd(p_hwfn, p_ptt,
1601                            port_cfg_addr +
1602                            offsetof(struct nvm_cfg1_port, link_settings));
1603         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
1604                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
1605         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
1606                 link->speed.autoneg = true;
1607                 break;
1608         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
1609                 link->speed.forced_speed = 1000;
1610                 break;
1611         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
1612                 link->speed.forced_speed = 10000;
1613                 break;
1614         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
1615                 link->speed.forced_speed = 25000;
1616                 break;
1617         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
1618                 link->speed.forced_speed = 40000;
1619                 break;
1620         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
1621                 link->speed.forced_speed = 50000;
1622                 break;
1623         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
1624                 link->speed.forced_speed = 100000;
1625                 break;
1626         default:
1627                 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
1628         }
1629
1630         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
1631         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
1632         link->pause.autoneg = !!(link_temp &
1633                                  NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
1634         link->pause.forced_rx = !!(link_temp &
1635                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
1636         link->pause.forced_tx = !!(link_temp &
1637                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
1638         link->loopback_mode = 0;
1639
1640         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1641                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
1642                    link->speed.forced_speed, link->speed.advertised_speeds,
1643                    link->speed.autoneg, link->pause.autoneg);
1644
1645         /* Read Multi-function information from shmem */
1646         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1647                offsetof(struct nvm_cfg1, glob) +
1648                offsetof(struct nvm_cfg1_glob, generic_cont0);
1649
1650         generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
1651
1652         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
1653                   NVM_CFG1_GLOB_MF_MODE_OFFSET;
1654
1655         switch (mf_mode) {
1656         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
1657                 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
1658                 break;
1659         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
1660                 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
1661                 break;
1662         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
1663                 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
1664                 break;
1665         }
1666         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
1667                 p_hwfn->cdev->mf_mode);
1668
1669         /* Read Multi-function information from shmem */
1670         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1671                 offsetof(struct nvm_cfg1, glob) +
1672                 offsetof(struct nvm_cfg1_glob, device_capabilities);
1673
1674         device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
1675         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
1676                 __set_bit(QED_DEV_CAP_ETH,
1677                           &p_hwfn->hw_info.device_capabilities);
1678         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
1679                 __set_bit(QED_DEV_CAP_ISCSI,
1680                           &p_hwfn->hw_info.device_capabilities);
1681         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
1682                 __set_bit(QED_DEV_CAP_ROCE,
1683                           &p_hwfn->hw_info.device_capabilities);
1684
1685         return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
1686 }
1687
1688 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1689 {
1690         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
1691         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
1692
1693         num_funcs = MAX_NUM_PFS_BB;
1694
1695         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
1696          * in the other bits are selected.
1697          * Bits 1-15 are for functions 1-15, respectively, and their value is
1698          * '0' only for enabled functions (function 0 always exists and
1699          * enabled).
1700          * In case of CMT, only the "even" functions are enabled, and thus the
1701          * number of functions for both hwfns is learnt from the same bits.
1702          */
1703         reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
1704
1705         if (reg_function_hide & 0x1) {
1706                 if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) {
1707                         num_funcs = 0;
1708                         eng_mask = 0xaaaa;
1709                 } else {
1710                         num_funcs = 1;
1711                         eng_mask = 0x5554;
1712                 }
1713
1714                 /* Get the number of the enabled functions on the engine */
1715                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
1716                 while (tmp) {
1717                         if (tmp & 0x1)
1718                                 num_funcs++;
1719                         tmp >>= 0x1;
1720                 }
1721
1722                 /* Get the PF index within the enabled functions */
1723                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
1724                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
1725                 while (tmp) {
1726                         if (tmp & 0x1)
1727                                 enabled_func_idx--;
1728                         tmp >>= 0x1;
1729                 }
1730         }
1731
1732         p_hwfn->num_funcs_on_engine = num_funcs;
1733         p_hwfn->enabled_func_idx = enabled_func_idx;
1734
1735         DP_VERBOSE(p_hwfn,
1736                    NETIF_MSG_PROBE,
1737                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
1738                    p_hwfn->rel_pf_id,
1739                    p_hwfn->abs_pf_id,
1740                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
1741 }
1742
1743 static int
1744 qed_get_hw_info(struct qed_hwfn *p_hwfn,
1745                 struct qed_ptt *p_ptt,
1746                 enum qed_pci_personality personality)
1747 {
1748         u32 port_mode;
1749         int rc;
1750
1751         /* Since all information is common, only first hwfns should do this */
1752         if (IS_LEAD_HWFN(p_hwfn)) {
1753                 rc = qed_iov_hw_info(p_hwfn);
1754                 if (rc)
1755                         return rc;
1756         }
1757
1758         /* Read the port mode */
1759         port_mode = qed_rd(p_hwfn, p_ptt,
1760                            CNIG_REG_NW_PORT_MODE_BB_B0);
1761
1762         if (port_mode < 3) {
1763                 p_hwfn->cdev->num_ports_in_engines = 1;
1764         } else if (port_mode <= 5) {
1765                 p_hwfn->cdev->num_ports_in_engines = 2;
1766         } else {
1767                 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
1768                           p_hwfn->cdev->num_ports_in_engines);
1769
1770                 /* Default num_ports_in_engines to something */
1771                 p_hwfn->cdev->num_ports_in_engines = 1;
1772         }
1773
1774         qed_hw_get_nvm_info(p_hwfn, p_ptt);
1775
1776         rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
1777         if (rc)
1778                 return rc;
1779
1780         if (qed_mcp_is_init(p_hwfn))
1781                 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
1782                                 p_hwfn->mcp_info->func_info.mac);
1783         else
1784                 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
1785
1786         if (qed_mcp_is_init(p_hwfn)) {
1787                 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
1788                         p_hwfn->hw_info.ovlan =
1789                                 p_hwfn->mcp_info->func_info.ovlan;
1790
1791                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
1792         }
1793
1794         if (qed_mcp_is_init(p_hwfn)) {
1795                 enum qed_pci_personality protocol;
1796
1797                 protocol = p_hwfn->mcp_info->func_info.protocol;
1798                 p_hwfn->hw_info.personality = protocol;
1799         }
1800
1801         qed_get_num_funcs(p_hwfn, p_ptt);
1802
1803         return qed_hw_get_resc(p_hwfn);
1804 }
1805
1806 static int qed_get_dev_info(struct qed_dev *cdev)
1807 {
1808         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1809         u32 tmp;
1810
1811         /* Read Vendor Id / Device Id */
1812         pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
1813         pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
1814
1815         cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1816                                      MISCS_REG_CHIP_NUM);
1817         cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1818                                      MISCS_REG_CHIP_REV);
1819         MASK_FIELD(CHIP_REV, cdev->chip_rev);
1820
1821         cdev->type = QED_DEV_TYPE_BB;
1822         /* Learn number of HW-functions */
1823         tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1824                      MISCS_REG_CMT_ENABLED_FOR_PAIR);
1825
1826         if (tmp & (1 << p_hwfn->rel_pf_id)) {
1827                 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
1828                 cdev->num_hwfns = 2;
1829         } else {
1830                 cdev->num_hwfns = 1;
1831         }
1832
1833         cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1834                                     MISCS_REG_CHIP_TEST_REG) >> 4;
1835         MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
1836         cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1837                                        MISCS_REG_CHIP_METAL);
1838         MASK_FIELD(CHIP_METAL, cdev->chip_metal);
1839
1840         DP_INFO(cdev->hwfns,
1841                 "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
1842                 cdev->chip_num, cdev->chip_rev,
1843                 cdev->chip_bond_id, cdev->chip_metal);
1844
1845         if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) {
1846                 DP_NOTICE(cdev->hwfns,
1847                           "The chip type/rev (BB A0) is not supported!\n");
1848                 return -EINVAL;
1849         }
1850
1851         return 0;
1852 }
1853
1854 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
1855                                  void __iomem *p_regview,
1856                                  void __iomem *p_doorbells,
1857                                  enum qed_pci_personality personality)
1858 {
1859         int rc = 0;
1860
1861         /* Split PCI bars evenly between hwfns */
1862         p_hwfn->regview = p_regview;
1863         p_hwfn->doorbells = p_doorbells;
1864
1865         if (IS_VF(p_hwfn->cdev))
1866                 return qed_vf_hw_prepare(p_hwfn);
1867
1868         /* Validate that chip access is feasible */
1869         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
1870                 DP_ERR(p_hwfn,
1871                        "Reading the ME register returns all Fs; Preventing further chip access\n");
1872                 return -EINVAL;
1873         }
1874
1875         get_function_id(p_hwfn);
1876
1877         /* Allocate PTT pool */
1878         rc = qed_ptt_pool_alloc(p_hwfn);
1879         if (rc)
1880                 goto err0;
1881
1882         /* Allocate the main PTT */
1883         p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
1884
1885         /* First hwfn learns basic information, e.g., number of hwfns */
1886         if (!p_hwfn->my_id) {
1887                 rc = qed_get_dev_info(p_hwfn->cdev);
1888                 if (rc)
1889                         goto err1;
1890         }
1891
1892         qed_hw_hwfn_prepare(p_hwfn);
1893
1894         /* Initialize MCP structure */
1895         rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
1896         if (rc) {
1897                 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
1898                 goto err1;
1899         }
1900
1901         /* Read the device configuration information from the HW and SHMEM */
1902         rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
1903         if (rc) {
1904                 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
1905                 goto err2;
1906         }
1907
1908         /* Allocate the init RT array and initialize the init-ops engine */
1909         rc = qed_init_alloc(p_hwfn);
1910         if (rc)
1911                 goto err2;
1912
1913         return rc;
1914 err2:
1915         if (IS_LEAD_HWFN(p_hwfn))
1916                 qed_iov_free_hw_info(p_hwfn->cdev);
1917         qed_mcp_free(p_hwfn);
1918 err1:
1919         qed_hw_hwfn_free(p_hwfn);
1920 err0:
1921         return rc;
1922 }
1923
1924 int qed_hw_prepare(struct qed_dev *cdev,
1925                    int personality)
1926 {
1927         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1928         int rc;
1929
1930         /* Store the precompiled init data ptrs */
1931         if (IS_PF(cdev))
1932                 qed_init_iro_array(cdev);
1933
1934         /* Initialize the first hwfn - will learn number of hwfns */
1935         rc = qed_hw_prepare_single(p_hwfn,
1936                                    cdev->regview,
1937                                    cdev->doorbells, personality);
1938         if (rc)
1939                 return rc;
1940
1941         personality = p_hwfn->hw_info.personality;
1942
1943         /* Initialize the rest of the hwfns */
1944         if (cdev->num_hwfns > 1) {
1945                 void __iomem *p_regview, *p_doorbell;
1946                 u8 __iomem *addr;
1947
1948                 /* adjust bar offset for second engine */
1949                 addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
1950                 p_regview = addr;
1951
1952                 /* adjust doorbell bar offset for second engine */
1953                 addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
1954                 p_doorbell = addr;
1955
1956                 /* prepare second hw function */
1957                 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
1958                                            p_doorbell, personality);
1959
1960                 /* in case of error, need to free the previously
1961                  * initiliazed hwfn 0.
1962                  */
1963                 if (rc) {
1964                         if (IS_PF(cdev)) {
1965                                 qed_init_free(p_hwfn);
1966                                 qed_mcp_free(p_hwfn);
1967                                 qed_hw_hwfn_free(p_hwfn);
1968                         }
1969                 }
1970         }
1971
1972         return rc;
1973 }
1974
1975 void qed_hw_remove(struct qed_dev *cdev)
1976 {
1977         int i;
1978
1979         for_each_hwfn(cdev, i) {
1980                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1981
1982                 if (IS_VF(cdev)) {
1983                         qed_vf_pf_release(p_hwfn);
1984                         continue;
1985                 }
1986
1987                 qed_init_free(p_hwfn);
1988                 qed_hw_hwfn_free(p_hwfn);
1989                 qed_mcp_free(p_hwfn);
1990         }
1991
1992         qed_iov_free_hw_info(cdev);
1993 }
1994
1995 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
1996                                     struct qed_chain *p_chain)
1997 {
1998         void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
1999         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
2000         struct qed_chain_next *p_next;
2001         u32 size, i;
2002
2003         if (!p_virt)
2004                 return;
2005
2006         size = p_chain->elem_size * p_chain->usable_per_page;
2007
2008         for (i = 0; i < p_chain->page_cnt; i++) {
2009                 if (!p_virt)
2010                         break;
2011
2012                 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
2013                 p_virt_next = p_next->next_virt;
2014                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
2015
2016                 dma_free_coherent(&cdev->pdev->dev,
2017                                   QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
2018
2019                 p_virt = p_virt_next;
2020                 p_phys = p_phys_next;
2021         }
2022 }
2023
2024 static void qed_chain_free_single(struct qed_dev *cdev,
2025                                   struct qed_chain *p_chain)
2026 {
2027         if (!p_chain->p_virt_addr)
2028                 return;
2029
2030         dma_free_coherent(&cdev->pdev->dev,
2031                           QED_CHAIN_PAGE_SIZE,
2032                           p_chain->p_virt_addr, p_chain->p_phys_addr);
2033 }
2034
2035 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
2036 {
2037         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
2038         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
2039         u8 *p_pbl_virt = p_chain->pbl.p_virt_table;
2040
2041         if (!pp_virt_addr_tbl)
2042                 return;
2043
2044         if (!p_chain->pbl.p_virt_table)
2045                 goto out;
2046
2047         for (i = 0; i < page_cnt; i++) {
2048                 if (!pp_virt_addr_tbl[i])
2049                         break;
2050
2051                 dma_free_coherent(&cdev->pdev->dev,
2052                                   QED_CHAIN_PAGE_SIZE,
2053                                   pp_virt_addr_tbl[i],
2054                                   *(dma_addr_t *)p_pbl_virt);
2055
2056                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
2057         }
2058
2059         pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
2060         dma_free_coherent(&cdev->pdev->dev,
2061                           pbl_size,
2062                           p_chain->pbl.p_virt_table, p_chain->pbl.p_phys_table);
2063 out:
2064         vfree(p_chain->pbl.pp_virt_addr_tbl);
2065 }
2066
2067 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
2068 {
2069         switch (p_chain->mode) {
2070         case QED_CHAIN_MODE_NEXT_PTR:
2071                 qed_chain_free_next_ptr(cdev, p_chain);
2072                 break;
2073         case QED_CHAIN_MODE_SINGLE:
2074                 qed_chain_free_single(cdev, p_chain);
2075                 break;
2076         case QED_CHAIN_MODE_PBL:
2077                 qed_chain_free_pbl(cdev, p_chain);
2078                 break;
2079         }
2080 }
2081
2082 static int
2083 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
2084                              enum qed_chain_cnt_type cnt_type,
2085                              size_t elem_size, u32 page_cnt)
2086 {
2087         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
2088
2089         /* The actual chain size can be larger than the maximal possible value
2090          * after rounding up the requested elements number to pages, and after
2091          * taking into acount the unusuable elements (next-ptr elements).
2092          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
2093          * size/capacity fields are of a u32 type.
2094          */
2095         if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
2096              chain_size > 0x10000) ||
2097             (cnt_type == QED_CHAIN_CNT_TYPE_U32 &&
2098              chain_size > 0x100000000ULL)) {
2099                 DP_NOTICE(cdev,
2100                           "The actual chain size (0x%llx) is larger than the maximal possible value\n",
2101                           chain_size);
2102                 return -EINVAL;
2103         }
2104
2105         return 0;
2106 }
2107
2108 static int
2109 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
2110 {
2111         void *p_virt = NULL, *p_virt_prev = NULL;
2112         dma_addr_t p_phys = 0;
2113         u32 i;
2114
2115         for (i = 0; i < p_chain->page_cnt; i++) {
2116                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2117                                             QED_CHAIN_PAGE_SIZE,
2118                                             &p_phys, GFP_KERNEL);
2119                 if (!p_virt)
2120                         return -ENOMEM;
2121
2122                 if (i == 0) {
2123                         qed_chain_init_mem(p_chain, p_virt, p_phys);
2124                         qed_chain_reset(p_chain);
2125                 } else {
2126                         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2127                                                      p_virt, p_phys);
2128                 }
2129
2130                 p_virt_prev = p_virt;
2131         }
2132         /* Last page's next element should point to the beginning of the
2133          * chain.
2134          */
2135         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2136                                      p_chain->p_virt_addr,
2137                                      p_chain->p_phys_addr);
2138
2139         return 0;
2140 }
2141
2142 static int
2143 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
2144 {
2145         dma_addr_t p_phys = 0;
2146         void *p_virt = NULL;
2147
2148         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2149                                     QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
2150         if (!p_virt)
2151                 return -ENOMEM;
2152
2153         qed_chain_init_mem(p_chain, p_virt, p_phys);
2154         qed_chain_reset(p_chain);
2155
2156         return 0;
2157 }
2158
2159 static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
2160 {
2161         u32 page_cnt = p_chain->page_cnt, size, i;
2162         dma_addr_t p_phys = 0, p_pbl_phys = 0;
2163         void **pp_virt_addr_tbl = NULL;
2164         u8 *p_pbl_virt = NULL;
2165         void *p_virt = NULL;
2166
2167         size = page_cnt * sizeof(*pp_virt_addr_tbl);
2168         pp_virt_addr_tbl = vzalloc(size);
2169         if (!pp_virt_addr_tbl)
2170                 return -ENOMEM;
2171
2172         /* The allocation of the PBL table is done with its full size, since it
2173          * is expected to be successive.
2174          * qed_chain_init_pbl_mem() is called even in a case of an allocation
2175          * failure, since pp_virt_addr_tbl was previously allocated, and it
2176          * should be saved to allow its freeing during the error flow.
2177          */
2178         size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
2179         p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
2180                                         size, &p_pbl_phys, GFP_KERNEL);
2181         qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
2182                                pp_virt_addr_tbl);
2183         if (!p_pbl_virt)
2184                 return -ENOMEM;
2185
2186         for (i = 0; i < page_cnt; i++) {
2187                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2188                                             QED_CHAIN_PAGE_SIZE,
2189                                             &p_phys, GFP_KERNEL);
2190                 if (!p_virt)
2191                         return -ENOMEM;
2192
2193                 if (i == 0) {
2194                         qed_chain_init_mem(p_chain, p_virt, p_phys);
2195                         qed_chain_reset(p_chain);
2196                 }
2197
2198                 /* Fill the PBL table with the physical address of the page */
2199                 *(dma_addr_t *)p_pbl_virt = p_phys;
2200                 /* Keep the virtual address of the page */
2201                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
2202
2203                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
2204         }
2205
2206         return 0;
2207 }
2208
2209 int qed_chain_alloc(struct qed_dev *cdev,
2210                     enum qed_chain_use_mode intended_use,
2211                     enum qed_chain_mode mode,
2212                     enum qed_chain_cnt_type cnt_type,
2213                     u32 num_elems, size_t elem_size, struct qed_chain *p_chain)
2214 {
2215         u32 page_cnt;
2216         int rc = 0;
2217
2218         if (mode == QED_CHAIN_MODE_SINGLE)
2219                 page_cnt = 1;
2220         else
2221                 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
2222
2223         rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
2224         if (rc) {
2225                 DP_NOTICE(cdev,
2226                           "Cannot allocate a chain with the given arguments:\n");
2227                 DP_NOTICE(cdev,
2228                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
2229                           intended_use, mode, cnt_type, num_elems, elem_size);
2230                 return rc;
2231         }
2232
2233         qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
2234                               mode, cnt_type);
2235
2236         switch (mode) {
2237         case QED_CHAIN_MODE_NEXT_PTR:
2238                 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
2239                 break;
2240         case QED_CHAIN_MODE_SINGLE:
2241                 rc = qed_chain_alloc_single(cdev, p_chain);
2242                 break;
2243         case QED_CHAIN_MODE_PBL:
2244                 rc = qed_chain_alloc_pbl(cdev, p_chain);
2245                 break;
2246         }
2247         if (rc)
2248                 goto nomem;
2249
2250         return 0;
2251
2252 nomem:
2253         qed_chain_free(cdev, p_chain);
2254         return rc;
2255 }
2256
2257 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
2258 {
2259         if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
2260                 u16 min, max;
2261
2262                 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
2263                 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
2264                 DP_NOTICE(p_hwfn,
2265                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
2266                           src_id, min, max);
2267
2268                 return -EINVAL;
2269         }
2270
2271         *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
2272
2273         return 0;
2274 }
2275
2276 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
2277 {
2278         if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
2279                 u8 min, max;
2280
2281                 min = (u8)RESC_START(p_hwfn, QED_VPORT);
2282                 max = min + RESC_NUM(p_hwfn, QED_VPORT);
2283                 DP_NOTICE(p_hwfn,
2284                           "vport id [%d] is not valid, available indices [%d - %d]\n",
2285                           src_id, min, max);
2286
2287                 return -EINVAL;
2288         }
2289
2290         *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
2291
2292         return 0;
2293 }
2294
2295 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
2296 {
2297         if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
2298                 u8 min, max;
2299
2300                 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
2301                 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
2302                 DP_NOTICE(p_hwfn,
2303                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
2304                           src_id, min, max);
2305
2306                 return -EINVAL;
2307         }
2308
2309         *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
2310
2311         return 0;
2312 }
2313
2314 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
2315                                   u8 *p_filter)
2316 {
2317         *p_high = p_filter[1] | (p_filter[0] << 8);
2318         *p_low = p_filter[5] | (p_filter[4] << 8) |
2319                  (p_filter[3] << 16) | (p_filter[2] << 24);
2320 }
2321
2322 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
2323                            struct qed_ptt *p_ptt, u8 *p_filter)
2324 {
2325         u32 high = 0, low = 0, en;
2326         int i;
2327
2328         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2329                 return 0;
2330
2331         qed_llh_mac_to_filter(&high, &low, p_filter);
2332
2333         /* Find a free entry and utilize it */
2334         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2335                 en = qed_rd(p_hwfn, p_ptt,
2336                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
2337                 if (en)
2338                         continue;
2339                 qed_wr(p_hwfn, p_ptt,
2340                        NIG_REG_LLH_FUNC_FILTER_VALUE +
2341                        2 * i * sizeof(u32), low);
2342                 qed_wr(p_hwfn, p_ptt,
2343                        NIG_REG_LLH_FUNC_FILTER_VALUE +
2344                        (2 * i + 1) * sizeof(u32), high);
2345                 qed_wr(p_hwfn, p_ptt,
2346                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
2347                 qed_wr(p_hwfn, p_ptt,
2348                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2349                        i * sizeof(u32), 0);
2350                 qed_wr(p_hwfn, p_ptt,
2351                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
2352                 break;
2353         }
2354         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
2355                 DP_NOTICE(p_hwfn,
2356                           "Failed to find an empty LLH filter to utilize\n");
2357                 return -EINVAL;
2358         }
2359
2360         DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2361                    "mac: %pM is added at %d\n",
2362                    p_filter, i);
2363
2364         return 0;
2365 }
2366
2367 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
2368                                struct qed_ptt *p_ptt, u8 *p_filter)
2369 {
2370         u32 high = 0, low = 0;
2371         int i;
2372
2373         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2374                 return;
2375
2376         qed_llh_mac_to_filter(&high, &low, p_filter);
2377
2378         /* Find the entry and clean it */
2379         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2380                 if (qed_rd(p_hwfn, p_ptt,
2381                            NIG_REG_LLH_FUNC_FILTER_VALUE +
2382                            2 * i * sizeof(u32)) != low)
2383                         continue;
2384                 if (qed_rd(p_hwfn, p_ptt,
2385                            NIG_REG_LLH_FUNC_FILTER_VALUE +
2386                            (2 * i + 1) * sizeof(u32)) != high)
2387                         continue;
2388
2389                 qed_wr(p_hwfn, p_ptt,
2390                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2391                 qed_wr(p_hwfn, p_ptt,
2392                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
2393                 qed_wr(p_hwfn, p_ptt,
2394                        NIG_REG_LLH_FUNC_FILTER_VALUE +
2395                        (2 * i + 1) * sizeof(u32), 0);
2396
2397                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2398                            "mac: %pM is removed from %d\n",
2399                            p_filter, i);
2400                 break;
2401         }
2402         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
2403                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
2404 }
2405
2406 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2407                             u32 hw_addr, void *p_eth_qzone,
2408                             size_t eth_qzone_size, u8 timeset)
2409 {
2410         struct coalescing_timeset *p_coal_timeset;
2411
2412         if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
2413                 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
2414                 return -EINVAL;
2415         }
2416
2417         p_coal_timeset = p_eth_qzone;
2418         memset(p_coal_timeset, 0, eth_qzone_size);
2419         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
2420         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
2421         qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
2422
2423         return 0;
2424 }
2425
2426 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2427                          u16 coalesce, u8 qid, u16 sb_id)
2428 {
2429         struct ustorm_eth_queue_zone eth_qzone;
2430         u8 timeset, timer_res;
2431         u16 fw_qid = 0;
2432         u32 address;
2433         int rc;
2434
2435         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
2436         if (coalesce <= 0x7F) {
2437                 timer_res = 0;
2438         } else if (coalesce <= 0xFF) {
2439                 timer_res = 1;
2440         } else if (coalesce <= 0x1FF) {
2441                 timer_res = 2;
2442         } else {
2443                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
2444                 return -EINVAL;
2445         }
2446         timeset = (u8)(coalesce >> timer_res);
2447
2448         rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
2449         if (rc)
2450                 return rc;
2451
2452         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
2453         if (rc)
2454                 goto out;
2455
2456         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
2457
2458         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
2459                               sizeof(struct ustorm_eth_queue_zone), timeset);
2460         if (rc)
2461                 goto out;
2462
2463         p_hwfn->cdev->rx_coalesce_usecs = coalesce;
2464 out:
2465         return rc;
2466 }
2467
2468 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2469                          u16 coalesce, u8 qid, u16 sb_id)
2470 {
2471         struct xstorm_eth_queue_zone eth_qzone;
2472         u8 timeset, timer_res;
2473         u16 fw_qid = 0;
2474         u32 address;
2475         int rc;
2476
2477         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
2478         if (coalesce <= 0x7F) {
2479                 timer_res = 0;
2480         } else if (coalesce <= 0xFF) {
2481                 timer_res = 1;
2482         } else if (coalesce <= 0x1FF) {
2483                 timer_res = 2;
2484         } else {
2485                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
2486                 return -EINVAL;
2487         }
2488         timeset = (u8)(coalesce >> timer_res);
2489
2490         rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
2491         if (rc)
2492                 return rc;
2493
2494         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
2495         if (rc)
2496                 goto out;
2497
2498         address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
2499
2500         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
2501                               sizeof(struct xstorm_eth_queue_zone), timeset);
2502         if (rc)
2503                 goto out;
2504
2505         p_hwfn->cdev->tx_coalesce_usecs = coalesce;
2506 out:
2507         return rc;
2508 }
2509
2510 /* Calculate final WFQ values for all vports and configure them.
2511  * After this configuration each vport will have
2512  * approx min rate =  min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
2513  */
2514 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
2515                                              struct qed_ptt *p_ptt,
2516                                              u32 min_pf_rate)
2517 {
2518         struct init_qm_vport_params *vport_params;
2519         int i;
2520
2521         vport_params = p_hwfn->qm_info.qm_vport_params;
2522
2523         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2524                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
2525
2526                 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
2527                                                 min_pf_rate;
2528                 qed_init_vport_wfq(p_hwfn, p_ptt,
2529                                    vport_params[i].first_tx_pq_id,
2530                                    vport_params[i].vport_wfq);
2531         }
2532 }
2533
2534 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
2535                                        u32 min_pf_rate)
2536
2537 {
2538         int i;
2539
2540         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
2541                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
2542 }
2543
2544 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
2545                                            struct qed_ptt *p_ptt,
2546                                            u32 min_pf_rate)
2547 {
2548         struct init_qm_vport_params *vport_params;
2549         int i;
2550
2551         vport_params = p_hwfn->qm_info.qm_vport_params;
2552
2553         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2554                 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
2555                 qed_init_vport_wfq(p_hwfn, p_ptt,
2556                                    vport_params[i].first_tx_pq_id,
2557                                    vport_params[i].vport_wfq);
2558         }
2559 }
2560
2561 /* This function performs several validations for WFQ
2562  * configuration and required min rate for a given vport
2563  * 1. req_rate must be greater than one percent of min_pf_rate.
2564  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
2565  *    rates to get less than one percent of min_pf_rate.
2566  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
2567  */
2568 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
2569                               u16 vport_id, u32 req_rate, u32 min_pf_rate)
2570 {
2571         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
2572         int non_requested_count = 0, req_count = 0, i, num_vports;
2573
2574         num_vports = p_hwfn->qm_info.num_vports;
2575
2576         /* Accounting for the vports which are configured for WFQ explicitly */
2577         for (i = 0; i < num_vports; i++) {
2578                 u32 tmp_speed;
2579
2580                 if ((i != vport_id) &&
2581                     p_hwfn->qm_info.wfq_data[i].configured) {
2582                         req_count++;
2583                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
2584                         total_req_min_rate += tmp_speed;
2585                 }
2586         }
2587
2588         /* Include current vport data as well */
2589         req_count++;
2590         total_req_min_rate += req_rate;
2591         non_requested_count = num_vports - req_count;
2592
2593         if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
2594                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2595                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
2596                            vport_id, req_rate, min_pf_rate);
2597                 return -EINVAL;
2598         }
2599
2600         if (num_vports > QED_WFQ_UNIT) {
2601                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2602                            "Number of vports is greater than %d\n",
2603                            QED_WFQ_UNIT);
2604                 return -EINVAL;
2605         }
2606
2607         if (total_req_min_rate > min_pf_rate) {
2608                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2609                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
2610                            total_req_min_rate, min_pf_rate);
2611                 return -EINVAL;
2612         }
2613
2614         total_left_rate = min_pf_rate - total_req_min_rate;
2615
2616         left_rate_per_vp = total_left_rate / non_requested_count;
2617         if (left_rate_per_vp <  min_pf_rate / QED_WFQ_UNIT) {
2618                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2619                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
2620                            left_rate_per_vp, min_pf_rate);
2621                 return -EINVAL;
2622         }
2623
2624         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
2625         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
2626
2627         for (i = 0; i < num_vports; i++) {
2628                 if (p_hwfn->qm_info.wfq_data[i].configured)
2629                         continue;
2630
2631                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
2632         }
2633
2634         return 0;
2635 }
2636
2637 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
2638                                      struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
2639 {
2640         struct qed_mcp_link_state *p_link;
2641         int rc = 0;
2642
2643         p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
2644
2645         if (!p_link->min_pf_rate) {
2646                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
2647                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
2648                 return rc;
2649         }
2650
2651         rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
2652
2653         if (!rc)
2654                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
2655                                                  p_link->min_pf_rate);
2656         else
2657                 DP_NOTICE(p_hwfn,
2658                           "Validation failed while configuring min rate\n");
2659
2660         return rc;
2661 }
2662
2663 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
2664                                                  struct qed_ptt *p_ptt,
2665                                                  u32 min_pf_rate)
2666 {
2667         bool use_wfq = false;
2668         int rc = 0;
2669         u16 i;
2670
2671         /* Validate all pre configured vports for wfq */
2672         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2673                 u32 rate;
2674
2675                 if (!p_hwfn->qm_info.wfq_data[i].configured)
2676                         continue;
2677
2678                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
2679                 use_wfq = true;
2680
2681                 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
2682                 if (rc) {
2683                         DP_NOTICE(p_hwfn,
2684                                   "WFQ validation failed while configuring min rate\n");
2685                         break;
2686                 }
2687         }
2688
2689         if (!rc && use_wfq)
2690                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
2691         else
2692                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
2693
2694         return rc;
2695 }
2696
2697 /* Main API for qed clients to configure vport min rate.
2698  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
2699  * rate - Speed in Mbps needs to be assigned to a given vport.
2700  */
2701 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
2702 {
2703         int i, rc = -EINVAL;
2704
2705         /* Currently not supported; Might change in future */
2706         if (cdev->num_hwfns > 1) {
2707                 DP_NOTICE(cdev,
2708                           "WFQ configuration is not supported for this device\n");
2709                 return rc;
2710         }
2711
2712         for_each_hwfn(cdev, i) {
2713                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2714                 struct qed_ptt *p_ptt;
2715
2716                 p_ptt = qed_ptt_acquire(p_hwfn);
2717                 if (!p_ptt)
2718                         return -EBUSY;
2719
2720                 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
2721
2722                 if (rc) {
2723                         qed_ptt_release(p_hwfn, p_ptt);
2724                         return rc;
2725                 }
2726
2727                 qed_ptt_release(p_hwfn, p_ptt);
2728         }
2729
2730         return rc;
2731 }
2732
2733 /* API to configure WFQ from mcp link change */
2734 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate)
2735 {
2736         int i;
2737
2738         if (cdev->num_hwfns > 1) {
2739                 DP_VERBOSE(cdev,
2740                            NETIF_MSG_LINK,
2741                            "WFQ configuration is not supported for this device\n");
2742                 return;
2743         }
2744
2745         for_each_hwfn(cdev, i) {
2746                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2747
2748                 __qed_configure_vp_wfq_on_link_change(p_hwfn,
2749                                                       p_hwfn->p_dpc_ptt,
2750                                                       min_pf_rate);
2751         }
2752 }
2753
2754 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
2755                                      struct qed_ptt *p_ptt,
2756                                      struct qed_mcp_link_state *p_link,
2757                                      u8 max_bw)
2758 {
2759         int rc = 0;
2760
2761         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
2762
2763         if (!p_link->line_speed && (max_bw != 100))
2764                 return rc;
2765
2766         p_link->speed = (p_link->line_speed * max_bw) / 100;
2767         p_hwfn->qm_info.pf_rl = p_link->speed;
2768
2769         /* Since the limiter also affects Tx-switched traffic, we don't want it
2770          * to limit such traffic in case there's no actual limit.
2771          * In that case, set limit to imaginary high boundary.
2772          */
2773         if (max_bw == 100)
2774                 p_hwfn->qm_info.pf_rl = 100000;
2775
2776         rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
2777                             p_hwfn->qm_info.pf_rl);
2778
2779         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2780                    "Configured MAX bandwidth to be %08x Mb/sec\n",
2781                    p_link->speed);
2782
2783         return rc;
2784 }
2785
2786 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
2787 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
2788 {
2789         int i, rc = -EINVAL;
2790
2791         if (max_bw < 1 || max_bw > 100) {
2792                 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
2793                 return rc;
2794         }
2795
2796         for_each_hwfn(cdev, i) {
2797                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2798                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
2799                 struct qed_mcp_link_state *p_link;
2800                 struct qed_ptt *p_ptt;
2801
2802                 p_link = &p_lead->mcp_info->link_output;
2803
2804                 p_ptt = qed_ptt_acquire(p_hwfn);
2805                 if (!p_ptt)
2806                         return -EBUSY;
2807
2808                 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
2809                                                       p_link, max_bw);
2810
2811                 qed_ptt_release(p_hwfn, p_ptt);
2812
2813                 if (rc)
2814                         break;
2815         }
2816
2817         return rc;
2818 }
2819
2820 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
2821                                      struct qed_ptt *p_ptt,
2822                                      struct qed_mcp_link_state *p_link,
2823                                      u8 min_bw)
2824 {
2825         int rc = 0;
2826
2827         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
2828         p_hwfn->qm_info.pf_wfq = min_bw;
2829
2830         if (!p_link->line_speed)
2831                 return rc;
2832
2833         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
2834
2835         rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
2836
2837         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2838                    "Configured MIN bandwidth to be %d Mb/sec\n",
2839                    p_link->min_pf_rate);
2840
2841         return rc;
2842 }
2843
2844 /* Main API to configure PF min bandwidth where bw range is [1-100] */
2845 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
2846 {
2847         int i, rc = -EINVAL;
2848
2849         if (min_bw < 1 || min_bw > 100) {
2850                 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
2851                 return rc;
2852         }
2853
2854         for_each_hwfn(cdev, i) {
2855                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2856                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
2857                 struct qed_mcp_link_state *p_link;
2858                 struct qed_ptt *p_ptt;
2859
2860                 p_link = &p_lead->mcp_info->link_output;
2861
2862                 p_ptt = qed_ptt_acquire(p_hwfn);
2863                 if (!p_ptt)
2864                         return -EBUSY;
2865
2866                 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
2867                                                       p_link, min_bw);
2868                 if (rc) {
2869                         qed_ptt_release(p_hwfn, p_ptt);
2870                         return rc;
2871                 }
2872
2873                 if (p_link->min_pf_rate) {
2874                         u32 min_rate = p_link->min_pf_rate;
2875
2876                         rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
2877                                                                    p_ptt,
2878                                                                    min_rate);
2879                 }
2880
2881                 qed_ptt_release(p_hwfn, p_ptt);
2882         }
2883
2884         return rc;
2885 }
2886
2887 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2888 {
2889         struct qed_mcp_link_state *p_link;
2890
2891         p_link = &p_hwfn->mcp_info->link_output;
2892
2893         if (p_link->min_pf_rate)
2894                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
2895                                                p_link->min_pf_rate);
2896
2897         memset(p_hwfn->qm_info.wfq_data, 0,
2898                sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
2899 }