drivers/net/ethernet/qlogic/qed/qed_int.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #include <linux/types.h>
  10 #include <asm/byteorder.h>
  11 #include <linux/io.h>
  12 #include <linux/bitops.h>
  13 #include <linux/delay.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/errno.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/kernel.h>
  18 #include <linux/pci.h>
  19 #include <linux/slab.h>
  20 #include <linux/string.h>
  21 #include "qed.h"
  22 #include "qed_hsi.h"
  23 #include "qed_hw.h"
  24 #include "qed_init_ops.h"
  25 #include "qed_int.h"
  26 #include "qed_mcp.h"
  27 #include "qed_reg_addr.h"
  28 #include "qed_sp.h"
  29
  30 struct qed_pi_info {
  31         qed_int_comp_cb_t       comp_cb;
  32         void                    *cookie;
  33 };
  34
  35 struct qed_sb_sp_info {
  36         struct qed_sb_info      sb_info;
  37
  38         /* per protocol index data */
  39         struct qed_pi_info      pi_info_arr[PIS_PER_SB];
  40 };
  41
  42 void qed_int_sp_dpc(unsigned long hwfn_cookie)
  43 {
  44         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie;
  45         struct qed_pi_info *pi_info = NULL;
  46         struct qed_sb_info *sb_info;
  47         int arr_size;
  48         u16 rc = 0;
  49
  50         if (!p_hwfn) {
  51                 DP_ERR(p_hwfn->cdev, "DPC called - no hwfn!\n");
  52                 return;
  53         }
  54
  55         if (!p_hwfn->p_sp_sb) {
  56                 DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n");
  57                 return;
  58         }
  59
  60         sb_info = &p_hwfn->p_sp_sb->sb_info;
  61         arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
  62         if (!sb_info) {
  63                 DP_ERR(p_hwfn->cdev,
  64                        "Status block is NULL - cannot ack interrupts\n");
  65                 return;
  66         }
  67
  68         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
  69                    p_hwfn, p_hwfn->my_id);
  70
  71         /* Disable ack for def status block. Required both for msix +
  72          * inta in non-mask mode, in inta does no harm.
  73          */
  74         qed_sb_ack(sb_info, IGU_INT_DISABLE, 0);
  75
  76         /* Gather Interrupts/Attentions information */
  77         if (!sb_info->sb_virt) {
  78                 DP_ERR(
  79                         p_hwfn->cdev,
  80                         "Interrupt Status block is NULL - cannot check for new interrupts!\n");
  81         } else {
  82                 u32 tmp_index = sb_info->sb_ack;
  83
  84                 rc = qed_sb_update_sb_idx(sb_info);
  85                 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,
  86                            "Interrupt indices: 0x%08x --> 0x%08x\n",
  87                            tmp_index, sb_info->sb_ack);
  88         }
  89
  90         /* Check if we expect interrupts at this time. if not just ack them */
  91         if (!(rc & QED_SB_EVENT_MASK)) {
  92                 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
  93                 return;
  94         }
  95
  96         /* Check the validity of the DPC ptt. If not ack interrupts and fail */
  97         if (!p_hwfn->p_dpc_ptt) {
  98                 DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n");
  99                 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
 100                 return;
 101         }
 102
 103         if (rc & QED_SB_IDX) {
 104                 int pi;
 105
 106                 /* Look for a free index */
 107                 for (pi = 0; pi < arr_size; pi++) {
 108                         pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
 109                         if (pi_info->comp_cb)
 110                                 pi_info->comp_cb(p_hwfn, pi_info->cookie);
 111                 }
 112         }
 113
 114         qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
 115 }
 116
 117 /* coalescing timeout = timeset << (timer_res + 1) */
 118 #define QED_CAU_DEF_RX_USECS 24
 119 #define QED_CAU_DEF_TX_USECS 48
 120
 121 void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
 122                            struct cau_sb_entry *p_sb_entry,
 123                            u8 pf_id,
 124                            u16 vf_number,
 125                            u8 vf_valid)
 126 {
 127         u32 cau_state;
 128
 129         memset(p_sb_entry, 0, sizeof(*p_sb_entry));
 130
 131         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
 132         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
 133         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid);
 134         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
 135         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
 136
 137         /* setting the time resultion to a fixed value ( = 1) */
 138         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0,
 139                   QED_CAU_DEF_RX_TIMER_RES);
 140         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1,
 141                   QED_CAU_DEF_TX_TIMER_RES);
 142
 143         cau_state = CAU_HC_DISABLE_STATE;
 144
 145         if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
 146                 cau_state = CAU_HC_ENABLE_STATE;
 147                 if (!p_hwfn->cdev->rx_coalesce_usecs)
 148                         p_hwfn->cdev->rx_coalesce_usecs =
 149                                 QED_CAU_DEF_RX_USECS;
 150                 if (!p_hwfn->cdev->tx_coalesce_usecs)
 151                         p_hwfn->cdev->tx_coalesce_usecs =
 152                                 QED_CAU_DEF_TX_USECS;
 153         }
 154
 155         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
 156         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
 157 }
 158
 159 void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
 160                          struct qed_ptt *p_ptt,
 161                          dma_addr_t sb_phys,
 162                          u16 igu_sb_id,
 163                          u16 vf_number,
 164                          u8 vf_valid)
 165 {
 166         struct cau_sb_entry sb_entry;
 167         u32 val;
 168
 169         qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
 170                               vf_number, vf_valid);
 171
 172         if (p_hwfn->hw_init_done) {
 173                 val = CAU_REG_SB_ADDR_MEMORY + igu_sb_id * sizeof(u64);
 174                 qed_wr(p_hwfn, p_ptt, val, lower_32_bits(sb_phys));
 175                 qed_wr(p_hwfn, p_ptt, val + sizeof(u32),
 176                        upper_32_bits(sb_phys));
 177
 178                 val = CAU_REG_SB_VAR_MEMORY + igu_sb_id * sizeof(u64);
 179                 qed_wr(p_hwfn, p_ptt, val, sb_entry.data);
 180                 qed_wr(p_hwfn, p_ptt, val + sizeof(u32), sb_entry.params);
 181         } else {
 182                 /* Initialize Status Block Address */
 183                 STORE_RT_REG_AGG(p_hwfn,
 184                                  CAU_REG_SB_ADDR_MEMORY_RT_OFFSET +
 185                                  igu_sb_id * 2,
 186                                  sb_phys);
 187
 188                 STORE_RT_REG_AGG(p_hwfn,
 189                                  CAU_REG_SB_VAR_MEMORY_RT_OFFSET +
 190                                  igu_sb_id * 2,
 191                                  sb_entry);
 192         }
 193
 194         /* Configure pi coalescing if set */
 195         if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
 196                 u8 timeset = p_hwfn->cdev->rx_coalesce_usecs >>
 197                              (QED_CAU_DEF_RX_TIMER_RES + 1);
 198                 u8 num_tc = 1, i;
 199
 200                 qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
 201                                     QED_COAL_RX_STATE_MACHINE,
 202                                     timeset);
 203
 204                 timeset = p_hwfn->cdev->tx_coalesce_usecs >>
 205                           (QED_CAU_DEF_TX_TIMER_RES + 1);
 206
 207                 for (i = 0; i < num_tc; i++) {
 208                         qed_int_cau_conf_pi(p_hwfn, p_ptt,
 209                                             igu_sb_id, TX_PI(i),
 210                                             QED_COAL_TX_STATE_MACHINE,
 211                                             timeset);
 212                 }
 213         }
 214 }
 215
 216 void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
 217                          struct qed_ptt *p_ptt,
 218                          u16 igu_sb_id,
 219                          u32 pi_index,
 220                          enum qed_coalescing_fsm coalescing_fsm,
 221                          u8 timeset)
 222 {
 223         struct cau_pi_entry pi_entry;
 224         u32 sb_offset;
 225         u32 pi_offset;
 226
 227         sb_offset = igu_sb_id * PIS_PER_SB;
 228         memset(&pi_entry, 0, sizeof(struct cau_pi_entry));
 229
 230         SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
 231         if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE)
 232                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
 233         else
 234                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
 235
 236         pi_offset = sb_offset + pi_index;
 237         if (p_hwfn->hw_init_done) {
 238                 qed_wr(p_hwfn, p_ptt,
 239                        CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
 240                        *((u32 *)&(pi_entry)));
 241         } else {
 242                 STORE_RT_REG(p_hwfn,
 243                              CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
 244                              *((u32 *)&(pi_entry)));
 245         }
 246 }
 247
 248 void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
 249                       struct qed_ptt *p_ptt,
 250                       struct qed_sb_info *sb_info)
 251 {
 252         /* zero status block and ack counter */
 253         sb_info->sb_ack = 0;
 254         memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
 255
 256         qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
 257                             sb_info->igu_sb_id, 0, 0);
 258 }
 259
 260 /**
 261  * @brief qed_get_igu_sb_id - given a sw sb_id return the
 262  *        igu_sb_id
 263  *
 264  * @param p_hwfn
 265  * @param sb_id
 266  *
 267  * @return u16
 268  */
 269 static u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn,
 270                              u16 sb_id)
 271 {
 272         u16 igu_sb_id;
 273
 274         /* Assuming continuous set of IGU SBs dedicated for given PF */
 275         if (sb_id == QED_SP_SB_ID)
 276                 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
 277         else
 278                 igu_sb_id = sb_id + p_hwfn->hw_info.p_igu_info->igu_base_sb;
 279
 280         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "SB [%s] index is 0x%04x\n",
 281                    (sb_id == QED_SP_SB_ID) ? "DSB" : "non-DSB", igu_sb_id);
 282
 283         return igu_sb_id;
 284 }
 285
 286 int qed_int_sb_init(struct qed_hwfn *p_hwfn,
 287                     struct qed_ptt *p_ptt,
 288                     struct qed_sb_info *sb_info,
 289                     void *sb_virt_addr,
 290                     dma_addr_t sb_phy_addr,
 291                     u16 sb_id)
 292 {
 293         sb_info->sb_virt = sb_virt_addr;
 294         sb_info->sb_phys = sb_phy_addr;
 295
 296         sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id);
 297
 298         if (sb_id != QED_SP_SB_ID) {
 299                 p_hwfn->sbs_info[sb_id] = sb_info;
 300                 p_hwfn->num_sbs++;
 301         }
 302
 303         sb_info->cdev = p_hwfn->cdev;
 304
 305         /* The igu address will hold the absolute address that needs to be
 306          * written to for a specific status block
 307          */
 308         sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview +
 309                                           GTT_BAR0_MAP_REG_IGU_CMD +
 310                                           (sb_info->igu_sb_id << 3);
 311
 312         sb_info->flags |= QED_SB_INFO_INIT;
 313
 314         qed_int_sb_setup(p_hwfn, p_ptt, sb_info);
 315
 316         return 0;
 317 }
 318
 319 int qed_int_sb_release(struct qed_hwfn *p_hwfn,
 320                        struct qed_sb_info *sb_info,
 321                        u16 sb_id)
 322 {
 323         if (sb_id == QED_SP_SB_ID) {
 324                 DP_ERR(p_hwfn, "Do Not free sp sb using this function");
 325                 return -EINVAL;
 326         }
 327
 328         /* zero status block and ack counter */
 329         sb_info->sb_ack = 0;
 330         memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
 331
 332         p_hwfn->sbs_info[sb_id] = NULL;
 333         p_hwfn->num_sbs--;
 334
 335         return 0;
 336 }
 337
 338 static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn)
 339 {
 340         struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
 341
 342         if (p_sb) {
 343                 if (p_sb->sb_info.sb_virt)
 344                         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
 345                                           SB_ALIGNED_SIZE(p_hwfn),
 346                                           p_sb->sb_info.sb_virt,
 347                                           p_sb->sb_info.sb_phys);
 348                 kfree(p_sb);
 349         }
 350 }
 351
 352 static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn,
 353                                struct qed_ptt *p_ptt)
 354 {
 355         struct qed_sb_sp_info *p_sb;
 356         dma_addr_t p_phys = 0;
 357         void *p_virt;
 358
 359         /* SB struct */
 360         p_sb = kmalloc(sizeof(*p_sb), GFP_ATOMIC);
 361         if (!p_sb) {
 362                 DP_NOTICE(p_hwfn, "Failed to allocate `struct qed_sb_info'\n");
 363                 return -ENOMEM;
 364         }
 365
 366         /* SB ring  */
 367         p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
 368                                     SB_ALIGNED_SIZE(p_hwfn),
 369                                     &p_phys, GFP_KERNEL);
 370         if (!p_virt) {
 371                 DP_NOTICE(p_hwfn, "Failed to allocate status block\n");
 372                 kfree(p_sb);
 373                 return -ENOMEM;
 374         }
 375
 376         /* Status Block setup */
 377         p_hwfn->p_sp_sb = p_sb;
 378         qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt,
 379                         p_phys, QED_SP_SB_ID);
 380
 381         memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
 382
 383         return 0;
 384 }
 385
 386 static void qed_int_sp_sb_setup(struct qed_hwfn *p_hwfn,
 387                                 struct qed_ptt *p_ptt)
 388 {
 389         if (!p_hwfn)
 390                 return;
 391
 392         if (p_hwfn->p_sp_sb)
 393                 qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
 394         else
 395                 DP_NOTICE(p_hwfn->cdev,
 396                           "Failed to setup Slow path status block - NULL pointer\n");
 397 }
 398
 399 int qed_int_register_cb(struct qed_hwfn *p_hwfn,
 400                         qed_int_comp_cb_t comp_cb,
 401                         void *cookie,
 402                         u8 *sb_idx,
 403                         __le16 **p_fw_cons)
 404 {
 405         struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
 406         int qed_status = -ENOMEM;
 407         u8 pi;
 408
 409         /* Look for a free index */
 410         for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
 411                 if (!p_sp_sb->pi_info_arr[pi].comp_cb) {
 412                         p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
 413                         p_sp_sb->pi_info_arr[pi].cookie = cookie;
 414                         *sb_idx = pi;
 415                         *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
 416                         qed_status = 0;
 417                         break;
 418                 }
 419         }
 420
 421         return qed_status;
 422 }
 423
 424 int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi)
 425 {
 426         struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
 427         int qed_status = -ENOMEM;
 428
 429         if (p_sp_sb->pi_info_arr[pi].comp_cb) {
 430                 p_sp_sb->pi_info_arr[pi].comp_cb = NULL;
 431                 p_sp_sb->pi_info_arr[pi].cookie = NULL;
 432                 qed_status = 0;
 433         }
 434
 435         return qed_status;
 436 }
 437
 438 u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn)
 439 {
 440         return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
 441 }
 442
 443 void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
 444                             struct qed_ptt *p_ptt,
 445                             enum qed_int_mode int_mode)
 446 {
 447         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
 448
 449         p_hwfn->cdev->int_mode = int_mode;
 450         switch (p_hwfn->cdev->int_mode) {
 451         case QED_INT_MODE_INTA:
 452                 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
 453                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
 454                 break;
 455
 456         case QED_INT_MODE_MSI:
 457                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
 458                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
 459                 break;
 460
 461         case QED_INT_MODE_MSIX:
 462                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
 463                 break;
 464         case QED_INT_MODE_POLL:
 465                 break;
 466         }
 467
 468         qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
 469 }
 470
 471 void qed_int_igu_enable(struct qed_hwfn *p_hwfn,
 472                         struct qed_ptt *p_ptt,
 473                         enum qed_int_mode int_mode)
 474 {
 475         int i;
 476
 477         p_hwfn->b_int_enabled = 1;
 478
 479         /* Mask non-link attentions */
 480         for (i = 0; i < 9; i++)
 481                 qed_wr(p_hwfn, p_ptt,
 482                        MISC_REG_AEU_ENABLE1_IGU_OUT_0 + (i << 2), 0);
 483
 484         /* Enable interrupt Generation */
 485         qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
 486
 487         /* Flush the writes to IGU */
 488         mmiowb();
 489 }
 490
 491 void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn,
 492                              struct qed_ptt *p_ptt)
 493 {
 494         p_hwfn->b_int_enabled = 0;
 495
 496         qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
 497 }
 498
 499 #define IGU_CLEANUP_SLEEP_LENGTH                (1000)
 500 void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn,
 501                             struct qed_ptt *p_ptt,
 502                             u32 sb_id,
 503                             bool cleanup_set,
 504                             u16 opaque_fid
 505                             )
 506 {
 507         u32 pxp_addr = IGU_CMD_INT_ACK_BASE + sb_id;
 508         u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
 509         u32 data = 0;
 510         u32 cmd_ctrl = 0;
 511         u32 val = 0;
 512         u32 sb_bit = 0;
 513         u32 sb_bit_addr = 0;
 514
 515         /* Set the data field */
 516         SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
 517         SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0);
 518         SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
 519
 520         /* Set the control register */
 521         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
 522         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
 523         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
 524
 525         qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
 526
 527         barrier();
 528
 529         qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
 530
 531         /* Flush the write to IGU */
 532         mmiowb();
 533
 534         /* calculate where to read the status bit from */
 535         sb_bit = 1 << (sb_id % 32);
 536         sb_bit_addr = sb_id / 32 * sizeof(u32);
 537
 538         sb_bit_addr += IGU_REG_CLEANUP_STATUS_0;
 539
 540         /* Now wait for the command to complete */
 541         do {
 542                 val = qed_rd(p_hwfn, p_ptt, sb_bit_addr);
 543
 544                 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
 545                         break;
 546
 547                 usleep_range(5000, 10000);
 548         } while (--sleep_cnt);
 549
 550         if (!sleep_cnt)
 551                 DP_NOTICE(p_hwfn,
 552                           "Timeout waiting for clear status 0x%08x [for sb %d]\n",
 553                           val, sb_id);
 554 }
 555
 556 void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
 557                                      struct qed_ptt *p_ptt,
 558                                      u32 sb_id,
 559                                      u16 opaque,
 560                                      bool b_set)
 561 {
 562         int pi;
 563
 564         /* Set */
 565         if (b_set)
 566                 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 1, opaque);
 567
 568         /* Clear */
 569         qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 0, opaque);
 570
 571         /* Clear the CAU for the SB */
 572         for (pi = 0; pi < 12; pi++)
 573                 qed_wr(p_hwfn, p_ptt,
 574                        CAU_REG_PI_MEMORY + (sb_id * 12 + pi) * 4, 0);
 575 }
 576
 577 void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
 578                               struct qed_ptt *p_ptt,
 579                               bool b_set,
 580                               bool b_slowpath)
 581 {
 582         u32 igu_base_sb = p_hwfn->hw_info.p_igu_info->igu_base_sb;
 583         u32 igu_sb_cnt = p_hwfn->hw_info.p_igu_info->igu_sb_cnt;
 584         u32 sb_id = 0;
 585         u32 val = 0;
 586
 587         val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
 588         val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
 589         val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
 590         qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
 591
 592         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
 593                    "IGU cleaning SBs [%d,...,%d]\n",
 594                    igu_base_sb, igu_base_sb + igu_sb_cnt - 1);
 595
 596         for (sb_id = igu_base_sb; sb_id < igu_base_sb + igu_sb_cnt; sb_id++)
 597                 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
 598                                                 p_hwfn->hw_info.opaque_fid,
 599                                                 b_set);
 600
 601         if (b_slowpath) {
 602                 sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
 603                 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
 604                            "IGU cleaning slowpath SB [%d]\n", sb_id);
 605                 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
 606                                                 p_hwfn->hw_info.opaque_fid,
 607                                                 b_set);
 608         }
 609 }
 610
 611 int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn,
 612                          struct qed_ptt *p_ptt)
 613 {
 614         struct qed_igu_info *p_igu_info;
 615         struct qed_igu_block *blk;
 616         u32 val;
 617         u16 sb_id;
 618         u16 prev_sb_id = 0xFF;
 619
 620         p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_ATOMIC);
 621
 622         if (!p_hwfn->hw_info.p_igu_info)
 623                 return -ENOMEM;
 624
 625         p_igu_info = p_hwfn->hw_info.p_igu_info;
 626
 627         /* Initialize base sb / sb cnt for PFs */
 628         p_igu_info->igu_base_sb         = 0xffff;
 629         p_igu_info->igu_sb_cnt          = 0;
 630         p_igu_info->igu_dsb_id          = 0xffff;
 631         p_igu_info->igu_base_sb_iov     = 0xffff;
 632
 633         for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev);
 634              sb_id++) {
 635                 blk = &p_igu_info->igu_map.igu_blocks[sb_id];
 636
 637                 val = qed_rd(p_hwfn, p_ptt,
 638                              IGU_REG_MAPPING_MEMORY + sizeof(u32) * sb_id);
 639
 640                 /* stop scanning when hit first invalid PF entry */
 641                 if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) &&
 642                     GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID))
 643                         break;
 644
 645                 blk->status = QED_IGU_STATUS_VALID;
 646                 blk->function_id = GET_FIELD(val,
 647                                              IGU_MAPPING_LINE_FUNCTION_NUMBER);
 648                 blk->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
 649                 blk->vector_number = GET_FIELD(val,
 650                                                IGU_MAPPING_LINE_VECTOR_NUMBER);
 651
 652                 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
 653                            "IGU_BLOCK[sb_id]:%x:func_id = %d is_pf = %d vector_num = 0x%x\n",
 654                            val, blk->function_id, blk->is_pf,
 655                            blk->vector_number);
 656
 657                 if (blk->is_pf) {
 658                         if (blk->function_id == p_hwfn->rel_pf_id) {
 659                                 blk->status |= QED_IGU_STATUS_PF;
 660
 661                                 if (blk->vector_number == 0) {
 662                                         if (p_igu_info->igu_dsb_id == 0xffff)
 663                                                 p_igu_info->igu_dsb_id = sb_id;
 664                                 } else {
 665                                         if (p_igu_info->igu_base_sb ==
 666                                             0xffff) {
 667                                                 p_igu_info->igu_base_sb = sb_id;
 668                                         } else if (prev_sb_id != sb_id - 1) {
 669                                                 DP_NOTICE(p_hwfn->cdev,
 670                                                           "consecutive igu vectors for HWFN %x broken",
 671                                                           p_hwfn->rel_pf_id);
 672                                                 break;
 673                                         }
 674                                         prev_sb_id = sb_id;
 675                                         /* we don't count the default */
 676                                         (p_igu_info->igu_sb_cnt)++;
 677                                 }
 678                         }
 679                 }
 680         }
 681
 682         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
 683                    "IGU igu_base_sb=0x%x igu_sb_cnt=%d igu_dsb_id=0x%x\n",
 684                    p_igu_info->igu_base_sb,
 685                    p_igu_info->igu_sb_cnt,
 686                    p_igu_info->igu_dsb_id);
 687
 688         if (p_igu_info->igu_base_sb == 0xffff ||
 689             p_igu_info->igu_dsb_id == 0xffff ||
 690             p_igu_info->igu_sb_cnt == 0) {
 691                 DP_NOTICE(p_hwfn,
 692                           "IGU CAM returned invalid values igu_base_sb=0x%x igu_sb_cnt=%d igu_dsb_id=0x%x\n",
 693                            p_igu_info->igu_base_sb,
 694                            p_igu_info->igu_sb_cnt,
 695                            p_igu_info->igu_dsb_id);
 696                 return -EINVAL;
 697         }
 698
 699         return 0;
 700 }
 701
 702 /**
 703  * @brief Initialize igu runtime registers
 704  *
 705  * @param p_hwfn
 706  */
 707 void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn)
 708 {
 709         u32 igu_pf_conf = 0;
 710
 711         igu_pf_conf |= IGU_PF_CONF_FUNC_EN;
 712
 713         STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
 714 }
 715
 716 u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn)
 717 {
 718         u64 intr_status = 0;
 719         u32 intr_status_lo = 0;
 720         u32 intr_status_hi = 0;
 721         u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER -
 722                                IGU_CMD_INT_ACK_BASE;
 723         u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER -
 724                                IGU_CMD_INT_ACK_BASE;
 725
 726         intr_status_lo = REG_RD(p_hwfn,
 727                                 GTT_BAR0_MAP_REG_IGU_CMD +
 728                                 lsb_igu_cmd_addr * 8);
 729         intr_status_hi = REG_RD(p_hwfn,
 730                                 GTT_BAR0_MAP_REG_IGU_CMD +
 731                                 msb_igu_cmd_addr * 8);
 732         intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
 733
 734         return intr_status;
 735 }
 736
 737 static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn)
 738 {
 739         tasklet_init(p_hwfn->sp_dpc,
 740                      qed_int_sp_dpc, (unsigned long)p_hwfn);
 741         p_hwfn->b_sp_dpc_enabled = true;
 742 }
 743
 744 static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn)
 745 {
 746         p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_ATOMIC);
 747         if (!p_hwfn->sp_dpc)
 748                 return -ENOMEM;
 749
 750         return 0;
 751 }
 752
 753 static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn)
 754 {
 755         kfree(p_hwfn->sp_dpc);
 756 }
 757
 758 int qed_int_alloc(struct qed_hwfn *p_hwfn,
 759                   struct qed_ptt *p_ptt)
 760 {
 761         int rc = 0;
 762
 763         rc = qed_int_sp_dpc_alloc(p_hwfn);
 764         if (rc) {
 765                 DP_ERR(p_hwfn->cdev, "Failed to allocate sp dpc mem\n");
 766                 return rc;
 767         }
 768         rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt);
 769         if (rc) {
 770                 DP_ERR(p_hwfn->cdev, "Failed to allocate sp sb mem\n");
 771                 return rc;
 772         }
 773
 774         return rc;
 775 }
 776
 777 void qed_int_free(struct qed_hwfn *p_hwfn)
 778 {
 779         qed_int_sp_sb_free(p_hwfn);
 780         qed_int_sp_dpc_free(p_hwfn);
 781 }
 782
 783 void qed_int_setup(struct qed_hwfn *p_hwfn,
 784                    struct qed_ptt *p_ptt)
 785 {
 786         qed_int_sp_sb_setup(p_hwfn, p_ptt);
 787         qed_int_sp_dpc_setup(p_hwfn);
 788 }
 789
 790 int qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
 791                         int *p_iov_blks)
 792 {
 793         struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info;
 794
 795         if (!info)
 796                 return 0;
 797
 798         if (p_iov_blks)
 799                 *p_iov_blks = info->free_blks;
 800
 801         return info->igu_sb_cnt;
 802 }