drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/gpio.h>
  33 #include <linux/of.h>
  34 #include <linux/of_net.h>
  35 #include <linux/of_device.h>
  36 #include <linux/if_vlan.h>
  37
  38 #include <linux/pinctrl/consumer.h>
  39
  40 #include "cpsw.h"
  41 #include "cpsw_ale.h"
  42 #include "cpts.h"
  43 #include "davinci_cpdma.h"
  44
  45 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  46                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  47                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  48                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  49                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  50                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  51                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  52                          NETIF_MSG_RX_STATUS)
  53
  54 #define cpsw_info(priv, type, format, ...)              \
  55 do {                                                            \
  56         if (netif_msg_##type(priv) && net_ratelimit())          \
  57                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  58 } while (0)
  59
  60 #define cpsw_err(priv, type, format, ...)               \
  61 do {                                                            \
  62         if (netif_msg_##type(priv) && net_ratelimit())          \
  63                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  64 } while (0)
  65
  66 #define cpsw_dbg(priv, type, format, ...)               \
  67 do {                                                            \
  68         if (netif_msg_##type(priv) && net_ratelimit())          \
  69                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  70 } while (0)
  71
  72 #define cpsw_notice(priv, type, format, ...)            \
  73 do {                                                            \
  74         if (netif_msg_##type(priv) && net_ratelimit())          \
  75                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  76 } while (0)
  77
  78 #define ALE_ALL_PORTS           0x7
  79
  80 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  81 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  82 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  83
  84 #define CPSW_VERSION_1          0x19010a
  85 #define CPSW_VERSION_2          0x19010c
  86 #define CPSW_VERSION_3          0x19010f
  87 #define CPSW_VERSION_4          0x190112
  88
  89 #define HOST_PORT_NUM           0
  90 #define SLIVER_SIZE             0x40
  91
  92 #define CPSW1_HOST_PORT_OFFSET  0x028
  93 #define CPSW1_SLAVE_OFFSET      0x050
  94 #define CPSW1_SLAVE_SIZE        0x040
  95 #define CPSW1_CPDMA_OFFSET      0x100
  96 #define CPSW1_STATERAM_OFFSET   0x200
  97 #define CPSW1_HW_STATS          0x400
  98 #define CPSW1_CPTS_OFFSET       0x500
  99 #define CPSW1_ALE_OFFSET        0x600
 100 #define CPSW1_SLIVER_OFFSET     0x700
 101
 102 #define CPSW2_HOST_PORT_OFFSET  0x108
 103 #define CPSW2_SLAVE_OFFSET      0x200
 104 #define CPSW2_SLAVE_SIZE        0x100
 105 #define CPSW2_CPDMA_OFFSET      0x800
 106 #define CPSW2_HW_STATS          0x900
 107 #define CPSW2_STATERAM_OFFSET   0xa00
 108 #define CPSW2_CPTS_OFFSET       0xc00
 109 #define CPSW2_ALE_OFFSET        0xd00
 110 #define CPSW2_SLIVER_OFFSET     0xd80
 111 #define CPSW2_BD_OFFSET         0x2000
 112
 113 #define CPDMA_RXTHRESH          0x0c0
 114 #define CPDMA_RXFREE            0x0e0
 115 #define CPDMA_TXHDP             0x00
 116 #define CPDMA_RXHDP             0x20
 117 #define CPDMA_TXCP              0x40
 118 #define CPDMA_RXCP              0x60
 119
 120 #define CPSW_POLL_WEIGHT        64
 121 #define CPSW_MIN_PACKET_SIZE    60
 122 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 123
 124 #define RX_PRIORITY_MAPPING     0x76543210
 125 #define TX_PRIORITY_MAPPING     0x33221100
 126 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 127
 128 #define CPSW_VLAN_AWARE         BIT(1)
 129 #define CPSW_ALE_VLAN_AWARE     1
 130
 131 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 132 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 133 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 134
 135 #define CPSW_INTPACEEN          (0x3f << 16)
 136 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 137 #define CPSW_CMINTMAX_CNT       63
 138 #define CPSW_CMINTMIN_CNT       2
 139 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 140 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 141
 142 #define cpsw_slave_index(priv)                          \
 143                 ((priv->data.dual_emac) ? priv->emac_port :     \
 144                 priv->data.active_slave)
 145
 146 static int debug_level;
 147 module_param(debug_level, int, 0);
 148 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 149
 150 static int ale_ageout = 10;
 151 module_param(ale_ageout, int, 0);
 152 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 153
 154 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 155 module_param(rx_packet_max, int, 0);
 156 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 157
 158 struct cpsw_wr_regs {
 159         u32     id_ver;
 160         u32     soft_reset;
 161         u32     control;
 162         u32     int_control;
 163         u32     rx_thresh_en;
 164         u32     rx_en;
 165         u32     tx_en;
 166         u32     misc_en;
 167         u32     mem_allign1[8];
 168         u32     rx_thresh_stat;
 169         u32     rx_stat;
 170         u32     tx_stat;
 171         u32     misc_stat;
 172         u32     mem_allign2[8];
 173         u32     rx_imax;
 174         u32     tx_imax;
 175
 176 };
 177
 178 struct cpsw_ss_regs {
 179         u32     id_ver;
 180         u32     control;
 181         u32     soft_reset;
 182         u32     stat_port_en;
 183         u32     ptype;
 184         u32     soft_idle;
 185         u32     thru_rate;
 186         u32     gap_thresh;
 187         u32     tx_start_wds;
 188         u32     flow_control;
 189         u32     vlan_ltype;
 190         u32     ts_ltype;
 191         u32     dlr_ltype;
 192 };
 193
 194 /* CPSW_PORT_V1 */
 195 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 196 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 197 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 198 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 199 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 200 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 201 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 202 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 203
 204 /* CPSW_PORT_V2 */
 205 #define CPSW2_CONTROL       0x00 /* Control Register */
 206 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 207 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 208 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 209 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 210 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 211 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 212
 213 /* CPSW_PORT_V1 and V2 */
 214 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 215 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 216 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 217
 218 /* CPSW_PORT_V2 only */
 219 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 220 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 221 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 222 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 223 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 224 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 225 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 226 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 227
 228 /* Bit definitions for the CPSW2_CONTROL register */
 229 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 230 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 231 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 232 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 233 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 234 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 235 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 236 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 237 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 238 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 239 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 240 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 241 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 242 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 243 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 244 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 245 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 246
 247 #define CTRL_V2_TS_BITS \
 248         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 249          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 250
 251 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 252 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 253 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 254
 255
 256 #define CTRL_V3_TS_BITS \
 257         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 258          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 259          TS_LTYPE1_EN)
 260
 261 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 262 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 263 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 264
 265 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 266 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 267 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 268 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 269 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 270
 271 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 272 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 273
 274 /* Bit definitions for the CPSW1_TS_CTL register */
 275 #define CPSW_V1_TS_RX_EN                BIT(0)
 276 #define CPSW_V1_TS_TX_EN                BIT(4)
 277 #define CPSW_V1_MSG_TYPE_OFS            16
 278
 279 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 280 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 281
 282 struct cpsw_host_regs {
 283         u32     max_blks;
 284         u32     blk_cnt;
 285         u32     tx_in_ctl;
 286         u32     port_vlan;
 287         u32     tx_pri_map;
 288         u32     cpdma_tx_pri_map;
 289         u32     cpdma_rx_chan_map;
 290 };
 291
 292 struct cpsw_sliver_regs {
 293         u32     id_ver;
 294         u32     mac_control;
 295         u32     mac_status;
 296         u32     soft_reset;
 297         u32     rx_maxlen;
 298         u32     __reserved_0;
 299         u32     rx_pause;
 300         u32     tx_pause;
 301         u32     __reserved_1;
 302         u32     rx_pri_map;
 303 };
 304
 305 struct cpsw_hw_stats {
 306         u32     rxgoodframes;
 307         u32     rxbroadcastframes;
 308         u32     rxmulticastframes;
 309         u32     rxpauseframes;
 310         u32     rxcrcerrors;
 311         u32     rxaligncodeerrors;
 312         u32     rxoversizedframes;
 313         u32     rxjabberframes;
 314         u32     rxundersizedframes;
 315         u32     rxfragments;
 316         u32     __pad_0[2];
 317         u32     rxoctets;
 318         u32     txgoodframes;
 319         u32     txbroadcastframes;
 320         u32     txmulticastframes;
 321         u32     txpauseframes;
 322         u32     txdeferredframes;
 323         u32     txcollisionframes;
 324         u32     txsinglecollframes;
 325         u32     txmultcollframes;
 326         u32     txexcessivecollisions;
 327         u32     txlatecollisions;
 328         u32     txunderrun;
 329         u32     txcarriersenseerrors;
 330         u32     txoctets;
 331         u32     octetframes64;
 332         u32     octetframes65t127;
 333         u32     octetframes128t255;
 334         u32     octetframes256t511;
 335         u32     octetframes512t1023;
 336         u32     octetframes1024tup;
 337         u32     netoctets;
 338         u32     rxsofoverruns;
 339         u32     rxmofoverruns;
 340         u32     rxdmaoverruns;
 341 };
 342
 343 struct cpsw_slave {
 344         void __iomem                    *regs;
 345         struct cpsw_sliver_regs __iomem *sliver;
 346         int                             slave_num;
 347         u32                             mac_control;
 348         struct cpsw_slave_data          *data;
 349         struct phy_device               *phy;
 350         struct net_device               *ndev;
 351         u32                             port_vlan;
 352         u32                             open_stat;
 353 };
 354
 355 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 356 {
 357         return __raw_readl(slave->regs + offset);
 358 }
 359
 360 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 361 {
 362         __raw_writel(val, slave->regs + offset);
 363 }
 364
 365 struct cpsw_priv {
 366         spinlock_t                      lock;
 367         struct platform_device          *pdev;
 368         struct net_device               *ndev;
 369         struct napi_struct              napi_rx;
 370         struct napi_struct              napi_tx;
 371         struct device                   *dev;
 372         struct cpsw_platform_data       data;
 373         struct cpsw_ss_regs __iomem     *regs;
 374         struct cpsw_wr_regs __iomem     *wr_regs;
 375         u8 __iomem                      *hw_stats;
 376         struct cpsw_host_regs __iomem   *host_port_regs;
 377         u32                             msg_enable;
 378         u32                             version;
 379         u32                             coal_intvl;
 380         u32                             bus_freq_mhz;
 381         int                             rx_packet_max;
 382         int                             host_port;
 383         struct clk                      *clk;
 384         u8                              mac_addr[ETH_ALEN];
 385         struct cpsw_slave               *slaves;
 386         struct cpdma_ctlr               *dma;
 387         struct cpdma_chan               *txch, *rxch;
 388         struct cpsw_ale                 *ale;
 389         bool                            rx_pause;
 390         bool                            tx_pause;
 391         bool                            quirk_irq;
 392         bool                            rx_irq_disabled;
 393         bool                            tx_irq_disabled;
 394         /* snapshot of IRQ numbers */
 395         u32 irqs_table[4];
 396         u32 num_irqs;
 397         struct cpts *cpts;
 398         u32 emac_port;
 399 };
 400
 401 struct cpsw_stats {
 402         char stat_string[ETH_GSTRING_LEN];
 403         int type;
 404         int sizeof_stat;
 405         int stat_offset;
 406 };
 407
 408 enum {
 409         CPSW_STATS,
 410         CPDMA_RX_STATS,
 411         CPDMA_TX_STATS,
 412 };
 413
 414 #define CPSW_STAT(m)            CPSW_STATS,                             \
 415                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 416                                 offsetof(struct cpsw_hw_stats, m)
 417 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 418                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 419                                 offsetof(struct cpdma_chan_stats, m)
 420 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 421                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 422                                 offsetof(struct cpdma_chan_stats, m)
 423
 424 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 425         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 426         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 427         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 428         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 429         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 430         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 431         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 432         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 433         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 434         { "Rx Fragments", CPSW_STAT(rxfragments) },
 435         { "Rx Octets", CPSW_STAT(rxoctets) },
 436         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 437         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 438         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 439         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 440         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 441         { "Collisions", CPSW_STAT(txcollisionframes) },
 442         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 443         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 444         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 445         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 446         { "Tx Underrun", CPSW_STAT(txunderrun) },
 447         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 448         { "Tx Octets", CPSW_STAT(txoctets) },
 449         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 450         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 451         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 452         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 453         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 454         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 455         { "Net Octets", CPSW_STAT(netoctets) },
 456         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 457         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 458         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 459         { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 460         { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 461         { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 462         { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
 463         { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 464         { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 465         { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 466         { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 467         { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 468         { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 469         { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 470         { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
 471         { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 472         { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
 473         { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
 474         { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
 475         { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
 476         { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
 477         { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
 478         { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
 479         { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
 480         { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
 481         { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
 482         { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
 483         { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
 484         { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
 485 };
 486
 487 #define CPSW_STATS_LEN  ARRAY_SIZE(cpsw_gstrings_stats)
 488
 489 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
 490 #define for_each_slave(priv, func, arg...)                              \
 491         do {                                                            \
 492                 struct cpsw_slave *slave;                               \
 493                 int n;                                                  \
 494                 if (priv->data.dual_emac)                               \
 495                         (func)((priv)->slaves + priv->emac_port, ##arg);\
 496                 else                                                    \
 497                         for (n = (priv)->data.slaves,                   \
 498                                         slave = (priv)->slaves;         \
 499                                         n; n--)                         \
 500                                 (func)(slave++, ##arg);                 \
 501         } while (0)
 502 #define cpsw_get_slave_ndev(priv, __slave_no__)                         \
 503         ((__slave_no__ < priv->data.slaves) ?                           \
 504                 priv->slaves[__slave_no__].ndev : NULL)
 505 #define cpsw_get_slave_priv(priv, __slave_no__)                         \
 506         (((__slave_no__ < priv->data.slaves) &&                         \
 507                 (priv->slaves[__slave_no__].ndev)) ?                    \
 508                 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)    \
 509
 510 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)         \
 511         do {                                                            \
 512                 if (!priv->data.dual_emac)                              \
 513                         break;                                          \
 514                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 515                         ndev = cpsw_get_slave_ndev(priv, 0);            \
 516                         priv = netdev_priv(ndev);                       \
 517                         skb->dev = ndev;                                \
 518                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 519                         ndev = cpsw_get_slave_ndev(priv, 1);            \
 520                         priv = netdev_priv(ndev);                       \
 521                         skb->dev = ndev;                                \
 522                 }                                                       \
 523         } while (0)
 524 #define cpsw_add_mcast(priv, addr)                                      \
 525         do {                                                            \
 526                 if (priv->data.dual_emac) {                             \
 527                         struct cpsw_slave *slave = priv->slaves +       \
 528                                                 priv->emac_port;        \
 529                         int slave_port = cpsw_get_slave_port(priv,      \
 530                                                 slave->slave_num);      \
 531                         cpsw_ale_add_mcast(priv->ale, addr,             \
 532                                 1 << slave_port | 1 << priv->host_port, \
 533                                 ALE_VLAN, slave->port_vlan, 0);         \
 534                 } else {                                                \
 535                         cpsw_ale_add_mcast(priv->ale, addr,             \
 536                                 ALE_ALL_PORTS << priv->host_port,       \
 537                                 0, 0, 0);                               \
 538                 }                                                       \
 539         } while (0)
 540
 541 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 542 {
 543         if (priv->host_port == 0)
 544                 return slave_num + 1;
 545         else
 546                 return slave_num;
 547 }
 548
 549 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 550 {
 551         struct cpsw_priv *priv = netdev_priv(ndev);
 552         struct cpsw_ale *ale = priv->ale;
 553         int i;
 554
 555         if (priv->data.dual_emac) {
 556                 bool flag = false;
 557
 558                 /* Enabling promiscuous mode for one interface will be
 559                  * common for both the interface as the interface shares
 560                  * the same hardware resource.
 561                  */
 562                 for (i = 0; i < priv->data.slaves; i++)
 563                         if (priv->slaves[i].ndev->flags & IFF_PROMISC)
 564                                 flag = true;
 565
 566                 if (!enable && flag) {
 567                         enable = true;
 568                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 569                 }
 570
 571                 if (enable) {
 572                         /* Enable Bypass */
 573                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 574
 575                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 576                 } else {
 577                         /* Disable Bypass */
 578                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 579                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 580                 }
 581         } else {
 582                 if (enable) {
 583                         unsigned long timeout = jiffies + HZ;
 584
 585                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 586                         for (i = 0; i <= priv->data.slaves; i++) {
 587                                 cpsw_ale_control_set(ale, i,
 588                                                      ALE_PORT_NOLEARN, 1);
 589                                 cpsw_ale_control_set(ale, i,
 590                                                      ALE_PORT_NO_SA_UPDATE, 1);
 591                         }
 592
 593                         /* Clear All Untouched entries */
 594                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 595                         do {
 596                                 cpu_relax();
 597                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 598                                         break;
 599                         } while (time_after(timeout, jiffies));
 600                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 601
 602                         /* Clear all mcast from ALE */
 603                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
 604                                                  priv->host_port, -1);
 605
 606                         /* Flood All Unicast Packets to Host port */
 607                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 608                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 609                 } else {
 610                         /* Don't Flood All Unicast Packets to Host port */
 611                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 612
 613                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 614                         for (i = 0; i <= priv->data.slaves; i++) {
 615                                 cpsw_ale_control_set(ale, i,
 616                                                      ALE_PORT_NOLEARN, 0);
 617                                 cpsw_ale_control_set(ale, i,
 618                                                      ALE_PORT_NO_SA_UPDATE, 0);
 619                         }
 620                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 621                 }
 622         }
 623 }
 624
 625 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 626 {
 627         struct cpsw_priv *priv = netdev_priv(ndev);
 628         int vid;
 629
 630         if (priv->data.dual_emac)
 631                 vid = priv->slaves[priv->emac_port].port_vlan;
 632         else
 633                 vid = priv->data.default_vlan;
 634
 635         if (ndev->flags & IFF_PROMISC) {
 636                 /* Enable promiscuous mode */
 637                 cpsw_set_promiscious(ndev, true);
 638                 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
 639                 return;
 640         } else {
 641                 /* Disable promiscuous mode */
 642                 cpsw_set_promiscious(ndev, false);
 643         }
 644
 645         /* Restore allmulti on vlans if necessary */
 646         cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
 647
 648         /* Clear all mcast from ALE */
 649         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
 650                                  vid);
 651
 652         if (!netdev_mc_empty(ndev)) {
 653                 struct netdev_hw_addr *ha;
 654
 655                 /* program multicast address list into ALE register */
 656                 netdev_for_each_mc_addr(ha, ndev) {
 657                         cpsw_add_mcast(priv, (u8 *)ha->addr);
 658                 }
 659         }
 660 }
 661
 662 static void cpsw_intr_enable(struct cpsw_priv *priv)
 663 {
 664         __raw_writel(0xFF, &priv->wr_regs->tx_en);
 665         __raw_writel(0xFF, &priv->wr_regs->rx_en);
 666
 667         cpdma_ctlr_int_ctrl(priv->dma, true);
 668         return;
 669 }
 670
 671 static void cpsw_intr_disable(struct cpsw_priv *priv)
 672 {
 673         __raw_writel(0, &priv->wr_regs->tx_en);
 674         __raw_writel(0, &priv->wr_regs->rx_en);
 675
 676         cpdma_ctlr_int_ctrl(priv->dma, false);
 677         return;
 678 }
 679
 680 static void cpsw_tx_handler(void *token, int len, int status)
 681 {
 682         struct sk_buff          *skb = token;
 683         struct net_device       *ndev = skb->dev;
 684         struct cpsw_priv        *priv = netdev_priv(ndev);
 685
 686         /* Check whether the queue is stopped due to stalled tx dma, if the
 687          * queue is stopped then start the queue as we have free desc for tx
 688          */
 689         if (unlikely(netif_queue_stopped(ndev)))
 690                 netif_wake_queue(ndev);
 691         cpts_tx_timestamp(priv->cpts, skb);
 692         ndev->stats.tx_packets++;
 693         ndev->stats.tx_bytes += len;
 694         dev_kfree_skb_any(skb);
 695 }
 696
 697 static void cpsw_rx_handler(void *token, int len, int status)
 698 {
 699         struct sk_buff          *skb = token;
 700         struct sk_buff          *new_skb;
 701         struct net_device       *ndev = skb->dev;
 702         struct cpsw_priv        *priv = netdev_priv(ndev);
 703         int                     ret = 0;
 704
 705         cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
 706
 707         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 708                 bool ndev_status = false;
 709                 struct cpsw_slave *slave = priv->slaves;
 710                 int n;
 711
 712                 if (priv->data.dual_emac) {
 713                         /* In dual emac mode check for all interfaces */
 714                         for (n = priv->data.slaves; n; n--, slave++)
 715                                 if (netif_running(slave->ndev))
 716                                         ndev_status = true;
 717                 }
 718
 719                 if (ndev_status && (status >= 0)) {
 720                         /* The packet received is for the interface which
 721                          * is already down and the other interface is up
 722                          * and running, instead of freeing which results
 723                          * in reducing of the number of rx descriptor in
 724                          * DMA engine, requeue skb back to cpdma.
 725                          */
 726                         new_skb = skb;
 727                         goto requeue;
 728                 }
 729
 730                 /* the interface is going down, skbs are purged */
 731                 dev_kfree_skb_any(skb);
 732                 return;
 733         }
 734
 735         new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
 736         if (new_skb) {
 737                 skb_put(skb, len);
 738                 cpts_rx_timestamp(priv->cpts, skb);
 739                 skb->protocol = eth_type_trans(skb, ndev);
 740                 netif_receive_skb(skb);
 741                 ndev->stats.rx_bytes += len;
 742                 ndev->stats.rx_packets++;
 743         } else {
 744                 ndev->stats.rx_dropped++;
 745                 new_skb = skb;
 746         }
 747
 748 requeue:
 749         ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
 750                         skb_tailroom(new_skb), 0);
 751         if (WARN_ON(ret < 0))
 752                 dev_kfree_skb_any(new_skb);
 753 }
 754
 755 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
 756 {
 757         struct cpsw_priv *priv = dev_id;
 758
 759         writel(0, &priv->wr_regs->tx_en);
 760         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
 761
 762         if (priv->quirk_irq) {
 763                 disable_irq_nosync(priv->irqs_table[1]);
 764                 priv->tx_irq_disabled = true;
 765         }
 766
 767         napi_schedule(&priv->napi_tx);
 768         return IRQ_HANDLED;
 769 }
 770
 771 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
 772 {
 773         struct cpsw_priv *priv = dev_id;
 774
 775         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
 776         writel(0, &priv->wr_regs->rx_en);
 777
 778         if (priv->quirk_irq) {
 779                 disable_irq_nosync(priv->irqs_table[0]);
 780                 priv->rx_irq_disabled = true;
 781         }
 782
 783         napi_schedule(&priv->napi_rx);
 784         return IRQ_HANDLED;
 785 }
 786
 787 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
 788 {
 789         struct cpsw_priv        *priv = napi_to_priv(napi_tx);
 790         int                     num_tx;
 791
 792         num_tx = cpdma_chan_process(priv->txch, budget);
 793         if (num_tx < budget) {
 794                 napi_complete(napi_tx);
 795                 writel(0xff, &priv->wr_regs->tx_en);
 796                 if (priv->quirk_irq && priv->tx_irq_disabled) {
 797                         priv->tx_irq_disabled = false;
 798                         enable_irq(priv->irqs_table[1]);
 799                 }
 800         }
 801
 802         if (num_tx)
 803                 cpsw_dbg(priv, intr, "poll %d tx pkts\n", num_tx);
 804
 805         return num_tx;
 806 }
 807
 808 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
 809 {
 810         struct cpsw_priv        *priv = napi_to_priv(napi_rx);
 811         int                     num_rx;
 812
 813         num_rx = cpdma_chan_process(priv->rxch, budget);
 814         if (num_rx < budget) {
 815                 napi_complete(napi_rx);
 816                 writel(0xff, &priv->wr_regs->rx_en);
 817                 if (priv->quirk_irq && priv->rx_irq_disabled) {
 818                         priv->rx_irq_disabled = false;
 819                         enable_irq(priv->irqs_table[0]);
 820                 }
 821         }
 822
 823         if (num_rx)
 824                 cpsw_dbg(priv, intr, "poll %d rx pkts\n", num_rx);
 825
 826         return num_rx;
 827 }
 828
 829 static inline void soft_reset(const char *module, void __iomem *reg)
 830 {
 831         unsigned long timeout = jiffies + HZ;
 832
 833         __raw_writel(1, reg);
 834         do {
 835                 cpu_relax();
 836         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 837
 838         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 839 }
 840
 841 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 842                          ((mac)[2] << 16) | ((mac)[3] << 24))
 843 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 844
 845 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 846                                struct cpsw_priv *priv)
 847 {
 848         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 849         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 850 }
 851
 852 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 853                               struct cpsw_priv *priv, bool *link)
 854 {
 855         struct phy_device       *phy = slave->phy;
 856         u32                     mac_control = 0;
 857         u32                     slave_port;
 858
 859         if (!phy)
 860                 return;
 861
 862         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 863
 864         if (phy->link) {
 865                 mac_control = priv->data.mac_control;
 866
 867                 /* enable forwarding */
 868                 cpsw_ale_control_set(priv->ale, slave_port,
 869                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 870
 871                 if (phy->speed == 1000)
 872                         mac_control |= BIT(7);  /* GIGABITEN    */
 873                 if (phy->duplex)
 874                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 875
 876                 /* set speed_in input in case RMII mode is used in 100Mbps */
 877                 if (phy->speed == 100)
 878                         mac_control |= BIT(15);
 879                 else if (phy->speed == 10)
 880                         mac_control |= BIT(18); /* In Band mode */
 881
 882                 if (priv->rx_pause)
 883                         mac_control |= BIT(3);
 884
 885                 if (priv->tx_pause)
 886                         mac_control |= BIT(4);
 887
 888                 *link = true;
 889         } else {
 890                 mac_control = 0;
 891                 /* disable forwarding */
 892                 cpsw_ale_control_set(priv->ale, slave_port,
 893                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 894         }
 895
 896         if (mac_control != slave->mac_control) {
 897                 phy_print_status(phy);
 898                 __raw_writel(mac_control, &slave->sliver->mac_control);
 899         }
 900
 901         slave->mac_control = mac_control;
 902 }
 903
 904 static void cpsw_adjust_link(struct net_device *ndev)
 905 {
 906         struct cpsw_priv        *priv = netdev_priv(ndev);
 907         bool                    link = false;
 908
 909         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 910
 911         if (link) {
 912                 netif_carrier_on(ndev);
 913                 if (netif_running(ndev))
 914                         netif_wake_queue(ndev);
 915         } else {
 916                 netif_carrier_off(ndev);
 917                 netif_stop_queue(ndev);
 918         }
 919 }
 920
 921 static int cpsw_get_coalesce(struct net_device *ndev,
 922                                 struct ethtool_coalesce *coal)
 923 {
 924         struct cpsw_priv *priv = netdev_priv(ndev);
 925
 926         coal->rx_coalesce_usecs = priv->coal_intvl;
 927         return 0;
 928 }
 929
 930 static int cpsw_set_coalesce(struct net_device *ndev,
 931                                 struct ethtool_coalesce *coal)
 932 {
 933         struct cpsw_priv *priv = netdev_priv(ndev);
 934         u32 int_ctrl;
 935         u32 num_interrupts = 0;
 936         u32 prescale = 0;
 937         u32 addnl_dvdr = 1;
 938         u32 coal_intvl = 0;
 939
 940         coal_intvl = coal->rx_coalesce_usecs;
 941
 942         int_ctrl =  readl(&priv->wr_regs->int_control);
 943         prescale = priv->bus_freq_mhz * 4;
 944
 945         if (!coal->rx_coalesce_usecs) {
 946                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
 947                 goto update_return;
 948         }
 949
 950         if (coal_intvl < CPSW_CMINTMIN_INTVL)
 951                 coal_intvl = CPSW_CMINTMIN_INTVL;
 952
 953         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
 954                 /* Interrupt pacer works with 4us Pulse, we can
 955                  * throttle further by dilating the 4us pulse.
 956                  */
 957                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
 958
 959                 if (addnl_dvdr > 1) {
 960                         prescale *= addnl_dvdr;
 961                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
 962                                 coal_intvl = (CPSW_CMINTMAX_INTVL
 963                                                 * addnl_dvdr);
 964                 } else {
 965                         addnl_dvdr = 1;
 966                         coal_intvl = CPSW_CMINTMAX_INTVL;
 967                 }
 968         }
 969
 970         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 971         writel(num_interrupts, &priv->wr_regs->rx_imax);
 972         writel(num_interrupts, &priv->wr_regs->tx_imax);
 973
 974         int_ctrl |= CPSW_INTPACEEN;
 975         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
 976         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
 977
 978 update_return:
 979         writel(int_ctrl, &priv->wr_regs->int_control);
 980
 981         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
 982         if (priv->data.dual_emac) {
 983                 int i;
 984
 985                 for (i = 0; i < priv->data.slaves; i++) {
 986                         priv = netdev_priv(priv->slaves[i].ndev);
 987                         priv->coal_intvl = coal_intvl;
 988                 }
 989         } else {
 990                 priv->coal_intvl = coal_intvl;
 991         }
 992
 993         return 0;
 994 }
 995
 996 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
 997 {
 998         switch (sset) {
 999         case ETH_SS_STATS:
1000                 return CPSW_STATS_LEN;
1001         default:
1002                 return -EOPNOTSUPP;
1003         }
1004 }
1005
1006 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1007 {
1008         u8 *p = data;
1009         int i;
1010
1011         switch (stringset) {
1012         case ETH_SS_STATS:
1013                 for (i = 0; i < CPSW_STATS_LEN; i++) {
1014                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1015                                ETH_GSTRING_LEN);
1016                         p += ETH_GSTRING_LEN;
1017                 }
1018                 break;
1019         }
1020 }
1021
1022 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1023                                     struct ethtool_stats *stats, u64 *data)
1024 {
1025         struct cpsw_priv *priv = netdev_priv(ndev);
1026         struct cpdma_chan_stats rx_stats;
1027         struct cpdma_chan_stats tx_stats;
1028         u32 val;
1029         u8 *p;
1030         int i;
1031
1032         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1033         cpdma_chan_get_stats(priv->rxch, &rx_stats);
1034         cpdma_chan_get_stats(priv->txch, &tx_stats);
1035
1036         for (i = 0; i < CPSW_STATS_LEN; i++) {
1037                 switch (cpsw_gstrings_stats[i].type) {
1038                 case CPSW_STATS:
1039                         val = readl(priv->hw_stats +
1040                                     cpsw_gstrings_stats[i].stat_offset);
1041                         data[i] = val;
1042                         break;
1043
1044                 case CPDMA_RX_STATS:
1045                         p = (u8 *)&rx_stats +
1046                                 cpsw_gstrings_stats[i].stat_offset;
1047                         data[i] = *(u32 *)p;
1048                         break;
1049
1050                 case CPDMA_TX_STATS:
1051                         p = (u8 *)&tx_stats +
1052                                 cpsw_gstrings_stats[i].stat_offset;
1053                         data[i] = *(u32 *)p;
1054                         break;
1055                 }
1056         }
1057 }
1058
1059 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1060 {
1061         u32 i;
1062         u32 usage_count = 0;
1063
1064         if (!priv->data.dual_emac)
1065                 return 0;
1066
1067         for (i = 0; i < priv->data.slaves; i++)
1068                 if (priv->slaves[i].open_stat)
1069                         usage_count++;
1070
1071         return usage_count;
1072 }
1073
1074 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1075                         struct cpsw_priv *priv, struct sk_buff *skb)
1076 {
1077         if (!priv->data.dual_emac)
1078                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1079                                   skb->len, 0);
1080
1081         if (ndev == cpsw_get_slave_ndev(priv, 0))
1082                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1083                                   skb->len, 1);
1084         else
1085                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1086                                   skb->len, 2);
1087 }
1088
1089 static inline void cpsw_add_dual_emac_def_ale_entries(
1090                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1091                 u32 slave_port)
1092 {
1093         u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1094
1095         if (priv->version == CPSW_VERSION_1)
1096                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1097         else
1098                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1099         cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1100                           port_mask, port_mask, 0);
1101         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1102                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1103         cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1104                 priv->host_port, ALE_VLAN | ALE_SECURE, slave->port_vlan);
1105 }
1106
1107 static void soft_reset_slave(struct cpsw_slave *slave)
1108 {
1109         char name[32];
1110
1111         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1112         soft_reset(name, &slave->sliver->soft_reset);
1113 }
1114
1115 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1116 {
1117         u32 slave_port;
1118
1119         soft_reset_slave(slave);
1120
1121         /* setup priority mapping */
1122         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1123
1124         switch (priv->version) {
1125         case CPSW_VERSION_1:
1126                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1127                 break;
1128         case CPSW_VERSION_2:
1129         case CPSW_VERSION_3:
1130         case CPSW_VERSION_4:
1131                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1132                 break;
1133         }
1134
1135         /* setup max packet size, and mac address */
1136         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1137         cpsw_set_slave_mac(slave, priv);
1138
1139         slave->mac_control = 0; /* no link yet */
1140
1141         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1142
1143         if (priv->data.dual_emac)
1144                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1145         else
1146                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1147                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1148
1149         slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1150                                  &cpsw_adjust_link, slave->data->phy_if);
1151         if (IS_ERR(slave->phy)) {
1152                 dev_err(priv->dev, "phy %s not found on slave %d\n",
1153                         slave->data->phy_id, slave->slave_num);
1154                 slave->phy = NULL;
1155         } else {
1156                 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1157                          slave->phy->phy_id);
1158                 phy_start(slave->phy);
1159
1160                 /* Configure GMII_SEL register */
1161                 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1162                              slave->slave_num);
1163         }
1164 }
1165
1166 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1167 {
1168         const int vlan = priv->data.default_vlan;
1169         const int port = priv->host_port;
1170         u32 reg;
1171         int i;
1172         int unreg_mcast_mask;
1173
1174         reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1175                CPSW2_PORT_VLAN;
1176
1177         writel(vlan, &priv->host_port_regs->port_vlan);
1178
1179         for (i = 0; i < priv->data.slaves; i++)
1180                 slave_write(priv->slaves + i, vlan, reg);
1181
1182         if (priv->ndev->flags & IFF_ALLMULTI)
1183                 unreg_mcast_mask = ALE_ALL_PORTS;
1184         else
1185                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1186
1187         cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1188                           ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1189                           unreg_mcast_mask << port);
1190 }
1191
1192 static void cpsw_init_host_port(struct cpsw_priv *priv)
1193 {
1194         u32 control_reg;
1195         u32 fifo_mode;
1196
1197         /* soft reset the controller and initialize ale */
1198         soft_reset("cpsw", &priv->regs->soft_reset);
1199         cpsw_ale_start(priv->ale);
1200
1201         /* switch to vlan unaware mode */
1202         cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1203                              CPSW_ALE_VLAN_AWARE);
1204         control_reg = readl(&priv->regs->control);
1205         control_reg |= CPSW_VLAN_AWARE;
1206         writel(control_reg, &priv->regs->control);
1207         fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1208                      CPSW_FIFO_NORMAL_MODE;
1209         writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1210
1211         /* setup host port priority mapping */
1212         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1213                      &priv->host_port_regs->cpdma_tx_pri_map);
1214         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1215
1216         cpsw_ale_control_set(priv->ale, priv->host_port,
1217                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1218
1219         if (!priv->data.dual_emac) {
1220                 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1221                                    0, 0);
1222                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1223                                    1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1224         }
1225 }
1226
1227 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1228 {
1229         u32 slave_port;
1230
1231         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1232
1233         if (!slave->phy)
1234                 return;
1235         phy_stop(slave->phy);
1236         phy_disconnect(slave->phy);
1237         slave->phy = NULL;
1238         cpsw_ale_control_set(priv->ale, slave_port,
1239                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1240 }
1241
1242 static int cpsw_ndo_open(struct net_device *ndev)
1243 {
1244         struct cpsw_priv *priv = netdev_priv(ndev);
1245         int i, ret;
1246         u32 reg;
1247
1248         if (!cpsw_common_res_usage_state(priv))
1249                 cpsw_intr_disable(priv);
1250         netif_carrier_off(ndev);
1251
1252         pm_runtime_get_sync(&priv->pdev->dev);
1253
1254         reg = priv->version;
1255
1256         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1257                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1258                  CPSW_RTL_VERSION(reg));
1259
1260         /* initialize host and slave ports */
1261         if (!cpsw_common_res_usage_state(priv))
1262                 cpsw_init_host_port(priv);
1263         for_each_slave(priv, cpsw_slave_open, priv);
1264
1265         /* Add default VLAN */
1266         if (!priv->data.dual_emac)
1267                 cpsw_add_default_vlan(priv);
1268         else
1269                 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1270                                   ALE_ALL_PORTS << priv->host_port,
1271                                   ALE_ALL_PORTS << priv->host_port, 0, 0);
1272
1273         if (!cpsw_common_res_usage_state(priv)) {
1274                 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1275
1276                 /* setup tx dma to fixed prio and zero offset */
1277                 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1278                 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1279
1280                 /* disable priority elevation */
1281                 __raw_writel(0, &priv->regs->ptype);
1282
1283                 /* enable statistics collection only on all ports */
1284                 __raw_writel(0x7, &priv->regs->stat_port_en);
1285
1286                 /* Enable internal fifo flow control */
1287                 writel(0x7, &priv->regs->flow_control);
1288
1289                 napi_enable(&priv_sl0->napi_rx);
1290                 napi_enable(&priv_sl0->napi_tx);
1291
1292                 if (priv_sl0->tx_irq_disabled) {
1293                         priv_sl0->tx_irq_disabled = false;
1294                         enable_irq(priv->irqs_table[1]);
1295                 }
1296
1297                 if (priv_sl0->rx_irq_disabled) {
1298                         priv_sl0->rx_irq_disabled = false;
1299                         enable_irq(priv->irqs_table[0]);
1300                 }
1301
1302                 if (WARN_ON(!priv->data.rx_descs))
1303                         priv->data.rx_descs = 128;
1304
1305                 for (i = 0; i < priv->data.rx_descs; i++) {
1306                         struct sk_buff *skb;
1307
1308                         ret = -ENOMEM;
1309                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1310                                         priv->rx_packet_max, GFP_KERNEL);
1311                         if (!skb)
1312                                 goto err_cleanup;
1313                         ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1314                                         skb_tailroom(skb), 0);
1315                         if (ret < 0) {
1316                                 kfree_skb(skb);
1317                                 goto err_cleanup;
1318                         }
1319                 }
1320                 /* continue even if we didn't manage to submit all
1321                  * receive descs
1322                  */
1323                 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1324
1325                 if (cpts_register(&priv->pdev->dev, priv->cpts,
1326                                   priv->data.cpts_clock_mult,
1327                                   priv->data.cpts_clock_shift))
1328                         dev_err(priv->dev, "error registering cpts device\n");
1329
1330         }
1331
1332         /* Enable Interrupt pacing if configured */
1333         if (priv->coal_intvl != 0) {
1334                 struct ethtool_coalesce coal;
1335
1336                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1337                 cpsw_set_coalesce(ndev, &coal);
1338         }
1339
1340         cpdma_ctlr_start(priv->dma);
1341         cpsw_intr_enable(priv);
1342
1343         if (priv->data.dual_emac)
1344                 priv->slaves[priv->emac_port].open_stat = true;
1345         return 0;
1346
1347 err_cleanup:
1348         cpdma_ctlr_stop(priv->dma);
1349         for_each_slave(priv, cpsw_slave_stop, priv);
1350         pm_runtime_put_sync(&priv->pdev->dev);
1351         netif_carrier_off(priv->ndev);
1352         return ret;
1353 }
1354
1355 static int cpsw_ndo_stop(struct net_device *ndev)
1356 {
1357         struct cpsw_priv *priv = netdev_priv(ndev);
1358
1359         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1360         netif_stop_queue(priv->ndev);
1361         netif_carrier_off(priv->ndev);
1362
1363         if (cpsw_common_res_usage_state(priv) <= 1) {
1364                 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1365
1366                 napi_disable(&priv_sl0->napi_rx);
1367                 napi_disable(&priv_sl0->napi_tx);
1368                 cpts_unregister(priv->cpts);
1369                 cpsw_intr_disable(priv);
1370                 cpdma_ctlr_stop(priv->dma);
1371                 cpsw_ale_stop(priv->ale);
1372         }
1373         for_each_slave(priv, cpsw_slave_stop, priv);
1374         pm_runtime_put_sync(&priv->pdev->dev);
1375         if (priv->data.dual_emac)
1376                 priv->slaves[priv->emac_port].open_stat = false;
1377         return 0;
1378 }
1379
1380 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1381                                        struct net_device *ndev)
1382 {
1383         struct cpsw_priv *priv = netdev_priv(ndev);
1384         int ret;
1385
1386         ndev->trans_start = jiffies;
1387
1388         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1389                 cpsw_err(priv, tx_err, "packet pad failed\n");
1390                 ndev->stats.tx_dropped++;
1391                 return NETDEV_TX_OK;
1392         }
1393
1394         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1395                                 priv->cpts->tx_enable)
1396                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1397
1398         skb_tx_timestamp(skb);
1399
1400         ret = cpsw_tx_packet_submit(ndev, priv, skb);
1401         if (unlikely(ret != 0)) {
1402                 cpsw_err(priv, tx_err, "desc submit failed\n");
1403                 goto fail;
1404         }
1405
1406         /* If there is no more tx desc left free then we need to
1407          * tell the kernel to stop sending us tx frames.
1408          */
1409         if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1410                 netif_stop_queue(ndev);
1411
1412         return NETDEV_TX_OK;
1413 fail:
1414         ndev->stats.tx_dropped++;
1415         netif_stop_queue(ndev);
1416         return NETDEV_TX_BUSY;
1417 }
1418
1419 #ifdef CONFIG_TI_CPTS
1420
1421 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1422 {
1423         struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1424         u32 ts_en, seq_id;
1425
1426         if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1427                 slave_write(slave, 0, CPSW1_TS_CTL);
1428                 return;
1429         }
1430
1431         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1432         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1433
1434         if (priv->cpts->tx_enable)
1435                 ts_en |= CPSW_V1_TS_TX_EN;
1436
1437         if (priv->cpts->rx_enable)
1438                 ts_en |= CPSW_V1_TS_RX_EN;
1439
1440         slave_write(slave, ts_en, CPSW1_TS_CTL);
1441         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1442 }
1443
1444 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1445 {
1446         struct cpsw_slave *slave;
1447         u32 ctrl, mtype;
1448
1449         if (priv->data.dual_emac)
1450                 slave = &priv->slaves[priv->emac_port];
1451         else
1452                 slave = &priv->slaves[priv->data.active_slave];
1453
1454         ctrl = slave_read(slave, CPSW2_CONTROL);
1455         switch (priv->version) {
1456         case CPSW_VERSION_2:
1457                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1458
1459                 if (priv->cpts->tx_enable)
1460                         ctrl |= CTRL_V2_TX_TS_BITS;
1461
1462                 if (priv->cpts->rx_enable)
1463                         ctrl |= CTRL_V2_RX_TS_BITS;
1464                 break;
1465         case CPSW_VERSION_3:
1466         default:
1467                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1468
1469                 if (priv->cpts->tx_enable)
1470                         ctrl |= CTRL_V3_TX_TS_BITS;
1471
1472                 if (priv->cpts->rx_enable)
1473                         ctrl |= CTRL_V3_RX_TS_BITS;
1474                 break;
1475         }
1476
1477         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1478
1479         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1480         slave_write(slave, ctrl, CPSW2_CONTROL);
1481         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1482 }
1483
1484 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1485 {
1486         struct cpsw_priv *priv = netdev_priv(dev);
1487         struct cpts *cpts = priv->cpts;
1488         struct hwtstamp_config cfg;
1489
1490         if (priv->version != CPSW_VERSION_1 &&
1491             priv->version != CPSW_VERSION_2 &&
1492             priv->version != CPSW_VERSION_3)
1493                 return -EOPNOTSUPP;
1494
1495         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1496                 return -EFAULT;
1497
1498         /* reserved for future extensions */
1499         if (cfg.flags)
1500                 return -EINVAL;
1501
1502         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1503                 return -ERANGE;
1504
1505         switch (cfg.rx_filter) {
1506         case HWTSTAMP_FILTER_NONE:
1507                 cpts->rx_enable = 0;
1508                 break;
1509         case HWTSTAMP_FILTER_ALL:
1510         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1511         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1512         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1513                 return -ERANGE;
1514         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1515         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1516         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1517         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1518         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1519         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1520         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1521         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1522         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1523                 cpts->rx_enable = 1;
1524                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1525                 break;
1526         default:
1527                 return -ERANGE;
1528         }
1529
1530         cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1531
1532         switch (priv->version) {
1533         case CPSW_VERSION_1:
1534                 cpsw_hwtstamp_v1(priv);
1535                 break;
1536         case CPSW_VERSION_2:
1537         case CPSW_VERSION_3:
1538                 cpsw_hwtstamp_v2(priv);
1539                 break;
1540         default:
1541                 WARN_ON(1);
1542         }
1543
1544         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1545 }
1546
1547 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1548 {
1549         struct cpsw_priv *priv = netdev_priv(dev);
1550         struct cpts *cpts = priv->cpts;
1551         struct hwtstamp_config cfg;
1552
1553         if (priv->version != CPSW_VERSION_1 &&
1554             priv->version != CPSW_VERSION_2 &&
1555             priv->version != CPSW_VERSION_3)
1556                 return -EOPNOTSUPP;
1557
1558         cfg.flags = 0;
1559         cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1560         cfg.rx_filter = (cpts->rx_enable ?
1561                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1562
1563         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1564 }
1565
1566 #endif /*CONFIG_TI_CPTS*/
1567
1568 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1569 {
1570         struct cpsw_priv *priv = netdev_priv(dev);
1571         int slave_no = cpsw_slave_index(priv);
1572
1573         if (!netif_running(dev))
1574                 return -EINVAL;
1575
1576         switch (cmd) {
1577 #ifdef CONFIG_TI_CPTS
1578         case SIOCSHWTSTAMP:
1579                 return cpsw_hwtstamp_set(dev, req);
1580         case SIOCGHWTSTAMP:
1581                 return cpsw_hwtstamp_get(dev, req);
1582 #endif
1583         }
1584
1585         if (!priv->slaves[slave_no].phy)
1586                 return -EOPNOTSUPP;
1587         return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1588 }
1589
1590 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1591 {
1592         struct cpsw_priv *priv = netdev_priv(ndev);
1593
1594         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1595         ndev->stats.tx_errors++;
1596         cpsw_intr_disable(priv);
1597         cpdma_chan_stop(priv->txch);
1598         cpdma_chan_start(priv->txch);
1599         cpsw_intr_enable(priv);
1600 }
1601
1602 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1603 {
1604         struct cpsw_priv *priv = netdev_priv(ndev);
1605         struct sockaddr *addr = (struct sockaddr *)p;
1606         int flags = 0;
1607         u16 vid = 0;
1608
1609         if (!is_valid_ether_addr(addr->sa_data))
1610                 return -EADDRNOTAVAIL;
1611
1612         if (priv->data.dual_emac) {
1613                 vid = priv->slaves[priv->emac_port].port_vlan;
1614                 flags = ALE_VLAN;
1615         }
1616
1617         cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1618                            flags, vid);
1619         cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1620                            flags, vid);
1621
1622         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1623         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1624         for_each_slave(priv, cpsw_set_slave_mac, priv);
1625
1626         return 0;
1627 }
1628
1629 #ifdef CONFIG_NET_POLL_CONTROLLER
1630 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1631 {
1632         struct cpsw_priv *priv = netdev_priv(ndev);
1633
1634         cpsw_intr_disable(priv);
1635         cpsw_rx_interrupt(priv->irqs_table[0], priv);
1636         cpsw_tx_interrupt(priv->irqs_table[1], priv);
1637         cpsw_intr_enable(priv);
1638 }
1639 #endif
1640
1641 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1642                                 unsigned short vid)
1643 {
1644         int ret;
1645         int unreg_mcast_mask = 0;
1646         u32 port_mask;
1647
1648         if (priv->data.dual_emac) {
1649                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1650
1651                 if (priv->ndev->flags & IFF_ALLMULTI)
1652                         unreg_mcast_mask = port_mask;
1653         } else {
1654                 port_mask = ALE_ALL_PORTS;
1655
1656                 if (priv->ndev->flags & IFF_ALLMULTI)
1657                         unreg_mcast_mask = ALE_ALL_PORTS;
1658                 else
1659                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1660         }
1661
1662         ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1663                                 unreg_mcast_mask << priv->host_port);
1664         if (ret != 0)
1665                 return ret;
1666
1667         ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1668                                  priv->host_port, ALE_VLAN, vid);
1669         if (ret != 0)
1670                 goto clean_vid;
1671
1672         ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1673                                  port_mask, ALE_VLAN, vid, 0);
1674         if (ret != 0)
1675                 goto clean_vlan_ucast;
1676         return 0;
1677
1678 clean_vlan_ucast:
1679         cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1680                             priv->host_port, ALE_VLAN, vid);
1681 clean_vid:
1682         cpsw_ale_del_vlan(priv->ale, vid, 0);
1683         return ret;
1684 }
1685
1686 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1687                                     __be16 proto, u16 vid)
1688 {
1689         struct cpsw_priv *priv = netdev_priv(ndev);
1690
1691         if (vid == priv->data.default_vlan)
1692                 return 0;
1693
1694         if (priv->data.dual_emac) {
1695                 /* In dual EMAC, reserved VLAN id should not be used for
1696                  * creating VLAN interfaces as this can break the dual
1697                  * EMAC port separation
1698                  */
1699                 int i;
1700
1701                 for (i = 0; i < priv->data.slaves; i++) {
1702                         if (vid == priv->slaves[i].port_vlan)
1703                                 return -EINVAL;
1704                 }
1705         }
1706
1707         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1708         return cpsw_add_vlan_ale_entry(priv, vid);
1709 }
1710
1711 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1712                                      __be16 proto, u16 vid)
1713 {
1714         struct cpsw_priv *priv = netdev_priv(ndev);
1715         int ret;
1716
1717         if (vid == priv->data.default_vlan)
1718                 return 0;
1719
1720         if (priv->data.dual_emac) {
1721                 int i;
1722
1723                 for (i = 0; i < priv->data.slaves; i++) {
1724                         if (vid == priv->slaves[i].port_vlan)
1725                                 return -EINVAL;
1726                 }
1727         }
1728
1729         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1730         ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1731         if (ret != 0)
1732                 return ret;
1733
1734         ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1735                                  priv->host_port, ALE_VLAN, vid);
1736         if (ret != 0)
1737                 return ret;
1738
1739         return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1740                                   0, ALE_VLAN, vid);
1741 }
1742
1743 static const struct net_device_ops cpsw_netdev_ops = {
1744         .ndo_open               = cpsw_ndo_open,
1745         .ndo_stop               = cpsw_ndo_stop,
1746         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1747         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1748         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1749         .ndo_validate_addr      = eth_validate_addr,
1750         .ndo_change_mtu         = eth_change_mtu,
1751         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1752         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1753 #ifdef CONFIG_NET_POLL_CONTROLLER
1754         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1755 #endif
1756         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1757         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1758 };
1759
1760 static int cpsw_get_regs_len(struct net_device *ndev)
1761 {
1762         struct cpsw_priv *priv = netdev_priv(ndev);
1763
1764         return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1765 }
1766
1767 static void cpsw_get_regs(struct net_device *ndev,
1768                           struct ethtool_regs *regs, void *p)
1769 {
1770         struct cpsw_priv *priv = netdev_priv(ndev);
1771         u32 *reg = p;
1772
1773         /* update CPSW IP version */
1774         regs->version = priv->version;
1775
1776         cpsw_ale_dump(priv->ale, reg);
1777 }
1778
1779 static void cpsw_get_drvinfo(struct net_device *ndev,
1780                              struct ethtool_drvinfo *info)
1781 {
1782         struct cpsw_priv *priv = netdev_priv(ndev);
1783
1784         strlcpy(info->driver, "cpsw", sizeof(info->driver));
1785         strlcpy(info->version, "1.0", sizeof(info->version));
1786         strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1787 }
1788
1789 static u32 cpsw_get_msglevel(struct net_device *ndev)
1790 {
1791         struct cpsw_priv *priv = netdev_priv(ndev);
1792         return priv->msg_enable;
1793 }
1794
1795 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1796 {
1797         struct cpsw_priv *priv = netdev_priv(ndev);
1798         priv->msg_enable = value;
1799 }
1800
1801 static int cpsw_get_ts_info(struct net_device *ndev,
1802                             struct ethtool_ts_info *info)
1803 {
1804 #ifdef CONFIG_TI_CPTS
1805         struct cpsw_priv *priv = netdev_priv(ndev);
1806
1807         info->so_timestamping =
1808                 SOF_TIMESTAMPING_TX_HARDWARE |
1809                 SOF_TIMESTAMPING_TX_SOFTWARE |
1810                 SOF_TIMESTAMPING_RX_HARDWARE |
1811                 SOF_TIMESTAMPING_RX_SOFTWARE |
1812                 SOF_TIMESTAMPING_SOFTWARE |
1813                 SOF_TIMESTAMPING_RAW_HARDWARE;
1814         info->phc_index = priv->cpts->phc_index;
1815         info->tx_types =
1816                 (1 << HWTSTAMP_TX_OFF) |
1817                 (1 << HWTSTAMP_TX_ON);
1818         info->rx_filters =
1819                 (1 << HWTSTAMP_FILTER_NONE) |
1820                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1821 #else
1822         info->so_timestamping =
1823                 SOF_TIMESTAMPING_TX_SOFTWARE |
1824                 SOF_TIMESTAMPING_RX_SOFTWARE |
1825                 SOF_TIMESTAMPING_SOFTWARE;
1826         info->phc_index = -1;
1827         info->tx_types = 0;
1828         info->rx_filters = 0;
1829 #endif
1830         return 0;
1831 }
1832
1833 static int cpsw_get_settings(struct net_device *ndev,
1834                              struct ethtool_cmd *ecmd)
1835 {
1836         struct cpsw_priv *priv = netdev_priv(ndev);
1837         int slave_no = cpsw_slave_index(priv);
1838
1839         if (priv->slaves[slave_no].phy)
1840                 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1841         else
1842                 return -EOPNOTSUPP;
1843 }
1844
1845 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1846 {
1847         struct cpsw_priv *priv = netdev_priv(ndev);
1848         int slave_no = cpsw_slave_index(priv);
1849
1850         if (priv->slaves[slave_no].phy)
1851                 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1852         else
1853                 return -EOPNOTSUPP;
1854 }
1855
1856 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1857 {
1858         struct cpsw_priv *priv = netdev_priv(ndev);
1859         int slave_no = cpsw_slave_index(priv);
1860
1861         wol->supported = 0;
1862         wol->wolopts = 0;
1863
1864         if (priv->slaves[slave_no].phy)
1865                 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1866 }
1867
1868 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1869 {
1870         struct cpsw_priv *priv = netdev_priv(ndev);
1871         int slave_no = cpsw_slave_index(priv);
1872
1873         if (priv->slaves[slave_no].phy)
1874                 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1875         else
1876                 return -EOPNOTSUPP;
1877 }
1878
1879 static void cpsw_get_pauseparam(struct net_device *ndev,
1880                                 struct ethtool_pauseparam *pause)
1881 {
1882         struct cpsw_priv *priv = netdev_priv(ndev);
1883
1884         pause->autoneg = AUTONEG_DISABLE;
1885         pause->rx_pause = priv->rx_pause ? true : false;
1886         pause->tx_pause = priv->tx_pause ? true : false;
1887 }
1888
1889 static int cpsw_set_pauseparam(struct net_device *ndev,
1890                                struct ethtool_pauseparam *pause)
1891 {
1892         struct cpsw_priv *priv = netdev_priv(ndev);
1893         bool link;
1894
1895         priv->rx_pause = pause->rx_pause ? true : false;
1896         priv->tx_pause = pause->tx_pause ? true : false;
1897
1898         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1899
1900         return 0;
1901 }
1902
1903 static const struct ethtool_ops cpsw_ethtool_ops = {
1904         .get_drvinfo    = cpsw_get_drvinfo,
1905         .get_msglevel   = cpsw_get_msglevel,
1906         .set_msglevel   = cpsw_set_msglevel,
1907         .get_link       = ethtool_op_get_link,
1908         .get_ts_info    = cpsw_get_ts_info,
1909         .get_settings   = cpsw_get_settings,
1910         .set_settings   = cpsw_set_settings,
1911         .get_coalesce   = cpsw_get_coalesce,
1912         .set_coalesce   = cpsw_set_coalesce,
1913         .get_sset_count         = cpsw_get_sset_count,
1914         .get_strings            = cpsw_get_strings,
1915         .get_ethtool_stats      = cpsw_get_ethtool_stats,
1916         .get_pauseparam         = cpsw_get_pauseparam,
1917         .set_pauseparam         = cpsw_set_pauseparam,
1918         .get_wol        = cpsw_get_wol,
1919         .set_wol        = cpsw_set_wol,
1920         .get_regs_len   = cpsw_get_regs_len,
1921         .get_regs       = cpsw_get_regs,
1922 };
1923
1924 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1925                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
1926 {
1927         void __iomem            *regs = priv->regs;
1928         int                     slave_num = slave->slave_num;
1929         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1930
1931         slave->data     = data;
1932         slave->regs     = regs + slave_reg_ofs;
1933         slave->sliver   = regs + sliver_reg_ofs;
1934         slave->port_vlan = data->dual_emac_res_vlan;
1935 }
1936
1937 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1938                          struct platform_device *pdev)
1939 {
1940         struct device_node *node = pdev->dev.of_node;
1941         struct device_node *slave_node;
1942         int i = 0, ret;
1943         u32 prop;
1944
1945         if (!node)
1946                 return -EINVAL;
1947
1948         if (of_property_read_u32(node, "slaves", &prop)) {
1949                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1950                 return -EINVAL;
1951         }
1952         data->slaves = prop;
1953
1954         if (of_property_read_u32(node, "active_slave", &prop)) {
1955                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1956                 return -EINVAL;
1957         }
1958         data->active_slave = prop;
1959
1960         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1961                 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1962                 return -EINVAL;
1963         }
1964         data->cpts_clock_mult = prop;
1965
1966         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1967                 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1968                 return -EINVAL;
1969         }
1970         data->cpts_clock_shift = prop;
1971
1972         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1973                                         * sizeof(struct cpsw_slave_data),
1974                                         GFP_KERNEL);
1975         if (!data->slave_data)
1976                 return -ENOMEM;
1977
1978         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1979                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
1980                 return -EINVAL;
1981         }
1982         data->channels = prop;
1983
1984         if (of_property_read_u32(node, "ale_entries", &prop)) {
1985                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
1986                 return -EINVAL;
1987         }
1988         data->ale_entries = prop;
1989
1990         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1991                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
1992                 return -EINVAL;
1993         }
1994         data->bd_ram_size = prop;
1995
1996         if (of_property_read_u32(node, "rx_descs", &prop)) {
1997                 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
1998                 return -EINVAL;
1999         }
2000         data->rx_descs = prop;
2001
2002         if (of_property_read_u32(node, "mac_control", &prop)) {
2003                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2004                 return -EINVAL;
2005         }
2006         data->mac_control = prop;
2007
2008         if (of_property_read_bool(node, "dual_emac"))
2009                 data->dual_emac = 1;
2010
2011         /*
2012          * Populate all the child nodes here...
2013          */
2014         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2015         /* We do not want to force this, as in some cases may not have child */
2016         if (ret)
2017                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2018
2019         for_each_child_of_node(node, slave_node) {
2020                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2021                 const void *mac_addr = NULL;
2022                 u32 phyid;
2023                 int lenp;
2024                 const __be32 *parp;
2025                 struct device_node *mdio_node;
2026                 struct platform_device *mdio;
2027
2028                 /* This is no slave child node, continue */
2029                 if (strcmp(slave_node->name, "slave"))
2030                         continue;
2031
2032                 parp = of_get_property(slave_node, "phy_id", &lenp);
2033                 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
2034                         dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
2035                         goto no_phy_slave;
2036                 }
2037                 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2038                 phyid = be32_to_cpup(parp+1);
2039                 mdio = of_find_device_by_node(mdio_node);
2040                 of_node_put(mdio_node);
2041                 if (!mdio) {
2042                         dev_err(&pdev->dev, "Missing mdio platform device\n");
2043                         return -EINVAL;
2044                 }
2045                 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2046                          PHY_ID_FMT, mdio->name, phyid);
2047
2048                 slave_data->phy_if = of_get_phy_mode(slave_node);
2049                 if (slave_data->phy_if < 0) {
2050                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2051                                 i);
2052                         return slave_data->phy_if;
2053                 }
2054
2055 no_phy_slave:
2056                 mac_addr = of_get_mac_address(slave_node);
2057                 if (mac_addr) {
2058                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2059                 } else {
2060                         ret = ti_cm_get_macid(&pdev->dev, i,
2061                                               slave_data->mac_addr);
2062                         if (ret)
2063                                 return ret;
2064                 }
2065                 if (data->dual_emac) {
2066                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2067                                                  &prop)) {
2068                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2069                                 slave_data->dual_emac_res_vlan = i+1;
2070                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2071                                         slave_data->dual_emac_res_vlan, i);
2072                         } else {
2073                                 slave_data->dual_emac_res_vlan = prop;
2074                         }
2075                 }
2076
2077                 i++;
2078                 if (i == data->slaves)
2079                         break;
2080         }
2081
2082         return 0;
2083 }
2084
2085 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2086                                 struct cpsw_priv *priv)
2087 {
2088         struct cpsw_platform_data       *data = &priv->data;
2089         struct net_device               *ndev;
2090         struct cpsw_priv                *priv_sl2;
2091         int ret = 0, i;
2092
2093         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2094         if (!ndev) {
2095                 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2096                 return -ENOMEM;
2097         }
2098
2099         priv_sl2 = netdev_priv(ndev);
2100         spin_lock_init(&priv_sl2->lock);
2101         priv_sl2->data = *data;
2102         priv_sl2->pdev = pdev;
2103         priv_sl2->ndev = ndev;
2104         priv_sl2->dev  = &ndev->dev;
2105         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2106         priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2107
2108         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2109                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2110                         ETH_ALEN);
2111                 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2112         } else {
2113                 random_ether_addr(priv_sl2->mac_addr);
2114                 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2115         }
2116         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2117
2118         priv_sl2->slaves = priv->slaves;
2119         priv_sl2->clk = priv->clk;
2120
2121         priv_sl2->coal_intvl = 0;
2122         priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2123
2124         priv_sl2->regs = priv->regs;
2125         priv_sl2->host_port = priv->host_port;
2126         priv_sl2->host_port_regs = priv->host_port_regs;
2127         priv_sl2->wr_regs = priv->wr_regs;
2128         priv_sl2->hw_stats = priv->hw_stats;
2129         priv_sl2->dma = priv->dma;
2130         priv_sl2->txch = priv->txch;
2131         priv_sl2->rxch = priv->rxch;
2132         priv_sl2->ale = priv->ale;
2133         priv_sl2->emac_port = 1;
2134         priv->slaves[1].ndev = ndev;
2135         priv_sl2->cpts = priv->cpts;
2136         priv_sl2->version = priv->version;
2137
2138         for (i = 0; i < priv->num_irqs; i++) {
2139                 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2140                 priv_sl2->num_irqs = priv->num_irqs;
2141         }
2142         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2143
2144         ndev->netdev_ops = &cpsw_netdev_ops;
2145         ndev->ethtool_ops = &cpsw_ethtool_ops;
2146
2147         /* register the network device */
2148         SET_NETDEV_DEV(ndev, &pdev->dev);
2149         ret = register_netdev(ndev);
2150         if (ret) {
2151                 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2152                 free_netdev(ndev);
2153                 ret = -ENODEV;
2154         }
2155
2156         return ret;
2157 }
2158
2159 #define CPSW_QUIRK_IRQ          BIT(0)
2160
2161 static struct platform_device_id cpsw_devtype[] = {
2162         {
2163                 /* keep it for existing comaptibles */
2164                 .name = "cpsw",
2165                 .driver_data = CPSW_QUIRK_IRQ,
2166         }, {
2167                 .name = "am335x-cpsw",
2168                 .driver_data = CPSW_QUIRK_IRQ,
2169         }, {
2170                 .name = "am4372-cpsw",
2171                 .driver_data = 0,
2172         }, {
2173                 .name = "dra7-cpsw",
2174                 .driver_data = 0,
2175         }, {
2176                 /* sentinel */
2177         }
2178 };
2179 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2180
2181 enum ti_cpsw_type {
2182         CPSW = 0,
2183         AM335X_CPSW,
2184         AM4372_CPSW,
2185         DRA7_CPSW,
2186 };
2187
2188 static const struct of_device_id cpsw_of_mtable[] = {
2189         { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2190         { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2191         { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2192         { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2193         { /* sentinel */ },
2194 };
2195 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2196
2197 static int cpsw_probe(struct platform_device *pdev)
2198 {
2199         struct cpsw_platform_data       *data;
2200         struct net_device               *ndev;
2201         struct cpsw_priv                *priv;
2202         struct cpdma_params             dma_params;
2203         struct cpsw_ale_params          ale_params;
2204         void __iomem                    *ss_regs;
2205         struct resource                 *res, *ss_res;
2206         const struct of_device_id       *of_id;
2207         struct gpio_descs               *mode;
2208         u32 slave_offset, sliver_offset, slave_size;
2209         int ret = 0, i;
2210         int irq;
2211
2212         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2213         if (!ndev) {
2214                 dev_err(&pdev->dev, "error allocating net_device\n");
2215                 return -ENOMEM;
2216         }
2217
2218         platform_set_drvdata(pdev, ndev);
2219         priv = netdev_priv(ndev);
2220         spin_lock_init(&priv->lock);
2221         priv->pdev = pdev;
2222         priv->ndev = ndev;
2223         priv->dev  = &ndev->dev;
2224         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2225         priv->rx_packet_max = max(rx_packet_max, 128);
2226         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2227         if (!priv->cpts) {
2228                 dev_err(&pdev->dev, "error allocating cpts\n");
2229                 ret = -ENOMEM;
2230                 goto clean_ndev_ret;
2231         }
2232
2233         mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2234         if (IS_ERR(mode)) {
2235                 ret = PTR_ERR(mode);
2236                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2237                 goto clean_ndev_ret;
2238         }
2239
2240         /*
2241          * This may be required here for child devices.
2242          */
2243         pm_runtime_enable(&pdev->dev);
2244
2245         /* Select default pin state */
2246         pinctrl_pm_select_default_state(&pdev->dev);
2247
2248         if (cpsw_probe_dt(&priv->data, pdev)) {
2249                 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2250                 ret = -ENODEV;
2251                 goto clean_runtime_disable_ret;
2252         }
2253         data = &priv->data;
2254
2255         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2256                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2257                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2258         } else {
2259                 eth_random_addr(priv->mac_addr);
2260                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2261         }
2262
2263         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2264
2265         priv->slaves = devm_kzalloc(&pdev->dev,
2266                                     sizeof(struct cpsw_slave) * data->slaves,
2267                                     GFP_KERNEL);
2268         if (!priv->slaves) {
2269                 ret = -ENOMEM;
2270                 goto clean_runtime_disable_ret;
2271         }
2272         for (i = 0; i < data->slaves; i++)
2273                 priv->slaves[i].slave_num = i;
2274
2275         priv->slaves[0].ndev = ndev;
2276         priv->emac_port = 0;
2277
2278         priv->clk = devm_clk_get(&pdev->dev, "fck");
2279         if (IS_ERR(priv->clk)) {
2280                 dev_err(priv->dev, "fck is not found\n");
2281                 ret = -ENODEV;
2282                 goto clean_runtime_disable_ret;
2283         }
2284         priv->coal_intvl = 0;
2285         priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2286
2287         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2288         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2289         if (IS_ERR(ss_regs)) {
2290                 ret = PTR_ERR(ss_regs);
2291                 goto clean_runtime_disable_ret;
2292         }
2293         priv->regs = ss_regs;
2294         priv->host_port = HOST_PORT_NUM;
2295
2296         /* Need to enable clocks with runtime PM api to access module
2297          * registers
2298          */
2299         pm_runtime_get_sync(&pdev->dev);
2300         priv->version = readl(&priv->regs->id_ver);
2301         pm_runtime_put_sync(&pdev->dev);
2302
2303         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2304         priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2305         if (IS_ERR(priv->wr_regs)) {
2306                 ret = PTR_ERR(priv->wr_regs);
2307                 goto clean_runtime_disable_ret;
2308         }
2309
2310         memset(&dma_params, 0, sizeof(dma_params));
2311         memset(&ale_params, 0, sizeof(ale_params));
2312
2313         switch (priv->version) {
2314         case CPSW_VERSION_1:
2315                 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2316                 priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2317                 priv->hw_stats       = ss_regs + CPSW1_HW_STATS;
2318                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2319                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2320                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2321                 slave_offset         = CPSW1_SLAVE_OFFSET;
2322                 slave_size           = CPSW1_SLAVE_SIZE;
2323                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2324                 dma_params.desc_mem_phys = 0;
2325                 break;
2326         case CPSW_VERSION_2:
2327         case CPSW_VERSION_3:
2328         case CPSW_VERSION_4:
2329                 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2330                 priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2331                 priv->hw_stats       = ss_regs + CPSW2_HW_STATS;
2332                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2333                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2334                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2335                 slave_offset         = CPSW2_SLAVE_OFFSET;
2336                 slave_size           = CPSW2_SLAVE_SIZE;
2337                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2338                 dma_params.desc_mem_phys =
2339                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2340                 break;
2341         default:
2342                 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2343                 ret = -ENODEV;
2344                 goto clean_runtime_disable_ret;
2345         }
2346         for (i = 0; i < priv->data.slaves; i++) {
2347                 struct cpsw_slave *slave = &priv->slaves[i];
2348                 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2349                 slave_offset  += slave_size;
2350                 sliver_offset += SLIVER_SIZE;
2351         }
2352
2353         dma_params.dev          = &pdev->dev;
2354         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2355         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2356         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2357         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2358         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2359
2360         dma_params.num_chan             = data->channels;
2361         dma_params.has_soft_reset       = true;
2362         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2363         dma_params.desc_mem_size        = data->bd_ram_size;
2364         dma_params.desc_align           = 16;
2365         dma_params.has_ext_regs         = true;
2366         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2367
2368         priv->dma = cpdma_ctlr_create(&dma_params);
2369         if (!priv->dma) {
2370                 dev_err(priv->dev, "error initializing dma\n");
2371                 ret = -ENOMEM;
2372                 goto clean_runtime_disable_ret;
2373         }
2374
2375         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2376                                        cpsw_tx_handler);
2377         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2378                                        cpsw_rx_handler);
2379
2380         if (WARN_ON(!priv->txch || !priv->rxch)) {
2381                 dev_err(priv->dev, "error initializing dma channels\n");
2382                 ret = -ENOMEM;
2383                 goto clean_dma_ret;
2384         }
2385
2386         ale_params.dev                  = &ndev->dev;
2387         ale_params.ale_ageout           = ale_ageout;
2388         ale_params.ale_entries          = data->ale_entries;
2389         ale_params.ale_ports            = data->slaves;
2390
2391         priv->ale = cpsw_ale_create(&ale_params);
2392         if (!priv->ale) {
2393                 dev_err(priv->dev, "error initializing ale engine\n");
2394                 ret = -ENODEV;
2395                 goto clean_dma_ret;
2396         }
2397
2398         ndev->irq = platform_get_irq(pdev, 1);
2399         if (ndev->irq < 0) {
2400                 dev_err(priv->dev, "error getting irq resource\n");
2401                 ret = -ENOENT;
2402                 goto clean_ale_ret;
2403         }
2404
2405         of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2406         if (of_id) {
2407                 pdev->id_entry = of_id->data;
2408                 if (pdev->id_entry->driver_data)
2409                         priv->quirk_irq = true;
2410         }
2411
2412         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2413          * MISC IRQs which are always kept disabled with this driver so
2414          * we will not request them.
2415          *
2416          * If anyone wants to implement support for those, make sure to
2417          * first request and append them to irqs_table array.
2418          */
2419
2420         /* RX IRQ */
2421         irq = platform_get_irq(pdev, 1);
2422         if (irq < 0)
2423                 goto clean_ale_ret;
2424
2425         priv->irqs_table[0] = irq;
2426         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2427                                0, dev_name(&pdev->dev), priv);
2428         if (ret < 0) {
2429                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2430                 goto clean_ale_ret;
2431         }
2432
2433         /* TX IRQ */
2434         irq = platform_get_irq(pdev, 2);
2435         if (irq < 0)
2436                 goto clean_ale_ret;
2437
2438         priv->irqs_table[1] = irq;
2439         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2440                                0, dev_name(&pdev->dev), priv);
2441         if (ret < 0) {
2442                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2443                 goto clean_ale_ret;
2444         }
2445         priv->num_irqs = 2;
2446
2447         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2448
2449         ndev->netdev_ops = &cpsw_netdev_ops;
2450         ndev->ethtool_ops = &cpsw_ethtool_ops;
2451         netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
2452         netif_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
2453
2454         /* register the network device */
2455         SET_NETDEV_DEV(ndev, &pdev->dev);
2456         ret = register_netdev(ndev);
2457         if (ret) {
2458                 dev_err(priv->dev, "error registering net device\n");
2459                 ret = -ENODEV;
2460                 goto clean_ale_ret;
2461         }
2462
2463         cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2464                     &ss_res->start, ndev->irq);
2465
2466         if (priv->data.dual_emac) {
2467                 ret = cpsw_probe_dual_emac(pdev, priv);
2468                 if (ret) {
2469                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2470                         goto clean_ale_ret;
2471                 }
2472         }
2473
2474         return 0;
2475
2476 clean_ale_ret:
2477         cpsw_ale_destroy(priv->ale);
2478 clean_dma_ret:
2479         cpdma_chan_destroy(priv->txch);
2480         cpdma_chan_destroy(priv->rxch);
2481         cpdma_ctlr_destroy(priv->dma);
2482 clean_runtime_disable_ret:
2483         pm_runtime_disable(&pdev->dev);
2484 clean_ndev_ret:
2485         free_netdev(priv->ndev);
2486         return ret;
2487 }
2488
2489 static int cpsw_remove_child_device(struct device *dev, void *c)
2490 {
2491         struct platform_device *pdev = to_platform_device(dev);
2492
2493         of_device_unregister(pdev);
2494
2495         return 0;
2496 }
2497
2498 static int cpsw_remove(struct platform_device *pdev)
2499 {
2500         struct net_device *ndev = platform_get_drvdata(pdev);
2501         struct cpsw_priv *priv = netdev_priv(ndev);
2502
2503         if (priv->data.dual_emac)
2504                 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2505         unregister_netdev(ndev);
2506
2507         cpsw_ale_destroy(priv->ale);
2508         cpdma_chan_destroy(priv->txch);
2509         cpdma_chan_destroy(priv->rxch);
2510         cpdma_ctlr_destroy(priv->dma);
2511         pm_runtime_disable(&pdev->dev);
2512         device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
2513         if (priv->data.dual_emac)
2514                 free_netdev(cpsw_get_slave_ndev(priv, 1));
2515         free_netdev(ndev);
2516         return 0;
2517 }
2518
2519 #ifdef CONFIG_PM_SLEEP
2520 static int cpsw_suspend(struct device *dev)
2521 {
2522         struct platform_device  *pdev = to_platform_device(dev);
2523         struct net_device       *ndev = platform_get_drvdata(pdev);
2524         struct cpsw_priv        *priv = netdev_priv(ndev);
2525
2526         if (priv->data.dual_emac) {
2527                 int i;
2528
2529                 for (i = 0; i < priv->data.slaves; i++) {
2530                         if (netif_running(priv->slaves[i].ndev))
2531                                 cpsw_ndo_stop(priv->slaves[i].ndev);
2532                         soft_reset_slave(priv->slaves + i);
2533                 }
2534         } else {
2535                 if (netif_running(ndev))
2536                         cpsw_ndo_stop(ndev);
2537                 for_each_slave(priv, soft_reset_slave);
2538         }
2539
2540         pm_runtime_put_sync(&pdev->dev);
2541
2542         /* Select sleep pin state */
2543         pinctrl_pm_select_sleep_state(&pdev->dev);
2544
2545         return 0;
2546 }
2547
2548 static int cpsw_resume(struct device *dev)
2549 {
2550         struct platform_device  *pdev = to_platform_device(dev);
2551         struct net_device       *ndev = platform_get_drvdata(pdev);
2552         struct cpsw_priv        *priv = netdev_priv(ndev);
2553
2554         pm_runtime_get_sync(&pdev->dev);
2555
2556         /* Select default pin state */
2557         pinctrl_pm_select_default_state(&pdev->dev);
2558
2559         if (priv->data.dual_emac) {
2560                 int i;
2561
2562                 for (i = 0; i < priv->data.slaves; i++) {
2563                         if (netif_running(priv->slaves[i].ndev))
2564                                 cpsw_ndo_open(priv->slaves[i].ndev);
2565                 }
2566         } else {
2567                 if (netif_running(ndev))
2568                         cpsw_ndo_open(ndev);
2569         }
2570         return 0;
2571 }
2572 #endif
2573
2574 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2575
2576 static struct platform_driver cpsw_driver = {
2577         .driver = {
2578                 .name    = "cpsw",
2579                 .pm      = &cpsw_pm_ops,
2580                 .of_match_table = cpsw_of_mtable,
2581         },
2582         .probe = cpsw_probe,
2583         .remove = cpsw_remove,
2584 };
2585
2586 static int __init cpsw_init(void)
2587 {
2588         return platform_driver_register(&cpsw_driver);
2589 }
2590 late_initcall(cpsw_init);
2591
2592 static void __exit cpsw_exit(void)
2593 {
2594         platform_driver_unregister(&cpsw_driver);
2595 }
2596 module_exit(cpsw_exit);
2597
2598 MODULE_LICENSE("GPL");
2599 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2600 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2601 MODULE_DESCRIPTION("TI CPSW Ethernet driver");