drivers/net/wireless/intel/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2016 Intel Deutschland GmbH
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of version 2 of the GNU General Public License as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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  22  * along with this program; if not, write to the Free Software
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  27  * in the file called COPYING.
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  29  * Contact Information:
  30  *  Intel Linux Wireless <linuxwifi@intel.com>
  31  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  32  *
  33  * BSD LICENSE
  34  *
  35  * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
  36  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  37  * Copyright(c) 2016 Intel Deutschland GmbH
  38  * All rights reserved.
  39  *
  40  * Redistribution and use in source and binary forms, with or without
  41  * modification, are permitted provided that the following conditions
  42  * are met:
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  44  *  * Redistributions of source code must retain the above copyright
  45  *    notice, this list of conditions and the following disclaimer.
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  49  *    distribution.
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  51  *    contributors may be used to endorse or promote products derived
  52  *    from this software without specific prior written permission.
  53  *
  54  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  55  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  56  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  57  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  58  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  61  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  62  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  63  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  64  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  65  *
  66  *****************************************************************************/
  67 #include <linux/pci.h>
  68 #include <linux/pci-aspm.h>
  69 #include <linux/interrupt.h>
  70 #include <linux/debugfs.h>
  71 #include <linux/sched.h>
  72 #include <linux/bitops.h>
  73 #include <linux/gfp.h>
  74 #include <linux/vmalloc.h>
  75 #include <linux/pm_runtime.h>
  76
  77 #include "iwl-drv.h"
  78 #include "iwl-trans.h"
  79 #include "iwl-csr.h"
  80 #include "iwl-prph.h"
  81 #include "iwl-scd.h"
  82 #include "iwl-agn-hw.h"
  83 #include "iwl-fw-error-dump.h"
  84 #include "internal.h"
  85 #include "iwl-fh.h"
  86
  87 /* extended range in FW SRAM */
  88 #define IWL_FW_MEM_EXTENDED_START       0x40000
  89 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  90
  91 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
  92 {
  93         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  94
  95         if (!trans_pcie->fw_mon_page)
  96                 return;
  97
  98         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
  99                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
 100         __free_pages(trans_pcie->fw_mon_page,
 101                      get_order(trans_pcie->fw_mon_size));
 102         trans_pcie->fw_mon_page = NULL;
 103         trans_pcie->fw_mon_phys = 0;
 104         trans_pcie->fw_mon_size = 0;
 105 }
 106
 107 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 108 {
 109         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 110         struct page *page = NULL;
 111         dma_addr_t phys;
 112         u32 size = 0;
 113         u8 power;
 114
 115         if (!max_power) {
 116                 /* default max_power is maximum */
 117                 max_power = 26;
 118         } else {
 119                 max_power += 11;
 120         }
 121
 122         if (WARN(max_power > 26,
 123                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 124                  max_power))
 125                 return;
 126
 127         if (trans_pcie->fw_mon_page) {
 128                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 129                                            trans_pcie->fw_mon_size,
 130                                            DMA_FROM_DEVICE);
 131                 return;
 132         }
 133
 134         phys = 0;
 135         for (power = max_power; power >= 11; power--) {
 136                 int order;
 137
 138                 size = BIT(power);
 139                 order = get_order(size);
 140                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 141                                    order);
 142                 if (!page)
 143                         continue;
 144
 145                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 146                                     DMA_FROM_DEVICE);
 147                 if (dma_mapping_error(trans->dev, phys)) {
 148                         __free_pages(page, order);
 149                         page = NULL;
 150                         continue;
 151                 }
 152                 IWL_INFO(trans,
 153                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 154                          size, order);
 155                 break;
 156         }
 157
 158         if (WARN_ON_ONCE(!page))
 159                 return;
 160
 161         if (power != max_power)
 162                 IWL_ERR(trans,
 163                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 164                         (unsigned long)BIT(power - 10),
 165                         (unsigned long)BIT(max_power - 10));
 166
 167         trans_pcie->fw_mon_page = page;
 168         trans_pcie->fw_mon_phys = phys;
 169         trans_pcie->fw_mon_size = size;
 170 }
 171
 172 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 173 {
 174         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 175                     ((reg & 0x0000ffff) | (2 << 28)));
 176         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 177 }
 178
 179 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 180 {
 181         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 182         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 183                     ((reg & 0x0000ffff) | (3 << 28)));
 184 }
 185
 186 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 187 {
 188         if (trans->cfg->apmg_not_supported)
 189                 return;
 190
 191         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 192                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 193                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 194                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 195         else
 196                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 197                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 198                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 199 }
 200
 201 /* PCI registers */
 202 #define PCI_CFG_RETRY_TIMEOUT   0x041
 203
 204 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 205 {
 206         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 207         u16 lctl;
 208         u16 cap;
 209
 210         /*
 211          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 212          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 213          * If so (likely), disable L0S, so device moves directly L0->L1;
 214          *    costs negligible amount of power savings.
 215          * If not (unlikely), enable L0S, so there is at least some
 216          *    power savings, even without L1.
 217          */
 218         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 219         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 220                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 221         else
 222                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 223         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 224
 225         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 226         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 227         dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
 228                  (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 229                  trans->ltr_enabled ? "En" : "Dis");
 230 }
 231
 232 /*
 233  * Start up NIC's basic functionality after it has been reset
 234  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 235  * NOTE:  This does not load uCode nor start the embedded processor
 236  */
 237 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 238 {
 239         int ret = 0;
 240         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 241
 242         /*
 243          * Use "set_bit" below rather than "write", to preserve any hardware
 244          * bits already set by default after reset.
 245          */
 246
 247         /* Disable L0S exit timer (platform NMI Work/Around) */
 248         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 249                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 250                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 251
 252         /*
 253          * Disable L0s without affecting L1;
 254          *  don't wait for ICH L0s (ICH bug W/A)
 255          */
 256         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 257                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 258
 259         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 260         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 261
 262         /*
 263          * Enable HAP INTA (interrupt from management bus) to
 264          * wake device's PCI Express link L1a -> L0s
 265          */
 266         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 267                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 268
 269         iwl_pcie_apm_config(trans);
 270
 271         /* Configure analog phase-lock-loop before activating to D0A */
 272         if (trans->cfg->base_params->pll_cfg)
 273                 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 274
 275         /*
 276          * Set "initialization complete" bit to move adapter from
 277          * D0U* --> D0A* (powered-up active) state.
 278          */
 279         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 280
 281         /*
 282          * Wait for clock stabilization; once stabilized, access to
 283          * device-internal resources is supported, e.g. iwl_write_prph()
 284          * and accesses to uCode SRAM.
 285          */
 286         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 287                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 288                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 289         if (ret < 0) {
 290                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 291                 goto out;
 292         }
 293
 294         if (trans->cfg->host_interrupt_operation_mode) {
 295                 /*
 296                  * This is a bit of an abuse - This is needed for 7260 / 3160
 297                  * only check host_interrupt_operation_mode even if this is
 298                  * not related to host_interrupt_operation_mode.
 299                  *
 300                  * Enable the oscillator to count wake up time for L1 exit. This
 301                  * consumes slightly more power (100uA) - but allows to be sure
 302                  * that we wake up from L1 on time.
 303                  *
 304                  * This looks weird: read twice the same register, discard the
 305                  * value, set a bit, and yet again, read that same register
 306                  * just to discard the value. But that's the way the hardware
 307                  * seems to like it.
 308                  */
 309                 iwl_read_prph(trans, OSC_CLK);
 310                 iwl_read_prph(trans, OSC_CLK);
 311                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 312                 iwl_read_prph(trans, OSC_CLK);
 313                 iwl_read_prph(trans, OSC_CLK);
 314         }
 315
 316         /*
 317          * Enable DMA clock and wait for it to stabilize.
 318          *
 319          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 320          * bits do not disable clocks.  This preserves any hardware
 321          * bits already set by default in "CLK_CTRL_REG" after reset.
 322          */
 323         if (!trans->cfg->apmg_not_supported) {
 324                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 325                                APMG_CLK_VAL_DMA_CLK_RQT);
 326                 udelay(20);
 327
 328                 /* Disable L1-Active */
 329                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 330                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 331
 332                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 333                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 334                                APMG_RTC_INT_STT_RFKILL);
 335         }
 336
 337         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 338
 339 out:
 340         return ret;
 341 }
 342
 343 /*
 344  * Enable LP XTAL to avoid HW bug where device may consume much power if
 345  * FW is not loaded after device reset. LP XTAL is disabled by default
 346  * after device HW reset. Do it only if XTAL is fed by internal source.
 347  * Configure device's "persistence" mode to avoid resetting XTAL again when
 348  * SHRD_HW_RST occurs in S3.
 349  */
 350 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 351 {
 352         int ret;
 353         u32 apmg_gp1_reg;
 354         u32 apmg_xtal_cfg_reg;
 355         u32 dl_cfg_reg;
 356
 357         /* Force XTAL ON */
 358         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 359                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 360
 361         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 362         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 363         usleep_range(1000, 2000);
 364
 365         /*
 366          * Set "initialization complete" bit to move adapter from
 367          * D0U* --> D0A* (powered-up active) state.
 368          */
 369         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 370
 371         /*
 372          * Wait for clock stabilization; once stabilized, access to
 373          * device-internal resources is possible.
 374          */
 375         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 376                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 377                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 378                            25000);
 379         if (WARN_ON(ret < 0)) {
 380                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 381                 /* Release XTAL ON request */
 382                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 383                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 384                 return;
 385         }
 386
 387         /*
 388          * Clear "disable persistence" to avoid LP XTAL resetting when
 389          * SHRD_HW_RST is applied in S3.
 390          */
 391         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 392                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 393
 394         /*
 395          * Force APMG XTAL to be active to prevent its disabling by HW
 396          * caused by APMG idle state.
 397          */
 398         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 399                                                     SHR_APMG_XTAL_CFG_REG);
 400         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 401                                  apmg_xtal_cfg_reg |
 402                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 403
 404         /*
 405          * Reset entire device again - do controller reset (results in
 406          * SHRD_HW_RST). Turn MAC off before proceeding.
 407          */
 408         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 409         usleep_range(1000, 2000);
 410
 411         /* Enable LP XTAL by indirect access through CSR */
 412         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 413         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 414                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 415                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 416
 417         /* Clear delay line clock power up */
 418         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 419         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 420                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 421
 422         /*
 423          * Enable persistence mode to avoid LP XTAL resetting when
 424          * SHRD_HW_RST is applied in S3.
 425          */
 426         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 427                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 428
 429         /*
 430          * Clear "initialization complete" bit to move adapter from
 431          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 432          */
 433         iwl_clear_bit(trans, CSR_GP_CNTRL,
 434                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 435
 436         /* Activates XTAL resources monitor */
 437         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 438                                  CSR_MONITOR_XTAL_RESOURCES);
 439
 440         /* Release XTAL ON request */
 441         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 442                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 443         udelay(10);
 444
 445         /* Release APMG XTAL */
 446         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 447                                  apmg_xtal_cfg_reg &
 448                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 449 }
 450
 451 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 452 {
 453         int ret = 0;
 454
 455         /* stop device's busmaster DMA activity */
 456         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 457
 458         ret = iwl_poll_bit(trans, CSR_RESET,
 459                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 460                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 461         if (ret < 0)
 462                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 463
 464         IWL_DEBUG_INFO(trans, "stop master\n");
 465
 466         return ret;
 467 }
 468
 469 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 470 {
 471         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 472
 473         if (op_mode_leave) {
 474                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 475                         iwl_pcie_apm_init(trans);
 476
 477                 /* inform ME that we are leaving */
 478                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 479                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 480                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 481                 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
 482                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 483                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 484                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 485                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 486                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 487                         mdelay(1);
 488                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 489                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 490                 }
 491                 mdelay(5);
 492         }
 493
 494         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 495
 496         /* Stop device's DMA activity */
 497         iwl_pcie_apm_stop_master(trans);
 498
 499         if (trans->cfg->lp_xtal_workaround) {
 500                 iwl_pcie_apm_lp_xtal_enable(trans);
 501                 return;
 502         }
 503
 504         /* Reset the entire device */
 505         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 506         usleep_range(1000, 2000);
 507
 508         /*
 509          * Clear "initialization complete" bit to move adapter from
 510          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 511          */
 512         iwl_clear_bit(trans, CSR_GP_CNTRL,
 513                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 514 }
 515
 516 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 517 {
 518         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 519
 520         /* nic_init */
 521         spin_lock(&trans_pcie->irq_lock);
 522         iwl_pcie_apm_init(trans);
 523
 524         spin_unlock(&trans_pcie->irq_lock);
 525
 526         iwl_pcie_set_pwr(trans, false);
 527
 528         iwl_op_mode_nic_config(trans->op_mode);
 529
 530         /* Allocate the RX queue, or reset if it is already allocated */
 531         iwl_pcie_rx_init(trans);
 532
 533         /* Allocate or reset and init all Tx and Command queues */
 534         if (iwl_pcie_tx_init(trans))
 535                 return -ENOMEM;
 536
 537         if (trans->cfg->base_params->shadow_reg_enable) {
 538                 /* enable shadow regs in HW */
 539                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 540                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 541         }
 542
 543         return 0;
 544 }
 545
 546 #define HW_READY_TIMEOUT (50)
 547
 548 /* Note: returns poll_bit return value, which is >= 0 if success */
 549 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 550 {
 551         int ret;
 552
 553         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 554                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 555
 556         /* See if we got it */
 557         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 558                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 559                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 560                            HW_READY_TIMEOUT);
 561
 562         if (ret >= 0)
 563                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 564
 565         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 566         return ret;
 567 }
 568
 569 /* Note: returns standard 0/-ERROR code */
 570 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 571 {
 572         int ret;
 573         int t = 0;
 574         int iter;
 575
 576         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 577
 578         ret = iwl_pcie_set_hw_ready(trans);
 579         /* If the card is ready, exit 0 */
 580         if (ret >= 0)
 581                 return 0;
 582
 583         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 584                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 585         msleep(1);
 586
 587         for (iter = 0; iter < 10; iter++) {
 588                 /* If HW is not ready, prepare the conditions to check again */
 589                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 590                             CSR_HW_IF_CONFIG_REG_PREPARE);
 591
 592                 do {
 593                         ret = iwl_pcie_set_hw_ready(trans);
 594                         if (ret >= 0)
 595                                 return 0;
 596
 597                         usleep_range(200, 1000);
 598                         t += 200;
 599                 } while (t < 150000);
 600                 msleep(25);
 601         }
 602
 603         IWL_ERR(trans, "Couldn't prepare the card\n");
 604
 605         return ret;
 606 }
 607
 608 /*
 609  * ucode
 610  */
 611 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 612                                    dma_addr_t phy_addr, u32 byte_cnt)
 613 {
 614         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 615         unsigned long flags;
 616         int ret;
 617
 618         trans_pcie->ucode_write_complete = false;
 619
 620         if (!iwl_trans_grab_nic_access(trans, &flags))
 621                 return -EIO;
 622
 623         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 624                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 625
 626         iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 627                     dst_addr);
 628
 629         iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 630                     phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 631
 632         iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 633                     (iwl_get_dma_hi_addr(phy_addr)
 634                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 635
 636         iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 637                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
 638                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
 639                     FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 640
 641         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 642                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 643                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 644                     FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 645
 646         iwl_trans_release_nic_access(trans, &flags);
 647
 648         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 649                                  trans_pcie->ucode_write_complete, 5 * HZ);
 650         if (!ret) {
 651                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 652                 return -ETIMEDOUT;
 653         }
 654
 655         return 0;
 656 }
 657
 658 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 659                             const struct fw_desc *section)
 660 {
 661         u8 *v_addr;
 662         dma_addr_t p_addr;
 663         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 664         int ret = 0;
 665
 666         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 667                      section_num);
 668
 669         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 670                                     GFP_KERNEL | __GFP_NOWARN);
 671         if (!v_addr) {
 672                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 673                 chunk_sz = PAGE_SIZE;
 674                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 675                                             &p_addr, GFP_KERNEL);
 676                 if (!v_addr)
 677                         return -ENOMEM;
 678         }
 679
 680         for (offset = 0; offset < section->len; offset += chunk_sz) {
 681                 u32 copy_size, dst_addr;
 682                 bool extended_addr = false;
 683
 684                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 685                 dst_addr = section->offset + offset;
 686
 687                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 688                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 689                         extended_addr = true;
 690
 691                 if (extended_addr)
 692                         iwl_set_bits_prph(trans, LMPM_CHICK,
 693                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 694
 695                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 696                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 697                                                    copy_size);
 698
 699                 if (extended_addr)
 700                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 701                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 702
 703                 if (ret) {
 704                         IWL_ERR(trans,
 705                                 "Could not load the [%d] uCode section\n",
 706                                 section_num);
 707                         break;
 708                 }
 709         }
 710
 711         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 712         return ret;
 713 }
 714
 715 /*
 716  * Driver Takes the ownership on secure machine before FW load
 717  * and prevent race with the BT load.
 718  * W/A for ROM bug. (should be remove in the next Si step)
 719  */
 720 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
 721 {
 722         u32 val, loop = 1000;
 723
 724         /*
 725          * Check the RSA semaphore is accessible.
 726          * If the HW isn't locked and the rsa semaphore isn't accessible,
 727          * we are in trouble.
 728          */
 729         val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
 730         if (val & (BIT(1) | BIT(17))) {
 731                 IWL_DEBUG_INFO(trans,
 732                                "can't access the RSA semaphore it is write protected\n");
 733                 return 0;
 734         }
 735
 736         /* take ownership on the AUX IF */
 737         iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
 738         iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
 739
 740         do {
 741                 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
 742                 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
 743                 if (val == 0x1) {
 744                         iwl_write_prph(trans, RSA_ENABLE, 0);
 745                         return 0;
 746                 }
 747
 748                 udelay(10);
 749                 loop--;
 750         } while (loop > 0);
 751
 752         IWL_ERR(trans, "Failed to take ownership on secure machine\n");
 753         return -EIO;
 754 }
 755
 756 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 757                                            const struct fw_img *image,
 758                                            int cpu,
 759                                            int *first_ucode_section)
 760 {
 761         int shift_param;
 762         int i, ret = 0, sec_num = 0x1;
 763         u32 val, last_read_idx = 0;
 764
 765         if (cpu == 1) {
 766                 shift_param = 0;
 767                 *first_ucode_section = 0;
 768         } else {
 769                 shift_param = 16;
 770                 (*first_ucode_section)++;
 771         }
 772
 773         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 774                 last_read_idx = i;
 775
 776                 /*
 777                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 778                  * CPU1 to CPU2.
 779                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 780                  * CPU2 non paged to CPU2 paging sec.
 781                  */
 782                 if (!image->sec[i].data ||
 783                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 784                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 785                         IWL_DEBUG_FW(trans,
 786                                      "Break since Data not valid or Empty section, sec = %d\n",
 787                                      i);
 788                         break;
 789                 }
 790
 791                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 792                 if (ret)
 793                         return ret;
 794
 795                 /* Notify the ucode of the loaded section number and status */
 796                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 797                 val = val | (sec_num << shift_param);
 798                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 799                 sec_num = (sec_num << 1) | 0x1;
 800         }
 801
 802         *first_ucode_section = last_read_idx;
 803
 804         if (cpu == 1)
 805                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
 806         else
 807                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
 808
 809         return 0;
 810 }
 811
 812 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 813                                       const struct fw_img *image,
 814                                       int cpu,
 815                                       int *first_ucode_section)
 816 {
 817         int shift_param;
 818         int i, ret = 0;
 819         u32 last_read_idx = 0;
 820
 821         if (cpu == 1) {
 822                 shift_param = 0;
 823                 *first_ucode_section = 0;
 824         } else {
 825                 shift_param = 16;
 826                 (*first_ucode_section)++;
 827         }
 828
 829         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 830                 last_read_idx = i;
 831
 832                 /*
 833                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 834                  * CPU1 to CPU2.
 835                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 836                  * CPU2 non paged to CPU2 paging sec.
 837                  */
 838                 if (!image->sec[i].data ||
 839                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 840                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 841                         IWL_DEBUG_FW(trans,
 842                                      "Break since Data not valid or Empty section, sec = %d\n",
 843                                      i);
 844                         break;
 845                 }
 846
 847                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 848                 if (ret)
 849                         return ret;
 850         }
 851
 852         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 853                 iwl_set_bits_prph(trans,
 854                                   CSR_UCODE_LOAD_STATUS_ADDR,
 855                                   (LMPM_CPU_UCODE_LOADING_COMPLETED |
 856                                    LMPM_CPU_HDRS_LOADING_COMPLETED |
 857                                    LMPM_CPU_UCODE_LOADING_STARTED) <<
 858                                         shift_param);
 859
 860         *first_ucode_section = last_read_idx;
 861
 862         return 0;
 863 }
 864
 865 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
 866 {
 867         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 868         const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
 869         int i;
 870
 871         if (dest->version)
 872                 IWL_ERR(trans,
 873                         "DBG DEST version is %d - expect issues\n",
 874                         dest->version);
 875
 876         IWL_INFO(trans, "Applying debug destination %s\n",
 877                  get_fw_dbg_mode_string(dest->monitor_mode));
 878
 879         if (dest->monitor_mode == EXTERNAL_MODE)
 880                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 881         else
 882                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 883
 884         for (i = 0; i < trans->dbg_dest_reg_num; i++) {
 885                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 886                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 887
 888                 switch (dest->reg_ops[i].op) {
 889                 case CSR_ASSIGN:
 890                         iwl_write32(trans, addr, val);
 891                         break;
 892                 case CSR_SETBIT:
 893                         iwl_set_bit(trans, addr, BIT(val));
 894                         break;
 895                 case CSR_CLEARBIT:
 896                         iwl_clear_bit(trans, addr, BIT(val));
 897                         break;
 898                 case PRPH_ASSIGN:
 899                         iwl_write_prph(trans, addr, val);
 900                         break;
 901                 case PRPH_SETBIT:
 902                         iwl_set_bits_prph(trans, addr, BIT(val));
 903                         break;
 904                 case PRPH_CLEARBIT:
 905                         iwl_clear_bits_prph(trans, addr, BIT(val));
 906                         break;
 907                 case PRPH_BLOCKBIT:
 908                         if (iwl_read_prph(trans, addr) & BIT(val)) {
 909                                 IWL_ERR(trans,
 910                                         "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
 911                                         val, addr);
 912                                 goto monitor;
 913                         }
 914                         break;
 915                 default:
 916                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 917                                 dest->reg_ops[i].op);
 918                         break;
 919                 }
 920         }
 921
 922 monitor:
 923         if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
 924                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 925                                trans_pcie->fw_mon_phys >> dest->base_shift);
 926                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 927                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 928                                        (trans_pcie->fw_mon_phys +
 929                                         trans_pcie->fw_mon_size - 256) >>
 930                                                 dest->end_shift);
 931                 else
 932                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 933                                        (trans_pcie->fw_mon_phys +
 934                                         trans_pcie->fw_mon_size) >>
 935                                                 dest->end_shift);
 936         }
 937 }
 938
 939 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 940                                 const struct fw_img *image)
 941 {
 942         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 943         int ret = 0;
 944         int first_ucode_section;
 945
 946         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 947                      image->is_dual_cpus ? "Dual" : "Single");
 948
 949         /* load to FW the binary non secured sections of CPU1 */
 950         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
 951         if (ret)
 952                 return ret;
 953
 954         if (image->is_dual_cpus) {
 955                 /* set CPU2 header address */
 956                 iwl_write_prph(trans,
 957                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
 958                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 959
 960                 /* load to FW the binary sections of CPU2 */
 961                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
 962                                                  &first_ucode_section);
 963                 if (ret)
 964                         return ret;
 965         }
 966
 967         /* supported for 7000 only for the moment */
 968         if (iwlwifi_mod_params.fw_monitor &&
 969             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
 970                 iwl_pcie_alloc_fw_monitor(trans, 0);
 971
 972                 if (trans_pcie->fw_mon_size) {
 973                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
 974                                        trans_pcie->fw_mon_phys >> 4);
 975                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
 976                                        (trans_pcie->fw_mon_phys +
 977                                         trans_pcie->fw_mon_size) >> 4);
 978                 }
 979         } else if (trans->dbg_dest_tlv) {
 980                 iwl_pcie_apply_destination(trans);
 981         }
 982
 983         /* release CPU reset */
 984         iwl_write32(trans, CSR_RESET, 0);
 985
 986         return 0;
 987 }
 988
 989 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
 990                                           const struct fw_img *image)
 991 {
 992         int ret = 0;
 993         int first_ucode_section;
 994
 995         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 996                      image->is_dual_cpus ? "Dual" : "Single");
 997
 998         if (trans->dbg_dest_tlv)
 999                 iwl_pcie_apply_destination(trans);
1000
1001         /* TODO: remove in the next Si step */
1002         ret = iwl_pcie_rsa_race_bug_wa(trans);
1003         if (ret)
1004                 return ret;
1005
1006         /* configure the ucode to be ready to get the secured image */
1007         /* release CPU reset */
1008         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1009
1010         /* load to FW the binary Secured sections of CPU1 */
1011         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1012                                               &first_ucode_section);
1013         if (ret)
1014                 return ret;
1015
1016         /* load to FW the binary sections of CPU2 */
1017         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1018                                                &first_ucode_section);
1019 }
1020
1021 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1022 {
1023         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1024         bool hw_rfkill, was_hw_rfkill;
1025
1026         lockdep_assert_held(&trans_pcie->mutex);
1027
1028         if (trans_pcie->is_down)
1029                 return;
1030
1031         trans_pcie->is_down = true;
1032
1033         was_hw_rfkill = iwl_is_rfkill_set(trans);
1034
1035         /* tell the device to stop sending interrupts */
1036         spin_lock(&trans_pcie->irq_lock);
1037         iwl_disable_interrupts(trans);
1038         spin_unlock(&trans_pcie->irq_lock);
1039
1040         /* device going down, Stop using ICT table */
1041         iwl_pcie_disable_ict(trans);
1042
1043         /*
1044          * If a HW restart happens during firmware loading,
1045          * then the firmware loading might call this function
1046          * and later it might be called again due to the
1047          * restart. So don't process again if the device is
1048          * already dead.
1049          */
1050         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1051                 IWL_DEBUG_INFO(trans,
1052                                "DEVICE_ENABLED bit was set and is now cleared\n");
1053                 iwl_pcie_tx_stop(trans);
1054                 iwl_pcie_rx_stop(trans);
1055
1056                 /* Power-down device's busmaster DMA clocks */
1057                 if (!trans->cfg->apmg_not_supported) {
1058                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1059                                        APMG_CLK_VAL_DMA_CLK_RQT);
1060                         udelay(5);
1061                 }
1062         }
1063
1064         /* Make sure (redundant) we've released our request to stay awake */
1065         iwl_clear_bit(trans, CSR_GP_CNTRL,
1066                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1067
1068         /* Stop the device, and put it in low power state */
1069         iwl_pcie_apm_stop(trans, false);
1070
1071         /* stop and reset the on-board processor */
1072         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1073         usleep_range(1000, 2000);
1074
1075         /*
1076          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1077          * This is a bug in certain verions of the hardware.
1078          * Certain devices also keep sending HW RF kill interrupt all
1079          * the time, unless the interrupt is ACKed even if the interrupt
1080          * should be masked. Re-ACK all the interrupts here.
1081          */
1082         spin_lock(&trans_pcie->irq_lock);
1083         iwl_disable_interrupts(trans);
1084         spin_unlock(&trans_pcie->irq_lock);
1085
1086         /* clear all status bits */
1087         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1088         clear_bit(STATUS_INT_ENABLED, &trans->status);
1089         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1090         clear_bit(STATUS_RFKILL, &trans->status);
1091
1092         /*
1093          * Even if we stop the HW, we still want the RF kill
1094          * interrupt
1095          */
1096         iwl_enable_rfkill_int(trans);
1097
1098         /*
1099          * Check again since the RF kill state may have changed while
1100          * all the interrupts were disabled, in this case we couldn't
1101          * receive the RF kill interrupt and update the state in the
1102          * op_mode.
1103          * Don't call the op_mode if the rkfill state hasn't changed.
1104          * This allows the op_mode to call stop_device from the rfkill
1105          * notification without endless recursion. Under very rare
1106          * circumstances, we might have a small recursion if the rfkill
1107          * state changed exactly now while we were called from stop_device.
1108          * This is very unlikely but can happen and is supported.
1109          */
1110         hw_rfkill = iwl_is_rfkill_set(trans);
1111         if (hw_rfkill)
1112                 set_bit(STATUS_RFKILL, &trans->status);
1113         else
1114                 clear_bit(STATUS_RFKILL, &trans->status);
1115         if (hw_rfkill != was_hw_rfkill)
1116                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1117
1118         /* re-take ownership to prevent other users from stealing the device */
1119         iwl_pcie_prepare_card_hw(trans);
1120 }
1121
1122 static void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1123 {
1124         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1125
1126         if (trans_pcie->msix_enabled) {
1127                 int i;
1128
1129                 for (i = 0; i < trans_pcie->allocated_vector; i++)
1130                         synchronize_irq(trans_pcie->msix_entries[i].vector);
1131         } else {
1132                 synchronize_irq(trans_pcie->pci_dev->irq);
1133         }
1134 }
1135
1136 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1137                                    const struct fw_img *fw, bool run_in_rfkill)
1138 {
1139         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1140         bool hw_rfkill;
1141         int ret;
1142
1143         /* This may fail if AMT took ownership of the device */
1144         if (iwl_pcie_prepare_card_hw(trans)) {
1145                 IWL_WARN(trans, "Exit HW not ready\n");
1146                 ret = -EIO;
1147                 goto out;
1148         }
1149
1150         iwl_enable_rfkill_int(trans);
1151
1152         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1153
1154         /*
1155          * We enabled the RF-Kill interrupt and the handler may very
1156          * well be running. Disable the interrupts to make sure no other
1157          * interrupt can be fired.
1158          */
1159         iwl_disable_interrupts(trans);
1160
1161         /* Make sure it finished running */
1162         iwl_pcie_synchronize_irqs(trans);
1163
1164         mutex_lock(&trans_pcie->mutex);
1165
1166         /* If platform's RF_KILL switch is NOT set to KILL */
1167         hw_rfkill = iwl_is_rfkill_set(trans);
1168         if (hw_rfkill)
1169                 set_bit(STATUS_RFKILL, &trans->status);
1170         else
1171                 clear_bit(STATUS_RFKILL, &trans->status);
1172         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1173         if (hw_rfkill && !run_in_rfkill) {
1174                 ret = -ERFKILL;
1175                 goto out;
1176         }
1177
1178         /* Someone called stop_device, don't try to start_fw */
1179         if (trans_pcie->is_down) {
1180                 IWL_WARN(trans,
1181                          "Can't start_fw since the HW hasn't been started\n");
1182                 ret = -EIO;
1183                 goto out;
1184         }
1185
1186         /* make sure rfkill handshake bits are cleared */
1187         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1188         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1189                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1190
1191         /* clear (again), then enable host interrupts */
1192         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1193
1194         ret = iwl_pcie_nic_init(trans);
1195         if (ret) {
1196                 IWL_ERR(trans, "Unable to init nic\n");
1197                 goto out;
1198         }
1199
1200         /*
1201          * Now, we load the firmware and don't want to be interrupted, even
1202          * by the RF-Kill interrupt (hence mask all the interrupt besides the
1203          * FH_TX interrupt which is needed to load the firmware). If the
1204          * RF-Kill switch is toggled, we will find out after having loaded
1205          * the firmware and return the proper value to the caller.
1206          */
1207         iwl_enable_fw_load_int(trans);
1208
1209         /* really make sure rfkill handshake bits are cleared */
1210         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1211         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1212
1213         /* Load the given image to the HW */
1214         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1215                 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1216         else
1217                 ret = iwl_pcie_load_given_ucode(trans, fw);
1218         iwl_enable_interrupts(trans);
1219
1220         /* re-check RF-Kill state since we may have missed the interrupt */
1221         hw_rfkill = iwl_is_rfkill_set(trans);
1222         if (hw_rfkill)
1223                 set_bit(STATUS_RFKILL, &trans->status);
1224         else
1225                 clear_bit(STATUS_RFKILL, &trans->status);
1226
1227         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1228         if (hw_rfkill && !run_in_rfkill)
1229                 ret = -ERFKILL;
1230
1231 out:
1232         mutex_unlock(&trans_pcie->mutex);
1233         return ret;
1234 }
1235
1236 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1237 {
1238         iwl_pcie_reset_ict(trans);
1239         iwl_pcie_tx_start(trans, scd_addr);
1240 }
1241
1242 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1243 {
1244         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1245
1246         mutex_lock(&trans_pcie->mutex);
1247         _iwl_trans_pcie_stop_device(trans, low_power);
1248         mutex_unlock(&trans_pcie->mutex);
1249 }
1250
1251 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1252 {
1253         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1254                 IWL_TRANS_GET_PCIE_TRANS(trans);
1255
1256         lockdep_assert_held(&trans_pcie->mutex);
1257
1258         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1259                 _iwl_trans_pcie_stop_device(trans, true);
1260 }
1261
1262 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1263                                       bool reset)
1264 {
1265         if (!reset) {
1266                 /* Enable persistence mode to avoid reset */
1267                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1268                             CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1269         }
1270
1271         iwl_disable_interrupts(trans);
1272
1273         /*
1274          * in testing mode, the host stays awake and the
1275          * hardware won't be reset (not even partially)
1276          */
1277         if (test)
1278                 return;
1279
1280         iwl_pcie_disable_ict(trans);
1281
1282         iwl_pcie_synchronize_irqs(trans);
1283
1284         iwl_clear_bit(trans, CSR_GP_CNTRL,
1285                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1286         iwl_clear_bit(trans, CSR_GP_CNTRL,
1287                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1288
1289         if (reset) {
1290                 /*
1291                  * reset TX queues -- some of their registers reset during S3
1292                  * so if we don't reset everything here the D3 image would try
1293                  * to execute some invalid memory upon resume
1294                  */
1295                 iwl_trans_pcie_tx_reset(trans);
1296         }
1297
1298         iwl_pcie_set_pwr(trans, true);
1299 }
1300
1301 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1302                                     enum iwl_d3_status *status,
1303                                     bool test,  bool reset)
1304 {
1305         u32 val;
1306         int ret;
1307
1308         if (test) {
1309                 iwl_enable_interrupts(trans);
1310                 *status = IWL_D3_STATUS_ALIVE;
1311                 return 0;
1312         }
1313
1314         /*
1315          * Also enables interrupts - none will happen as the device doesn't
1316          * know we're waking it up, only when the opmode actually tells it
1317          * after this call.
1318          */
1319         iwl_pcie_reset_ict(trans);
1320         iwl_enable_interrupts(trans);
1321
1322         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1323         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1324
1325         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1326                 udelay(2);
1327
1328         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1329                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1330                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1331                            25000);
1332         if (ret < 0) {
1333                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1334                 return ret;
1335         }
1336
1337         iwl_pcie_set_pwr(trans, false);
1338
1339         if (!reset) {
1340                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1341                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1342         } else {
1343                 iwl_trans_pcie_tx_reset(trans);
1344
1345                 ret = iwl_pcie_rx_init(trans);
1346                 if (ret) {
1347                         IWL_ERR(trans,
1348                                 "Failed to resume the device (RX reset)\n");
1349                         return ret;
1350                 }
1351         }
1352
1353         val = iwl_read32(trans, CSR_RESET);
1354         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1355                 *status = IWL_D3_STATUS_RESET;
1356         else
1357                 *status = IWL_D3_STATUS_ALIVE;
1358
1359         return 0;
1360 }
1361
1362 struct iwl_causes_list {
1363         u32 cause_num;
1364         u32 mask_reg;
1365         u8 addr;
1366 };
1367
1368 static struct iwl_causes_list causes_list[] = {
1369         {MSIX_FH_INT_CAUSES_D2S_CH0_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0},
1370         {MSIX_FH_INT_CAUSES_D2S_CH1_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0x1},
1371         {MSIX_FH_INT_CAUSES_S2D,                CSR_MSIX_FH_INT_MASK_AD, 0x3},
1372         {MSIX_FH_INT_CAUSES_FH_ERR,             CSR_MSIX_FH_INT_MASK_AD, 0x5},
1373         {MSIX_HW_INT_CAUSES_REG_ALIVE,          CSR_MSIX_HW_INT_MASK_AD, 0x10},
1374         {MSIX_HW_INT_CAUSES_REG_WAKEUP,         CSR_MSIX_HW_INT_MASK_AD, 0x11},
1375         {MSIX_HW_INT_CAUSES_REG_CT_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x16},
1376         {MSIX_HW_INT_CAUSES_REG_RF_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x17},
1377         {MSIX_HW_INT_CAUSES_REG_PERIODIC,       CSR_MSIX_HW_INT_MASK_AD, 0x18},
1378         {MSIX_HW_INT_CAUSES_REG_SW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x29},
1379         {MSIX_HW_INT_CAUSES_REG_SCD,            CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1380         {MSIX_HW_INT_CAUSES_REG_FH_TX,          CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1381         {MSIX_HW_INT_CAUSES_REG_HW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1382         {MSIX_HW_INT_CAUSES_REG_HAP,            CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1383 };
1384
1385 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1386 {
1387         u32 val, max_rx_vector, i;
1388         struct iwl_trans *trans = trans_pcie->trans;
1389
1390         max_rx_vector = trans_pcie->allocated_vector - 1;
1391
1392         if (!trans_pcie->msix_enabled)
1393                 return;
1394
1395         iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1396
1397         /*
1398          * Each cause from the list above and the RX causes is represented as
1399          * a byte in the IVAR table. We access the first (N - 1) bytes and map
1400          * them to the (N - 1) vectors so these vectors will be used as rx
1401          * vectors. Then access all non rx causes and map them to the
1402          * default queue (N'th queue).
1403          */
1404         for (i = 0; i < max_rx_vector; i++) {
1405                 iwl_write8(trans, CSR_MSIX_RX_IVAR(i), MSIX_FH_INT_CAUSES_Q(i));
1406                 iwl_clear_bit(trans, CSR_MSIX_FH_INT_MASK_AD,
1407                               BIT(MSIX_FH_INT_CAUSES_Q(i)));
1408         }
1409
1410         for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1411                 val = trans_pcie->default_irq_num |
1412                         MSIX_NON_AUTO_CLEAR_CAUSE;
1413                 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1414                 iwl_clear_bit(trans, causes_list[i].mask_reg,
1415                               causes_list[i].cause_num);
1416         }
1417         trans_pcie->fh_init_mask =
1418                 ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1419         trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1420         trans_pcie->hw_init_mask =
1421                 ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1422         trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1423 }
1424
1425 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1426                                         struct iwl_trans *trans)
1427 {
1428         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1429         u16 pci_cmd;
1430         int max_vector;
1431         int ret, i;
1432
1433         if (trans->cfg->mq_rx_supported) {
1434                 max_vector = min_t(u32, (num_possible_cpus() + 2),
1435                                    IWL_MAX_RX_HW_QUEUES);
1436                 for (i = 0; i < max_vector; i++)
1437                         trans_pcie->msix_entries[i].entry = i;
1438
1439                 ret = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1440                                             MSIX_MIN_INTERRUPT_VECTORS,
1441                                             max_vector);
1442                 if (ret > 1) {
1443                         IWL_DEBUG_INFO(trans,
1444                                        "Enable MSI-X allocate %d interrupt vector\n",
1445                                        ret);
1446                         trans_pcie->allocated_vector = ret;
1447                         trans_pcie->default_irq_num =
1448                                 trans_pcie->allocated_vector - 1;
1449                         trans_pcie->trans->num_rx_queues =
1450                                 trans_pcie->allocated_vector - 1;
1451                         trans_pcie->msix_enabled = true;
1452
1453                         return;
1454                 }
1455                 IWL_DEBUG_INFO(trans,
1456                                "ret = %d %s move to msi mode\n", ret,
1457                                (ret == 1) ?
1458                                "can't allocate more than 1 interrupt vector" :
1459                                "failed to enable msi-x mode");
1460                 pci_disable_msix(pdev);
1461         }
1462
1463         ret = pci_enable_msi(pdev);
1464         if (ret) {
1465                 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1466                 /* enable rfkill interrupt: hw bug w/a */
1467                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1468                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1469                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1470                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1471                 }
1472         }
1473 }
1474
1475 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1476                                       struct iwl_trans_pcie *trans_pcie)
1477 {
1478         int i, last_vector;
1479
1480         last_vector = trans_pcie->trans->num_rx_queues;
1481
1482         for (i = 0; i < trans_pcie->allocated_vector; i++) {
1483                 int ret;
1484
1485                 ret = request_threaded_irq(trans_pcie->msix_entries[i].vector,
1486                                            iwl_pcie_msix_isr,
1487                                            (i == last_vector) ?
1488                                            iwl_pcie_irq_msix_handler :
1489                                            iwl_pcie_irq_rx_msix_handler,
1490                                            IRQF_SHARED,
1491                                            DRV_NAME,
1492                                            &trans_pcie->msix_entries[i]);
1493                 if (ret) {
1494                         int j;
1495
1496                         IWL_ERR(trans_pcie->trans,
1497                                 "Error allocating IRQ %d\n", i);
1498                         for (j = 0; j < i; j++)
1499                                 free_irq(trans_pcie->msix_entries[j].vector,
1500                                          &trans_pcie->msix_entries[j]);
1501                         pci_disable_msix(pdev);
1502                         return ret;
1503                 }
1504         }
1505
1506         return 0;
1507 }
1508
1509 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1510 {
1511         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1512         bool hw_rfkill;
1513         int err;
1514
1515         lockdep_assert_held(&trans_pcie->mutex);
1516
1517         err = iwl_pcie_prepare_card_hw(trans);
1518         if (err) {
1519                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1520                 return err;
1521         }
1522
1523         /* Reset the entire device */
1524         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1525         usleep_range(1000, 2000);
1526
1527         iwl_pcie_apm_init(trans);
1528
1529         iwl_pcie_init_msix(trans_pcie);
1530         /* From now on, the op_mode will be kept updated about RF kill state */
1531         iwl_enable_rfkill_int(trans);
1532
1533         /* Set is_down to false here so that...*/
1534         trans_pcie->is_down = false;
1535
1536         hw_rfkill = iwl_is_rfkill_set(trans);
1537         if (hw_rfkill)
1538                 set_bit(STATUS_RFKILL, &trans->status);
1539         else
1540                 clear_bit(STATUS_RFKILL, &trans->status);
1541         /* ... rfkill can call stop_device and set it false if needed */
1542         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1543
1544         /* Make sure we sync here, because we'll need full access later */
1545         if (low_power)
1546                 pm_runtime_resume(trans->dev);
1547
1548         return 0;
1549 }
1550
1551 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1552 {
1553         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1554         int ret;
1555
1556         mutex_lock(&trans_pcie->mutex);
1557         ret = _iwl_trans_pcie_start_hw(trans, low_power);
1558         mutex_unlock(&trans_pcie->mutex);
1559
1560         return ret;
1561 }
1562
1563 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1564 {
1565         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1566
1567         mutex_lock(&trans_pcie->mutex);
1568
1569         /* disable interrupts - don't enable HW RF kill interrupt */
1570         spin_lock(&trans_pcie->irq_lock);
1571         iwl_disable_interrupts(trans);
1572         spin_unlock(&trans_pcie->irq_lock);
1573
1574         iwl_pcie_apm_stop(trans, true);
1575
1576         spin_lock(&trans_pcie->irq_lock);
1577         iwl_disable_interrupts(trans);
1578         spin_unlock(&trans_pcie->irq_lock);
1579
1580         iwl_pcie_disable_ict(trans);
1581
1582         mutex_unlock(&trans_pcie->mutex);
1583
1584         iwl_pcie_synchronize_irqs(trans);
1585 }
1586
1587 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1588 {
1589         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1590 }
1591
1592 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1593 {
1594         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1595 }
1596
1597 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1598 {
1599         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1600 }
1601
1602 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1603 {
1604         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1605                                ((reg & 0x000FFFFF) | (3 << 24)));
1606         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1607 }
1608
1609 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1610                                       u32 val)
1611 {
1612         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1613                                ((addr & 0x000FFFFF) | (3 << 24)));
1614         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1615 }
1616
1617 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1618                                      const struct iwl_trans_config *trans_cfg)
1619 {
1620         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1621
1622         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1623         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1624         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1625         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1626                 trans_pcie->n_no_reclaim_cmds = 0;
1627         else
1628                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1629         if (trans_pcie->n_no_reclaim_cmds)
1630                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1631                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1632
1633         trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1634         trans_pcie->rx_page_order =
1635                 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1636
1637         trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header;
1638         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1639         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1640         trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1641
1642         trans->command_groups = trans_cfg->command_groups;
1643         trans->command_groups_size = trans_cfg->command_groups_size;
1644
1645         /* Initialize NAPI here - it should be before registering to mac80211
1646          * in the opmode but after the HW struct is allocated.
1647          * As this function may be called again in some corner cases don't
1648          * do anything if NAPI was already initialized.
1649          */
1650         if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1651                 init_dummy_netdev(&trans_pcie->napi_dev);
1652 }
1653
1654 void iwl_trans_pcie_free(struct iwl_trans *trans)
1655 {
1656         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1657         int i;
1658
1659         iwl_pcie_synchronize_irqs(trans);
1660
1661         iwl_pcie_tx_free(trans);
1662         iwl_pcie_rx_free(trans);
1663
1664         if (trans_pcie->msix_enabled) {
1665                 for (i = 0; i < trans_pcie->allocated_vector; i++)
1666                         free_irq(trans_pcie->msix_entries[i].vector,
1667                                  &trans_pcie->msix_entries[i]);
1668
1669                 pci_disable_msix(trans_pcie->pci_dev);
1670                 trans_pcie->msix_enabled = false;
1671         } else {
1672                 free_irq(trans_pcie->pci_dev->irq, trans);
1673
1674                 iwl_pcie_free_ict(trans);
1675
1676                 pci_disable_msi(trans_pcie->pci_dev);
1677         }
1678         iounmap(trans_pcie->hw_base);
1679         pci_release_regions(trans_pcie->pci_dev);
1680         pci_disable_device(trans_pcie->pci_dev);
1681
1682         iwl_pcie_free_fw_monitor(trans);
1683
1684         for_each_possible_cpu(i) {
1685                 struct iwl_tso_hdr_page *p =
1686                         per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1687
1688                 if (p->page)
1689                         __free_page(p->page);
1690         }
1691
1692         free_percpu(trans_pcie->tso_hdr_page);
1693         mutex_destroy(&trans_pcie->mutex);
1694         iwl_trans_free(trans);
1695 }
1696
1697 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1698 {
1699         if (state)
1700                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1701         else
1702                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1703 }
1704
1705 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1706                                            unsigned long *flags)
1707 {
1708         int ret;
1709         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1710
1711         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1712
1713         if (trans_pcie->cmd_hold_nic_awake)
1714                 goto out;
1715
1716         /* this bit wakes up the NIC */
1717         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1718                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1719         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1720                 udelay(2);
1721
1722         /*
1723          * These bits say the device is running, and should keep running for
1724          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1725          * but they do not indicate that embedded SRAM is restored yet;
1726          * 3945 and 4965 have volatile SRAM, and must save/restore contents
1727          * to/from host DRAM when sleeping/waking for power-saving.
1728          * Each direction takes approximately 1/4 millisecond; with this
1729          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1730          * series of register accesses are expected (e.g. reading Event Log),
1731          * to keep device from sleeping.
1732          *
1733          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1734          * SRAM is okay/restored.  We don't check that here because this call
1735          * is just for hardware register access; but GP1 MAC_SLEEP check is a
1736          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1737          *
1738          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1739          * and do not save/restore SRAM when power cycling.
1740          */
1741         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1742                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1743                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1744                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1745         if (unlikely(ret < 0)) {
1746                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1747                 WARN_ONCE(1,
1748                           "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1749                           iwl_read32(trans, CSR_GP_CNTRL));
1750                 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1751                 return false;
1752         }
1753
1754 out:
1755         /*
1756          * Fool sparse by faking we release the lock - sparse will
1757          * track nic_access anyway.
1758          */
1759         __release(&trans_pcie->reg_lock);
1760         return true;
1761 }
1762
1763 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1764                                               unsigned long *flags)
1765 {
1766         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1767
1768         lockdep_assert_held(&trans_pcie->reg_lock);
1769
1770         /*
1771          * Fool sparse by faking we acquiring the lock - sparse will
1772          * track nic_access anyway.
1773          */
1774         __acquire(&trans_pcie->reg_lock);
1775
1776         if (trans_pcie->cmd_hold_nic_awake)
1777                 goto out;
1778
1779         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1780                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1781         /*
1782          * Above we read the CSR_GP_CNTRL register, which will flush
1783          * any previous writes, but we need the write that clears the
1784          * MAC_ACCESS_REQ bit to be performed before any other writes
1785          * scheduled on different CPUs (after we drop reg_lock).
1786          */
1787         mmiowb();
1788 out:
1789         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1790 }
1791
1792 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1793                                    void *buf, int dwords)
1794 {
1795         unsigned long flags;
1796         int offs, ret = 0;
1797         u32 *vals = buf;
1798
1799         if (iwl_trans_grab_nic_access(trans, &flags)) {
1800                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1801                 for (offs = 0; offs < dwords; offs++)
1802                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1803                 iwl_trans_release_nic_access(trans, &flags);
1804         } else {
1805                 ret = -EBUSY;
1806         }
1807         return ret;
1808 }
1809
1810 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1811                                     const void *buf, int dwords)
1812 {
1813         unsigned long flags;
1814         int offs, ret = 0;
1815         const u32 *vals = buf;
1816
1817         if (iwl_trans_grab_nic_access(trans, &flags)) {
1818                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1819                 for (offs = 0; offs < dwords; offs++)
1820                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1821                                     vals ? vals[offs] : 0);
1822                 iwl_trans_release_nic_access(trans, &flags);
1823         } else {
1824                 ret = -EBUSY;
1825         }
1826         return ret;
1827 }
1828
1829 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1830                                             unsigned long txqs,
1831                                             bool freeze)
1832 {
1833         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1834         int queue;
1835
1836         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1837                 struct iwl_txq *txq = &trans_pcie->txq[queue];
1838                 unsigned long now;
1839
1840                 spin_lock_bh(&txq->lock);
1841
1842                 now = jiffies;
1843
1844                 if (txq->frozen == freeze)
1845                         goto next_queue;
1846
1847                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1848                                     freeze ? "Freezing" : "Waking", queue);
1849
1850                 txq->frozen = freeze;
1851
1852                 if (txq->q.read_ptr == txq->q.write_ptr)
1853                         goto next_queue;
1854
1855                 if (freeze) {
1856                         if (unlikely(time_after(now,
1857                                                 txq->stuck_timer.expires))) {
1858                                 /*
1859                                  * The timer should have fired, maybe it is
1860                                  * spinning right now on the lock.
1861                                  */
1862                                 goto next_queue;
1863                         }
1864                         /* remember how long until the timer fires */
1865                         txq->frozen_expiry_remainder =
1866                                 txq->stuck_timer.expires - now;
1867                         del_timer(&txq->stuck_timer);
1868                         goto next_queue;
1869                 }
1870
1871                 /*
1872                  * Wake a non-empty queue -> arm timer with the
1873                  * remainder before it froze
1874                  */
1875                 mod_timer(&txq->stuck_timer,
1876                           now + txq->frozen_expiry_remainder);
1877
1878 next_queue:
1879                 spin_unlock_bh(&txq->lock);
1880         }
1881 }
1882
1883 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
1884 {
1885         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1886         int i;
1887
1888         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1889                 struct iwl_txq *txq = &trans_pcie->txq[i];
1890
1891                 if (i == trans_pcie->cmd_queue)
1892                         continue;
1893
1894                 spin_lock_bh(&txq->lock);
1895
1896                 if (!block && !(WARN_ON_ONCE(!txq->block))) {
1897                         txq->block--;
1898                         if (!txq->block) {
1899                                 iwl_write32(trans, HBUS_TARG_WRPTR,
1900                                             txq->q.write_ptr | (i << 8));
1901                         }
1902                 } else if (block) {
1903                         txq->block++;
1904                 }
1905
1906                 spin_unlock_bh(&txq->lock);
1907         }
1908 }
1909
1910 #define IWL_FLUSH_WAIT_MS       2000
1911
1912 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1913 {
1914         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1915         struct iwl_txq *txq;
1916         struct iwl_queue *q;
1917         int cnt;
1918         unsigned long now = jiffies;
1919         u32 scd_sram_addr;
1920         u8 buf[16];
1921         int ret = 0;
1922
1923         /* waiting for all the tx frames complete might take a while */
1924         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1925                 u8 wr_ptr;
1926
1927                 if (cnt == trans_pcie->cmd_queue)
1928                         continue;
1929                 if (!test_bit(cnt, trans_pcie->queue_used))
1930                         continue;
1931                 if (!(BIT(cnt) & txq_bm))
1932                         continue;
1933
1934                 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1935                 txq = &trans_pcie->txq[cnt];
1936                 q = &txq->q;
1937                 wr_ptr = ACCESS_ONCE(q->write_ptr);
1938
1939                 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1940                        !time_after(jiffies,
1941                                    now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1942                         u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1943
1944                         if (WARN_ONCE(wr_ptr != write_ptr,
1945                                       "WR pointer moved while flushing %d -> %d\n",
1946                                       wr_ptr, write_ptr))
1947                                 return -ETIMEDOUT;
1948                         msleep(1);
1949                 }
1950
1951                 if (q->read_ptr != q->write_ptr) {
1952                         IWL_ERR(trans,
1953                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1954                         ret = -ETIMEDOUT;
1955                         break;
1956                 }
1957                 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1958         }
1959
1960         if (!ret)
1961                 return 0;
1962
1963         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1964                 txq->q.read_ptr, txq->q.write_ptr);
1965
1966         scd_sram_addr = trans_pcie->scd_base_addr +
1967                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1968         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1969
1970         iwl_print_hex_error(trans, buf, sizeof(buf));
1971
1972         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1973                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1974                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1975
1976         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1977                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1978                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1979                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1980                 u32 tbl_dw =
1981                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1982                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1983
1984                 if (cnt & 0x1)
1985                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1986                 else
1987                         tbl_dw = tbl_dw & 0x0000FFFF;
1988
1989                 IWL_ERR(trans,
1990                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1991                         cnt, active ? "" : "in", fifo, tbl_dw,
1992                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1993                                 (TFD_QUEUE_SIZE_MAX - 1),
1994                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1995         }
1996
1997         return ret;
1998 }
1999
2000 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2001                                          u32 mask, u32 value)
2002 {
2003         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2004         unsigned long flags;
2005
2006         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2007         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2008         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2009 }
2010
2011 static void iwl_trans_pcie_ref(struct iwl_trans *trans)
2012 {
2013         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2014
2015         if (iwlwifi_mod_params.d0i3_disable)
2016                 return;
2017
2018         pm_runtime_get(&trans_pcie->pci_dev->dev);
2019
2020 #ifdef CONFIG_PM
2021         IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2022                       atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2023 #endif /* CONFIG_PM */
2024 }
2025
2026 static void iwl_trans_pcie_unref(struct iwl_trans *trans)
2027 {
2028         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2029
2030         if (iwlwifi_mod_params.d0i3_disable)
2031                 return;
2032
2033         pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2034         pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
2035
2036 #ifdef CONFIG_PM
2037         IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2038                       atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2039 #endif /* CONFIG_PM */
2040 }
2041
2042 static const char *get_csr_string(int cmd)
2043 {
2044 #define IWL_CMD(x) case x: return #x
2045         switch (cmd) {
2046         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2047         IWL_CMD(CSR_INT_COALESCING);
2048         IWL_CMD(CSR_INT);
2049         IWL_CMD(CSR_INT_MASK);
2050         IWL_CMD(CSR_FH_INT_STATUS);
2051         IWL_CMD(CSR_GPIO_IN);
2052         IWL_CMD(CSR_RESET);
2053         IWL_CMD(CSR_GP_CNTRL);
2054         IWL_CMD(CSR_HW_REV);
2055         IWL_CMD(CSR_EEPROM_REG);
2056         IWL_CMD(CSR_EEPROM_GP);
2057         IWL_CMD(CSR_OTP_GP_REG);
2058         IWL_CMD(CSR_GIO_REG);
2059         IWL_CMD(CSR_GP_UCODE_REG);
2060         IWL_CMD(CSR_GP_DRIVER_REG);
2061         IWL_CMD(CSR_UCODE_DRV_GP1);
2062         IWL_CMD(CSR_UCODE_DRV_GP2);
2063         IWL_CMD(CSR_LED_REG);
2064         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2065         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2066         IWL_CMD(CSR_ANA_PLL_CFG);
2067         IWL_CMD(CSR_HW_REV_WA_REG);
2068         IWL_CMD(CSR_MONITOR_STATUS_REG);
2069         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2070         default:
2071                 return "UNKNOWN";
2072         }
2073 #undef IWL_CMD
2074 }
2075
2076 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2077 {
2078         int i;
2079         static const u32 csr_tbl[] = {
2080                 CSR_HW_IF_CONFIG_REG,
2081                 CSR_INT_COALESCING,
2082                 CSR_INT,
2083                 CSR_INT_MASK,
2084                 CSR_FH_INT_STATUS,
2085                 CSR_GPIO_IN,
2086                 CSR_RESET,
2087                 CSR_GP_CNTRL,
2088                 CSR_HW_REV,
2089                 CSR_EEPROM_REG,
2090                 CSR_EEPROM_GP,
2091                 CSR_OTP_GP_REG,
2092                 CSR_GIO_REG,
2093                 CSR_GP_UCODE_REG,
2094                 CSR_GP_DRIVER_REG,
2095                 CSR_UCODE_DRV_GP1,
2096                 CSR_UCODE_DRV_GP2,
2097                 CSR_LED_REG,
2098                 CSR_DRAM_INT_TBL_REG,
2099                 CSR_GIO_CHICKEN_BITS,
2100                 CSR_ANA_PLL_CFG,
2101                 CSR_MONITOR_STATUS_REG,
2102                 CSR_HW_REV_WA_REG,
2103                 CSR_DBG_HPET_MEM_REG
2104         };
2105         IWL_ERR(trans, "CSR values:\n");
2106         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2107                 "CSR_INT_PERIODIC_REG)\n");
2108         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2109                 IWL_ERR(trans, "  %25s: 0X%08x\n",
2110                         get_csr_string(csr_tbl[i]),
2111                         iwl_read32(trans, csr_tbl[i]));
2112         }
2113 }
2114
2115 #ifdef CONFIG_IWLWIFI_DEBUGFS
2116 /* create and remove of files */
2117 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
2118         if (!debugfs_create_file(#name, mode, parent, trans,            \
2119                                  &iwl_dbgfs_##name##_ops))              \
2120                 goto err;                                               \
2121 } while (0)
2122
2123 /* file operation */
2124 #define DEBUGFS_READ_FILE_OPS(name)                                     \
2125 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2126         .read = iwl_dbgfs_##name##_read,                                \
2127         .open = simple_open,                                            \
2128         .llseek = generic_file_llseek,                                  \
2129 };
2130
2131 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2132 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2133         .write = iwl_dbgfs_##name##_write,                              \
2134         .open = simple_open,                                            \
2135         .llseek = generic_file_llseek,                                  \
2136 };
2137
2138 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
2139 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2140         .write = iwl_dbgfs_##name##_write,                              \
2141         .read = iwl_dbgfs_##name##_read,                                \
2142         .open = simple_open,                                            \
2143         .llseek = generic_file_llseek,                                  \
2144 };
2145
2146 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
2147                                        char __user *user_buf,
2148                                        size_t count, loff_t *ppos)
2149 {
2150         struct iwl_trans *trans = file->private_data;
2151         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2152         struct iwl_txq *txq;
2153         struct iwl_queue *q;
2154         char *buf;
2155         int pos = 0;
2156         int cnt;
2157         int ret;
2158         size_t bufsz;
2159
2160         bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
2161
2162         if (!trans_pcie->txq)
2163                 return -EAGAIN;
2164
2165         buf = kzalloc(bufsz, GFP_KERNEL);
2166         if (!buf)
2167                 return -ENOMEM;
2168
2169         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2170                 txq = &trans_pcie->txq[cnt];
2171                 q = &txq->q;
2172                 pos += scnprintf(buf + pos, bufsz - pos,
2173                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2174                                 cnt, q->read_ptr, q->write_ptr,
2175                                 !!test_bit(cnt, trans_pcie->queue_used),
2176                                  !!test_bit(cnt, trans_pcie->queue_stopped),
2177                                  txq->need_update, txq->frozen,
2178                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2179         }
2180         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2181         kfree(buf);
2182         return ret;
2183 }
2184
2185 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2186                                        char __user *user_buf,
2187                                        size_t count, loff_t *ppos)
2188 {
2189         struct iwl_trans *trans = file->private_data;
2190         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2191         char *buf;
2192         int pos = 0, i, ret;
2193         size_t bufsz = sizeof(buf);
2194
2195         bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2196
2197         if (!trans_pcie->rxq)
2198                 return -EAGAIN;
2199
2200         buf = kzalloc(bufsz, GFP_KERNEL);
2201         if (!buf)
2202                 return -ENOMEM;
2203
2204         for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2205                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2206
2207                 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2208                                  i);
2209                 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2210                                  rxq->read);
2211                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2212                                  rxq->write);
2213                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2214                                  rxq->write_actual);
2215                 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2216                                  rxq->need_update);
2217                 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2218                                  rxq->free_count);
2219                 if (rxq->rb_stts) {
2220                         pos += scnprintf(buf + pos, bufsz - pos,
2221                                          "\tclosed_rb_num: %u\n",
2222                                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2223                                          0x0FFF);
2224                 } else {
2225                         pos += scnprintf(buf + pos, bufsz - pos,
2226                                          "\tclosed_rb_num: Not Allocated\n");
2227                 }
2228         }
2229         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2230         kfree(buf);
2231
2232         return ret;
2233 }
2234
2235 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2236                                         char __user *user_buf,
2237                                         size_t count, loff_t *ppos)
2238 {
2239         struct iwl_trans *trans = file->private_data;
2240         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2241         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2242
2243         int pos = 0;
2244         char *buf;
2245         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2246         ssize_t ret;
2247
2248         buf = kzalloc(bufsz, GFP_KERNEL);
2249         if (!buf)
2250                 return -ENOMEM;
2251
2252         pos += scnprintf(buf + pos, bufsz - pos,
2253                         "Interrupt Statistics Report:\n");
2254
2255         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2256                 isr_stats->hw);
2257         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2258                 isr_stats->sw);
2259         if (isr_stats->sw || isr_stats->hw) {
2260                 pos += scnprintf(buf + pos, bufsz - pos,
2261                         "\tLast Restarting Code:  0x%X\n",
2262                         isr_stats->err_code);
2263         }
2264 #ifdef CONFIG_IWLWIFI_DEBUG
2265         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2266                 isr_stats->sch);
2267         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2268                 isr_stats->alive);
2269 #endif
2270         pos += scnprintf(buf + pos, bufsz - pos,
2271                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2272
2273         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2274                 isr_stats->ctkill);
2275
2276         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2277                 isr_stats->wakeup);
2278
2279         pos += scnprintf(buf + pos, bufsz - pos,
2280                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2281
2282         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2283                 isr_stats->tx);
2284
2285         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2286                 isr_stats->unhandled);
2287
2288         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2289         kfree(buf);
2290         return ret;
2291 }
2292
2293 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2294                                          const char __user *user_buf,
2295                                          size_t count, loff_t *ppos)
2296 {
2297         struct iwl_trans *trans = file->private_data;
2298         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2299         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2300
2301         char buf[8];
2302         int buf_size;
2303         u32 reset_flag;
2304
2305         memset(buf, 0, sizeof(buf));
2306         buf_size = min(count, sizeof(buf) -  1);
2307         if (copy_from_user(buf, user_buf, buf_size))
2308                 return -EFAULT;
2309         if (sscanf(buf, "%x", &reset_flag) != 1)
2310                 return -EFAULT;
2311         if (reset_flag == 0)
2312                 memset(isr_stats, 0, sizeof(*isr_stats));
2313
2314         return count;
2315 }
2316
2317 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2318                                    const char __user *user_buf,
2319                                    size_t count, loff_t *ppos)
2320 {
2321         struct iwl_trans *trans = file->private_data;
2322         char buf[8];
2323         int buf_size;
2324         int csr;
2325
2326         memset(buf, 0, sizeof(buf));
2327         buf_size = min(count, sizeof(buf) -  1);
2328         if (copy_from_user(buf, user_buf, buf_size))
2329                 return -EFAULT;
2330         if (sscanf(buf, "%d", &csr) != 1)
2331                 return -EFAULT;
2332
2333         iwl_pcie_dump_csr(trans);
2334
2335         return count;
2336 }
2337
2338 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2339                                      char __user *user_buf,
2340                                      size_t count, loff_t *ppos)
2341 {
2342         struct iwl_trans *trans = file->private_data;
2343         char *buf = NULL;
2344         ssize_t ret;
2345
2346         ret = iwl_dump_fh(trans, &buf);
2347         if (ret < 0)
2348                 return ret;
2349         if (!buf)
2350                 return -EINVAL;
2351         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2352         kfree(buf);
2353         return ret;
2354 }
2355
2356 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2357 DEBUGFS_READ_FILE_OPS(fh_reg);
2358 DEBUGFS_READ_FILE_OPS(rx_queue);
2359 DEBUGFS_READ_FILE_OPS(tx_queue);
2360 DEBUGFS_WRITE_FILE_OPS(csr);
2361
2362 /* Create the debugfs files and directories */
2363 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2364 {
2365         struct dentry *dir = trans->dbgfs_dir;
2366
2367         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2368         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2369         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2370         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2371         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2372         return 0;
2373
2374 err:
2375         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2376         return -ENOMEM;
2377 }
2378 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2379
2380 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2381 {
2382         u32 cmdlen = 0;
2383         int i;
2384
2385         for (i = 0; i < IWL_NUM_OF_TBS; i++)
2386                 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2387
2388         return cmdlen;
2389 }
2390
2391 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2392                                    struct iwl_fw_error_dump_data **data,
2393                                    int allocated_rb_nums)
2394 {
2395         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2396         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2397         /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2398         struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2399         u32 i, r, j, rb_len = 0;
2400
2401         spin_lock(&rxq->lock);
2402
2403         r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2404
2405         for (i = rxq->read, j = 0;
2406              i != r && j < allocated_rb_nums;
2407              i = (i + 1) & RX_QUEUE_MASK, j++) {
2408                 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2409                 struct iwl_fw_error_dump_rb *rb;
2410
2411                 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2412                                DMA_FROM_DEVICE);
2413
2414                 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2415
2416                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2417                 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2418                 rb = (void *)(*data)->data;
2419                 rb->index = cpu_to_le32(i);
2420                 memcpy(rb->data, page_address(rxb->page), max_len);
2421                 /* remap the page for the free benefit */
2422                 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2423                                                      max_len,
2424                                                      DMA_FROM_DEVICE);
2425
2426                 *data = iwl_fw_error_next_data(*data);
2427         }
2428
2429         spin_unlock(&rxq->lock);
2430
2431         return rb_len;
2432 }
2433 #define IWL_CSR_TO_DUMP (0x250)
2434
2435 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2436                                    struct iwl_fw_error_dump_data **data)
2437 {
2438         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2439         __le32 *val;
2440         int i;
2441
2442         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2443         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2444         val = (void *)(*data)->data;
2445
2446         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2447                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2448
2449         *data = iwl_fw_error_next_data(*data);
2450
2451         return csr_len;
2452 }
2453
2454 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2455                                        struct iwl_fw_error_dump_data **data)
2456 {
2457         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2458         unsigned long flags;
2459         __le32 *val;
2460         int i;
2461
2462         if (!iwl_trans_grab_nic_access(trans, &flags))
2463                 return 0;
2464
2465         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2466         (*data)->len = cpu_to_le32(fh_regs_len);
2467         val = (void *)(*data)->data;
2468
2469         for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2470                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2471
2472         iwl_trans_release_nic_access(trans, &flags);
2473
2474         *data = iwl_fw_error_next_data(*data);
2475
2476         return sizeof(**data) + fh_regs_len;
2477 }
2478
2479 static u32
2480 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2481                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2482                                  u32 monitor_len)
2483 {
2484         u32 buf_size_in_dwords = (monitor_len >> 2);
2485         u32 *buffer = (u32 *)fw_mon_data->data;
2486         unsigned long flags;
2487         u32 i;
2488
2489         if (!iwl_trans_grab_nic_access(trans, &flags))
2490                 return 0;
2491
2492         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2493         for (i = 0; i < buf_size_in_dwords; i++)
2494                 buffer[i] = iwl_read_prph_no_grab(trans,
2495                                 MON_DMARB_RD_DATA_ADDR);
2496         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2497
2498         iwl_trans_release_nic_access(trans, &flags);
2499
2500         return monitor_len;
2501 }
2502
2503 static u32
2504 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2505                             struct iwl_fw_error_dump_data **data,
2506                             u32 monitor_len)
2507 {
2508         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2509         u32 len = 0;
2510
2511         if ((trans_pcie->fw_mon_page &&
2512              trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2513             trans->dbg_dest_tlv) {
2514                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2515                 u32 base, write_ptr, wrap_cnt;
2516
2517                 /* If there was a dest TLV - use the values from there */
2518                 if (trans->dbg_dest_tlv) {
2519                         write_ptr =
2520                                 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2521                         wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2522                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2523                 } else {
2524                         base = MON_BUFF_BASE_ADDR;
2525                         write_ptr = MON_BUFF_WRPTR;
2526                         wrap_cnt = MON_BUFF_CYCLE_CNT;
2527                 }
2528
2529                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2530                 fw_mon_data = (void *)(*data)->data;
2531                 fw_mon_data->fw_mon_wr_ptr =
2532                         cpu_to_le32(iwl_read_prph(trans, write_ptr));
2533                 fw_mon_data->fw_mon_cycle_cnt =
2534                         cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2535                 fw_mon_data->fw_mon_base_ptr =
2536                         cpu_to_le32(iwl_read_prph(trans, base));
2537
2538                 len += sizeof(**data) + sizeof(*fw_mon_data);
2539                 if (trans_pcie->fw_mon_page) {
2540                         /*
2541                          * The firmware is now asserted, it won't write anything
2542                          * to the buffer. CPU can take ownership to fetch the
2543                          * data. The buffer will be handed back to the device
2544                          * before the firmware will be restarted.
2545                          */
2546                         dma_sync_single_for_cpu(trans->dev,
2547                                                 trans_pcie->fw_mon_phys,
2548                                                 trans_pcie->fw_mon_size,
2549                                                 DMA_FROM_DEVICE);
2550                         memcpy(fw_mon_data->data,
2551                                page_address(trans_pcie->fw_mon_page),
2552                                trans_pcie->fw_mon_size);
2553
2554                         monitor_len = trans_pcie->fw_mon_size;
2555                 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2556                         /*
2557                          * Update pointers to reflect actual values after
2558                          * shifting
2559                          */
2560                         base = iwl_read_prph(trans, base) <<
2561                                trans->dbg_dest_tlv->base_shift;
2562                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
2563                                            monitor_len / sizeof(u32));
2564                 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2565                         monitor_len =
2566                                 iwl_trans_pci_dump_marbh_monitor(trans,
2567                                                                  fw_mon_data,
2568                                                                  monitor_len);
2569                 } else {
2570                         /* Didn't match anything - output no monitor data */
2571                         monitor_len = 0;
2572                 }
2573
2574                 len += monitor_len;
2575                 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2576         }
2577
2578         return len;
2579 }
2580
2581 static struct iwl_trans_dump_data
2582 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2583                           const struct iwl_fw_dbg_trigger_tlv *trigger)
2584 {
2585         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2586         struct iwl_fw_error_dump_data *data;
2587         struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2588         struct iwl_fw_error_dump_txcmd *txcmd;
2589         struct iwl_trans_dump_data *dump_data;
2590         u32 len, num_rbs;
2591         u32 monitor_len;
2592         int i, ptr;
2593         bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2594                         !trans->cfg->mq_rx_supported;
2595
2596         /* transport dump header */
2597         len = sizeof(*dump_data);
2598
2599         /* host commands */
2600         len += sizeof(*data) +
2601                 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2602
2603         /* FW monitor */
2604         if (trans_pcie->fw_mon_page) {
2605                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2606                        trans_pcie->fw_mon_size;
2607                 monitor_len = trans_pcie->fw_mon_size;
2608         } else if (trans->dbg_dest_tlv) {
2609                 u32 base, end;
2610
2611                 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2612                 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2613
2614                 base = iwl_read_prph(trans, base) <<
2615                        trans->dbg_dest_tlv->base_shift;
2616                 end = iwl_read_prph(trans, end) <<
2617                       trans->dbg_dest_tlv->end_shift;
2618
2619                 /* Make "end" point to the actual end */
2620                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2621                     trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2622                         end += (1 << trans->dbg_dest_tlv->end_shift);
2623                 monitor_len = end - base;
2624                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2625                        monitor_len;
2626         } else {
2627                 monitor_len = 0;
2628         }
2629
2630         if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2631                 dump_data = vzalloc(len);
2632                 if (!dump_data)
2633                         return NULL;
2634
2635                 data = (void *)dump_data->data;
2636                 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2637                 dump_data->len = len;
2638
2639                 return dump_data;
2640         }
2641
2642         /* CSR registers */
2643         len += sizeof(*data) + IWL_CSR_TO_DUMP;
2644
2645         /* FH registers */
2646         len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2647
2648         if (dump_rbs) {
2649                 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2650                 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2651                 /* RBs */
2652                 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
2653                                       & 0x0FFF;
2654                 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
2655                 len += num_rbs * (sizeof(*data) +
2656                                   sizeof(struct iwl_fw_error_dump_rb) +
2657                                   (PAGE_SIZE << trans_pcie->rx_page_order));
2658         }
2659
2660         dump_data = vzalloc(len);
2661         if (!dump_data)
2662                 return NULL;
2663
2664         len = 0;
2665         data = (void *)dump_data->data;
2666         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2667         txcmd = (void *)data->data;
2668         spin_lock_bh(&cmdq->lock);
2669         ptr = cmdq->q.write_ptr;
2670         for (i = 0; i < cmdq->q.n_window; i++) {
2671                 u8 idx = get_cmd_index(&cmdq->q, ptr);
2672                 u32 caplen, cmdlen;
2673
2674                 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2675                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2676
2677                 if (cmdlen) {
2678                         len += sizeof(*txcmd) + caplen;
2679                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2680                         txcmd->caplen = cpu_to_le32(caplen);
2681                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2682                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2683                 }
2684
2685                 ptr = iwl_queue_dec_wrap(ptr);
2686         }
2687         spin_unlock_bh(&cmdq->lock);
2688
2689         data->len = cpu_to_le32(len);
2690         len += sizeof(*data);
2691         data = iwl_fw_error_next_data(data);
2692
2693         len += iwl_trans_pcie_dump_csr(trans, &data);
2694         len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2695         if (dump_rbs)
2696                 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
2697
2698         len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2699
2700         dump_data->len = len;
2701
2702         return dump_data;
2703 }
2704
2705 #ifdef CONFIG_PM_SLEEP
2706 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2707 {
2708         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2709                 return iwl_pci_fw_enter_d0i3(trans);
2710
2711         return 0;
2712 }
2713
2714 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
2715 {
2716         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2717                 iwl_pci_fw_exit_d0i3(trans);
2718 }
2719 #endif /* CONFIG_PM_SLEEP */
2720
2721 static const struct iwl_trans_ops trans_ops_pcie = {
2722         .start_hw = iwl_trans_pcie_start_hw,
2723         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2724         .fw_alive = iwl_trans_pcie_fw_alive,
2725         .start_fw = iwl_trans_pcie_start_fw,
2726         .stop_device = iwl_trans_pcie_stop_device,
2727
2728         .d3_suspend = iwl_trans_pcie_d3_suspend,
2729         .d3_resume = iwl_trans_pcie_d3_resume,
2730
2731 #ifdef CONFIG_PM_SLEEP
2732         .suspend = iwl_trans_pcie_suspend,
2733         .resume = iwl_trans_pcie_resume,
2734 #endif /* CONFIG_PM_SLEEP */
2735
2736         .send_cmd = iwl_trans_pcie_send_hcmd,
2737
2738         .tx = iwl_trans_pcie_tx,
2739         .reclaim = iwl_trans_pcie_reclaim,
2740
2741         .txq_disable = iwl_trans_pcie_txq_disable,
2742         .txq_enable = iwl_trans_pcie_txq_enable,
2743
2744         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2745         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2746         .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
2747
2748         .write8 = iwl_trans_pcie_write8,
2749         .write32 = iwl_trans_pcie_write32,
2750         .read32 = iwl_trans_pcie_read32,
2751         .read_prph = iwl_trans_pcie_read_prph,
2752         .write_prph = iwl_trans_pcie_write_prph,
2753         .read_mem = iwl_trans_pcie_read_mem,
2754         .write_mem = iwl_trans_pcie_write_mem,
2755         .configure = iwl_trans_pcie_configure,
2756         .set_pmi = iwl_trans_pcie_set_pmi,
2757         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2758         .release_nic_access = iwl_trans_pcie_release_nic_access,
2759         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2760
2761         .ref = iwl_trans_pcie_ref,
2762         .unref = iwl_trans_pcie_unref,
2763
2764         .dump_data = iwl_trans_pcie_dump_data,
2765 };
2766
2767 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2768                                        const struct pci_device_id *ent,
2769                                        const struct iwl_cfg *cfg)
2770 {
2771         struct iwl_trans_pcie *trans_pcie;
2772         struct iwl_trans *trans;
2773         int ret, addr_size;
2774
2775         trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2776                                 &pdev->dev, cfg, &trans_ops_pcie, 0);
2777         if (!trans)
2778                 return ERR_PTR(-ENOMEM);
2779
2780         trans->max_skb_frags = IWL_PCIE_MAX_FRAGS;
2781
2782         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2783
2784         trans_pcie->trans = trans;
2785         spin_lock_init(&trans_pcie->irq_lock);
2786         spin_lock_init(&trans_pcie->reg_lock);
2787         mutex_init(&trans_pcie->mutex);
2788         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2789         trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
2790         if (!trans_pcie->tso_hdr_page) {
2791                 ret = -ENOMEM;
2792                 goto out_no_pci;
2793         }
2794
2795         ret = pci_enable_device(pdev);
2796         if (ret)
2797                 goto out_no_pci;
2798
2799         if (!cfg->base_params->pcie_l1_allowed) {
2800                 /*
2801                  * W/A - seems to solve weird behavior. We need to remove this
2802                  * if we don't want to stay in L1 all the time. This wastes a
2803                  * lot of power.
2804                  */
2805                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2806                                        PCIE_LINK_STATE_L1 |
2807                                        PCIE_LINK_STATE_CLKPM);
2808         }
2809
2810         if (cfg->mq_rx_supported)
2811                 addr_size = 64;
2812         else
2813                 addr_size = 36;
2814
2815         pci_set_master(pdev);
2816
2817         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
2818         if (!ret)
2819                 ret = pci_set_consistent_dma_mask(pdev,
2820                                                   DMA_BIT_MASK(addr_size));
2821         if (ret) {
2822                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2823                 if (!ret)
2824                         ret = pci_set_consistent_dma_mask(pdev,
2825                                                           DMA_BIT_MASK(32));
2826                 /* both attempts failed: */
2827                 if (ret) {
2828                         dev_err(&pdev->dev, "No suitable DMA available\n");
2829                         goto out_pci_disable_device;
2830                 }
2831         }
2832
2833         ret = pci_request_regions(pdev, DRV_NAME);
2834         if (ret) {
2835                 dev_err(&pdev->dev, "pci_request_regions failed\n");
2836                 goto out_pci_disable_device;
2837         }
2838
2839         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2840         if (!trans_pcie->hw_base) {
2841                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2842                 ret = -ENODEV;
2843                 goto out_pci_release_regions;
2844         }
2845
2846         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2847          * PCI Tx retries from interfering with C3 CPU state */
2848         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2849
2850         trans->dev = &pdev->dev;
2851         trans_pcie->pci_dev = pdev;
2852         iwl_disable_interrupts(trans);
2853
2854         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2855         /*
2856          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2857          * changed, and now the revision step also includes bit 0-1 (no more
2858          * "dash" value). To keep hw_rev backwards compatible - we'll store it
2859          * in the old format.
2860          */
2861         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2862                 unsigned long flags;
2863
2864                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2865                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2866
2867                 ret = iwl_pcie_prepare_card_hw(trans);
2868                 if (ret) {
2869                         IWL_WARN(trans, "Exit HW not ready\n");
2870                         goto out_pci_disable_msi;
2871                 }
2872
2873                 /*
2874                  * in-order to recognize C step driver should read chip version
2875                  * id located at the AUX bus MISC address space.
2876                  */
2877                 iwl_set_bit(trans, CSR_GP_CNTRL,
2878                             CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2879                 udelay(2);
2880
2881                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2882                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2883                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2884                                    25000);
2885                 if (ret < 0) {
2886                         IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2887                         goto out_pci_disable_msi;
2888                 }
2889
2890                 if (iwl_trans_grab_nic_access(trans, &flags)) {
2891                         u32 hw_step;
2892
2893                         hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
2894                         hw_step |= ENABLE_WFPM;
2895                         iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
2896                         hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
2897                         hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2898                         if (hw_step == 0x3)
2899                                 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2900                                                 (SILICON_C_STEP << 2);
2901                         iwl_trans_release_nic_access(trans, &flags);
2902                 }
2903         }
2904
2905         trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
2906
2907         iwl_pcie_set_interrupt_capa(pdev, trans);
2908         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2909         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2910                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2911
2912         /* Initialize the wait queue for commands */
2913         init_waitqueue_head(&trans_pcie->wait_command_queue);
2914
2915         init_waitqueue_head(&trans_pcie->d0i3_waitq);
2916
2917         if (trans_pcie->msix_enabled) {
2918                 if (iwl_pcie_init_msix_handler(pdev, trans_pcie))
2919                         goto out_pci_release_regions;
2920          } else {
2921                 ret = iwl_pcie_alloc_ict(trans);
2922                 if (ret)
2923                         goto out_pci_disable_msi;
2924
2925                 ret = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2926                                            iwl_pcie_irq_handler,
2927                                            IRQF_SHARED, DRV_NAME, trans);
2928                 if (ret) {
2929                         IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2930                         goto out_free_ict;
2931                 }
2932                 trans_pcie->inta_mask = CSR_INI_SET_MASK;
2933          }
2934
2935 #ifdef CONFIG_IWLWIFI_PCIE_RTPM
2936         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
2937 #else
2938         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
2939 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */
2940
2941         return trans;
2942
2943 out_free_ict:
2944         iwl_pcie_free_ict(trans);
2945 out_pci_disable_msi:
2946         pci_disable_msi(pdev);
2947 out_pci_release_regions:
2948         pci_release_regions(pdev);
2949 out_pci_disable_device:
2950         pci_disable_device(pdev);
2951 out_no_pci:
2952         free_percpu(trans_pcie->tso_hdr_page);
2953         iwl_trans_free(trans);
2954         return ERR_PTR(ret);
2955 }