drivers/net/wireless/intel/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2016 Intel Deutschland GmbH
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of version 2 of the GNU General Public License as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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  22  * along with this program; if not, write to the Free Software
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  27  * in the file called COPYING.
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  29  * Contact Information:
  30  *  Intel Linux Wireless <linuxwifi@intel.com>
  31  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  32  *
  33  * BSD LICENSE
  34  *
  35  * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
  36  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  37  * Copyright(c) 2016 Intel Deutschland GmbH
  38  * All rights reserved.
  39  *
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  41  * modification, are permitted provided that the following conditions
  42  * are met:
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  44  *  * Redistributions of source code must retain the above copyright
  45  *    notice, this list of conditions and the following disclaimer.
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  49  *    distribution.
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  51  *    contributors may be used to endorse or promote products derived
  52  *    from this software without specific prior written permission.
  53  *
  54  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  55  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  56  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  57  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  58  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  60  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  61  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  63  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  64  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  65  *
  66  *****************************************************************************/
  67 #include <linux/pci.h>
  68 #include <linux/pci-aspm.h>
  69 #include <linux/interrupt.h>
  70 #include <linux/debugfs.h>
  71 #include <linux/sched.h>
  72 #include <linux/bitops.h>
  73 #include <linux/gfp.h>
  74 #include <linux/vmalloc.h>
  75 #include <linux/pm_runtime.h>
  76
  77 #include "iwl-drv.h"
  78 #include "iwl-trans.h"
  79 #include "iwl-csr.h"
  80 #include "iwl-prph.h"
  81 #include "iwl-scd.h"
  82 #include "iwl-agn-hw.h"
  83 #include "iwl-fw-error-dump.h"
  84 #include "internal.h"
  85 #include "iwl-fh.h"
  86
  87 /* extended range in FW SRAM */
  88 #define IWL_FW_MEM_EXTENDED_START       0x40000
  89 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  90
  91 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
  92 {
  93         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  94
  95         if (!trans_pcie->fw_mon_page)
  96                 return;
  97
  98         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
  99                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
 100         __free_pages(trans_pcie->fw_mon_page,
 101                      get_order(trans_pcie->fw_mon_size));
 102         trans_pcie->fw_mon_page = NULL;
 103         trans_pcie->fw_mon_phys = 0;
 104         trans_pcie->fw_mon_size = 0;
 105 }
 106
 107 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 108 {
 109         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 110         struct page *page = NULL;
 111         dma_addr_t phys;
 112         u32 size = 0;
 113         u8 power;
 114
 115         if (!max_power) {
 116                 /* default max_power is maximum */
 117                 max_power = 26;
 118         } else {
 119                 max_power += 11;
 120         }
 121
 122         if (WARN(max_power > 26,
 123                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 124                  max_power))
 125                 return;
 126
 127         if (trans_pcie->fw_mon_page) {
 128                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 129                                            trans_pcie->fw_mon_size,
 130                                            DMA_FROM_DEVICE);
 131                 return;
 132         }
 133
 134         phys = 0;
 135         for (power = max_power; power >= 11; power--) {
 136                 int order;
 137
 138                 size = BIT(power);
 139                 order = get_order(size);
 140                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 141                                    order);
 142                 if (!page)
 143                         continue;
 144
 145                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 146                                     DMA_FROM_DEVICE);
 147                 if (dma_mapping_error(trans->dev, phys)) {
 148                         __free_pages(page, order);
 149                         page = NULL;
 150                         continue;
 151                 }
 152                 IWL_INFO(trans,
 153                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 154                          size, order);
 155                 break;
 156         }
 157
 158         if (WARN_ON_ONCE(!page))
 159                 return;
 160
 161         if (power != max_power)
 162                 IWL_ERR(trans,
 163                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 164                         (unsigned long)BIT(power - 10),
 165                         (unsigned long)BIT(max_power - 10));
 166
 167         trans_pcie->fw_mon_page = page;
 168         trans_pcie->fw_mon_phys = phys;
 169         trans_pcie->fw_mon_size = size;
 170 }
 171
 172 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 173 {
 174         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 175                     ((reg & 0x0000ffff) | (2 << 28)));
 176         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 177 }
 178
 179 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 180 {
 181         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 182         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 183                     ((reg & 0x0000ffff) | (3 << 28)));
 184 }
 185
 186 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 187 {
 188         if (trans->cfg->apmg_not_supported)
 189                 return;
 190
 191         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 192                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 193                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 194                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 195         else
 196                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 197                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 198                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 199 }
 200
 201 /* PCI registers */
 202 #define PCI_CFG_RETRY_TIMEOUT   0x041
 203
 204 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 205 {
 206         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 207         u16 lctl;
 208         u16 cap;
 209
 210         /*
 211          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 212          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 213          * If so (likely), disable L0S, so device moves directly L0->L1;
 214          *    costs negligible amount of power savings.
 215          * If not (unlikely), enable L0S, so there is at least some
 216          *    power savings, even without L1.
 217          */
 218         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 219         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 220                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 221         else
 222                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 223         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 224
 225         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 226         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 227         dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
 228                  (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 229                  trans->ltr_enabled ? "En" : "Dis");
 230 }
 231
 232 /*
 233  * Start up NIC's basic functionality after it has been reset
 234  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 235  * NOTE:  This does not load uCode nor start the embedded processor
 236  */
 237 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 238 {
 239         int ret = 0;
 240         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 241
 242         /*
 243          * Use "set_bit" below rather than "write", to preserve any hardware
 244          * bits already set by default after reset.
 245          */
 246
 247         /* Disable L0S exit timer (platform NMI Work/Around) */
 248         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 249                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 250                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 251
 252         /*
 253          * Disable L0s without affecting L1;
 254          *  don't wait for ICH L0s (ICH bug W/A)
 255          */
 256         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 257                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 258
 259         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 260         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 261
 262         /*
 263          * Enable HAP INTA (interrupt from management bus) to
 264          * wake device's PCI Express link L1a -> L0s
 265          */
 266         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 267                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 268
 269         iwl_pcie_apm_config(trans);
 270
 271         /* Configure analog phase-lock-loop before activating to D0A */
 272         if (trans->cfg->base_params->pll_cfg_val)
 273                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 274                             trans->cfg->base_params->pll_cfg_val);
 275
 276         /*
 277          * Set "initialization complete" bit to move adapter from
 278          * D0U* --> D0A* (powered-up active) state.
 279          */
 280         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 281
 282         /*
 283          * Wait for clock stabilization; once stabilized, access to
 284          * device-internal resources is supported, e.g. iwl_write_prph()
 285          * and accesses to uCode SRAM.
 286          */
 287         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 288                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 289                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 290         if (ret < 0) {
 291                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 292                 goto out;
 293         }
 294
 295         if (trans->cfg->host_interrupt_operation_mode) {
 296                 /*
 297                  * This is a bit of an abuse - This is needed for 7260 / 3160
 298                  * only check host_interrupt_operation_mode even if this is
 299                  * not related to host_interrupt_operation_mode.
 300                  *
 301                  * Enable the oscillator to count wake up time for L1 exit. This
 302                  * consumes slightly more power (100uA) - but allows to be sure
 303                  * that we wake up from L1 on time.
 304                  *
 305                  * This looks weird: read twice the same register, discard the
 306                  * value, set a bit, and yet again, read that same register
 307                  * just to discard the value. But that's the way the hardware
 308                  * seems to like it.
 309                  */
 310                 iwl_read_prph(trans, OSC_CLK);
 311                 iwl_read_prph(trans, OSC_CLK);
 312                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 313                 iwl_read_prph(trans, OSC_CLK);
 314                 iwl_read_prph(trans, OSC_CLK);
 315         }
 316
 317         /*
 318          * Enable DMA clock and wait for it to stabilize.
 319          *
 320          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 321          * bits do not disable clocks.  This preserves any hardware
 322          * bits already set by default in "CLK_CTRL_REG" after reset.
 323          */
 324         if (!trans->cfg->apmg_not_supported) {
 325                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 326                                APMG_CLK_VAL_DMA_CLK_RQT);
 327                 udelay(20);
 328
 329                 /* Disable L1-Active */
 330                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 331                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 332
 333                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 334                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 335                                APMG_RTC_INT_STT_RFKILL);
 336         }
 337
 338         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 339
 340 out:
 341         return ret;
 342 }
 343
 344 /*
 345  * Enable LP XTAL to avoid HW bug where device may consume much power if
 346  * FW is not loaded after device reset. LP XTAL is disabled by default
 347  * after device HW reset. Do it only if XTAL is fed by internal source.
 348  * Configure device's "persistence" mode to avoid resetting XTAL again when
 349  * SHRD_HW_RST occurs in S3.
 350  */
 351 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 352 {
 353         int ret;
 354         u32 apmg_gp1_reg;
 355         u32 apmg_xtal_cfg_reg;
 356         u32 dl_cfg_reg;
 357
 358         /* Force XTAL ON */
 359         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 360                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 361
 362         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 363         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 364
 365         udelay(10);
 366
 367         /*
 368          * Set "initialization complete" bit to move adapter from
 369          * D0U* --> D0A* (powered-up active) state.
 370          */
 371         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 372
 373         /*
 374          * Wait for clock stabilization; once stabilized, access to
 375          * device-internal resources is possible.
 376          */
 377         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 378                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 379                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 380                            25000);
 381         if (WARN_ON(ret < 0)) {
 382                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 383                 /* Release XTAL ON request */
 384                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 385                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 386                 return;
 387         }
 388
 389         /*
 390          * Clear "disable persistence" to avoid LP XTAL resetting when
 391          * SHRD_HW_RST is applied in S3.
 392          */
 393         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 394                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 395
 396         /*
 397          * Force APMG XTAL to be active to prevent its disabling by HW
 398          * caused by APMG idle state.
 399          */
 400         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 401                                                     SHR_APMG_XTAL_CFG_REG);
 402         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 403                                  apmg_xtal_cfg_reg |
 404                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 405
 406         /*
 407          * Reset entire device again - do controller reset (results in
 408          * SHRD_HW_RST). Turn MAC off before proceeding.
 409          */
 410         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 411
 412         udelay(10);
 413
 414         /* Enable LP XTAL by indirect access through CSR */
 415         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 416         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 417                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 418                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 419
 420         /* Clear delay line clock power up */
 421         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 422         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 423                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 424
 425         /*
 426          * Enable persistence mode to avoid LP XTAL resetting when
 427          * SHRD_HW_RST is applied in S3.
 428          */
 429         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 430                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 431
 432         /*
 433          * Clear "initialization complete" bit to move adapter from
 434          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 435          */
 436         iwl_clear_bit(trans, CSR_GP_CNTRL,
 437                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 438
 439         /* Activates XTAL resources monitor */
 440         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 441                                  CSR_MONITOR_XTAL_RESOURCES);
 442
 443         /* Release XTAL ON request */
 444         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 445                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 446         udelay(10);
 447
 448         /* Release APMG XTAL */
 449         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 450                                  apmg_xtal_cfg_reg &
 451                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 452 }
 453
 454 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 455 {
 456         int ret = 0;
 457
 458         /* stop device's busmaster DMA activity */
 459         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 460
 461         ret = iwl_poll_bit(trans, CSR_RESET,
 462                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 463                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 464         if (ret < 0)
 465                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 466
 467         IWL_DEBUG_INFO(trans, "stop master\n");
 468
 469         return ret;
 470 }
 471
 472 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 473 {
 474         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 475
 476         if (op_mode_leave) {
 477                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 478                         iwl_pcie_apm_init(trans);
 479
 480                 /* inform ME that we are leaving */
 481                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 482                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 483                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 484                 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
 485                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 486                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 487                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 488                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 489                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 490                         mdelay(1);
 491                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 492                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 493                 }
 494                 mdelay(5);
 495         }
 496
 497         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 498
 499         /* Stop device's DMA activity */
 500         iwl_pcie_apm_stop_master(trans);
 501
 502         if (trans->cfg->lp_xtal_workaround) {
 503                 iwl_pcie_apm_lp_xtal_enable(trans);
 504                 return;
 505         }
 506
 507         /* Reset the entire device */
 508         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 509
 510         udelay(10);
 511
 512         /*
 513          * Clear "initialization complete" bit to move adapter from
 514          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 515          */
 516         iwl_clear_bit(trans, CSR_GP_CNTRL,
 517                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 518 }
 519
 520 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 521 {
 522         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 523
 524         /* nic_init */
 525         spin_lock(&trans_pcie->irq_lock);
 526         iwl_pcie_apm_init(trans);
 527
 528         spin_unlock(&trans_pcie->irq_lock);
 529
 530         iwl_pcie_set_pwr(trans, false);
 531
 532         iwl_op_mode_nic_config(trans->op_mode);
 533
 534         /* Allocate the RX queue, or reset if it is already allocated */
 535         iwl_pcie_rx_init(trans);
 536
 537         /* Allocate or reset and init all Tx and Command queues */
 538         if (iwl_pcie_tx_init(trans))
 539                 return -ENOMEM;
 540
 541         if (trans->cfg->base_params->shadow_reg_enable) {
 542                 /* enable shadow regs in HW */
 543                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 544                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 545         }
 546
 547         return 0;
 548 }
 549
 550 #define HW_READY_TIMEOUT (50)
 551
 552 /* Note: returns poll_bit return value, which is >= 0 if success */
 553 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 554 {
 555         int ret;
 556
 557         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 558                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 559
 560         /* See if we got it */
 561         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 562                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 563                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 564                            HW_READY_TIMEOUT);
 565
 566         if (ret >= 0)
 567                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 568
 569         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 570         return ret;
 571 }
 572
 573 /* Note: returns standard 0/-ERROR code */
 574 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 575 {
 576         int ret;
 577         int t = 0;
 578         int iter;
 579
 580         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 581
 582         ret = iwl_pcie_set_hw_ready(trans);
 583         /* If the card is ready, exit 0 */
 584         if (ret >= 0)
 585                 return 0;
 586
 587         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 588                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 589         msleep(1);
 590
 591         for (iter = 0; iter < 10; iter++) {
 592                 /* If HW is not ready, prepare the conditions to check again */
 593                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 594                             CSR_HW_IF_CONFIG_REG_PREPARE);
 595
 596                 do {
 597                         ret = iwl_pcie_set_hw_ready(trans);
 598                         if (ret >= 0)
 599                                 return 0;
 600
 601                         usleep_range(200, 1000);
 602                         t += 200;
 603                 } while (t < 150000);
 604                 msleep(25);
 605         }
 606
 607         IWL_ERR(trans, "Couldn't prepare the card\n");
 608
 609         return ret;
 610 }
 611
 612 /*
 613  * ucode
 614  */
 615 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 616                                    dma_addr_t phy_addr, u32 byte_cnt)
 617 {
 618         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 619         unsigned long flags;
 620         int ret;
 621
 622         trans_pcie->ucode_write_complete = false;
 623
 624         if (!iwl_trans_grab_nic_access(trans, &flags))
 625                 return -EIO;
 626
 627         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 628                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 629
 630         iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 631                     dst_addr);
 632
 633         iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 634                     phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 635
 636         iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 637                     (iwl_get_dma_hi_addr(phy_addr)
 638                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 639
 640         iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 641                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
 642                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
 643                     FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 644
 645         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 646                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 647                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 648                     FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 649
 650         iwl_trans_release_nic_access(trans, &flags);
 651
 652         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 653                                  trans_pcie->ucode_write_complete, 5 * HZ);
 654         if (!ret) {
 655                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 656                 return -ETIMEDOUT;
 657         }
 658
 659         return 0;
 660 }
 661
 662 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 663                             const struct fw_desc *section)
 664 {
 665         u8 *v_addr;
 666         dma_addr_t p_addr;
 667         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 668         int ret = 0;
 669
 670         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 671                      section_num);
 672
 673         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 674                                     GFP_KERNEL | __GFP_NOWARN);
 675         if (!v_addr) {
 676                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 677                 chunk_sz = PAGE_SIZE;
 678                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 679                                             &p_addr, GFP_KERNEL);
 680                 if (!v_addr)
 681                         return -ENOMEM;
 682         }
 683
 684         for (offset = 0; offset < section->len; offset += chunk_sz) {
 685                 u32 copy_size, dst_addr;
 686                 bool extended_addr = false;
 687
 688                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 689                 dst_addr = section->offset + offset;
 690
 691                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 692                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 693                         extended_addr = true;
 694
 695                 if (extended_addr)
 696                         iwl_set_bits_prph(trans, LMPM_CHICK,
 697                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 698
 699                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 700                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 701                                                    copy_size);
 702
 703                 if (extended_addr)
 704                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 705                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 706
 707                 if (ret) {
 708                         IWL_ERR(trans,
 709                                 "Could not load the [%d] uCode section\n",
 710                                 section_num);
 711                         break;
 712                 }
 713         }
 714
 715         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 716         return ret;
 717 }
 718
 719 /*
 720  * Driver Takes the ownership on secure machine before FW load
 721  * and prevent race with the BT load.
 722  * W/A for ROM bug. (should be remove in the next Si step)
 723  */
 724 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
 725 {
 726         u32 val, loop = 1000;
 727
 728         /*
 729          * Check the RSA semaphore is accessible.
 730          * If the HW isn't locked and the rsa semaphore isn't accessible,
 731          * we are in trouble.
 732          */
 733         val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
 734         if (val & (BIT(1) | BIT(17))) {
 735                 IWL_INFO(trans,
 736                          "can't access the RSA semaphore it is write protected\n");
 737                 return 0;
 738         }
 739
 740         /* take ownership on the AUX IF */
 741         iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
 742         iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
 743
 744         do {
 745                 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
 746                 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
 747                 if (val == 0x1) {
 748                         iwl_write_prph(trans, RSA_ENABLE, 0);
 749                         return 0;
 750                 }
 751
 752                 udelay(10);
 753                 loop--;
 754         } while (loop > 0);
 755
 756         IWL_ERR(trans, "Failed to take ownership on secure machine\n");
 757         return -EIO;
 758 }
 759
 760 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 761                                            const struct fw_img *image,
 762                                            int cpu,
 763                                            int *first_ucode_section)
 764 {
 765         int shift_param;
 766         int i, ret = 0, sec_num = 0x1;
 767         u32 val, last_read_idx = 0;
 768
 769         if (cpu == 1) {
 770                 shift_param = 0;
 771                 *first_ucode_section = 0;
 772         } else {
 773                 shift_param = 16;
 774                 (*first_ucode_section)++;
 775         }
 776
 777         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 778                 last_read_idx = i;
 779
 780                 /*
 781                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 782                  * CPU1 to CPU2.
 783                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 784                  * CPU2 non paged to CPU2 paging sec.
 785                  */
 786                 if (!image->sec[i].data ||
 787                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 788                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 789                         IWL_DEBUG_FW(trans,
 790                                      "Break since Data not valid or Empty section, sec = %d\n",
 791                                      i);
 792                         break;
 793                 }
 794
 795                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 796                 if (ret)
 797                         return ret;
 798
 799                 /* Notify the ucode of the loaded section number and status */
 800                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 801                 val = val | (sec_num << shift_param);
 802                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 803                 sec_num = (sec_num << 1) | 0x1;
 804         }
 805
 806         *first_ucode_section = last_read_idx;
 807
 808         if (cpu == 1)
 809                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
 810         else
 811                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
 812
 813         return 0;
 814 }
 815
 816 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 817                                       const struct fw_img *image,
 818                                       int cpu,
 819                                       int *first_ucode_section)
 820 {
 821         int shift_param;
 822         int i, ret = 0;
 823         u32 last_read_idx = 0;
 824
 825         if (cpu == 1) {
 826                 shift_param = 0;
 827                 *first_ucode_section = 0;
 828         } else {
 829                 shift_param = 16;
 830                 (*first_ucode_section)++;
 831         }
 832
 833         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 834                 last_read_idx = i;
 835
 836                 /*
 837                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 838                  * CPU1 to CPU2.
 839                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 840                  * CPU2 non paged to CPU2 paging sec.
 841                  */
 842                 if (!image->sec[i].data ||
 843                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 844                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 845                         IWL_DEBUG_FW(trans,
 846                                      "Break since Data not valid or Empty section, sec = %d\n",
 847                                      i);
 848                         break;
 849                 }
 850
 851                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 852                 if (ret)
 853                         return ret;
 854         }
 855
 856         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 857                 iwl_set_bits_prph(trans,
 858                                   CSR_UCODE_LOAD_STATUS_ADDR,
 859                                   (LMPM_CPU_UCODE_LOADING_COMPLETED |
 860                                    LMPM_CPU_HDRS_LOADING_COMPLETED |
 861                                    LMPM_CPU_UCODE_LOADING_STARTED) <<
 862                                         shift_param);
 863
 864         *first_ucode_section = last_read_idx;
 865
 866         return 0;
 867 }
 868
 869 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
 870 {
 871         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 872         const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
 873         int i;
 874
 875         if (dest->version)
 876                 IWL_ERR(trans,
 877                         "DBG DEST version is %d - expect issues\n",
 878                         dest->version);
 879
 880         IWL_INFO(trans, "Applying debug destination %s\n",
 881                  get_fw_dbg_mode_string(dest->monitor_mode));
 882
 883         if (dest->monitor_mode == EXTERNAL_MODE)
 884                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 885         else
 886                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 887
 888         for (i = 0; i < trans->dbg_dest_reg_num; i++) {
 889                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 890                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 891
 892                 switch (dest->reg_ops[i].op) {
 893                 case CSR_ASSIGN:
 894                         iwl_write32(trans, addr, val);
 895                         break;
 896                 case CSR_SETBIT:
 897                         iwl_set_bit(trans, addr, BIT(val));
 898                         break;
 899                 case CSR_CLEARBIT:
 900                         iwl_clear_bit(trans, addr, BIT(val));
 901                         break;
 902                 case PRPH_ASSIGN:
 903                         iwl_write_prph(trans, addr, val);
 904                         break;
 905                 case PRPH_SETBIT:
 906                         iwl_set_bits_prph(trans, addr, BIT(val));
 907                         break;
 908                 case PRPH_CLEARBIT:
 909                         iwl_clear_bits_prph(trans, addr, BIT(val));
 910                         break;
 911                 case PRPH_BLOCKBIT:
 912                         if (iwl_read_prph(trans, addr) & BIT(val)) {
 913                                 IWL_ERR(trans,
 914                                         "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
 915                                         val, addr);
 916                                 goto monitor;
 917                         }
 918                         break;
 919                 default:
 920                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 921                                 dest->reg_ops[i].op);
 922                         break;
 923                 }
 924         }
 925
 926 monitor:
 927         if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
 928                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 929                                trans_pcie->fw_mon_phys >> dest->base_shift);
 930                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 931                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 932                                        (trans_pcie->fw_mon_phys +
 933                                         trans_pcie->fw_mon_size - 256) >>
 934                                                 dest->end_shift);
 935                 else
 936                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 937                                        (trans_pcie->fw_mon_phys +
 938                                         trans_pcie->fw_mon_size) >>
 939                                                 dest->end_shift);
 940         }
 941 }
 942
 943 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 944                                 const struct fw_img *image)
 945 {
 946         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 947         int ret = 0;
 948         int first_ucode_section;
 949
 950         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 951                      image->is_dual_cpus ? "Dual" : "Single");
 952
 953         /* load to FW the binary non secured sections of CPU1 */
 954         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
 955         if (ret)
 956                 return ret;
 957
 958         if (image->is_dual_cpus) {
 959                 /* set CPU2 header address */
 960                 iwl_write_prph(trans,
 961                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
 962                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 963
 964                 /* load to FW the binary sections of CPU2 */
 965                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
 966                                                  &first_ucode_section);
 967                 if (ret)
 968                         return ret;
 969         }
 970
 971         /* supported for 7000 only for the moment */
 972         if (iwlwifi_mod_params.fw_monitor &&
 973             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
 974                 iwl_pcie_alloc_fw_monitor(trans, 0);
 975
 976                 if (trans_pcie->fw_mon_size) {
 977                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
 978                                        trans_pcie->fw_mon_phys >> 4);
 979                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
 980                                        (trans_pcie->fw_mon_phys +
 981                                         trans_pcie->fw_mon_size) >> 4);
 982                 }
 983         } else if (trans->dbg_dest_tlv) {
 984                 iwl_pcie_apply_destination(trans);
 985         }
 986
 987         /* release CPU reset */
 988         iwl_write32(trans, CSR_RESET, 0);
 989
 990         return 0;
 991 }
 992
 993 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
 994                                           const struct fw_img *image)
 995 {
 996         int ret = 0;
 997         int first_ucode_section;
 998
 999         IWL_DEBUG_FW(trans, "working with %s CPU\n",
1000                      image->is_dual_cpus ? "Dual" : "Single");
1001
1002         if (trans->dbg_dest_tlv)
1003                 iwl_pcie_apply_destination(trans);
1004
1005         /* TODO: remove in the next Si step */
1006         ret = iwl_pcie_rsa_race_bug_wa(trans);
1007         if (ret)
1008                 return ret;
1009
1010         /* configure the ucode to be ready to get the secured image */
1011         /* release CPU reset */
1012         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1013
1014         /* load to FW the binary Secured sections of CPU1 */
1015         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1016                                               &first_ucode_section);
1017         if (ret)
1018                 return ret;
1019
1020         /* load to FW the binary sections of CPU2 */
1021         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1022                                                &first_ucode_section);
1023 }
1024
1025 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1026 {
1027         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1028         bool hw_rfkill, was_hw_rfkill;
1029
1030         lockdep_assert_held(&trans_pcie->mutex);
1031
1032         if (trans_pcie->is_down)
1033                 return;
1034
1035         trans_pcie->is_down = true;
1036
1037         was_hw_rfkill = iwl_is_rfkill_set(trans);
1038
1039         /* tell the device to stop sending interrupts */
1040         spin_lock(&trans_pcie->irq_lock);
1041         iwl_disable_interrupts(trans);
1042         spin_unlock(&trans_pcie->irq_lock);
1043
1044         /* device going down, Stop using ICT table */
1045         iwl_pcie_disable_ict(trans);
1046
1047         /*
1048          * If a HW restart happens during firmware loading,
1049          * then the firmware loading might call this function
1050          * and later it might be called again due to the
1051          * restart. So don't process again if the device is
1052          * already dead.
1053          */
1054         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1055                 IWL_DEBUG_INFO(trans,
1056                                "DEVICE_ENABLED bit was set and is now cleared\n");
1057                 iwl_pcie_tx_stop(trans);
1058                 iwl_pcie_rx_stop(trans);
1059
1060                 /* Power-down device's busmaster DMA clocks */
1061                 if (!trans->cfg->apmg_not_supported) {
1062                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1063                                        APMG_CLK_VAL_DMA_CLK_RQT);
1064                         udelay(5);
1065                 }
1066         }
1067
1068         /* Make sure (redundant) we've released our request to stay awake */
1069         iwl_clear_bit(trans, CSR_GP_CNTRL,
1070                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1071
1072         /* Stop the device, and put it in low power state */
1073         iwl_pcie_apm_stop(trans, false);
1074
1075         /* stop and reset the on-board processor */
1076         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1077         udelay(20);
1078
1079         /*
1080          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1081          * This is a bug in certain verions of the hardware.
1082          * Certain devices also keep sending HW RF kill interrupt all
1083          * the time, unless the interrupt is ACKed even if the interrupt
1084          * should be masked. Re-ACK all the interrupts here.
1085          */
1086         spin_lock(&trans_pcie->irq_lock);
1087         iwl_disable_interrupts(trans);
1088         spin_unlock(&trans_pcie->irq_lock);
1089
1090         /* clear all status bits */
1091         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1092         clear_bit(STATUS_INT_ENABLED, &trans->status);
1093         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1094         clear_bit(STATUS_RFKILL, &trans->status);
1095
1096         /*
1097          * Even if we stop the HW, we still want the RF kill
1098          * interrupt
1099          */
1100         iwl_enable_rfkill_int(trans);
1101
1102         /*
1103          * Check again since the RF kill state may have changed while
1104          * all the interrupts were disabled, in this case we couldn't
1105          * receive the RF kill interrupt and update the state in the
1106          * op_mode.
1107          * Don't call the op_mode if the rkfill state hasn't changed.
1108          * This allows the op_mode to call stop_device from the rfkill
1109          * notification without endless recursion. Under very rare
1110          * circumstances, we might have a small recursion if the rfkill
1111          * state changed exactly now while we were called from stop_device.
1112          * This is very unlikely but can happen and is supported.
1113          */
1114         hw_rfkill = iwl_is_rfkill_set(trans);
1115         if (hw_rfkill)
1116                 set_bit(STATUS_RFKILL, &trans->status);
1117         else
1118                 clear_bit(STATUS_RFKILL, &trans->status);
1119         if (hw_rfkill != was_hw_rfkill)
1120                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1121
1122         /* re-take ownership to prevent other users from stealing the device */
1123         iwl_pcie_prepare_card_hw(trans);
1124 }
1125
1126 static void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1127 {
1128         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1129
1130         if (trans_pcie->msix_enabled) {
1131                 int i;
1132
1133                 for (i = 0; i < trans_pcie->allocated_vector; i++)
1134                         synchronize_irq(trans_pcie->msix_entries[i].vector);
1135         } else {
1136                 synchronize_irq(trans_pcie->pci_dev->irq);
1137         }
1138 }
1139
1140 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1141                                    const struct fw_img *fw, bool run_in_rfkill)
1142 {
1143         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1144         bool hw_rfkill;
1145         int ret;
1146
1147         /* This may fail if AMT took ownership of the device */
1148         if (iwl_pcie_prepare_card_hw(trans)) {
1149                 IWL_WARN(trans, "Exit HW not ready\n");
1150                 ret = -EIO;
1151                 goto out;
1152         }
1153
1154         iwl_enable_rfkill_int(trans);
1155
1156         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1157
1158         /*
1159          * We enabled the RF-Kill interrupt and the handler may very
1160          * well be running. Disable the interrupts to make sure no other
1161          * interrupt can be fired.
1162          */
1163         iwl_disable_interrupts(trans);
1164
1165         /* Make sure it finished running */
1166         iwl_pcie_synchronize_irqs(trans);
1167
1168         mutex_lock(&trans_pcie->mutex);
1169
1170         /* If platform's RF_KILL switch is NOT set to KILL */
1171         hw_rfkill = iwl_is_rfkill_set(trans);
1172         if (hw_rfkill)
1173                 set_bit(STATUS_RFKILL, &trans->status);
1174         else
1175                 clear_bit(STATUS_RFKILL, &trans->status);
1176         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1177         if (hw_rfkill && !run_in_rfkill) {
1178                 ret = -ERFKILL;
1179                 goto out;
1180         }
1181
1182         /* Someone called stop_device, don't try to start_fw */
1183         if (trans_pcie->is_down) {
1184                 IWL_WARN(trans,
1185                          "Can't start_fw since the HW hasn't been started\n");
1186                 ret = -EIO;
1187                 goto out;
1188         }
1189
1190         /* make sure rfkill handshake bits are cleared */
1191         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1192         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1193                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1194
1195         /* clear (again), then enable host interrupts */
1196         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1197
1198         ret = iwl_pcie_nic_init(trans);
1199         if (ret) {
1200                 IWL_ERR(trans, "Unable to init nic\n");
1201                 goto out;
1202         }
1203
1204         /*
1205          * Now, we load the firmware and don't want to be interrupted, even
1206          * by the RF-Kill interrupt (hence mask all the interrupt besides the
1207          * FH_TX interrupt which is needed to load the firmware). If the
1208          * RF-Kill switch is toggled, we will find out after having loaded
1209          * the firmware and return the proper value to the caller.
1210          */
1211         iwl_enable_fw_load_int(trans);
1212
1213         /* really make sure rfkill handshake bits are cleared */
1214         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1215         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1216
1217         /* Load the given image to the HW */
1218         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1219                 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1220         else
1221                 ret = iwl_pcie_load_given_ucode(trans, fw);
1222         iwl_enable_interrupts(trans);
1223
1224         /* re-check RF-Kill state since we may have missed the interrupt */
1225         hw_rfkill = iwl_is_rfkill_set(trans);
1226         if (hw_rfkill)
1227                 set_bit(STATUS_RFKILL, &trans->status);
1228         else
1229                 clear_bit(STATUS_RFKILL, &trans->status);
1230
1231         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1232         if (hw_rfkill && !run_in_rfkill)
1233                 ret = -ERFKILL;
1234
1235 out:
1236         mutex_unlock(&trans_pcie->mutex);
1237         return ret;
1238 }
1239
1240 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1241 {
1242         iwl_pcie_reset_ict(trans);
1243         iwl_pcie_tx_start(trans, scd_addr);
1244 }
1245
1246 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1247 {
1248         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1249
1250         mutex_lock(&trans_pcie->mutex);
1251         _iwl_trans_pcie_stop_device(trans, low_power);
1252         mutex_unlock(&trans_pcie->mutex);
1253 }
1254
1255 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1256 {
1257         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1258                 IWL_TRANS_GET_PCIE_TRANS(trans);
1259
1260         lockdep_assert_held(&trans_pcie->mutex);
1261
1262         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1263                 _iwl_trans_pcie_stop_device(trans, true);
1264 }
1265
1266 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1267                                       bool reset)
1268 {
1269         if (!reset) {
1270                 /* Enable persistence mode to avoid reset */
1271                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1272                             CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1273         }
1274
1275         iwl_disable_interrupts(trans);
1276
1277         /*
1278          * in testing mode, the host stays awake and the
1279          * hardware won't be reset (not even partially)
1280          */
1281         if (test)
1282                 return;
1283
1284         iwl_pcie_disable_ict(trans);
1285
1286         iwl_pcie_synchronize_irqs(trans);
1287
1288         iwl_clear_bit(trans, CSR_GP_CNTRL,
1289                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1290         iwl_clear_bit(trans, CSR_GP_CNTRL,
1291                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1292
1293         if (reset) {
1294                 /*
1295                  * reset TX queues -- some of their registers reset during S3
1296                  * so if we don't reset everything here the D3 image would try
1297                  * to execute some invalid memory upon resume
1298                  */
1299                 iwl_trans_pcie_tx_reset(trans);
1300         }
1301
1302         iwl_pcie_set_pwr(trans, true);
1303 }
1304
1305 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1306                                     enum iwl_d3_status *status,
1307                                     bool test,  bool reset)
1308 {
1309         u32 val;
1310         int ret;
1311
1312         if (test) {
1313                 iwl_enable_interrupts(trans);
1314                 *status = IWL_D3_STATUS_ALIVE;
1315                 return 0;
1316         }
1317
1318         /*
1319          * Also enables interrupts - none will happen as the device doesn't
1320          * know we're waking it up, only when the opmode actually tells it
1321          * after this call.
1322          */
1323         iwl_pcie_reset_ict(trans);
1324
1325         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1326         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1327
1328         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1329                 udelay(2);
1330
1331         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1332                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1333                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1334                            25000);
1335         if (ret < 0) {
1336                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1337                 return ret;
1338         }
1339
1340         iwl_pcie_set_pwr(trans, false);
1341
1342         if (!reset) {
1343                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1344                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1345         } else {
1346                 iwl_trans_pcie_tx_reset(trans);
1347
1348                 ret = iwl_pcie_rx_init(trans);
1349                 if (ret) {
1350                         IWL_ERR(trans,
1351                                 "Failed to resume the device (RX reset)\n");
1352                         return ret;
1353                 }
1354         }
1355
1356         val = iwl_read32(trans, CSR_RESET);
1357         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1358                 *status = IWL_D3_STATUS_RESET;
1359         else
1360                 *status = IWL_D3_STATUS_ALIVE;
1361
1362         return 0;
1363 }
1364
1365 struct iwl_causes_list {
1366         u32 cause_num;
1367         u32 mask_reg;
1368         u8 addr;
1369 };
1370
1371 static struct iwl_causes_list causes_list[] = {
1372         {MSIX_FH_INT_CAUSES_D2S_CH0_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0},
1373         {MSIX_FH_INT_CAUSES_D2S_CH1_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0x1},
1374         {MSIX_FH_INT_CAUSES_S2D,                CSR_MSIX_FH_INT_MASK_AD, 0x3},
1375         {MSIX_FH_INT_CAUSES_FH_ERR,             CSR_MSIX_FH_INT_MASK_AD, 0x5},
1376         {MSIX_HW_INT_CAUSES_REG_ALIVE,          CSR_MSIX_HW_INT_MASK_AD, 0x10},
1377         {MSIX_HW_INT_CAUSES_REG_WAKEUP,         CSR_MSIX_HW_INT_MASK_AD, 0x11},
1378         {MSIX_HW_INT_CAUSES_REG_CT_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x16},
1379         {MSIX_HW_INT_CAUSES_REG_RF_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x17},
1380         {MSIX_HW_INT_CAUSES_REG_PERIODIC,       CSR_MSIX_HW_INT_MASK_AD, 0x18},
1381         {MSIX_HW_INT_CAUSES_REG_SW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x29},
1382         {MSIX_HW_INT_CAUSES_REG_SCD,            CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1383         {MSIX_HW_INT_CAUSES_REG_FH_TX,          CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1384         {MSIX_HW_INT_CAUSES_REG_HW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1385         {MSIX_HW_INT_CAUSES_REG_HAP,            CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1386 };
1387
1388 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1389 {
1390         u32 val, max_rx_vector, i;
1391         struct iwl_trans *trans = trans_pcie->trans;
1392
1393         max_rx_vector = trans_pcie->allocated_vector - 1;
1394
1395         if (!trans_pcie->msix_enabled)
1396                 return;
1397
1398         iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1399
1400         /*
1401          * Each cause from the list above and the RX causes is represented as
1402          * a byte in the IVAR table. We access the first (N - 1) bytes and map
1403          * them to the (N - 1) vectors so these vectors will be used as rx
1404          * vectors. Then access all non rx causes and map them to the
1405          * default queue (N'th queue).
1406          */
1407         for (i = 0; i < max_rx_vector; i++) {
1408                 iwl_write8(trans, CSR_MSIX_RX_IVAR(i), MSIX_FH_INT_CAUSES_Q(i));
1409                 iwl_clear_bit(trans, CSR_MSIX_FH_INT_MASK_AD,
1410                               BIT(MSIX_FH_INT_CAUSES_Q(i)));
1411         }
1412
1413         for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1414                 val = trans_pcie->default_irq_num |
1415                         MSIX_NON_AUTO_CLEAR_CAUSE;
1416                 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1417                 iwl_clear_bit(trans, causes_list[i].mask_reg,
1418                               causes_list[i].cause_num);
1419         }
1420         trans_pcie->fh_init_mask =
1421                 ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1422         trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1423         trans_pcie->hw_init_mask =
1424                 ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1425         trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1426 }
1427
1428 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1429                                         struct iwl_trans *trans)
1430 {
1431         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1432         u16 pci_cmd;
1433         int max_vector;
1434         int ret, i;
1435
1436         if (trans->cfg->mq_rx_supported) {
1437                 max_vector = min_t(u32, (num_possible_cpus() + 1),
1438                                    IWL_MAX_RX_HW_QUEUES);
1439                 for (i = 0; i < max_vector; i++)
1440                         trans_pcie->msix_entries[i].entry = i;
1441
1442                 ret = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1443                                             MSIX_MIN_INTERRUPT_VECTORS,
1444                                             max_vector);
1445                 if (ret > 1) {
1446                         IWL_DEBUG_INFO(trans,
1447                                        "Enable MSI-X allocate %d interrupt vector\n",
1448                                        ret);
1449                         trans_pcie->allocated_vector = ret;
1450                         trans_pcie->default_irq_num =
1451                                 trans_pcie->allocated_vector - 1;
1452                         trans_pcie->trans->num_rx_queues =
1453                                 trans_pcie->allocated_vector - 1;
1454                         trans_pcie->msix_enabled = true;
1455
1456                         return;
1457                 }
1458                 IWL_DEBUG_INFO(trans,
1459                                "ret = %d %s move to msi mode\n", ret,
1460                                (ret == 1) ?
1461                                "can't allocate more than 1 interrupt vector" :
1462                                "failed to enable msi-x mode");
1463                 pci_disable_msix(pdev);
1464         }
1465
1466         ret = pci_enable_msi(pdev);
1467         if (ret) {
1468                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", ret);
1469                 /* enable rfkill interrupt: hw bug w/a */
1470                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1471                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1472                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1473                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1474                 }
1475         }
1476 }
1477
1478 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1479                                       struct iwl_trans_pcie *trans_pcie)
1480 {
1481         int i, last_vector;
1482
1483         last_vector = trans_pcie->trans->num_rx_queues;
1484
1485         for (i = 0; i < trans_pcie->allocated_vector; i++) {
1486                 int ret;
1487
1488                 ret = request_threaded_irq(trans_pcie->msix_entries[i].vector,
1489                                            iwl_pcie_msix_isr,
1490                                            (i == last_vector) ?
1491                                            iwl_pcie_irq_msix_handler :
1492                                            iwl_pcie_irq_rx_msix_handler,
1493                                            IRQF_SHARED,
1494                                            DRV_NAME,
1495                                            &trans_pcie->msix_entries[i]);
1496                 if (ret) {
1497                         int j;
1498
1499                         IWL_ERR(trans_pcie->trans,
1500                                 "Error allocating IRQ %d\n", i);
1501                         for (j = 0; j < i; j++)
1502                                 free_irq(trans_pcie->msix_entries[i].vector,
1503                                          &trans_pcie->msix_entries[i]);
1504                         pci_disable_msix(pdev);
1505                         return ret;
1506                 }
1507         }
1508
1509         return 0;
1510 }
1511
1512 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1513 {
1514         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1515         bool hw_rfkill;
1516         int err;
1517
1518         lockdep_assert_held(&trans_pcie->mutex);
1519
1520         err = iwl_pcie_prepare_card_hw(trans);
1521         if (err) {
1522                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1523                 return err;
1524         }
1525
1526         /* Reset the entire device */
1527         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1528
1529         usleep_range(10, 15);
1530
1531         iwl_pcie_apm_init(trans);
1532
1533         iwl_pcie_init_msix(trans_pcie);
1534         /* From now on, the op_mode will be kept updated about RF kill state */
1535         iwl_enable_rfkill_int(trans);
1536
1537         /* Set is_down to false here so that...*/
1538         trans_pcie->is_down = false;
1539
1540         hw_rfkill = iwl_is_rfkill_set(trans);
1541         if (hw_rfkill)
1542                 set_bit(STATUS_RFKILL, &trans->status);
1543         else
1544                 clear_bit(STATUS_RFKILL, &trans->status);
1545         /* ... rfkill can call stop_device and set it false if needed */
1546         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1547
1548         /* Make sure we sync here, because we'll need full access later */
1549         if (low_power)
1550                 pm_runtime_resume(trans->dev);
1551
1552         return 0;
1553 }
1554
1555 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1556 {
1557         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1558         int ret;
1559
1560         mutex_lock(&trans_pcie->mutex);
1561         ret = _iwl_trans_pcie_start_hw(trans, low_power);
1562         mutex_unlock(&trans_pcie->mutex);
1563
1564         return ret;
1565 }
1566
1567 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1568 {
1569         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1570
1571         mutex_lock(&trans_pcie->mutex);
1572
1573         /* disable interrupts - don't enable HW RF kill interrupt */
1574         spin_lock(&trans_pcie->irq_lock);
1575         iwl_disable_interrupts(trans);
1576         spin_unlock(&trans_pcie->irq_lock);
1577
1578         iwl_pcie_apm_stop(trans, true);
1579
1580         spin_lock(&trans_pcie->irq_lock);
1581         iwl_disable_interrupts(trans);
1582         spin_unlock(&trans_pcie->irq_lock);
1583
1584         iwl_pcie_disable_ict(trans);
1585
1586         mutex_unlock(&trans_pcie->mutex);
1587
1588         iwl_pcie_synchronize_irqs(trans);
1589 }
1590
1591 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1592 {
1593         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1594 }
1595
1596 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1597 {
1598         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1599 }
1600
1601 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1602 {
1603         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1604 }
1605
1606 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1607 {
1608         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1609                                ((reg & 0x000FFFFF) | (3 << 24)));
1610         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1611 }
1612
1613 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1614                                       u32 val)
1615 {
1616         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1617                                ((addr & 0x000FFFFF) | (3 << 24)));
1618         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1619 }
1620
1621 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1622                                      const struct iwl_trans_config *trans_cfg)
1623 {
1624         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1625
1626         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1627         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1628         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1629         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1630                 trans_pcie->n_no_reclaim_cmds = 0;
1631         else
1632                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1633         if (trans_pcie->n_no_reclaim_cmds)
1634                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1635                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1636
1637         trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1638         trans_pcie->rx_page_order =
1639                 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1640
1641         trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header;
1642         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1643         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1644         trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1645
1646         trans->command_groups = trans_cfg->command_groups;
1647         trans->command_groups_size = trans_cfg->command_groups_size;
1648
1649         /* Initialize NAPI here - it should be before registering to mac80211
1650          * in the opmode but after the HW struct is allocated.
1651          * As this function may be called again in some corner cases don't
1652          * do anything if NAPI was already initialized.
1653          */
1654         if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1655                 init_dummy_netdev(&trans_pcie->napi_dev);
1656 }
1657
1658 void iwl_trans_pcie_free(struct iwl_trans *trans)
1659 {
1660         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1661         int i;
1662
1663         iwl_pcie_synchronize_irqs(trans);
1664
1665         iwl_pcie_tx_free(trans);
1666         iwl_pcie_rx_free(trans);
1667
1668         if (trans_pcie->msix_enabled) {
1669                 for (i = 0; i < trans_pcie->allocated_vector; i++)
1670                         free_irq(trans_pcie->msix_entries[i].vector,
1671                                  &trans_pcie->msix_entries[i]);
1672
1673                 pci_disable_msix(trans_pcie->pci_dev);
1674                 trans_pcie->msix_enabled = false;
1675         } else {
1676                 free_irq(trans_pcie->pci_dev->irq, trans);
1677
1678                 iwl_pcie_free_ict(trans);
1679
1680                 pci_disable_msi(trans_pcie->pci_dev);
1681         }
1682         iounmap(trans_pcie->hw_base);
1683         pci_release_regions(trans_pcie->pci_dev);
1684         pci_disable_device(trans_pcie->pci_dev);
1685
1686         iwl_pcie_free_fw_monitor(trans);
1687
1688         for_each_possible_cpu(i) {
1689                 struct iwl_tso_hdr_page *p =
1690                         per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1691
1692                 if (p->page)
1693                         __free_page(p->page);
1694         }
1695
1696         free_percpu(trans_pcie->tso_hdr_page);
1697         iwl_trans_free(trans);
1698 }
1699
1700 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1701 {
1702         if (state)
1703                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1704         else
1705                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1706 }
1707
1708 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1709                                            unsigned long *flags)
1710 {
1711         int ret;
1712         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1713
1714         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1715
1716         if (trans_pcie->cmd_hold_nic_awake)
1717                 goto out;
1718
1719         /* this bit wakes up the NIC */
1720         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1721                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1722         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1723                 udelay(2);
1724
1725         /*
1726          * These bits say the device is running, and should keep running for
1727          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1728          * but they do not indicate that embedded SRAM is restored yet;
1729          * 3945 and 4965 have volatile SRAM, and must save/restore contents
1730          * to/from host DRAM when sleeping/waking for power-saving.
1731          * Each direction takes approximately 1/4 millisecond; with this
1732          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1733          * series of register accesses are expected (e.g. reading Event Log),
1734          * to keep device from sleeping.
1735          *
1736          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1737          * SRAM is okay/restored.  We don't check that here because this call
1738          * is just for hardware register access; but GP1 MAC_SLEEP check is a
1739          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1740          *
1741          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1742          * and do not save/restore SRAM when power cycling.
1743          */
1744         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1745                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1746                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1747                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1748         if (unlikely(ret < 0)) {
1749                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1750                 WARN_ONCE(1,
1751                           "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1752                           iwl_read32(trans, CSR_GP_CNTRL));
1753                 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1754                 return false;
1755         }
1756
1757 out:
1758         /*
1759          * Fool sparse by faking we release the lock - sparse will
1760          * track nic_access anyway.
1761          */
1762         __release(&trans_pcie->reg_lock);
1763         return true;
1764 }
1765
1766 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1767                                               unsigned long *flags)
1768 {
1769         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1770
1771         lockdep_assert_held(&trans_pcie->reg_lock);
1772
1773         /*
1774          * Fool sparse by faking we acquiring the lock - sparse will
1775          * track nic_access anyway.
1776          */
1777         __acquire(&trans_pcie->reg_lock);
1778
1779         if (trans_pcie->cmd_hold_nic_awake)
1780                 goto out;
1781
1782         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1783                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1784         /*
1785          * Above we read the CSR_GP_CNTRL register, which will flush
1786          * any previous writes, but we need the write that clears the
1787          * MAC_ACCESS_REQ bit to be performed before any other writes
1788          * scheduled on different CPUs (after we drop reg_lock).
1789          */
1790         mmiowb();
1791 out:
1792         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1793 }
1794
1795 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1796                                    void *buf, int dwords)
1797 {
1798         unsigned long flags;
1799         int offs, ret = 0;
1800         u32 *vals = buf;
1801
1802         if (iwl_trans_grab_nic_access(trans, &flags)) {
1803                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1804                 for (offs = 0; offs < dwords; offs++)
1805                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1806                 iwl_trans_release_nic_access(trans, &flags);
1807         } else {
1808                 ret = -EBUSY;
1809         }
1810         return ret;
1811 }
1812
1813 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1814                                     const void *buf, int dwords)
1815 {
1816         unsigned long flags;
1817         int offs, ret = 0;
1818         const u32 *vals = buf;
1819
1820         if (iwl_trans_grab_nic_access(trans, &flags)) {
1821                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1822                 for (offs = 0; offs < dwords; offs++)
1823                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1824                                     vals ? vals[offs] : 0);
1825                 iwl_trans_release_nic_access(trans, &flags);
1826         } else {
1827                 ret = -EBUSY;
1828         }
1829         return ret;
1830 }
1831
1832 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1833                                             unsigned long txqs,
1834                                             bool freeze)
1835 {
1836         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1837         int queue;
1838
1839         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1840                 struct iwl_txq *txq = &trans_pcie->txq[queue];
1841                 unsigned long now;
1842
1843                 spin_lock_bh(&txq->lock);
1844
1845                 now = jiffies;
1846
1847                 if (txq->frozen == freeze)
1848                         goto next_queue;
1849
1850                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1851                                     freeze ? "Freezing" : "Waking", queue);
1852
1853                 txq->frozen = freeze;
1854
1855                 if (txq->q.read_ptr == txq->q.write_ptr)
1856                         goto next_queue;
1857
1858                 if (freeze) {
1859                         if (unlikely(time_after(now,
1860                                                 txq->stuck_timer.expires))) {
1861                                 /*
1862                                  * The timer should have fired, maybe it is
1863                                  * spinning right now on the lock.
1864                                  */
1865                                 goto next_queue;
1866                         }
1867                         /* remember how long until the timer fires */
1868                         txq->frozen_expiry_remainder =
1869                                 txq->stuck_timer.expires - now;
1870                         del_timer(&txq->stuck_timer);
1871                         goto next_queue;
1872                 }
1873
1874                 /*
1875                  * Wake a non-empty queue -> arm timer with the
1876                  * remainder before it froze
1877                  */
1878                 mod_timer(&txq->stuck_timer,
1879                           now + txq->frozen_expiry_remainder);
1880
1881 next_queue:
1882                 spin_unlock_bh(&txq->lock);
1883         }
1884 }
1885
1886 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
1887 {
1888         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1889         int i;
1890
1891         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1892                 struct iwl_txq *txq = &trans_pcie->txq[i];
1893
1894                 if (i == trans_pcie->cmd_queue)
1895                         continue;
1896
1897                 spin_lock_bh(&txq->lock);
1898
1899                 if (!block && !(WARN_ON_ONCE(!txq->block))) {
1900                         txq->block--;
1901                         if (!txq->block) {
1902                                 iwl_write32(trans, HBUS_TARG_WRPTR,
1903                                             txq->q.write_ptr | (i << 8));
1904                         }
1905                 } else if (block) {
1906                         txq->block++;
1907                 }
1908
1909                 spin_unlock_bh(&txq->lock);
1910         }
1911 }
1912
1913 #define IWL_FLUSH_WAIT_MS       2000
1914
1915 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1916 {
1917         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1918         struct iwl_txq *txq;
1919         struct iwl_queue *q;
1920         int cnt;
1921         unsigned long now = jiffies;
1922         u32 scd_sram_addr;
1923         u8 buf[16];
1924         int ret = 0;
1925
1926         /* waiting for all the tx frames complete might take a while */
1927         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1928                 u8 wr_ptr;
1929
1930                 if (cnt == trans_pcie->cmd_queue)
1931                         continue;
1932                 if (!test_bit(cnt, trans_pcie->queue_used))
1933                         continue;
1934                 if (!(BIT(cnt) & txq_bm))
1935                         continue;
1936
1937                 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1938                 txq = &trans_pcie->txq[cnt];
1939                 q = &txq->q;
1940                 wr_ptr = ACCESS_ONCE(q->write_ptr);
1941
1942                 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1943                        !time_after(jiffies,
1944                                    now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1945                         u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1946
1947                         if (WARN_ONCE(wr_ptr != write_ptr,
1948                                       "WR pointer moved while flushing %d -> %d\n",
1949                                       wr_ptr, write_ptr))
1950                                 return -ETIMEDOUT;
1951                         msleep(1);
1952                 }
1953
1954                 if (q->read_ptr != q->write_ptr) {
1955                         IWL_ERR(trans,
1956                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1957                         ret = -ETIMEDOUT;
1958                         break;
1959                 }
1960                 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1961         }
1962
1963         if (!ret)
1964                 return 0;
1965
1966         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1967                 txq->q.read_ptr, txq->q.write_ptr);
1968
1969         scd_sram_addr = trans_pcie->scd_base_addr +
1970                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1971         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1972
1973         iwl_print_hex_error(trans, buf, sizeof(buf));
1974
1975         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1976                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1977                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1978
1979         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1980                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1981                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1982                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1983                 u32 tbl_dw =
1984                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1985                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1986
1987                 if (cnt & 0x1)
1988                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1989                 else
1990                         tbl_dw = tbl_dw & 0x0000FFFF;
1991
1992                 IWL_ERR(trans,
1993                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1994                         cnt, active ? "" : "in", fifo, tbl_dw,
1995                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1996                                 (TFD_QUEUE_SIZE_MAX - 1),
1997                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1998         }
1999
2000         return ret;
2001 }
2002
2003 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2004                                          u32 mask, u32 value)
2005 {
2006         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2007         unsigned long flags;
2008
2009         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2010         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2011         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2012 }
2013
2014 void iwl_trans_pcie_ref(struct iwl_trans *trans)
2015 {
2016         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2017         unsigned long flags;
2018
2019         if (iwlwifi_mod_params.d0i3_disable)
2020                 return;
2021
2022         spin_lock_irqsave(&trans_pcie->ref_lock, flags);
2023         IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
2024         trans_pcie->ref_count++;
2025         pm_runtime_get(&trans_pcie->pci_dev->dev);
2026         spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
2027 }
2028
2029 void iwl_trans_pcie_unref(struct iwl_trans *trans)
2030 {
2031         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2032         unsigned long flags;
2033
2034         if (iwlwifi_mod_params.d0i3_disable)
2035                 return;
2036
2037         spin_lock_irqsave(&trans_pcie->ref_lock, flags);
2038         IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
2039         if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
2040                 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
2041                 return;
2042         }
2043         trans_pcie->ref_count--;
2044
2045         pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2046         pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
2047
2048         spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
2049 }
2050
2051 static const char *get_csr_string(int cmd)
2052 {
2053 #define IWL_CMD(x) case x: return #x
2054         switch (cmd) {
2055         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2056         IWL_CMD(CSR_INT_COALESCING);
2057         IWL_CMD(CSR_INT);
2058         IWL_CMD(CSR_INT_MASK);
2059         IWL_CMD(CSR_FH_INT_STATUS);
2060         IWL_CMD(CSR_GPIO_IN);
2061         IWL_CMD(CSR_RESET);
2062         IWL_CMD(CSR_GP_CNTRL);
2063         IWL_CMD(CSR_HW_REV);
2064         IWL_CMD(CSR_EEPROM_REG);
2065         IWL_CMD(CSR_EEPROM_GP);
2066         IWL_CMD(CSR_OTP_GP_REG);
2067         IWL_CMD(CSR_GIO_REG);
2068         IWL_CMD(CSR_GP_UCODE_REG);
2069         IWL_CMD(CSR_GP_DRIVER_REG);
2070         IWL_CMD(CSR_UCODE_DRV_GP1);
2071         IWL_CMD(CSR_UCODE_DRV_GP2);
2072         IWL_CMD(CSR_LED_REG);
2073         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2074         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2075         IWL_CMD(CSR_ANA_PLL_CFG);
2076         IWL_CMD(CSR_HW_REV_WA_REG);
2077         IWL_CMD(CSR_MONITOR_STATUS_REG);
2078         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2079         default:
2080                 return "UNKNOWN";
2081         }
2082 #undef IWL_CMD
2083 }
2084
2085 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2086 {
2087         int i;
2088         static const u32 csr_tbl[] = {
2089                 CSR_HW_IF_CONFIG_REG,
2090                 CSR_INT_COALESCING,
2091                 CSR_INT,
2092                 CSR_INT_MASK,
2093                 CSR_FH_INT_STATUS,
2094                 CSR_GPIO_IN,
2095                 CSR_RESET,
2096                 CSR_GP_CNTRL,
2097                 CSR_HW_REV,
2098                 CSR_EEPROM_REG,
2099                 CSR_EEPROM_GP,
2100                 CSR_OTP_GP_REG,
2101                 CSR_GIO_REG,
2102                 CSR_GP_UCODE_REG,
2103                 CSR_GP_DRIVER_REG,
2104                 CSR_UCODE_DRV_GP1,
2105                 CSR_UCODE_DRV_GP2,
2106                 CSR_LED_REG,
2107                 CSR_DRAM_INT_TBL_REG,
2108                 CSR_GIO_CHICKEN_BITS,
2109                 CSR_ANA_PLL_CFG,
2110                 CSR_MONITOR_STATUS_REG,
2111                 CSR_HW_REV_WA_REG,
2112                 CSR_DBG_HPET_MEM_REG
2113         };
2114         IWL_ERR(trans, "CSR values:\n");
2115         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2116                 "CSR_INT_PERIODIC_REG)\n");
2117         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2118                 IWL_ERR(trans, "  %25s: 0X%08x\n",
2119                         get_csr_string(csr_tbl[i]),
2120                         iwl_read32(trans, csr_tbl[i]));
2121         }
2122 }
2123
2124 #ifdef CONFIG_IWLWIFI_DEBUGFS
2125 /* create and remove of files */
2126 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
2127         if (!debugfs_create_file(#name, mode, parent, trans,            \
2128                                  &iwl_dbgfs_##name##_ops))              \
2129                 goto err;                                               \
2130 } while (0)
2131
2132 /* file operation */
2133 #define DEBUGFS_READ_FILE_OPS(name)                                     \
2134 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2135         .read = iwl_dbgfs_##name##_read,                                \
2136         .open = simple_open,                                            \
2137         .llseek = generic_file_llseek,                                  \
2138 };
2139
2140 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2141 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2142         .write = iwl_dbgfs_##name##_write,                              \
2143         .open = simple_open,                                            \
2144         .llseek = generic_file_llseek,                                  \
2145 };
2146
2147 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
2148 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2149         .write = iwl_dbgfs_##name##_write,                              \
2150         .read = iwl_dbgfs_##name##_read,                                \
2151         .open = simple_open,                                            \
2152         .llseek = generic_file_llseek,                                  \
2153 };
2154
2155 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
2156                                        char __user *user_buf,
2157                                        size_t count, loff_t *ppos)
2158 {
2159         struct iwl_trans *trans = file->private_data;
2160         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2161         struct iwl_txq *txq;
2162         struct iwl_queue *q;
2163         char *buf;
2164         int pos = 0;
2165         int cnt;
2166         int ret;
2167         size_t bufsz;
2168
2169         bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
2170
2171         if (!trans_pcie->txq)
2172                 return -EAGAIN;
2173
2174         buf = kzalloc(bufsz, GFP_KERNEL);
2175         if (!buf)
2176                 return -ENOMEM;
2177
2178         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2179                 txq = &trans_pcie->txq[cnt];
2180                 q = &txq->q;
2181                 pos += scnprintf(buf + pos, bufsz - pos,
2182                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2183                                 cnt, q->read_ptr, q->write_ptr,
2184                                 !!test_bit(cnt, trans_pcie->queue_used),
2185                                  !!test_bit(cnt, trans_pcie->queue_stopped),
2186                                  txq->need_update, txq->frozen,
2187                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2188         }
2189         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2190         kfree(buf);
2191         return ret;
2192 }
2193
2194 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2195                                        char __user *user_buf,
2196                                        size_t count, loff_t *ppos)
2197 {
2198         struct iwl_trans *trans = file->private_data;
2199         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2200         char *buf;
2201         int pos = 0, i, ret;
2202         size_t bufsz = sizeof(buf);
2203
2204         bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2205
2206         if (!trans_pcie->rxq)
2207                 return -EAGAIN;
2208
2209         buf = kzalloc(bufsz, GFP_KERNEL);
2210         if (!buf)
2211                 return -ENOMEM;
2212
2213         for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2214                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2215
2216                 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2217                                  i);
2218                 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2219                                  rxq->read);
2220                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2221                                  rxq->write);
2222                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2223                                  rxq->write_actual);
2224                 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2225                                  rxq->need_update);
2226                 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2227                                  rxq->free_count);
2228                 if (rxq->rb_stts) {
2229                         pos += scnprintf(buf + pos, bufsz - pos,
2230                                          "\tclosed_rb_num: %u\n",
2231                                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2232                                          0x0FFF);
2233                 } else {
2234                         pos += scnprintf(buf + pos, bufsz - pos,
2235                                          "\tclosed_rb_num: Not Allocated\n");
2236                 }
2237         }
2238         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2239         kfree(buf);
2240
2241         return ret;
2242 }
2243
2244 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2245                                         char __user *user_buf,
2246                                         size_t count, loff_t *ppos)
2247 {
2248         struct iwl_trans *trans = file->private_data;
2249         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2250         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2251
2252         int pos = 0;
2253         char *buf;
2254         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2255         ssize_t ret;
2256
2257         buf = kzalloc(bufsz, GFP_KERNEL);
2258         if (!buf)
2259                 return -ENOMEM;
2260
2261         pos += scnprintf(buf + pos, bufsz - pos,
2262                         "Interrupt Statistics Report:\n");
2263
2264         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2265                 isr_stats->hw);
2266         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2267                 isr_stats->sw);
2268         if (isr_stats->sw || isr_stats->hw) {
2269                 pos += scnprintf(buf + pos, bufsz - pos,
2270                         "\tLast Restarting Code:  0x%X\n",
2271                         isr_stats->err_code);
2272         }
2273 #ifdef CONFIG_IWLWIFI_DEBUG
2274         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2275                 isr_stats->sch);
2276         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2277                 isr_stats->alive);
2278 #endif
2279         pos += scnprintf(buf + pos, bufsz - pos,
2280                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2281
2282         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2283                 isr_stats->ctkill);
2284
2285         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2286                 isr_stats->wakeup);
2287
2288         pos += scnprintf(buf + pos, bufsz - pos,
2289                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2290
2291         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2292                 isr_stats->tx);
2293
2294         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2295                 isr_stats->unhandled);
2296
2297         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2298         kfree(buf);
2299         return ret;
2300 }
2301
2302 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2303                                          const char __user *user_buf,
2304                                          size_t count, loff_t *ppos)
2305 {
2306         struct iwl_trans *trans = file->private_data;
2307         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2308         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2309
2310         char buf[8];
2311         int buf_size;
2312         u32 reset_flag;
2313
2314         memset(buf, 0, sizeof(buf));
2315         buf_size = min(count, sizeof(buf) -  1);
2316         if (copy_from_user(buf, user_buf, buf_size))
2317                 return -EFAULT;
2318         if (sscanf(buf, "%x", &reset_flag) != 1)
2319                 return -EFAULT;
2320         if (reset_flag == 0)
2321                 memset(isr_stats, 0, sizeof(*isr_stats));
2322
2323         return count;
2324 }
2325
2326 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2327                                    const char __user *user_buf,
2328                                    size_t count, loff_t *ppos)
2329 {
2330         struct iwl_trans *trans = file->private_data;
2331         char buf[8];
2332         int buf_size;
2333         int csr;
2334
2335         memset(buf, 0, sizeof(buf));
2336         buf_size = min(count, sizeof(buf) -  1);
2337         if (copy_from_user(buf, user_buf, buf_size))
2338                 return -EFAULT;
2339         if (sscanf(buf, "%d", &csr) != 1)
2340                 return -EFAULT;
2341
2342         iwl_pcie_dump_csr(trans);
2343
2344         return count;
2345 }
2346
2347 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2348                                      char __user *user_buf,
2349                                      size_t count, loff_t *ppos)
2350 {
2351         struct iwl_trans *trans = file->private_data;
2352         char *buf = NULL;
2353         ssize_t ret;
2354
2355         ret = iwl_dump_fh(trans, &buf);
2356         if (ret < 0)
2357                 return ret;
2358         if (!buf)
2359                 return -EINVAL;
2360         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2361         kfree(buf);
2362         return ret;
2363 }
2364
2365 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2366 DEBUGFS_READ_FILE_OPS(fh_reg);
2367 DEBUGFS_READ_FILE_OPS(rx_queue);
2368 DEBUGFS_READ_FILE_OPS(tx_queue);
2369 DEBUGFS_WRITE_FILE_OPS(csr);
2370
2371 /* Create the debugfs files and directories */
2372 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2373 {
2374         struct dentry *dir = trans->dbgfs_dir;
2375
2376         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2377         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2378         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2379         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2380         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2381         return 0;
2382
2383 err:
2384         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2385         return -ENOMEM;
2386 }
2387 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2388
2389 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2390 {
2391         u32 cmdlen = 0;
2392         int i;
2393
2394         for (i = 0; i < IWL_NUM_OF_TBS; i++)
2395                 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2396
2397         return cmdlen;
2398 }
2399
2400 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2401                                    struct iwl_fw_error_dump_data **data,
2402                                    int allocated_rb_nums)
2403 {
2404         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2405         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2406         /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2407         struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2408         u32 i, r, j, rb_len = 0;
2409
2410         spin_lock(&rxq->lock);
2411
2412         r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2413
2414         for (i = rxq->read, j = 0;
2415              i != r && j < allocated_rb_nums;
2416              i = (i + 1) & RX_QUEUE_MASK, j++) {
2417                 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2418                 struct iwl_fw_error_dump_rb *rb;
2419
2420                 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2421                                DMA_FROM_DEVICE);
2422
2423                 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2424
2425                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2426                 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2427                 rb = (void *)(*data)->data;
2428                 rb->index = cpu_to_le32(i);
2429                 memcpy(rb->data, page_address(rxb->page), max_len);
2430                 /* remap the page for the free benefit */
2431                 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2432                                                      max_len,
2433                                                      DMA_FROM_DEVICE);
2434
2435                 *data = iwl_fw_error_next_data(*data);
2436         }
2437
2438         spin_unlock(&rxq->lock);
2439
2440         return rb_len;
2441 }
2442 #define IWL_CSR_TO_DUMP (0x250)
2443
2444 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2445                                    struct iwl_fw_error_dump_data **data)
2446 {
2447         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2448         __le32 *val;
2449         int i;
2450
2451         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2452         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2453         val = (void *)(*data)->data;
2454
2455         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2456                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2457
2458         *data = iwl_fw_error_next_data(*data);
2459
2460         return csr_len;
2461 }
2462
2463 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2464                                        struct iwl_fw_error_dump_data **data)
2465 {
2466         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2467         unsigned long flags;
2468         __le32 *val;
2469         int i;
2470
2471         if (!iwl_trans_grab_nic_access(trans, &flags))
2472                 return 0;
2473
2474         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2475         (*data)->len = cpu_to_le32(fh_regs_len);
2476         val = (void *)(*data)->data;
2477
2478         for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2479                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2480
2481         iwl_trans_release_nic_access(trans, &flags);
2482
2483         *data = iwl_fw_error_next_data(*data);
2484
2485         return sizeof(**data) + fh_regs_len;
2486 }
2487
2488 static u32
2489 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2490                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2491                                  u32 monitor_len)
2492 {
2493         u32 buf_size_in_dwords = (monitor_len >> 2);
2494         u32 *buffer = (u32 *)fw_mon_data->data;
2495         unsigned long flags;
2496         u32 i;
2497
2498         if (!iwl_trans_grab_nic_access(trans, &flags))
2499                 return 0;
2500
2501         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2502         for (i = 0; i < buf_size_in_dwords; i++)
2503                 buffer[i] = iwl_read_prph_no_grab(trans,
2504                                 MON_DMARB_RD_DATA_ADDR);
2505         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2506
2507         iwl_trans_release_nic_access(trans, &flags);
2508
2509         return monitor_len;
2510 }
2511
2512 static u32
2513 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2514                             struct iwl_fw_error_dump_data **data,
2515                             u32 monitor_len)
2516 {
2517         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2518         u32 len = 0;
2519
2520         if ((trans_pcie->fw_mon_page &&
2521              trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2522             trans->dbg_dest_tlv) {
2523                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2524                 u32 base, write_ptr, wrap_cnt;
2525
2526                 /* If there was a dest TLV - use the values from there */
2527                 if (trans->dbg_dest_tlv) {
2528                         write_ptr =
2529                                 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2530                         wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2531                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2532                 } else {
2533                         base = MON_BUFF_BASE_ADDR;
2534                         write_ptr = MON_BUFF_WRPTR;
2535                         wrap_cnt = MON_BUFF_CYCLE_CNT;
2536                 }
2537
2538                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2539                 fw_mon_data = (void *)(*data)->data;
2540                 fw_mon_data->fw_mon_wr_ptr =
2541                         cpu_to_le32(iwl_read_prph(trans, write_ptr));
2542                 fw_mon_data->fw_mon_cycle_cnt =
2543                         cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2544                 fw_mon_data->fw_mon_base_ptr =
2545                         cpu_to_le32(iwl_read_prph(trans, base));
2546
2547                 len += sizeof(**data) + sizeof(*fw_mon_data);
2548                 if (trans_pcie->fw_mon_page) {
2549                         /*
2550                          * The firmware is now asserted, it won't write anything
2551                          * to the buffer. CPU can take ownership to fetch the
2552                          * data. The buffer will be handed back to the device
2553                          * before the firmware will be restarted.
2554                          */
2555                         dma_sync_single_for_cpu(trans->dev,
2556                                                 trans_pcie->fw_mon_phys,
2557                                                 trans_pcie->fw_mon_size,
2558                                                 DMA_FROM_DEVICE);
2559                         memcpy(fw_mon_data->data,
2560                                page_address(trans_pcie->fw_mon_page),
2561                                trans_pcie->fw_mon_size);
2562
2563                         monitor_len = trans_pcie->fw_mon_size;
2564                 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2565                         /*
2566                          * Update pointers to reflect actual values after
2567                          * shifting
2568                          */
2569                         base = iwl_read_prph(trans, base) <<
2570                                trans->dbg_dest_tlv->base_shift;
2571                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
2572                                            monitor_len / sizeof(u32));
2573                 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2574                         monitor_len =
2575                                 iwl_trans_pci_dump_marbh_monitor(trans,
2576                                                                  fw_mon_data,
2577                                                                  monitor_len);
2578                 } else {
2579                         /* Didn't match anything - output no monitor data */
2580                         monitor_len = 0;
2581                 }
2582
2583                 len += monitor_len;
2584                 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2585         }
2586
2587         return len;
2588 }
2589
2590 static struct iwl_trans_dump_data
2591 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2592                           const struct iwl_fw_dbg_trigger_tlv *trigger)
2593 {
2594         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2595         struct iwl_fw_error_dump_data *data;
2596         struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2597         struct iwl_fw_error_dump_txcmd *txcmd;
2598         struct iwl_trans_dump_data *dump_data;
2599         u32 len, num_rbs;
2600         u32 monitor_len;
2601         int i, ptr;
2602         bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2603                         !trans->cfg->mq_rx_supported;
2604
2605         /* transport dump header */
2606         len = sizeof(*dump_data);
2607
2608         /* host commands */
2609         len += sizeof(*data) +
2610                 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2611
2612         /* FW monitor */
2613         if (trans_pcie->fw_mon_page) {
2614                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2615                        trans_pcie->fw_mon_size;
2616                 monitor_len = trans_pcie->fw_mon_size;
2617         } else if (trans->dbg_dest_tlv) {
2618                 u32 base, end;
2619
2620                 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2621                 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2622
2623                 base = iwl_read_prph(trans, base) <<
2624                        trans->dbg_dest_tlv->base_shift;
2625                 end = iwl_read_prph(trans, end) <<
2626                       trans->dbg_dest_tlv->end_shift;
2627
2628                 /* Make "end" point to the actual end */
2629                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2630                     trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2631                         end += (1 << trans->dbg_dest_tlv->end_shift);
2632                 monitor_len = end - base;
2633                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2634                        monitor_len;
2635         } else {
2636                 monitor_len = 0;
2637         }
2638
2639         if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2640                 dump_data = vzalloc(len);
2641                 if (!dump_data)
2642                         return NULL;
2643
2644                 data = (void *)dump_data->data;
2645                 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2646                 dump_data->len = len;
2647
2648                 return dump_data;
2649         }
2650
2651         /* CSR registers */
2652         len += sizeof(*data) + IWL_CSR_TO_DUMP;
2653
2654         /* FH registers */
2655         len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2656
2657         if (dump_rbs) {
2658                 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2659                 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2660                 /* RBs */
2661                 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
2662                                       & 0x0FFF;
2663                 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
2664                 len += num_rbs * (sizeof(*data) +
2665                                   sizeof(struct iwl_fw_error_dump_rb) +
2666                                   (PAGE_SIZE << trans_pcie->rx_page_order));
2667         }
2668
2669         dump_data = vzalloc(len);
2670         if (!dump_data)
2671                 return NULL;
2672
2673         len = 0;
2674         data = (void *)dump_data->data;
2675         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2676         txcmd = (void *)data->data;
2677         spin_lock_bh(&cmdq->lock);
2678         ptr = cmdq->q.write_ptr;
2679         for (i = 0; i < cmdq->q.n_window; i++) {
2680                 u8 idx = get_cmd_index(&cmdq->q, ptr);
2681                 u32 caplen, cmdlen;
2682
2683                 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2684                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2685
2686                 if (cmdlen) {
2687                         len += sizeof(*txcmd) + caplen;
2688                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2689                         txcmd->caplen = cpu_to_le32(caplen);
2690                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2691                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2692                 }
2693
2694                 ptr = iwl_queue_dec_wrap(ptr);
2695         }
2696         spin_unlock_bh(&cmdq->lock);
2697
2698         data->len = cpu_to_le32(len);
2699         len += sizeof(*data);
2700         data = iwl_fw_error_next_data(data);
2701
2702         len += iwl_trans_pcie_dump_csr(trans, &data);
2703         len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2704         if (dump_rbs)
2705                 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
2706
2707         len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2708
2709         dump_data->len = len;
2710
2711         return dump_data;
2712 }
2713
2714 #ifdef CONFIG_PM_SLEEP
2715 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2716 {
2717         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2718                 return iwl_pci_fw_enter_d0i3(trans);
2719
2720         return 0;
2721 }
2722
2723 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
2724 {
2725         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2726                 iwl_pci_fw_exit_d0i3(trans);
2727 }
2728 #endif /* CONFIG_PM_SLEEP */
2729
2730 static const struct iwl_trans_ops trans_ops_pcie = {
2731         .start_hw = iwl_trans_pcie_start_hw,
2732         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2733         .fw_alive = iwl_trans_pcie_fw_alive,
2734         .start_fw = iwl_trans_pcie_start_fw,
2735         .stop_device = iwl_trans_pcie_stop_device,
2736
2737         .d3_suspend = iwl_trans_pcie_d3_suspend,
2738         .d3_resume = iwl_trans_pcie_d3_resume,
2739
2740 #ifdef CONFIG_PM_SLEEP
2741         .suspend = iwl_trans_pcie_suspend,
2742         .resume = iwl_trans_pcie_resume,
2743 #endif /* CONFIG_PM_SLEEP */
2744
2745         .send_cmd = iwl_trans_pcie_send_hcmd,
2746
2747         .tx = iwl_trans_pcie_tx,
2748         .reclaim = iwl_trans_pcie_reclaim,
2749
2750         .txq_disable = iwl_trans_pcie_txq_disable,
2751         .txq_enable = iwl_trans_pcie_txq_enable,
2752
2753         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2754         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2755         .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
2756
2757         .write8 = iwl_trans_pcie_write8,
2758         .write32 = iwl_trans_pcie_write32,
2759         .read32 = iwl_trans_pcie_read32,
2760         .read_prph = iwl_trans_pcie_read_prph,
2761         .write_prph = iwl_trans_pcie_write_prph,
2762         .read_mem = iwl_trans_pcie_read_mem,
2763         .write_mem = iwl_trans_pcie_write_mem,
2764         .configure = iwl_trans_pcie_configure,
2765         .set_pmi = iwl_trans_pcie_set_pmi,
2766         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2767         .release_nic_access = iwl_trans_pcie_release_nic_access,
2768         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2769
2770         .ref = iwl_trans_pcie_ref,
2771         .unref = iwl_trans_pcie_unref,
2772
2773         .dump_data = iwl_trans_pcie_dump_data,
2774 };
2775
2776 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2777                                        const struct pci_device_id *ent,
2778                                        const struct iwl_cfg *cfg)
2779 {
2780         struct iwl_trans_pcie *trans_pcie;
2781         struct iwl_trans *trans;
2782         int ret, addr_size;
2783
2784         trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2785                                 &pdev->dev, cfg, &trans_ops_pcie, 0);
2786         if (!trans)
2787                 return ERR_PTR(-ENOMEM);
2788
2789         trans->max_skb_frags = IWL_PCIE_MAX_FRAGS;
2790
2791         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2792
2793         trans_pcie->trans = trans;
2794         spin_lock_init(&trans_pcie->irq_lock);
2795         spin_lock_init(&trans_pcie->reg_lock);
2796         spin_lock_init(&trans_pcie->ref_lock);
2797         mutex_init(&trans_pcie->mutex);
2798         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2799         trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
2800         if (!trans_pcie->tso_hdr_page) {
2801                 ret = -ENOMEM;
2802                 goto out_no_pci;
2803         }
2804
2805         ret = pci_enable_device(pdev);
2806         if (ret)
2807                 goto out_no_pci;
2808
2809         if (!cfg->base_params->pcie_l1_allowed) {
2810                 /*
2811                  * W/A - seems to solve weird behavior. We need to remove this
2812                  * if we don't want to stay in L1 all the time. This wastes a
2813                  * lot of power.
2814                  */
2815                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2816                                        PCIE_LINK_STATE_L1 |
2817                                        PCIE_LINK_STATE_CLKPM);
2818         }
2819
2820         if (cfg->mq_rx_supported)
2821                 addr_size = 64;
2822         else
2823                 addr_size = 36;
2824
2825         pci_set_master(pdev);
2826
2827         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
2828         if (!ret)
2829                 ret = pci_set_consistent_dma_mask(pdev,
2830                                                   DMA_BIT_MASK(addr_size));
2831         if (ret) {
2832                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2833                 if (!ret)
2834                         ret = pci_set_consistent_dma_mask(pdev,
2835                                                           DMA_BIT_MASK(32));
2836                 /* both attempts failed: */
2837                 if (ret) {
2838                         dev_err(&pdev->dev, "No suitable DMA available\n");
2839                         goto out_pci_disable_device;
2840                 }
2841         }
2842
2843         ret = pci_request_regions(pdev, DRV_NAME);
2844         if (ret) {
2845                 dev_err(&pdev->dev, "pci_request_regions failed\n");
2846                 goto out_pci_disable_device;
2847         }
2848
2849         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2850         if (!trans_pcie->hw_base) {
2851                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2852                 ret = -ENODEV;
2853                 goto out_pci_release_regions;
2854         }
2855
2856         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2857          * PCI Tx retries from interfering with C3 CPU state */
2858         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2859
2860         trans->dev = &pdev->dev;
2861         trans_pcie->pci_dev = pdev;
2862         iwl_disable_interrupts(trans);
2863
2864         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2865         /*
2866          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2867          * changed, and now the revision step also includes bit 0-1 (no more
2868          * "dash" value). To keep hw_rev backwards compatible - we'll store it
2869          * in the old format.
2870          */
2871         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2872                 unsigned long flags;
2873
2874                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2875                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2876
2877                 ret = iwl_pcie_prepare_card_hw(trans);
2878                 if (ret) {
2879                         IWL_WARN(trans, "Exit HW not ready\n");
2880                         goto out_pci_disable_msi;
2881                 }
2882
2883                 /*
2884                  * in-order to recognize C step driver should read chip version
2885                  * id located at the AUX bus MISC address space.
2886                  */
2887                 iwl_set_bit(trans, CSR_GP_CNTRL,
2888                             CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2889                 udelay(2);
2890
2891                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2892                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2893                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2894                                    25000);
2895                 if (ret < 0) {
2896                         IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2897                         goto out_pci_disable_msi;
2898                 }
2899
2900                 if (iwl_trans_grab_nic_access(trans, &flags)) {
2901                         u32 hw_step;
2902
2903                         hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
2904                         hw_step |= ENABLE_WFPM;
2905                         iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
2906                         hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
2907                         hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2908                         if (hw_step == 0x3)
2909                                 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2910                                                 (SILICON_C_STEP << 2);
2911                         iwl_trans_release_nic_access(trans, &flags);
2912                 }
2913         }
2914
2915         iwl_pcie_set_interrupt_capa(pdev, trans);
2916         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2917         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2918                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2919
2920         /* Initialize the wait queue for commands */
2921         init_waitqueue_head(&trans_pcie->wait_command_queue);
2922
2923         init_waitqueue_head(&trans_pcie->d0i3_waitq);
2924
2925         if (trans_pcie->msix_enabled) {
2926                 if (iwl_pcie_init_msix_handler(pdev, trans_pcie))
2927                         goto out_pci_release_regions;
2928          } else {
2929                 ret = iwl_pcie_alloc_ict(trans);
2930                 if (ret)
2931                         goto out_pci_disable_msi;
2932
2933                 ret = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2934                                            iwl_pcie_irq_handler,
2935                                            IRQF_SHARED, DRV_NAME, trans);
2936                 if (ret) {
2937                         IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2938                         goto out_free_ict;
2939                 }
2940                 trans_pcie->inta_mask = CSR_INI_SET_MASK;
2941          }
2942
2943 #ifdef CONFIG_IWLWIFI_PCIE_RTPM
2944         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
2945 #else
2946         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
2947 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */
2948
2949         return trans;
2950
2951 out_free_ict:
2952         iwl_pcie_free_ict(trans);
2953 out_pci_disable_msi:
2954         pci_disable_msi(pdev);
2955 out_pci_release_regions:
2956         pci_release_regions(pdev);
2957 out_pci_disable_device:
2958         pci_disable_device(pdev);
2959 out_no_pci:
2960         free_percpu(trans_pcie->tso_hdr_page);
2961         iwl_trans_free(trans);
2962         return ERR_PTR(ret);
2963 }