2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/dmi.h>
13 #include <linux/init.h>
15 #include <linux/of_pci.h>
16 #include <linux/pci.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <linux/spinlock.h>
21 #include <linux/string.h>
22 #include <linux/log2.h>
23 #include <linux/pci-aspm.h>
24 #include <linux/pm_wakeup.h>
25 #include <linux/interrupt.h>
26 #include <linux/device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/pci_hotplug.h>
29 #include <asm/setup.h>
30 #include <linux/aer.h>
33 const char *pci_power_names[] = {
34 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
36 EXPORT_SYMBOL_GPL(pci_power_names);
38 int isa_dma_bridge_buggy;
39 EXPORT_SYMBOL(isa_dma_bridge_buggy);
42 EXPORT_SYMBOL(pci_pci_problems);
44 unsigned int pci_pm_d3_delay;
46 static void pci_pme_list_scan(struct work_struct *work);
48 static LIST_HEAD(pci_pme_list);
49 static DEFINE_MUTEX(pci_pme_list_mutex);
50 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
52 struct pci_pme_device {
53 struct list_head list;
57 #define PME_TIMEOUT 1000 /* How long between PME checks */
59 static void pci_dev_d3_sleep(struct pci_dev *dev)
61 unsigned int delay = dev->d3_delay;
63 if (delay < pci_pm_d3_delay)
64 delay = pci_pm_d3_delay;
69 #ifdef CONFIG_PCI_DOMAINS
70 int pci_domains_supported = 1;
73 #define DEFAULT_CARDBUS_IO_SIZE (256)
74 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
75 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
76 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
77 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
79 #define DEFAULT_HOTPLUG_IO_SIZE (256)
80 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
81 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
82 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
83 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
85 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
88 * The default CLS is used if arch didn't set CLS explicitly and not
89 * all pci devices agree on the same value. Arch can override either
90 * the dfl or actual value as it sees fit. Don't forget this is
91 * measured in 32-bit words, not bytes.
93 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
94 u8 pci_cache_line_size;
97 * If we set up a device for bus mastering, we need to check the latency
98 * timer as certain BIOSes forget to set it properly.
100 unsigned int pcibios_max_latency = 255;
102 /* If set, the PCIe ARI capability will not be used. */
103 static bool pcie_ari_disabled;
105 /* Disable bridge_d3 for all PCIe ports */
106 static bool pci_bridge_d3_disable;
107 /* Force bridge_d3 for all PCIe ports */
108 static bool pci_bridge_d3_force;
110 static int __init pcie_port_pm_setup(char *str)
112 if (!strcmp(str, "off"))
113 pci_bridge_d3_disable = true;
114 else if (!strcmp(str, "force"))
115 pci_bridge_d3_force = true;
118 __setup("pcie_port_pm=", pcie_port_pm_setup);
121 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
122 * @bus: pointer to PCI bus structure to search
124 * Given a PCI bus, returns the highest PCI bus number present in the set
125 * including the given PCI bus and its list of child PCI buses.
127 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
130 unsigned char max, n;
132 max = bus->busn_res.end;
133 list_for_each_entry(tmp, &bus->children, node) {
134 n = pci_bus_max_busnr(tmp);
140 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
142 #ifdef CONFIG_HAS_IOMEM
143 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
145 struct resource *res = &pdev->resource[bar];
148 * Make sure the BAR is actually a memory resource, not an IO resource
150 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
151 dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res);
154 return ioremap_nocache(res->start, resource_size(res));
156 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
158 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
161 * Make sure the BAR is actually a memory resource, not an IO resource
163 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
167 return ioremap_wc(pci_resource_start(pdev, bar),
168 pci_resource_len(pdev, bar));
170 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
174 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
175 u8 pos, int cap, int *ttl)
180 pci_bus_read_config_byte(bus, devfn, pos, &pos);
186 pci_bus_read_config_word(bus, devfn, pos, &ent);
198 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
201 int ttl = PCI_FIND_CAP_TTL;
203 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
206 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
208 return __pci_find_next_cap(dev->bus, dev->devfn,
209 pos + PCI_CAP_LIST_NEXT, cap);
211 EXPORT_SYMBOL_GPL(pci_find_next_capability);
213 static int __pci_bus_find_cap_start(struct pci_bus *bus,
214 unsigned int devfn, u8 hdr_type)
218 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
219 if (!(status & PCI_STATUS_CAP_LIST))
223 case PCI_HEADER_TYPE_NORMAL:
224 case PCI_HEADER_TYPE_BRIDGE:
225 return PCI_CAPABILITY_LIST;
226 case PCI_HEADER_TYPE_CARDBUS:
227 return PCI_CB_CAPABILITY_LIST;
234 * pci_find_capability - query for devices' capabilities
235 * @dev: PCI device to query
236 * @cap: capability code
238 * Tell if a device supports a given PCI capability.
239 * Returns the address of the requested capability structure within the
240 * device's PCI configuration space or 0 in case the device does not
241 * support it. Possible values for @cap:
243 * %PCI_CAP_ID_PM Power Management
244 * %PCI_CAP_ID_AGP Accelerated Graphics Port
245 * %PCI_CAP_ID_VPD Vital Product Data
246 * %PCI_CAP_ID_SLOTID Slot Identification
247 * %PCI_CAP_ID_MSI Message Signalled Interrupts
248 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
249 * %PCI_CAP_ID_PCIX PCI-X
250 * %PCI_CAP_ID_EXP PCI Express
252 int pci_find_capability(struct pci_dev *dev, int cap)
256 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
258 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
262 EXPORT_SYMBOL(pci_find_capability);
265 * pci_bus_find_capability - query for devices' capabilities
266 * @bus: the PCI bus to query
267 * @devfn: PCI device to query
268 * @cap: capability code
270 * Like pci_find_capability() but works for pci devices that do not have a
271 * pci_dev structure set up yet.
273 * Returns the address of the requested capability structure within the
274 * device's PCI configuration space or 0 in case the device does not
277 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
282 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
284 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
286 pos = __pci_find_next_cap(bus, devfn, pos, cap);
290 EXPORT_SYMBOL(pci_bus_find_capability);
293 * pci_find_next_ext_capability - Find an extended capability
294 * @dev: PCI device to query
295 * @start: address at which to start looking (0 to start at beginning of list)
296 * @cap: capability code
298 * Returns the address of the next matching extended capability structure
299 * within the device's PCI configuration space or 0 if the device does
300 * not support it. Some capabilities can occur several times, e.g., the
301 * vendor-specific capability, and this provides a way to find them all.
303 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
307 int pos = PCI_CFG_SPACE_SIZE;
309 /* minimum 8 bytes per capability */
310 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
312 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
318 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
322 * If we have no capabilities, this is indicated by cap ID,
323 * cap version and next pointer all being 0.
329 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
332 pos = PCI_EXT_CAP_NEXT(header);
333 if (pos < PCI_CFG_SPACE_SIZE)
336 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
342 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
345 * pci_find_ext_capability - Find an extended capability
346 * @dev: PCI device to query
347 * @cap: capability code
349 * Returns the address of the requested extended capability structure
350 * within the device's PCI configuration space or 0 if the device does
351 * not support it. Possible values for @cap:
353 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
354 * %PCI_EXT_CAP_ID_VC Virtual Channel
355 * %PCI_EXT_CAP_ID_DSN Device Serial Number
356 * %PCI_EXT_CAP_ID_PWR Power Budgeting
358 int pci_find_ext_capability(struct pci_dev *dev, int cap)
360 return pci_find_next_ext_capability(dev, 0, cap);
362 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
364 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
366 int rc, ttl = PCI_FIND_CAP_TTL;
369 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
370 mask = HT_3BIT_CAP_MASK;
372 mask = HT_5BIT_CAP_MASK;
374 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
375 PCI_CAP_ID_HT, &ttl);
377 rc = pci_read_config_byte(dev, pos + 3, &cap);
378 if (rc != PCIBIOS_SUCCESSFUL)
381 if ((cap & mask) == ht_cap)
384 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
385 pos + PCI_CAP_LIST_NEXT,
386 PCI_CAP_ID_HT, &ttl);
392 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
393 * @dev: PCI device to query
394 * @pos: Position from which to continue searching
395 * @ht_cap: Hypertransport capability code
397 * To be used in conjunction with pci_find_ht_capability() to search for
398 * all capabilities matching @ht_cap. @pos should always be a value returned
399 * from pci_find_ht_capability().
401 * NB. To be 100% safe against broken PCI devices, the caller should take
402 * steps to avoid an infinite loop.
404 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
406 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
408 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
411 * pci_find_ht_capability - query a device's Hypertransport capabilities
412 * @dev: PCI device to query
413 * @ht_cap: Hypertransport capability code
415 * Tell if a device supports a given Hypertransport capability.
416 * Returns an address within the device's PCI configuration space
417 * or 0 in case the device does not support the request capability.
418 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
419 * which has a Hypertransport capability matching @ht_cap.
421 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
425 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
427 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
431 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
434 * pci_find_parent_resource - return resource region of parent bus of given region
435 * @dev: PCI device structure contains resources to be searched
436 * @res: child resource record for which parent is sought
438 * For given resource region of given device, return the resource
439 * region of parent bus the given region is contained in.
441 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
442 struct resource *res)
444 const struct pci_bus *bus = dev->bus;
448 pci_bus_for_each_resource(bus, r, i) {
451 if (res->start && resource_contains(r, res)) {
454 * If the window is prefetchable but the BAR is
455 * not, the allocator made a mistake.
457 if (r->flags & IORESOURCE_PREFETCH &&
458 !(res->flags & IORESOURCE_PREFETCH))
462 * If we're below a transparent bridge, there may
463 * be both a positively-decoded aperture and a
464 * subtractively-decoded region that contain the BAR.
465 * We want the positively-decoded one, so this depends
466 * on pci_bus_for_each_resource() giving us those
474 EXPORT_SYMBOL(pci_find_parent_resource);
477 * pci_find_pcie_root_port - return PCIe Root Port
478 * @dev: PCI device to query
480 * Traverse up the parent chain and return the PCIe Root Port PCI Device
481 * for a given PCI Device.
483 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
485 struct pci_dev *bridge, *highest_pcie_bridge = NULL;
487 bridge = pci_upstream_bridge(dev);
488 while (bridge && pci_is_pcie(bridge)) {
489 highest_pcie_bridge = bridge;
490 bridge = pci_upstream_bridge(bridge);
493 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
496 return highest_pcie_bridge;
498 EXPORT_SYMBOL(pci_find_pcie_root_port);
501 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
502 * @dev: the PCI device to operate on
503 * @pos: config space offset of status word
504 * @mask: mask of bit(s) to care about in status word
506 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
508 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
512 /* Wait for Transaction Pending bit clean */
513 for (i = 0; i < 4; i++) {
516 msleep((1 << (i - 1)) * 100);
518 pci_read_config_word(dev, pos, &status);
519 if (!(status & mask))
527 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
528 * @dev: PCI device to have its BARs restored
530 * Restore the BAR values for a given device, so as to make it
531 * accessible by its driver.
533 static void pci_restore_bars(struct pci_dev *dev)
537 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
541 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
542 pci_update_resource(dev, i);
545 static const struct pci_platform_pm_ops *pci_platform_pm;
547 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
549 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
552 pci_platform_pm = ops;
556 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
558 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
561 static inline int platform_pci_set_power_state(struct pci_dev *dev,
564 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
567 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
569 return pci_platform_pm ?
570 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
573 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
575 return pci_platform_pm ?
576 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
579 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
581 return pci_platform_pm ?
582 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
585 static inline bool platform_pci_need_resume(struct pci_dev *dev)
587 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
591 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
593 * @dev: PCI device to handle.
594 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
597 * -EINVAL if the requested state is invalid.
598 * -EIO if device does not support PCI PM or its PM capabilities register has a
599 * wrong version, or device doesn't support the requested state.
600 * 0 if device already is in the requested state.
601 * 0 if device's power state has been successfully changed.
603 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
606 bool need_restore = false;
608 /* Check if we're already there */
609 if (dev->current_state == state)
615 if (state < PCI_D0 || state > PCI_D3hot)
618 /* Validate current state:
619 * Can enter D0 from any state, but if we can only go deeper
620 * to sleep if we're already in a low power state
622 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
623 && dev->current_state > state) {
624 dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n",
625 dev->current_state, state);
629 /* check if this device supports the desired state */
630 if ((state == PCI_D1 && !dev->d1_support)
631 || (state == PCI_D2 && !dev->d2_support))
634 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
636 /* If we're (effectively) in D3, force entire word to 0.
637 * This doesn't affect PME_Status, disables PME_En, and
638 * sets PowerState to 0.
640 switch (dev->current_state) {
644 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
649 case PCI_UNKNOWN: /* Boot-up */
650 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
651 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
653 /* Fall-through: force to D0 */
659 /* enter specified state */
660 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
662 /* Mandatory power management transition delays */
663 /* see PCI PM 1.1 5.6.1 table 18 */
664 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
665 pci_dev_d3_sleep(dev);
666 else if (state == PCI_D2 || dev->current_state == PCI_D2)
667 udelay(PCI_PM_D2_DELAY);
669 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
670 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
671 if (dev->current_state != state && printk_ratelimit())
672 dev_info(&dev->dev, "Refused to change power state, currently in D%d\n",
676 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
677 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
678 * from D3hot to D0 _may_ perform an internal reset, thereby
679 * going to "D0 Uninitialized" rather than "D0 Initialized".
680 * For example, at least some versions of the 3c905B and the
681 * 3c556B exhibit this behaviour.
683 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
684 * devices in a D3hot state at boot. Consequently, we need to
685 * restore at least the BARs so that the device will be
686 * accessible to its driver.
689 pci_restore_bars(dev);
692 pcie_aspm_pm_state_change(dev->bus->self);
698 * pci_update_current_state - Read PCI power state of given device from its
699 * PCI PM registers and cache it
700 * @dev: PCI device to handle.
701 * @state: State to cache in case the device doesn't have the PM capability
703 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
709 * Configuration space is not accessible for device in
710 * D3cold, so just keep or set D3cold for safety
712 if (dev->current_state == PCI_D3cold)
714 if (state == PCI_D3cold) {
715 dev->current_state = PCI_D3cold;
718 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
719 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
721 dev->current_state = state;
726 * pci_power_up - Put the given device into D0 forcibly
727 * @dev: PCI device to power up
729 void pci_power_up(struct pci_dev *dev)
731 if (platform_pci_power_manageable(dev))
732 platform_pci_set_power_state(dev, PCI_D0);
734 pci_raw_set_power_state(dev, PCI_D0);
735 pci_update_current_state(dev, PCI_D0);
739 * pci_platform_power_transition - Use platform to change device power state
740 * @dev: PCI device to handle.
741 * @state: State to put the device into.
743 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
747 if (platform_pci_power_manageable(dev)) {
748 error = platform_pci_set_power_state(dev, state);
750 pci_update_current_state(dev, state);
754 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
755 dev->current_state = PCI_D0;
761 * pci_wakeup - Wake up a PCI device
762 * @pci_dev: Device to handle.
763 * @ign: ignored parameter
765 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
767 pci_wakeup_event(pci_dev);
768 pm_request_resume(&pci_dev->dev);
773 * pci_wakeup_bus - Walk given bus and wake up devices on it
774 * @bus: Top bus of the subtree to walk.
776 static void pci_wakeup_bus(struct pci_bus *bus)
779 pci_walk_bus(bus, pci_wakeup, NULL);
783 * __pci_start_power_transition - Start power transition of a PCI device
784 * @dev: PCI device to handle.
785 * @state: State to put the device into.
787 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
789 if (state == PCI_D0) {
790 pci_platform_power_transition(dev, PCI_D0);
792 * Mandatory power management transition delays, see
793 * PCI Express Base Specification Revision 2.0 Section
794 * 6.6.1: Conventional Reset. Do not delay for
795 * devices powered on/off by corresponding bridge,
796 * because have already delayed for the bridge.
798 if (dev->runtime_d3cold) {
799 msleep(dev->d3cold_delay);
801 * When powering on a bridge from D3cold, the
802 * whole hierarchy may be powered on into
803 * D0uninitialized state, resume them to give
804 * them a chance to suspend again
806 pci_wakeup_bus(dev->subordinate);
812 * __pci_dev_set_current_state - Set current state of a PCI device
813 * @dev: Device to handle
814 * @data: pointer to state to be set
816 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
818 pci_power_t state = *(pci_power_t *)data;
820 dev->current_state = state;
825 * __pci_bus_set_current_state - Walk given bus and set current state of devices
826 * @bus: Top bus of the subtree to walk.
827 * @state: state to be set
829 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
832 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
836 * __pci_complete_power_transition - Complete power transition of a PCI device
837 * @dev: PCI device to handle.
838 * @state: State to put the device into.
840 * This function should not be called directly by device drivers.
842 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
848 ret = pci_platform_power_transition(dev, state);
849 /* Power off the bridge may power off the whole hierarchy */
850 if (!ret && state == PCI_D3cold)
851 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
854 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
857 * pci_set_power_state - Set the power state of a PCI device
858 * @dev: PCI device to handle.
859 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
861 * Transition a device to a new power state, using the platform firmware and/or
862 * the device's PCI PM registers.
865 * -EINVAL if the requested state is invalid.
866 * -EIO if device does not support PCI PM or its PM capabilities register has a
867 * wrong version, or device doesn't support the requested state.
868 * 0 if device already is in the requested state.
869 * 0 if device's power state has been successfully changed.
871 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
875 /* bound the state we're entering */
876 if (state > PCI_D3cold)
878 else if (state < PCI_D0)
880 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
882 * If the device or the parent bridge do not support PCI PM,
883 * ignore the request if we're doing anything other than putting
884 * it into D0 (which would only happen on boot).
888 /* Check if we're already there */
889 if (dev->current_state == state)
892 __pci_start_power_transition(dev, state);
894 /* This device is quirked not to be put into D3, so
895 don't put it in D3 */
896 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
900 * To put device in D3cold, we put device into D3hot in native
901 * way, then put device into D3cold with platform ops
903 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
906 if (!__pci_complete_power_transition(dev, state))
911 EXPORT_SYMBOL(pci_set_power_state);
914 * pci_choose_state - Choose the power state of a PCI device
915 * @dev: PCI device to be suspended
916 * @state: target sleep state for the whole system. This is the value
917 * that is passed to suspend() function.
919 * Returns PCI power state suitable for given device and given system
923 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
930 ret = platform_pci_choose_state(dev);
931 if (ret != PCI_POWER_ERROR)
934 switch (state.event) {
937 case PM_EVENT_FREEZE:
938 case PM_EVENT_PRETHAW:
939 /* REVISIT both freeze and pre-thaw "should" use D0 */
940 case PM_EVENT_SUSPEND:
941 case PM_EVENT_HIBERNATE:
944 dev_info(&dev->dev, "unrecognized suspend event %d\n",
950 EXPORT_SYMBOL(pci_choose_state);
952 #define PCI_EXP_SAVE_REGS 7
954 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
955 u16 cap, bool extended)
957 struct pci_cap_saved_state *tmp;
959 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
960 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
966 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
968 return _pci_find_saved_cap(dev, cap, false);
971 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
973 return _pci_find_saved_cap(dev, cap, true);
976 static int pci_save_pcie_state(struct pci_dev *dev)
979 struct pci_cap_saved_state *save_state;
982 if (!pci_is_pcie(dev))
985 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
987 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
991 cap = (u16 *)&save_state->cap.data[0];
992 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
993 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
994 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
995 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
996 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
997 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
998 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1003 static void pci_restore_pcie_state(struct pci_dev *dev)
1006 struct pci_cap_saved_state *save_state;
1009 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1013 cap = (u16 *)&save_state->cap.data[0];
1014 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1015 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1016 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1017 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1018 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1019 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1020 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1024 static int pci_save_pcix_state(struct pci_dev *dev)
1027 struct pci_cap_saved_state *save_state;
1029 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1033 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1035 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
1039 pci_read_config_word(dev, pos + PCI_X_CMD,
1040 (u16 *)save_state->cap.data);
1045 static void pci_restore_pcix_state(struct pci_dev *dev)
1048 struct pci_cap_saved_state *save_state;
1051 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1052 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1053 if (!save_state || !pos)
1055 cap = (u16 *)&save_state->cap.data[0];
1057 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1062 * pci_save_state - save the PCI configuration space of a device before suspending
1063 * @dev: - PCI device that we're dealing with
1065 int pci_save_state(struct pci_dev *dev)
1068 /* XXX: 100% dword access ok here? */
1069 for (i = 0; i < 16; i++)
1070 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1071 dev->state_saved = true;
1073 i = pci_save_pcie_state(dev);
1077 i = pci_save_pcix_state(dev);
1081 return pci_save_vc_state(dev);
1083 EXPORT_SYMBOL(pci_save_state);
1085 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1086 u32 saved_val, int retry)
1090 pci_read_config_dword(pdev, offset, &val);
1091 if (val == saved_val)
1095 dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1096 offset, val, saved_val);
1097 pci_write_config_dword(pdev, offset, saved_val);
1101 pci_read_config_dword(pdev, offset, &val);
1102 if (val == saved_val)
1109 static void pci_restore_config_space_range(struct pci_dev *pdev,
1110 int start, int end, int retry)
1114 for (index = end; index >= start; index--)
1115 pci_restore_config_dword(pdev, 4 * index,
1116 pdev->saved_config_space[index],
1120 static void pci_restore_config_space(struct pci_dev *pdev)
1122 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1123 pci_restore_config_space_range(pdev, 10, 15, 0);
1124 /* Restore BARs before the command register. */
1125 pci_restore_config_space_range(pdev, 4, 9, 10);
1126 pci_restore_config_space_range(pdev, 0, 3, 0);
1128 pci_restore_config_space_range(pdev, 0, 15, 0);
1133 * pci_restore_state - Restore the saved state of a PCI device
1134 * @dev: - PCI device that we're dealing with
1136 void pci_restore_state(struct pci_dev *dev)
1138 if (!dev->state_saved)
1141 /* PCI Express register must be restored first */
1142 pci_restore_pcie_state(dev);
1143 pci_restore_ats_state(dev);
1144 pci_restore_vc_state(dev);
1146 pci_cleanup_aer_error_status_regs(dev);
1148 pci_restore_config_space(dev);
1150 pci_restore_pcix_state(dev);
1151 pci_restore_msi_state(dev);
1153 /* Restore ACS and IOV configuration state */
1154 pci_enable_acs(dev);
1155 pci_restore_iov_state(dev);
1157 dev->state_saved = false;
1159 EXPORT_SYMBOL(pci_restore_state);
1161 struct pci_saved_state {
1162 u32 config_space[16];
1163 struct pci_cap_saved_data cap[0];
1167 * pci_store_saved_state - Allocate and return an opaque struct containing
1168 * the device saved state.
1169 * @dev: PCI device that we're dealing with
1171 * Return NULL if no state or error.
1173 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1175 struct pci_saved_state *state;
1176 struct pci_cap_saved_state *tmp;
1177 struct pci_cap_saved_data *cap;
1180 if (!dev->state_saved)
1183 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1185 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1186 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1188 state = kzalloc(size, GFP_KERNEL);
1192 memcpy(state->config_space, dev->saved_config_space,
1193 sizeof(state->config_space));
1196 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1197 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1198 memcpy(cap, &tmp->cap, len);
1199 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1201 /* Empty cap_save terminates list */
1205 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1208 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1209 * @dev: PCI device that we're dealing with
1210 * @state: Saved state returned from pci_store_saved_state()
1212 int pci_load_saved_state(struct pci_dev *dev,
1213 struct pci_saved_state *state)
1215 struct pci_cap_saved_data *cap;
1217 dev->state_saved = false;
1222 memcpy(dev->saved_config_space, state->config_space,
1223 sizeof(state->config_space));
1227 struct pci_cap_saved_state *tmp;
1229 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1230 if (!tmp || tmp->cap.size != cap->size)
1233 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1234 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1235 sizeof(struct pci_cap_saved_data) + cap->size);
1238 dev->state_saved = true;
1241 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1244 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1245 * and free the memory allocated for it.
1246 * @dev: PCI device that we're dealing with
1247 * @state: Pointer to saved state returned from pci_store_saved_state()
1249 int pci_load_and_free_saved_state(struct pci_dev *dev,
1250 struct pci_saved_state **state)
1252 int ret = pci_load_saved_state(dev, *state);
1257 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1259 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1261 return pci_enable_resources(dev, bars);
1264 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1267 struct pci_dev *bridge;
1271 err = pci_set_power_state(dev, PCI_D0);
1272 if (err < 0 && err != -EIO)
1275 bridge = pci_upstream_bridge(dev);
1277 pcie_aspm_powersave_config_link(bridge);
1279 err = pcibios_enable_device(dev, bars);
1282 pci_fixup_device(pci_fixup_enable, dev);
1284 if (dev->msi_enabled || dev->msix_enabled)
1287 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1289 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1290 if (cmd & PCI_COMMAND_INTX_DISABLE)
1291 pci_write_config_word(dev, PCI_COMMAND,
1292 cmd & ~PCI_COMMAND_INTX_DISABLE);
1299 * pci_reenable_device - Resume abandoned device
1300 * @dev: PCI device to be resumed
1302 * Note this function is a backend of pci_default_resume and is not supposed
1303 * to be called by normal code, write proper resume handler and use it instead.
1305 int pci_reenable_device(struct pci_dev *dev)
1307 if (pci_is_enabled(dev))
1308 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1311 EXPORT_SYMBOL(pci_reenable_device);
1313 static void pci_enable_bridge(struct pci_dev *dev)
1315 struct pci_dev *bridge;
1318 bridge = pci_upstream_bridge(dev);
1320 pci_enable_bridge(bridge);
1322 if (pci_is_enabled(dev)) {
1323 if (!dev->is_busmaster)
1324 pci_set_master(dev);
1328 retval = pci_enable_device(dev);
1330 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1332 pci_set_master(dev);
1335 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1337 struct pci_dev *bridge;
1342 * Power state could be unknown at this point, either due to a fresh
1343 * boot or a device removal call. So get the current power state
1344 * so that things like MSI message writing will behave as expected
1345 * (e.g. if the device really is in D0 at enable time).
1349 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1350 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1353 if (atomic_inc_return(&dev->enable_cnt) > 1)
1354 return 0; /* already enabled */
1356 bridge = pci_upstream_bridge(dev);
1358 pci_enable_bridge(bridge);
1360 /* only skip sriov related */
1361 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1362 if (dev->resource[i].flags & flags)
1364 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1365 if (dev->resource[i].flags & flags)
1368 err = do_pci_enable_device(dev, bars);
1370 atomic_dec(&dev->enable_cnt);
1375 * pci_enable_device_io - Initialize a device for use with IO space
1376 * @dev: PCI device to be initialized
1378 * Initialize device before it's used by a driver. Ask low-level code
1379 * to enable I/O resources. Wake up the device if it was suspended.
1380 * Beware, this function can fail.
1382 int pci_enable_device_io(struct pci_dev *dev)
1384 return pci_enable_device_flags(dev, IORESOURCE_IO);
1386 EXPORT_SYMBOL(pci_enable_device_io);
1389 * pci_enable_device_mem - Initialize a device for use with Memory space
1390 * @dev: PCI device to be initialized
1392 * Initialize device before it's used by a driver. Ask low-level code
1393 * to enable Memory resources. Wake up the device if it was suspended.
1394 * Beware, this function can fail.
1396 int pci_enable_device_mem(struct pci_dev *dev)
1398 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1400 EXPORT_SYMBOL(pci_enable_device_mem);
1403 * pci_enable_device - Initialize device before it's used by a driver.
1404 * @dev: PCI device to be initialized
1406 * Initialize device before it's used by a driver. Ask low-level code
1407 * to enable I/O and memory. Wake up the device if it was suspended.
1408 * Beware, this function can fail.
1410 * Note we don't actually enable the device many times if we call
1411 * this function repeatedly (we just increment the count).
1413 int pci_enable_device(struct pci_dev *dev)
1415 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1417 EXPORT_SYMBOL(pci_enable_device);
1420 * Managed PCI resources. This manages device on/off, intx/msi/msix
1421 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1422 * there's no need to track it separately. pci_devres is initialized
1423 * when a device is enabled using managed PCI device enable interface.
1426 unsigned int enabled:1;
1427 unsigned int pinned:1;
1428 unsigned int orig_intx:1;
1429 unsigned int restore_intx:1;
1433 static void pcim_release(struct device *gendev, void *res)
1435 struct pci_dev *dev = to_pci_dev(gendev);
1436 struct pci_devres *this = res;
1439 if (dev->msi_enabled)
1440 pci_disable_msi(dev);
1441 if (dev->msix_enabled)
1442 pci_disable_msix(dev);
1444 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1445 if (this->region_mask & (1 << i))
1446 pci_release_region(dev, i);
1448 if (this->restore_intx)
1449 pci_intx(dev, this->orig_intx);
1451 if (this->enabled && !this->pinned)
1452 pci_disable_device(dev);
1455 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1457 struct pci_devres *dr, *new_dr;
1459 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1463 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1466 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1469 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1471 if (pci_is_managed(pdev))
1472 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1477 * pcim_enable_device - Managed pci_enable_device()
1478 * @pdev: PCI device to be initialized
1480 * Managed pci_enable_device().
1482 int pcim_enable_device(struct pci_dev *pdev)
1484 struct pci_devres *dr;
1487 dr = get_pci_dr(pdev);
1493 rc = pci_enable_device(pdev);
1495 pdev->is_managed = 1;
1500 EXPORT_SYMBOL(pcim_enable_device);
1503 * pcim_pin_device - Pin managed PCI device
1504 * @pdev: PCI device to pin
1506 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1507 * driver detach. @pdev must have been enabled with
1508 * pcim_enable_device().
1510 void pcim_pin_device(struct pci_dev *pdev)
1512 struct pci_devres *dr;
1514 dr = find_pci_dr(pdev);
1515 WARN_ON(!dr || !dr->enabled);
1519 EXPORT_SYMBOL(pcim_pin_device);
1522 * pcibios_add_device - provide arch specific hooks when adding device dev
1523 * @dev: the PCI device being added
1525 * Permits the platform to provide architecture specific functionality when
1526 * devices are added. This is the default implementation. Architecture
1527 * implementations can override this.
1529 int __weak pcibios_add_device(struct pci_dev *dev)
1535 * pcibios_release_device - provide arch specific hooks when releasing device dev
1536 * @dev: the PCI device being released
1538 * Permits the platform to provide architecture specific functionality when
1539 * devices are released. This is the default implementation. Architecture
1540 * implementations can override this.
1542 void __weak pcibios_release_device(struct pci_dev *dev) {}
1545 * pcibios_disable_device - disable arch specific PCI resources for device dev
1546 * @dev: the PCI device to disable
1548 * Disables architecture specific PCI resources for the device. This
1549 * is the default implementation. Architecture implementations can
1552 void __weak pcibios_disable_device(struct pci_dev *dev) {}
1555 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1556 * @irq: ISA IRQ to penalize
1557 * @active: IRQ active or not
1559 * Permits the platform to provide architecture-specific functionality when
1560 * penalizing ISA IRQs. This is the default implementation. Architecture
1561 * implementations can override this.
1563 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1565 static void do_pci_disable_device(struct pci_dev *dev)
1569 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1570 if (pci_command & PCI_COMMAND_MASTER) {
1571 pci_command &= ~PCI_COMMAND_MASTER;
1572 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1575 pcibios_disable_device(dev);
1579 * pci_disable_enabled_device - Disable device without updating enable_cnt
1580 * @dev: PCI device to disable
1582 * NOTE: This function is a backend of PCI power management routines and is
1583 * not supposed to be called drivers.
1585 void pci_disable_enabled_device(struct pci_dev *dev)
1587 if (pci_is_enabled(dev))
1588 do_pci_disable_device(dev);
1592 * pci_disable_device - Disable PCI device after use
1593 * @dev: PCI device to be disabled
1595 * Signal to the system that the PCI device is not in use by the system
1596 * anymore. This only involves disabling PCI bus-mastering, if active.
1598 * Note we don't actually disable the device until all callers of
1599 * pci_enable_device() have called pci_disable_device().
1601 void pci_disable_device(struct pci_dev *dev)
1603 struct pci_devres *dr;
1605 dr = find_pci_dr(dev);
1609 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1610 "disabling already-disabled device");
1612 if (atomic_dec_return(&dev->enable_cnt) != 0)
1615 do_pci_disable_device(dev);
1617 dev->is_busmaster = 0;
1619 EXPORT_SYMBOL(pci_disable_device);
1622 * pcibios_set_pcie_reset_state - set reset state for device dev
1623 * @dev: the PCIe device reset
1624 * @state: Reset state to enter into
1627 * Sets the PCIe reset state for the device. This is the default
1628 * implementation. Architecture implementations can override this.
1630 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1631 enum pcie_reset_state state)
1637 * pci_set_pcie_reset_state - set reset state for device dev
1638 * @dev: the PCIe device reset
1639 * @state: Reset state to enter into
1642 * Sets the PCI reset state for the device.
1644 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1646 return pcibios_set_pcie_reset_state(dev, state);
1648 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1651 * pci_check_pme_status - Check if given device has generated PME.
1652 * @dev: Device to check.
1654 * Check the PME status of the device and if set, clear it and clear PME enable
1655 * (if set). Return 'true' if PME status and PME enable were both set or
1656 * 'false' otherwise.
1658 bool pci_check_pme_status(struct pci_dev *dev)
1667 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1668 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1669 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1672 /* Clear PME status. */
1673 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1674 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1675 /* Disable PME to avoid interrupt flood. */
1676 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1680 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1686 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1687 * @dev: Device to handle.
1688 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1690 * Check if @dev has generated PME and queue a resume request for it in that
1693 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1695 if (pme_poll_reset && dev->pme_poll)
1696 dev->pme_poll = false;
1698 if (pci_check_pme_status(dev)) {
1699 pci_wakeup_event(dev);
1700 pm_request_resume(&dev->dev);
1706 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1707 * @bus: Top bus of the subtree to walk.
1709 void pci_pme_wakeup_bus(struct pci_bus *bus)
1712 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1717 * pci_pme_capable - check the capability of PCI device to generate PME#
1718 * @dev: PCI device to handle.
1719 * @state: PCI state from which device will issue PME#.
1721 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1726 return !!(dev->pme_support & (1 << state));
1728 EXPORT_SYMBOL(pci_pme_capable);
1730 static void pci_pme_list_scan(struct work_struct *work)
1732 struct pci_pme_device *pme_dev, *n;
1734 mutex_lock(&pci_pme_list_mutex);
1735 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1736 if (pme_dev->dev->pme_poll) {
1737 struct pci_dev *bridge;
1739 bridge = pme_dev->dev->bus->self;
1741 * If bridge is in low power state, the
1742 * configuration space of subordinate devices
1743 * may be not accessible
1745 if (bridge && bridge->current_state != PCI_D0)
1747 pci_pme_wakeup(pme_dev->dev, NULL);
1749 list_del(&pme_dev->list);
1753 if (!list_empty(&pci_pme_list))
1754 schedule_delayed_work(&pci_pme_work,
1755 msecs_to_jiffies(PME_TIMEOUT));
1756 mutex_unlock(&pci_pme_list_mutex);
1759 static void __pci_pme_active(struct pci_dev *dev, bool enable)
1763 if (!dev->pme_support)
1766 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1767 /* Clear PME_Status by writing 1 to it and enable PME# */
1768 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1770 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1772 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1776 * pci_pme_active - enable or disable PCI device's PME# function
1777 * @dev: PCI device to handle.
1778 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1780 * The caller must verify that the device is capable of generating PME# before
1781 * calling this function with @enable equal to 'true'.
1783 void pci_pme_active(struct pci_dev *dev, bool enable)
1785 __pci_pme_active(dev, enable);
1788 * PCI (as opposed to PCIe) PME requires that the device have
1789 * its PME# line hooked up correctly. Not all hardware vendors
1790 * do this, so the PME never gets delivered and the device
1791 * remains asleep. The easiest way around this is to
1792 * periodically walk the list of suspended devices and check
1793 * whether any have their PME flag set. The assumption is that
1794 * we'll wake up often enough anyway that this won't be a huge
1795 * hit, and the power savings from the devices will still be a
1798 * Although PCIe uses in-band PME message instead of PME# line
1799 * to report PME, PME does not work for some PCIe devices in
1800 * reality. For example, there are devices that set their PME
1801 * status bits, but don't really bother to send a PME message;
1802 * there are PCI Express Root Ports that don't bother to
1803 * trigger interrupts when they receive PME messages from the
1804 * devices below. So PME poll is used for PCIe devices too.
1807 if (dev->pme_poll) {
1808 struct pci_pme_device *pme_dev;
1810 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1813 dev_warn(&dev->dev, "can't enable PME#\n");
1817 mutex_lock(&pci_pme_list_mutex);
1818 list_add(&pme_dev->list, &pci_pme_list);
1819 if (list_is_singular(&pci_pme_list))
1820 schedule_delayed_work(&pci_pme_work,
1821 msecs_to_jiffies(PME_TIMEOUT));
1822 mutex_unlock(&pci_pme_list_mutex);
1824 mutex_lock(&pci_pme_list_mutex);
1825 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1826 if (pme_dev->dev == dev) {
1827 list_del(&pme_dev->list);
1832 mutex_unlock(&pci_pme_list_mutex);
1836 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1838 EXPORT_SYMBOL(pci_pme_active);
1841 * __pci_enable_wake - enable PCI device as wakeup event source
1842 * @dev: PCI device affected
1843 * @state: PCI state from which device will issue wakeup events
1844 * @runtime: True if the events are to be generated at run time
1845 * @enable: True to enable event generation; false to disable
1847 * This enables the device as a wakeup event source, or disables it.
1848 * When such events involves platform-specific hooks, those hooks are
1849 * called automatically by this routine.
1851 * Devices with legacy power management (no standard PCI PM capabilities)
1852 * always require such platform hooks.
1855 * 0 is returned on success
1856 * -EINVAL is returned if device is not supposed to wake up the system
1857 * Error code depending on the platform is returned if both the platform and
1858 * the native mechanism fail to enable the generation of wake-up events
1860 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1861 bool runtime, bool enable)
1865 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1868 /* Don't do the same thing twice in a row for one device. */
1869 if (!!enable == !!dev->wakeup_prepared)
1873 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1874 * Anderson we should be doing PME# wake enable followed by ACPI wake
1875 * enable. To disable wake-up we call the platform first, for symmetry.
1881 if (pci_pme_capable(dev, state))
1882 pci_pme_active(dev, true);
1885 error = runtime ? platform_pci_run_wake(dev, true) :
1886 platform_pci_sleep_wake(dev, true);
1890 dev->wakeup_prepared = true;
1893 platform_pci_run_wake(dev, false);
1895 platform_pci_sleep_wake(dev, false);
1896 pci_pme_active(dev, false);
1897 dev->wakeup_prepared = false;
1902 EXPORT_SYMBOL(__pci_enable_wake);
1905 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1906 * @dev: PCI device to prepare
1907 * @enable: True to enable wake-up event generation; false to disable
1909 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1910 * and this function allows them to set that up cleanly - pci_enable_wake()
1911 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1912 * ordering constraints.
1914 * This function only returns error code if the device is not capable of
1915 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1916 * enable wake-up power for it.
1918 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1920 return pci_pme_capable(dev, PCI_D3cold) ?
1921 pci_enable_wake(dev, PCI_D3cold, enable) :
1922 pci_enable_wake(dev, PCI_D3hot, enable);
1924 EXPORT_SYMBOL(pci_wake_from_d3);
1927 * pci_target_state - find an appropriate low power state for a given PCI dev
1930 * Use underlying platform code to find a supported low power state for @dev.
1931 * If the platform can't manage @dev, return the deepest state from which it
1932 * can generate wake events, based on any available PME info.
1934 static pci_power_t pci_target_state(struct pci_dev *dev)
1936 pci_power_t target_state = PCI_D3hot;
1938 if (platform_pci_power_manageable(dev)) {
1940 * Call the platform to choose the target state of the device
1941 * and enable wake-up from this state if supported.
1943 pci_power_t state = platform_pci_choose_state(dev);
1946 case PCI_POWER_ERROR:
1951 if (pci_no_d1d2(dev))
1954 target_state = state;
1956 } else if (!dev->pm_cap) {
1957 target_state = PCI_D0;
1958 } else if (device_may_wakeup(&dev->dev)) {
1960 * Find the deepest state from which the device can generate
1961 * wake-up events, make it the target state and enable device
1964 if (dev->pme_support) {
1966 && !(dev->pme_support & (1 << target_state)))
1971 return target_state;
1975 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1976 * @dev: Device to handle.
1978 * Choose the power state appropriate for the device depending on whether
1979 * it can wake up the system and/or is power manageable by the platform
1980 * (PCI_D3hot is the default) and put the device into that state.
1982 int pci_prepare_to_sleep(struct pci_dev *dev)
1984 pci_power_t target_state = pci_target_state(dev);
1987 if (target_state == PCI_POWER_ERROR)
1990 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1992 error = pci_set_power_state(dev, target_state);
1995 pci_enable_wake(dev, target_state, false);
1999 EXPORT_SYMBOL(pci_prepare_to_sleep);
2002 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2003 * @dev: Device to handle.
2005 * Disable device's system wake-up capability and put it into D0.
2007 int pci_back_from_sleep(struct pci_dev *dev)
2009 pci_enable_wake(dev, PCI_D0, false);
2010 return pci_set_power_state(dev, PCI_D0);
2012 EXPORT_SYMBOL(pci_back_from_sleep);
2015 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2016 * @dev: PCI device being suspended.
2018 * Prepare @dev to generate wake-up events at run time and put it into a low
2021 int pci_finish_runtime_suspend(struct pci_dev *dev)
2023 pci_power_t target_state = pci_target_state(dev);
2026 if (target_state == PCI_POWER_ERROR)
2029 dev->runtime_d3cold = target_state == PCI_D3cold;
2031 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
2033 error = pci_set_power_state(dev, target_state);
2036 __pci_enable_wake(dev, target_state, true, false);
2037 dev->runtime_d3cold = false;
2044 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2045 * @dev: Device to check.
2047 * Return true if the device itself is capable of generating wake-up events
2048 * (through the platform or using the native PCIe PME) or if the device supports
2049 * PME and one of its upstream bridges can generate wake-up events.
2051 bool pci_dev_run_wake(struct pci_dev *dev)
2053 struct pci_bus *bus = dev->bus;
2055 if (device_run_wake(&dev->dev))
2058 if (!dev->pme_support)
2061 while (bus->parent) {
2062 struct pci_dev *bridge = bus->self;
2064 if (device_run_wake(&bridge->dev))
2070 /* We have reached the root bus. */
2072 return device_run_wake(bus->bridge);
2076 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2079 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2080 * @pci_dev: Device to check.
2082 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2083 * reconfigured due to wakeup settings difference between system and runtime
2084 * suspend and the current power state of it is suitable for the upcoming
2085 * (system) transition.
2087 * If the device is not configured for system wakeup, disable PME for it before
2088 * returning 'true' to prevent it from waking up the system unnecessarily.
2090 bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2092 struct device *dev = &pci_dev->dev;
2094 if (!pm_runtime_suspended(dev)
2095 || pci_target_state(pci_dev) != pci_dev->current_state
2096 || platform_pci_need_resume(pci_dev))
2100 * At this point the device is good to go unless it's been configured
2101 * to generate PME at the runtime suspend time, but it is not supposed
2102 * to wake up the system. In that case, simply disable PME for it
2103 * (it will have to be re-enabled on exit from system resume).
2105 * If the device's power state is D3cold and the platform check above
2106 * hasn't triggered, the device's configuration is suitable and we don't
2107 * need to manipulate it at all.
2109 spin_lock_irq(&dev->power.lock);
2111 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2112 !device_may_wakeup(dev))
2113 __pci_pme_active(pci_dev, false);
2115 spin_unlock_irq(&dev->power.lock);
2120 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2121 * @pci_dev: Device to handle.
2123 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2124 * it might have been disabled during the prepare phase of system suspend if
2125 * the device was not configured for system wakeup.
2127 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2129 struct device *dev = &pci_dev->dev;
2131 if (!pci_dev_run_wake(pci_dev))
2134 spin_lock_irq(&dev->power.lock);
2136 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2137 __pci_pme_active(pci_dev, true);
2139 spin_unlock_irq(&dev->power.lock);
2142 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2144 struct device *dev = &pdev->dev;
2145 struct device *parent = dev->parent;
2148 pm_runtime_get_sync(parent);
2149 pm_runtime_get_noresume(dev);
2151 * pdev->current_state is set to PCI_D3cold during suspending,
2152 * so wait until suspending completes
2154 pm_runtime_barrier(dev);
2156 * Only need to resume devices in D3cold, because config
2157 * registers are still accessible for devices suspended but
2160 if (pdev->current_state == PCI_D3cold)
2161 pm_runtime_resume(dev);
2164 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2166 struct device *dev = &pdev->dev;
2167 struct device *parent = dev->parent;
2169 pm_runtime_put(dev);
2171 pm_runtime_put_sync(parent);
2175 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2176 * @bridge: Bridge to check
2178 * This function checks if it is possible to move the bridge to D3.
2179 * Currently we only allow D3 for recent enough PCIe ports.
2181 static bool pci_bridge_d3_possible(struct pci_dev *bridge)
2185 if (!pci_is_pcie(bridge))
2188 switch (pci_pcie_type(bridge)) {
2189 case PCI_EXP_TYPE_ROOT_PORT:
2190 case PCI_EXP_TYPE_UPSTREAM:
2191 case PCI_EXP_TYPE_DOWNSTREAM:
2192 if (pci_bridge_d3_disable)
2194 if (pci_bridge_d3_force)
2198 * It should be safe to put PCIe ports from 2015 or newer
2201 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
2211 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2213 bool *d3cold_ok = data;
2217 * The device needs to be allowed to go D3cold and if it is wake
2218 * capable to do so from D3cold.
2220 no_d3cold = dev->no_d3cold || !dev->d3cold_allowed ||
2221 (device_may_wakeup(&dev->dev) && !pci_pme_capable(dev, PCI_D3cold)) ||
2222 !pci_power_manageable(dev);
2224 *d3cold_ok = !no_d3cold;
2230 * pci_bridge_d3_update - Update bridge D3 capabilities
2231 * @dev: PCI device which is changed
2232 * @remove: Is the device being removed
2234 * Update upstream bridge PM capabilities accordingly depending on if the
2235 * device PM configuration was changed or the device is being removed. The
2236 * change is also propagated upstream.
2238 static void pci_bridge_d3_update(struct pci_dev *dev, bool remove)
2240 struct pci_dev *bridge;
2241 bool d3cold_ok = true;
2243 bridge = pci_upstream_bridge(dev);
2244 if (!bridge || !pci_bridge_d3_possible(bridge))
2247 pci_dev_get(bridge);
2249 * If the device is removed we do not care about its D3cold
2253 pci_dev_check_d3cold(dev, &d3cold_ok);
2257 * We need to go through all children to find out if all of
2258 * them can still go to D3cold.
2260 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2264 if (bridge->bridge_d3 != d3cold_ok) {
2265 bridge->bridge_d3 = d3cold_ok;
2266 /* Propagate change to upstream bridges */
2267 pci_bridge_d3_update(bridge, false);
2270 pci_dev_put(bridge);
2274 * pci_bridge_d3_device_changed - Update bridge D3 capabilities on change
2275 * @dev: PCI device that was changed
2277 * If a device is added or its PM configuration, such as is it allowed to
2278 * enter D3cold, is changed this function updates upstream bridge PM
2279 * capabilities accordingly.
2281 void pci_bridge_d3_device_changed(struct pci_dev *dev)
2283 pci_bridge_d3_update(dev, false);
2287 * pci_bridge_d3_device_removed - Update bridge D3 capabilities on remove
2288 * @dev: PCI device being removed
2290 * Function updates upstream bridge PM capabilities based on other devices
2291 * still left on the bus.
2293 void pci_bridge_d3_device_removed(struct pci_dev *dev)
2295 pci_bridge_d3_update(dev, true);
2299 * pci_d3cold_enable - Enable D3cold for device
2300 * @dev: PCI device to handle
2302 * This function can be used in drivers to enable D3cold from the device
2303 * they handle. It also updates upstream PCI bridge PM capabilities
2306 void pci_d3cold_enable(struct pci_dev *dev)
2308 if (dev->no_d3cold) {
2309 dev->no_d3cold = false;
2310 pci_bridge_d3_device_changed(dev);
2313 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2316 * pci_d3cold_disable - Disable D3cold for device
2317 * @dev: PCI device to handle
2319 * This function can be used in drivers to disable D3cold from the device
2320 * they handle. It also updates upstream PCI bridge PM capabilities
2323 void pci_d3cold_disable(struct pci_dev *dev)
2325 if (!dev->no_d3cold) {
2326 dev->no_d3cold = true;
2327 pci_bridge_d3_device_changed(dev);
2330 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
2333 * pci_pm_init - Initialize PM functions of given PCI device
2334 * @dev: PCI device to handle.
2336 void pci_pm_init(struct pci_dev *dev)
2341 pm_runtime_forbid(&dev->dev);
2342 pm_runtime_set_active(&dev->dev);
2343 pm_runtime_enable(&dev->dev);
2344 device_enable_async_suspend(&dev->dev);
2345 dev->wakeup_prepared = false;
2348 dev->pme_support = 0;
2350 /* find PCI PM capability in list */
2351 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2354 /* Check device's ability to generate PME# */
2355 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2357 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2358 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
2359 pmc & PCI_PM_CAP_VER_MASK);
2364 dev->d3_delay = PCI_PM_D3_WAIT;
2365 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2366 dev->bridge_d3 = pci_bridge_d3_possible(dev);
2367 dev->d3cold_allowed = true;
2369 dev->d1_support = false;
2370 dev->d2_support = false;
2371 if (!pci_no_d1d2(dev)) {
2372 if (pmc & PCI_PM_CAP_D1)
2373 dev->d1_support = true;
2374 if (pmc & PCI_PM_CAP_D2)
2375 dev->d2_support = true;
2377 if (dev->d1_support || dev->d2_support)
2378 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
2379 dev->d1_support ? " D1" : "",
2380 dev->d2_support ? " D2" : "");
2383 pmc &= PCI_PM_CAP_PME_MASK;
2385 dev_printk(KERN_DEBUG, &dev->dev,
2386 "PME# supported from%s%s%s%s%s\n",
2387 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2388 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2389 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2390 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2391 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2392 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2393 dev->pme_poll = true;
2395 * Make device's PM flags reflect the wake-up capability, but
2396 * let the user space enable it to wake up the system as needed.
2398 device_set_wakeup_capable(&dev->dev, true);
2399 /* Disable the PME# generation functionality */
2400 pci_pme_active(dev, false);
2404 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2406 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
2410 case PCI_EA_P_VF_MEM:
2411 flags |= IORESOURCE_MEM;
2413 case PCI_EA_P_MEM_PREFETCH:
2414 case PCI_EA_P_VF_MEM_PREFETCH:
2415 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2418 flags |= IORESOURCE_IO;
2427 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2430 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2431 return &dev->resource[bei];
2432 #ifdef CONFIG_PCI_IOV
2433 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2434 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2435 return &dev->resource[PCI_IOV_RESOURCES +
2436 bei - PCI_EA_BEI_VF_BAR0];
2438 else if (bei == PCI_EA_BEI_ROM)
2439 return &dev->resource[PCI_ROM_RESOURCE];
2444 /* Read an Enhanced Allocation (EA) entry */
2445 static int pci_ea_read(struct pci_dev *dev, int offset)
2447 struct resource *res;
2448 int ent_size, ent_offset = offset;
2449 resource_size_t start, end;
2450 unsigned long flags;
2451 u32 dw0, bei, base, max_offset;
2453 bool support_64 = (sizeof(resource_size_t) >= 8);
2455 pci_read_config_dword(dev, ent_offset, &dw0);
2458 /* Entry size field indicates DWORDs after 1st */
2459 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2461 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2464 bei = (dw0 & PCI_EA_BEI) >> 4;
2465 prop = (dw0 & PCI_EA_PP) >> 8;
2468 * If the Property is in the reserved range, try the Secondary
2471 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
2472 prop = (dw0 & PCI_EA_SP) >> 16;
2473 if (prop > PCI_EA_P_BRIDGE_IO)
2476 res = pci_ea_get_resource(dev, bei, prop);
2478 dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei);
2482 flags = pci_ea_flags(dev, prop);
2484 dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop);
2489 pci_read_config_dword(dev, ent_offset, &base);
2490 start = (base & PCI_EA_FIELD_MASK);
2493 /* Read MaxOffset */
2494 pci_read_config_dword(dev, ent_offset, &max_offset);
2497 /* Read Base MSBs (if 64-bit entry) */
2498 if (base & PCI_EA_IS_64) {
2501 pci_read_config_dword(dev, ent_offset, &base_upper);
2504 flags |= IORESOURCE_MEM_64;
2506 /* entry starts above 32-bit boundary, can't use */
2507 if (!support_64 && base_upper)
2511 start |= ((u64)base_upper << 32);
2514 end = start + (max_offset | 0x03);
2516 /* Read MaxOffset MSBs (if 64-bit entry) */
2517 if (max_offset & PCI_EA_IS_64) {
2518 u32 max_offset_upper;
2520 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2523 flags |= IORESOURCE_MEM_64;
2525 /* entry too big, can't use */
2526 if (!support_64 && max_offset_upper)
2530 end += ((u64)max_offset_upper << 32);
2534 dev_err(&dev->dev, "EA Entry crosses address boundary\n");
2538 if (ent_size != ent_offset - offset) {
2540 "EA Entry Size (%d) does not match length read (%d)\n",
2541 ent_size, ent_offset - offset);
2545 res->name = pci_name(dev);
2550 if (bei <= PCI_EA_BEI_BAR5)
2551 dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2553 else if (bei == PCI_EA_BEI_ROM)
2554 dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2556 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2557 dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2558 bei - PCI_EA_BEI_VF_BAR0, res, prop);
2560 dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2564 return offset + ent_size;
2567 /* Enhanced Allocation Initialization */
2568 void pci_ea_init(struct pci_dev *dev)
2575 /* find PCI EA capability in list */
2576 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
2580 /* determine the number of entries */
2581 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
2583 num_ent &= PCI_EA_NUM_ENT_MASK;
2585 offset = ea + PCI_EA_FIRST_ENT;
2587 /* Skip DWORD 2 for type 1 functions */
2588 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2591 /* parse each EA entry */
2592 for (i = 0; i < num_ent; ++i)
2593 offset = pci_ea_read(dev, offset);
2596 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2597 struct pci_cap_saved_state *new_cap)
2599 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2603 * _pci_add_cap_save_buffer - allocate buffer for saving given
2604 * capability registers
2605 * @dev: the PCI device
2606 * @cap: the capability to allocate the buffer for
2607 * @extended: Standard or Extended capability ID
2608 * @size: requested size of the buffer
2610 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2611 bool extended, unsigned int size)
2614 struct pci_cap_saved_state *save_state;
2617 pos = pci_find_ext_capability(dev, cap);
2619 pos = pci_find_capability(dev, cap);
2624 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2628 save_state->cap.cap_nr = cap;
2629 save_state->cap.cap_extended = extended;
2630 save_state->cap.size = size;
2631 pci_add_saved_cap(dev, save_state);
2636 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2638 return _pci_add_cap_save_buffer(dev, cap, false, size);
2641 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2643 return _pci_add_cap_save_buffer(dev, cap, true, size);
2647 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2648 * @dev: the PCI device
2650 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2654 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2655 PCI_EXP_SAVE_REGS * sizeof(u16));
2658 "unable to preallocate PCI Express save buffer\n");
2660 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2663 "unable to preallocate PCI-X save buffer\n");
2665 pci_allocate_vc_save_buffers(dev);
2668 void pci_free_cap_save_buffers(struct pci_dev *dev)
2670 struct pci_cap_saved_state *tmp;
2671 struct hlist_node *n;
2673 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2678 * pci_configure_ari - enable or disable ARI forwarding
2679 * @dev: the PCI device
2681 * If @dev and its upstream bridge both support ARI, enable ARI in the
2682 * bridge. Otherwise, disable ARI in the bridge.
2684 void pci_configure_ari(struct pci_dev *dev)
2687 struct pci_dev *bridge;
2689 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2692 bridge = dev->bus->self;
2696 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2697 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2700 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2701 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2702 PCI_EXP_DEVCTL2_ARI);
2703 bridge->ari_enabled = 1;
2705 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2706 PCI_EXP_DEVCTL2_ARI);
2707 bridge->ari_enabled = 0;
2711 static int pci_acs_enable;
2714 * pci_request_acs - ask for ACS to be enabled if supported
2716 void pci_request_acs(void)
2722 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2723 * @dev: the PCI device
2725 static void pci_std_enable_acs(struct pci_dev *dev)
2731 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2735 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2736 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2738 /* Source Validation */
2739 ctrl |= (cap & PCI_ACS_SV);
2741 /* P2P Request Redirect */
2742 ctrl |= (cap & PCI_ACS_RR);
2744 /* P2P Completion Redirect */
2745 ctrl |= (cap & PCI_ACS_CR);
2747 /* Upstream Forwarding */
2748 ctrl |= (cap & PCI_ACS_UF);
2750 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2754 * pci_enable_acs - enable ACS if hardware support it
2755 * @dev: the PCI device
2757 void pci_enable_acs(struct pci_dev *dev)
2759 if (!pci_acs_enable)
2762 if (!pci_dev_specific_enable_acs(dev))
2765 pci_std_enable_acs(dev);
2768 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2773 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2778 * Except for egress control, capabilities are either required
2779 * or only required if controllable. Features missing from the
2780 * capability field can therefore be assumed as hard-wired enabled.
2782 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2783 acs_flags &= (cap | PCI_ACS_EC);
2785 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2786 return (ctrl & acs_flags) == acs_flags;
2790 * pci_acs_enabled - test ACS against required flags for a given device
2791 * @pdev: device to test
2792 * @acs_flags: required PCI ACS flags
2794 * Return true if the device supports the provided flags. Automatically
2795 * filters out flags that are not implemented on multifunction devices.
2797 * Note that this interface checks the effective ACS capabilities of the
2798 * device rather than the actual capabilities. For instance, most single
2799 * function endpoints are not required to support ACS because they have no
2800 * opportunity for peer-to-peer access. We therefore return 'true'
2801 * regardless of whether the device exposes an ACS capability. This makes
2802 * it much easier for callers of this function to ignore the actual type
2803 * or topology of the device when testing ACS support.
2805 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2809 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2814 * Conventional PCI and PCI-X devices never support ACS, either
2815 * effectively or actually. The shared bus topology implies that
2816 * any device on the bus can receive or snoop DMA.
2818 if (!pci_is_pcie(pdev))
2821 switch (pci_pcie_type(pdev)) {
2823 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2824 * but since their primary interface is PCI/X, we conservatively
2825 * handle them as we would a non-PCIe device.
2827 case PCI_EXP_TYPE_PCIE_BRIDGE:
2829 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2830 * applicable... must never implement an ACS Extended Capability...".
2831 * This seems arbitrary, but we take a conservative interpretation
2832 * of this statement.
2834 case PCI_EXP_TYPE_PCI_BRIDGE:
2835 case PCI_EXP_TYPE_RC_EC:
2838 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2839 * implement ACS in order to indicate their peer-to-peer capabilities,
2840 * regardless of whether they are single- or multi-function devices.
2842 case PCI_EXP_TYPE_DOWNSTREAM:
2843 case PCI_EXP_TYPE_ROOT_PORT:
2844 return pci_acs_flags_enabled(pdev, acs_flags);
2846 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2847 * implemented by the remaining PCIe types to indicate peer-to-peer
2848 * capabilities, but only when they are part of a multifunction
2849 * device. The footnote for section 6.12 indicates the specific
2850 * PCIe types included here.
2852 case PCI_EXP_TYPE_ENDPOINT:
2853 case PCI_EXP_TYPE_UPSTREAM:
2854 case PCI_EXP_TYPE_LEG_END:
2855 case PCI_EXP_TYPE_RC_END:
2856 if (!pdev->multifunction)
2859 return pci_acs_flags_enabled(pdev, acs_flags);
2863 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2864 * to single function devices with the exception of downstream ports.
2870 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2871 * @start: starting downstream device
2872 * @end: ending upstream device or NULL to search to the root bus
2873 * @acs_flags: required flags
2875 * Walk up a device tree from start to end testing PCI ACS support. If
2876 * any step along the way does not support the required flags, return false.
2878 bool pci_acs_path_enabled(struct pci_dev *start,
2879 struct pci_dev *end, u16 acs_flags)
2881 struct pci_dev *pdev, *parent = start;
2886 if (!pci_acs_enabled(pdev, acs_flags))
2889 if (pci_is_root_bus(pdev->bus))
2890 return (end == NULL);
2892 parent = pdev->bus->self;
2893 } while (pdev != end);
2899 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2900 * @dev: the PCI device
2901 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2903 * Perform INTx swizzling for a device behind one level of bridge. This is
2904 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2905 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2906 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2907 * the PCI Express Base Specification, Revision 2.1)
2909 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2913 if (pci_ari_enabled(dev->bus))
2916 slot = PCI_SLOT(dev->devfn);
2918 return (((pin - 1) + slot) % 4) + 1;
2921 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2929 while (!pci_is_root_bus(dev->bus)) {
2930 pin = pci_swizzle_interrupt_pin(dev, pin);
2931 dev = dev->bus->self;
2938 * pci_common_swizzle - swizzle INTx all the way to root bridge
2939 * @dev: the PCI device
2940 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2942 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2943 * bridges all the way up to a PCI root bus.
2945 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2949 while (!pci_is_root_bus(dev->bus)) {
2950 pin = pci_swizzle_interrupt_pin(dev, pin);
2951 dev = dev->bus->self;
2954 return PCI_SLOT(dev->devfn);
2956 EXPORT_SYMBOL_GPL(pci_common_swizzle);
2959 * pci_release_region - Release a PCI bar
2960 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2961 * @bar: BAR to release
2963 * Releases the PCI I/O and memory resources previously reserved by a
2964 * successful call to pci_request_region. Call this function only
2965 * after all use of the PCI regions has ceased.
2967 void pci_release_region(struct pci_dev *pdev, int bar)
2969 struct pci_devres *dr;
2971 if (pci_resource_len(pdev, bar) == 0)
2973 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2974 release_region(pci_resource_start(pdev, bar),
2975 pci_resource_len(pdev, bar));
2976 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2977 release_mem_region(pci_resource_start(pdev, bar),
2978 pci_resource_len(pdev, bar));
2980 dr = find_pci_dr(pdev);
2982 dr->region_mask &= ~(1 << bar);
2984 EXPORT_SYMBOL(pci_release_region);
2987 * __pci_request_region - Reserved PCI I/O and memory resource
2988 * @pdev: PCI device whose resources are to be reserved
2989 * @bar: BAR to be reserved
2990 * @res_name: Name to be associated with resource.
2991 * @exclusive: whether the region access is exclusive or not
2993 * Mark the PCI region associated with PCI device @pdev BR @bar as
2994 * being reserved by owner @res_name. Do not access any
2995 * address inside the PCI regions unless this call returns
2998 * If @exclusive is set, then the region is marked so that userspace
2999 * is explicitly not allowed to map the resource via /dev/mem or
3000 * sysfs MMIO access.
3002 * Returns 0 on success, or %EBUSY on error. A warning
3003 * message is also printed on failure.
3005 static int __pci_request_region(struct pci_dev *pdev, int bar,
3006 const char *res_name, int exclusive)
3008 struct pci_devres *dr;
3010 if (pci_resource_len(pdev, bar) == 0)
3013 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3014 if (!request_region(pci_resource_start(pdev, bar),
3015 pci_resource_len(pdev, bar), res_name))
3017 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3018 if (!__request_mem_region(pci_resource_start(pdev, bar),
3019 pci_resource_len(pdev, bar), res_name,
3024 dr = find_pci_dr(pdev);
3026 dr->region_mask |= 1 << bar;
3031 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
3032 &pdev->resource[bar]);
3037 * pci_request_region - Reserve PCI I/O and memory resource
3038 * @pdev: PCI device whose resources are to be reserved
3039 * @bar: BAR to be reserved
3040 * @res_name: Name to be associated with resource
3042 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3043 * being reserved by owner @res_name. Do not access any
3044 * address inside the PCI regions unless this call returns
3047 * Returns 0 on success, or %EBUSY on error. A warning
3048 * message is also printed on failure.
3050 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3052 return __pci_request_region(pdev, bar, res_name, 0);
3054 EXPORT_SYMBOL(pci_request_region);
3057 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3058 * @pdev: PCI device whose resources are to be reserved
3059 * @bar: BAR to be reserved
3060 * @res_name: Name to be associated with resource.
3062 * Mark the PCI region associated with PCI device @pdev BR @bar as
3063 * being reserved by owner @res_name. Do not access any
3064 * address inside the PCI regions unless this call returns
3067 * Returns 0 on success, or %EBUSY on error. A warning
3068 * message is also printed on failure.
3070 * The key difference that _exclusive makes it that userspace is
3071 * explicitly not allowed to map the resource via /dev/mem or
3074 int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
3075 const char *res_name)
3077 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
3079 EXPORT_SYMBOL(pci_request_region_exclusive);
3082 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3083 * @pdev: PCI device whose resources were previously reserved
3084 * @bars: Bitmask of BARs to be released
3086 * Release selected PCI I/O and memory resources previously reserved.
3087 * Call this function only after all use of the PCI regions has ceased.
3089 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3093 for (i = 0; i < 6; i++)
3094 if (bars & (1 << i))
3095 pci_release_region(pdev, i);
3097 EXPORT_SYMBOL(pci_release_selected_regions);
3099 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3100 const char *res_name, int excl)
3104 for (i = 0; i < 6; i++)
3105 if (bars & (1 << i))
3106 if (__pci_request_region(pdev, i, res_name, excl))
3112 if (bars & (1 << i))
3113 pci_release_region(pdev, i);
3120 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3121 * @pdev: PCI device whose resources are to be reserved
3122 * @bars: Bitmask of BARs to be requested
3123 * @res_name: Name to be associated with resource
3125 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3126 const char *res_name)
3128 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3130 EXPORT_SYMBOL(pci_request_selected_regions);
3132 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3133 const char *res_name)
3135 return __pci_request_selected_regions(pdev, bars, res_name,
3136 IORESOURCE_EXCLUSIVE);
3138 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3141 * pci_release_regions - Release reserved PCI I/O and memory resources
3142 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3144 * Releases all PCI I/O and memory resources previously reserved by a
3145 * successful call to pci_request_regions. Call this function only
3146 * after all use of the PCI regions has ceased.
3149 void pci_release_regions(struct pci_dev *pdev)
3151 pci_release_selected_regions(pdev, (1 << 6) - 1);
3153 EXPORT_SYMBOL(pci_release_regions);
3156 * pci_request_regions - Reserved PCI I/O and memory resources
3157 * @pdev: PCI device whose resources are to be reserved
3158 * @res_name: Name to be associated with resource.
3160 * Mark all PCI regions associated with PCI device @pdev as
3161 * being reserved by owner @res_name. Do not access any
3162 * address inside the PCI regions unless this call returns
3165 * Returns 0 on success, or %EBUSY on error. A warning
3166 * message is also printed on failure.
3168 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3170 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
3172 EXPORT_SYMBOL(pci_request_regions);
3175 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3176 * @pdev: PCI device whose resources are to be reserved
3177 * @res_name: Name to be associated with resource.
3179 * Mark all PCI regions associated with PCI device @pdev as
3180 * being reserved by owner @res_name. Do not access any
3181 * address inside the PCI regions unless this call returns
3184 * pci_request_regions_exclusive() will mark the region so that
3185 * /dev/mem and the sysfs MMIO access will not be allowed.
3187 * Returns 0 on success, or %EBUSY on error. A warning
3188 * message is also printed on failure.
3190 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3192 return pci_request_selected_regions_exclusive(pdev,
3193 ((1 << 6) - 1), res_name);
3195 EXPORT_SYMBOL(pci_request_regions_exclusive);
3199 struct list_head list;
3201 resource_size_t size;
3204 static LIST_HEAD(io_range_list);
3205 static DEFINE_SPINLOCK(io_range_lock);
3209 * Record the PCI IO range (expressed as CPU physical address + size).
3210 * Return a negative value if an error has occured, zero otherwise
3212 int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size)
3217 struct io_range *range;
3218 resource_size_t allocated_size = 0;
3220 /* check if the range hasn't been previously recorded */
3221 spin_lock(&io_range_lock);
3222 list_for_each_entry(range, &io_range_list, list) {
3223 if (addr >= range->start && addr + size <= range->start + size) {
3224 /* range already registered, bail out */
3227 allocated_size += range->size;
3230 /* range not registed yet, check for available space */
3231 if (allocated_size + size - 1 > IO_SPACE_LIMIT) {
3232 /* if it's too big check if 64K space can be reserved */
3233 if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) {
3239 pr_warn("Requested IO range too big, new size set to 64K\n");
3242 /* add the range to the list */
3243 range = kzalloc(sizeof(*range), GFP_ATOMIC);
3249 range->start = addr;
3252 list_add_tail(&range->list, &io_range_list);
3255 spin_unlock(&io_range_lock);
3261 phys_addr_t pci_pio_to_address(unsigned long pio)
3263 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
3266 struct io_range *range;
3267 resource_size_t allocated_size = 0;
3269 if (pio > IO_SPACE_LIMIT)
3272 spin_lock(&io_range_lock);
3273 list_for_each_entry(range, &io_range_list, list) {
3274 if (pio >= allocated_size && pio < allocated_size + range->size) {
3275 address = range->start + pio - allocated_size;
3278 allocated_size += range->size;
3280 spin_unlock(&io_range_lock);
3286 unsigned long __weak pci_address_to_pio(phys_addr_t address)
3289 struct io_range *res;
3290 resource_size_t offset = 0;
3291 unsigned long addr = -1;
3293 spin_lock(&io_range_lock);
3294 list_for_each_entry(res, &io_range_list, list) {
3295 if (address >= res->start && address < res->start + res->size) {
3296 addr = address - res->start + offset;
3299 offset += res->size;
3301 spin_unlock(&io_range_lock);
3305 if (address > IO_SPACE_LIMIT)
3306 return (unsigned long)-1;
3308 return (unsigned long) address;
3313 * pci_remap_iospace - Remap the memory mapped I/O space
3314 * @res: Resource describing the I/O space
3315 * @phys_addr: physical address of range to be mapped
3317 * Remap the memory mapped I/O space described by the @res
3318 * and the CPU physical address @phys_addr into virtual address space.
3319 * Only architectures that have memory mapped IO functions defined
3320 * (and the PCI_IOBASE value defined) should call this function.
3322 int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3324 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3325 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3327 if (!(res->flags & IORESOURCE_IO))
3330 if (res->end > IO_SPACE_LIMIT)
3333 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3334 pgprot_device(PAGE_KERNEL));
3336 /* this architecture does not have memory mapped I/O space,
3337 so this function should never be called */
3338 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3343 static void __pci_set_master(struct pci_dev *dev, bool enable)
3347 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
3349 cmd = old_cmd | PCI_COMMAND_MASTER;
3351 cmd = old_cmd & ~PCI_COMMAND_MASTER;
3352 if (cmd != old_cmd) {
3353 dev_dbg(&dev->dev, "%s bus mastering\n",
3354 enable ? "enabling" : "disabling");
3355 pci_write_config_word(dev, PCI_COMMAND, cmd);
3357 dev->is_busmaster = enable;
3361 * pcibios_setup - process "pci=" kernel boot arguments
3362 * @str: string used to pass in "pci=" kernel boot arguments
3364 * Process kernel boot arguments. This is the default implementation.
3365 * Architecture specific implementations can override this as necessary.
3367 char * __weak __init pcibios_setup(char *str)
3373 * pcibios_set_master - enable PCI bus-mastering for device dev
3374 * @dev: the PCI device to enable
3376 * Enables PCI bus-mastering for the device. This is the default
3377 * implementation. Architecture specific implementations can override
3378 * this if necessary.
3380 void __weak pcibios_set_master(struct pci_dev *dev)
3384 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3385 if (pci_is_pcie(dev))
3388 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
3390 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
3391 else if (lat > pcibios_max_latency)
3392 lat = pcibios_max_latency;
3396 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
3400 * pci_set_master - enables bus-mastering for device dev
3401 * @dev: the PCI device to enable
3403 * Enables bus-mastering on the device and calls pcibios_set_master()
3404 * to do the needed arch specific settings.
3406 void pci_set_master(struct pci_dev *dev)
3408 __pci_set_master(dev, true);
3409 pcibios_set_master(dev);
3411 EXPORT_SYMBOL(pci_set_master);
3414 * pci_clear_master - disables bus-mastering for device dev
3415 * @dev: the PCI device to disable
3417 void pci_clear_master(struct pci_dev *dev)
3419 __pci_set_master(dev, false);
3421 EXPORT_SYMBOL(pci_clear_master);
3424 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3425 * @dev: the PCI device for which MWI is to be enabled
3427 * Helper function for pci_set_mwi.
3428 * Originally copied from drivers/net/acenic.c.
3429 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3431 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3433 int pci_set_cacheline_size(struct pci_dev *dev)
3437 if (!pci_cache_line_size)
3440 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3441 equal to or multiple of the right value. */
3442 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3443 if (cacheline_size >= pci_cache_line_size &&
3444 (cacheline_size % pci_cache_line_size) == 0)
3447 /* Write the correct value. */
3448 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
3450 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3451 if (cacheline_size == pci_cache_line_size)
3454 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n",
3455 pci_cache_line_size << 2);
3459 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
3462 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3463 * @dev: the PCI device for which MWI is enabled
3465 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3467 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3469 int pci_set_mwi(struct pci_dev *dev)
3471 #ifdef PCI_DISABLE_MWI
3477 rc = pci_set_cacheline_size(dev);
3481 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3482 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
3483 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
3484 cmd |= PCI_COMMAND_INVALIDATE;
3485 pci_write_config_word(dev, PCI_COMMAND, cmd);
3490 EXPORT_SYMBOL(pci_set_mwi);
3493 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3494 * @dev: the PCI device for which MWI is enabled
3496 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3497 * Callers are not required to check the return value.
3499 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3501 int pci_try_set_mwi(struct pci_dev *dev)
3503 #ifdef PCI_DISABLE_MWI
3506 return pci_set_mwi(dev);
3509 EXPORT_SYMBOL(pci_try_set_mwi);
3512 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3513 * @dev: the PCI device to disable
3515 * Disables PCI Memory-Write-Invalidate transaction on the device
3517 void pci_clear_mwi(struct pci_dev *dev)
3519 #ifndef PCI_DISABLE_MWI
3522 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3523 if (cmd & PCI_COMMAND_INVALIDATE) {
3524 cmd &= ~PCI_COMMAND_INVALIDATE;
3525 pci_write_config_word(dev, PCI_COMMAND, cmd);
3529 EXPORT_SYMBOL(pci_clear_mwi);
3532 * pci_intx - enables/disables PCI INTx for device dev
3533 * @pdev: the PCI device to operate on
3534 * @enable: boolean: whether to enable or disable PCI INTx
3536 * Enables/disables PCI INTx for device dev
3538 void pci_intx(struct pci_dev *pdev, int enable)
3540 u16 pci_command, new;
3542 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
3545 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
3547 new = pci_command | PCI_COMMAND_INTX_DISABLE;
3549 if (new != pci_command) {
3550 struct pci_devres *dr;
3552 pci_write_config_word(pdev, PCI_COMMAND, new);
3554 dr = find_pci_dr(pdev);
3555 if (dr && !dr->restore_intx) {
3556 dr->restore_intx = 1;
3557 dr->orig_intx = !enable;
3561 EXPORT_SYMBOL_GPL(pci_intx);
3564 * pci_intx_mask_supported - probe for INTx masking support
3565 * @dev: the PCI device to operate on
3567 * Check if the device dev support INTx masking via the config space
3570 bool pci_intx_mask_supported(struct pci_dev *dev)
3572 bool mask_supported = false;
3575 if (dev->broken_intx_masking)
3578 pci_cfg_access_lock(dev);
3580 pci_read_config_word(dev, PCI_COMMAND, &orig);
3581 pci_write_config_word(dev, PCI_COMMAND,
3582 orig ^ PCI_COMMAND_INTX_DISABLE);
3583 pci_read_config_word(dev, PCI_COMMAND, &new);
3586 * There's no way to protect against hardware bugs or detect them
3587 * reliably, but as long as we know what the value should be, let's
3588 * go ahead and check it.
3590 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
3591 dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n",
3593 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
3594 mask_supported = true;
3595 pci_write_config_word(dev, PCI_COMMAND, orig);
3598 pci_cfg_access_unlock(dev);
3599 return mask_supported;
3601 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
3603 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3605 struct pci_bus *bus = dev->bus;
3606 bool mask_updated = true;
3607 u32 cmd_status_dword;
3608 u16 origcmd, newcmd;
3609 unsigned long flags;
3613 * We do a single dword read to retrieve both command and status.
3614 * Document assumptions that make this possible.
3616 BUILD_BUG_ON(PCI_COMMAND % 4);
3617 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3619 raw_spin_lock_irqsave(&pci_lock, flags);
3621 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3623 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3626 * Check interrupt status register to see whether our device
3627 * triggered the interrupt (when masking) or the next IRQ is
3628 * already pending (when unmasking).
3630 if (mask != irq_pending) {
3631 mask_updated = false;
3635 origcmd = cmd_status_dword;
3636 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3638 newcmd |= PCI_COMMAND_INTX_DISABLE;
3639 if (newcmd != origcmd)
3640 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3643 raw_spin_unlock_irqrestore(&pci_lock, flags);
3645 return mask_updated;
3649 * pci_check_and_mask_intx - mask INTx on pending interrupt
3650 * @dev: the PCI device to operate on
3652 * Check if the device dev has its INTx line asserted, mask it and
3653 * return true in that case. False is returned if not interrupt was
3656 bool pci_check_and_mask_intx(struct pci_dev *dev)
3658 return pci_check_and_set_intx_mask(dev, true);
3660 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3663 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3664 * @dev: the PCI device to operate on
3666 * Check if the device dev has its INTx line asserted, unmask it if not
3667 * and return true. False is returned and the mask remains active if
3668 * there was still an interrupt pending.
3670 bool pci_check_and_unmask_intx(struct pci_dev *dev)
3672 return pci_check_and_set_intx_mask(dev, false);
3674 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3677 * pci_wait_for_pending_transaction - waits for pending transaction
3678 * @dev: the PCI device to operate on
3680 * Return 0 if transaction is pending 1 otherwise.
3682 int pci_wait_for_pending_transaction(struct pci_dev *dev)
3684 if (!pci_is_pcie(dev))
3687 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
3688 PCI_EXP_DEVSTA_TRPND);
3690 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3693 * We should only need to wait 100ms after FLR, but some devices take longer.
3694 * Wait for up to 1000ms for config space to return something other than -1.
3695 * Intel IGD requires this when an LCD panel is attached. We read the 2nd
3696 * dword because VFs don't implement the 1st dword.
3698 static void pci_flr_wait(struct pci_dev *dev)
3705 pci_read_config_dword(dev, PCI_COMMAND, &id);
3706 } while (i++ < 10 && id == ~0);
3709 dev_warn(&dev->dev, "Failed to return from FLR\n");
3711 dev_info(&dev->dev, "Required additional %dms to return from FLR\n",
3715 static int pcie_flr(struct pci_dev *dev, int probe)
3719 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3720 if (!(cap & PCI_EXP_DEVCAP_FLR))
3726 if (!pci_wait_for_pending_transaction(dev))
3727 dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
3729 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3734 static int pci_af_flr(struct pci_dev *dev, int probe)
3739 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3743 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3744 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3751 * Wait for Transaction Pending bit to clear. A word-aligned test
3752 * is used, so we use the conrol offset rather than status and shift
3753 * the test bit to match.
3755 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
3756 PCI_AF_STATUS_TP << 8))
3757 dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
3759 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3765 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3766 * @dev: Device to reset.
3767 * @probe: If set, only check if the device can be reset this way.
3769 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3770 * unset, it will be reinitialized internally when going from PCI_D3hot to
3771 * PCI_D0. If that's the case and the device is not in a low-power state
3772 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3774 * NOTE: This causes the caller to sleep for twice the device power transition
3775 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3776 * by default (i.e. unless the @dev's d3_delay field has a different value).
3777 * Moreover, only devices in D0 can be reset by this function.
3779 static int pci_pm_reset(struct pci_dev *dev, int probe)
3783 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
3786 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3787 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3793 if (dev->current_state != PCI_D0)
3796 csr &= ~PCI_PM_CTRL_STATE_MASK;
3798 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3799 pci_dev_d3_sleep(dev);
3801 csr &= ~PCI_PM_CTRL_STATE_MASK;
3803 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3804 pci_dev_d3_sleep(dev);
3809 void pci_reset_secondary_bus(struct pci_dev *dev)
3813 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3814 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3815 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3817 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3818 * this to 2ms to ensure that we meet the minimum requirement.
3822 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3823 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3826 * Trhfa for conventional PCI is 2^25 clock cycles.
3827 * Assuming a minimum 33MHz clock this results in a 1s
3828 * delay before we can consider subordinate devices to
3829 * be re-initialized. PCIe has some ways to shorten this,
3830 * but we don't make use of them yet.
3835 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
3837 pci_reset_secondary_bus(dev);
3841 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3842 * @dev: Bridge device
3844 * Use the bridge control register to assert reset on the secondary bus.
3845 * Devices on the secondary bus are left in power-on state.
3847 void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3849 pcibios_reset_secondary_bus(dev);
3851 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3853 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3855 struct pci_dev *pdev;
3857 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
3858 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3861 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3868 pci_reset_bridge_secondary_bus(dev->bus->self);
3873 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3877 if (!hotplug || !try_module_get(hotplug->ops->owner))
3880 if (hotplug->ops->reset_slot)
3881 rc = hotplug->ops->reset_slot(hotplug, probe);
3883 module_put(hotplug->ops->owner);
3888 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3890 struct pci_dev *pdev;
3892 if (dev->subordinate || !dev->slot ||
3893 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3896 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3897 if (pdev != dev && pdev->slot == dev->slot)
3900 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3903 static int __pci_dev_reset(struct pci_dev *dev, int probe)
3909 rc = pci_dev_specific_reset(dev, probe);
3913 rc = pcie_flr(dev, probe);
3917 rc = pci_af_flr(dev, probe);
3921 rc = pci_pm_reset(dev, probe);
3925 rc = pci_dev_reset_slot_function(dev, probe);
3929 rc = pci_parent_bus_reset(dev, probe);
3934 static void pci_dev_lock(struct pci_dev *dev)
3936 pci_cfg_access_lock(dev);
3937 /* block PM suspend, driver probe, etc. */
3938 device_lock(&dev->dev);
3941 /* Return 1 on successful lock, 0 on contention */
3942 static int pci_dev_trylock(struct pci_dev *dev)
3944 if (pci_cfg_access_trylock(dev)) {
3945 if (device_trylock(&dev->dev))
3947 pci_cfg_access_unlock(dev);
3953 static void pci_dev_unlock(struct pci_dev *dev)
3955 device_unlock(&dev->dev);
3956 pci_cfg_access_unlock(dev);
3960 * pci_reset_notify - notify device driver of reset
3961 * @dev: device to be notified of reset
3962 * @prepare: 'true' if device is about to be reset; 'false' if reset attempt
3965 * Must be called prior to device access being disabled and after device
3966 * access is restored.
3968 static void pci_reset_notify(struct pci_dev *dev, bool prepare)
3970 const struct pci_error_handlers *err_handler =
3971 dev->driver ? dev->driver->err_handler : NULL;
3972 if (err_handler && err_handler->reset_notify)
3973 err_handler->reset_notify(dev, prepare);
3976 static void pci_dev_save_and_disable(struct pci_dev *dev)
3978 pci_reset_notify(dev, true);
3981 * Wake-up device prior to save. PM registers default to D0 after
3982 * reset and a simple register restore doesn't reliably return
3983 * to a non-D0 state anyway.
3985 pci_set_power_state(dev, PCI_D0);
3987 pci_save_state(dev);
3989 * Disable the device by clearing the Command register, except for
3990 * INTx-disable which is set. This not only disables MMIO and I/O port
3991 * BARs, but also prevents the device from being Bus Master, preventing
3992 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
3993 * compliant devices, INTx-disable prevents legacy interrupts.
3995 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3998 static void pci_dev_restore(struct pci_dev *dev)
4000 pci_restore_state(dev);
4001 pci_reset_notify(dev, false);
4004 static int pci_dev_reset(struct pci_dev *dev, int probe)
4011 rc = __pci_dev_reset(dev, probe);
4014 pci_dev_unlock(dev);
4020 * __pci_reset_function - reset a PCI device function
4021 * @dev: PCI device to reset
4023 * Some devices allow an individual function to be reset without affecting
4024 * other functions in the same device. The PCI device must be responsive
4025 * to PCI config space in order to use this function.
4027 * The device function is presumed to be unused when this function is called.
4028 * Resetting the device will make the contents of PCI configuration space
4029 * random, so any caller of this must be prepared to reinitialise the
4030 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4033 * Returns 0 if the device function was successfully reset or negative if the
4034 * device doesn't support resetting a single function.
4036 int __pci_reset_function(struct pci_dev *dev)
4038 return pci_dev_reset(dev, 0);
4040 EXPORT_SYMBOL_GPL(__pci_reset_function);
4043 * __pci_reset_function_locked - reset a PCI device function while holding
4044 * the @dev mutex lock.
4045 * @dev: PCI device to reset
4047 * Some devices allow an individual function to be reset without affecting
4048 * other functions in the same device. The PCI device must be responsive
4049 * to PCI config space in order to use this function.
4051 * The device function is presumed to be unused and the caller is holding
4052 * the device mutex lock when this function is called.
4053 * Resetting the device will make the contents of PCI configuration space
4054 * random, so any caller of this must be prepared to reinitialise the
4055 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4058 * Returns 0 if the device function was successfully reset or negative if the
4059 * device doesn't support resetting a single function.
4061 int __pci_reset_function_locked(struct pci_dev *dev)
4063 return __pci_dev_reset(dev, 0);
4065 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
4068 * pci_probe_reset_function - check whether the device can be safely reset
4069 * @dev: PCI device to reset
4071 * Some devices allow an individual function to be reset without affecting
4072 * other functions in the same device. The PCI device must be responsive
4073 * to PCI config space in order to use this function.
4075 * Returns 0 if the device function can be reset or negative if the
4076 * device doesn't support resetting a single function.
4078 int pci_probe_reset_function(struct pci_dev *dev)
4080 return pci_dev_reset(dev, 1);
4084 * pci_reset_function - quiesce and reset a PCI device function
4085 * @dev: PCI device to reset
4087 * Some devices allow an individual function to be reset without affecting
4088 * other functions in the same device. The PCI device must be responsive
4089 * to PCI config space in order to use this function.
4091 * This function does not just reset the PCI portion of a device, but
4092 * clears all the state associated with the device. This function differs
4093 * from __pci_reset_function in that it saves and restores device state
4096 * Returns 0 if the device function was successfully reset or negative if the
4097 * device doesn't support resetting a single function.
4099 int pci_reset_function(struct pci_dev *dev)
4103 rc = pci_dev_reset(dev, 1);
4107 pci_dev_save_and_disable(dev);
4109 rc = pci_dev_reset(dev, 0);
4111 pci_dev_restore(dev);
4115 EXPORT_SYMBOL_GPL(pci_reset_function);
4118 * pci_try_reset_function - quiesce and reset a PCI device function
4119 * @dev: PCI device to reset
4121 * Same as above, except return -EAGAIN if unable to lock device.
4123 int pci_try_reset_function(struct pci_dev *dev)
4127 rc = pci_dev_reset(dev, 1);
4131 pci_dev_save_and_disable(dev);
4133 if (pci_dev_trylock(dev)) {
4134 rc = __pci_dev_reset(dev, 0);
4135 pci_dev_unlock(dev);
4139 pci_dev_restore(dev);
4143 EXPORT_SYMBOL_GPL(pci_try_reset_function);
4145 /* Do any devices on or below this bus prevent a bus reset? */
4146 static bool pci_bus_resetable(struct pci_bus *bus)
4148 struct pci_dev *dev;
4150 list_for_each_entry(dev, &bus->devices, bus_list) {
4151 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4152 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4159 /* Lock devices from the top of the tree down */
4160 static void pci_bus_lock(struct pci_bus *bus)
4162 struct pci_dev *dev;
4164 list_for_each_entry(dev, &bus->devices, bus_list) {
4166 if (dev->subordinate)
4167 pci_bus_lock(dev->subordinate);
4171 /* Unlock devices from the bottom of the tree up */
4172 static void pci_bus_unlock(struct pci_bus *bus)
4174 struct pci_dev *dev;
4176 list_for_each_entry(dev, &bus->devices, bus_list) {
4177 if (dev->subordinate)
4178 pci_bus_unlock(dev->subordinate);
4179 pci_dev_unlock(dev);
4183 /* Return 1 on successful lock, 0 on contention */
4184 static int pci_bus_trylock(struct pci_bus *bus)
4186 struct pci_dev *dev;
4188 list_for_each_entry(dev, &bus->devices, bus_list) {
4189 if (!pci_dev_trylock(dev))
4191 if (dev->subordinate) {
4192 if (!pci_bus_trylock(dev->subordinate)) {
4193 pci_dev_unlock(dev);
4201 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
4202 if (dev->subordinate)
4203 pci_bus_unlock(dev->subordinate);
4204 pci_dev_unlock(dev);
4209 /* Do any devices on or below this slot prevent a bus reset? */
4210 static bool pci_slot_resetable(struct pci_slot *slot)
4212 struct pci_dev *dev;
4214 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4215 if (!dev->slot || dev->slot != slot)
4217 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4218 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4225 /* Lock devices from the top of the tree down */
4226 static void pci_slot_lock(struct pci_slot *slot)
4228 struct pci_dev *dev;
4230 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4231 if (!dev->slot || dev->slot != slot)
4234 if (dev->subordinate)
4235 pci_bus_lock(dev->subordinate);
4239 /* Unlock devices from the bottom of the tree up */
4240 static void pci_slot_unlock(struct pci_slot *slot)
4242 struct pci_dev *dev;
4244 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4245 if (!dev->slot || dev->slot != slot)
4247 if (dev->subordinate)
4248 pci_bus_unlock(dev->subordinate);
4249 pci_dev_unlock(dev);
4253 /* Return 1 on successful lock, 0 on contention */
4254 static int pci_slot_trylock(struct pci_slot *slot)
4256 struct pci_dev *dev;
4258 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4259 if (!dev->slot || dev->slot != slot)
4261 if (!pci_dev_trylock(dev))
4263 if (dev->subordinate) {
4264 if (!pci_bus_trylock(dev->subordinate)) {
4265 pci_dev_unlock(dev);
4273 list_for_each_entry_continue_reverse(dev,
4274 &slot->bus->devices, bus_list) {
4275 if (!dev->slot || dev->slot != slot)
4277 if (dev->subordinate)
4278 pci_bus_unlock(dev->subordinate);
4279 pci_dev_unlock(dev);
4284 /* Save and disable devices from the top of the tree down */
4285 static void pci_bus_save_and_disable(struct pci_bus *bus)
4287 struct pci_dev *dev;
4289 list_for_each_entry(dev, &bus->devices, bus_list) {
4290 pci_dev_save_and_disable(dev);
4291 if (dev->subordinate)
4292 pci_bus_save_and_disable(dev->subordinate);
4297 * Restore devices from top of the tree down - parent bridges need to be
4298 * restored before we can get to subordinate devices.
4300 static void pci_bus_restore(struct pci_bus *bus)
4302 struct pci_dev *dev;
4304 list_for_each_entry(dev, &bus->devices, bus_list) {
4305 pci_dev_restore(dev);
4306 if (dev->subordinate)
4307 pci_bus_restore(dev->subordinate);
4311 /* Save and disable devices from the top of the tree down */
4312 static void pci_slot_save_and_disable(struct pci_slot *slot)
4314 struct pci_dev *dev;
4316 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4317 if (!dev->slot || dev->slot != slot)
4319 pci_dev_save_and_disable(dev);
4320 if (dev->subordinate)
4321 pci_bus_save_and_disable(dev->subordinate);
4326 * Restore devices from top of the tree down - parent bridges need to be
4327 * restored before we can get to subordinate devices.
4329 static void pci_slot_restore(struct pci_slot *slot)
4331 struct pci_dev *dev;
4333 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4334 if (!dev->slot || dev->slot != slot)
4336 pci_dev_restore(dev);
4337 if (dev->subordinate)
4338 pci_bus_restore(dev->subordinate);
4342 static int pci_slot_reset(struct pci_slot *slot, int probe)
4346 if (!slot || !pci_slot_resetable(slot))
4350 pci_slot_lock(slot);
4354 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
4357 pci_slot_unlock(slot);
4363 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4364 * @slot: PCI slot to probe
4366 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4368 int pci_probe_reset_slot(struct pci_slot *slot)
4370 return pci_slot_reset(slot, 1);
4372 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
4375 * pci_reset_slot - reset a PCI slot
4376 * @slot: PCI slot to reset
4378 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4379 * independent of other slots. For instance, some slots may support slot power
4380 * control. In the case of a 1:1 bus to slot architecture, this function may
4381 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4382 * Generally a slot reset should be attempted before a bus reset. All of the
4383 * function of the slot and any subordinate buses behind the slot are reset
4384 * through this function. PCI config space of all devices in the slot and
4385 * behind the slot is saved before and restored after reset.
4387 * Return 0 on success, non-zero on error.
4389 int pci_reset_slot(struct pci_slot *slot)
4393 rc = pci_slot_reset(slot, 1);
4397 pci_slot_save_and_disable(slot);
4399 rc = pci_slot_reset(slot, 0);
4401 pci_slot_restore(slot);
4405 EXPORT_SYMBOL_GPL(pci_reset_slot);
4408 * pci_try_reset_slot - Try to reset a PCI slot
4409 * @slot: PCI slot to reset
4411 * Same as above except return -EAGAIN if the slot cannot be locked
4413 int pci_try_reset_slot(struct pci_slot *slot)
4417 rc = pci_slot_reset(slot, 1);
4421 pci_slot_save_and_disable(slot);
4423 if (pci_slot_trylock(slot)) {
4425 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
4426 pci_slot_unlock(slot);
4430 pci_slot_restore(slot);
4434 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
4436 static int pci_bus_reset(struct pci_bus *bus, int probe)
4438 if (!bus->self || !pci_bus_resetable(bus))
4448 pci_reset_bridge_secondary_bus(bus->self);
4450 pci_bus_unlock(bus);
4456 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4457 * @bus: PCI bus to probe
4459 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4461 int pci_probe_reset_bus(struct pci_bus *bus)
4463 return pci_bus_reset(bus, 1);
4465 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
4468 * pci_reset_bus - reset a PCI bus
4469 * @bus: top level PCI bus to reset
4471 * Do a bus reset on the given bus and any subordinate buses, saving
4472 * and restoring state of all devices.
4474 * Return 0 on success, non-zero on error.
4476 int pci_reset_bus(struct pci_bus *bus)
4480 rc = pci_bus_reset(bus, 1);
4484 pci_bus_save_and_disable(bus);
4486 rc = pci_bus_reset(bus, 0);
4488 pci_bus_restore(bus);
4492 EXPORT_SYMBOL_GPL(pci_reset_bus);
4495 * pci_try_reset_bus - Try to reset a PCI bus
4496 * @bus: top level PCI bus to reset
4498 * Same as above except return -EAGAIN if the bus cannot be locked
4500 int pci_try_reset_bus(struct pci_bus *bus)
4504 rc = pci_bus_reset(bus, 1);
4508 pci_bus_save_and_disable(bus);
4510 if (pci_bus_trylock(bus)) {
4512 pci_reset_bridge_secondary_bus(bus->self);
4513 pci_bus_unlock(bus);
4517 pci_bus_restore(bus);
4521 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
4524 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
4525 * @dev: PCI device to query
4527 * Returns mmrbc: maximum designed memory read count in bytes
4528 * or appropriate error value.
4530 int pcix_get_max_mmrbc(struct pci_dev *dev)
4535 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4539 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4542 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
4544 EXPORT_SYMBOL(pcix_get_max_mmrbc);
4547 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
4548 * @dev: PCI device to query
4550 * Returns mmrbc: maximum memory read count in bytes
4551 * or appropriate error value.
4553 int pcix_get_mmrbc(struct pci_dev *dev)
4558 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4562 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4565 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
4567 EXPORT_SYMBOL(pcix_get_mmrbc);
4570 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4571 * @dev: PCI device to query
4572 * @mmrbc: maximum memory read count in bytes
4573 * valid values are 512, 1024, 2048, 4096
4575 * If possible sets maximum memory read byte count, some bridges have erratas
4576 * that prevent this.
4578 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
4584 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
4587 v = ffs(mmrbc) - 10;
4589 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4593 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4596 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
4599 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4602 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
4604 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
4607 cmd &= ~PCI_X_CMD_MAX_READ;
4609 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
4614 EXPORT_SYMBOL(pcix_set_mmrbc);
4617 * pcie_get_readrq - get PCI Express read request size
4618 * @dev: PCI device to query
4620 * Returns maximum memory read request in bytes
4621 * or appropriate error value.
4623 int pcie_get_readrq(struct pci_dev *dev)
4627 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4629 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4631 EXPORT_SYMBOL(pcie_get_readrq);
4634 * pcie_set_readrq - set PCI Express maximum memory read request
4635 * @dev: PCI device to query
4636 * @rq: maximum memory read count in bytes
4637 * valid values are 128, 256, 512, 1024, 2048, 4096
4639 * If possible sets maximum memory read request in bytes
4641 int pcie_set_readrq(struct pci_dev *dev, int rq)
4645 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
4649 * If using the "performance" PCIe config, we clamp the
4650 * read rq size to the max packet size to prevent the
4651 * host bridge generating requests larger than we can
4654 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
4655 int mps = pcie_get_mps(dev);
4661 v = (ffs(rq) - 8) << 12;
4663 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4664 PCI_EXP_DEVCTL_READRQ, v);
4666 EXPORT_SYMBOL(pcie_set_readrq);
4669 * pcie_get_mps - get PCI Express maximum payload size
4670 * @dev: PCI device to query
4672 * Returns maximum payload size in bytes
4674 int pcie_get_mps(struct pci_dev *dev)
4678 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4680 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4682 EXPORT_SYMBOL(pcie_get_mps);
4685 * pcie_set_mps - set PCI Express maximum payload size
4686 * @dev: PCI device to query
4687 * @mps: maximum payload size in bytes
4688 * valid values are 128, 256, 512, 1024, 2048, 4096
4690 * If possible sets maximum payload size
4692 int pcie_set_mps(struct pci_dev *dev, int mps)
4696 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
4700 if (v > dev->pcie_mpss)
4704 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4705 PCI_EXP_DEVCTL_PAYLOAD, v);
4707 EXPORT_SYMBOL(pcie_set_mps);
4710 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4711 * @dev: PCI device to query
4712 * @speed: storage for minimum speed
4713 * @width: storage for minimum width
4715 * This function will walk up the PCI device chain and determine the minimum
4716 * link width and speed of the device.
4718 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
4719 enum pcie_link_width *width)
4723 *speed = PCI_SPEED_UNKNOWN;
4724 *width = PCIE_LNK_WIDTH_UNKNOWN;
4728 enum pci_bus_speed next_speed;
4729 enum pcie_link_width next_width;
4731 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4735 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4736 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4737 PCI_EXP_LNKSTA_NLW_SHIFT;
4739 if (next_speed < *speed)
4740 *speed = next_speed;
4742 if (next_width < *width)
4743 *width = next_width;
4745 dev = dev->bus->self;
4750 EXPORT_SYMBOL(pcie_get_minimum_link);
4753 * pci_select_bars - Make BAR mask from the type of resource
4754 * @dev: the PCI device for which BAR mask is made
4755 * @flags: resource type mask to be selected
4757 * This helper routine makes bar mask from the type of resource.
4759 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4762 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4763 if (pci_resource_flags(dev, i) & flags)
4767 EXPORT_SYMBOL(pci_select_bars);
4770 * pci_resource_bar - get position of the BAR associated with a resource
4771 * @dev: the PCI device
4772 * @resno: the resource number
4773 * @type: the BAR type to be filled in
4775 * Returns BAR position in config space, or 0 if the BAR is invalid.
4777 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
4781 if (resno < PCI_ROM_RESOURCE) {
4782 *type = pci_bar_unknown;
4783 return PCI_BASE_ADDRESS_0 + 4 * resno;
4784 } else if (resno == PCI_ROM_RESOURCE) {
4785 *type = pci_bar_mem32;
4786 return dev->rom_base_reg;
4787 } else if (resno < PCI_BRIDGE_RESOURCES) {
4788 /* device specific resource */
4789 *type = pci_bar_unknown;
4790 reg = pci_iov_resource_bar(dev, resno);
4795 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
4799 /* Some architectures require additional programming to enable VGA */
4800 static arch_set_vga_state_t arch_set_vga_state;
4802 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4804 arch_set_vga_state = func; /* NULL disables */
4807 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
4808 unsigned int command_bits, u32 flags)
4810 if (arch_set_vga_state)
4811 return arch_set_vga_state(dev, decode, command_bits,
4817 * pci_set_vga_state - set VGA decode state on device and parents if requested
4818 * @dev: the PCI device
4819 * @decode: true = enable decoding, false = disable decoding
4820 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4821 * @flags: traverse ancestors and change bridges
4822 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4824 int pci_set_vga_state(struct pci_dev *dev, bool decode,
4825 unsigned int command_bits, u32 flags)
4827 struct pci_bus *bus;
4828 struct pci_dev *bridge;
4832 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4834 /* ARCH specific VGA enables */
4835 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4839 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4840 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4842 cmd |= command_bits;
4844 cmd &= ~command_bits;
4845 pci_write_config_word(dev, PCI_COMMAND, cmd);
4848 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
4855 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4858 cmd |= PCI_BRIDGE_CTL_VGA;
4860 cmd &= ~PCI_BRIDGE_CTL_VGA;
4861 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4870 * pci_add_dma_alias - Add a DMA devfn alias for a device
4871 * @dev: the PCI device for which alias is added
4872 * @devfn: alias slot and function
4874 * This helper encodes 8-bit devfn as bit number in dma_alias_mask.
4875 * It should be called early, preferably as PCI fixup header quirk.
4877 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
4879 if (!dev->dma_alias_mask)
4880 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
4881 sizeof(long), GFP_KERNEL);
4882 if (!dev->dma_alias_mask) {
4883 dev_warn(&dev->dev, "Unable to allocate DMA alias mask\n");
4887 set_bit(devfn, dev->dma_alias_mask);
4888 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n",
4889 PCI_SLOT(devfn), PCI_FUNC(devfn));
4892 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
4894 return (dev1->dma_alias_mask &&
4895 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
4896 (dev2->dma_alias_mask &&
4897 test_bit(dev1->devfn, dev2->dma_alias_mask));
4900 bool pci_device_is_present(struct pci_dev *pdev)
4904 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
4906 EXPORT_SYMBOL_GPL(pci_device_is_present);
4908 void pci_ignore_hotplug(struct pci_dev *dev)
4910 struct pci_dev *bridge = dev->bus->self;
4912 dev->ignore_hotplug = 1;
4913 /* Propagate the "ignore hotplug" setting to the parent bridge. */
4915 bridge->ignore_hotplug = 1;
4917 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
4919 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4920 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
4921 static DEFINE_SPINLOCK(resource_alignment_lock);
4924 * pci_specified_resource_alignment - get resource alignment specified by user.
4925 * @dev: the PCI device to get
4927 * RETURNS: Resource alignment if it is specified.
4928 * Zero if it is not specified.
4930 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
4932 int seg, bus, slot, func, align_order, count;
4933 resource_size_t align = 0;
4936 spin_lock(&resource_alignment_lock);
4937 p = resource_alignment_param;
4940 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
4946 if (sscanf(p, "%x:%x:%x.%x%n",
4947 &seg, &bus, &slot, &func, &count) != 4) {
4949 if (sscanf(p, "%x:%x.%x%n",
4950 &bus, &slot, &func, &count) != 3) {
4951 /* Invalid format */
4952 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
4958 if (seg == pci_domain_nr(dev->bus) &&
4959 bus == dev->bus->number &&
4960 slot == PCI_SLOT(dev->devfn) &&
4961 func == PCI_FUNC(dev->devfn)) {
4962 if (align_order == -1)
4965 align = 1 << align_order;
4969 if (*p != ';' && *p != ',') {
4970 /* End of param or invalid format */
4975 spin_unlock(&resource_alignment_lock);
4980 * This function disables memory decoding and releases memory resources
4981 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
4982 * It also rounds up size to specified alignment.
4983 * Later on, the kernel will assign page-aligned memory resource back
4986 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
4990 resource_size_t align, size;
4993 /* check if specified PCI is target device to reassign */
4994 align = pci_specified_resource_alignment(dev);
4998 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
4999 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
5001 "Can't reassign resources to host bridge.\n");
5006 "Disabling memory decoding and releasing memory resources.\n");
5007 pci_read_config_word(dev, PCI_COMMAND, &command);
5008 command &= ~PCI_COMMAND_MEMORY;
5009 pci_write_config_word(dev, PCI_COMMAND, command);
5011 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
5012 r = &dev->resource[i];
5013 if (!(r->flags & IORESOURCE_MEM))
5015 size = resource_size(r);
5019 "Rounding up size of resource #%d to %#llx.\n",
5020 i, (unsigned long long)size);
5022 r->flags |= IORESOURCE_UNSET;
5026 /* Need to disable bridge's resource window,
5027 * to enable the kernel to reassign new resource
5030 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
5031 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
5032 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
5033 r = &dev->resource[i];
5034 if (!(r->flags & IORESOURCE_MEM))
5036 r->flags |= IORESOURCE_UNSET;
5037 r->end = resource_size(r) - 1;
5040 pci_disable_bridge_window(dev);
5044 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
5046 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
5047 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
5048 spin_lock(&resource_alignment_lock);
5049 strncpy(resource_alignment_param, buf, count);
5050 resource_alignment_param[count] = '\0';
5051 spin_unlock(&resource_alignment_lock);
5055 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
5058 spin_lock(&resource_alignment_lock);
5059 count = snprintf(buf, size, "%s", resource_alignment_param);
5060 spin_unlock(&resource_alignment_lock);
5064 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
5066 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
5069 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
5070 const char *buf, size_t count)
5072 return pci_set_resource_alignment_param(buf, count);
5075 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
5076 pci_resource_alignment_store);
5078 static int __init pci_resource_alignment_sysfs_init(void)
5080 return bus_create_file(&pci_bus_type,
5081 &bus_attr_resource_alignment);
5083 late_initcall(pci_resource_alignment_sysfs_init);
5085 static void pci_no_domains(void)
5087 #ifdef CONFIG_PCI_DOMAINS
5088 pci_domains_supported = 0;
5092 #ifdef CONFIG_PCI_DOMAINS
5093 static atomic_t __domain_nr = ATOMIC_INIT(-1);
5095 int pci_get_new_domain_nr(void)
5097 return atomic_inc_return(&__domain_nr);
5100 #ifdef CONFIG_PCI_DOMAINS_GENERIC
5101 void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent)
5103 static int use_dt_domains = -1;
5107 domain = of_get_pci_domain_nr(parent->of_node);
5109 * Check DT domain and use_dt_domains values.
5111 * If DT domain property is valid (domain >= 0) and
5112 * use_dt_domains != 0, the DT assignment is valid since this means
5113 * we have not previously allocated a domain number by using
5114 * pci_get_new_domain_nr(); we should also update use_dt_domains to
5115 * 1, to indicate that we have just assigned a domain number from
5118 * If DT domain property value is not valid (ie domain < 0), and we
5119 * have not previously assigned a domain number from DT
5120 * (use_dt_domains != 1) we should assign a domain number by
5123 * pci_get_new_domain_nr()
5125 * API and update the use_dt_domains value to keep track of method we
5126 * are using to assign domain numbers (use_dt_domains = 0).
5128 * All other combinations imply we have a platform that is trying
5129 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
5130 * which is a recipe for domain mishandling and it is prevented by
5131 * invalidating the domain value (domain = -1) and printing a
5132 * corresponding error.
5134 if (domain >= 0 && use_dt_domains) {
5136 } else if (domain < 0 && use_dt_domains != 1) {
5138 domain = pci_get_new_domain_nr();
5140 dev_err(parent, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n",
5141 parent->of_node->full_name);
5145 bus->domain_nr = domain;
5151 * pci_ext_cfg_avail - can we access extended PCI config space?
5153 * Returns 1 if we can access PCI extended config space (offsets
5154 * greater than 0xff). This is the default implementation. Architecture
5155 * implementations can override this.
5157 int __weak pci_ext_cfg_avail(void)
5162 void __weak pci_fixup_cardbus(struct pci_bus *bus)
5165 EXPORT_SYMBOL(pci_fixup_cardbus);
5167 static int __init pci_setup(char *str)
5170 char *k = strchr(str, ',');
5173 if (*str && (str = pcibios_setup(str)) && *str) {
5174 if (!strcmp(str, "nomsi")) {
5176 } else if (!strcmp(str, "noaer")) {
5178 } else if (!strncmp(str, "realloc=", 8)) {
5179 pci_realloc_get_opt(str + 8);
5180 } else if (!strncmp(str, "realloc", 7)) {
5181 pci_realloc_get_opt("on");
5182 } else if (!strcmp(str, "nodomains")) {
5184 } else if (!strncmp(str, "noari", 5)) {
5185 pcie_ari_disabled = true;
5186 } else if (!strncmp(str, "cbiosize=", 9)) {
5187 pci_cardbus_io_size = memparse(str + 9, &str);
5188 } else if (!strncmp(str, "cbmemsize=", 10)) {
5189 pci_cardbus_mem_size = memparse(str + 10, &str);
5190 } else if (!strncmp(str, "resource_alignment=", 19)) {
5191 pci_set_resource_alignment_param(str + 19,
5193 } else if (!strncmp(str, "ecrc=", 5)) {
5194 pcie_ecrc_get_policy(str + 5);
5195 } else if (!strncmp(str, "hpiosize=", 9)) {
5196 pci_hotplug_io_size = memparse(str + 9, &str);
5197 } else if (!strncmp(str, "hpmemsize=", 10)) {
5198 pci_hotplug_mem_size = memparse(str + 10, &str);
5199 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
5200 pcie_bus_config = PCIE_BUS_TUNE_OFF;
5201 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
5202 pcie_bus_config = PCIE_BUS_SAFE;
5203 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
5204 pcie_bus_config = PCIE_BUS_PERFORMANCE;
5205 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
5206 pcie_bus_config = PCIE_BUS_PEER2PEER;
5207 } else if (!strncmp(str, "pcie_scan_all", 13)) {
5208 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
5210 printk(KERN_ERR "PCI: Unknown option `%s'\n",
5218 early_param("pci", pci_setup);