include/linux/mlx4/qp.h

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX4_QP_H
  34 #define MLX4_QP_H
  35
  36 #include <linux/types.h>
  37
  38 #include <linux/mlx4/device.h>
  39
  40 #define MLX4_INVALID_LKEY       0x100
  41
  42 enum mlx4_qp_optpar {
  43         MLX4_QP_OPTPAR_ALT_ADDR_PATH            = 1 << 0,
  44         MLX4_QP_OPTPAR_RRE                      = 1 << 1,
  45         MLX4_QP_OPTPAR_RAE                      = 1 << 2,
  46         MLX4_QP_OPTPAR_RWE                      = 1 << 3,
  47         MLX4_QP_OPTPAR_PKEY_INDEX               = 1 << 4,
  48         MLX4_QP_OPTPAR_Q_KEY                    = 1 << 5,
  49         MLX4_QP_OPTPAR_RNR_TIMEOUT              = 1 << 6,
  50         MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH        = 1 << 7,
  51         MLX4_QP_OPTPAR_SRA_MAX                  = 1 << 8,
  52         MLX4_QP_OPTPAR_RRA_MAX                  = 1 << 9,
  53         MLX4_QP_OPTPAR_PM_STATE                 = 1 << 10,
  54         MLX4_QP_OPTPAR_RETRY_COUNT              = 1 << 12,
  55         MLX4_QP_OPTPAR_RNR_RETRY                = 1 << 13,
  56         MLX4_QP_OPTPAR_ACK_TIMEOUT              = 1 << 14,
  57         MLX4_QP_OPTPAR_SCHED_QUEUE              = 1 << 16,
  58         MLX4_QP_OPTPAR_COUNTER_INDEX            = 1 << 20
  59 };
  60
  61 enum mlx4_qp_state {
  62         MLX4_QP_STATE_RST                       = 0,
  63         MLX4_QP_STATE_INIT                      = 1,
  64         MLX4_QP_STATE_RTR                       = 2,
  65         MLX4_QP_STATE_RTS                       = 3,
  66         MLX4_QP_STATE_SQER                      = 4,
  67         MLX4_QP_STATE_SQD                       = 5,
  68         MLX4_QP_STATE_ERR                       = 6,
  69         MLX4_QP_STATE_SQ_DRAINING               = 7,
  70         MLX4_QP_NUM_STATE
  71 };
  72
  73 enum {
  74         MLX4_QP_ST_RC                           = 0x0,
  75         MLX4_QP_ST_UC                           = 0x1,
  76         MLX4_QP_ST_RD                           = 0x2,
  77         MLX4_QP_ST_UD                           = 0x3,
  78         MLX4_QP_ST_XRC                          = 0x6,
  79         MLX4_QP_ST_MLX                          = 0x7
  80 };
  81
  82 enum {
  83         MLX4_QP_PM_MIGRATED                     = 0x3,
  84         MLX4_QP_PM_ARMED                        = 0x0,
  85         MLX4_QP_PM_REARM                        = 0x1
  86 };
  87
  88 enum {
  89         /* params1 */
  90         MLX4_QP_BIT_SRE                         = 1 << 15,
  91         MLX4_QP_BIT_SWE                         = 1 << 14,
  92         MLX4_QP_BIT_SAE                         = 1 << 13,
  93         /* params2 */
  94         MLX4_QP_BIT_RRE                         = 1 << 15,
  95         MLX4_QP_BIT_RWE                         = 1 << 14,
  96         MLX4_QP_BIT_RAE                         = 1 << 13,
  97         MLX4_QP_BIT_RIC                         = 1 <<  4,
  98 };
  99
 100 enum {
 101         MLX4_RSS_HASH_XOR                       = 0,
 102         MLX4_RSS_HASH_TOP                       = 1,
 103
 104         MLX4_RSS_UDP_IPV6                       = 1 << 0,
 105         MLX4_RSS_UDP_IPV4                       = 1 << 1,
 106         MLX4_RSS_TCP_IPV6                       = 1 << 2,
 107         MLX4_RSS_IPV6                           = 1 << 3,
 108         MLX4_RSS_TCP_IPV4                       = 1 << 4,
 109         MLX4_RSS_IPV4                           = 1 << 5,
 110
 111         /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */
 112         MLX4_RSS_OFFSET_IN_QPC_PRI_PATH         = 0x24,
 113         /* offset of being RSS indirection QP within mlx4_qp_context.flags */
 114         MLX4_RSS_QPC_FLAG_OFFSET                = 13,
 115 };
 116
 117 struct mlx4_rss_context {
 118         __be32                  base_qpn;
 119         __be32                  default_qpn;
 120         u16                     reserved;
 121         u8                      hash_fn;
 122         u8                      flags;
 123         __be32                  rss_key[10];
 124         __be32                  base_qpn_udp;
 125 };
 126
 127 struct mlx4_qp_path {
 128         u8                      fl;
 129         u8                      vlan_control;
 130         u8                      disable_pkey_check;
 131         u8                      pkey_index;
 132         u8                      counter_index;
 133         u8                      grh_mylmc;
 134         __be16                  rlid;
 135         u8                      ackto;
 136         u8                      mgid_index;
 137         u8                      static_rate;
 138         u8                      hop_limit;
 139         __be32                  tclass_flowlabel;
 140         u8                      rgid[16];
 141         u8                      sched_queue;
 142         u8                      vlan_index;
 143         u8                      feup;
 144         u8                      fvl_rx;
 145         u8                      reserved4[2];
 146         u8                      dmac[6];
 147 };
 148
 149 enum { /* fl */
 150         MLX4_FL_CV      = 1 << 6,
 151         MLX4_FL_ETH_HIDE_CQE_VLAN       = 1 << 2
 152 };
 153 enum { /* vlan_control */
 154         MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED      = 1 << 6,
 155         MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED      = 1 << 2,
 156         MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1, /* 802.1p priority tag */
 157         MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED    = 1 << 0
 158 };
 159
 160 enum { /* feup */
 161         MLX4_FEUP_FORCE_ETH_UP          = 1 << 6, /* force Eth UP */
 162         MLX4_FSM_FORCE_ETH_SRC_MAC      = 1 << 5, /* force Source MAC */
 163         MLX4_FVL_FORCE_ETH_VLAN         = 1 << 3  /* force Eth vlan */
 164 };
 165
 166 enum { /* fvl_rx */
 167         MLX4_FVL_RX_FORCE_ETH_VLAN      = 1 << 0 /* enforce Eth rx vlan */
 168 };
 169
 170 struct mlx4_qp_context {
 171         __be32                  flags;
 172         __be32                  pd;
 173         u8                      mtu_msgmax;
 174         u8                      rq_size_stride;
 175         u8                      sq_size_stride;
 176         u8                      rlkey;
 177         __be32                  usr_page;
 178         __be32                  local_qpn;
 179         __be32                  remote_qpn;
 180         struct                  mlx4_qp_path pri_path;
 181         struct                  mlx4_qp_path alt_path;
 182         __be32                  params1;
 183         u32                     reserved1;
 184         __be32                  next_send_psn;
 185         __be32                  cqn_send;
 186         u32                     reserved2[2];
 187         __be32                  last_acked_psn;
 188         __be32                  ssn;
 189         __be32                  params2;
 190         __be32                  rnr_nextrecvpsn;
 191         __be32                  xrcd;
 192         __be32                  cqn_recv;
 193         __be64                  db_rec_addr;
 194         __be32                  qkey;
 195         __be32                  srqn;
 196         __be32                  msn;
 197         __be16                  rq_wqe_counter;
 198         __be16                  sq_wqe_counter;
 199         u32                     reserved3[2];
 200         __be32                  param3;
 201         __be32                  nummmcpeers_basemkey;
 202         u8                      log_page_size;
 203         u8                      reserved4[2];
 204         u8                      mtt_base_addr_h;
 205         __be32                  mtt_base_addr_l;
 206         u32                     reserved5[10];
 207 };
 208
 209 struct mlx4_update_qp_context {
 210         __be64                  qp_mask;
 211         __be64                  primary_addr_path_mask;
 212         __be64                  secondary_addr_path_mask;
 213         u64                     reserved1;
 214         struct mlx4_qp_context  qp_context;
 215         u64                     reserved2[58];
 216 };
 217
 218 enum {
 219         MLX4_UPD_QP_MASK_PM_STATE       = 32,
 220         MLX4_UPD_QP_MASK_VSD            = 33,
 221 };
 222
 223 enum {
 224         MLX4_UPD_QP_PATH_MASK_PKEY_INDEX                = 0 + 32,
 225         MLX4_UPD_QP_PATH_MASK_FSM                       = 1 + 32,
 226         MLX4_UPD_QP_PATH_MASK_MAC_INDEX                 = 2 + 32,
 227         MLX4_UPD_QP_PATH_MASK_FVL                       = 3 + 32,
 228         MLX4_UPD_QP_PATH_MASK_CV                        = 4 + 32,
 229         MLX4_UPD_QP_PATH_MASK_VLAN_INDEX                = 5 + 32,
 230         MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN         = 6 + 32,
 231         MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED     = 7 + 32,
 232         MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P           = 8 + 32,
 233         MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED       = 9 + 32,
 234         MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED     = 10 + 32,
 235         MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P           = 11 + 32,
 236         MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED       = 12 + 32,
 237         MLX4_UPD_QP_PATH_MASK_FEUP                      = 13 + 32,
 238         MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE               = 14 + 32,
 239         MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX          = 15 + 32,
 240         MLX4_UPD_QP_PATH_MASK_FVL_RX                    = 16 + 32,
 241 };
 242
 243 enum { /* param3 */
 244         MLX4_STRIP_VLAN = 1 << 30
 245 };
 246
 247 /* Which firmware version adds support for NEC (NoErrorCompletion) bit */
 248 #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
 249
 250 enum {
 251         MLX4_WQE_CTRL_NEC               = 1 << 29,
 252         MLX4_WQE_CTRL_FENCE             = 1 << 6,
 253         MLX4_WQE_CTRL_CQ_UPDATE         = 3 << 2,
 254         MLX4_WQE_CTRL_SOLICITED         = 1 << 1,
 255         MLX4_WQE_CTRL_IP_CSUM           = 1 << 4,
 256         MLX4_WQE_CTRL_TCP_UDP_CSUM      = 1 << 5,
 257         MLX4_WQE_CTRL_INS_VLAN          = 1 << 6,
 258         MLX4_WQE_CTRL_STRONG_ORDER      = 1 << 7,
 259         MLX4_WQE_CTRL_FORCE_LOOPBACK    = 1 << 0,
 260 };
 261
 262 struct mlx4_wqe_ctrl_seg {
 263         __be32                  owner_opcode;
 264         __be16                  vlan_tag;
 265         u8                      ins_vlan;
 266         u8                      fence_size;
 267         /*
 268          * High 24 bits are SRC remote buffer; low 8 bits are flags:
 269          * [7]   SO (strong ordering)
 270          * [5]   TCP/UDP checksum
 271          * [4]   IP checksum
 272          * [3:2] C (generate completion queue entry)
 273          * [1]   SE (solicited event)
 274          * [0]   FL (force loopback)
 275          */
 276         union {
 277                 __be32                  srcrb_flags;
 278                 __be16                  srcrb_flags16[2];
 279         };
 280         /*
 281          * imm is immediate data for send/RDMA write w/ immediate;
 282          * also invalidation key for send with invalidate; input
 283          * modifier for WQEs on CCQs.
 284          */
 285         __be32                  imm;
 286 };
 287
 288 enum {
 289         MLX4_WQE_MLX_VL15       = 1 << 17,
 290         MLX4_WQE_MLX_SLR        = 1 << 16
 291 };
 292
 293 struct mlx4_wqe_mlx_seg {
 294         u8                      owner;
 295         u8                      reserved1[2];
 296         u8                      opcode;
 297         __be16                  sched_prio;
 298         u8                      reserved2;
 299         u8                      size;
 300         /*
 301          * [17]    VL15
 302          * [16]    SLR
 303          * [15:12] static rate
 304          * [11:8]  SL
 305          * [4]     ICRC
 306          * [3:2]   C
 307          * [0]     FL (force loopback)
 308          */
 309         __be32                  flags;
 310         __be16                  rlid;
 311         u16                     reserved3;
 312 };
 313
 314 struct mlx4_wqe_datagram_seg {
 315         __be32                  av[8];
 316         __be32                  dqpn;
 317         __be32                  qkey;
 318         __be16                  vlan;
 319         u8                      mac[6];
 320 };
 321
 322 struct mlx4_wqe_lso_seg {
 323         __be32                  mss_hdr_size;
 324         __be32                  header[0];
 325 };
 326
 327 enum mlx4_wqe_bind_seg_flags2 {
 328         MLX4_WQE_BIND_ZERO_BASED = (1 << 30),
 329         MLX4_WQE_BIND_TYPE_2     = (1 << 31),
 330 };
 331
 332 struct mlx4_wqe_bind_seg {
 333         __be32                  flags1;
 334         __be32                  flags2;
 335         __be32                  new_rkey;
 336         __be32                  lkey;
 337         __be64                  addr;
 338         __be64                  length;
 339 };
 340
 341 enum {
 342         MLX4_WQE_FMR_PERM_LOCAL_READ    = 1 << 27,
 343         MLX4_WQE_FMR_PERM_LOCAL_WRITE   = 1 << 28,
 344         MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ  = 1 << 29,
 345         MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30,
 346         MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC       = 1 << 31
 347 };
 348
 349 struct mlx4_wqe_fmr_seg {
 350         __be32                  flags;
 351         __be32                  mem_key;
 352         __be64                  buf_list;
 353         __be64                  start_addr;
 354         __be64                  reg_len;
 355         __be32                  offset;
 356         __be32                  page_size;
 357         u32                     reserved[2];
 358 };
 359
 360 struct mlx4_wqe_fmr_ext_seg {
 361         u8                      flags;
 362         u8                      reserved;
 363         __be16                  app_mask;
 364         __be16                  wire_app_tag;
 365         __be16                  mem_app_tag;
 366         __be32                  wire_ref_tag_base;
 367         __be32                  mem_ref_tag_base;
 368 };
 369
 370 struct mlx4_wqe_local_inval_seg {
 371         u64                     reserved1;
 372         __be32                  mem_key;
 373         u32                     reserved2;
 374         u64                     reserved3[2];
 375 };
 376
 377 struct mlx4_wqe_raddr_seg {
 378         __be64                  raddr;
 379         __be32                  rkey;
 380         u32                     reserved;
 381 };
 382
 383 struct mlx4_wqe_atomic_seg {
 384         __be64                  swap_add;
 385         __be64                  compare;
 386 };
 387
 388 struct mlx4_wqe_masked_atomic_seg {
 389         __be64                  swap_add;
 390         __be64                  compare;
 391         __be64                  swap_add_mask;
 392         __be64                  compare_mask;
 393 };
 394
 395 struct mlx4_wqe_data_seg {
 396         __be32                  byte_count;
 397         __be32                  lkey;
 398         __be64                  addr;
 399 };
 400
 401 enum {
 402         MLX4_INLINE_ALIGN       = 64,
 403         MLX4_INLINE_SEG         = 1 << 31,
 404 };
 405
 406 struct mlx4_wqe_inline_seg {
 407         __be32                  byte_count;
 408 };
 409
 410 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 411                    enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
 412                    struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
 413                    int sqd_event, struct mlx4_qp *qp);
 414
 415 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
 416                   struct mlx4_qp_context *context);
 417
 418 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 419                      struct mlx4_qp_context *context,
 420                      struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);
 421
 422 static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
 423 {
 424         return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
 425 }
 426
 427 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
 428
 429 #endif /* MLX4_QP_H */