2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock_types.h>
40 #include <linux/semaphore.h>
41 #include <linux/slab.h>
42 #include <linux/vmalloc.h>
43 #include <linux/radix-tree.h>
45 #include <linux/mlx5/device.h>
46 #include <linux/mlx5/doorbell.h>
49 MLX5_RQ_BITMASK_VSD = 1 << 1,
53 MLX5_BOARD_ID_LEN = 64,
54 MLX5_MAX_NAME_LEN = 16,
58 /* one minute for the sake of bringup. Generally, commands must always
59 * complete and we may need to increase this timeout value
61 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
62 MLX5_CMD_WQ_MAX_NAME = 32,
68 CMD_STATUS_SUCCESS = 0,
74 MLX5_SQP_IEEE_1588 = 2,
76 MLX5_SQP_SYNC_UMR = 4,
84 MLX5_EQ_VEC_PAGES = 0,
86 MLX5_EQ_VEC_ASYNC = 2,
87 MLX5_EQ_VEC_COMP_BASE,
91 MLX5_MAX_IRQ_NAME = 32
95 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
96 MLX5_ATOMIC_MODE_CX = 2 << 16,
97 MLX5_ATOMIC_MODE_8B = 3 << 16,
98 MLX5_ATOMIC_MODE_16B = 4 << 16,
99 MLX5_ATOMIC_MODE_32B = 5 << 16,
100 MLX5_ATOMIC_MODE_64B = 6 << 16,
101 MLX5_ATOMIC_MODE_128B = 7 << 16,
102 MLX5_ATOMIC_MODE_256B = 8 << 16,
106 MLX5_REG_QETCR = 0x4005,
107 MLX5_REG_QTCT = 0x400a,
108 MLX5_REG_PCAP = 0x5001,
109 MLX5_REG_PMTU = 0x5003,
110 MLX5_REG_PTYS = 0x5004,
111 MLX5_REG_PAOS = 0x5006,
112 MLX5_REG_PFCC = 0x5007,
113 MLX5_REG_PPCNT = 0x5008,
114 MLX5_REG_PMAOS = 0x5012,
115 MLX5_REG_PUDE = 0x5009,
116 MLX5_REG_PMPE = 0x5010,
117 MLX5_REG_PELC = 0x500e,
118 MLX5_REG_PVLC = 0x500f,
119 MLX5_REG_PCMR = 0x5041,
120 MLX5_REG_PMLP = 0x5002,
121 MLX5_REG_NODE_DESC = 0x6001,
122 MLX5_REG_HOST_ENDIANNESS = 0x7004,
123 MLX5_REG_MCIA = 0x9014,
124 MLX5_REG_MLCR = 0x902b,
128 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
129 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
132 enum mlx5_page_fault_resume_flags {
133 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
134 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
135 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
136 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
145 struct mlx5_field_desc {
150 struct mlx5_rsc_debug {
151 struct mlx5_core_dev *dev;
153 enum dbg_rsc_type type;
155 struct mlx5_field_desc fields[0];
158 enum mlx5_dev_event {
159 MLX5_DEV_EVENT_SYS_ERROR,
160 MLX5_DEV_EVENT_PORT_UP,
161 MLX5_DEV_EVENT_PORT_DOWN,
162 MLX5_DEV_EVENT_PORT_INITIALIZED,
163 MLX5_DEV_EVENT_LID_CHANGE,
164 MLX5_DEV_EVENT_PKEY_CHANGE,
165 MLX5_DEV_EVENT_GUID_CHANGE,
166 MLX5_DEV_EVENT_CLIENT_REREG,
169 enum mlx5_port_status {
174 struct mlx5_uuar_info {
175 struct mlx5_uar *uars;
177 int num_low_latency_uuars;
178 unsigned long *bitmap;
183 * protect uuar allocation data structs
191 void __iomem *regreg;
193 struct mlx5_uar *uar;
194 unsigned long offset;
196 /* protect blue flame buffer selection when needed
200 /* serialize 64 bit writes when done as two 32 bit accesses
206 struct mlx5_cmd_first {
210 struct mlx5_cmd_msg {
211 struct list_head list;
212 struct cache_ent *cache;
214 struct mlx5_cmd_first first;
215 struct mlx5_cmd_mailbox *next;
218 struct mlx5_cmd_debug {
219 struct dentry *dbg_root;
220 struct dentry *dbg_in;
221 struct dentry *dbg_out;
222 struct dentry *dbg_outlen;
223 struct dentry *dbg_status;
224 struct dentry *dbg_run;
233 /* protect block chain allocations
236 struct list_head head;
239 struct cmd_msg_cache {
240 struct cache_ent large;
241 struct cache_ent med;
245 struct mlx5_cmd_stats {
250 struct dentry *count;
251 /* protect command average calculations */
257 dma_addr_t alloc_dma;
268 /* protect command queue allocations
270 spinlock_t alloc_lock;
272 /* protect token allocations
274 spinlock_t token_lock;
276 unsigned long bitmask;
277 char wq_name[MLX5_CMD_WQ_MAX_NAME];
278 struct workqueue_struct *wq;
279 struct semaphore sem;
280 struct semaphore pages_sem;
282 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
283 struct pci_pool *pool;
284 struct mlx5_cmd_debug dbg;
285 struct cmd_msg_cache cache;
286 int checksum_disabled;
287 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
290 struct mlx5_port_caps {
296 struct mlx5_cmd_mailbox {
299 struct mlx5_cmd_mailbox *next;
302 struct mlx5_buf_list {
308 struct mlx5_buf_list direct;
315 struct mlx5_core_dev *dev;
316 __be32 __iomem *doorbell;
324 struct list_head list;
326 struct mlx5_rsc_debug *dbg;
329 struct mlx5_core_psv {
341 struct mlx5_core_sig_ctx {
342 struct mlx5_core_psv psv_memory;
343 struct mlx5_core_psv psv_wire;
344 struct ib_sig_err err_item;
345 bool sig_status_checked;
350 struct mlx5_core_mkey {
358 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
359 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
360 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
365 struct mlx5_core_rsc_common {
366 enum mlx5_res_type res;
368 struct completion free;
371 struct mlx5_core_srq {
372 struct mlx5_core_rsc_common common; /* must be first */
376 int max_avail_gather;
378 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
381 struct completion free;
384 struct mlx5_eq_table {
385 void __iomem *update_ci;
386 void __iomem *update_arm_ci;
387 struct list_head comp_eqs_list;
388 struct mlx5_eq pages_eq;
389 struct mlx5_eq async_eq;
390 struct mlx5_eq cmd_eq;
391 int num_comp_vectors;
399 struct list_head bf_list;
400 unsigned free_bf_bmap;
401 void __iomem *bf_map;
406 struct mlx5_core_health {
407 struct health_buffer __iomem *health;
408 __be32 __iomem *health_counter;
409 struct timer_list timer;
413 struct workqueue_struct *wq;
414 struct work_struct work;
417 struct mlx5_cq_table {
418 /* protect radix tree
421 struct radix_tree_root tree;
424 struct mlx5_qp_table {
425 /* protect radix tree
428 struct radix_tree_root tree;
431 struct mlx5_srq_table {
432 /* protect radix tree
435 struct radix_tree_root tree;
438 struct mlx5_mkey_table {
439 /* protect radix tree
442 struct radix_tree_root tree;
445 struct mlx5_vf_context {
449 struct mlx5_core_sriov {
450 struct mlx5_vf_context *vfs_ctx;
455 struct mlx5_irq_info {
457 char name[MLX5_MAX_IRQ_NAME];
463 char name[MLX5_MAX_NAME_LEN];
464 struct mlx5_eq_table eq_table;
465 struct msix_entry *msix_arr;
466 struct mlx5_irq_info *irq_info;
467 struct mlx5_uuar_info uuari;
468 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
471 struct workqueue_struct *pg_wq;
472 struct rb_root page_root;
475 struct list_head free_list;
478 struct mlx5_core_health health;
480 struct mlx5_srq_table srq_table;
482 /* start: qp staff */
483 struct mlx5_qp_table qp_table;
484 struct dentry *qp_debugfs;
485 struct dentry *eq_debugfs;
486 struct dentry *cq_debugfs;
487 struct dentry *cmdif_debugfs;
490 /* start: cq staff */
491 struct mlx5_cq_table cq_table;
494 /* start: mkey staff */
495 struct mlx5_mkey_table mkey_table;
496 /* end: mkey staff */
498 /* start: alloc staff */
499 /* protect buffer alocation according to numa node */
500 struct mutex alloc_mutex;
503 struct mutex pgdir_mutex;
504 struct list_head pgdir_list;
505 /* end: alloc staff */
506 struct dentry *dbg_root;
508 /* protect mkey key part */
509 spinlock_t mkey_lock;
512 struct list_head dev_list;
513 struct list_head ctx_list;
516 struct mlx5_eswitch *eswitch;
517 struct mlx5_core_sriov sriov;
518 unsigned long pci_dev_data;
519 struct mlx5_flow_root_namespace *root_ns;
520 struct mlx5_flow_root_namespace *fdb_root_ns;
523 enum mlx5_device_state {
524 MLX5_DEVICE_STATE_UP,
525 MLX5_DEVICE_STATE_INTERNAL_ERROR,
528 enum mlx5_interface_state {
529 MLX5_INTERFACE_STATE_DOWN = BIT(0),
530 MLX5_INTERFACE_STATE_UP = BIT(1),
531 MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2),
534 enum mlx5_pci_status {
535 MLX5_PCI_STATUS_DISABLED,
536 MLX5_PCI_STATUS_ENABLED,
539 struct mlx5_core_dev {
540 struct pci_dev *pdev;
542 struct mutex pci_status_mutex;
543 enum mlx5_pci_status pci_status;
545 char board_id[MLX5_BOARD_ID_LEN];
547 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
548 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
549 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
550 phys_addr_t iseg_base;
551 struct mlx5_init_seg __iomem *iseg;
552 enum mlx5_device_state state;
553 /* sync interface state */
554 struct mutex intf_state_mutex;
555 unsigned long intf_state;
556 void (*event) (struct mlx5_core_dev *dev,
557 enum mlx5_dev_event event,
558 unsigned long param);
559 struct mlx5_priv priv;
560 struct mlx5_profile *profile;
563 #ifdef CONFIG_RFS_ACCEL
564 struct cpu_rmap *rmap;
571 struct mlx5_db_pgdir *pgdir;
572 struct mlx5_ib_user_db_page *user_page;
579 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
583 MLX5_COMP_EQ_SIZE = 1024,
587 MLX5_PTYS_IB = 1 << 0,
588 MLX5_PTYS_EN = 1 << 2,
591 struct mlx5_db_pgdir {
592 struct list_head list;
593 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
598 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
600 struct mlx5_cmd_work_ent {
601 struct mlx5_cmd_msg *in;
602 struct mlx5_cmd_msg *out;
605 mlx5_cmd_cbk_t callback;
608 struct completion done;
609 struct mlx5_cmd *cmd;
610 struct work_struct work;
611 struct mlx5_cmd_layout *lay;
626 enum port_state_policy {
627 MLX5_POLICY_DOWN = 0,
629 MLX5_POLICY_FOLLOW = 2,
630 MLX5_POLICY_INVALID = 0xffffffff
633 enum phy_port_state {
637 struct mlx5_hca_vport_context {
642 enum port_state_policy policy;
643 enum phy_port_state phys_state;
644 enum ib_port_state vport_state;
645 u8 port_physical_state;
654 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
659 u16 qkey_violation_counter;
660 u16 pkey_violation_counter;
664 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
666 return buf->direct.buf + offset;
669 extern struct workqueue_struct *mlx5_core_wq;
671 #define STRUCT_FIELD(header, field) \
672 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
673 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
675 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
677 return pci_get_drvdata(pdev);
680 extern struct dentry *mlx5_debugfs_root;
682 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
684 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
687 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
689 return ioread32be(&dev->iseg->fw_rev) >> 16;
692 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
694 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
697 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
699 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
702 static inline void *mlx5_vzalloc(unsigned long size)
706 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
712 static inline u32 mlx5_base_mkey(const u32 key)
714 return key & 0xffffff00u;
717 int mlx5_cmd_init(struct mlx5_core_dev *dev);
718 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
719 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
720 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
721 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
722 int mlx5_cmd_status_to_err_v2(void *ptr);
723 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
724 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
726 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
727 void *out, int out_size, mlx5_cmd_cbk_t callback,
729 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
730 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
731 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
732 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
733 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar,
735 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
736 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
737 int mlx5_health_init(struct mlx5_core_dev *dev);
738 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
739 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
740 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
741 struct mlx5_buf *buf, int node);
742 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
743 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
744 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
745 gfp_t flags, int npages);
746 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
747 struct mlx5_cmd_mailbox *head);
748 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
749 struct mlx5_create_srq_mbox_in *in, int inlen,
751 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
752 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
753 struct mlx5_query_srq_mbox_out *out);
754 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
755 u16 lwm, int is_srq);
756 void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
757 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
758 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
759 struct mlx5_core_mkey *mkey,
760 struct mlx5_create_mkey_mbox_in *in, int inlen,
761 mlx5_cmd_cbk_t callback, void *context,
762 struct mlx5_create_mkey_mbox_out *out);
763 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
764 struct mlx5_core_mkey *mkey);
765 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
766 struct mlx5_query_mkey_mbox_out *out, int outlen);
767 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
769 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
770 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
771 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
773 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
774 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
775 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
776 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
777 int mlx5_sriov_init(struct mlx5_core_dev *dev);
778 int mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
779 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
781 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
782 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
783 void mlx5_register_debugfs(void);
784 void mlx5_unregister_debugfs(void);
785 int mlx5_eq_init(struct mlx5_core_dev *dev);
786 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
787 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
788 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
789 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
790 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
791 void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
793 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
794 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
795 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec);
796 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
797 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
798 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
799 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
800 int mlx5_start_eqs(struct mlx5_core_dev *dev);
801 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
802 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
804 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
805 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
807 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
808 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
809 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
810 int size_in, void *data_out, int size_out,
811 u16 reg_num, int arg, int write);
813 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
814 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
815 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
816 struct mlx5_query_eq_mbox_out *out, int outlen);
817 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
818 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
819 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
820 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
821 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
822 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
824 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
826 const char *mlx5_command_str(int command);
827 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
828 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
829 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
830 int npsvs, u32 *sig_index);
831 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
832 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
833 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
834 struct mlx5_odp_caps *odp_caps);
835 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
836 u8 port_num, void *out, size_t sz);
838 static inline int fw_initializing(struct mlx5_core_dev *dev)
840 return ioread32be(&dev->iseg->initializing) >> 31;
843 static inline u32 mlx5_mkey_to_idx(u32 mkey)
848 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
850 return mkey_idx << 8;
853 static inline u8 mlx5_mkey_variant(u32 mkey)
859 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
860 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
864 MAX_MR_CACHE_ENTRIES = 16,
868 MLX5_INTERFACE_PROTOCOL_IB = 0,
869 MLX5_INTERFACE_PROTOCOL_ETH = 1,
872 struct mlx5_interface {
873 void * (*add)(struct mlx5_core_dev *dev);
874 void (*remove)(struct mlx5_core_dev *dev, void *context);
875 void (*event)(struct mlx5_core_dev *dev, void *context,
876 enum mlx5_dev_event event, unsigned long param);
877 void * (*get_dev)(void *context);
879 struct list_head list;
882 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
883 int mlx5_register_interface(struct mlx5_interface *intf);
884 void mlx5_unregister_interface(struct mlx5_interface *intf);
885 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
887 struct mlx5_profile {
893 } mr_cache[MAX_MR_CACHE_ENTRIES];
897 MLX5_PCI_DEV_IS_VF = 1 << 0,
900 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
902 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
905 static inline int mlx5_get_gid_table_len(u16 param)
908 pr_warn("gid table length is zero\n");
912 return 8 * (1 << param);
916 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
919 #endif /* MLX5_DRIVER_H */