include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  71         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  72 };
  73
  74 enum {
  75         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  76         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  77         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  78         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  79         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  80         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  81         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  82         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  83         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  84         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  85         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  86         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  87         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  88         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  89         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  90         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  91         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  92         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  93         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  94         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  95         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  96         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  97         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  98         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
  99         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 100         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 101         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 102         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 103         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 104         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 105         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 106         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 107         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 108         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 109         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 110         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 111         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 112         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 113         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 114         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 115         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 116         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 117         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 118         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 119         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 120         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 121         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 122         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 123         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 124         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 125         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 126         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 127         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 128         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 129         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 130         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 131         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 132         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 133         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 134         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 135         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 136         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 137         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 138         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 139         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 140         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 141         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 142         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 143         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 144         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 145         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 146         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 147         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 148         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 149         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 150         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 151         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 152         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 153         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 154         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 155         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 156         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 157         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 158         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 159         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 160         MLX5_CMD_OP_NOP                           = 0x80d,
 161         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 162         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 163         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 164         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 165         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 166         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 167         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 168         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 169         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 170         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 171         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 172         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 173         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 174         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 175         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 176         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 177         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 178         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 179         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 180         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 181         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 182         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 183         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 184         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 185         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 186         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 187         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 188         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 189         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 190         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 191         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 192         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 193         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 194         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 195         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 196         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 197         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 198         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 199         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 200         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 201         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 202         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 203         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 204         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 205         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 206         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 207         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 208         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 209         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 210         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 211         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 212         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 213         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 214         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 215         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 216         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 217         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 218         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 219         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 220         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 221         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 222         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 223         MLX5_CMD_OP_MAX
 224 };
 225
 226 struct mlx5_ifc_flow_table_fields_supported_bits {
 227         u8         outer_dmac[0x1];
 228         u8         outer_smac[0x1];
 229         u8         outer_ether_type[0x1];
 230         u8         reserved_at_3[0x1];
 231         u8         outer_first_prio[0x1];
 232         u8         outer_first_cfi[0x1];
 233         u8         outer_first_vid[0x1];
 234         u8         reserved_at_7[0x1];
 235         u8         outer_second_prio[0x1];
 236         u8         outer_second_cfi[0x1];
 237         u8         outer_second_vid[0x1];
 238         u8         reserved_at_b[0x1];
 239         u8         outer_sip[0x1];
 240         u8         outer_dip[0x1];
 241         u8         outer_frag[0x1];
 242         u8         outer_ip_protocol[0x1];
 243         u8         outer_ip_ecn[0x1];
 244         u8         outer_ip_dscp[0x1];
 245         u8         outer_udp_sport[0x1];
 246         u8         outer_udp_dport[0x1];
 247         u8         outer_tcp_sport[0x1];
 248         u8         outer_tcp_dport[0x1];
 249         u8         outer_tcp_flags[0x1];
 250         u8         outer_gre_protocol[0x1];
 251         u8         outer_gre_key[0x1];
 252         u8         outer_vxlan_vni[0x1];
 253         u8         reserved_at_1a[0x5];
 254         u8         source_eswitch_port[0x1];
 255
 256         u8         inner_dmac[0x1];
 257         u8         inner_smac[0x1];
 258         u8         inner_ether_type[0x1];
 259         u8         reserved_at_23[0x1];
 260         u8         inner_first_prio[0x1];
 261         u8         inner_first_cfi[0x1];
 262         u8         inner_first_vid[0x1];
 263         u8         reserved_at_27[0x1];
 264         u8         inner_second_prio[0x1];
 265         u8         inner_second_cfi[0x1];
 266         u8         inner_second_vid[0x1];
 267         u8         reserved_at_2b[0x1];
 268         u8         inner_sip[0x1];
 269         u8         inner_dip[0x1];
 270         u8         inner_frag[0x1];
 271         u8         inner_ip_protocol[0x1];
 272         u8         inner_ip_ecn[0x1];
 273         u8         inner_ip_dscp[0x1];
 274         u8         inner_udp_sport[0x1];
 275         u8         inner_udp_dport[0x1];
 276         u8         inner_tcp_sport[0x1];
 277         u8         inner_tcp_dport[0x1];
 278         u8         inner_tcp_flags[0x1];
 279         u8         reserved_at_37[0x9];
 280
 281         u8         reserved_at_40[0x40];
 282 };
 283
 284 struct mlx5_ifc_flow_table_prop_layout_bits {
 285         u8         ft_support[0x1];
 286         u8         reserved_at_1[0x1];
 287         u8         flow_counter[0x1];
 288         u8         flow_modify_en[0x1];
 289         u8         modify_root[0x1];
 290         u8         identified_miss_table_mode[0x1];
 291         u8         flow_table_modify[0x1];
 292         u8         encap[0x1];
 293         u8         decap[0x1];
 294         u8         reserved_at_9[0x17];
 295
 296         u8         reserved_at_20[0x2];
 297         u8         log_max_ft_size[0x6];
 298         u8         reserved_at_28[0x10];
 299         u8         max_ft_level[0x8];
 300
 301         u8         reserved_at_40[0x20];
 302
 303         u8         reserved_at_60[0x18];
 304         u8         log_max_ft_num[0x8];
 305
 306         u8         reserved_at_80[0x18];
 307         u8         log_max_destination[0x8];
 308
 309         u8         reserved_at_a0[0x18];
 310         u8         log_max_flow[0x8];
 311
 312         u8         reserved_at_c0[0x40];
 313
 314         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 315
 316         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 317 };
 318
 319 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 320         u8         send[0x1];
 321         u8         receive[0x1];
 322         u8         write[0x1];
 323         u8         read[0x1];
 324         u8         reserved_at_4[0x1];
 325         u8         srq_receive[0x1];
 326         u8         reserved_at_6[0x1a];
 327 };
 328
 329 struct mlx5_ifc_ipv4_layout_bits {
 330         u8         reserved_at_0[0x60];
 331
 332         u8         ipv4[0x20];
 333 };
 334
 335 struct mlx5_ifc_ipv6_layout_bits {
 336         u8         ipv6[16][0x8];
 337 };
 338
 339 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 340         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 341         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 342         u8         reserved_at_0[0x80];
 343 };
 344
 345 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 346         u8         smac_47_16[0x20];
 347
 348         u8         smac_15_0[0x10];
 349         u8         ethertype[0x10];
 350
 351         u8         dmac_47_16[0x20];
 352
 353         u8         dmac_15_0[0x10];
 354         u8         first_prio[0x3];
 355         u8         first_cfi[0x1];
 356         u8         first_vid[0xc];
 357
 358         u8         ip_protocol[0x8];
 359         u8         ip_dscp[0x6];
 360         u8         ip_ecn[0x2];
 361         u8         vlan_tag[0x1];
 362         u8         reserved_at_91[0x1];
 363         u8         frag[0x1];
 364         u8         reserved_at_93[0x4];
 365         u8         tcp_flags[0x9];
 366
 367         u8         tcp_sport[0x10];
 368         u8         tcp_dport[0x10];
 369
 370         u8         reserved_at_c0[0x20];
 371
 372         u8         udp_sport[0x10];
 373         u8         udp_dport[0x10];
 374
 375         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 376
 377         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 378 };
 379
 380 struct mlx5_ifc_fte_match_set_misc_bits {
 381         u8         reserved_at_0[0x8];
 382         u8         source_sqn[0x18];
 383
 384         u8         reserved_at_20[0x10];
 385         u8         source_port[0x10];
 386
 387         u8         outer_second_prio[0x3];
 388         u8         outer_second_cfi[0x1];
 389         u8         outer_second_vid[0xc];
 390         u8         inner_second_prio[0x3];
 391         u8         inner_second_cfi[0x1];
 392         u8         inner_second_vid[0xc];
 393
 394         u8         outer_second_vlan_tag[0x1];
 395         u8         inner_second_vlan_tag[0x1];
 396         u8         reserved_at_62[0xe];
 397         u8         gre_protocol[0x10];
 398
 399         u8         gre_key_h[0x18];
 400         u8         gre_key_l[0x8];
 401
 402         u8         vxlan_vni[0x18];
 403         u8         reserved_at_b8[0x8];
 404
 405         u8         reserved_at_c0[0x20];
 406
 407         u8         reserved_at_e0[0xc];
 408         u8         outer_ipv6_flow_label[0x14];
 409
 410         u8         reserved_at_100[0xc];
 411         u8         inner_ipv6_flow_label[0x14];
 412
 413         u8         reserved_at_120[0xe0];
 414 };
 415
 416 struct mlx5_ifc_cmd_pas_bits {
 417         u8         pa_h[0x20];
 418
 419         u8         pa_l[0x14];
 420         u8         reserved_at_34[0xc];
 421 };
 422
 423 struct mlx5_ifc_uint64_bits {
 424         u8         hi[0x20];
 425
 426         u8         lo[0x20];
 427 };
 428
 429 enum {
 430         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 431         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 432         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 433         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 434         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 435         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 436         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 437         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 438         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 439         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 440 };
 441
 442 struct mlx5_ifc_ads_bits {
 443         u8         fl[0x1];
 444         u8         free_ar[0x1];
 445         u8         reserved_at_2[0xe];
 446         u8         pkey_index[0x10];
 447
 448         u8         reserved_at_20[0x8];
 449         u8         grh[0x1];
 450         u8         mlid[0x7];
 451         u8         rlid[0x10];
 452
 453         u8         ack_timeout[0x5];
 454         u8         reserved_at_45[0x3];
 455         u8         src_addr_index[0x8];
 456         u8         reserved_at_50[0x4];
 457         u8         stat_rate[0x4];
 458         u8         hop_limit[0x8];
 459
 460         u8         reserved_at_60[0x4];
 461         u8         tclass[0x8];
 462         u8         flow_label[0x14];
 463
 464         u8         rgid_rip[16][0x8];
 465
 466         u8         reserved_at_100[0x4];
 467         u8         f_dscp[0x1];
 468         u8         f_ecn[0x1];
 469         u8         reserved_at_106[0x1];
 470         u8         f_eth_prio[0x1];
 471         u8         ecn[0x2];
 472         u8         dscp[0x6];
 473         u8         udp_sport[0x10];
 474
 475         u8         dei_cfi[0x1];
 476         u8         eth_prio[0x3];
 477         u8         sl[0x4];
 478         u8         port[0x8];
 479         u8         rmac_47_32[0x10];
 480
 481         u8         rmac_31_0[0x20];
 482 };
 483
 484 struct mlx5_ifc_flow_table_nic_cap_bits {
 485         u8         nic_rx_multi_path_tirs[0x1];
 486         u8         reserved_at_1[0x1ff];
 487
 488         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 489
 490         u8         reserved_at_400[0x200];
 491
 492         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 493
 494         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 495
 496         u8         reserved_at_a00[0x200];
 497
 498         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 499
 500         u8         reserved_at_e00[0x7200];
 501 };
 502
 503 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 504         u8     reserved_at_0[0x200];
 505
 506         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 507
 508         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 509
 510         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 511
 512         u8      reserved_at_800[0x7800];
 513 };
 514
 515 struct mlx5_ifc_e_switch_cap_bits {
 516         u8         vport_svlan_strip[0x1];
 517         u8         vport_cvlan_strip[0x1];
 518         u8         vport_svlan_insert[0x1];
 519         u8         vport_cvlan_insert_if_not_exist[0x1];
 520         u8         vport_cvlan_insert_overwrite[0x1];
 521         u8         reserved_at_5[0x19];
 522         u8         nic_vport_node_guid_modify[0x1];
 523         u8         nic_vport_port_guid_modify[0x1];
 524
 525         u8         vxlan_encap_decap[0x1];
 526         u8         nvgre_encap_decap[0x1];
 527         u8         reserved_at_22[0x9];
 528         u8         log_max_encap_headers[0x5];
 529         u8         reserved_2b[0x6];
 530         u8         max_encap_header_size[0xa];
 531
 532         u8         reserved_40[0x7c0];
 533
 534 };
 535
 536 struct mlx5_ifc_qos_cap_bits {
 537         u8         packet_pacing[0x1];
 538         u8         reserved_0[0x1f];
 539         u8         reserved_1[0x20];
 540         u8         packet_pacing_max_rate[0x20];
 541         u8         packet_pacing_min_rate[0x20];
 542         u8         reserved_2[0x10];
 543         u8         packet_pacing_rate_table_size[0x10];
 544         u8         reserved_3[0x760];
 545 };
 546
 547 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 548         u8         csum_cap[0x1];
 549         u8         vlan_cap[0x1];
 550         u8         lro_cap[0x1];
 551         u8         lro_psh_flag[0x1];
 552         u8         lro_time_stamp[0x1];
 553         u8         reserved_at_5[0x3];
 554         u8         self_lb_en_modifiable[0x1];
 555         u8         reserved_at_9[0x2];
 556         u8         max_lso_cap[0x5];
 557         u8         reserved_at_10[0x2];
 558         u8         wqe_inline_mode[0x2];
 559         u8         rss_ind_tbl_cap[0x4];
 560         u8         reg_umr_sq[0x1];
 561         u8         scatter_fcs[0x1];
 562         u8         reserved_at_1a[0x1];
 563         u8         tunnel_lso_const_out_ip_id[0x1];
 564         u8         reserved_at_1c[0x2];
 565         u8         tunnel_statless_gre[0x1];
 566         u8         tunnel_stateless_vxlan[0x1];
 567
 568         u8         reserved_at_20[0x20];
 569
 570         u8         reserved_at_40[0x10];
 571         u8         lro_min_mss_size[0x10];
 572
 573         u8         reserved_at_60[0x120];
 574
 575         u8         lro_timer_supported_periods[4][0x20];
 576
 577         u8         reserved_at_200[0x600];
 578 };
 579
 580 struct mlx5_ifc_roce_cap_bits {
 581         u8         roce_apm[0x1];
 582         u8         reserved_at_1[0x1f];
 583
 584         u8         reserved_at_20[0x60];
 585
 586         u8         reserved_at_80[0xc];
 587         u8         l3_type[0x4];
 588         u8         reserved_at_90[0x8];
 589         u8         roce_version[0x8];
 590
 591         u8         reserved_at_a0[0x10];
 592         u8         r_roce_dest_udp_port[0x10];
 593
 594         u8         r_roce_max_src_udp_port[0x10];
 595         u8         r_roce_min_src_udp_port[0x10];
 596
 597         u8         reserved_at_e0[0x10];
 598         u8         roce_address_table_size[0x10];
 599
 600         u8         reserved_at_100[0x700];
 601 };
 602
 603 enum {
 604         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 605         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 606         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 607         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 608         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 609         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 610         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 611         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 612         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 613 };
 614
 615 enum {
 616         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 617         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 618         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 619         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 620         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 621         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 622         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 623         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 624         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 625 };
 626
 627 struct mlx5_ifc_atomic_caps_bits {
 628         u8         reserved_at_0[0x40];
 629
 630         u8         atomic_req_8B_endianess_mode[0x2];
 631         u8         reserved_at_42[0x4];
 632         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 633
 634         u8         reserved_at_47[0x19];
 635
 636         u8         reserved_at_60[0x20];
 637
 638         u8         reserved_at_80[0x10];
 639         u8         atomic_operations[0x10];
 640
 641         u8         reserved_at_a0[0x10];
 642         u8         atomic_size_qp[0x10];
 643
 644         u8         reserved_at_c0[0x10];
 645         u8         atomic_size_dc[0x10];
 646
 647         u8         reserved_at_e0[0x720];
 648 };
 649
 650 struct mlx5_ifc_odp_cap_bits {
 651         u8         reserved_at_0[0x40];
 652
 653         u8         sig[0x1];
 654         u8         reserved_at_41[0x1f];
 655
 656         u8         reserved_at_60[0x20];
 657
 658         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 659
 660         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 661
 662         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 663
 664         u8         reserved_at_e0[0x720];
 665 };
 666
 667 struct mlx5_ifc_calc_op {
 668         u8        reserved_at_0[0x10];
 669         u8        reserved_at_10[0x9];
 670         u8        op_swap_endianness[0x1];
 671         u8        op_min[0x1];
 672         u8        op_xor[0x1];
 673         u8        op_or[0x1];
 674         u8        op_and[0x1];
 675         u8        op_max[0x1];
 676         u8        op_add[0x1];
 677 };
 678
 679 struct mlx5_ifc_vector_calc_cap_bits {
 680         u8         calc_matrix[0x1];
 681         u8         reserved_at_1[0x1f];
 682         u8         reserved_at_20[0x8];
 683         u8         max_vec_count[0x8];
 684         u8         reserved_at_30[0xd];
 685         u8         max_chunk_size[0x3];
 686         struct mlx5_ifc_calc_op calc0;
 687         struct mlx5_ifc_calc_op calc1;
 688         struct mlx5_ifc_calc_op calc2;
 689         struct mlx5_ifc_calc_op calc3;
 690
 691         u8         reserved_at_e0[0x720];
 692 };
 693
 694 enum {
 695         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 696         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 697         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 698 };
 699
 700 enum {
 701         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 702         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 703 };
 704
 705 enum {
 706         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 707         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 708         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 709         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 710         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 711 };
 712
 713 enum {
 714         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 715         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 716         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 717         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 718         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 719         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 720 };
 721
 722 enum {
 723         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 724         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 725 };
 726
 727 enum {
 728         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 729         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 730         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 731 };
 732
 733 enum {
 734         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 735         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 736 };
 737
 738 struct mlx5_ifc_cmd_hca_cap_bits {
 739         u8         reserved_at_0[0x80];
 740
 741         u8         log_max_srq_sz[0x8];
 742         u8         log_max_qp_sz[0x8];
 743         u8         reserved_at_90[0xb];
 744         u8         log_max_qp[0x5];
 745
 746         u8         reserved_at_a0[0xb];
 747         u8         log_max_srq[0x5];
 748         u8         reserved_at_b0[0x10];
 749
 750         u8         reserved_at_c0[0x8];
 751         u8         log_max_cq_sz[0x8];
 752         u8         reserved_at_d0[0xb];
 753         u8         log_max_cq[0x5];
 754
 755         u8         log_max_eq_sz[0x8];
 756         u8         reserved_at_e8[0x2];
 757         u8         log_max_mkey[0x6];
 758         u8         reserved_at_f0[0xc];
 759         u8         log_max_eq[0x4];
 760
 761         u8         max_indirection[0x8];
 762         u8         reserved_at_108[0x1];
 763         u8         log_max_mrw_sz[0x7];
 764         u8         reserved_at_110[0x2];
 765         u8         log_max_bsf_list_size[0x6];
 766         u8         reserved_at_118[0x2];
 767         u8         log_max_klm_list_size[0x6];
 768
 769         u8         reserved_at_120[0xa];
 770         u8         log_max_ra_req_dc[0x6];
 771         u8         reserved_at_130[0xa];
 772         u8         log_max_ra_res_dc[0x6];
 773
 774         u8         reserved_at_140[0xa];
 775         u8         log_max_ra_req_qp[0x6];
 776         u8         reserved_at_150[0xa];
 777         u8         log_max_ra_res_qp[0x6];
 778
 779         u8         pad_cap[0x1];
 780         u8         cc_query_allowed[0x1];
 781         u8         cc_modify_allowed[0x1];
 782         u8         reserved_at_163[0xd];
 783         u8         gid_table_size[0x10];
 784
 785         u8         out_of_seq_cnt[0x1];
 786         u8         vport_counters[0x1];
 787         u8         retransmission_q_counters[0x1];
 788         u8         reserved_at_183[0x1];
 789         u8         modify_rq_counter_set_id[0x1];
 790         u8         reserved_at_185[0x1];
 791         u8         max_qp_cnt[0xa];
 792         u8         pkey_table_size[0x10];
 793
 794         u8         vport_group_manager[0x1];
 795         u8         vhca_group_manager[0x1];
 796         u8         ib_virt[0x1];
 797         u8         eth_virt[0x1];
 798         u8         reserved_at_1a4[0x1];
 799         u8         ets[0x1];
 800         u8         nic_flow_table[0x1];
 801         u8         eswitch_flow_table[0x1];
 802         u8         early_vf_enable[0x1];
 803         u8         reserved_at_1a9[0x2];
 804         u8         local_ca_ack_delay[0x5];
 805         u8         reserved_at_1af[0x2];
 806         u8         ports_check[0x1];
 807         u8         reserved_at_1b2[0x1];
 808         u8         disable_link_up[0x1];
 809         u8         beacon_led[0x1];
 810         u8         port_type[0x2];
 811         u8         num_ports[0x8];
 812
 813         u8         reserved_at_1c0[0x3];
 814         u8         log_max_msg[0x5];
 815         u8         reserved_at_1c8[0x4];
 816         u8         max_tc[0x4];
 817         u8         reserved_at_1d0[0x1];
 818         u8         dcbx[0x1];
 819         u8         reserved_at_1d2[0x4];
 820         u8         rol_s[0x1];
 821         u8         rol_g[0x1];
 822         u8         reserved_at_1d8[0x1];
 823         u8         wol_s[0x1];
 824         u8         wol_g[0x1];
 825         u8         wol_a[0x1];
 826         u8         wol_b[0x1];
 827         u8         wol_m[0x1];
 828         u8         wol_u[0x1];
 829         u8         wol_p[0x1];
 830
 831         u8         stat_rate_support[0x10];
 832         u8         reserved_at_1f0[0xc];
 833         u8         cqe_version[0x4];
 834
 835         u8         compact_address_vector[0x1];
 836         u8         striding_rq[0x1];
 837         u8         reserved_at_201[0x2];
 838         u8         ipoib_basic_offloads[0x1];
 839         u8         reserved_at_205[0xa];
 840         u8         drain_sigerr[0x1];
 841         u8         cmdif_checksum[0x2];
 842         u8         sigerr_cqe[0x1];
 843         u8         reserved_at_213[0x1];
 844         u8         wq_signature[0x1];
 845         u8         sctr_data_cqe[0x1];
 846         u8         reserved_at_216[0x1];
 847         u8         sho[0x1];
 848         u8         tph[0x1];
 849         u8         rf[0x1];
 850         u8         dct[0x1];
 851         u8         qos[0x1];
 852         u8         eth_net_offloads[0x1];
 853         u8         roce[0x1];
 854         u8         atomic[0x1];
 855         u8         reserved_at_21f[0x1];
 856
 857         u8         cq_oi[0x1];
 858         u8         cq_resize[0x1];
 859         u8         cq_moderation[0x1];
 860         u8         reserved_at_223[0x3];
 861         u8         cq_eq_remap[0x1];
 862         u8         pg[0x1];
 863         u8         block_lb_mc[0x1];
 864         u8         reserved_at_229[0x1];
 865         u8         scqe_break_moderation[0x1];
 866         u8         cq_period_start_from_cqe[0x1];
 867         u8         cd[0x1];
 868         u8         reserved_at_22d[0x1];
 869         u8         apm[0x1];
 870         u8         vector_calc[0x1];
 871         u8         umr_ptr_rlky[0x1];
 872         u8         imaicl[0x1];
 873         u8         reserved_at_232[0x4];
 874         u8         qkv[0x1];
 875         u8         pkv[0x1];
 876         u8         set_deth_sqpn[0x1];
 877         u8         reserved_at_239[0x3];
 878         u8         xrc[0x1];
 879         u8         ud[0x1];
 880         u8         uc[0x1];
 881         u8         rc[0x1];
 882
 883         u8         reserved_at_240[0xa];
 884         u8         uar_sz[0x6];
 885         u8         reserved_at_250[0x8];
 886         u8         log_pg_sz[0x8];
 887
 888         u8         bf[0x1];
 889         u8         reserved_at_261[0x1];
 890         u8         pad_tx_eth_packet[0x1];
 891         u8         reserved_at_263[0x8];
 892         u8         log_bf_reg_size[0x5];
 893
 894         u8         reserved_at_270[0xb];
 895         u8         lag_master[0x1];
 896         u8         num_lag_ports[0x4];
 897
 898         u8         reserved_at_280[0x10];
 899         u8         max_wqe_sz_sq[0x10];
 900
 901         u8         reserved_at_2a0[0x10];
 902         u8         max_wqe_sz_rq[0x10];
 903
 904         u8         reserved_at_2c0[0x10];
 905         u8         max_wqe_sz_sq_dc[0x10];
 906
 907         u8         reserved_at_2e0[0x7];
 908         u8         max_qp_mcg[0x19];
 909
 910         u8         reserved_at_300[0x18];
 911         u8         log_max_mcg[0x8];
 912
 913         u8         reserved_at_320[0x3];
 914         u8         log_max_transport_domain[0x5];
 915         u8         reserved_at_328[0x3];
 916         u8         log_max_pd[0x5];
 917         u8         reserved_at_330[0xb];
 918         u8         log_max_xrcd[0x5];
 919
 920         u8         reserved_at_340[0x8];
 921         u8         log_max_flow_counter_bulk[0x8];
 922         u8         max_flow_counter[0x10];
 923
 924
 925         u8         reserved_at_360[0x3];
 926         u8         log_max_rq[0x5];
 927         u8         reserved_at_368[0x3];
 928         u8         log_max_sq[0x5];
 929         u8         reserved_at_370[0x3];
 930         u8         log_max_tir[0x5];
 931         u8         reserved_at_378[0x3];
 932         u8         log_max_tis[0x5];
 933
 934         u8         basic_cyclic_rcv_wqe[0x1];
 935         u8         reserved_at_381[0x2];
 936         u8         log_max_rmp[0x5];
 937         u8         reserved_at_388[0x3];
 938         u8         log_max_rqt[0x5];
 939         u8         reserved_at_390[0x3];
 940         u8         log_max_rqt_size[0x5];
 941         u8         reserved_at_398[0x3];
 942         u8         log_max_tis_per_sq[0x5];
 943
 944         u8         reserved_at_3a0[0x3];
 945         u8         log_max_stride_sz_rq[0x5];
 946         u8         reserved_at_3a8[0x3];
 947         u8         log_min_stride_sz_rq[0x5];
 948         u8         reserved_at_3b0[0x3];
 949         u8         log_max_stride_sz_sq[0x5];
 950         u8         reserved_at_3b8[0x3];
 951         u8         log_min_stride_sz_sq[0x5];
 952
 953         u8         reserved_at_3c0[0x1b];
 954         u8         log_max_wq_sz[0x5];
 955
 956         u8         nic_vport_change_event[0x1];
 957         u8         reserved_at_3e1[0xa];
 958         u8         log_max_vlan_list[0x5];
 959         u8         reserved_at_3f0[0x3];
 960         u8         log_max_current_mc_list[0x5];
 961         u8         reserved_at_3f8[0x3];
 962         u8         log_max_current_uc_list[0x5];
 963
 964         u8         reserved_at_400[0x80];
 965
 966         u8         reserved_at_480[0x3];
 967         u8         log_max_l2_table[0x5];
 968         u8         reserved_at_488[0x8];
 969         u8         log_uar_page_sz[0x10];
 970
 971         u8         reserved_at_4a0[0x20];
 972         u8         device_frequency_mhz[0x20];
 973         u8         device_frequency_khz[0x20];
 974
 975         u8         reserved_at_500[0x80];
 976
 977         u8         reserved_at_580[0x3f];
 978         u8         cqe_compression[0x1];
 979
 980         u8         cqe_compression_timeout[0x10];
 981         u8         cqe_compression_max_num[0x10];
 982
 983         u8         reserved_at_5e0[0x10];
 984         u8         tag_matching[0x1];
 985         u8         rndv_offload_rc[0x1];
 986         u8         rndv_offload_dc[0x1];
 987         u8         log_tag_matching_list_sz[0x5];
 988         u8         reserved_at_5e8[0x3];
 989         u8         log_max_xrq[0x5];
 990
 991         u8         reserved_at_5f0[0x200];
 992 };
 993
 994 enum mlx5_flow_destination_type {
 995         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
 996         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
 997         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
 998
 999         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1000 };
1001
1002 struct mlx5_ifc_dest_format_struct_bits {
1003         u8         destination_type[0x8];
1004         u8         destination_id[0x18];
1005
1006         u8         reserved_at_20[0x20];
1007 };
1008
1009 struct mlx5_ifc_flow_counter_list_bits {
1010         u8         clear[0x1];
1011         u8         num_of_counters[0xf];
1012         u8         flow_counter_id[0x10];
1013
1014         u8         reserved_at_20[0x20];
1015 };
1016
1017 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1018         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1019         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1020         u8         reserved_at_0[0x40];
1021 };
1022
1023 struct mlx5_ifc_fte_match_param_bits {
1024         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1025
1026         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1027
1028         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1029
1030         u8         reserved_at_600[0xa00];
1031 };
1032
1033 enum {
1034         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1035         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1036         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1037         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1038         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1039 };
1040
1041 struct mlx5_ifc_rx_hash_field_select_bits {
1042         u8         l3_prot_type[0x1];
1043         u8         l4_prot_type[0x1];
1044         u8         selected_fields[0x1e];
1045 };
1046
1047 enum {
1048         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1049         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1050 };
1051
1052 enum {
1053         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1054         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1055 };
1056
1057 struct mlx5_ifc_wq_bits {
1058         u8         wq_type[0x4];
1059         u8         wq_signature[0x1];
1060         u8         end_padding_mode[0x2];
1061         u8         cd_slave[0x1];
1062         u8         reserved_at_8[0x18];
1063
1064         u8         hds_skip_first_sge[0x1];
1065         u8         log2_hds_buf_size[0x3];
1066         u8         reserved_at_24[0x7];
1067         u8         page_offset[0x5];
1068         u8         lwm[0x10];
1069
1070         u8         reserved_at_40[0x8];
1071         u8         pd[0x18];
1072
1073         u8         reserved_at_60[0x8];
1074         u8         uar_page[0x18];
1075
1076         u8         dbr_addr[0x40];
1077
1078         u8         hw_counter[0x20];
1079
1080         u8         sw_counter[0x20];
1081
1082         u8         reserved_at_100[0xc];
1083         u8         log_wq_stride[0x4];
1084         u8         reserved_at_110[0x3];
1085         u8         log_wq_pg_sz[0x5];
1086         u8         reserved_at_118[0x3];
1087         u8         log_wq_sz[0x5];
1088
1089         u8         reserved_at_120[0x15];
1090         u8         log_wqe_num_of_strides[0x3];
1091         u8         two_byte_shift_en[0x1];
1092         u8         reserved_at_139[0x4];
1093         u8         log_wqe_stride_size[0x3];
1094
1095         u8         reserved_at_140[0x4c0];
1096
1097         struct mlx5_ifc_cmd_pas_bits pas[0];
1098 };
1099
1100 struct mlx5_ifc_rq_num_bits {
1101         u8         reserved_at_0[0x8];
1102         u8         rq_num[0x18];
1103 };
1104
1105 struct mlx5_ifc_mac_address_layout_bits {
1106         u8         reserved_at_0[0x10];
1107         u8         mac_addr_47_32[0x10];
1108
1109         u8         mac_addr_31_0[0x20];
1110 };
1111
1112 struct mlx5_ifc_vlan_layout_bits {
1113         u8         reserved_at_0[0x14];
1114         u8         vlan[0x0c];
1115
1116         u8         reserved_at_20[0x20];
1117 };
1118
1119 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1120         u8         reserved_at_0[0xa0];
1121
1122         u8         min_time_between_cnps[0x20];
1123
1124         u8         reserved_at_c0[0x12];
1125         u8         cnp_dscp[0x6];
1126         u8         reserved_at_d8[0x5];
1127         u8         cnp_802p_prio[0x3];
1128
1129         u8         reserved_at_e0[0x720];
1130 };
1131
1132 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1133         u8         reserved_at_0[0x60];
1134
1135         u8         reserved_at_60[0x4];
1136         u8         clamp_tgt_rate[0x1];
1137         u8         reserved_at_65[0x3];
1138         u8         clamp_tgt_rate_after_time_inc[0x1];
1139         u8         reserved_at_69[0x17];
1140
1141         u8         reserved_at_80[0x20];
1142
1143         u8         rpg_time_reset[0x20];
1144
1145         u8         rpg_byte_reset[0x20];
1146
1147         u8         rpg_threshold[0x20];
1148
1149         u8         rpg_max_rate[0x20];
1150
1151         u8         rpg_ai_rate[0x20];
1152
1153         u8         rpg_hai_rate[0x20];
1154
1155         u8         rpg_gd[0x20];
1156
1157         u8         rpg_min_dec_fac[0x20];
1158
1159         u8         rpg_min_rate[0x20];
1160
1161         u8         reserved_at_1c0[0xe0];
1162
1163         u8         rate_to_set_on_first_cnp[0x20];
1164
1165         u8         dce_tcp_g[0x20];
1166
1167         u8         dce_tcp_rtt[0x20];
1168
1169         u8         rate_reduce_monitor_period[0x20];
1170
1171         u8         reserved_at_320[0x20];
1172
1173         u8         initial_alpha_value[0x20];
1174
1175         u8         reserved_at_360[0x4a0];
1176 };
1177
1178 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1179         u8         reserved_at_0[0x80];
1180
1181         u8         rppp_max_rps[0x20];
1182
1183         u8         rpg_time_reset[0x20];
1184
1185         u8         rpg_byte_reset[0x20];
1186
1187         u8         rpg_threshold[0x20];
1188
1189         u8         rpg_max_rate[0x20];
1190
1191         u8         rpg_ai_rate[0x20];
1192
1193         u8         rpg_hai_rate[0x20];
1194
1195         u8         rpg_gd[0x20];
1196
1197         u8         rpg_min_dec_fac[0x20];
1198
1199         u8         rpg_min_rate[0x20];
1200
1201         u8         reserved_at_1c0[0x640];
1202 };
1203
1204 enum {
1205         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1206         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1207         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1208 };
1209
1210 struct mlx5_ifc_resize_field_select_bits {
1211         u8         resize_field_select[0x20];
1212 };
1213
1214 enum {
1215         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1216         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1217         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1218         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1219 };
1220
1221 struct mlx5_ifc_modify_field_select_bits {
1222         u8         modify_field_select[0x20];
1223 };
1224
1225 struct mlx5_ifc_field_select_r_roce_np_bits {
1226         u8         field_select_r_roce_np[0x20];
1227 };
1228
1229 struct mlx5_ifc_field_select_r_roce_rp_bits {
1230         u8         field_select_r_roce_rp[0x20];
1231 };
1232
1233 enum {
1234         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1235         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1236         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1237         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1238         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1239         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1240         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1241         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1242         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1243         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1244 };
1245
1246 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1247         u8         field_select_8021qaurp[0x20];
1248 };
1249
1250 struct mlx5_ifc_phys_layer_cntrs_bits {
1251         u8         time_since_last_clear_high[0x20];
1252
1253         u8         time_since_last_clear_low[0x20];
1254
1255         u8         symbol_errors_high[0x20];
1256
1257         u8         symbol_errors_low[0x20];
1258
1259         u8         sync_headers_errors_high[0x20];
1260
1261         u8         sync_headers_errors_low[0x20];
1262
1263         u8         edpl_bip_errors_lane0_high[0x20];
1264
1265         u8         edpl_bip_errors_lane0_low[0x20];
1266
1267         u8         edpl_bip_errors_lane1_high[0x20];
1268
1269         u8         edpl_bip_errors_lane1_low[0x20];
1270
1271         u8         edpl_bip_errors_lane2_high[0x20];
1272
1273         u8         edpl_bip_errors_lane2_low[0x20];
1274
1275         u8         edpl_bip_errors_lane3_high[0x20];
1276
1277         u8         edpl_bip_errors_lane3_low[0x20];
1278
1279         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1280
1281         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1282
1283         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1284
1285         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1286
1287         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1288
1289         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1290
1291         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1292
1293         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1294
1295         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1296
1297         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1298
1299         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1300
1301         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1302
1303         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1304
1305         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1306
1307         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1308
1309         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1310
1311         u8         rs_fec_corrected_blocks_high[0x20];
1312
1313         u8         rs_fec_corrected_blocks_low[0x20];
1314
1315         u8         rs_fec_uncorrectable_blocks_high[0x20];
1316
1317         u8         rs_fec_uncorrectable_blocks_low[0x20];
1318
1319         u8         rs_fec_no_errors_blocks_high[0x20];
1320
1321         u8         rs_fec_no_errors_blocks_low[0x20];
1322
1323         u8         rs_fec_single_error_blocks_high[0x20];
1324
1325         u8         rs_fec_single_error_blocks_low[0x20];
1326
1327         u8         rs_fec_corrected_symbols_total_high[0x20];
1328
1329         u8         rs_fec_corrected_symbols_total_low[0x20];
1330
1331         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1332
1333         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1334
1335         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1336
1337         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1338
1339         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1340
1341         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1342
1343         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1344
1345         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1346
1347         u8         link_down_events[0x20];
1348
1349         u8         successful_recovery_events[0x20];
1350
1351         u8         reserved_at_640[0x180];
1352 };
1353
1354 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1355         u8         symbol_error_counter[0x10];
1356
1357         u8         link_error_recovery_counter[0x8];
1358
1359         u8         link_downed_counter[0x8];
1360
1361         u8         port_rcv_errors[0x10];
1362
1363         u8         port_rcv_remote_physical_errors[0x10];
1364
1365         u8         port_rcv_switch_relay_errors[0x10];
1366
1367         u8         port_xmit_discards[0x10];
1368
1369         u8         port_xmit_constraint_errors[0x8];
1370
1371         u8         port_rcv_constraint_errors[0x8];
1372
1373         u8         reserved_at_70[0x8];
1374
1375         u8         link_overrun_errors[0x8];
1376
1377         u8         reserved_at_80[0x10];
1378
1379         u8         vl_15_dropped[0x10];
1380
1381         u8         reserved_at_a0[0xa0];
1382 };
1383
1384 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1385         u8         transmit_queue_high[0x20];
1386
1387         u8         transmit_queue_low[0x20];
1388
1389         u8         reserved_at_40[0x780];
1390 };
1391
1392 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1393         u8         rx_octets_high[0x20];
1394
1395         u8         rx_octets_low[0x20];
1396
1397         u8         reserved_at_40[0xc0];
1398
1399         u8         rx_frames_high[0x20];
1400
1401         u8         rx_frames_low[0x20];
1402
1403         u8         tx_octets_high[0x20];
1404
1405         u8         tx_octets_low[0x20];
1406
1407         u8         reserved_at_180[0xc0];
1408
1409         u8         tx_frames_high[0x20];
1410
1411         u8         tx_frames_low[0x20];
1412
1413         u8         rx_pause_high[0x20];
1414
1415         u8         rx_pause_low[0x20];
1416
1417         u8         rx_pause_duration_high[0x20];
1418
1419         u8         rx_pause_duration_low[0x20];
1420
1421         u8         tx_pause_high[0x20];
1422
1423         u8         tx_pause_low[0x20];
1424
1425         u8         tx_pause_duration_high[0x20];
1426
1427         u8         tx_pause_duration_low[0x20];
1428
1429         u8         rx_pause_transition_high[0x20];
1430
1431         u8         rx_pause_transition_low[0x20];
1432
1433         u8         reserved_at_3c0[0x400];
1434 };
1435
1436 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1437         u8         port_transmit_wait_high[0x20];
1438
1439         u8         port_transmit_wait_low[0x20];
1440
1441         u8         reserved_at_40[0x780];
1442 };
1443
1444 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1445         u8         dot3stats_alignment_errors_high[0x20];
1446
1447         u8         dot3stats_alignment_errors_low[0x20];
1448
1449         u8         dot3stats_fcs_errors_high[0x20];
1450
1451         u8         dot3stats_fcs_errors_low[0x20];
1452
1453         u8         dot3stats_single_collision_frames_high[0x20];
1454
1455         u8         dot3stats_single_collision_frames_low[0x20];
1456
1457         u8         dot3stats_multiple_collision_frames_high[0x20];
1458
1459         u8         dot3stats_multiple_collision_frames_low[0x20];
1460
1461         u8         dot3stats_sqe_test_errors_high[0x20];
1462
1463         u8         dot3stats_sqe_test_errors_low[0x20];
1464
1465         u8         dot3stats_deferred_transmissions_high[0x20];
1466
1467         u8         dot3stats_deferred_transmissions_low[0x20];
1468
1469         u8         dot3stats_late_collisions_high[0x20];
1470
1471         u8         dot3stats_late_collisions_low[0x20];
1472
1473         u8         dot3stats_excessive_collisions_high[0x20];
1474
1475         u8         dot3stats_excessive_collisions_low[0x20];
1476
1477         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1478
1479         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1480
1481         u8         dot3stats_carrier_sense_errors_high[0x20];
1482
1483         u8         dot3stats_carrier_sense_errors_low[0x20];
1484
1485         u8         dot3stats_frame_too_longs_high[0x20];
1486
1487         u8         dot3stats_frame_too_longs_low[0x20];
1488
1489         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1490
1491         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1492
1493         u8         dot3stats_symbol_errors_high[0x20];
1494
1495         u8         dot3stats_symbol_errors_low[0x20];
1496
1497         u8         dot3control_in_unknown_opcodes_high[0x20];
1498
1499         u8         dot3control_in_unknown_opcodes_low[0x20];
1500
1501         u8         dot3in_pause_frames_high[0x20];
1502
1503         u8         dot3in_pause_frames_low[0x20];
1504
1505         u8         dot3out_pause_frames_high[0x20];
1506
1507         u8         dot3out_pause_frames_low[0x20];
1508
1509         u8         reserved_at_400[0x3c0];
1510 };
1511
1512 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1513         u8         ether_stats_drop_events_high[0x20];
1514
1515         u8         ether_stats_drop_events_low[0x20];
1516
1517         u8         ether_stats_octets_high[0x20];
1518
1519         u8         ether_stats_octets_low[0x20];
1520
1521         u8         ether_stats_pkts_high[0x20];
1522
1523         u8         ether_stats_pkts_low[0x20];
1524
1525         u8         ether_stats_broadcast_pkts_high[0x20];
1526
1527         u8         ether_stats_broadcast_pkts_low[0x20];
1528
1529         u8         ether_stats_multicast_pkts_high[0x20];
1530
1531         u8         ether_stats_multicast_pkts_low[0x20];
1532
1533         u8         ether_stats_crc_align_errors_high[0x20];
1534
1535         u8         ether_stats_crc_align_errors_low[0x20];
1536
1537         u8         ether_stats_undersize_pkts_high[0x20];
1538
1539         u8         ether_stats_undersize_pkts_low[0x20];
1540
1541         u8         ether_stats_oversize_pkts_high[0x20];
1542
1543         u8         ether_stats_oversize_pkts_low[0x20];
1544
1545         u8         ether_stats_fragments_high[0x20];
1546
1547         u8         ether_stats_fragments_low[0x20];
1548
1549         u8         ether_stats_jabbers_high[0x20];
1550
1551         u8         ether_stats_jabbers_low[0x20];
1552
1553         u8         ether_stats_collisions_high[0x20];
1554
1555         u8         ether_stats_collisions_low[0x20];
1556
1557         u8         ether_stats_pkts64octets_high[0x20];
1558
1559         u8         ether_stats_pkts64octets_low[0x20];
1560
1561         u8         ether_stats_pkts65to127octets_high[0x20];
1562
1563         u8         ether_stats_pkts65to127octets_low[0x20];
1564
1565         u8         ether_stats_pkts128to255octets_high[0x20];
1566
1567         u8         ether_stats_pkts128to255octets_low[0x20];
1568
1569         u8         ether_stats_pkts256to511octets_high[0x20];
1570
1571         u8         ether_stats_pkts256to511octets_low[0x20];
1572
1573         u8         ether_stats_pkts512to1023octets_high[0x20];
1574
1575         u8         ether_stats_pkts512to1023octets_low[0x20];
1576
1577         u8         ether_stats_pkts1024to1518octets_high[0x20];
1578
1579         u8         ether_stats_pkts1024to1518octets_low[0x20];
1580
1581         u8         ether_stats_pkts1519to2047octets_high[0x20];
1582
1583         u8         ether_stats_pkts1519to2047octets_low[0x20];
1584
1585         u8         ether_stats_pkts2048to4095octets_high[0x20];
1586
1587         u8         ether_stats_pkts2048to4095octets_low[0x20];
1588
1589         u8         ether_stats_pkts4096to8191octets_high[0x20];
1590
1591         u8         ether_stats_pkts4096to8191octets_low[0x20];
1592
1593         u8         ether_stats_pkts8192to10239octets_high[0x20];
1594
1595         u8         ether_stats_pkts8192to10239octets_low[0x20];
1596
1597         u8         reserved_at_540[0x280];
1598 };
1599
1600 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1601         u8         if_in_octets_high[0x20];
1602
1603         u8         if_in_octets_low[0x20];
1604
1605         u8         if_in_ucast_pkts_high[0x20];
1606
1607         u8         if_in_ucast_pkts_low[0x20];
1608
1609         u8         if_in_discards_high[0x20];
1610
1611         u8         if_in_discards_low[0x20];
1612
1613         u8         if_in_errors_high[0x20];
1614
1615         u8         if_in_errors_low[0x20];
1616
1617         u8         if_in_unknown_protos_high[0x20];
1618
1619         u8         if_in_unknown_protos_low[0x20];
1620
1621         u8         if_out_octets_high[0x20];
1622
1623         u8         if_out_octets_low[0x20];
1624
1625         u8         if_out_ucast_pkts_high[0x20];
1626
1627         u8         if_out_ucast_pkts_low[0x20];
1628
1629         u8         if_out_discards_high[0x20];
1630
1631         u8         if_out_discards_low[0x20];
1632
1633         u8         if_out_errors_high[0x20];
1634
1635         u8         if_out_errors_low[0x20];
1636
1637         u8         if_in_multicast_pkts_high[0x20];
1638
1639         u8         if_in_multicast_pkts_low[0x20];
1640
1641         u8         if_in_broadcast_pkts_high[0x20];
1642
1643         u8         if_in_broadcast_pkts_low[0x20];
1644
1645         u8         if_out_multicast_pkts_high[0x20];
1646
1647         u8         if_out_multicast_pkts_low[0x20];
1648
1649         u8         if_out_broadcast_pkts_high[0x20];
1650
1651         u8         if_out_broadcast_pkts_low[0x20];
1652
1653         u8         reserved_at_340[0x480];
1654 };
1655
1656 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1657         u8         a_frames_transmitted_ok_high[0x20];
1658
1659         u8         a_frames_transmitted_ok_low[0x20];
1660
1661         u8         a_frames_received_ok_high[0x20];
1662
1663         u8         a_frames_received_ok_low[0x20];
1664
1665         u8         a_frame_check_sequence_errors_high[0x20];
1666
1667         u8         a_frame_check_sequence_errors_low[0x20];
1668
1669         u8         a_alignment_errors_high[0x20];
1670
1671         u8         a_alignment_errors_low[0x20];
1672
1673         u8         a_octets_transmitted_ok_high[0x20];
1674
1675         u8         a_octets_transmitted_ok_low[0x20];
1676
1677         u8         a_octets_received_ok_high[0x20];
1678
1679         u8         a_octets_received_ok_low[0x20];
1680
1681         u8         a_multicast_frames_xmitted_ok_high[0x20];
1682
1683         u8         a_multicast_frames_xmitted_ok_low[0x20];
1684
1685         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1686
1687         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1688
1689         u8         a_multicast_frames_received_ok_high[0x20];
1690
1691         u8         a_multicast_frames_received_ok_low[0x20];
1692
1693         u8         a_broadcast_frames_received_ok_high[0x20];
1694
1695         u8         a_broadcast_frames_received_ok_low[0x20];
1696
1697         u8         a_in_range_length_errors_high[0x20];
1698
1699         u8         a_in_range_length_errors_low[0x20];
1700
1701         u8         a_out_of_range_length_field_high[0x20];
1702
1703         u8         a_out_of_range_length_field_low[0x20];
1704
1705         u8         a_frame_too_long_errors_high[0x20];
1706
1707         u8         a_frame_too_long_errors_low[0x20];
1708
1709         u8         a_symbol_error_during_carrier_high[0x20];
1710
1711         u8         a_symbol_error_during_carrier_low[0x20];
1712
1713         u8         a_mac_control_frames_transmitted_high[0x20];
1714
1715         u8         a_mac_control_frames_transmitted_low[0x20];
1716
1717         u8         a_mac_control_frames_received_high[0x20];
1718
1719         u8         a_mac_control_frames_received_low[0x20];
1720
1721         u8         a_unsupported_opcodes_received_high[0x20];
1722
1723         u8         a_unsupported_opcodes_received_low[0x20];
1724
1725         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1726
1727         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1728
1729         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1730
1731         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1732
1733         u8         reserved_at_4c0[0x300];
1734 };
1735
1736 struct mlx5_ifc_cmd_inter_comp_event_bits {
1737         u8         command_completion_vector[0x20];
1738
1739         u8         reserved_at_20[0xc0];
1740 };
1741
1742 struct mlx5_ifc_stall_vl_event_bits {
1743         u8         reserved_at_0[0x18];
1744         u8         port_num[0x1];
1745         u8         reserved_at_19[0x3];
1746         u8         vl[0x4];
1747
1748         u8         reserved_at_20[0xa0];
1749 };
1750
1751 struct mlx5_ifc_db_bf_congestion_event_bits {
1752         u8         event_subtype[0x8];
1753         u8         reserved_at_8[0x8];
1754         u8         congestion_level[0x8];
1755         u8         reserved_at_18[0x8];
1756
1757         u8         reserved_at_20[0xa0];
1758 };
1759
1760 struct mlx5_ifc_gpio_event_bits {
1761         u8         reserved_at_0[0x60];
1762
1763         u8         gpio_event_hi[0x20];
1764
1765         u8         gpio_event_lo[0x20];
1766
1767         u8         reserved_at_a0[0x40];
1768 };
1769
1770 struct mlx5_ifc_port_state_change_event_bits {
1771         u8         reserved_at_0[0x40];
1772
1773         u8         port_num[0x4];
1774         u8         reserved_at_44[0x1c];
1775
1776         u8         reserved_at_60[0x80];
1777 };
1778
1779 struct mlx5_ifc_dropped_packet_logged_bits {
1780         u8         reserved_at_0[0xe0];
1781 };
1782
1783 enum {
1784         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1785         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1786 };
1787
1788 struct mlx5_ifc_cq_error_bits {
1789         u8         reserved_at_0[0x8];
1790         u8         cqn[0x18];
1791
1792         u8         reserved_at_20[0x20];
1793
1794         u8         reserved_at_40[0x18];
1795         u8         syndrome[0x8];
1796
1797         u8         reserved_at_60[0x80];
1798 };
1799
1800 struct mlx5_ifc_rdma_page_fault_event_bits {
1801         u8         bytes_committed[0x20];
1802
1803         u8         r_key[0x20];
1804
1805         u8         reserved_at_40[0x10];
1806         u8         packet_len[0x10];
1807
1808         u8         rdma_op_len[0x20];
1809
1810         u8         rdma_va[0x40];
1811
1812         u8         reserved_at_c0[0x5];
1813         u8         rdma[0x1];
1814         u8         write[0x1];
1815         u8         requestor[0x1];
1816         u8         qp_number[0x18];
1817 };
1818
1819 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1820         u8         bytes_committed[0x20];
1821
1822         u8         reserved_at_20[0x10];
1823         u8         wqe_index[0x10];
1824
1825         u8         reserved_at_40[0x10];
1826         u8         len[0x10];
1827
1828         u8         reserved_at_60[0x60];
1829
1830         u8         reserved_at_c0[0x5];
1831         u8         rdma[0x1];
1832         u8         write_read[0x1];
1833         u8         requestor[0x1];
1834         u8         qpn[0x18];
1835 };
1836
1837 struct mlx5_ifc_qp_events_bits {
1838         u8         reserved_at_0[0xa0];
1839
1840         u8         type[0x8];
1841         u8         reserved_at_a8[0x18];
1842
1843         u8         reserved_at_c0[0x8];
1844         u8         qpn_rqn_sqn[0x18];
1845 };
1846
1847 struct mlx5_ifc_dct_events_bits {
1848         u8         reserved_at_0[0xc0];
1849
1850         u8         reserved_at_c0[0x8];
1851         u8         dct_number[0x18];
1852 };
1853
1854 struct mlx5_ifc_comp_event_bits {
1855         u8         reserved_at_0[0xc0];
1856
1857         u8         reserved_at_c0[0x8];
1858         u8         cq_number[0x18];
1859 };
1860
1861 enum {
1862         MLX5_QPC_STATE_RST        = 0x0,
1863         MLX5_QPC_STATE_INIT       = 0x1,
1864         MLX5_QPC_STATE_RTR        = 0x2,
1865         MLX5_QPC_STATE_RTS        = 0x3,
1866         MLX5_QPC_STATE_SQER       = 0x4,
1867         MLX5_QPC_STATE_ERR        = 0x6,
1868         MLX5_QPC_STATE_SQD        = 0x7,
1869         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1870 };
1871
1872 enum {
1873         MLX5_QPC_ST_RC            = 0x0,
1874         MLX5_QPC_ST_UC            = 0x1,
1875         MLX5_QPC_ST_UD            = 0x2,
1876         MLX5_QPC_ST_XRC           = 0x3,
1877         MLX5_QPC_ST_DCI           = 0x5,
1878         MLX5_QPC_ST_QP0           = 0x7,
1879         MLX5_QPC_ST_QP1           = 0x8,
1880         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1881         MLX5_QPC_ST_REG_UMR       = 0xc,
1882 };
1883
1884 enum {
1885         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1886         MLX5_QPC_PM_STATE_REARM     = 0x1,
1887         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1888         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1889 };
1890
1891 enum {
1892         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1893         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1894 };
1895
1896 enum {
1897         MLX5_QPC_MTU_256_BYTES        = 0x1,
1898         MLX5_QPC_MTU_512_BYTES        = 0x2,
1899         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1900         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1901         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1902         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1903 };
1904
1905 enum {
1906         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1907         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1908         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1909         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1910         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1911         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1912         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1913         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1914 };
1915
1916 enum {
1917         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1918         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1919         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1920 };
1921
1922 enum {
1923         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1924         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1925         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1926 };
1927
1928 struct mlx5_ifc_qpc_bits {
1929         u8         state[0x4];
1930         u8         lag_tx_port_affinity[0x4];
1931         u8         st[0x8];
1932         u8         reserved_at_10[0x3];
1933         u8         pm_state[0x2];
1934         u8         reserved_at_15[0x7];
1935         u8         end_padding_mode[0x2];
1936         u8         reserved_at_1e[0x2];
1937
1938         u8         wq_signature[0x1];
1939         u8         block_lb_mc[0x1];
1940         u8         atomic_like_write_en[0x1];
1941         u8         latency_sensitive[0x1];
1942         u8         reserved_at_24[0x1];
1943         u8         drain_sigerr[0x1];
1944         u8         reserved_at_26[0x2];
1945         u8         pd[0x18];
1946
1947         u8         mtu[0x3];
1948         u8         log_msg_max[0x5];
1949         u8         reserved_at_48[0x1];
1950         u8         log_rq_size[0x4];
1951         u8         log_rq_stride[0x3];
1952         u8         no_sq[0x1];
1953         u8         log_sq_size[0x4];
1954         u8         reserved_at_55[0x6];
1955         u8         rlky[0x1];
1956         u8         ulp_stateless_offload_mode[0x4];
1957
1958         u8         counter_set_id[0x8];
1959         u8         uar_page[0x18];
1960
1961         u8         reserved_at_80[0x8];
1962         u8         user_index[0x18];
1963
1964         u8         reserved_at_a0[0x3];
1965         u8         log_page_size[0x5];
1966         u8         remote_qpn[0x18];
1967
1968         struct mlx5_ifc_ads_bits primary_address_path;
1969
1970         struct mlx5_ifc_ads_bits secondary_address_path;
1971
1972         u8         log_ack_req_freq[0x4];
1973         u8         reserved_at_384[0x4];
1974         u8         log_sra_max[0x3];
1975         u8         reserved_at_38b[0x2];
1976         u8         retry_count[0x3];
1977         u8         rnr_retry[0x3];
1978         u8         reserved_at_393[0x1];
1979         u8         fre[0x1];
1980         u8         cur_rnr_retry[0x3];
1981         u8         cur_retry_count[0x3];
1982         u8         reserved_at_39b[0x5];
1983
1984         u8         reserved_at_3a0[0x20];
1985
1986         u8         reserved_at_3c0[0x8];
1987         u8         next_send_psn[0x18];
1988
1989         u8         reserved_at_3e0[0x8];
1990         u8         cqn_snd[0x18];
1991
1992         u8         reserved_at_400[0x8];
1993         u8         deth_sqpn[0x18];
1994
1995         u8         reserved_at_420[0x20];
1996
1997         u8         reserved_at_440[0x8];
1998         u8         last_acked_psn[0x18];
1999
2000         u8         reserved_at_460[0x8];
2001         u8         ssn[0x18];
2002
2003         u8         reserved_at_480[0x8];
2004         u8         log_rra_max[0x3];
2005         u8         reserved_at_48b[0x1];
2006         u8         atomic_mode[0x4];
2007         u8         rre[0x1];
2008         u8         rwe[0x1];
2009         u8         rae[0x1];
2010         u8         reserved_at_493[0x1];
2011         u8         page_offset[0x6];
2012         u8         reserved_at_49a[0x3];
2013         u8         cd_slave_receive[0x1];
2014         u8         cd_slave_send[0x1];
2015         u8         cd_master[0x1];
2016
2017         u8         reserved_at_4a0[0x3];
2018         u8         min_rnr_nak[0x5];
2019         u8         next_rcv_psn[0x18];
2020
2021         u8         reserved_at_4c0[0x8];
2022         u8         xrcd[0x18];
2023
2024         u8         reserved_at_4e0[0x8];
2025         u8         cqn_rcv[0x18];
2026
2027         u8         dbr_addr[0x40];
2028
2029         u8         q_key[0x20];
2030
2031         u8         reserved_at_560[0x5];
2032         u8         rq_type[0x3];
2033         u8         srqn_rmpn_xrqn[0x18];
2034
2035         u8         reserved_at_580[0x8];
2036         u8         rmsn[0x18];
2037
2038         u8         hw_sq_wqebb_counter[0x10];
2039         u8         sw_sq_wqebb_counter[0x10];
2040
2041         u8         hw_rq_counter[0x20];
2042
2043         u8         sw_rq_counter[0x20];
2044
2045         u8         reserved_at_600[0x20];
2046
2047         u8         reserved_at_620[0xf];
2048         u8         cgs[0x1];
2049         u8         cs_req[0x8];
2050         u8         cs_res[0x8];
2051
2052         u8         dc_access_key[0x40];
2053
2054         u8         reserved_at_680[0xc0];
2055 };
2056
2057 struct mlx5_ifc_roce_addr_layout_bits {
2058         u8         source_l3_address[16][0x8];
2059
2060         u8         reserved_at_80[0x3];
2061         u8         vlan_valid[0x1];
2062         u8         vlan_id[0xc];
2063         u8         source_mac_47_32[0x10];
2064
2065         u8         source_mac_31_0[0x20];
2066
2067         u8         reserved_at_c0[0x14];
2068         u8         roce_l3_type[0x4];
2069         u8         roce_version[0x8];
2070
2071         u8         reserved_at_e0[0x20];
2072 };
2073
2074 union mlx5_ifc_hca_cap_union_bits {
2075         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2076         struct mlx5_ifc_odp_cap_bits odp_cap;
2077         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2078         struct mlx5_ifc_roce_cap_bits roce_cap;
2079         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2080         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2081         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2082         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2083         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2084         struct mlx5_ifc_qos_cap_bits qos_cap;
2085         u8         reserved_at_0[0x8000];
2086 };
2087
2088 enum {
2089         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2090         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2091         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2092         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2093         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2094         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2095 };
2096
2097 struct mlx5_ifc_flow_context_bits {
2098         u8         reserved_at_0[0x20];
2099
2100         u8         group_id[0x20];
2101
2102         u8         reserved_at_40[0x8];
2103         u8         flow_tag[0x18];
2104
2105         u8         reserved_at_60[0x10];
2106         u8         action[0x10];
2107
2108         u8         reserved_at_80[0x8];
2109         u8         destination_list_size[0x18];
2110
2111         u8         reserved_at_a0[0x8];
2112         u8         flow_counter_list_size[0x18];
2113
2114         u8         encap_id[0x20];
2115
2116         u8         reserved_at_e0[0x120];
2117
2118         struct mlx5_ifc_fte_match_param_bits match_value;
2119
2120         u8         reserved_at_1200[0x600];
2121
2122         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2123 };
2124
2125 enum {
2126         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2127         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2128 };
2129
2130 struct mlx5_ifc_xrc_srqc_bits {
2131         u8         state[0x4];
2132         u8         log_xrc_srq_size[0x4];
2133         u8         reserved_at_8[0x18];
2134
2135         u8         wq_signature[0x1];
2136         u8         cont_srq[0x1];
2137         u8         reserved_at_22[0x1];
2138         u8         rlky[0x1];
2139         u8         basic_cyclic_rcv_wqe[0x1];
2140         u8         log_rq_stride[0x3];
2141         u8         xrcd[0x18];
2142
2143         u8         page_offset[0x6];
2144         u8         reserved_at_46[0x2];
2145         u8         cqn[0x18];
2146
2147         u8         reserved_at_60[0x20];
2148
2149         u8         user_index_equal_xrc_srqn[0x1];
2150         u8         reserved_at_81[0x1];
2151         u8         log_page_size[0x6];
2152         u8         user_index[0x18];
2153
2154         u8         reserved_at_a0[0x20];
2155
2156         u8         reserved_at_c0[0x8];
2157         u8         pd[0x18];
2158
2159         u8         lwm[0x10];
2160         u8         wqe_cnt[0x10];
2161
2162         u8         reserved_at_100[0x40];
2163
2164         u8         db_record_addr_h[0x20];
2165
2166         u8         db_record_addr_l[0x1e];
2167         u8         reserved_at_17e[0x2];
2168
2169         u8         reserved_at_180[0x80];
2170 };
2171
2172 struct mlx5_ifc_traffic_counter_bits {
2173         u8         packets[0x40];
2174
2175         u8         octets[0x40];
2176 };
2177
2178 struct mlx5_ifc_tisc_bits {
2179         u8         strict_lag_tx_port_affinity[0x1];
2180         u8         reserved_at_1[0x3];
2181         u8         lag_tx_port_affinity[0x04];
2182
2183         u8         reserved_at_8[0x4];
2184         u8         prio[0x4];
2185         u8         reserved_at_10[0x10];
2186
2187         u8         reserved_at_20[0x100];
2188
2189         u8         reserved_at_120[0x8];
2190         u8         transport_domain[0x18];
2191
2192         u8         reserved_at_140[0x3c0];
2193 };
2194
2195 enum {
2196         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2197         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2198 };
2199
2200 enum {
2201         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2202         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2203 };
2204
2205 enum {
2206         MLX5_RX_HASH_FN_NONE           = 0x0,
2207         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2208         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2209 };
2210
2211 enum {
2212         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2213         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2214 };
2215
2216 struct mlx5_ifc_tirc_bits {
2217         u8         reserved_at_0[0x20];
2218
2219         u8         disp_type[0x4];
2220         u8         reserved_at_24[0x1c];
2221
2222         u8         reserved_at_40[0x40];
2223
2224         u8         reserved_at_80[0x4];
2225         u8         lro_timeout_period_usecs[0x10];
2226         u8         lro_enable_mask[0x4];
2227         u8         lro_max_ip_payload_size[0x8];
2228
2229         u8         reserved_at_a0[0x40];
2230
2231         u8         reserved_at_e0[0x8];
2232         u8         inline_rqn[0x18];
2233
2234         u8         rx_hash_symmetric[0x1];
2235         u8         reserved_at_101[0x1];
2236         u8         tunneled_offload_en[0x1];
2237         u8         reserved_at_103[0x5];
2238         u8         indirect_table[0x18];
2239
2240         u8         rx_hash_fn[0x4];
2241         u8         reserved_at_124[0x2];
2242         u8         self_lb_block[0x2];
2243         u8         transport_domain[0x18];
2244
2245         u8         rx_hash_toeplitz_key[10][0x20];
2246
2247         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2248
2249         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2250
2251         u8         reserved_at_2c0[0x4c0];
2252 };
2253
2254 enum {
2255         MLX5_SRQC_STATE_GOOD   = 0x0,
2256         MLX5_SRQC_STATE_ERROR  = 0x1,
2257 };
2258
2259 struct mlx5_ifc_srqc_bits {
2260         u8         state[0x4];
2261         u8         log_srq_size[0x4];
2262         u8         reserved_at_8[0x18];
2263
2264         u8         wq_signature[0x1];
2265         u8         cont_srq[0x1];
2266         u8         reserved_at_22[0x1];
2267         u8         rlky[0x1];
2268         u8         reserved_at_24[0x1];
2269         u8         log_rq_stride[0x3];
2270         u8         xrcd[0x18];
2271
2272         u8         page_offset[0x6];
2273         u8         reserved_at_46[0x2];
2274         u8         cqn[0x18];
2275
2276         u8         reserved_at_60[0x20];
2277
2278         u8         reserved_at_80[0x2];
2279         u8         log_page_size[0x6];
2280         u8         reserved_at_88[0x18];
2281
2282         u8         reserved_at_a0[0x20];
2283
2284         u8         reserved_at_c0[0x8];
2285         u8         pd[0x18];
2286
2287         u8         lwm[0x10];
2288         u8         wqe_cnt[0x10];
2289
2290         u8         reserved_at_100[0x40];
2291
2292         u8         dbr_addr[0x40];
2293
2294         u8         reserved_at_180[0x80];
2295 };
2296
2297 enum {
2298         MLX5_SQC_STATE_RST  = 0x0,
2299         MLX5_SQC_STATE_RDY  = 0x1,
2300         MLX5_SQC_STATE_ERR  = 0x3,
2301 };
2302
2303 struct mlx5_ifc_sqc_bits {
2304         u8         rlky[0x1];
2305         u8         cd_master[0x1];
2306         u8         fre[0x1];
2307         u8         flush_in_error_en[0x1];
2308         u8         reserved_at_4[0x1];
2309         u8         min_wqe_inline_mode[0x3];
2310         u8         state[0x4];
2311         u8         reg_umr[0x1];
2312         u8         reserved_at_d[0x13];
2313
2314         u8         reserved_at_20[0x8];
2315         u8         user_index[0x18];
2316
2317         u8         reserved_at_40[0x8];
2318         u8         cqn[0x18];
2319
2320         u8         reserved_at_60[0x90];
2321
2322         u8         packet_pacing_rate_limit_index[0x10];
2323         u8         tis_lst_sz[0x10];
2324         u8         reserved_at_110[0x10];
2325
2326         u8         reserved_at_120[0x40];
2327
2328         u8         reserved_at_160[0x8];
2329         u8         tis_num_0[0x18];
2330
2331         struct mlx5_ifc_wq_bits wq;
2332 };
2333
2334 struct mlx5_ifc_rqtc_bits {
2335         u8         reserved_at_0[0xa0];
2336
2337         u8         reserved_at_a0[0x10];
2338         u8         rqt_max_size[0x10];
2339
2340         u8         reserved_at_c0[0x10];
2341         u8         rqt_actual_size[0x10];
2342
2343         u8         reserved_at_e0[0x6a0];
2344
2345         struct mlx5_ifc_rq_num_bits rq_num[0];
2346 };
2347
2348 enum {
2349         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2350         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2351 };
2352
2353 enum {
2354         MLX5_RQC_STATE_RST  = 0x0,
2355         MLX5_RQC_STATE_RDY  = 0x1,
2356         MLX5_RQC_STATE_ERR  = 0x3,
2357 };
2358
2359 struct mlx5_ifc_rqc_bits {
2360         u8         rlky[0x1];
2361         u8         reserved_at_1[0x1];
2362         u8         scatter_fcs[0x1];
2363         u8         vsd[0x1];
2364         u8         mem_rq_type[0x4];
2365         u8         state[0x4];
2366         u8         reserved_at_c[0x1];
2367         u8         flush_in_error_en[0x1];
2368         u8         reserved_at_e[0x12];
2369
2370         u8         reserved_at_20[0x8];
2371         u8         user_index[0x18];
2372
2373         u8         reserved_at_40[0x8];
2374         u8         cqn[0x18];
2375
2376         u8         counter_set_id[0x8];
2377         u8         reserved_at_68[0x18];
2378
2379         u8         reserved_at_80[0x8];
2380         u8         rmpn[0x18];
2381
2382         u8         reserved_at_a0[0xe0];
2383
2384         struct mlx5_ifc_wq_bits wq;
2385 };
2386
2387 enum {
2388         MLX5_RMPC_STATE_RDY  = 0x1,
2389         MLX5_RMPC_STATE_ERR  = 0x3,
2390 };
2391
2392 struct mlx5_ifc_rmpc_bits {
2393         u8         reserved_at_0[0x8];
2394         u8         state[0x4];
2395         u8         reserved_at_c[0x14];
2396
2397         u8         basic_cyclic_rcv_wqe[0x1];
2398         u8         reserved_at_21[0x1f];
2399
2400         u8         reserved_at_40[0x140];
2401
2402         struct mlx5_ifc_wq_bits wq;
2403 };
2404
2405 struct mlx5_ifc_nic_vport_context_bits {
2406         u8         reserved_at_0[0x5];
2407         u8         min_wqe_inline_mode[0x3];
2408         u8         reserved_at_8[0x17];
2409         u8         roce_en[0x1];
2410
2411         u8         arm_change_event[0x1];
2412         u8         reserved_at_21[0x1a];
2413         u8         event_on_mtu[0x1];
2414         u8         event_on_promisc_change[0x1];
2415         u8         event_on_vlan_change[0x1];
2416         u8         event_on_mc_address_change[0x1];
2417         u8         event_on_uc_address_change[0x1];
2418
2419         u8         reserved_at_40[0xf0];
2420
2421         u8         mtu[0x10];
2422
2423         u8         system_image_guid[0x40];
2424         u8         port_guid[0x40];
2425         u8         node_guid[0x40];
2426
2427         u8         reserved_at_200[0x140];
2428         u8         qkey_violation_counter[0x10];
2429         u8         reserved_at_350[0x430];
2430
2431         u8         promisc_uc[0x1];
2432         u8         promisc_mc[0x1];
2433         u8         promisc_all[0x1];
2434         u8         reserved_at_783[0x2];
2435         u8         allowed_list_type[0x3];
2436         u8         reserved_at_788[0xc];
2437         u8         allowed_list_size[0xc];
2438
2439         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2440
2441         u8         reserved_at_7e0[0x20];
2442
2443         u8         current_uc_mac_address[0][0x40];
2444 };
2445
2446 enum {
2447         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2448         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2449         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2450 };
2451
2452 struct mlx5_ifc_mkc_bits {
2453         u8         reserved_at_0[0x1];
2454         u8         free[0x1];
2455         u8         reserved_at_2[0xd];
2456         u8         small_fence_on_rdma_read_response[0x1];
2457         u8         umr_en[0x1];
2458         u8         a[0x1];
2459         u8         rw[0x1];
2460         u8         rr[0x1];
2461         u8         lw[0x1];
2462         u8         lr[0x1];
2463         u8         access_mode[0x2];
2464         u8         reserved_at_18[0x8];
2465
2466         u8         qpn[0x18];
2467         u8         mkey_7_0[0x8];
2468
2469         u8         reserved_at_40[0x20];
2470
2471         u8         length64[0x1];
2472         u8         bsf_en[0x1];
2473         u8         sync_umr[0x1];
2474         u8         reserved_at_63[0x2];
2475         u8         expected_sigerr_count[0x1];
2476         u8         reserved_at_66[0x1];
2477         u8         en_rinval[0x1];
2478         u8         pd[0x18];
2479
2480         u8         start_addr[0x40];
2481
2482         u8         len[0x40];
2483
2484         u8         bsf_octword_size[0x20];
2485
2486         u8         reserved_at_120[0x80];
2487
2488         u8         translations_octword_size[0x20];
2489
2490         u8         reserved_at_1c0[0x1b];
2491         u8         log_page_size[0x5];
2492
2493         u8         reserved_at_1e0[0x20];
2494 };
2495
2496 struct mlx5_ifc_pkey_bits {
2497         u8         reserved_at_0[0x10];
2498         u8         pkey[0x10];
2499 };
2500
2501 struct mlx5_ifc_array128_auto_bits {
2502         u8         array128_auto[16][0x8];
2503 };
2504
2505 struct mlx5_ifc_hca_vport_context_bits {
2506         u8         field_select[0x20];
2507
2508         u8         reserved_at_20[0xe0];
2509
2510         u8         sm_virt_aware[0x1];
2511         u8         has_smi[0x1];
2512         u8         has_raw[0x1];
2513         u8         grh_required[0x1];
2514         u8         reserved_at_104[0xc];
2515         u8         port_physical_state[0x4];
2516         u8         vport_state_policy[0x4];
2517         u8         port_state[0x4];
2518         u8         vport_state[0x4];
2519
2520         u8         reserved_at_120[0x20];
2521
2522         u8         system_image_guid[0x40];
2523
2524         u8         port_guid[0x40];
2525
2526         u8         node_guid[0x40];
2527
2528         u8         cap_mask1[0x20];
2529
2530         u8         cap_mask1_field_select[0x20];
2531
2532         u8         cap_mask2[0x20];
2533
2534         u8         cap_mask2_field_select[0x20];
2535
2536         u8         reserved_at_280[0x80];
2537
2538         u8         lid[0x10];
2539         u8         reserved_at_310[0x4];
2540         u8         init_type_reply[0x4];
2541         u8         lmc[0x3];
2542         u8         subnet_timeout[0x5];
2543
2544         u8         sm_lid[0x10];
2545         u8         sm_sl[0x4];
2546         u8         reserved_at_334[0xc];
2547
2548         u8         qkey_violation_counter[0x10];
2549         u8         pkey_violation_counter[0x10];
2550
2551         u8         reserved_at_360[0xca0];
2552 };
2553
2554 struct mlx5_ifc_esw_vport_context_bits {
2555         u8         reserved_at_0[0x3];
2556         u8         vport_svlan_strip[0x1];
2557         u8         vport_cvlan_strip[0x1];
2558         u8         vport_svlan_insert[0x1];
2559         u8         vport_cvlan_insert[0x2];
2560         u8         reserved_at_8[0x18];
2561
2562         u8         reserved_at_20[0x20];
2563
2564         u8         svlan_cfi[0x1];
2565         u8         svlan_pcp[0x3];
2566         u8         svlan_id[0xc];
2567         u8         cvlan_cfi[0x1];
2568         u8         cvlan_pcp[0x3];
2569         u8         cvlan_id[0xc];
2570
2571         u8         reserved_at_60[0x7a0];
2572 };
2573
2574 enum {
2575         MLX5_EQC_STATUS_OK                = 0x0,
2576         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2577 };
2578
2579 enum {
2580         MLX5_EQC_ST_ARMED  = 0x9,
2581         MLX5_EQC_ST_FIRED  = 0xa,
2582 };
2583
2584 struct mlx5_ifc_eqc_bits {
2585         u8         status[0x4];
2586         u8         reserved_at_4[0x9];
2587         u8         ec[0x1];
2588         u8         oi[0x1];
2589         u8         reserved_at_f[0x5];
2590         u8         st[0x4];
2591         u8         reserved_at_18[0x8];
2592
2593         u8         reserved_at_20[0x20];
2594
2595         u8         reserved_at_40[0x14];
2596         u8         page_offset[0x6];
2597         u8         reserved_at_5a[0x6];
2598
2599         u8         reserved_at_60[0x3];
2600         u8         log_eq_size[0x5];
2601         u8         uar_page[0x18];
2602
2603         u8         reserved_at_80[0x20];
2604
2605         u8         reserved_at_a0[0x18];
2606         u8         intr[0x8];
2607
2608         u8         reserved_at_c0[0x3];
2609         u8         log_page_size[0x5];
2610         u8         reserved_at_c8[0x18];
2611
2612         u8         reserved_at_e0[0x60];
2613
2614         u8         reserved_at_140[0x8];
2615         u8         consumer_counter[0x18];
2616
2617         u8         reserved_at_160[0x8];
2618         u8         producer_counter[0x18];
2619
2620         u8         reserved_at_180[0x80];
2621 };
2622
2623 enum {
2624         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2625         MLX5_DCTC_STATE_DRAINING  = 0x1,
2626         MLX5_DCTC_STATE_DRAINED   = 0x2,
2627 };
2628
2629 enum {
2630         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2631         MLX5_DCTC_CS_RES_NA         = 0x1,
2632         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2633 };
2634
2635 enum {
2636         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2637         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2638         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2639         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2640         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2641 };
2642
2643 struct mlx5_ifc_dctc_bits {
2644         u8         reserved_at_0[0x4];
2645         u8         state[0x4];
2646         u8         reserved_at_8[0x18];
2647
2648         u8         reserved_at_20[0x8];
2649         u8         user_index[0x18];
2650
2651         u8         reserved_at_40[0x8];
2652         u8         cqn[0x18];
2653
2654         u8         counter_set_id[0x8];
2655         u8         atomic_mode[0x4];
2656         u8         rre[0x1];
2657         u8         rwe[0x1];
2658         u8         rae[0x1];
2659         u8         atomic_like_write_en[0x1];
2660         u8         latency_sensitive[0x1];
2661         u8         rlky[0x1];
2662         u8         free_ar[0x1];
2663         u8         reserved_at_73[0xd];
2664
2665         u8         reserved_at_80[0x8];
2666         u8         cs_res[0x8];
2667         u8         reserved_at_90[0x3];
2668         u8         min_rnr_nak[0x5];
2669         u8         reserved_at_98[0x8];
2670
2671         u8         reserved_at_a0[0x8];
2672         u8         srqn_xrqn[0x18];
2673
2674         u8         reserved_at_c0[0x8];
2675         u8         pd[0x18];
2676
2677         u8         tclass[0x8];
2678         u8         reserved_at_e8[0x4];
2679         u8         flow_label[0x14];
2680
2681         u8         dc_access_key[0x40];
2682
2683         u8         reserved_at_140[0x5];
2684         u8         mtu[0x3];
2685         u8         port[0x8];
2686         u8         pkey_index[0x10];
2687
2688         u8         reserved_at_160[0x8];
2689         u8         my_addr_index[0x8];
2690         u8         reserved_at_170[0x8];
2691         u8         hop_limit[0x8];
2692
2693         u8         dc_access_key_violation_count[0x20];
2694
2695         u8         reserved_at_1a0[0x14];
2696         u8         dei_cfi[0x1];
2697         u8         eth_prio[0x3];
2698         u8         ecn[0x2];
2699         u8         dscp[0x6];
2700
2701         u8         reserved_at_1c0[0x40];
2702 };
2703
2704 enum {
2705         MLX5_CQC_STATUS_OK             = 0x0,
2706         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2707         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2708 };
2709
2710 enum {
2711         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2712         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2713 };
2714
2715 enum {
2716         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2717         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2718         MLX5_CQC_ST_FIRED                                 = 0xa,
2719 };
2720
2721 enum {
2722         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2723         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2724         MLX5_CQ_PERIOD_NUM_MODES
2725 };
2726
2727 struct mlx5_ifc_cqc_bits {
2728         u8         status[0x4];
2729         u8         reserved_at_4[0x4];
2730         u8         cqe_sz[0x3];
2731         u8         cc[0x1];
2732         u8         reserved_at_c[0x1];
2733         u8         scqe_break_moderation_en[0x1];
2734         u8         oi[0x1];
2735         u8         cq_period_mode[0x2];
2736         u8         cqe_comp_en[0x1];
2737         u8         mini_cqe_res_format[0x2];
2738         u8         st[0x4];
2739         u8         reserved_at_18[0x8];
2740
2741         u8         reserved_at_20[0x20];
2742
2743         u8         reserved_at_40[0x14];
2744         u8         page_offset[0x6];
2745         u8         reserved_at_5a[0x6];
2746
2747         u8         reserved_at_60[0x3];
2748         u8         log_cq_size[0x5];
2749         u8         uar_page[0x18];
2750
2751         u8         reserved_at_80[0x4];
2752         u8         cq_period[0xc];
2753         u8         cq_max_count[0x10];
2754
2755         u8         reserved_at_a0[0x18];
2756         u8         c_eqn[0x8];
2757
2758         u8         reserved_at_c0[0x3];
2759         u8         log_page_size[0x5];
2760         u8         reserved_at_c8[0x18];
2761
2762         u8         reserved_at_e0[0x20];
2763
2764         u8         reserved_at_100[0x8];
2765         u8         last_notified_index[0x18];
2766
2767         u8         reserved_at_120[0x8];
2768         u8         last_solicit_index[0x18];
2769
2770         u8         reserved_at_140[0x8];
2771         u8         consumer_counter[0x18];
2772
2773         u8         reserved_at_160[0x8];
2774         u8         producer_counter[0x18];
2775
2776         u8         reserved_at_180[0x40];
2777
2778         u8         dbr_addr[0x40];
2779 };
2780
2781 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2782         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2783         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2784         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2785         u8         reserved_at_0[0x800];
2786 };
2787
2788 struct mlx5_ifc_query_adapter_param_block_bits {
2789         u8         reserved_at_0[0xc0];
2790
2791         u8         reserved_at_c0[0x8];
2792         u8         ieee_vendor_id[0x18];
2793
2794         u8         reserved_at_e0[0x10];
2795         u8         vsd_vendor_id[0x10];
2796
2797         u8         vsd[208][0x8];
2798
2799         u8         vsd_contd_psid[16][0x8];
2800 };
2801
2802 enum {
2803         MLX5_XRQC_STATE_GOOD   = 0x0,
2804         MLX5_XRQC_STATE_ERROR  = 0x1,
2805 };
2806
2807 enum {
2808         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2809         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
2810 };
2811
2812 enum {
2813         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2814 };
2815
2816 struct mlx5_ifc_tag_matching_topology_context_bits {
2817         u8         log_matching_list_sz[0x4];
2818         u8         reserved_at_4[0xc];
2819         u8         append_next_index[0x10];
2820
2821         u8         sw_phase_cnt[0x10];
2822         u8         hw_phase_cnt[0x10];
2823
2824         u8         reserved_at_40[0x40];
2825 };
2826
2827 struct mlx5_ifc_xrqc_bits {
2828         u8         state[0x4];
2829         u8         rlkey[0x1];
2830         u8         reserved_at_5[0xf];
2831         u8         topology[0x4];
2832         u8         reserved_at_18[0x4];
2833         u8         offload[0x4];
2834
2835         u8         reserved_at_20[0x8];
2836         u8         user_index[0x18];
2837
2838         u8         reserved_at_40[0x8];
2839         u8         cqn[0x18];
2840
2841         u8         reserved_at_60[0xa0];
2842
2843         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2844
2845         u8         reserved_at_180[0x200];
2846
2847         struct mlx5_ifc_wq_bits wq;
2848 };
2849
2850 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2851         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2852         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2853         u8         reserved_at_0[0x20];
2854 };
2855
2856 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2857         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2858         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2859         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2860         u8         reserved_at_0[0x20];
2861 };
2862
2863 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2864         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2865         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2866         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2867         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2868         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2869         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2870         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2871         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2872         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2873         u8         reserved_at_0[0x7c0];
2874 };
2875
2876 union mlx5_ifc_event_auto_bits {
2877         struct mlx5_ifc_comp_event_bits comp_event;
2878         struct mlx5_ifc_dct_events_bits dct_events;
2879         struct mlx5_ifc_qp_events_bits qp_events;
2880         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2881         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2882         struct mlx5_ifc_cq_error_bits cq_error;
2883         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2884         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2885         struct mlx5_ifc_gpio_event_bits gpio_event;
2886         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2887         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2888         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2889         u8         reserved_at_0[0xe0];
2890 };
2891
2892 struct mlx5_ifc_health_buffer_bits {
2893         u8         reserved_at_0[0x100];
2894
2895         u8         assert_existptr[0x20];
2896
2897         u8         assert_callra[0x20];
2898
2899         u8         reserved_at_140[0x40];
2900
2901         u8         fw_version[0x20];
2902
2903         u8         hw_id[0x20];
2904
2905         u8         reserved_at_1c0[0x20];
2906
2907         u8         irisc_index[0x8];
2908         u8         synd[0x8];
2909         u8         ext_synd[0x10];
2910 };
2911
2912 struct mlx5_ifc_register_loopback_control_bits {
2913         u8         no_lb[0x1];
2914         u8         reserved_at_1[0x7];
2915         u8         port[0x8];
2916         u8         reserved_at_10[0x10];
2917
2918         u8         reserved_at_20[0x60];
2919 };
2920
2921 struct mlx5_ifc_teardown_hca_out_bits {
2922         u8         status[0x8];
2923         u8         reserved_at_8[0x18];
2924
2925         u8         syndrome[0x20];
2926
2927         u8         reserved_at_40[0x40];
2928 };
2929
2930 enum {
2931         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
2932         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
2933 };
2934
2935 struct mlx5_ifc_teardown_hca_in_bits {
2936         u8         opcode[0x10];
2937         u8         reserved_at_10[0x10];
2938
2939         u8         reserved_at_20[0x10];
2940         u8         op_mod[0x10];
2941
2942         u8         reserved_at_40[0x10];
2943         u8         profile[0x10];
2944
2945         u8         reserved_at_60[0x20];
2946 };
2947
2948 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2949         u8         status[0x8];
2950         u8         reserved_at_8[0x18];
2951
2952         u8         syndrome[0x20];
2953
2954         u8         reserved_at_40[0x40];
2955 };
2956
2957 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2958         u8         opcode[0x10];
2959         u8         reserved_at_10[0x10];
2960
2961         u8         reserved_at_20[0x10];
2962         u8         op_mod[0x10];
2963
2964         u8         reserved_at_40[0x8];
2965         u8         qpn[0x18];
2966
2967         u8         reserved_at_60[0x20];
2968
2969         u8         opt_param_mask[0x20];
2970
2971         u8         reserved_at_a0[0x20];
2972
2973         struct mlx5_ifc_qpc_bits qpc;
2974
2975         u8         reserved_at_800[0x80];
2976 };
2977
2978 struct mlx5_ifc_sqd2rts_qp_out_bits {
2979         u8         status[0x8];
2980         u8         reserved_at_8[0x18];
2981
2982         u8         syndrome[0x20];
2983
2984         u8         reserved_at_40[0x40];
2985 };
2986
2987 struct mlx5_ifc_sqd2rts_qp_in_bits {
2988         u8         opcode[0x10];
2989         u8         reserved_at_10[0x10];
2990
2991         u8         reserved_at_20[0x10];
2992         u8         op_mod[0x10];
2993
2994         u8         reserved_at_40[0x8];
2995         u8         qpn[0x18];
2996
2997         u8         reserved_at_60[0x20];
2998
2999         u8         opt_param_mask[0x20];
3000
3001         u8         reserved_at_a0[0x20];
3002
3003         struct mlx5_ifc_qpc_bits qpc;
3004
3005         u8         reserved_at_800[0x80];
3006 };
3007
3008 struct mlx5_ifc_set_roce_address_out_bits {
3009         u8         status[0x8];
3010         u8         reserved_at_8[0x18];
3011
3012         u8         syndrome[0x20];
3013
3014         u8         reserved_at_40[0x40];
3015 };
3016
3017 struct mlx5_ifc_set_roce_address_in_bits {
3018         u8         opcode[0x10];
3019         u8         reserved_at_10[0x10];
3020
3021         u8         reserved_at_20[0x10];
3022         u8         op_mod[0x10];
3023
3024         u8         roce_address_index[0x10];
3025         u8         reserved_at_50[0x10];
3026
3027         u8         reserved_at_60[0x20];
3028
3029         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3030 };
3031
3032 struct mlx5_ifc_set_mad_demux_out_bits {
3033         u8         status[0x8];
3034         u8         reserved_at_8[0x18];
3035
3036         u8         syndrome[0x20];
3037
3038         u8         reserved_at_40[0x40];
3039 };
3040
3041 enum {
3042         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3043         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3044 };
3045
3046 struct mlx5_ifc_set_mad_demux_in_bits {
3047         u8         opcode[0x10];
3048         u8         reserved_at_10[0x10];
3049
3050         u8         reserved_at_20[0x10];
3051         u8         op_mod[0x10];
3052
3053         u8         reserved_at_40[0x20];
3054
3055         u8         reserved_at_60[0x6];
3056         u8         demux_mode[0x2];
3057         u8         reserved_at_68[0x18];
3058 };
3059
3060 struct mlx5_ifc_set_l2_table_entry_out_bits {
3061         u8         status[0x8];
3062         u8         reserved_at_8[0x18];
3063
3064         u8         syndrome[0x20];
3065
3066         u8         reserved_at_40[0x40];
3067 };
3068
3069 struct mlx5_ifc_set_l2_table_entry_in_bits {
3070         u8         opcode[0x10];
3071         u8         reserved_at_10[0x10];
3072
3073         u8         reserved_at_20[0x10];
3074         u8         op_mod[0x10];
3075
3076         u8         reserved_at_40[0x60];
3077
3078         u8         reserved_at_a0[0x8];
3079         u8         table_index[0x18];
3080
3081         u8         reserved_at_c0[0x20];
3082
3083         u8         reserved_at_e0[0x13];
3084         u8         vlan_valid[0x1];
3085         u8         vlan[0xc];
3086
3087         struct mlx5_ifc_mac_address_layout_bits mac_address;
3088
3089         u8         reserved_at_140[0xc0];
3090 };
3091
3092 struct mlx5_ifc_set_issi_out_bits {
3093         u8         status[0x8];
3094         u8         reserved_at_8[0x18];
3095
3096         u8         syndrome[0x20];
3097
3098         u8         reserved_at_40[0x40];
3099 };
3100
3101 struct mlx5_ifc_set_issi_in_bits {
3102         u8         opcode[0x10];
3103         u8         reserved_at_10[0x10];
3104
3105         u8         reserved_at_20[0x10];
3106         u8         op_mod[0x10];
3107
3108         u8         reserved_at_40[0x10];
3109         u8         current_issi[0x10];
3110
3111         u8         reserved_at_60[0x20];
3112 };
3113
3114 struct mlx5_ifc_set_hca_cap_out_bits {
3115         u8         status[0x8];
3116         u8         reserved_at_8[0x18];
3117
3118         u8         syndrome[0x20];
3119
3120         u8         reserved_at_40[0x40];
3121 };
3122
3123 struct mlx5_ifc_set_hca_cap_in_bits {
3124         u8         opcode[0x10];
3125         u8         reserved_at_10[0x10];
3126
3127         u8         reserved_at_20[0x10];
3128         u8         op_mod[0x10];
3129
3130         u8         reserved_at_40[0x40];
3131
3132         union mlx5_ifc_hca_cap_union_bits capability;
3133 };
3134
3135 enum {
3136         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3137         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3138         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3139         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3140 };
3141
3142 struct mlx5_ifc_set_fte_out_bits {
3143         u8         status[0x8];
3144         u8         reserved_at_8[0x18];
3145
3146         u8         syndrome[0x20];
3147
3148         u8         reserved_at_40[0x40];
3149 };
3150
3151 struct mlx5_ifc_set_fte_in_bits {
3152         u8         opcode[0x10];
3153         u8         reserved_at_10[0x10];
3154
3155         u8         reserved_at_20[0x10];
3156         u8         op_mod[0x10];
3157
3158         u8         other_vport[0x1];
3159         u8         reserved_at_41[0xf];
3160         u8         vport_number[0x10];
3161
3162         u8         reserved_at_60[0x20];
3163
3164         u8         table_type[0x8];
3165         u8         reserved_at_88[0x18];
3166
3167         u8         reserved_at_a0[0x8];
3168         u8         table_id[0x18];
3169
3170         u8         reserved_at_c0[0x18];
3171         u8         modify_enable_mask[0x8];
3172
3173         u8         reserved_at_e0[0x20];
3174
3175         u8         flow_index[0x20];
3176
3177         u8         reserved_at_120[0xe0];
3178
3179         struct mlx5_ifc_flow_context_bits flow_context;
3180 };
3181
3182 struct mlx5_ifc_rts2rts_qp_out_bits {
3183         u8         status[0x8];
3184         u8         reserved_at_8[0x18];
3185
3186         u8         syndrome[0x20];
3187
3188         u8         reserved_at_40[0x40];
3189 };
3190
3191 struct mlx5_ifc_rts2rts_qp_in_bits {
3192         u8         opcode[0x10];
3193         u8         reserved_at_10[0x10];
3194
3195         u8         reserved_at_20[0x10];
3196         u8         op_mod[0x10];
3197
3198         u8         reserved_at_40[0x8];
3199         u8         qpn[0x18];
3200
3201         u8         reserved_at_60[0x20];
3202
3203         u8         opt_param_mask[0x20];
3204
3205         u8         reserved_at_a0[0x20];
3206
3207         struct mlx5_ifc_qpc_bits qpc;
3208
3209         u8         reserved_at_800[0x80];
3210 };
3211
3212 struct mlx5_ifc_rtr2rts_qp_out_bits {
3213         u8         status[0x8];
3214         u8         reserved_at_8[0x18];
3215
3216         u8         syndrome[0x20];
3217
3218         u8         reserved_at_40[0x40];
3219 };
3220
3221 struct mlx5_ifc_rtr2rts_qp_in_bits {
3222         u8         opcode[0x10];
3223         u8         reserved_at_10[0x10];
3224
3225         u8         reserved_at_20[0x10];
3226         u8         op_mod[0x10];
3227
3228         u8         reserved_at_40[0x8];
3229         u8         qpn[0x18];
3230
3231         u8         reserved_at_60[0x20];
3232
3233         u8         opt_param_mask[0x20];
3234
3235         u8         reserved_at_a0[0x20];
3236
3237         struct mlx5_ifc_qpc_bits qpc;
3238
3239         u8         reserved_at_800[0x80];
3240 };
3241
3242 struct mlx5_ifc_rst2init_qp_out_bits {
3243         u8         status[0x8];
3244         u8         reserved_at_8[0x18];
3245
3246         u8         syndrome[0x20];
3247
3248         u8         reserved_at_40[0x40];
3249 };
3250
3251 struct mlx5_ifc_rst2init_qp_in_bits {
3252         u8         opcode[0x10];
3253         u8         reserved_at_10[0x10];
3254
3255         u8         reserved_at_20[0x10];
3256         u8         op_mod[0x10];
3257
3258         u8         reserved_at_40[0x8];
3259         u8         qpn[0x18];
3260
3261         u8         reserved_at_60[0x20];
3262
3263         u8         opt_param_mask[0x20];
3264
3265         u8         reserved_at_a0[0x20];
3266
3267         struct mlx5_ifc_qpc_bits qpc;
3268
3269         u8         reserved_at_800[0x80];
3270 };
3271
3272 struct mlx5_ifc_query_xrq_out_bits {
3273         u8         status[0x8];
3274         u8         reserved_at_8[0x18];
3275
3276         u8         syndrome[0x20];
3277
3278         u8         reserved_at_40[0x40];
3279
3280         struct mlx5_ifc_xrqc_bits xrq_context;
3281 };
3282
3283 struct mlx5_ifc_query_xrq_in_bits {
3284         u8         opcode[0x10];
3285         u8         reserved_at_10[0x10];
3286
3287         u8         reserved_at_20[0x10];
3288         u8         op_mod[0x10];
3289
3290         u8         reserved_at_40[0x8];
3291         u8         xrqn[0x18];
3292
3293         u8         reserved_at_60[0x20];
3294 };
3295
3296 struct mlx5_ifc_query_xrc_srq_out_bits {
3297         u8         status[0x8];
3298         u8         reserved_at_8[0x18];
3299
3300         u8         syndrome[0x20];
3301
3302         u8         reserved_at_40[0x40];
3303
3304         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3305
3306         u8         reserved_at_280[0x600];
3307
3308         u8         pas[0][0x40];
3309 };
3310
3311 struct mlx5_ifc_query_xrc_srq_in_bits {
3312         u8         opcode[0x10];
3313         u8         reserved_at_10[0x10];
3314
3315         u8         reserved_at_20[0x10];
3316         u8         op_mod[0x10];
3317
3318         u8         reserved_at_40[0x8];
3319         u8         xrc_srqn[0x18];
3320
3321         u8         reserved_at_60[0x20];
3322 };
3323
3324 enum {
3325         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3326         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3327 };
3328
3329 struct mlx5_ifc_query_vport_state_out_bits {
3330         u8         status[0x8];
3331         u8         reserved_at_8[0x18];
3332
3333         u8         syndrome[0x20];
3334
3335         u8         reserved_at_40[0x20];
3336
3337         u8         reserved_at_60[0x18];
3338         u8         admin_state[0x4];
3339         u8         state[0x4];
3340 };
3341
3342 enum {
3343         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3344         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3345 };
3346
3347 struct mlx5_ifc_query_vport_state_in_bits {
3348         u8         opcode[0x10];
3349         u8         reserved_at_10[0x10];
3350
3351         u8         reserved_at_20[0x10];
3352         u8         op_mod[0x10];
3353
3354         u8         other_vport[0x1];
3355         u8         reserved_at_41[0xf];
3356         u8         vport_number[0x10];
3357
3358         u8         reserved_at_60[0x20];
3359 };
3360
3361 struct mlx5_ifc_query_vport_counter_out_bits {
3362         u8         status[0x8];
3363         u8         reserved_at_8[0x18];
3364
3365         u8         syndrome[0x20];
3366
3367         u8         reserved_at_40[0x40];
3368
3369         struct mlx5_ifc_traffic_counter_bits received_errors;
3370
3371         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3372
3373         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3374
3375         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3376
3377         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3378
3379         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3380
3381         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3382
3383         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3384
3385         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3386
3387         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3388
3389         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3390
3391         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3392
3393         u8         reserved_at_680[0xa00];
3394 };
3395
3396 enum {
3397         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3398 };
3399
3400 struct mlx5_ifc_query_vport_counter_in_bits {
3401         u8         opcode[0x10];
3402         u8         reserved_at_10[0x10];
3403
3404         u8         reserved_at_20[0x10];
3405         u8         op_mod[0x10];
3406
3407         u8         other_vport[0x1];
3408         u8         reserved_at_41[0xb];
3409         u8         port_num[0x4];
3410         u8         vport_number[0x10];
3411
3412         u8         reserved_at_60[0x60];
3413
3414         u8         clear[0x1];
3415         u8         reserved_at_c1[0x1f];
3416
3417         u8         reserved_at_e0[0x20];
3418 };
3419
3420 struct mlx5_ifc_query_tis_out_bits {
3421         u8         status[0x8];
3422         u8         reserved_at_8[0x18];
3423
3424         u8         syndrome[0x20];
3425
3426         u8         reserved_at_40[0x40];
3427
3428         struct mlx5_ifc_tisc_bits tis_context;
3429 };
3430
3431 struct mlx5_ifc_query_tis_in_bits {
3432         u8         opcode[0x10];
3433         u8         reserved_at_10[0x10];
3434
3435         u8         reserved_at_20[0x10];
3436         u8         op_mod[0x10];
3437
3438         u8         reserved_at_40[0x8];
3439         u8         tisn[0x18];
3440
3441         u8         reserved_at_60[0x20];
3442 };
3443
3444 struct mlx5_ifc_query_tir_out_bits {
3445         u8         status[0x8];
3446         u8         reserved_at_8[0x18];
3447
3448         u8         syndrome[0x20];
3449
3450         u8         reserved_at_40[0xc0];
3451
3452         struct mlx5_ifc_tirc_bits tir_context;
3453 };
3454
3455 struct mlx5_ifc_query_tir_in_bits {
3456         u8         opcode[0x10];
3457         u8         reserved_at_10[0x10];
3458
3459         u8         reserved_at_20[0x10];
3460         u8         op_mod[0x10];
3461
3462         u8         reserved_at_40[0x8];
3463         u8         tirn[0x18];
3464
3465         u8         reserved_at_60[0x20];
3466 };
3467
3468 struct mlx5_ifc_query_srq_out_bits {
3469         u8         status[0x8];
3470         u8         reserved_at_8[0x18];
3471
3472         u8         syndrome[0x20];
3473
3474         u8         reserved_at_40[0x40];
3475
3476         struct mlx5_ifc_srqc_bits srq_context_entry;
3477
3478         u8         reserved_at_280[0x600];
3479
3480         u8         pas[0][0x40];
3481 };
3482
3483 struct mlx5_ifc_query_srq_in_bits {
3484         u8         opcode[0x10];
3485         u8         reserved_at_10[0x10];
3486
3487         u8         reserved_at_20[0x10];
3488         u8         op_mod[0x10];
3489
3490         u8         reserved_at_40[0x8];
3491         u8         srqn[0x18];
3492
3493         u8         reserved_at_60[0x20];
3494 };
3495
3496 struct mlx5_ifc_query_sq_out_bits {
3497         u8         status[0x8];
3498         u8         reserved_at_8[0x18];
3499
3500         u8         syndrome[0x20];
3501
3502         u8         reserved_at_40[0xc0];
3503
3504         struct mlx5_ifc_sqc_bits sq_context;
3505 };
3506
3507 struct mlx5_ifc_query_sq_in_bits {
3508         u8         opcode[0x10];
3509         u8         reserved_at_10[0x10];
3510
3511         u8         reserved_at_20[0x10];
3512         u8         op_mod[0x10];
3513
3514         u8         reserved_at_40[0x8];
3515         u8         sqn[0x18];
3516
3517         u8         reserved_at_60[0x20];
3518 };
3519
3520 struct mlx5_ifc_query_special_contexts_out_bits {
3521         u8         status[0x8];
3522         u8         reserved_at_8[0x18];
3523
3524         u8         syndrome[0x20];
3525
3526         u8         dump_fill_mkey[0x20];
3527
3528         u8         resd_lkey[0x20];
3529 };
3530
3531 struct mlx5_ifc_query_special_contexts_in_bits {
3532         u8         opcode[0x10];
3533         u8         reserved_at_10[0x10];
3534
3535         u8         reserved_at_20[0x10];
3536         u8         op_mod[0x10];
3537
3538         u8         reserved_at_40[0x40];
3539 };
3540
3541 struct mlx5_ifc_query_rqt_out_bits {
3542         u8         status[0x8];
3543         u8         reserved_at_8[0x18];
3544
3545         u8         syndrome[0x20];
3546
3547         u8         reserved_at_40[0xc0];
3548
3549         struct mlx5_ifc_rqtc_bits rqt_context;
3550 };
3551
3552 struct mlx5_ifc_query_rqt_in_bits {
3553         u8         opcode[0x10];
3554         u8         reserved_at_10[0x10];
3555
3556         u8         reserved_at_20[0x10];
3557         u8         op_mod[0x10];
3558
3559         u8         reserved_at_40[0x8];
3560         u8         rqtn[0x18];
3561
3562         u8         reserved_at_60[0x20];
3563 };
3564
3565 struct mlx5_ifc_query_rq_out_bits {
3566         u8         status[0x8];
3567         u8         reserved_at_8[0x18];
3568
3569         u8         syndrome[0x20];
3570
3571         u8         reserved_at_40[0xc0];
3572
3573         struct mlx5_ifc_rqc_bits rq_context;
3574 };
3575
3576 struct mlx5_ifc_query_rq_in_bits {
3577         u8         opcode[0x10];
3578         u8         reserved_at_10[0x10];
3579
3580         u8         reserved_at_20[0x10];
3581         u8         op_mod[0x10];
3582
3583         u8         reserved_at_40[0x8];
3584         u8         rqn[0x18];
3585
3586         u8         reserved_at_60[0x20];
3587 };
3588
3589 struct mlx5_ifc_query_roce_address_out_bits {
3590         u8         status[0x8];
3591         u8         reserved_at_8[0x18];
3592
3593         u8         syndrome[0x20];
3594
3595         u8         reserved_at_40[0x40];
3596
3597         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3598 };
3599
3600 struct mlx5_ifc_query_roce_address_in_bits {
3601         u8         opcode[0x10];
3602         u8         reserved_at_10[0x10];
3603
3604         u8         reserved_at_20[0x10];
3605         u8         op_mod[0x10];
3606
3607         u8         roce_address_index[0x10];
3608         u8         reserved_at_50[0x10];
3609
3610         u8         reserved_at_60[0x20];
3611 };
3612
3613 struct mlx5_ifc_query_rmp_out_bits {
3614         u8         status[0x8];
3615         u8         reserved_at_8[0x18];
3616
3617         u8         syndrome[0x20];
3618
3619         u8         reserved_at_40[0xc0];
3620
3621         struct mlx5_ifc_rmpc_bits rmp_context;
3622 };
3623
3624 struct mlx5_ifc_query_rmp_in_bits {
3625         u8         opcode[0x10];
3626         u8         reserved_at_10[0x10];
3627
3628         u8         reserved_at_20[0x10];
3629         u8         op_mod[0x10];
3630
3631         u8         reserved_at_40[0x8];
3632         u8         rmpn[0x18];
3633
3634         u8         reserved_at_60[0x20];
3635 };
3636
3637 struct mlx5_ifc_query_qp_out_bits {
3638         u8         status[0x8];
3639         u8         reserved_at_8[0x18];
3640
3641         u8         syndrome[0x20];
3642
3643         u8         reserved_at_40[0x40];
3644
3645         u8         opt_param_mask[0x20];
3646
3647         u8         reserved_at_a0[0x20];
3648
3649         struct mlx5_ifc_qpc_bits qpc;
3650
3651         u8         reserved_at_800[0x80];
3652
3653         u8         pas[0][0x40];
3654 };
3655
3656 struct mlx5_ifc_query_qp_in_bits {
3657         u8         opcode[0x10];
3658         u8         reserved_at_10[0x10];
3659
3660         u8         reserved_at_20[0x10];
3661         u8         op_mod[0x10];
3662
3663         u8         reserved_at_40[0x8];
3664         u8         qpn[0x18];
3665
3666         u8         reserved_at_60[0x20];
3667 };
3668
3669 struct mlx5_ifc_query_q_counter_out_bits {
3670         u8         status[0x8];
3671         u8         reserved_at_8[0x18];
3672
3673         u8         syndrome[0x20];
3674
3675         u8         reserved_at_40[0x40];
3676
3677         u8         rx_write_requests[0x20];
3678
3679         u8         reserved_at_a0[0x20];
3680
3681         u8         rx_read_requests[0x20];
3682
3683         u8         reserved_at_e0[0x20];
3684
3685         u8         rx_atomic_requests[0x20];
3686
3687         u8         reserved_at_120[0x20];
3688
3689         u8         rx_dct_connect[0x20];
3690
3691         u8         reserved_at_160[0x20];
3692
3693         u8         out_of_buffer[0x20];
3694
3695         u8         reserved_at_1a0[0x20];
3696
3697         u8         out_of_sequence[0x20];
3698
3699         u8         reserved_at_1e0[0x20];
3700
3701         u8         duplicate_request[0x20];
3702
3703         u8         reserved_at_220[0x20];
3704
3705         u8         rnr_nak_retry_err[0x20];
3706
3707         u8         reserved_at_260[0x20];
3708
3709         u8         packet_seq_err[0x20];
3710
3711         u8         reserved_at_2a0[0x20];
3712
3713         u8         implied_nak_seq_err[0x20];
3714
3715         u8         reserved_at_2e0[0x20];
3716
3717         u8         local_ack_timeout_err[0x20];
3718
3719         u8         reserved_at_320[0x4e0];
3720 };
3721
3722 struct mlx5_ifc_query_q_counter_in_bits {
3723         u8         opcode[0x10];
3724         u8         reserved_at_10[0x10];
3725
3726         u8         reserved_at_20[0x10];
3727         u8         op_mod[0x10];
3728
3729         u8         reserved_at_40[0x80];
3730
3731         u8         clear[0x1];
3732         u8         reserved_at_c1[0x1f];
3733
3734         u8         reserved_at_e0[0x18];
3735         u8         counter_set_id[0x8];
3736 };
3737
3738 struct mlx5_ifc_query_pages_out_bits {
3739         u8         status[0x8];
3740         u8         reserved_at_8[0x18];
3741
3742         u8         syndrome[0x20];
3743
3744         u8         reserved_at_40[0x10];
3745         u8         function_id[0x10];
3746
3747         u8         num_pages[0x20];
3748 };
3749
3750 enum {
3751         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3752         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3753         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3754 };
3755
3756 struct mlx5_ifc_query_pages_in_bits {
3757         u8         opcode[0x10];
3758         u8         reserved_at_10[0x10];
3759
3760         u8         reserved_at_20[0x10];
3761         u8         op_mod[0x10];
3762
3763         u8         reserved_at_40[0x10];
3764         u8         function_id[0x10];
3765
3766         u8         reserved_at_60[0x20];
3767 };
3768
3769 struct mlx5_ifc_query_nic_vport_context_out_bits {
3770         u8         status[0x8];
3771         u8         reserved_at_8[0x18];
3772
3773         u8         syndrome[0x20];
3774
3775         u8         reserved_at_40[0x40];
3776
3777         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3778 };
3779
3780 struct mlx5_ifc_query_nic_vport_context_in_bits {
3781         u8         opcode[0x10];
3782         u8         reserved_at_10[0x10];
3783
3784         u8         reserved_at_20[0x10];
3785         u8         op_mod[0x10];
3786
3787         u8         other_vport[0x1];
3788         u8         reserved_at_41[0xf];
3789         u8         vport_number[0x10];
3790
3791         u8         reserved_at_60[0x5];
3792         u8         allowed_list_type[0x3];
3793         u8         reserved_at_68[0x18];
3794 };
3795
3796 struct mlx5_ifc_query_mkey_out_bits {
3797         u8         status[0x8];
3798         u8         reserved_at_8[0x18];
3799
3800         u8         syndrome[0x20];
3801
3802         u8         reserved_at_40[0x40];
3803
3804         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3805
3806         u8         reserved_at_280[0x600];
3807
3808         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3809
3810         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3811 };
3812
3813 struct mlx5_ifc_query_mkey_in_bits {
3814         u8         opcode[0x10];
3815         u8         reserved_at_10[0x10];
3816
3817         u8         reserved_at_20[0x10];
3818         u8         op_mod[0x10];
3819
3820         u8         reserved_at_40[0x8];
3821         u8         mkey_index[0x18];
3822
3823         u8         pg_access[0x1];
3824         u8         reserved_at_61[0x1f];
3825 };
3826
3827 struct mlx5_ifc_query_mad_demux_out_bits {
3828         u8         status[0x8];
3829         u8         reserved_at_8[0x18];
3830
3831         u8         syndrome[0x20];
3832
3833         u8         reserved_at_40[0x40];
3834
3835         u8         mad_dumux_parameters_block[0x20];
3836 };
3837
3838 struct mlx5_ifc_query_mad_demux_in_bits {
3839         u8         opcode[0x10];
3840         u8         reserved_at_10[0x10];
3841
3842         u8         reserved_at_20[0x10];
3843         u8         op_mod[0x10];
3844
3845         u8         reserved_at_40[0x40];
3846 };
3847
3848 struct mlx5_ifc_query_l2_table_entry_out_bits {
3849         u8         status[0x8];
3850         u8         reserved_at_8[0x18];
3851
3852         u8         syndrome[0x20];
3853
3854         u8         reserved_at_40[0xa0];
3855
3856         u8         reserved_at_e0[0x13];
3857         u8         vlan_valid[0x1];
3858         u8         vlan[0xc];
3859
3860         struct mlx5_ifc_mac_address_layout_bits mac_address;
3861
3862         u8         reserved_at_140[0xc0];
3863 };
3864
3865 struct mlx5_ifc_query_l2_table_entry_in_bits {
3866         u8         opcode[0x10];
3867         u8         reserved_at_10[0x10];
3868
3869         u8         reserved_at_20[0x10];
3870         u8         op_mod[0x10];
3871
3872         u8         reserved_at_40[0x60];
3873
3874         u8         reserved_at_a0[0x8];
3875         u8         table_index[0x18];
3876
3877         u8         reserved_at_c0[0x140];
3878 };
3879
3880 struct mlx5_ifc_query_issi_out_bits {
3881         u8         status[0x8];
3882         u8         reserved_at_8[0x18];
3883
3884         u8         syndrome[0x20];
3885
3886         u8         reserved_at_40[0x10];
3887         u8         current_issi[0x10];
3888
3889         u8         reserved_at_60[0xa0];
3890
3891         u8         reserved_at_100[76][0x8];
3892         u8         supported_issi_dw0[0x20];
3893 };
3894
3895 struct mlx5_ifc_query_issi_in_bits {
3896         u8         opcode[0x10];
3897         u8         reserved_at_10[0x10];
3898
3899         u8         reserved_at_20[0x10];
3900         u8         op_mod[0x10];
3901
3902         u8         reserved_at_40[0x40];
3903 };
3904
3905 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3906         u8         status[0x8];
3907         u8         reserved_at_8[0x18];
3908
3909         u8         syndrome[0x20];
3910
3911         u8         reserved_at_40[0x40];
3912
3913         struct mlx5_ifc_pkey_bits pkey[0];
3914 };
3915
3916 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3917         u8         opcode[0x10];
3918         u8         reserved_at_10[0x10];
3919
3920         u8         reserved_at_20[0x10];
3921         u8         op_mod[0x10];
3922
3923         u8         other_vport[0x1];
3924         u8         reserved_at_41[0xb];
3925         u8         port_num[0x4];
3926         u8         vport_number[0x10];
3927
3928         u8         reserved_at_60[0x10];
3929         u8         pkey_index[0x10];
3930 };
3931
3932 enum {
3933         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
3934         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
3935         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
3936 };
3937
3938 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3939         u8         status[0x8];
3940         u8         reserved_at_8[0x18];
3941
3942         u8         syndrome[0x20];
3943
3944         u8         reserved_at_40[0x20];
3945
3946         u8         gids_num[0x10];
3947         u8         reserved_at_70[0x10];
3948
3949         struct mlx5_ifc_array128_auto_bits gid[0];
3950 };
3951
3952 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3953         u8         opcode[0x10];
3954         u8         reserved_at_10[0x10];
3955
3956         u8         reserved_at_20[0x10];
3957         u8         op_mod[0x10];
3958
3959         u8         other_vport[0x1];
3960         u8         reserved_at_41[0xb];
3961         u8         port_num[0x4];
3962         u8         vport_number[0x10];
3963
3964         u8         reserved_at_60[0x10];
3965         u8         gid_index[0x10];
3966 };
3967
3968 struct mlx5_ifc_query_hca_vport_context_out_bits {
3969         u8         status[0x8];
3970         u8         reserved_at_8[0x18];
3971
3972         u8         syndrome[0x20];
3973
3974         u8         reserved_at_40[0x40];
3975
3976         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3977 };
3978
3979 struct mlx5_ifc_query_hca_vport_context_in_bits {
3980         u8         opcode[0x10];
3981         u8         reserved_at_10[0x10];
3982
3983         u8         reserved_at_20[0x10];
3984         u8         op_mod[0x10];
3985
3986         u8         other_vport[0x1];
3987         u8         reserved_at_41[0xb];
3988         u8         port_num[0x4];
3989         u8         vport_number[0x10];
3990
3991         u8         reserved_at_60[0x20];
3992 };
3993
3994 struct mlx5_ifc_query_hca_cap_out_bits {
3995         u8         status[0x8];
3996         u8         reserved_at_8[0x18];
3997
3998         u8         syndrome[0x20];
3999
4000         u8         reserved_at_40[0x40];
4001
4002         union mlx5_ifc_hca_cap_union_bits capability;
4003 };
4004
4005 struct mlx5_ifc_query_hca_cap_in_bits {
4006         u8         opcode[0x10];
4007         u8         reserved_at_10[0x10];
4008
4009         u8         reserved_at_20[0x10];
4010         u8         op_mod[0x10];
4011
4012         u8         reserved_at_40[0x40];
4013 };
4014
4015 struct mlx5_ifc_query_flow_table_out_bits {
4016         u8         status[0x8];
4017         u8         reserved_at_8[0x18];
4018
4019         u8         syndrome[0x20];
4020
4021         u8         reserved_at_40[0x80];
4022
4023         u8         reserved_at_c0[0x8];
4024         u8         level[0x8];
4025         u8         reserved_at_d0[0x8];
4026         u8         log_size[0x8];
4027
4028         u8         reserved_at_e0[0x120];
4029 };
4030
4031 struct mlx5_ifc_query_flow_table_in_bits {
4032         u8         opcode[0x10];
4033         u8         reserved_at_10[0x10];
4034
4035         u8         reserved_at_20[0x10];
4036         u8         op_mod[0x10];
4037
4038         u8         reserved_at_40[0x40];
4039
4040         u8         table_type[0x8];
4041         u8         reserved_at_88[0x18];
4042
4043         u8         reserved_at_a0[0x8];
4044         u8         table_id[0x18];
4045
4046         u8         reserved_at_c0[0x140];
4047 };
4048
4049 struct mlx5_ifc_query_fte_out_bits {
4050         u8         status[0x8];
4051         u8         reserved_at_8[0x18];
4052
4053         u8         syndrome[0x20];
4054
4055         u8         reserved_at_40[0x1c0];
4056
4057         struct mlx5_ifc_flow_context_bits flow_context;
4058 };
4059
4060 struct mlx5_ifc_query_fte_in_bits {
4061         u8         opcode[0x10];
4062         u8         reserved_at_10[0x10];
4063
4064         u8         reserved_at_20[0x10];
4065         u8         op_mod[0x10];
4066
4067         u8         reserved_at_40[0x40];
4068
4069         u8         table_type[0x8];
4070         u8         reserved_at_88[0x18];
4071
4072         u8         reserved_at_a0[0x8];
4073         u8         table_id[0x18];
4074
4075         u8         reserved_at_c0[0x40];
4076
4077         u8         flow_index[0x20];
4078
4079         u8         reserved_at_120[0xe0];
4080 };
4081
4082 enum {
4083         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4084         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4085         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4086 };
4087
4088 struct mlx5_ifc_query_flow_group_out_bits {
4089         u8         status[0x8];
4090         u8         reserved_at_8[0x18];
4091
4092         u8         syndrome[0x20];
4093
4094         u8         reserved_at_40[0xa0];
4095
4096         u8         start_flow_index[0x20];
4097
4098         u8         reserved_at_100[0x20];
4099
4100         u8         end_flow_index[0x20];
4101
4102         u8         reserved_at_140[0xa0];
4103
4104         u8         reserved_at_1e0[0x18];
4105         u8         match_criteria_enable[0x8];
4106
4107         struct mlx5_ifc_fte_match_param_bits match_criteria;
4108
4109         u8         reserved_at_1200[0xe00];
4110 };
4111
4112 struct mlx5_ifc_query_flow_group_in_bits {
4113         u8         opcode[0x10];
4114         u8         reserved_at_10[0x10];
4115
4116         u8         reserved_at_20[0x10];
4117         u8         op_mod[0x10];
4118
4119         u8         reserved_at_40[0x40];
4120
4121         u8         table_type[0x8];
4122         u8         reserved_at_88[0x18];
4123
4124         u8         reserved_at_a0[0x8];
4125         u8         table_id[0x18];
4126
4127         u8         group_id[0x20];
4128
4129         u8         reserved_at_e0[0x120];
4130 };
4131
4132 struct mlx5_ifc_query_flow_counter_out_bits {
4133         u8         status[0x8];
4134         u8         reserved_at_8[0x18];
4135
4136         u8         syndrome[0x20];
4137
4138         u8         reserved_at_40[0x40];
4139
4140         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4141 };
4142
4143 struct mlx5_ifc_query_flow_counter_in_bits {
4144         u8         opcode[0x10];
4145         u8         reserved_at_10[0x10];
4146
4147         u8         reserved_at_20[0x10];
4148         u8         op_mod[0x10];
4149
4150         u8         reserved_at_40[0x80];
4151
4152         u8         clear[0x1];
4153         u8         reserved_at_c1[0xf];
4154         u8         num_of_counters[0x10];
4155
4156         u8         reserved_at_e0[0x10];
4157         u8         flow_counter_id[0x10];
4158 };
4159
4160 struct mlx5_ifc_query_esw_vport_context_out_bits {
4161         u8         status[0x8];
4162         u8         reserved_at_8[0x18];
4163
4164         u8         syndrome[0x20];
4165
4166         u8         reserved_at_40[0x40];
4167
4168         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4169 };
4170
4171 struct mlx5_ifc_query_esw_vport_context_in_bits {
4172         u8         opcode[0x10];
4173         u8         reserved_at_10[0x10];
4174
4175         u8         reserved_at_20[0x10];
4176         u8         op_mod[0x10];
4177
4178         u8         other_vport[0x1];
4179         u8         reserved_at_41[0xf];
4180         u8         vport_number[0x10];
4181
4182         u8         reserved_at_60[0x20];
4183 };
4184
4185 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4186         u8         status[0x8];
4187         u8         reserved_at_8[0x18];
4188
4189         u8         syndrome[0x20];
4190
4191         u8         reserved_at_40[0x40];
4192 };
4193
4194 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4195         u8         reserved_at_0[0x1c];
4196         u8         vport_cvlan_insert[0x1];
4197         u8         vport_svlan_insert[0x1];
4198         u8         vport_cvlan_strip[0x1];
4199         u8         vport_svlan_strip[0x1];
4200 };
4201
4202 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4203         u8         opcode[0x10];
4204         u8         reserved_at_10[0x10];
4205
4206         u8         reserved_at_20[0x10];
4207         u8         op_mod[0x10];
4208
4209         u8         other_vport[0x1];
4210         u8         reserved_at_41[0xf];
4211         u8         vport_number[0x10];
4212
4213         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4214
4215         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4216 };
4217
4218 struct mlx5_ifc_query_eq_out_bits {
4219         u8         status[0x8];
4220         u8         reserved_at_8[0x18];
4221
4222         u8         syndrome[0x20];
4223
4224         u8         reserved_at_40[0x40];
4225
4226         struct mlx5_ifc_eqc_bits eq_context_entry;
4227
4228         u8         reserved_at_280[0x40];
4229
4230         u8         event_bitmask[0x40];
4231
4232         u8         reserved_at_300[0x580];
4233
4234         u8         pas[0][0x40];
4235 };
4236
4237 struct mlx5_ifc_query_eq_in_bits {
4238         u8         opcode[0x10];
4239         u8         reserved_at_10[0x10];
4240
4241         u8         reserved_at_20[0x10];
4242         u8         op_mod[0x10];
4243
4244         u8         reserved_at_40[0x18];
4245         u8         eq_number[0x8];
4246
4247         u8         reserved_at_60[0x20];
4248 };
4249
4250 struct mlx5_ifc_encap_header_in_bits {
4251         u8         reserved_at_0[0x5];
4252         u8         header_type[0x3];
4253         u8         reserved_at_8[0xe];
4254         u8         encap_header_size[0xa];
4255
4256         u8         reserved_at_20[0x10];
4257         u8         encap_header[2][0x8];
4258
4259         u8         more_encap_header[0][0x8];
4260 };
4261
4262 struct mlx5_ifc_query_encap_header_out_bits {
4263         u8         status[0x8];
4264         u8         reserved_at_8[0x18];
4265
4266         u8         syndrome[0x20];
4267
4268         u8         reserved_at_40[0xa0];
4269
4270         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4271 };
4272
4273 struct mlx5_ifc_query_encap_header_in_bits {
4274         u8         opcode[0x10];
4275         u8         reserved_at_10[0x10];
4276
4277         u8         reserved_at_20[0x10];
4278         u8         op_mod[0x10];
4279
4280         u8         encap_id[0x20];
4281
4282         u8         reserved_at_60[0xa0];
4283 };
4284
4285 struct mlx5_ifc_alloc_encap_header_out_bits {
4286         u8         status[0x8];
4287         u8         reserved_at_8[0x18];
4288
4289         u8         syndrome[0x20];
4290
4291         u8         encap_id[0x20];
4292
4293         u8         reserved_at_60[0x20];
4294 };
4295
4296 struct mlx5_ifc_alloc_encap_header_in_bits {
4297         u8         opcode[0x10];
4298         u8         reserved_at_10[0x10];
4299
4300         u8         reserved_at_20[0x10];
4301         u8         op_mod[0x10];
4302
4303         u8         reserved_at_40[0xa0];
4304
4305         struct mlx5_ifc_encap_header_in_bits encap_header;
4306 };
4307
4308 struct mlx5_ifc_dealloc_encap_header_out_bits {
4309         u8         status[0x8];
4310         u8         reserved_at_8[0x18];
4311
4312         u8         syndrome[0x20];
4313
4314         u8         reserved_at_40[0x40];
4315 };
4316
4317 struct mlx5_ifc_dealloc_encap_header_in_bits {
4318         u8         opcode[0x10];
4319         u8         reserved_at_10[0x10];
4320
4321         u8         reserved_20[0x10];
4322         u8         op_mod[0x10];
4323
4324         u8         encap_id[0x20];
4325
4326         u8         reserved_60[0x20];
4327 };
4328
4329 struct mlx5_ifc_query_dct_out_bits {
4330         u8         status[0x8];
4331         u8         reserved_at_8[0x18];
4332
4333         u8         syndrome[0x20];
4334
4335         u8         reserved_at_40[0x40];
4336
4337         struct mlx5_ifc_dctc_bits dct_context_entry;
4338
4339         u8         reserved_at_280[0x180];
4340 };
4341
4342 struct mlx5_ifc_query_dct_in_bits {
4343         u8         opcode[0x10];
4344         u8         reserved_at_10[0x10];
4345
4346         u8         reserved_at_20[0x10];
4347         u8         op_mod[0x10];
4348
4349         u8         reserved_at_40[0x8];
4350         u8         dctn[0x18];
4351
4352         u8         reserved_at_60[0x20];
4353 };
4354
4355 struct mlx5_ifc_query_cq_out_bits {
4356         u8         status[0x8];
4357         u8         reserved_at_8[0x18];
4358
4359         u8         syndrome[0x20];
4360
4361         u8         reserved_at_40[0x40];
4362
4363         struct mlx5_ifc_cqc_bits cq_context;
4364
4365         u8         reserved_at_280[0x600];
4366
4367         u8         pas[0][0x40];
4368 };
4369
4370 struct mlx5_ifc_query_cq_in_bits {
4371         u8         opcode[0x10];
4372         u8         reserved_at_10[0x10];
4373
4374         u8         reserved_at_20[0x10];
4375         u8         op_mod[0x10];
4376
4377         u8         reserved_at_40[0x8];
4378         u8         cqn[0x18];
4379
4380         u8         reserved_at_60[0x20];
4381 };
4382
4383 struct mlx5_ifc_query_cong_status_out_bits {
4384         u8         status[0x8];
4385         u8         reserved_at_8[0x18];
4386
4387         u8         syndrome[0x20];
4388
4389         u8         reserved_at_40[0x20];
4390
4391         u8         enable[0x1];
4392         u8         tag_enable[0x1];
4393         u8         reserved_at_62[0x1e];
4394 };
4395
4396 struct mlx5_ifc_query_cong_status_in_bits {
4397         u8         opcode[0x10];
4398         u8         reserved_at_10[0x10];
4399
4400         u8         reserved_at_20[0x10];
4401         u8         op_mod[0x10];
4402
4403         u8         reserved_at_40[0x18];
4404         u8         priority[0x4];
4405         u8         cong_protocol[0x4];
4406
4407         u8         reserved_at_60[0x20];
4408 };
4409
4410 struct mlx5_ifc_query_cong_statistics_out_bits {
4411         u8         status[0x8];
4412         u8         reserved_at_8[0x18];
4413
4414         u8         syndrome[0x20];
4415
4416         u8         reserved_at_40[0x40];
4417
4418         u8         cur_flows[0x20];
4419
4420         u8         sum_flows[0x20];
4421
4422         u8         cnp_ignored_high[0x20];
4423
4424         u8         cnp_ignored_low[0x20];
4425
4426         u8         cnp_handled_high[0x20];
4427
4428         u8         cnp_handled_low[0x20];
4429
4430         u8         reserved_at_140[0x100];
4431
4432         u8         time_stamp_high[0x20];
4433
4434         u8         time_stamp_low[0x20];
4435
4436         u8         accumulators_period[0x20];
4437
4438         u8         ecn_marked_roce_packets_high[0x20];
4439
4440         u8         ecn_marked_roce_packets_low[0x20];
4441
4442         u8         cnps_sent_high[0x20];
4443
4444         u8         cnps_sent_low[0x20];
4445
4446         u8         reserved_at_320[0x560];
4447 };
4448
4449 struct mlx5_ifc_query_cong_statistics_in_bits {
4450         u8         opcode[0x10];
4451         u8         reserved_at_10[0x10];
4452
4453         u8         reserved_at_20[0x10];
4454         u8         op_mod[0x10];
4455
4456         u8         clear[0x1];
4457         u8         reserved_at_41[0x1f];
4458
4459         u8         reserved_at_60[0x20];
4460 };
4461
4462 struct mlx5_ifc_query_cong_params_out_bits {
4463         u8         status[0x8];
4464         u8         reserved_at_8[0x18];
4465
4466         u8         syndrome[0x20];
4467
4468         u8         reserved_at_40[0x40];
4469
4470         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4471 };
4472
4473 struct mlx5_ifc_query_cong_params_in_bits {
4474         u8         opcode[0x10];
4475         u8         reserved_at_10[0x10];
4476
4477         u8         reserved_at_20[0x10];
4478         u8         op_mod[0x10];
4479
4480         u8         reserved_at_40[0x1c];
4481         u8         cong_protocol[0x4];
4482
4483         u8         reserved_at_60[0x20];
4484 };
4485
4486 struct mlx5_ifc_query_adapter_out_bits {
4487         u8         status[0x8];
4488         u8         reserved_at_8[0x18];
4489
4490         u8         syndrome[0x20];
4491
4492         u8         reserved_at_40[0x40];
4493
4494         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4495 };
4496
4497 struct mlx5_ifc_query_adapter_in_bits {
4498         u8         opcode[0x10];
4499         u8         reserved_at_10[0x10];
4500
4501         u8         reserved_at_20[0x10];
4502         u8         op_mod[0x10];
4503
4504         u8         reserved_at_40[0x40];
4505 };
4506
4507 struct mlx5_ifc_qp_2rst_out_bits {
4508         u8         status[0x8];
4509         u8         reserved_at_8[0x18];
4510
4511         u8         syndrome[0x20];
4512
4513         u8         reserved_at_40[0x40];
4514 };
4515
4516 struct mlx5_ifc_qp_2rst_in_bits {
4517         u8         opcode[0x10];
4518         u8         reserved_at_10[0x10];
4519
4520         u8         reserved_at_20[0x10];
4521         u8         op_mod[0x10];
4522
4523         u8         reserved_at_40[0x8];
4524         u8         qpn[0x18];
4525
4526         u8         reserved_at_60[0x20];
4527 };
4528
4529 struct mlx5_ifc_qp_2err_out_bits {
4530         u8         status[0x8];
4531         u8         reserved_at_8[0x18];
4532
4533         u8         syndrome[0x20];
4534
4535         u8         reserved_at_40[0x40];
4536 };
4537
4538 struct mlx5_ifc_qp_2err_in_bits {
4539         u8         opcode[0x10];
4540         u8         reserved_at_10[0x10];
4541
4542         u8         reserved_at_20[0x10];
4543         u8         op_mod[0x10];
4544
4545         u8         reserved_at_40[0x8];
4546         u8         qpn[0x18];
4547
4548         u8         reserved_at_60[0x20];
4549 };
4550
4551 struct mlx5_ifc_page_fault_resume_out_bits {
4552         u8         status[0x8];
4553         u8         reserved_at_8[0x18];
4554
4555         u8         syndrome[0x20];
4556
4557         u8         reserved_at_40[0x40];
4558 };
4559
4560 struct mlx5_ifc_page_fault_resume_in_bits {
4561         u8         opcode[0x10];
4562         u8         reserved_at_10[0x10];
4563
4564         u8         reserved_at_20[0x10];
4565         u8         op_mod[0x10];
4566
4567         u8         error[0x1];
4568         u8         reserved_at_41[0x4];
4569         u8         rdma[0x1];
4570         u8         read_write[0x1];
4571         u8         req_res[0x1];
4572         u8         qpn[0x18];
4573
4574         u8         reserved_at_60[0x20];
4575 };
4576
4577 struct mlx5_ifc_nop_out_bits {
4578         u8         status[0x8];
4579         u8         reserved_at_8[0x18];
4580
4581         u8         syndrome[0x20];
4582
4583         u8         reserved_at_40[0x40];
4584 };
4585
4586 struct mlx5_ifc_nop_in_bits {
4587         u8         opcode[0x10];
4588         u8         reserved_at_10[0x10];
4589
4590         u8         reserved_at_20[0x10];
4591         u8         op_mod[0x10];
4592
4593         u8         reserved_at_40[0x40];
4594 };
4595
4596 struct mlx5_ifc_modify_vport_state_out_bits {
4597         u8         status[0x8];
4598         u8         reserved_at_8[0x18];
4599
4600         u8         syndrome[0x20];
4601
4602         u8         reserved_at_40[0x40];
4603 };
4604
4605 struct mlx5_ifc_modify_vport_state_in_bits {
4606         u8         opcode[0x10];
4607         u8         reserved_at_10[0x10];
4608
4609         u8         reserved_at_20[0x10];
4610         u8         op_mod[0x10];
4611
4612         u8         other_vport[0x1];
4613         u8         reserved_at_41[0xf];
4614         u8         vport_number[0x10];
4615
4616         u8         reserved_at_60[0x18];
4617         u8         admin_state[0x4];
4618         u8         reserved_at_7c[0x4];
4619 };
4620
4621 struct mlx5_ifc_modify_tis_out_bits {
4622         u8         status[0x8];
4623         u8         reserved_at_8[0x18];
4624
4625         u8         syndrome[0x20];
4626
4627         u8         reserved_at_40[0x40];
4628 };
4629
4630 struct mlx5_ifc_modify_tis_bitmask_bits {
4631         u8         reserved_at_0[0x20];
4632
4633         u8         reserved_at_20[0x1d];
4634         u8         lag_tx_port_affinity[0x1];
4635         u8         strict_lag_tx_port_affinity[0x1];
4636         u8         prio[0x1];
4637 };
4638
4639 struct mlx5_ifc_modify_tis_in_bits {
4640         u8         opcode[0x10];
4641         u8         reserved_at_10[0x10];
4642
4643         u8         reserved_at_20[0x10];
4644         u8         op_mod[0x10];
4645
4646         u8         reserved_at_40[0x8];
4647         u8         tisn[0x18];
4648
4649         u8         reserved_at_60[0x20];
4650
4651         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4652
4653         u8         reserved_at_c0[0x40];
4654
4655         struct mlx5_ifc_tisc_bits ctx;
4656 };
4657
4658 struct mlx5_ifc_modify_tir_bitmask_bits {
4659         u8         reserved_at_0[0x20];
4660
4661         u8         reserved_at_20[0x1b];
4662         u8         self_lb_en[0x1];
4663         u8         reserved_at_3c[0x1];
4664         u8         hash[0x1];
4665         u8         reserved_at_3e[0x1];
4666         u8         lro[0x1];
4667 };
4668
4669 struct mlx5_ifc_modify_tir_out_bits {
4670         u8         status[0x8];
4671         u8         reserved_at_8[0x18];
4672
4673         u8         syndrome[0x20];
4674
4675         u8         reserved_at_40[0x40];
4676 };
4677
4678 struct mlx5_ifc_modify_tir_in_bits {
4679         u8         opcode[0x10];
4680         u8         reserved_at_10[0x10];
4681
4682         u8         reserved_at_20[0x10];
4683         u8         op_mod[0x10];
4684
4685         u8         reserved_at_40[0x8];
4686         u8         tirn[0x18];
4687
4688         u8         reserved_at_60[0x20];
4689
4690         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4691
4692         u8         reserved_at_c0[0x40];
4693
4694         struct mlx5_ifc_tirc_bits ctx;
4695 };
4696
4697 struct mlx5_ifc_modify_sq_out_bits {
4698         u8         status[0x8];
4699         u8         reserved_at_8[0x18];
4700
4701         u8         syndrome[0x20];
4702
4703         u8         reserved_at_40[0x40];
4704 };
4705
4706 struct mlx5_ifc_modify_sq_in_bits {
4707         u8         opcode[0x10];
4708         u8         reserved_at_10[0x10];
4709
4710         u8         reserved_at_20[0x10];
4711         u8         op_mod[0x10];
4712
4713         u8         sq_state[0x4];
4714         u8         reserved_at_44[0x4];
4715         u8         sqn[0x18];
4716
4717         u8         reserved_at_60[0x20];
4718
4719         u8         modify_bitmask[0x40];
4720
4721         u8         reserved_at_c0[0x40];
4722
4723         struct mlx5_ifc_sqc_bits ctx;
4724 };
4725
4726 struct mlx5_ifc_modify_rqt_out_bits {
4727         u8         status[0x8];
4728         u8         reserved_at_8[0x18];
4729
4730         u8         syndrome[0x20];
4731
4732         u8         reserved_at_40[0x40];
4733 };
4734
4735 struct mlx5_ifc_rqt_bitmask_bits {
4736         u8         reserved_at_0[0x20];
4737
4738         u8         reserved_at_20[0x1f];
4739         u8         rqn_list[0x1];
4740 };
4741
4742 struct mlx5_ifc_modify_rqt_in_bits {
4743         u8         opcode[0x10];
4744         u8         reserved_at_10[0x10];
4745
4746         u8         reserved_at_20[0x10];
4747         u8         op_mod[0x10];
4748
4749         u8         reserved_at_40[0x8];
4750         u8         rqtn[0x18];
4751
4752         u8         reserved_at_60[0x20];
4753
4754         struct mlx5_ifc_rqt_bitmask_bits bitmask;
4755
4756         u8         reserved_at_c0[0x40];
4757
4758         struct mlx5_ifc_rqtc_bits ctx;
4759 };
4760
4761 struct mlx5_ifc_modify_rq_out_bits {
4762         u8         status[0x8];
4763         u8         reserved_at_8[0x18];
4764
4765         u8         syndrome[0x20];
4766
4767         u8         reserved_at_40[0x40];
4768 };
4769
4770 enum {
4771         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
4772         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
4773 };
4774
4775 struct mlx5_ifc_modify_rq_in_bits {
4776         u8         opcode[0x10];
4777         u8         reserved_at_10[0x10];
4778
4779         u8         reserved_at_20[0x10];
4780         u8         op_mod[0x10];
4781
4782         u8         rq_state[0x4];
4783         u8         reserved_at_44[0x4];
4784         u8         rqn[0x18];
4785
4786         u8         reserved_at_60[0x20];
4787
4788         u8         modify_bitmask[0x40];
4789
4790         u8         reserved_at_c0[0x40];
4791
4792         struct mlx5_ifc_rqc_bits ctx;
4793 };
4794
4795 struct mlx5_ifc_modify_rmp_out_bits {
4796         u8         status[0x8];
4797         u8         reserved_at_8[0x18];
4798
4799         u8         syndrome[0x20];
4800
4801         u8         reserved_at_40[0x40];
4802 };
4803
4804 struct mlx5_ifc_rmp_bitmask_bits {
4805         u8         reserved_at_0[0x20];
4806
4807         u8         reserved_at_20[0x1f];
4808         u8         lwm[0x1];
4809 };
4810
4811 struct mlx5_ifc_modify_rmp_in_bits {
4812         u8         opcode[0x10];
4813         u8         reserved_at_10[0x10];
4814
4815         u8         reserved_at_20[0x10];
4816         u8         op_mod[0x10];
4817
4818         u8         rmp_state[0x4];
4819         u8         reserved_at_44[0x4];
4820         u8         rmpn[0x18];
4821
4822         u8         reserved_at_60[0x20];
4823
4824         struct mlx5_ifc_rmp_bitmask_bits bitmask;
4825
4826         u8         reserved_at_c0[0x40];
4827
4828         struct mlx5_ifc_rmpc_bits ctx;
4829 };
4830
4831 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4832         u8         status[0x8];
4833         u8         reserved_at_8[0x18];
4834
4835         u8         syndrome[0x20];
4836
4837         u8         reserved_at_40[0x40];
4838 };
4839
4840 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4841         u8         reserved_at_0[0x16];
4842         u8         node_guid[0x1];
4843         u8         port_guid[0x1];
4844         u8         min_inline[0x1];
4845         u8         mtu[0x1];
4846         u8         change_event[0x1];
4847         u8         promisc[0x1];
4848         u8         permanent_address[0x1];
4849         u8         addresses_list[0x1];
4850         u8         roce_en[0x1];
4851         u8         reserved_at_1f[0x1];
4852 };
4853
4854 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4855         u8         opcode[0x10];
4856         u8         reserved_at_10[0x10];
4857
4858         u8         reserved_at_20[0x10];
4859         u8         op_mod[0x10];
4860
4861         u8         other_vport[0x1];
4862         u8         reserved_at_41[0xf];
4863         u8         vport_number[0x10];
4864
4865         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4866
4867         u8         reserved_at_80[0x780];
4868
4869         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4870 };
4871
4872 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4873         u8         status[0x8];
4874         u8         reserved_at_8[0x18];
4875
4876         u8         syndrome[0x20];
4877
4878         u8         reserved_at_40[0x40];
4879 };
4880
4881 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4882         u8         opcode[0x10];
4883         u8         reserved_at_10[0x10];
4884
4885         u8         reserved_at_20[0x10];
4886         u8         op_mod[0x10];
4887
4888         u8         other_vport[0x1];
4889         u8         reserved_at_41[0xb];
4890         u8         port_num[0x4];
4891         u8         vport_number[0x10];
4892
4893         u8         reserved_at_60[0x20];
4894
4895         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4896 };
4897
4898 struct mlx5_ifc_modify_cq_out_bits {
4899         u8         status[0x8];
4900         u8         reserved_at_8[0x18];
4901
4902         u8         syndrome[0x20];
4903
4904         u8         reserved_at_40[0x40];
4905 };
4906
4907 enum {
4908         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
4909         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
4910 };
4911
4912 struct mlx5_ifc_modify_cq_in_bits {
4913         u8         opcode[0x10];
4914         u8         reserved_at_10[0x10];
4915
4916         u8         reserved_at_20[0x10];
4917         u8         op_mod[0x10];
4918
4919         u8         reserved_at_40[0x8];
4920         u8         cqn[0x18];
4921
4922         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4923
4924         struct mlx5_ifc_cqc_bits cq_context;
4925
4926         u8         reserved_at_280[0x600];
4927
4928         u8         pas[0][0x40];
4929 };
4930
4931 struct mlx5_ifc_modify_cong_status_out_bits {
4932         u8         status[0x8];
4933         u8         reserved_at_8[0x18];
4934
4935         u8         syndrome[0x20];
4936
4937         u8         reserved_at_40[0x40];
4938 };
4939
4940 struct mlx5_ifc_modify_cong_status_in_bits {
4941         u8         opcode[0x10];
4942         u8         reserved_at_10[0x10];
4943
4944         u8         reserved_at_20[0x10];
4945         u8         op_mod[0x10];
4946
4947         u8         reserved_at_40[0x18];
4948         u8         priority[0x4];
4949         u8         cong_protocol[0x4];
4950
4951         u8         enable[0x1];
4952         u8         tag_enable[0x1];
4953         u8         reserved_at_62[0x1e];
4954 };
4955
4956 struct mlx5_ifc_modify_cong_params_out_bits {
4957         u8         status[0x8];
4958         u8         reserved_at_8[0x18];
4959
4960         u8         syndrome[0x20];
4961
4962         u8         reserved_at_40[0x40];
4963 };
4964
4965 struct mlx5_ifc_modify_cong_params_in_bits {
4966         u8         opcode[0x10];
4967         u8         reserved_at_10[0x10];
4968
4969         u8         reserved_at_20[0x10];
4970         u8         op_mod[0x10];
4971
4972         u8         reserved_at_40[0x1c];
4973         u8         cong_protocol[0x4];
4974
4975         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4976
4977         u8         reserved_at_80[0x80];
4978
4979         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4980 };
4981
4982 struct mlx5_ifc_manage_pages_out_bits {
4983         u8         status[0x8];
4984         u8         reserved_at_8[0x18];
4985
4986         u8         syndrome[0x20];
4987
4988         u8         output_num_entries[0x20];
4989
4990         u8         reserved_at_60[0x20];
4991
4992         u8         pas[0][0x40];
4993 };
4994
4995 enum {
4996         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
4997         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
4998         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
4999 };
5000
5001 struct mlx5_ifc_manage_pages_in_bits {
5002         u8         opcode[0x10];
5003         u8         reserved_at_10[0x10];
5004
5005         u8         reserved_at_20[0x10];
5006         u8         op_mod[0x10];
5007
5008         u8         reserved_at_40[0x10];
5009         u8         function_id[0x10];
5010
5011         u8         input_num_entries[0x20];
5012
5013         u8         pas[0][0x40];
5014 };
5015
5016 struct mlx5_ifc_mad_ifc_out_bits {
5017         u8         status[0x8];
5018         u8         reserved_at_8[0x18];
5019
5020         u8         syndrome[0x20];
5021
5022         u8         reserved_at_40[0x40];
5023
5024         u8         response_mad_packet[256][0x8];
5025 };
5026
5027 struct mlx5_ifc_mad_ifc_in_bits {
5028         u8         opcode[0x10];
5029         u8         reserved_at_10[0x10];
5030
5031         u8         reserved_at_20[0x10];
5032         u8         op_mod[0x10];
5033
5034         u8         remote_lid[0x10];
5035         u8         reserved_at_50[0x8];
5036         u8         port[0x8];
5037
5038         u8         reserved_at_60[0x20];
5039
5040         u8         mad[256][0x8];
5041 };
5042
5043 struct mlx5_ifc_init_hca_out_bits {
5044         u8         status[0x8];
5045         u8         reserved_at_8[0x18];
5046
5047         u8         syndrome[0x20];
5048
5049         u8         reserved_at_40[0x40];
5050 };
5051
5052 struct mlx5_ifc_init_hca_in_bits {
5053         u8         opcode[0x10];
5054         u8         reserved_at_10[0x10];
5055
5056         u8         reserved_at_20[0x10];
5057         u8         op_mod[0x10];
5058
5059         u8         reserved_at_40[0x40];
5060 };
5061
5062 struct mlx5_ifc_init2rtr_qp_out_bits {
5063         u8         status[0x8];
5064         u8         reserved_at_8[0x18];
5065
5066         u8         syndrome[0x20];
5067
5068         u8         reserved_at_40[0x40];
5069 };
5070
5071 struct mlx5_ifc_init2rtr_qp_in_bits {
5072         u8         opcode[0x10];
5073         u8         reserved_at_10[0x10];
5074
5075         u8         reserved_at_20[0x10];
5076         u8         op_mod[0x10];
5077
5078         u8         reserved_at_40[0x8];
5079         u8         qpn[0x18];
5080
5081         u8         reserved_at_60[0x20];
5082
5083         u8         opt_param_mask[0x20];
5084
5085         u8         reserved_at_a0[0x20];
5086
5087         struct mlx5_ifc_qpc_bits qpc;
5088
5089         u8         reserved_at_800[0x80];
5090 };
5091
5092 struct mlx5_ifc_init2init_qp_out_bits {
5093         u8         status[0x8];
5094         u8         reserved_at_8[0x18];
5095
5096         u8         syndrome[0x20];
5097
5098         u8         reserved_at_40[0x40];
5099 };
5100
5101 struct mlx5_ifc_init2init_qp_in_bits {
5102         u8         opcode[0x10];
5103         u8         reserved_at_10[0x10];
5104
5105         u8         reserved_at_20[0x10];
5106         u8         op_mod[0x10];
5107
5108         u8         reserved_at_40[0x8];
5109         u8         qpn[0x18];
5110
5111         u8         reserved_at_60[0x20];
5112
5113         u8         opt_param_mask[0x20];
5114
5115         u8         reserved_at_a0[0x20];
5116
5117         struct mlx5_ifc_qpc_bits qpc;
5118
5119         u8         reserved_at_800[0x80];
5120 };
5121
5122 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5123         u8         status[0x8];
5124         u8         reserved_at_8[0x18];
5125
5126         u8         syndrome[0x20];
5127
5128         u8         reserved_at_40[0x40];
5129
5130         u8         packet_headers_log[128][0x8];
5131
5132         u8         packet_syndrome[64][0x8];
5133 };
5134
5135 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5136         u8         opcode[0x10];
5137         u8         reserved_at_10[0x10];
5138
5139         u8         reserved_at_20[0x10];
5140         u8         op_mod[0x10];
5141
5142         u8         reserved_at_40[0x40];
5143 };
5144
5145 struct mlx5_ifc_gen_eqe_in_bits {
5146         u8         opcode[0x10];
5147         u8         reserved_at_10[0x10];
5148
5149         u8         reserved_at_20[0x10];
5150         u8         op_mod[0x10];
5151
5152         u8         reserved_at_40[0x18];
5153         u8         eq_number[0x8];
5154
5155         u8         reserved_at_60[0x20];
5156
5157         u8         eqe[64][0x8];
5158 };
5159
5160 struct mlx5_ifc_gen_eq_out_bits {
5161         u8         status[0x8];
5162         u8         reserved_at_8[0x18];
5163
5164         u8         syndrome[0x20];
5165
5166         u8         reserved_at_40[0x40];
5167 };
5168
5169 struct mlx5_ifc_enable_hca_out_bits {
5170         u8         status[0x8];
5171         u8         reserved_at_8[0x18];
5172
5173         u8         syndrome[0x20];
5174
5175         u8         reserved_at_40[0x20];
5176 };
5177
5178 struct mlx5_ifc_enable_hca_in_bits {
5179         u8         opcode[0x10];
5180         u8         reserved_at_10[0x10];
5181
5182         u8         reserved_at_20[0x10];
5183         u8         op_mod[0x10];
5184
5185         u8         reserved_at_40[0x10];
5186         u8         function_id[0x10];
5187
5188         u8         reserved_at_60[0x20];
5189 };
5190
5191 struct mlx5_ifc_drain_dct_out_bits {
5192         u8         status[0x8];
5193         u8         reserved_at_8[0x18];
5194
5195         u8         syndrome[0x20];
5196
5197         u8         reserved_at_40[0x40];
5198 };
5199
5200 struct mlx5_ifc_drain_dct_in_bits {
5201         u8         opcode[0x10];
5202         u8         reserved_at_10[0x10];
5203
5204         u8         reserved_at_20[0x10];
5205         u8         op_mod[0x10];
5206
5207         u8         reserved_at_40[0x8];
5208         u8         dctn[0x18];
5209
5210         u8         reserved_at_60[0x20];
5211 };
5212
5213 struct mlx5_ifc_disable_hca_out_bits {
5214         u8         status[0x8];
5215         u8         reserved_at_8[0x18];
5216
5217         u8         syndrome[0x20];
5218
5219         u8         reserved_at_40[0x20];
5220 };
5221
5222 struct mlx5_ifc_disable_hca_in_bits {
5223         u8         opcode[0x10];
5224         u8         reserved_at_10[0x10];
5225
5226         u8         reserved_at_20[0x10];
5227         u8         op_mod[0x10];
5228
5229         u8         reserved_at_40[0x10];
5230         u8         function_id[0x10];
5231
5232         u8         reserved_at_60[0x20];
5233 };
5234
5235 struct mlx5_ifc_detach_from_mcg_out_bits {
5236         u8         status[0x8];
5237         u8         reserved_at_8[0x18];
5238
5239         u8         syndrome[0x20];
5240
5241         u8         reserved_at_40[0x40];
5242 };
5243
5244 struct mlx5_ifc_detach_from_mcg_in_bits {
5245         u8         opcode[0x10];
5246         u8         reserved_at_10[0x10];
5247
5248         u8         reserved_at_20[0x10];
5249         u8         op_mod[0x10];
5250
5251         u8         reserved_at_40[0x8];
5252         u8         qpn[0x18];
5253
5254         u8         reserved_at_60[0x20];
5255
5256         u8         multicast_gid[16][0x8];
5257 };
5258
5259 struct mlx5_ifc_destroy_xrq_out_bits {
5260         u8         status[0x8];
5261         u8         reserved_at_8[0x18];
5262
5263         u8         syndrome[0x20];
5264
5265         u8         reserved_at_40[0x40];
5266 };
5267
5268 struct mlx5_ifc_destroy_xrq_in_bits {
5269         u8         opcode[0x10];
5270         u8         reserved_at_10[0x10];
5271
5272         u8         reserved_at_20[0x10];
5273         u8         op_mod[0x10];
5274
5275         u8         reserved_at_40[0x8];
5276         u8         xrqn[0x18];
5277
5278         u8         reserved_at_60[0x20];
5279 };
5280
5281 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5282         u8         status[0x8];
5283         u8         reserved_at_8[0x18];
5284
5285         u8         syndrome[0x20];
5286
5287         u8         reserved_at_40[0x40];
5288 };
5289
5290 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5291         u8         opcode[0x10];
5292         u8         reserved_at_10[0x10];
5293
5294         u8         reserved_at_20[0x10];
5295         u8         op_mod[0x10];
5296
5297         u8         reserved_at_40[0x8];
5298         u8         xrc_srqn[0x18];
5299
5300         u8         reserved_at_60[0x20];
5301 };
5302
5303 struct mlx5_ifc_destroy_tis_out_bits {
5304         u8         status[0x8];
5305         u8         reserved_at_8[0x18];
5306
5307         u8         syndrome[0x20];
5308
5309         u8         reserved_at_40[0x40];
5310 };
5311
5312 struct mlx5_ifc_destroy_tis_in_bits {
5313         u8         opcode[0x10];
5314         u8         reserved_at_10[0x10];
5315
5316         u8         reserved_at_20[0x10];
5317         u8         op_mod[0x10];
5318
5319         u8         reserved_at_40[0x8];
5320         u8         tisn[0x18];
5321
5322         u8         reserved_at_60[0x20];
5323 };
5324
5325 struct mlx5_ifc_destroy_tir_out_bits {
5326         u8         status[0x8];
5327         u8         reserved_at_8[0x18];
5328
5329         u8         syndrome[0x20];
5330
5331         u8         reserved_at_40[0x40];
5332 };
5333
5334 struct mlx5_ifc_destroy_tir_in_bits {
5335         u8         opcode[0x10];
5336         u8         reserved_at_10[0x10];
5337
5338         u8         reserved_at_20[0x10];
5339         u8         op_mod[0x10];
5340
5341         u8         reserved_at_40[0x8];
5342         u8         tirn[0x18];
5343
5344         u8         reserved_at_60[0x20];
5345 };
5346
5347 struct mlx5_ifc_destroy_srq_out_bits {
5348         u8         status[0x8];
5349         u8         reserved_at_8[0x18];
5350
5351         u8         syndrome[0x20];
5352
5353         u8         reserved_at_40[0x40];
5354 };
5355
5356 struct mlx5_ifc_destroy_srq_in_bits {
5357         u8         opcode[0x10];
5358         u8         reserved_at_10[0x10];
5359
5360         u8         reserved_at_20[0x10];
5361         u8         op_mod[0x10];
5362
5363         u8         reserved_at_40[0x8];
5364         u8         srqn[0x18];
5365
5366         u8         reserved_at_60[0x20];
5367 };
5368
5369 struct mlx5_ifc_destroy_sq_out_bits {
5370         u8         status[0x8];
5371         u8         reserved_at_8[0x18];
5372
5373         u8         syndrome[0x20];
5374
5375         u8         reserved_at_40[0x40];
5376 };
5377
5378 struct mlx5_ifc_destroy_sq_in_bits {
5379         u8         opcode[0x10];
5380         u8         reserved_at_10[0x10];
5381
5382         u8         reserved_at_20[0x10];
5383         u8         op_mod[0x10];
5384
5385         u8         reserved_at_40[0x8];
5386         u8         sqn[0x18];
5387
5388         u8         reserved_at_60[0x20];
5389 };
5390
5391 struct mlx5_ifc_destroy_rqt_out_bits {
5392         u8         status[0x8];
5393         u8         reserved_at_8[0x18];
5394
5395         u8         syndrome[0x20];
5396
5397         u8         reserved_at_40[0x40];
5398 };
5399
5400 struct mlx5_ifc_destroy_rqt_in_bits {
5401         u8         opcode[0x10];
5402         u8         reserved_at_10[0x10];
5403
5404         u8         reserved_at_20[0x10];
5405         u8         op_mod[0x10];
5406
5407         u8         reserved_at_40[0x8];
5408         u8         rqtn[0x18];
5409
5410         u8         reserved_at_60[0x20];
5411 };
5412
5413 struct mlx5_ifc_destroy_rq_out_bits {
5414         u8         status[0x8];
5415         u8         reserved_at_8[0x18];
5416
5417         u8         syndrome[0x20];
5418
5419         u8         reserved_at_40[0x40];
5420 };
5421
5422 struct mlx5_ifc_destroy_rq_in_bits {
5423         u8         opcode[0x10];
5424         u8         reserved_at_10[0x10];
5425
5426         u8         reserved_at_20[0x10];
5427         u8         op_mod[0x10];
5428
5429         u8         reserved_at_40[0x8];
5430         u8         rqn[0x18];
5431
5432         u8         reserved_at_60[0x20];
5433 };
5434
5435 struct mlx5_ifc_destroy_rmp_out_bits {
5436         u8         status[0x8];
5437         u8         reserved_at_8[0x18];
5438
5439         u8         syndrome[0x20];
5440
5441         u8         reserved_at_40[0x40];
5442 };
5443
5444 struct mlx5_ifc_destroy_rmp_in_bits {
5445         u8         opcode[0x10];
5446         u8         reserved_at_10[0x10];
5447
5448         u8         reserved_at_20[0x10];
5449         u8         op_mod[0x10];
5450
5451         u8         reserved_at_40[0x8];
5452         u8         rmpn[0x18];
5453
5454         u8         reserved_at_60[0x20];
5455 };
5456
5457 struct mlx5_ifc_destroy_qp_out_bits {
5458         u8         status[0x8];
5459         u8         reserved_at_8[0x18];
5460
5461         u8         syndrome[0x20];
5462
5463         u8         reserved_at_40[0x40];
5464 };
5465
5466 struct mlx5_ifc_destroy_qp_in_bits {
5467         u8         opcode[0x10];
5468         u8         reserved_at_10[0x10];
5469
5470         u8         reserved_at_20[0x10];
5471         u8         op_mod[0x10];
5472
5473         u8         reserved_at_40[0x8];
5474         u8         qpn[0x18];
5475
5476         u8         reserved_at_60[0x20];
5477 };
5478
5479 struct mlx5_ifc_destroy_psv_out_bits {
5480         u8         status[0x8];
5481         u8         reserved_at_8[0x18];
5482
5483         u8         syndrome[0x20];
5484
5485         u8         reserved_at_40[0x40];
5486 };
5487
5488 struct mlx5_ifc_destroy_psv_in_bits {
5489         u8         opcode[0x10];
5490         u8         reserved_at_10[0x10];
5491
5492         u8         reserved_at_20[0x10];
5493         u8         op_mod[0x10];
5494
5495         u8         reserved_at_40[0x8];
5496         u8         psvn[0x18];
5497
5498         u8         reserved_at_60[0x20];
5499 };
5500
5501 struct mlx5_ifc_destroy_mkey_out_bits {
5502         u8         status[0x8];
5503         u8         reserved_at_8[0x18];
5504
5505         u8         syndrome[0x20];
5506
5507         u8         reserved_at_40[0x40];
5508 };
5509
5510 struct mlx5_ifc_destroy_mkey_in_bits {
5511         u8         opcode[0x10];
5512         u8         reserved_at_10[0x10];
5513
5514         u8         reserved_at_20[0x10];
5515         u8         op_mod[0x10];
5516
5517         u8         reserved_at_40[0x8];
5518         u8         mkey_index[0x18];
5519
5520         u8         reserved_at_60[0x20];
5521 };
5522
5523 struct mlx5_ifc_destroy_flow_table_out_bits {
5524         u8         status[0x8];
5525         u8         reserved_at_8[0x18];
5526
5527         u8         syndrome[0x20];
5528
5529         u8         reserved_at_40[0x40];
5530 };
5531
5532 struct mlx5_ifc_destroy_flow_table_in_bits {
5533         u8         opcode[0x10];
5534         u8         reserved_at_10[0x10];
5535
5536         u8         reserved_at_20[0x10];
5537         u8         op_mod[0x10];
5538
5539         u8         other_vport[0x1];
5540         u8         reserved_at_41[0xf];
5541         u8         vport_number[0x10];
5542
5543         u8         reserved_at_60[0x20];
5544
5545         u8         table_type[0x8];
5546         u8         reserved_at_88[0x18];
5547
5548         u8         reserved_at_a0[0x8];
5549         u8         table_id[0x18];
5550
5551         u8         reserved_at_c0[0x140];
5552 };
5553
5554 struct mlx5_ifc_destroy_flow_group_out_bits {
5555         u8         status[0x8];
5556         u8         reserved_at_8[0x18];
5557
5558         u8         syndrome[0x20];
5559
5560         u8         reserved_at_40[0x40];
5561 };
5562
5563 struct mlx5_ifc_destroy_flow_group_in_bits {
5564         u8         opcode[0x10];
5565         u8         reserved_at_10[0x10];
5566
5567         u8         reserved_at_20[0x10];
5568         u8         op_mod[0x10];
5569
5570         u8         other_vport[0x1];
5571         u8         reserved_at_41[0xf];
5572         u8         vport_number[0x10];
5573
5574         u8         reserved_at_60[0x20];
5575
5576         u8         table_type[0x8];
5577         u8         reserved_at_88[0x18];
5578
5579         u8         reserved_at_a0[0x8];
5580         u8         table_id[0x18];
5581
5582         u8         group_id[0x20];
5583
5584         u8         reserved_at_e0[0x120];
5585 };
5586
5587 struct mlx5_ifc_destroy_eq_out_bits {
5588         u8         status[0x8];
5589         u8         reserved_at_8[0x18];
5590
5591         u8         syndrome[0x20];
5592
5593         u8         reserved_at_40[0x40];
5594 };
5595
5596 struct mlx5_ifc_destroy_eq_in_bits {
5597         u8         opcode[0x10];
5598         u8         reserved_at_10[0x10];
5599
5600         u8         reserved_at_20[0x10];
5601         u8         op_mod[0x10];
5602
5603         u8         reserved_at_40[0x18];
5604         u8         eq_number[0x8];
5605
5606         u8         reserved_at_60[0x20];
5607 };
5608
5609 struct mlx5_ifc_destroy_dct_out_bits {
5610         u8         status[0x8];
5611         u8         reserved_at_8[0x18];
5612
5613         u8         syndrome[0x20];
5614
5615         u8         reserved_at_40[0x40];
5616 };
5617
5618 struct mlx5_ifc_destroy_dct_in_bits {
5619         u8         opcode[0x10];
5620         u8         reserved_at_10[0x10];
5621
5622         u8         reserved_at_20[0x10];
5623         u8         op_mod[0x10];
5624
5625         u8         reserved_at_40[0x8];
5626         u8         dctn[0x18];
5627
5628         u8         reserved_at_60[0x20];
5629 };
5630
5631 struct mlx5_ifc_destroy_cq_out_bits {
5632         u8         status[0x8];
5633         u8         reserved_at_8[0x18];
5634
5635         u8         syndrome[0x20];
5636
5637         u8         reserved_at_40[0x40];
5638 };
5639
5640 struct mlx5_ifc_destroy_cq_in_bits {
5641         u8         opcode[0x10];
5642         u8         reserved_at_10[0x10];
5643
5644         u8         reserved_at_20[0x10];
5645         u8         op_mod[0x10];
5646
5647         u8         reserved_at_40[0x8];
5648         u8         cqn[0x18];
5649
5650         u8         reserved_at_60[0x20];
5651 };
5652
5653 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5654         u8         status[0x8];
5655         u8         reserved_at_8[0x18];
5656
5657         u8         syndrome[0x20];
5658
5659         u8         reserved_at_40[0x40];
5660 };
5661
5662 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5663         u8         opcode[0x10];
5664         u8         reserved_at_10[0x10];
5665
5666         u8         reserved_at_20[0x10];
5667         u8         op_mod[0x10];
5668
5669         u8         reserved_at_40[0x20];
5670
5671         u8         reserved_at_60[0x10];
5672         u8         vxlan_udp_port[0x10];
5673 };
5674
5675 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5676         u8         status[0x8];
5677         u8         reserved_at_8[0x18];
5678
5679         u8         syndrome[0x20];
5680
5681         u8         reserved_at_40[0x40];
5682 };
5683
5684 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5685         u8         opcode[0x10];
5686         u8         reserved_at_10[0x10];
5687
5688         u8         reserved_at_20[0x10];
5689         u8         op_mod[0x10];
5690
5691         u8         reserved_at_40[0x60];
5692
5693         u8         reserved_at_a0[0x8];
5694         u8         table_index[0x18];
5695
5696         u8         reserved_at_c0[0x140];
5697 };
5698
5699 struct mlx5_ifc_delete_fte_out_bits {
5700         u8         status[0x8];
5701         u8         reserved_at_8[0x18];
5702
5703         u8         syndrome[0x20];
5704
5705         u8         reserved_at_40[0x40];
5706 };
5707
5708 struct mlx5_ifc_delete_fte_in_bits {
5709         u8         opcode[0x10];
5710         u8         reserved_at_10[0x10];
5711
5712         u8         reserved_at_20[0x10];
5713         u8         op_mod[0x10];
5714
5715         u8         other_vport[0x1];
5716         u8         reserved_at_41[0xf];
5717         u8         vport_number[0x10];
5718
5719         u8         reserved_at_60[0x20];
5720
5721         u8         table_type[0x8];
5722         u8         reserved_at_88[0x18];
5723
5724         u8         reserved_at_a0[0x8];
5725         u8         table_id[0x18];
5726
5727         u8         reserved_at_c0[0x40];
5728
5729         u8         flow_index[0x20];
5730
5731         u8         reserved_at_120[0xe0];
5732 };
5733
5734 struct mlx5_ifc_dealloc_xrcd_out_bits {
5735         u8         status[0x8];
5736         u8         reserved_at_8[0x18];
5737
5738         u8         syndrome[0x20];
5739
5740         u8         reserved_at_40[0x40];
5741 };
5742
5743 struct mlx5_ifc_dealloc_xrcd_in_bits {
5744         u8         opcode[0x10];
5745         u8         reserved_at_10[0x10];
5746
5747         u8         reserved_at_20[0x10];
5748         u8         op_mod[0x10];
5749
5750         u8         reserved_at_40[0x8];
5751         u8         xrcd[0x18];
5752
5753         u8         reserved_at_60[0x20];
5754 };
5755
5756 struct mlx5_ifc_dealloc_uar_out_bits {
5757         u8         status[0x8];
5758         u8         reserved_at_8[0x18];
5759
5760         u8         syndrome[0x20];
5761
5762         u8         reserved_at_40[0x40];
5763 };
5764
5765 struct mlx5_ifc_dealloc_uar_in_bits {
5766         u8         opcode[0x10];
5767         u8         reserved_at_10[0x10];
5768
5769         u8         reserved_at_20[0x10];
5770         u8         op_mod[0x10];
5771
5772         u8         reserved_at_40[0x8];
5773         u8         uar[0x18];
5774
5775         u8         reserved_at_60[0x20];
5776 };
5777
5778 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5779         u8         status[0x8];
5780         u8         reserved_at_8[0x18];
5781
5782         u8         syndrome[0x20];
5783
5784         u8         reserved_at_40[0x40];
5785 };
5786
5787 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5788         u8         opcode[0x10];
5789         u8         reserved_at_10[0x10];
5790
5791         u8         reserved_at_20[0x10];
5792         u8         op_mod[0x10];
5793
5794         u8         reserved_at_40[0x8];
5795         u8         transport_domain[0x18];
5796
5797         u8         reserved_at_60[0x20];
5798 };
5799
5800 struct mlx5_ifc_dealloc_q_counter_out_bits {
5801         u8         status[0x8];
5802         u8         reserved_at_8[0x18];
5803
5804         u8         syndrome[0x20];
5805
5806         u8         reserved_at_40[0x40];
5807 };
5808
5809 struct mlx5_ifc_dealloc_q_counter_in_bits {
5810         u8         opcode[0x10];
5811         u8         reserved_at_10[0x10];
5812
5813         u8         reserved_at_20[0x10];
5814         u8         op_mod[0x10];
5815
5816         u8         reserved_at_40[0x18];
5817         u8         counter_set_id[0x8];
5818
5819         u8         reserved_at_60[0x20];
5820 };
5821
5822 struct mlx5_ifc_dealloc_pd_out_bits {
5823         u8         status[0x8];
5824         u8         reserved_at_8[0x18];
5825
5826         u8         syndrome[0x20];
5827
5828         u8         reserved_at_40[0x40];
5829 };
5830
5831 struct mlx5_ifc_dealloc_pd_in_bits {
5832         u8         opcode[0x10];
5833         u8         reserved_at_10[0x10];
5834
5835         u8         reserved_at_20[0x10];
5836         u8         op_mod[0x10];
5837
5838         u8         reserved_at_40[0x8];
5839         u8         pd[0x18];
5840
5841         u8         reserved_at_60[0x20];
5842 };
5843
5844 struct mlx5_ifc_dealloc_flow_counter_out_bits {
5845         u8         status[0x8];
5846         u8         reserved_at_8[0x18];
5847
5848         u8         syndrome[0x20];
5849
5850         u8         reserved_at_40[0x40];
5851 };
5852
5853 struct mlx5_ifc_dealloc_flow_counter_in_bits {
5854         u8         opcode[0x10];
5855         u8         reserved_at_10[0x10];
5856
5857         u8         reserved_at_20[0x10];
5858         u8         op_mod[0x10];
5859
5860         u8         reserved_at_40[0x10];
5861         u8         flow_counter_id[0x10];
5862
5863         u8         reserved_at_60[0x20];
5864 };
5865
5866 struct mlx5_ifc_create_xrq_out_bits {
5867         u8         status[0x8];
5868         u8         reserved_at_8[0x18];
5869
5870         u8         syndrome[0x20];
5871
5872         u8         reserved_at_40[0x8];
5873         u8         xrqn[0x18];
5874
5875         u8         reserved_at_60[0x20];
5876 };
5877
5878 struct mlx5_ifc_create_xrq_in_bits {
5879         u8         opcode[0x10];
5880         u8         reserved_at_10[0x10];
5881
5882         u8         reserved_at_20[0x10];
5883         u8         op_mod[0x10];
5884
5885         u8         reserved_at_40[0x40];
5886
5887         struct mlx5_ifc_xrqc_bits xrq_context;
5888 };
5889
5890 struct mlx5_ifc_create_xrc_srq_out_bits {
5891         u8         status[0x8];
5892         u8         reserved_at_8[0x18];
5893
5894         u8         syndrome[0x20];
5895
5896         u8         reserved_at_40[0x8];
5897         u8         xrc_srqn[0x18];
5898
5899         u8         reserved_at_60[0x20];
5900 };
5901
5902 struct mlx5_ifc_create_xrc_srq_in_bits {
5903         u8         opcode[0x10];
5904         u8         reserved_at_10[0x10];
5905
5906         u8         reserved_at_20[0x10];
5907         u8         op_mod[0x10];
5908
5909         u8         reserved_at_40[0x40];
5910
5911         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5912
5913         u8         reserved_at_280[0x600];
5914
5915         u8         pas[0][0x40];
5916 };
5917
5918 struct mlx5_ifc_create_tis_out_bits {
5919         u8         status[0x8];
5920         u8         reserved_at_8[0x18];
5921
5922         u8         syndrome[0x20];
5923
5924         u8         reserved_at_40[0x8];
5925         u8         tisn[0x18];
5926
5927         u8         reserved_at_60[0x20];
5928 };
5929
5930 struct mlx5_ifc_create_tis_in_bits {
5931         u8         opcode[0x10];
5932         u8         reserved_at_10[0x10];
5933
5934         u8         reserved_at_20[0x10];
5935         u8         op_mod[0x10];
5936
5937         u8         reserved_at_40[0xc0];
5938
5939         struct mlx5_ifc_tisc_bits ctx;
5940 };
5941
5942 struct mlx5_ifc_create_tir_out_bits {
5943         u8         status[0x8];
5944         u8         reserved_at_8[0x18];
5945
5946         u8         syndrome[0x20];
5947
5948         u8         reserved_at_40[0x8];
5949         u8         tirn[0x18];
5950
5951         u8         reserved_at_60[0x20];
5952 };
5953
5954 struct mlx5_ifc_create_tir_in_bits {
5955         u8         opcode[0x10];
5956         u8         reserved_at_10[0x10];
5957
5958         u8         reserved_at_20[0x10];
5959         u8         op_mod[0x10];
5960
5961         u8         reserved_at_40[0xc0];
5962
5963         struct mlx5_ifc_tirc_bits ctx;
5964 };
5965
5966 struct mlx5_ifc_create_srq_out_bits {
5967         u8         status[0x8];
5968         u8         reserved_at_8[0x18];
5969
5970         u8         syndrome[0x20];
5971
5972         u8         reserved_at_40[0x8];
5973         u8         srqn[0x18];
5974
5975         u8         reserved_at_60[0x20];
5976 };
5977
5978 struct mlx5_ifc_create_srq_in_bits {
5979         u8         opcode[0x10];
5980         u8         reserved_at_10[0x10];
5981
5982         u8         reserved_at_20[0x10];
5983         u8         op_mod[0x10];
5984
5985         u8         reserved_at_40[0x40];
5986
5987         struct mlx5_ifc_srqc_bits srq_context_entry;
5988
5989         u8         reserved_at_280[0x600];
5990
5991         u8         pas[0][0x40];
5992 };
5993
5994 struct mlx5_ifc_create_sq_out_bits {
5995         u8         status[0x8];
5996         u8         reserved_at_8[0x18];
5997
5998         u8         syndrome[0x20];
5999
6000         u8         reserved_at_40[0x8];
6001         u8         sqn[0x18];
6002
6003         u8         reserved_at_60[0x20];
6004 };
6005
6006 struct mlx5_ifc_create_sq_in_bits {
6007         u8         opcode[0x10];
6008         u8         reserved_at_10[0x10];
6009
6010         u8         reserved_at_20[0x10];
6011         u8         op_mod[0x10];
6012
6013         u8         reserved_at_40[0xc0];
6014
6015         struct mlx5_ifc_sqc_bits ctx;
6016 };
6017
6018 struct mlx5_ifc_create_rqt_out_bits {
6019         u8         status[0x8];
6020         u8         reserved_at_8[0x18];
6021
6022         u8         syndrome[0x20];
6023
6024         u8         reserved_at_40[0x8];
6025         u8         rqtn[0x18];
6026
6027         u8         reserved_at_60[0x20];
6028 };
6029
6030 struct mlx5_ifc_create_rqt_in_bits {
6031         u8         opcode[0x10];
6032         u8         reserved_at_10[0x10];
6033
6034         u8         reserved_at_20[0x10];
6035         u8         op_mod[0x10];
6036
6037         u8         reserved_at_40[0xc0];
6038
6039         struct mlx5_ifc_rqtc_bits rqt_context;
6040 };
6041
6042 struct mlx5_ifc_create_rq_out_bits {
6043         u8         status[0x8];
6044         u8         reserved_at_8[0x18];
6045
6046         u8         syndrome[0x20];
6047
6048         u8         reserved_at_40[0x8];
6049         u8         rqn[0x18];
6050
6051         u8         reserved_at_60[0x20];
6052 };
6053
6054 struct mlx5_ifc_create_rq_in_bits {
6055         u8         opcode[0x10];
6056         u8         reserved_at_10[0x10];
6057
6058         u8         reserved_at_20[0x10];
6059         u8         op_mod[0x10];
6060
6061         u8         reserved_at_40[0xc0];
6062
6063         struct mlx5_ifc_rqc_bits ctx;
6064 };
6065
6066 struct mlx5_ifc_create_rmp_out_bits {
6067         u8         status[0x8];
6068         u8         reserved_at_8[0x18];
6069
6070         u8         syndrome[0x20];
6071
6072         u8         reserved_at_40[0x8];
6073         u8         rmpn[0x18];
6074
6075         u8         reserved_at_60[0x20];
6076 };
6077
6078 struct mlx5_ifc_create_rmp_in_bits {
6079         u8         opcode[0x10];
6080         u8         reserved_at_10[0x10];
6081
6082         u8         reserved_at_20[0x10];
6083         u8         op_mod[0x10];
6084
6085         u8         reserved_at_40[0xc0];
6086
6087         struct mlx5_ifc_rmpc_bits ctx;
6088 };
6089
6090 struct mlx5_ifc_create_qp_out_bits {
6091         u8         status[0x8];
6092         u8         reserved_at_8[0x18];
6093
6094         u8         syndrome[0x20];
6095
6096         u8         reserved_at_40[0x8];
6097         u8         qpn[0x18];
6098
6099         u8         reserved_at_60[0x20];
6100 };
6101
6102 struct mlx5_ifc_create_qp_in_bits {
6103         u8         opcode[0x10];
6104         u8         reserved_at_10[0x10];
6105
6106         u8         reserved_at_20[0x10];
6107         u8         op_mod[0x10];
6108
6109         u8         reserved_at_40[0x40];
6110
6111         u8         opt_param_mask[0x20];
6112
6113         u8         reserved_at_a0[0x20];
6114
6115         struct mlx5_ifc_qpc_bits qpc;
6116
6117         u8         reserved_at_800[0x80];
6118
6119         u8         pas[0][0x40];
6120 };
6121
6122 struct mlx5_ifc_create_psv_out_bits {
6123         u8         status[0x8];
6124         u8         reserved_at_8[0x18];
6125
6126         u8         syndrome[0x20];
6127
6128         u8         reserved_at_40[0x40];
6129
6130         u8         reserved_at_80[0x8];
6131         u8         psv0_index[0x18];
6132
6133         u8         reserved_at_a0[0x8];
6134         u8         psv1_index[0x18];
6135
6136         u8         reserved_at_c0[0x8];
6137         u8         psv2_index[0x18];
6138
6139         u8         reserved_at_e0[0x8];
6140         u8         psv3_index[0x18];
6141 };
6142
6143 struct mlx5_ifc_create_psv_in_bits {
6144         u8         opcode[0x10];
6145         u8         reserved_at_10[0x10];
6146
6147         u8         reserved_at_20[0x10];
6148         u8         op_mod[0x10];
6149
6150         u8         num_psv[0x4];
6151         u8         reserved_at_44[0x4];
6152         u8         pd[0x18];
6153
6154         u8         reserved_at_60[0x20];
6155 };
6156
6157 struct mlx5_ifc_create_mkey_out_bits {
6158         u8         status[0x8];
6159         u8         reserved_at_8[0x18];
6160
6161         u8         syndrome[0x20];
6162
6163         u8         reserved_at_40[0x8];
6164         u8         mkey_index[0x18];
6165
6166         u8         reserved_at_60[0x20];
6167 };
6168
6169 struct mlx5_ifc_create_mkey_in_bits {
6170         u8         opcode[0x10];
6171         u8         reserved_at_10[0x10];
6172
6173         u8         reserved_at_20[0x10];
6174         u8         op_mod[0x10];
6175
6176         u8         reserved_at_40[0x20];
6177
6178         u8         pg_access[0x1];
6179         u8         reserved_at_61[0x1f];
6180
6181         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6182
6183         u8         reserved_at_280[0x80];
6184
6185         u8         translations_octword_actual_size[0x20];
6186
6187         u8         reserved_at_320[0x560];
6188
6189         u8         klm_pas_mtt[0][0x20];
6190 };
6191
6192 struct mlx5_ifc_create_flow_table_out_bits {
6193         u8         status[0x8];
6194         u8         reserved_at_8[0x18];
6195
6196         u8         syndrome[0x20];
6197
6198         u8         reserved_at_40[0x8];
6199         u8         table_id[0x18];
6200
6201         u8         reserved_at_60[0x20];
6202 };
6203
6204 struct mlx5_ifc_create_flow_table_in_bits {
6205         u8         opcode[0x10];
6206         u8         reserved_at_10[0x10];
6207
6208         u8         reserved_at_20[0x10];
6209         u8         op_mod[0x10];
6210
6211         u8         other_vport[0x1];
6212         u8         reserved_at_41[0xf];
6213         u8         vport_number[0x10];
6214
6215         u8         reserved_at_60[0x20];
6216
6217         u8         table_type[0x8];
6218         u8         reserved_at_88[0x18];
6219
6220         u8         reserved_at_a0[0x20];
6221
6222         u8         encap_en[0x1];
6223         u8         decap_en[0x1];
6224         u8         reserved_at_c2[0x2];
6225         u8         table_miss_mode[0x4];
6226         u8         level[0x8];
6227         u8         reserved_at_d0[0x8];
6228         u8         log_size[0x8];
6229
6230         u8         reserved_at_e0[0x8];
6231         u8         table_miss_id[0x18];
6232
6233         u8         reserved_at_100[0x8];
6234         u8         lag_master_next_table_id[0x18];
6235
6236         u8         reserved_at_120[0x80];
6237 };
6238
6239 struct mlx5_ifc_create_flow_group_out_bits {
6240         u8         status[0x8];
6241         u8         reserved_at_8[0x18];
6242
6243         u8         syndrome[0x20];
6244
6245         u8         reserved_at_40[0x8];
6246         u8         group_id[0x18];
6247
6248         u8         reserved_at_60[0x20];
6249 };
6250
6251 enum {
6252         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6253         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6254         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6255 };
6256
6257 struct mlx5_ifc_create_flow_group_in_bits {
6258         u8         opcode[0x10];
6259         u8         reserved_at_10[0x10];
6260
6261         u8         reserved_at_20[0x10];
6262         u8         op_mod[0x10];
6263
6264         u8         other_vport[0x1];
6265         u8         reserved_at_41[0xf];
6266         u8         vport_number[0x10];
6267
6268         u8         reserved_at_60[0x20];
6269
6270         u8         table_type[0x8];
6271         u8         reserved_at_88[0x18];
6272
6273         u8         reserved_at_a0[0x8];
6274         u8         table_id[0x18];
6275
6276         u8         reserved_at_c0[0x20];
6277
6278         u8         start_flow_index[0x20];
6279
6280         u8         reserved_at_100[0x20];
6281
6282         u8         end_flow_index[0x20];
6283
6284         u8         reserved_at_140[0xa0];
6285
6286         u8         reserved_at_1e0[0x18];
6287         u8         match_criteria_enable[0x8];
6288
6289         struct mlx5_ifc_fte_match_param_bits match_criteria;
6290
6291         u8         reserved_at_1200[0xe00];
6292 };
6293
6294 struct mlx5_ifc_create_eq_out_bits {
6295         u8         status[0x8];
6296         u8         reserved_at_8[0x18];
6297
6298         u8         syndrome[0x20];
6299
6300         u8         reserved_at_40[0x18];
6301         u8         eq_number[0x8];
6302
6303         u8         reserved_at_60[0x20];
6304 };
6305
6306 struct mlx5_ifc_create_eq_in_bits {
6307         u8         opcode[0x10];
6308         u8         reserved_at_10[0x10];
6309
6310         u8         reserved_at_20[0x10];
6311         u8         op_mod[0x10];
6312
6313         u8         reserved_at_40[0x40];
6314
6315         struct mlx5_ifc_eqc_bits eq_context_entry;
6316
6317         u8         reserved_at_280[0x40];
6318
6319         u8         event_bitmask[0x40];
6320
6321         u8         reserved_at_300[0x580];
6322
6323         u8         pas[0][0x40];
6324 };
6325
6326 struct mlx5_ifc_create_dct_out_bits {
6327         u8         status[0x8];
6328         u8         reserved_at_8[0x18];
6329
6330         u8         syndrome[0x20];
6331
6332         u8         reserved_at_40[0x8];
6333         u8         dctn[0x18];
6334
6335         u8         reserved_at_60[0x20];
6336 };
6337
6338 struct mlx5_ifc_create_dct_in_bits {
6339         u8         opcode[0x10];
6340         u8         reserved_at_10[0x10];
6341
6342         u8         reserved_at_20[0x10];
6343         u8         op_mod[0x10];
6344
6345         u8         reserved_at_40[0x40];
6346
6347         struct mlx5_ifc_dctc_bits dct_context_entry;
6348
6349         u8         reserved_at_280[0x180];
6350 };
6351
6352 struct mlx5_ifc_create_cq_out_bits {
6353         u8         status[0x8];
6354         u8         reserved_at_8[0x18];
6355
6356         u8         syndrome[0x20];
6357
6358         u8         reserved_at_40[0x8];
6359         u8         cqn[0x18];
6360
6361         u8         reserved_at_60[0x20];
6362 };
6363
6364 struct mlx5_ifc_create_cq_in_bits {
6365         u8         opcode[0x10];
6366         u8         reserved_at_10[0x10];
6367
6368         u8         reserved_at_20[0x10];
6369         u8         op_mod[0x10];
6370
6371         u8         reserved_at_40[0x40];
6372
6373         struct mlx5_ifc_cqc_bits cq_context;
6374
6375         u8         reserved_at_280[0x600];
6376
6377         u8         pas[0][0x40];
6378 };
6379
6380 struct mlx5_ifc_config_int_moderation_out_bits {
6381         u8         status[0x8];
6382         u8         reserved_at_8[0x18];
6383
6384         u8         syndrome[0x20];
6385
6386         u8         reserved_at_40[0x4];
6387         u8         min_delay[0xc];
6388         u8         int_vector[0x10];
6389
6390         u8         reserved_at_60[0x20];
6391 };
6392
6393 enum {
6394         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6395         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6396 };
6397
6398 struct mlx5_ifc_config_int_moderation_in_bits {
6399         u8         opcode[0x10];
6400         u8         reserved_at_10[0x10];
6401
6402         u8         reserved_at_20[0x10];
6403         u8         op_mod[0x10];
6404
6405         u8         reserved_at_40[0x4];
6406         u8         min_delay[0xc];
6407         u8         int_vector[0x10];
6408
6409         u8         reserved_at_60[0x20];
6410 };
6411
6412 struct mlx5_ifc_attach_to_mcg_out_bits {
6413         u8         status[0x8];
6414         u8         reserved_at_8[0x18];
6415
6416         u8         syndrome[0x20];
6417
6418         u8         reserved_at_40[0x40];
6419 };
6420
6421 struct mlx5_ifc_attach_to_mcg_in_bits {
6422         u8         opcode[0x10];
6423         u8         reserved_at_10[0x10];
6424
6425         u8         reserved_at_20[0x10];
6426         u8         op_mod[0x10];
6427
6428         u8         reserved_at_40[0x8];
6429         u8         qpn[0x18];
6430
6431         u8         reserved_at_60[0x20];
6432
6433         u8         multicast_gid[16][0x8];
6434 };
6435
6436 struct mlx5_ifc_arm_xrq_out_bits {
6437         u8         status[0x8];
6438         u8         reserved_at_8[0x18];
6439
6440         u8         syndrome[0x20];
6441
6442         u8         reserved_at_40[0x40];
6443 };
6444
6445 struct mlx5_ifc_arm_xrq_in_bits {
6446         u8         opcode[0x10];
6447         u8         reserved_at_10[0x10];
6448
6449         u8         reserved_at_20[0x10];
6450         u8         op_mod[0x10];
6451
6452         u8         reserved_at_40[0x8];
6453         u8         xrqn[0x18];
6454
6455         u8         reserved_at_60[0x10];
6456         u8         lwm[0x10];
6457 };
6458
6459 struct mlx5_ifc_arm_xrc_srq_out_bits {
6460         u8         status[0x8];
6461         u8         reserved_at_8[0x18];
6462
6463         u8         syndrome[0x20];
6464
6465         u8         reserved_at_40[0x40];
6466 };
6467
6468 enum {
6469         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
6470 };
6471
6472 struct mlx5_ifc_arm_xrc_srq_in_bits {
6473         u8         opcode[0x10];
6474         u8         reserved_at_10[0x10];
6475
6476         u8         reserved_at_20[0x10];
6477         u8         op_mod[0x10];
6478
6479         u8         reserved_at_40[0x8];
6480         u8         xrc_srqn[0x18];
6481
6482         u8         reserved_at_60[0x10];
6483         u8         lwm[0x10];
6484 };
6485
6486 struct mlx5_ifc_arm_rq_out_bits {
6487         u8         status[0x8];
6488         u8         reserved_at_8[0x18];
6489
6490         u8         syndrome[0x20];
6491
6492         u8         reserved_at_40[0x40];
6493 };
6494
6495 enum {
6496         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6497         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6498 };
6499
6500 struct mlx5_ifc_arm_rq_in_bits {
6501         u8         opcode[0x10];
6502         u8         reserved_at_10[0x10];
6503
6504         u8         reserved_at_20[0x10];
6505         u8         op_mod[0x10];
6506
6507         u8         reserved_at_40[0x8];
6508         u8         srq_number[0x18];
6509
6510         u8         reserved_at_60[0x10];
6511         u8         lwm[0x10];
6512 };
6513
6514 struct mlx5_ifc_arm_dct_out_bits {
6515         u8         status[0x8];
6516         u8         reserved_at_8[0x18];
6517
6518         u8         syndrome[0x20];
6519
6520         u8         reserved_at_40[0x40];
6521 };
6522
6523 struct mlx5_ifc_arm_dct_in_bits {
6524         u8         opcode[0x10];
6525         u8         reserved_at_10[0x10];
6526
6527         u8         reserved_at_20[0x10];
6528         u8         op_mod[0x10];
6529
6530         u8         reserved_at_40[0x8];
6531         u8         dct_number[0x18];
6532
6533         u8         reserved_at_60[0x20];
6534 };
6535
6536 struct mlx5_ifc_alloc_xrcd_out_bits {
6537         u8         status[0x8];
6538         u8         reserved_at_8[0x18];
6539
6540         u8         syndrome[0x20];
6541
6542         u8         reserved_at_40[0x8];
6543         u8         xrcd[0x18];
6544
6545         u8         reserved_at_60[0x20];
6546 };
6547
6548 struct mlx5_ifc_alloc_xrcd_in_bits {
6549         u8         opcode[0x10];
6550         u8         reserved_at_10[0x10];
6551
6552         u8         reserved_at_20[0x10];
6553         u8         op_mod[0x10];
6554
6555         u8         reserved_at_40[0x40];
6556 };
6557
6558 struct mlx5_ifc_alloc_uar_out_bits {
6559         u8         status[0x8];
6560         u8         reserved_at_8[0x18];
6561
6562         u8         syndrome[0x20];
6563
6564         u8         reserved_at_40[0x8];
6565         u8         uar[0x18];
6566
6567         u8         reserved_at_60[0x20];
6568 };
6569
6570 struct mlx5_ifc_alloc_uar_in_bits {
6571         u8         opcode[0x10];
6572         u8         reserved_at_10[0x10];
6573
6574         u8         reserved_at_20[0x10];
6575         u8         op_mod[0x10];
6576
6577         u8         reserved_at_40[0x40];
6578 };
6579
6580 struct mlx5_ifc_alloc_transport_domain_out_bits {
6581         u8         status[0x8];
6582         u8         reserved_at_8[0x18];
6583
6584         u8         syndrome[0x20];
6585
6586         u8         reserved_at_40[0x8];
6587         u8         transport_domain[0x18];
6588
6589         u8         reserved_at_60[0x20];
6590 };
6591
6592 struct mlx5_ifc_alloc_transport_domain_in_bits {
6593         u8         opcode[0x10];
6594         u8         reserved_at_10[0x10];
6595
6596         u8         reserved_at_20[0x10];
6597         u8         op_mod[0x10];
6598
6599         u8         reserved_at_40[0x40];
6600 };
6601
6602 struct mlx5_ifc_alloc_q_counter_out_bits {
6603         u8         status[0x8];
6604         u8         reserved_at_8[0x18];
6605
6606         u8         syndrome[0x20];
6607
6608         u8         reserved_at_40[0x18];
6609         u8         counter_set_id[0x8];
6610
6611         u8         reserved_at_60[0x20];
6612 };
6613
6614 struct mlx5_ifc_alloc_q_counter_in_bits {
6615         u8         opcode[0x10];
6616         u8         reserved_at_10[0x10];
6617
6618         u8         reserved_at_20[0x10];
6619         u8         op_mod[0x10];
6620
6621         u8         reserved_at_40[0x40];
6622 };
6623
6624 struct mlx5_ifc_alloc_pd_out_bits {
6625         u8         status[0x8];
6626         u8         reserved_at_8[0x18];
6627
6628         u8         syndrome[0x20];
6629
6630         u8         reserved_at_40[0x8];
6631         u8         pd[0x18];
6632
6633         u8         reserved_at_60[0x20];
6634 };
6635
6636 struct mlx5_ifc_alloc_pd_in_bits {
6637         u8         opcode[0x10];
6638         u8         reserved_at_10[0x10];
6639
6640         u8         reserved_at_20[0x10];
6641         u8         op_mod[0x10];
6642
6643         u8         reserved_at_40[0x40];
6644 };
6645
6646 struct mlx5_ifc_alloc_flow_counter_out_bits {
6647         u8         status[0x8];
6648         u8         reserved_at_8[0x18];
6649
6650         u8         syndrome[0x20];
6651
6652         u8         reserved_at_40[0x10];
6653         u8         flow_counter_id[0x10];
6654
6655         u8         reserved_at_60[0x20];
6656 };
6657
6658 struct mlx5_ifc_alloc_flow_counter_in_bits {
6659         u8         opcode[0x10];
6660         u8         reserved_at_10[0x10];
6661
6662         u8         reserved_at_20[0x10];
6663         u8         op_mod[0x10];
6664
6665         u8         reserved_at_40[0x40];
6666 };
6667
6668 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6669         u8         status[0x8];
6670         u8         reserved_at_8[0x18];
6671
6672         u8         syndrome[0x20];
6673
6674         u8         reserved_at_40[0x40];
6675 };
6676
6677 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6678         u8         opcode[0x10];
6679         u8         reserved_at_10[0x10];
6680
6681         u8         reserved_at_20[0x10];
6682         u8         op_mod[0x10];
6683
6684         u8         reserved_at_40[0x20];
6685
6686         u8         reserved_at_60[0x10];
6687         u8         vxlan_udp_port[0x10];
6688 };
6689
6690 struct mlx5_ifc_set_rate_limit_out_bits {
6691         u8         status[0x8];
6692         u8         reserved_at_8[0x18];
6693
6694         u8         syndrome[0x20];
6695
6696         u8         reserved_at_40[0x40];
6697 };
6698
6699 struct mlx5_ifc_set_rate_limit_in_bits {
6700         u8         opcode[0x10];
6701         u8         reserved_at_10[0x10];
6702
6703         u8         reserved_at_20[0x10];
6704         u8         op_mod[0x10];
6705
6706         u8         reserved_at_40[0x10];
6707         u8         rate_limit_index[0x10];
6708
6709         u8         reserved_at_60[0x20];
6710
6711         u8         rate_limit[0x20];
6712 };
6713
6714 struct mlx5_ifc_access_register_out_bits {
6715         u8         status[0x8];
6716         u8         reserved_at_8[0x18];
6717
6718         u8         syndrome[0x20];
6719
6720         u8         reserved_at_40[0x40];
6721
6722         u8         register_data[0][0x20];
6723 };
6724
6725 enum {
6726         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
6727         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
6728 };
6729
6730 struct mlx5_ifc_access_register_in_bits {
6731         u8         opcode[0x10];
6732         u8         reserved_at_10[0x10];
6733
6734         u8         reserved_at_20[0x10];
6735         u8         op_mod[0x10];
6736
6737         u8         reserved_at_40[0x10];
6738         u8         register_id[0x10];
6739
6740         u8         argument[0x20];
6741
6742         u8         register_data[0][0x20];
6743 };
6744
6745 struct mlx5_ifc_sltp_reg_bits {
6746         u8         status[0x4];
6747         u8         version[0x4];
6748         u8         local_port[0x8];
6749         u8         pnat[0x2];
6750         u8         reserved_at_12[0x2];
6751         u8         lane[0x4];
6752         u8         reserved_at_18[0x8];
6753
6754         u8         reserved_at_20[0x20];
6755
6756         u8         reserved_at_40[0x7];
6757         u8         polarity[0x1];
6758         u8         ob_tap0[0x8];
6759         u8         ob_tap1[0x8];
6760         u8         ob_tap2[0x8];
6761
6762         u8         reserved_at_60[0xc];
6763         u8         ob_preemp_mode[0x4];
6764         u8         ob_reg[0x8];
6765         u8         ob_bias[0x8];
6766
6767         u8         reserved_at_80[0x20];
6768 };
6769
6770 struct mlx5_ifc_slrg_reg_bits {
6771         u8         status[0x4];
6772         u8         version[0x4];
6773         u8         local_port[0x8];
6774         u8         pnat[0x2];
6775         u8         reserved_at_12[0x2];
6776         u8         lane[0x4];
6777         u8         reserved_at_18[0x8];
6778
6779         u8         time_to_link_up[0x10];
6780         u8         reserved_at_30[0xc];
6781         u8         grade_lane_speed[0x4];
6782
6783         u8         grade_version[0x8];
6784         u8         grade[0x18];
6785
6786         u8         reserved_at_60[0x4];
6787         u8         height_grade_type[0x4];
6788         u8         height_grade[0x18];
6789
6790         u8         height_dz[0x10];
6791         u8         height_dv[0x10];
6792
6793         u8         reserved_at_a0[0x10];
6794         u8         height_sigma[0x10];
6795
6796         u8         reserved_at_c0[0x20];
6797
6798         u8         reserved_at_e0[0x4];
6799         u8         phase_grade_type[0x4];
6800         u8         phase_grade[0x18];
6801
6802         u8         reserved_at_100[0x8];
6803         u8         phase_eo_pos[0x8];
6804         u8         reserved_at_110[0x8];
6805         u8         phase_eo_neg[0x8];
6806
6807         u8         ffe_set_tested[0x10];
6808         u8         test_errors_per_lane[0x10];
6809 };
6810
6811 struct mlx5_ifc_pvlc_reg_bits {
6812         u8         reserved_at_0[0x8];
6813         u8         local_port[0x8];
6814         u8         reserved_at_10[0x10];
6815
6816         u8         reserved_at_20[0x1c];
6817         u8         vl_hw_cap[0x4];
6818
6819         u8         reserved_at_40[0x1c];
6820         u8         vl_admin[0x4];
6821
6822         u8         reserved_at_60[0x1c];
6823         u8         vl_operational[0x4];
6824 };
6825
6826 struct mlx5_ifc_pude_reg_bits {
6827         u8         swid[0x8];
6828         u8         local_port[0x8];
6829         u8         reserved_at_10[0x4];
6830         u8         admin_status[0x4];
6831         u8         reserved_at_18[0x4];
6832         u8         oper_status[0x4];
6833
6834         u8         reserved_at_20[0x60];
6835 };
6836
6837 struct mlx5_ifc_ptys_reg_bits {
6838         u8         an_disable_cap[0x1];
6839         u8         an_disable_admin[0x1];
6840         u8         reserved_at_2[0x6];
6841         u8         local_port[0x8];
6842         u8         reserved_at_10[0xd];
6843         u8         proto_mask[0x3];
6844
6845         u8         an_status[0x4];
6846         u8         reserved_at_24[0x3c];
6847
6848         u8         eth_proto_capability[0x20];
6849
6850         u8         ib_link_width_capability[0x10];
6851         u8         ib_proto_capability[0x10];
6852
6853         u8         reserved_at_a0[0x20];
6854
6855         u8         eth_proto_admin[0x20];
6856
6857         u8         ib_link_width_admin[0x10];
6858         u8         ib_proto_admin[0x10];
6859
6860         u8         reserved_at_100[0x20];
6861
6862         u8         eth_proto_oper[0x20];
6863
6864         u8         ib_link_width_oper[0x10];
6865         u8         ib_proto_oper[0x10];
6866
6867         u8         reserved_at_160[0x20];
6868
6869         u8         eth_proto_lp_advertise[0x20];
6870
6871         u8         reserved_at_1a0[0x60];
6872 };
6873
6874 struct mlx5_ifc_mlcr_reg_bits {
6875         u8         reserved_at_0[0x8];
6876         u8         local_port[0x8];
6877         u8         reserved_at_10[0x20];
6878
6879         u8         beacon_duration[0x10];
6880         u8         reserved_at_40[0x10];
6881
6882         u8         beacon_remain[0x10];
6883 };
6884
6885 struct mlx5_ifc_ptas_reg_bits {
6886         u8         reserved_at_0[0x20];
6887
6888         u8         algorithm_options[0x10];
6889         u8         reserved_at_30[0x4];
6890         u8         repetitions_mode[0x4];
6891         u8         num_of_repetitions[0x8];
6892
6893         u8         grade_version[0x8];
6894         u8         height_grade_type[0x4];
6895         u8         phase_grade_type[0x4];
6896         u8         height_grade_weight[0x8];
6897         u8         phase_grade_weight[0x8];
6898
6899         u8         gisim_measure_bits[0x10];
6900         u8         adaptive_tap_measure_bits[0x10];
6901
6902         u8         ber_bath_high_error_threshold[0x10];
6903         u8         ber_bath_mid_error_threshold[0x10];
6904
6905         u8         ber_bath_low_error_threshold[0x10];
6906         u8         one_ratio_high_threshold[0x10];
6907
6908         u8         one_ratio_high_mid_threshold[0x10];
6909         u8         one_ratio_low_mid_threshold[0x10];
6910
6911         u8         one_ratio_low_threshold[0x10];
6912         u8         ndeo_error_threshold[0x10];
6913
6914         u8         mixer_offset_step_size[0x10];
6915         u8         reserved_at_110[0x8];
6916         u8         mix90_phase_for_voltage_bath[0x8];
6917
6918         u8         mixer_offset_start[0x10];
6919         u8         mixer_offset_end[0x10];
6920
6921         u8         reserved_at_140[0x15];
6922         u8         ber_test_time[0xb];
6923 };
6924
6925 struct mlx5_ifc_pspa_reg_bits {
6926         u8         swid[0x8];
6927         u8         local_port[0x8];
6928         u8         sub_port[0x8];
6929         u8         reserved_at_18[0x8];
6930
6931         u8         reserved_at_20[0x20];
6932 };
6933
6934 struct mlx5_ifc_pqdr_reg_bits {
6935         u8         reserved_at_0[0x8];
6936         u8         local_port[0x8];
6937         u8         reserved_at_10[0x5];
6938         u8         prio[0x3];
6939         u8         reserved_at_18[0x6];
6940         u8         mode[0x2];
6941
6942         u8         reserved_at_20[0x20];
6943
6944         u8         reserved_at_40[0x10];
6945         u8         min_threshold[0x10];
6946
6947         u8         reserved_at_60[0x10];
6948         u8         max_threshold[0x10];
6949
6950         u8         reserved_at_80[0x10];
6951         u8         mark_probability_denominator[0x10];
6952
6953         u8         reserved_at_a0[0x60];
6954 };
6955
6956 struct mlx5_ifc_ppsc_reg_bits {
6957         u8         reserved_at_0[0x8];
6958         u8         local_port[0x8];
6959         u8         reserved_at_10[0x10];
6960
6961         u8         reserved_at_20[0x60];
6962
6963         u8         reserved_at_80[0x1c];
6964         u8         wrps_admin[0x4];
6965
6966         u8         reserved_at_a0[0x1c];
6967         u8         wrps_status[0x4];
6968
6969         u8         reserved_at_c0[0x8];
6970         u8         up_threshold[0x8];
6971         u8         reserved_at_d0[0x8];
6972         u8         down_threshold[0x8];
6973
6974         u8         reserved_at_e0[0x20];
6975
6976         u8         reserved_at_100[0x1c];
6977         u8         srps_admin[0x4];
6978
6979         u8         reserved_at_120[0x1c];
6980         u8         srps_status[0x4];
6981
6982         u8         reserved_at_140[0x40];
6983 };
6984
6985 struct mlx5_ifc_pplr_reg_bits {
6986         u8         reserved_at_0[0x8];
6987         u8         local_port[0x8];
6988         u8         reserved_at_10[0x10];
6989
6990         u8         reserved_at_20[0x8];
6991         u8         lb_cap[0x8];
6992         u8         reserved_at_30[0x8];
6993         u8         lb_en[0x8];
6994 };
6995
6996 struct mlx5_ifc_pplm_reg_bits {
6997         u8         reserved_at_0[0x8];
6998         u8         local_port[0x8];
6999         u8         reserved_at_10[0x10];
7000
7001         u8         reserved_at_20[0x20];
7002
7003         u8         port_profile_mode[0x8];
7004         u8         static_port_profile[0x8];
7005         u8         active_port_profile[0x8];
7006         u8         reserved_at_58[0x8];
7007
7008         u8         retransmission_active[0x8];
7009         u8         fec_mode_active[0x18];
7010
7011         u8         reserved_at_80[0x20];
7012 };
7013
7014 struct mlx5_ifc_ppcnt_reg_bits {
7015         u8         swid[0x8];
7016         u8         local_port[0x8];
7017         u8         pnat[0x2];
7018         u8         reserved_at_12[0x8];
7019         u8         grp[0x6];
7020
7021         u8         clr[0x1];
7022         u8         reserved_at_21[0x1c];
7023         u8         prio_tc[0x3];
7024
7025         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7026 };
7027
7028 struct mlx5_ifc_ppad_reg_bits {
7029         u8         reserved_at_0[0x3];
7030         u8         single_mac[0x1];
7031         u8         reserved_at_4[0x4];
7032         u8         local_port[0x8];
7033         u8         mac_47_32[0x10];
7034
7035         u8         mac_31_0[0x20];
7036
7037         u8         reserved_at_40[0x40];
7038 };
7039
7040 struct mlx5_ifc_pmtu_reg_bits {
7041         u8         reserved_at_0[0x8];
7042         u8         local_port[0x8];
7043         u8         reserved_at_10[0x10];
7044
7045         u8         max_mtu[0x10];
7046         u8         reserved_at_30[0x10];
7047
7048         u8         admin_mtu[0x10];
7049         u8         reserved_at_50[0x10];
7050
7051         u8         oper_mtu[0x10];
7052         u8         reserved_at_70[0x10];
7053 };
7054
7055 struct mlx5_ifc_pmpr_reg_bits {
7056         u8         reserved_at_0[0x8];
7057         u8         module[0x8];
7058         u8         reserved_at_10[0x10];
7059
7060         u8         reserved_at_20[0x18];
7061         u8         attenuation_5g[0x8];
7062
7063         u8         reserved_at_40[0x18];
7064         u8         attenuation_7g[0x8];
7065
7066         u8         reserved_at_60[0x18];
7067         u8         attenuation_12g[0x8];
7068 };
7069
7070 struct mlx5_ifc_pmpe_reg_bits {
7071         u8         reserved_at_0[0x8];
7072         u8         module[0x8];
7073         u8         reserved_at_10[0xc];
7074         u8         module_status[0x4];
7075
7076         u8         reserved_at_20[0x60];
7077 };
7078
7079 struct mlx5_ifc_pmpc_reg_bits {
7080         u8         module_state_updated[32][0x8];
7081 };
7082
7083 struct mlx5_ifc_pmlpn_reg_bits {
7084         u8         reserved_at_0[0x4];
7085         u8         mlpn_status[0x4];
7086         u8         local_port[0x8];
7087         u8         reserved_at_10[0x10];
7088
7089         u8         e[0x1];
7090         u8         reserved_at_21[0x1f];
7091 };
7092
7093 struct mlx5_ifc_pmlp_reg_bits {
7094         u8         rxtx[0x1];
7095         u8         reserved_at_1[0x7];
7096         u8         local_port[0x8];
7097         u8         reserved_at_10[0x8];
7098         u8         width[0x8];
7099
7100         u8         lane0_module_mapping[0x20];
7101
7102         u8         lane1_module_mapping[0x20];
7103
7104         u8         lane2_module_mapping[0x20];
7105
7106         u8         lane3_module_mapping[0x20];
7107
7108         u8         reserved_at_a0[0x160];
7109 };
7110
7111 struct mlx5_ifc_pmaos_reg_bits {
7112         u8         reserved_at_0[0x8];
7113         u8         module[0x8];
7114         u8         reserved_at_10[0x4];
7115         u8         admin_status[0x4];
7116         u8         reserved_at_18[0x4];
7117         u8         oper_status[0x4];
7118
7119         u8         ase[0x1];
7120         u8         ee[0x1];
7121         u8         reserved_at_22[0x1c];
7122         u8         e[0x2];
7123
7124         u8         reserved_at_40[0x40];
7125 };
7126
7127 struct mlx5_ifc_plpc_reg_bits {
7128         u8         reserved_at_0[0x4];
7129         u8         profile_id[0xc];
7130         u8         reserved_at_10[0x4];
7131         u8         proto_mask[0x4];
7132         u8         reserved_at_18[0x8];
7133
7134         u8         reserved_at_20[0x10];
7135         u8         lane_speed[0x10];
7136
7137         u8         reserved_at_40[0x17];
7138         u8         lpbf[0x1];
7139         u8         fec_mode_policy[0x8];
7140
7141         u8         retransmission_capability[0x8];
7142         u8         fec_mode_capability[0x18];
7143
7144         u8         retransmission_support_admin[0x8];
7145         u8         fec_mode_support_admin[0x18];
7146
7147         u8         retransmission_request_admin[0x8];
7148         u8         fec_mode_request_admin[0x18];
7149
7150         u8         reserved_at_c0[0x80];
7151 };
7152
7153 struct mlx5_ifc_plib_reg_bits {
7154         u8         reserved_at_0[0x8];
7155         u8         local_port[0x8];
7156         u8         reserved_at_10[0x8];
7157         u8         ib_port[0x8];
7158
7159         u8         reserved_at_20[0x60];
7160 };
7161
7162 struct mlx5_ifc_plbf_reg_bits {
7163         u8         reserved_at_0[0x8];
7164         u8         local_port[0x8];
7165         u8         reserved_at_10[0xd];
7166         u8         lbf_mode[0x3];
7167
7168         u8         reserved_at_20[0x20];
7169 };
7170
7171 struct mlx5_ifc_pipg_reg_bits {
7172         u8         reserved_at_0[0x8];
7173         u8         local_port[0x8];
7174         u8         reserved_at_10[0x10];
7175
7176         u8         dic[0x1];
7177         u8         reserved_at_21[0x19];
7178         u8         ipg[0x4];
7179         u8         reserved_at_3e[0x2];
7180 };
7181
7182 struct mlx5_ifc_pifr_reg_bits {
7183         u8         reserved_at_0[0x8];
7184         u8         local_port[0x8];
7185         u8         reserved_at_10[0x10];
7186
7187         u8         reserved_at_20[0xe0];
7188
7189         u8         port_filter[8][0x20];
7190
7191         u8         port_filter_update_en[8][0x20];
7192 };
7193
7194 struct mlx5_ifc_pfcc_reg_bits {
7195         u8         reserved_at_0[0x8];
7196         u8         local_port[0x8];
7197         u8         reserved_at_10[0x10];
7198
7199         u8         ppan[0x4];
7200         u8         reserved_at_24[0x4];
7201         u8         prio_mask_tx[0x8];
7202         u8         reserved_at_30[0x8];
7203         u8         prio_mask_rx[0x8];
7204
7205         u8         pptx[0x1];
7206         u8         aptx[0x1];
7207         u8         reserved_at_42[0x6];
7208         u8         pfctx[0x8];
7209         u8         reserved_at_50[0x10];
7210
7211         u8         pprx[0x1];
7212         u8         aprx[0x1];
7213         u8         reserved_at_62[0x6];
7214         u8         pfcrx[0x8];
7215         u8         reserved_at_70[0x10];
7216
7217         u8         reserved_at_80[0x80];
7218 };
7219
7220 struct mlx5_ifc_pelc_reg_bits {
7221         u8         op[0x4];
7222         u8         reserved_at_4[0x4];
7223         u8         local_port[0x8];
7224         u8         reserved_at_10[0x10];
7225
7226         u8         op_admin[0x8];
7227         u8         op_capability[0x8];
7228         u8         op_request[0x8];
7229         u8         op_active[0x8];
7230
7231         u8         admin[0x40];
7232
7233         u8         capability[0x40];
7234
7235         u8         request[0x40];
7236
7237         u8         active[0x40];
7238
7239         u8         reserved_at_140[0x80];
7240 };
7241
7242 struct mlx5_ifc_peir_reg_bits {
7243         u8         reserved_at_0[0x8];
7244         u8         local_port[0x8];
7245         u8         reserved_at_10[0x10];
7246
7247         u8         reserved_at_20[0xc];
7248         u8         error_count[0x4];
7249         u8         reserved_at_30[0x10];
7250
7251         u8         reserved_at_40[0xc];
7252         u8         lane[0x4];
7253         u8         reserved_at_50[0x8];
7254         u8         error_type[0x8];
7255 };
7256
7257 struct mlx5_ifc_pcap_reg_bits {
7258         u8         reserved_at_0[0x8];
7259         u8         local_port[0x8];
7260         u8         reserved_at_10[0x10];
7261
7262         u8         port_capability_mask[4][0x20];
7263 };
7264
7265 struct mlx5_ifc_paos_reg_bits {
7266         u8         swid[0x8];
7267         u8         local_port[0x8];
7268         u8         reserved_at_10[0x4];
7269         u8         admin_status[0x4];
7270         u8         reserved_at_18[0x4];
7271         u8         oper_status[0x4];
7272
7273         u8         ase[0x1];
7274         u8         ee[0x1];
7275         u8         reserved_at_22[0x1c];
7276         u8         e[0x2];
7277
7278         u8         reserved_at_40[0x40];
7279 };
7280
7281 struct mlx5_ifc_pamp_reg_bits {
7282         u8         reserved_at_0[0x8];
7283         u8         opamp_group[0x8];
7284         u8         reserved_at_10[0xc];
7285         u8         opamp_group_type[0x4];
7286
7287         u8         start_index[0x10];
7288         u8         reserved_at_30[0x4];
7289         u8         num_of_indices[0xc];
7290
7291         u8         index_data[18][0x10];
7292 };
7293
7294 struct mlx5_ifc_pcmr_reg_bits {
7295         u8         reserved_at_0[0x8];
7296         u8         local_port[0x8];
7297         u8         reserved_at_10[0x2e];
7298         u8         fcs_cap[0x1];
7299         u8         reserved_at_3f[0x1f];
7300         u8         fcs_chk[0x1];
7301         u8         reserved_at_5f[0x1];
7302 };
7303
7304 struct mlx5_ifc_lane_2_module_mapping_bits {
7305         u8         reserved_at_0[0x6];
7306         u8         rx_lane[0x2];
7307         u8         reserved_at_8[0x6];
7308         u8         tx_lane[0x2];
7309         u8         reserved_at_10[0x8];
7310         u8         module[0x8];
7311 };
7312
7313 struct mlx5_ifc_bufferx_reg_bits {
7314         u8         reserved_at_0[0x6];
7315         u8         lossy[0x1];
7316         u8         epsb[0x1];
7317         u8         reserved_at_8[0xc];
7318         u8         size[0xc];
7319
7320         u8         xoff_threshold[0x10];
7321         u8         xon_threshold[0x10];
7322 };
7323
7324 struct mlx5_ifc_set_node_in_bits {
7325         u8         node_description[64][0x8];
7326 };
7327
7328 struct mlx5_ifc_register_power_settings_bits {
7329         u8         reserved_at_0[0x18];
7330         u8         power_settings_level[0x8];
7331
7332         u8         reserved_at_20[0x60];
7333 };
7334
7335 struct mlx5_ifc_register_host_endianness_bits {
7336         u8         he[0x1];
7337         u8         reserved_at_1[0x1f];
7338
7339         u8         reserved_at_20[0x60];
7340 };
7341
7342 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7343         u8         reserved_at_0[0x20];
7344
7345         u8         mkey[0x20];
7346
7347         u8         addressh_63_32[0x20];
7348
7349         u8         addressl_31_0[0x20];
7350 };
7351
7352 struct mlx5_ifc_ud_adrs_vector_bits {
7353         u8         dc_key[0x40];
7354
7355         u8         ext[0x1];
7356         u8         reserved_at_41[0x7];
7357         u8         destination_qp_dct[0x18];
7358
7359         u8         static_rate[0x4];
7360         u8         sl_eth_prio[0x4];
7361         u8         fl[0x1];
7362         u8         mlid[0x7];
7363         u8         rlid_udp_sport[0x10];
7364
7365         u8         reserved_at_80[0x20];
7366
7367         u8         rmac_47_16[0x20];
7368
7369         u8         rmac_15_0[0x10];
7370         u8         tclass[0x8];
7371         u8         hop_limit[0x8];
7372
7373         u8         reserved_at_e0[0x1];
7374         u8         grh[0x1];
7375         u8         reserved_at_e2[0x2];
7376         u8         src_addr_index[0x8];
7377         u8         flow_label[0x14];
7378
7379         u8         rgid_rip[16][0x8];
7380 };
7381
7382 struct mlx5_ifc_pages_req_event_bits {
7383         u8         reserved_at_0[0x10];
7384         u8         function_id[0x10];
7385
7386         u8         num_pages[0x20];
7387
7388         u8         reserved_at_40[0xa0];
7389 };
7390
7391 struct mlx5_ifc_eqe_bits {
7392         u8         reserved_at_0[0x8];
7393         u8         event_type[0x8];
7394         u8         reserved_at_10[0x8];
7395         u8         event_sub_type[0x8];
7396
7397         u8         reserved_at_20[0xe0];
7398
7399         union mlx5_ifc_event_auto_bits event_data;
7400
7401         u8         reserved_at_1e0[0x10];
7402         u8         signature[0x8];
7403         u8         reserved_at_1f8[0x7];
7404         u8         owner[0x1];
7405 };
7406
7407 enum {
7408         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
7409 };
7410
7411 struct mlx5_ifc_cmd_queue_entry_bits {
7412         u8         type[0x8];
7413         u8         reserved_at_8[0x18];
7414
7415         u8         input_length[0x20];
7416
7417         u8         input_mailbox_pointer_63_32[0x20];
7418
7419         u8         input_mailbox_pointer_31_9[0x17];
7420         u8         reserved_at_77[0x9];
7421
7422         u8         command_input_inline_data[16][0x8];
7423
7424         u8         command_output_inline_data[16][0x8];
7425
7426         u8         output_mailbox_pointer_63_32[0x20];
7427
7428         u8         output_mailbox_pointer_31_9[0x17];
7429         u8         reserved_at_1b7[0x9];
7430
7431         u8         output_length[0x20];
7432
7433         u8         token[0x8];
7434         u8         signature[0x8];
7435         u8         reserved_at_1f0[0x8];
7436         u8         status[0x7];
7437         u8         ownership[0x1];
7438 };
7439
7440 struct mlx5_ifc_cmd_out_bits {
7441         u8         status[0x8];
7442         u8         reserved_at_8[0x18];
7443
7444         u8         syndrome[0x20];
7445
7446         u8         command_output[0x20];
7447 };
7448
7449 struct mlx5_ifc_cmd_in_bits {
7450         u8         opcode[0x10];
7451         u8         reserved_at_10[0x10];
7452
7453         u8         reserved_at_20[0x10];
7454         u8         op_mod[0x10];
7455
7456         u8         command[0][0x20];
7457 };
7458
7459 struct mlx5_ifc_cmd_if_box_bits {
7460         u8         mailbox_data[512][0x8];
7461
7462         u8         reserved_at_1000[0x180];
7463
7464         u8         next_pointer_63_32[0x20];
7465
7466         u8         next_pointer_31_10[0x16];
7467         u8         reserved_at_11b6[0xa];
7468
7469         u8         block_number[0x20];
7470
7471         u8         reserved_at_11e0[0x8];
7472         u8         token[0x8];
7473         u8         ctrl_signature[0x8];
7474         u8         signature[0x8];
7475 };
7476
7477 struct mlx5_ifc_mtt_bits {
7478         u8         ptag_63_32[0x20];
7479
7480         u8         ptag_31_8[0x18];
7481         u8         reserved_at_38[0x6];
7482         u8         wr_en[0x1];
7483         u8         rd_en[0x1];
7484 };
7485
7486 struct mlx5_ifc_query_wol_rol_out_bits {
7487         u8         status[0x8];
7488         u8         reserved_at_8[0x18];
7489
7490         u8         syndrome[0x20];
7491
7492         u8         reserved_at_40[0x10];
7493         u8         rol_mode[0x8];
7494         u8         wol_mode[0x8];
7495
7496         u8         reserved_at_60[0x20];
7497 };
7498
7499 struct mlx5_ifc_query_wol_rol_in_bits {
7500         u8         opcode[0x10];
7501         u8         reserved_at_10[0x10];
7502
7503         u8         reserved_at_20[0x10];
7504         u8         op_mod[0x10];
7505
7506         u8         reserved_at_40[0x40];
7507 };
7508
7509 struct mlx5_ifc_set_wol_rol_out_bits {
7510         u8         status[0x8];
7511         u8         reserved_at_8[0x18];
7512
7513         u8         syndrome[0x20];
7514
7515         u8         reserved_at_40[0x40];
7516 };
7517
7518 struct mlx5_ifc_set_wol_rol_in_bits {
7519         u8         opcode[0x10];
7520         u8         reserved_at_10[0x10];
7521
7522         u8         reserved_at_20[0x10];
7523         u8         op_mod[0x10];
7524
7525         u8         rol_mode_valid[0x1];
7526         u8         wol_mode_valid[0x1];
7527         u8         reserved_at_42[0xe];
7528         u8         rol_mode[0x8];
7529         u8         wol_mode[0x8];
7530
7531         u8         reserved_at_60[0x20];
7532 };
7533
7534 enum {
7535         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
7536         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
7537         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
7538 };
7539
7540 enum {
7541         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
7542         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
7543         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
7544 };
7545
7546 enum {
7547         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
7548         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
7549         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
7550         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
7551         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
7552         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
7553         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
7554         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
7555         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
7556         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
7557         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
7558 };
7559
7560 struct mlx5_ifc_initial_seg_bits {
7561         u8         fw_rev_minor[0x10];
7562         u8         fw_rev_major[0x10];
7563
7564         u8         cmd_interface_rev[0x10];
7565         u8         fw_rev_subminor[0x10];
7566
7567         u8         reserved_at_40[0x40];
7568
7569         u8         cmdq_phy_addr_63_32[0x20];
7570
7571         u8         cmdq_phy_addr_31_12[0x14];
7572         u8         reserved_at_b4[0x2];
7573         u8         nic_interface[0x2];
7574         u8         log_cmdq_size[0x4];
7575         u8         log_cmdq_stride[0x4];
7576
7577         u8         command_doorbell_vector[0x20];
7578
7579         u8         reserved_at_e0[0xf00];
7580
7581         u8         initializing[0x1];
7582         u8         reserved_at_fe1[0x4];
7583         u8         nic_interface_supported[0x3];
7584         u8         reserved_at_fe8[0x18];
7585
7586         struct mlx5_ifc_health_buffer_bits health_buffer;
7587
7588         u8         no_dram_nic_offset[0x20];
7589
7590         u8         reserved_at_1220[0x6e40];
7591
7592         u8         reserved_at_8060[0x1f];
7593         u8         clear_int[0x1];
7594
7595         u8         health_syndrome[0x8];
7596         u8         health_counter[0x18];
7597
7598         u8         reserved_at_80a0[0x17fc0];
7599 };
7600
7601 union mlx5_ifc_ports_control_registers_document_bits {
7602         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7603         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7604         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7605         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7606         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7607         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7608         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7609         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7610         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7611         struct mlx5_ifc_pamp_reg_bits pamp_reg;
7612         struct mlx5_ifc_paos_reg_bits paos_reg;
7613         struct mlx5_ifc_pcap_reg_bits pcap_reg;
7614         struct mlx5_ifc_peir_reg_bits peir_reg;
7615         struct mlx5_ifc_pelc_reg_bits pelc_reg;
7616         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7617         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7618         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7619         struct mlx5_ifc_pifr_reg_bits pifr_reg;
7620         struct mlx5_ifc_pipg_reg_bits pipg_reg;
7621         struct mlx5_ifc_plbf_reg_bits plbf_reg;
7622         struct mlx5_ifc_plib_reg_bits plib_reg;
7623         struct mlx5_ifc_plpc_reg_bits plpc_reg;
7624         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7625         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7626         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7627         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7628         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7629         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7630         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7631         struct mlx5_ifc_ppad_reg_bits ppad_reg;
7632         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7633         struct mlx5_ifc_pplm_reg_bits pplm_reg;
7634         struct mlx5_ifc_pplr_reg_bits pplr_reg;
7635         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7636         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7637         struct mlx5_ifc_pspa_reg_bits pspa_reg;
7638         struct mlx5_ifc_ptas_reg_bits ptas_reg;
7639         struct mlx5_ifc_ptys_reg_bits ptys_reg;
7640         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
7641         struct mlx5_ifc_pude_reg_bits pude_reg;
7642         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7643         struct mlx5_ifc_slrg_reg_bits slrg_reg;
7644         struct mlx5_ifc_sltp_reg_bits sltp_reg;
7645         u8         reserved_at_0[0x60e0];
7646 };
7647
7648 union mlx5_ifc_debug_enhancements_document_bits {
7649         struct mlx5_ifc_health_buffer_bits health_buffer;
7650         u8         reserved_at_0[0x200];
7651 };
7652
7653 union mlx5_ifc_uplink_pci_interface_document_bits {
7654         struct mlx5_ifc_initial_seg_bits initial_seg;
7655         u8         reserved_at_0[0x20060];
7656 };
7657
7658 struct mlx5_ifc_set_flow_table_root_out_bits {
7659         u8         status[0x8];
7660         u8         reserved_at_8[0x18];
7661
7662         u8         syndrome[0x20];
7663
7664         u8         reserved_at_40[0x40];
7665 };
7666
7667 struct mlx5_ifc_set_flow_table_root_in_bits {
7668         u8         opcode[0x10];
7669         u8         reserved_at_10[0x10];
7670
7671         u8         reserved_at_20[0x10];
7672         u8         op_mod[0x10];
7673
7674         u8         other_vport[0x1];
7675         u8         reserved_at_41[0xf];
7676         u8         vport_number[0x10];
7677
7678         u8         reserved_at_60[0x20];
7679
7680         u8         table_type[0x8];
7681         u8         reserved_at_88[0x18];
7682
7683         u8         reserved_at_a0[0x8];
7684         u8         table_id[0x18];
7685
7686         u8         reserved_at_c0[0x140];
7687 };
7688
7689 enum {
7690         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
7691         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
7692 };
7693
7694 struct mlx5_ifc_modify_flow_table_out_bits {
7695         u8         status[0x8];
7696         u8         reserved_at_8[0x18];
7697
7698         u8         syndrome[0x20];
7699
7700         u8         reserved_at_40[0x40];
7701 };
7702
7703 struct mlx5_ifc_modify_flow_table_in_bits {
7704         u8         opcode[0x10];
7705         u8         reserved_at_10[0x10];
7706
7707         u8         reserved_at_20[0x10];
7708         u8         op_mod[0x10];
7709
7710         u8         other_vport[0x1];
7711         u8         reserved_at_41[0xf];
7712         u8         vport_number[0x10];
7713
7714         u8         reserved_at_60[0x10];
7715         u8         modify_field_select[0x10];
7716
7717         u8         table_type[0x8];
7718         u8         reserved_at_88[0x18];
7719
7720         u8         reserved_at_a0[0x8];
7721         u8         table_id[0x18];
7722
7723         u8         reserved_at_c0[0x4];
7724         u8         table_miss_mode[0x4];
7725         u8         reserved_at_c8[0x18];
7726
7727         u8         reserved_at_e0[0x8];
7728         u8         table_miss_id[0x18];
7729
7730         u8         reserved_at_100[0x8];
7731         u8         lag_master_next_table_id[0x18];
7732
7733         u8         reserved_at_120[0x80];
7734 };
7735
7736 struct mlx5_ifc_ets_tcn_config_reg_bits {
7737         u8         g[0x1];
7738         u8         b[0x1];
7739         u8         r[0x1];
7740         u8         reserved_at_3[0x9];
7741         u8         group[0x4];
7742         u8         reserved_at_10[0x9];
7743         u8         bw_allocation[0x7];
7744
7745         u8         reserved_at_20[0xc];
7746         u8         max_bw_units[0x4];
7747         u8         reserved_at_30[0x8];
7748         u8         max_bw_value[0x8];
7749 };
7750
7751 struct mlx5_ifc_ets_global_config_reg_bits {
7752         u8         reserved_at_0[0x2];
7753         u8         r[0x1];
7754         u8         reserved_at_3[0x1d];
7755
7756         u8         reserved_at_20[0xc];
7757         u8         max_bw_units[0x4];
7758         u8         reserved_at_30[0x8];
7759         u8         max_bw_value[0x8];
7760 };
7761
7762 struct mlx5_ifc_qetc_reg_bits {
7763         u8                                         reserved_at_0[0x8];
7764         u8                                         port_number[0x8];
7765         u8                                         reserved_at_10[0x30];
7766
7767         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
7768         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7769 };
7770
7771 struct mlx5_ifc_qtct_reg_bits {
7772         u8         reserved_at_0[0x8];
7773         u8         port_number[0x8];
7774         u8         reserved_at_10[0xd];
7775         u8         prio[0x3];
7776
7777         u8         reserved_at_20[0x1d];
7778         u8         tclass[0x3];
7779 };
7780
7781 struct mlx5_ifc_mcia_reg_bits {
7782         u8         l[0x1];
7783         u8         reserved_at_1[0x7];
7784         u8         module[0x8];
7785         u8         reserved_at_10[0x8];
7786         u8         status[0x8];
7787
7788         u8         i2c_device_address[0x8];
7789         u8         page_number[0x8];
7790         u8         device_address[0x10];
7791
7792         u8         reserved_at_40[0x10];
7793         u8         size[0x10];
7794
7795         u8         reserved_at_60[0x20];
7796
7797         u8         dword_0[0x20];
7798         u8         dword_1[0x20];
7799         u8         dword_2[0x20];
7800         u8         dword_3[0x20];
7801         u8         dword_4[0x20];
7802         u8         dword_5[0x20];
7803         u8         dword_6[0x20];
7804         u8         dword_7[0x20];
7805         u8         dword_8[0x20];
7806         u8         dword_9[0x20];
7807         u8         dword_10[0x20];
7808         u8         dword_11[0x20];
7809 };
7810
7811 struct mlx5_ifc_dcbx_param_bits {
7812         u8         dcbx_cee_cap[0x1];
7813         u8         dcbx_ieee_cap[0x1];
7814         u8         dcbx_standby_cap[0x1];
7815         u8         reserved_at_0[0x5];
7816         u8         port_number[0x8];
7817         u8         reserved_at_10[0xa];
7818         u8         max_application_table_size[6];
7819         u8         reserved_at_20[0x15];
7820         u8         version_oper[0x3];
7821         u8         reserved_at_38[5];
7822         u8         version_admin[0x3];
7823         u8         willing_admin[0x1];
7824         u8         reserved_at_41[0x3];
7825         u8         pfc_cap_oper[0x4];
7826         u8         reserved_at_48[0x4];
7827         u8         pfc_cap_admin[0x4];
7828         u8         reserved_at_50[0x4];
7829         u8         num_of_tc_oper[0x4];
7830         u8         reserved_at_58[0x4];
7831         u8         num_of_tc_admin[0x4];
7832         u8         remote_willing[0x1];
7833         u8         reserved_at_61[3];
7834         u8         remote_pfc_cap[4];
7835         u8         reserved_at_68[0x14];
7836         u8         remote_num_of_tc[0x4];
7837         u8         reserved_at_80[0x18];
7838         u8         error[0x8];
7839         u8         reserved_at_a0[0x160];
7840 };
7841
7842 struct mlx5_ifc_lagc_bits {
7843         u8         reserved_at_0[0x1d];
7844         u8         lag_state[0x3];
7845
7846         u8         reserved_at_20[0x14];
7847         u8         tx_remap_affinity_2[0x4];
7848         u8         reserved_at_38[0x4];
7849         u8         tx_remap_affinity_1[0x4];
7850 };
7851
7852 struct mlx5_ifc_create_lag_out_bits {
7853         u8         status[0x8];
7854         u8         reserved_at_8[0x18];
7855
7856         u8         syndrome[0x20];
7857
7858         u8         reserved_at_40[0x40];
7859 };
7860
7861 struct mlx5_ifc_create_lag_in_bits {
7862         u8         opcode[0x10];
7863         u8         reserved_at_10[0x10];
7864
7865         u8         reserved_at_20[0x10];
7866         u8         op_mod[0x10];
7867
7868         struct mlx5_ifc_lagc_bits ctx;
7869 };
7870
7871 struct mlx5_ifc_modify_lag_out_bits {
7872         u8         status[0x8];
7873         u8         reserved_at_8[0x18];
7874
7875         u8         syndrome[0x20];
7876
7877         u8         reserved_at_40[0x40];
7878 };
7879
7880 struct mlx5_ifc_modify_lag_in_bits {
7881         u8         opcode[0x10];
7882         u8         reserved_at_10[0x10];
7883
7884         u8         reserved_at_20[0x10];
7885         u8         op_mod[0x10];
7886
7887         u8         reserved_at_40[0x20];
7888         u8         field_select[0x20];
7889
7890         struct mlx5_ifc_lagc_bits ctx;
7891 };
7892
7893 struct mlx5_ifc_query_lag_out_bits {
7894         u8         status[0x8];
7895         u8         reserved_at_8[0x18];
7896
7897         u8         syndrome[0x20];
7898
7899         u8         reserved_at_40[0x40];
7900
7901         struct mlx5_ifc_lagc_bits ctx;
7902 };
7903
7904 struct mlx5_ifc_query_lag_in_bits {
7905         u8         opcode[0x10];
7906         u8         reserved_at_10[0x10];
7907
7908         u8         reserved_at_20[0x10];
7909         u8         op_mod[0x10];
7910
7911         u8         reserved_at_40[0x40];
7912 };
7913
7914 struct mlx5_ifc_destroy_lag_out_bits {
7915         u8         status[0x8];
7916         u8         reserved_at_8[0x18];
7917
7918         u8         syndrome[0x20];
7919
7920         u8         reserved_at_40[0x40];
7921 };
7922
7923 struct mlx5_ifc_destroy_lag_in_bits {
7924         u8         opcode[0x10];
7925         u8         reserved_at_10[0x10];
7926
7927         u8         reserved_at_20[0x10];
7928         u8         op_mod[0x10];
7929
7930         u8         reserved_at_40[0x40];
7931 };
7932
7933 struct mlx5_ifc_create_vport_lag_out_bits {
7934         u8         status[0x8];
7935         u8         reserved_at_8[0x18];
7936
7937         u8         syndrome[0x20];
7938
7939         u8         reserved_at_40[0x40];
7940 };
7941
7942 struct mlx5_ifc_create_vport_lag_in_bits {
7943         u8         opcode[0x10];
7944         u8         reserved_at_10[0x10];
7945
7946         u8         reserved_at_20[0x10];
7947         u8         op_mod[0x10];
7948
7949         u8         reserved_at_40[0x40];
7950 };
7951
7952 struct mlx5_ifc_destroy_vport_lag_out_bits {
7953         u8         status[0x8];
7954         u8         reserved_at_8[0x18];
7955
7956         u8         syndrome[0x20];
7957
7958         u8         reserved_at_40[0x40];
7959 };
7960
7961 struct mlx5_ifc_destroy_vport_lag_in_bits {
7962         u8         opcode[0x10];
7963         u8         reserved_at_10[0x10];
7964
7965         u8         reserved_at_20[0x10];
7966         u8         op_mod[0x10];
7967
7968         u8         reserved_at_40[0x40];
7969 };
7970
7971 #endif /* MLX5_IFC_H */