include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  71         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  72 };
  73
  74 enum {
  75         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  76         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  77         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  78         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  79         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  80         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  81         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  82         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  83         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  84         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  85         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  86         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  87         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  88         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  89         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  90         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  91         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  92         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  93         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  94         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  95         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  96         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  97         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  98         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
  99         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 100         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 101         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 102         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 103         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 104         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 105         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 106         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 107         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 108         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 109         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 110         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 111         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 112         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 113         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 114         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 115         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 116         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 117         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 118         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 119         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 120         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 121         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 122         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 123         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 124         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 125         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 126         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 127         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 128         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 129         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 130         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 131         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 132         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 133         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 134         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 135         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 136         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 137         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 138         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 139         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 140         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 141         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 142         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 143         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 144         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 145         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 146         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 147         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 148         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 149         MLX5_CMD_OP_DETTACH_FROM_MCG              = 0x807,
 150         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 151         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 152         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 153         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 154         MLX5_CMD_OP_NOP                           = 0x80d,
 155         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 156         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 157         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 158         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 159         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 160         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 161         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 162         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 163         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 164         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 165         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 166         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 167         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 168         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 169         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 170         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 171         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 172         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 173         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 174         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 175         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 176         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 177         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 178         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 179         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 180         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 181         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 182         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 183         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 184         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 185         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 186         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 187         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 188         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 189         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 190         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 191         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 192         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 193         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 194         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 195         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 196         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 197         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 198         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 199         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 200         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 201         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 202         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 203         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 204         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 205         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c
 206 };
 207
 208 struct mlx5_ifc_flow_table_fields_supported_bits {
 209         u8         outer_dmac[0x1];
 210         u8         outer_smac[0x1];
 211         u8         outer_ether_type[0x1];
 212         u8         reserved_at_3[0x1];
 213         u8         outer_first_prio[0x1];
 214         u8         outer_first_cfi[0x1];
 215         u8         outer_first_vid[0x1];
 216         u8         reserved_at_7[0x1];
 217         u8         outer_second_prio[0x1];
 218         u8         outer_second_cfi[0x1];
 219         u8         outer_second_vid[0x1];
 220         u8         reserved_at_b[0x1];
 221         u8         outer_sip[0x1];
 222         u8         outer_dip[0x1];
 223         u8         outer_frag[0x1];
 224         u8         outer_ip_protocol[0x1];
 225         u8         outer_ip_ecn[0x1];
 226         u8         outer_ip_dscp[0x1];
 227         u8         outer_udp_sport[0x1];
 228         u8         outer_udp_dport[0x1];
 229         u8         outer_tcp_sport[0x1];
 230         u8         outer_tcp_dport[0x1];
 231         u8         outer_tcp_flags[0x1];
 232         u8         outer_gre_protocol[0x1];
 233         u8         outer_gre_key[0x1];
 234         u8         outer_vxlan_vni[0x1];
 235         u8         reserved_at_1a[0x5];
 236         u8         source_eswitch_port[0x1];
 237
 238         u8         inner_dmac[0x1];
 239         u8         inner_smac[0x1];
 240         u8         inner_ether_type[0x1];
 241         u8         reserved_at_23[0x1];
 242         u8         inner_first_prio[0x1];
 243         u8         inner_first_cfi[0x1];
 244         u8         inner_first_vid[0x1];
 245         u8         reserved_at_27[0x1];
 246         u8         inner_second_prio[0x1];
 247         u8         inner_second_cfi[0x1];
 248         u8         inner_second_vid[0x1];
 249         u8         reserved_at_2b[0x1];
 250         u8         inner_sip[0x1];
 251         u8         inner_dip[0x1];
 252         u8         inner_frag[0x1];
 253         u8         inner_ip_protocol[0x1];
 254         u8         inner_ip_ecn[0x1];
 255         u8         inner_ip_dscp[0x1];
 256         u8         inner_udp_sport[0x1];
 257         u8         inner_udp_dport[0x1];
 258         u8         inner_tcp_sport[0x1];
 259         u8         inner_tcp_dport[0x1];
 260         u8         inner_tcp_flags[0x1];
 261         u8         reserved_at_37[0x9];
 262
 263         u8         reserved_at_40[0x40];
 264 };
 265
 266 struct mlx5_ifc_flow_table_prop_layout_bits {
 267         u8         ft_support[0x1];
 268         u8         reserved_at_1[0x2];
 269         u8         flow_modify_en[0x1];
 270         u8         modify_root[0x1];
 271         u8         identified_miss_table_mode[0x1];
 272         u8         flow_table_modify[0x1];
 273         u8         reserved_at_7[0x19];
 274
 275         u8         reserved_at_20[0x2];
 276         u8         log_max_ft_size[0x6];
 277         u8         reserved_at_28[0x10];
 278         u8         max_ft_level[0x8];
 279
 280         u8         reserved_at_40[0x20];
 281
 282         u8         reserved_at_60[0x18];
 283         u8         log_max_ft_num[0x8];
 284
 285         u8         reserved_at_80[0x18];
 286         u8         log_max_destination[0x8];
 287
 288         u8         reserved_at_a0[0x18];
 289         u8         log_max_flow[0x8];
 290
 291         u8         reserved_at_c0[0x40];
 292
 293         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 294
 295         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 296 };
 297
 298 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 299         u8         send[0x1];
 300         u8         receive[0x1];
 301         u8         write[0x1];
 302         u8         read[0x1];
 303         u8         reserved_at_4[0x1];
 304         u8         srq_receive[0x1];
 305         u8         reserved_at_6[0x1a];
 306 };
 307
 308 struct mlx5_ifc_ipv4_layout_bits {
 309         u8         reserved_at_0[0x60];
 310
 311         u8         ipv4[0x20];
 312 };
 313
 314 struct mlx5_ifc_ipv6_layout_bits {
 315         u8         ipv6[16][0x8];
 316 };
 317
 318 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 319         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 320         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 321         u8         reserved_at_0[0x80];
 322 };
 323
 324 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 325         u8         smac_47_16[0x20];
 326
 327         u8         smac_15_0[0x10];
 328         u8         ethertype[0x10];
 329
 330         u8         dmac_47_16[0x20];
 331
 332         u8         dmac_15_0[0x10];
 333         u8         first_prio[0x3];
 334         u8         first_cfi[0x1];
 335         u8         first_vid[0xc];
 336
 337         u8         ip_protocol[0x8];
 338         u8         ip_dscp[0x6];
 339         u8         ip_ecn[0x2];
 340         u8         vlan_tag[0x1];
 341         u8         reserved_at_91[0x1];
 342         u8         frag[0x1];
 343         u8         reserved_at_93[0x4];
 344         u8         tcp_flags[0x9];
 345
 346         u8         tcp_sport[0x10];
 347         u8         tcp_dport[0x10];
 348
 349         u8         reserved_at_c0[0x20];
 350
 351         u8         udp_sport[0x10];
 352         u8         udp_dport[0x10];
 353
 354         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 355
 356         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 357 };
 358
 359 struct mlx5_ifc_fte_match_set_misc_bits {
 360         u8         reserved_at_0[0x20];
 361
 362         u8         reserved_at_20[0x10];
 363         u8         source_port[0x10];
 364
 365         u8         outer_second_prio[0x3];
 366         u8         outer_second_cfi[0x1];
 367         u8         outer_second_vid[0xc];
 368         u8         inner_second_prio[0x3];
 369         u8         inner_second_cfi[0x1];
 370         u8         inner_second_vid[0xc];
 371
 372         u8         outer_second_vlan_tag[0x1];
 373         u8         inner_second_vlan_tag[0x1];
 374         u8         reserved_at_62[0xe];
 375         u8         gre_protocol[0x10];
 376
 377         u8         gre_key_h[0x18];
 378         u8         gre_key_l[0x8];
 379
 380         u8         vxlan_vni[0x18];
 381         u8         reserved_at_b8[0x8];
 382
 383         u8         reserved_at_c0[0x20];
 384
 385         u8         reserved_at_e0[0xc];
 386         u8         outer_ipv6_flow_label[0x14];
 387
 388         u8         reserved_at_100[0xc];
 389         u8         inner_ipv6_flow_label[0x14];
 390
 391         u8         reserved_at_120[0xe0];
 392 };
 393
 394 struct mlx5_ifc_cmd_pas_bits {
 395         u8         pa_h[0x20];
 396
 397         u8         pa_l[0x14];
 398         u8         reserved_at_34[0xc];
 399 };
 400
 401 struct mlx5_ifc_uint64_bits {
 402         u8         hi[0x20];
 403
 404         u8         lo[0x20];
 405 };
 406
 407 enum {
 408         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 409         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 410         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 411         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 412         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 413         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 414         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 415         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 416         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 417         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 418 };
 419
 420 struct mlx5_ifc_ads_bits {
 421         u8         fl[0x1];
 422         u8         free_ar[0x1];
 423         u8         reserved_at_2[0xe];
 424         u8         pkey_index[0x10];
 425
 426         u8         reserved_at_20[0x8];
 427         u8         grh[0x1];
 428         u8         mlid[0x7];
 429         u8         rlid[0x10];
 430
 431         u8         ack_timeout[0x5];
 432         u8         reserved_at_45[0x3];
 433         u8         src_addr_index[0x8];
 434         u8         reserved_at_50[0x4];
 435         u8         stat_rate[0x4];
 436         u8         hop_limit[0x8];
 437
 438         u8         reserved_at_60[0x4];
 439         u8         tclass[0x8];
 440         u8         flow_label[0x14];
 441
 442         u8         rgid_rip[16][0x8];
 443
 444         u8         reserved_at_100[0x4];
 445         u8         f_dscp[0x1];
 446         u8         f_ecn[0x1];
 447         u8         reserved_at_106[0x1];
 448         u8         f_eth_prio[0x1];
 449         u8         ecn[0x2];
 450         u8         dscp[0x6];
 451         u8         udp_sport[0x10];
 452
 453         u8         dei_cfi[0x1];
 454         u8         eth_prio[0x3];
 455         u8         sl[0x4];
 456         u8         port[0x8];
 457         u8         rmac_47_32[0x10];
 458
 459         u8         rmac_31_0[0x20];
 460 };
 461
 462 struct mlx5_ifc_flow_table_nic_cap_bits {
 463         u8         nic_rx_multi_path_tirs[0x1];
 464         u8         reserved_at_1[0x1ff];
 465
 466         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 467
 468         u8         reserved_at_400[0x200];
 469
 470         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 471
 472         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 473
 474         u8         reserved_at_a00[0x200];
 475
 476         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 477
 478         u8         reserved_at_e00[0x7200];
 479 };
 480
 481 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 482         u8     reserved_at_0[0x200];
 483
 484         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 485
 486         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 487
 488         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 489
 490         u8      reserved_at_800[0x7800];
 491 };
 492
 493 struct mlx5_ifc_e_switch_cap_bits {
 494         u8         vport_svlan_strip[0x1];
 495         u8         vport_cvlan_strip[0x1];
 496         u8         vport_svlan_insert[0x1];
 497         u8         vport_cvlan_insert_if_not_exist[0x1];
 498         u8         vport_cvlan_insert_overwrite[0x1];
 499         u8         reserved_at_5[0x1b];
 500
 501         u8         reserved_at_20[0x7e0];
 502 };
 503
 504 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 505         u8         csum_cap[0x1];
 506         u8         vlan_cap[0x1];
 507         u8         lro_cap[0x1];
 508         u8         lro_psh_flag[0x1];
 509         u8         lro_time_stamp[0x1];
 510         u8         reserved_at_5[0x3];
 511         u8         self_lb_en_modifiable[0x1];
 512         u8         reserved_at_9[0x2];
 513         u8         max_lso_cap[0x5];
 514         u8         reserved_at_10[0x4];
 515         u8         rss_ind_tbl_cap[0x4];
 516         u8         reg_umr_sq[0x1];
 517         u8         scatter_fcs[0x1];
 518         u8         reserved_at_1a[0x1];
 519         u8         tunnel_lso_const_out_ip_id[0x1];
 520         u8         reserved_at_1c[0x2];
 521         u8         tunnel_statless_gre[0x1];
 522         u8         tunnel_stateless_vxlan[0x1];
 523
 524         u8         reserved_at_20[0x20];
 525
 526         u8         reserved_at_40[0x10];
 527         u8         lro_min_mss_size[0x10];
 528
 529         u8         reserved_at_60[0x120];
 530
 531         u8         lro_timer_supported_periods[4][0x20];
 532
 533         u8         reserved_at_200[0x600];
 534 };
 535
 536 struct mlx5_ifc_roce_cap_bits {
 537         u8         roce_apm[0x1];
 538         u8         reserved_at_1[0x1f];
 539
 540         u8         reserved_at_20[0x60];
 541
 542         u8         reserved_at_80[0xc];
 543         u8         l3_type[0x4];
 544         u8         reserved_at_90[0x8];
 545         u8         roce_version[0x8];
 546
 547         u8         reserved_at_a0[0x10];
 548         u8         r_roce_dest_udp_port[0x10];
 549
 550         u8         r_roce_max_src_udp_port[0x10];
 551         u8         r_roce_min_src_udp_port[0x10];
 552
 553         u8         reserved_at_e0[0x10];
 554         u8         roce_address_table_size[0x10];
 555
 556         u8         reserved_at_100[0x700];
 557 };
 558
 559 enum {
 560         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 561         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 562         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 563         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 564         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 565         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 566         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 567         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 568         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 569 };
 570
 571 enum {
 572         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 573         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 574         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 575         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 576         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 577         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 578         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 579         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 580         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 581 };
 582
 583 struct mlx5_ifc_atomic_caps_bits {
 584         u8         reserved_at_0[0x40];
 585
 586         u8         atomic_req_8B_endianess_mode[0x2];
 587         u8         reserved_at_42[0x4];
 588         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 589
 590         u8         reserved_at_47[0x19];
 591
 592         u8         reserved_at_60[0x20];
 593
 594         u8         reserved_at_80[0x10];
 595         u8         atomic_operations[0x10];
 596
 597         u8         reserved_at_a0[0x10];
 598         u8         atomic_size_qp[0x10];
 599
 600         u8         reserved_at_c0[0x10];
 601         u8         atomic_size_dc[0x10];
 602
 603         u8         reserved_at_e0[0x720];
 604 };
 605
 606 struct mlx5_ifc_odp_cap_bits {
 607         u8         reserved_at_0[0x40];
 608
 609         u8         sig[0x1];
 610         u8         reserved_at_41[0x1f];
 611
 612         u8         reserved_at_60[0x20];
 613
 614         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 615
 616         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 617
 618         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 619
 620         u8         reserved_at_e0[0x720];
 621 };
 622
 623 struct mlx5_ifc_calc_op {
 624         u8        reserved_at_0[0x10];
 625         u8        reserved_at_10[0x9];
 626         u8        op_swap_endianness[0x1];
 627         u8        op_min[0x1];
 628         u8        op_xor[0x1];
 629         u8        op_or[0x1];
 630         u8        op_and[0x1];
 631         u8        op_max[0x1];
 632         u8        op_add[0x1];
 633 };
 634
 635 struct mlx5_ifc_vector_calc_cap_bits {
 636         u8         calc_matrix[0x1];
 637         u8         reserved_at_1[0x1f];
 638         u8         reserved_at_20[0x8];
 639         u8         max_vec_count[0x8];
 640         u8         reserved_at_30[0xd];
 641         u8         max_chunk_size[0x3];
 642         struct mlx5_ifc_calc_op calc0;
 643         struct mlx5_ifc_calc_op calc1;
 644         struct mlx5_ifc_calc_op calc2;
 645         struct mlx5_ifc_calc_op calc3;
 646
 647         u8         reserved_at_e0[0x720];
 648 };
 649
 650 enum {
 651         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 652         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 653         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 654 };
 655
 656 enum {
 657         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 658         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 659 };
 660
 661 enum {
 662         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 663         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 664         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 665         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 666         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 667 };
 668
 669 enum {
 670         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 671         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 672         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 673         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 674         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 675         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 676 };
 677
 678 enum {
 679         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 680         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 681 };
 682
 683 enum {
 684         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 685         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 686         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 687 };
 688
 689 enum {
 690         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 691         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 692 };
 693
 694 struct mlx5_ifc_cmd_hca_cap_bits {
 695         u8         reserved_at_0[0x80];
 696
 697         u8         log_max_srq_sz[0x8];
 698         u8         log_max_qp_sz[0x8];
 699         u8         reserved_at_90[0xb];
 700         u8         log_max_qp[0x5];
 701
 702         u8         reserved_at_a0[0xb];
 703         u8         log_max_srq[0x5];
 704         u8         reserved_at_b0[0x10];
 705
 706         u8         reserved_at_c0[0x8];
 707         u8         log_max_cq_sz[0x8];
 708         u8         reserved_at_d0[0xb];
 709         u8         log_max_cq[0x5];
 710
 711         u8         log_max_eq_sz[0x8];
 712         u8         reserved_at_e8[0x2];
 713         u8         log_max_mkey[0x6];
 714         u8         reserved_at_f0[0xc];
 715         u8         log_max_eq[0x4];
 716
 717         u8         max_indirection[0x8];
 718         u8         reserved_at_108[0x1];
 719         u8         log_max_mrw_sz[0x7];
 720         u8         reserved_at_110[0x2];
 721         u8         log_max_bsf_list_size[0x6];
 722         u8         reserved_at_118[0x2];
 723         u8         log_max_klm_list_size[0x6];
 724
 725         u8         reserved_at_120[0xa];
 726         u8         log_max_ra_req_dc[0x6];
 727         u8         reserved_at_130[0xa];
 728         u8         log_max_ra_res_dc[0x6];
 729
 730         u8         reserved_at_140[0xa];
 731         u8         log_max_ra_req_qp[0x6];
 732         u8         reserved_at_150[0xa];
 733         u8         log_max_ra_res_qp[0x6];
 734
 735         u8         pad_cap[0x1];
 736         u8         cc_query_allowed[0x1];
 737         u8         cc_modify_allowed[0x1];
 738         u8         reserved_at_163[0xd];
 739         u8         gid_table_size[0x10];
 740
 741         u8         out_of_seq_cnt[0x1];
 742         u8         vport_counters[0x1];
 743         u8         reserved_at_182[0x4];
 744         u8         max_qp_cnt[0xa];
 745         u8         pkey_table_size[0x10];
 746
 747         u8         vport_group_manager[0x1];
 748         u8         vhca_group_manager[0x1];
 749         u8         ib_virt[0x1];
 750         u8         eth_virt[0x1];
 751         u8         reserved_at_1a4[0x1];
 752         u8         ets[0x1];
 753         u8         nic_flow_table[0x1];
 754         u8         eswitch_flow_table[0x1];
 755         u8         early_vf_enable[0x1];
 756         u8         reserved_at_1a9[0x2];
 757         u8         local_ca_ack_delay[0x5];
 758         u8         reserved_at_1af[0x2];
 759         u8         ports_check[0x1];
 760         u8         reserved_at_1b2[0x1];
 761         u8         disable_link_up[0x1];
 762         u8         beacon_led[0x1];
 763         u8         port_type[0x2];
 764         u8         num_ports[0x8];
 765
 766         u8         reserved_at_1c0[0x3];
 767         u8         log_max_msg[0x5];
 768         u8         reserved_at_1c8[0x4];
 769         u8         max_tc[0x4];
 770         u8         reserved_at_1d0[0x6];
 771         u8         rol_s[0x1];
 772         u8         rol_g[0x1];
 773         u8         reserved_at_1d8[0x1];
 774         u8         wol_s[0x1];
 775         u8         wol_g[0x1];
 776         u8         wol_a[0x1];
 777         u8         wol_b[0x1];
 778         u8         wol_m[0x1];
 779         u8         wol_u[0x1];
 780         u8         wol_p[0x1];
 781
 782         u8         stat_rate_support[0x10];
 783         u8         reserved_at_1f0[0xc];
 784         u8         cqe_version[0x4];
 785
 786         u8         compact_address_vector[0x1];
 787         u8         striding_rq[0x1];
 788         u8         reserved_at_201[0x2];
 789         u8         ipoib_basic_offloads[0x1];
 790         u8         reserved_at_205[0xa];
 791         u8         drain_sigerr[0x1];
 792         u8         cmdif_checksum[0x2];
 793         u8         sigerr_cqe[0x1];
 794         u8         reserved_at_213[0x1];
 795         u8         wq_signature[0x1];
 796         u8         sctr_data_cqe[0x1];
 797         u8         reserved_at_216[0x1];
 798         u8         sho[0x1];
 799         u8         tph[0x1];
 800         u8         rf[0x1];
 801         u8         dct[0x1];
 802         u8         reserved_at_21b[0x1];
 803         u8         eth_net_offloads[0x1];
 804         u8         roce[0x1];
 805         u8         atomic[0x1];
 806         u8         reserved_at_21f[0x1];
 807
 808         u8         cq_oi[0x1];
 809         u8         cq_resize[0x1];
 810         u8         cq_moderation[0x1];
 811         u8         reserved_at_223[0x3];
 812         u8         cq_eq_remap[0x1];
 813         u8         pg[0x1];
 814         u8         block_lb_mc[0x1];
 815         u8         reserved_at_229[0x1];
 816         u8         scqe_break_moderation[0x1];
 817         u8         cq_period_start_from_cqe[0x1];
 818         u8         cd[0x1];
 819         u8         reserved_at_22d[0x1];
 820         u8         apm[0x1];
 821         u8         vector_calc[0x1];
 822         u8         umr_ptr_rlky[0x1];
 823         u8         imaicl[0x1];
 824         u8         reserved_at_232[0x4];
 825         u8         qkv[0x1];
 826         u8         pkv[0x1];
 827         u8         set_deth_sqpn[0x1];
 828         u8         reserved_at_239[0x3];
 829         u8         xrc[0x1];
 830         u8         ud[0x1];
 831         u8         uc[0x1];
 832         u8         rc[0x1];
 833
 834         u8         reserved_at_240[0xa];
 835         u8         uar_sz[0x6];
 836         u8         reserved_at_250[0x8];
 837         u8         log_pg_sz[0x8];
 838
 839         u8         bf[0x1];
 840         u8         reserved_at_261[0x1];
 841         u8         pad_tx_eth_packet[0x1];
 842         u8         reserved_at_263[0x8];
 843         u8         log_bf_reg_size[0x5];
 844         u8         reserved_at_270[0x10];
 845
 846         u8         reserved_at_280[0x10];
 847         u8         max_wqe_sz_sq[0x10];
 848
 849         u8         reserved_at_2a0[0x10];
 850         u8         max_wqe_sz_rq[0x10];
 851
 852         u8         reserved_at_2c0[0x10];
 853         u8         max_wqe_sz_sq_dc[0x10];
 854
 855         u8         reserved_at_2e0[0x7];
 856         u8         max_qp_mcg[0x19];
 857
 858         u8         reserved_at_300[0x18];
 859         u8         log_max_mcg[0x8];
 860
 861         u8         reserved_at_320[0x3];
 862         u8         log_max_transport_domain[0x5];
 863         u8         reserved_at_328[0x3];
 864         u8         log_max_pd[0x5];
 865         u8         reserved_at_330[0xb];
 866         u8         log_max_xrcd[0x5];
 867
 868         u8         reserved_at_340[0x20];
 869
 870         u8         reserved_at_360[0x3];
 871         u8         log_max_rq[0x5];
 872         u8         reserved_at_368[0x3];
 873         u8         log_max_sq[0x5];
 874         u8         reserved_at_370[0x3];
 875         u8         log_max_tir[0x5];
 876         u8         reserved_at_378[0x3];
 877         u8         log_max_tis[0x5];
 878
 879         u8         basic_cyclic_rcv_wqe[0x1];
 880         u8         reserved_at_381[0x2];
 881         u8         log_max_rmp[0x5];
 882         u8         reserved_at_388[0x3];
 883         u8         log_max_rqt[0x5];
 884         u8         reserved_at_390[0x3];
 885         u8         log_max_rqt_size[0x5];
 886         u8         reserved_at_398[0x3];
 887         u8         log_max_tis_per_sq[0x5];
 888
 889         u8         reserved_at_3a0[0x3];
 890         u8         log_max_stride_sz_rq[0x5];
 891         u8         reserved_at_3a8[0x3];
 892         u8         log_min_stride_sz_rq[0x5];
 893         u8         reserved_at_3b0[0x3];
 894         u8         log_max_stride_sz_sq[0x5];
 895         u8         reserved_at_3b8[0x3];
 896         u8         log_min_stride_sz_sq[0x5];
 897
 898         u8         reserved_at_3c0[0x1b];
 899         u8         log_max_wq_sz[0x5];
 900
 901         u8         nic_vport_change_event[0x1];
 902         u8         reserved_at_3e1[0xa];
 903         u8         log_max_vlan_list[0x5];
 904         u8         reserved_at_3f0[0x3];
 905         u8         log_max_current_mc_list[0x5];
 906         u8         reserved_at_3f8[0x3];
 907         u8         log_max_current_uc_list[0x5];
 908
 909         u8         reserved_at_400[0x80];
 910
 911         u8         reserved_at_480[0x3];
 912         u8         log_max_l2_table[0x5];
 913         u8         reserved_at_488[0x8];
 914         u8         log_uar_page_sz[0x10];
 915
 916         u8         reserved_at_4a0[0x20];
 917         u8         device_frequency_mhz[0x20];
 918         u8         device_frequency_khz[0x20];
 919
 920         u8         reserved_at_500[0x80];
 921
 922         u8         reserved_at_580[0x3f];
 923         u8         cqe_compression[0x1];
 924
 925         u8         cqe_compression_timeout[0x10];
 926         u8         cqe_compression_max_num[0x10];
 927
 928         u8         reserved_at_5e0[0x220];
 929 };
 930
 931 enum mlx5_flow_destination_type {
 932         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
 933         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
 934         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
 935 };
 936
 937 struct mlx5_ifc_dest_format_struct_bits {
 938         u8         destination_type[0x8];
 939         u8         destination_id[0x18];
 940
 941         u8         reserved_at_20[0x20];
 942 };
 943
 944 struct mlx5_ifc_fte_match_param_bits {
 945         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
 946
 947         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
 948
 949         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 950
 951         u8         reserved_at_600[0xa00];
 952 };
 953
 954 enum {
 955         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
 956         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
 957         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
 958         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
 959         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
 960 };
 961
 962 struct mlx5_ifc_rx_hash_field_select_bits {
 963         u8         l3_prot_type[0x1];
 964         u8         l4_prot_type[0x1];
 965         u8         selected_fields[0x1e];
 966 };
 967
 968 enum {
 969         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
 970         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
 971 };
 972
 973 enum {
 974         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
 975         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
 976 };
 977
 978 struct mlx5_ifc_wq_bits {
 979         u8         wq_type[0x4];
 980         u8         wq_signature[0x1];
 981         u8         end_padding_mode[0x2];
 982         u8         cd_slave[0x1];
 983         u8         reserved_at_8[0x18];
 984
 985         u8         hds_skip_first_sge[0x1];
 986         u8         log2_hds_buf_size[0x3];
 987         u8         reserved_at_24[0x7];
 988         u8         page_offset[0x5];
 989         u8         lwm[0x10];
 990
 991         u8         reserved_at_40[0x8];
 992         u8         pd[0x18];
 993
 994         u8         reserved_at_60[0x8];
 995         u8         uar_page[0x18];
 996
 997         u8         dbr_addr[0x40];
 998
 999         u8         hw_counter[0x20];
1000
1001         u8         sw_counter[0x20];
1002
1003         u8         reserved_at_100[0xc];
1004         u8         log_wq_stride[0x4];
1005         u8         reserved_at_110[0x3];
1006         u8         log_wq_pg_sz[0x5];
1007         u8         reserved_at_118[0x3];
1008         u8         log_wq_sz[0x5];
1009
1010         u8         reserved_at_120[0x15];
1011         u8         log_wqe_num_of_strides[0x3];
1012         u8         two_byte_shift_en[0x1];
1013         u8         reserved_at_139[0x4];
1014         u8         log_wqe_stride_size[0x3];
1015
1016         u8         reserved_at_140[0x4c0];
1017
1018         struct mlx5_ifc_cmd_pas_bits pas[0];
1019 };
1020
1021 struct mlx5_ifc_rq_num_bits {
1022         u8         reserved_at_0[0x8];
1023         u8         rq_num[0x18];
1024 };
1025
1026 struct mlx5_ifc_mac_address_layout_bits {
1027         u8         reserved_at_0[0x10];
1028         u8         mac_addr_47_32[0x10];
1029
1030         u8         mac_addr_31_0[0x20];
1031 };
1032
1033 struct mlx5_ifc_vlan_layout_bits {
1034         u8         reserved_at_0[0x14];
1035         u8         vlan[0x0c];
1036
1037         u8         reserved_at_20[0x20];
1038 };
1039
1040 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1041         u8         reserved_at_0[0xa0];
1042
1043         u8         min_time_between_cnps[0x20];
1044
1045         u8         reserved_at_c0[0x12];
1046         u8         cnp_dscp[0x6];
1047         u8         reserved_at_d8[0x5];
1048         u8         cnp_802p_prio[0x3];
1049
1050         u8         reserved_at_e0[0x720];
1051 };
1052
1053 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1054         u8         reserved_at_0[0x60];
1055
1056         u8         reserved_at_60[0x4];
1057         u8         clamp_tgt_rate[0x1];
1058         u8         reserved_at_65[0x3];
1059         u8         clamp_tgt_rate_after_time_inc[0x1];
1060         u8         reserved_at_69[0x17];
1061
1062         u8         reserved_at_80[0x20];
1063
1064         u8         rpg_time_reset[0x20];
1065
1066         u8         rpg_byte_reset[0x20];
1067
1068         u8         rpg_threshold[0x20];
1069
1070         u8         rpg_max_rate[0x20];
1071
1072         u8         rpg_ai_rate[0x20];
1073
1074         u8         rpg_hai_rate[0x20];
1075
1076         u8         rpg_gd[0x20];
1077
1078         u8         rpg_min_dec_fac[0x20];
1079
1080         u8         rpg_min_rate[0x20];
1081
1082         u8         reserved_at_1c0[0xe0];
1083
1084         u8         rate_to_set_on_first_cnp[0x20];
1085
1086         u8         dce_tcp_g[0x20];
1087
1088         u8         dce_tcp_rtt[0x20];
1089
1090         u8         rate_reduce_monitor_period[0x20];
1091
1092         u8         reserved_at_320[0x20];
1093
1094         u8         initial_alpha_value[0x20];
1095
1096         u8         reserved_at_360[0x4a0];
1097 };
1098
1099 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1100         u8         reserved_at_0[0x80];
1101
1102         u8         rppp_max_rps[0x20];
1103
1104         u8         rpg_time_reset[0x20];
1105
1106         u8         rpg_byte_reset[0x20];
1107
1108         u8         rpg_threshold[0x20];
1109
1110         u8         rpg_max_rate[0x20];
1111
1112         u8         rpg_ai_rate[0x20];
1113
1114         u8         rpg_hai_rate[0x20];
1115
1116         u8         rpg_gd[0x20];
1117
1118         u8         rpg_min_dec_fac[0x20];
1119
1120         u8         rpg_min_rate[0x20];
1121
1122         u8         reserved_at_1c0[0x640];
1123 };
1124
1125 enum {
1126         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1127         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1128         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1129 };
1130
1131 struct mlx5_ifc_resize_field_select_bits {
1132         u8         resize_field_select[0x20];
1133 };
1134
1135 enum {
1136         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1137         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1138         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1139         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1140 };
1141
1142 struct mlx5_ifc_modify_field_select_bits {
1143         u8         modify_field_select[0x20];
1144 };
1145
1146 struct mlx5_ifc_field_select_r_roce_np_bits {
1147         u8         field_select_r_roce_np[0x20];
1148 };
1149
1150 struct mlx5_ifc_field_select_r_roce_rp_bits {
1151         u8         field_select_r_roce_rp[0x20];
1152 };
1153
1154 enum {
1155         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1156         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1157         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1158         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1159         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1160         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1161         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1162         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1163         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1164         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1165 };
1166
1167 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1168         u8         field_select_8021qaurp[0x20];
1169 };
1170
1171 struct mlx5_ifc_phys_layer_cntrs_bits {
1172         u8         time_since_last_clear_high[0x20];
1173
1174         u8         time_since_last_clear_low[0x20];
1175
1176         u8         symbol_errors_high[0x20];
1177
1178         u8         symbol_errors_low[0x20];
1179
1180         u8         sync_headers_errors_high[0x20];
1181
1182         u8         sync_headers_errors_low[0x20];
1183
1184         u8         edpl_bip_errors_lane0_high[0x20];
1185
1186         u8         edpl_bip_errors_lane0_low[0x20];
1187
1188         u8         edpl_bip_errors_lane1_high[0x20];
1189
1190         u8         edpl_bip_errors_lane1_low[0x20];
1191
1192         u8         edpl_bip_errors_lane2_high[0x20];
1193
1194         u8         edpl_bip_errors_lane2_low[0x20];
1195
1196         u8         edpl_bip_errors_lane3_high[0x20];
1197
1198         u8         edpl_bip_errors_lane3_low[0x20];
1199
1200         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1201
1202         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1203
1204         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1205
1206         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1207
1208         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1209
1210         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1211
1212         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1213
1214         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1215
1216         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1217
1218         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1219
1220         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1221
1222         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1223
1224         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1225
1226         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1227
1228         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1229
1230         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1231
1232         u8         rs_fec_corrected_blocks_high[0x20];
1233
1234         u8         rs_fec_corrected_blocks_low[0x20];
1235
1236         u8         rs_fec_uncorrectable_blocks_high[0x20];
1237
1238         u8         rs_fec_uncorrectable_blocks_low[0x20];
1239
1240         u8         rs_fec_no_errors_blocks_high[0x20];
1241
1242         u8         rs_fec_no_errors_blocks_low[0x20];
1243
1244         u8         rs_fec_single_error_blocks_high[0x20];
1245
1246         u8         rs_fec_single_error_blocks_low[0x20];
1247
1248         u8         rs_fec_corrected_symbols_total_high[0x20];
1249
1250         u8         rs_fec_corrected_symbols_total_low[0x20];
1251
1252         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1253
1254         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1255
1256         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1257
1258         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1259
1260         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1261
1262         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1263
1264         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1265
1266         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1267
1268         u8         link_down_events[0x20];
1269
1270         u8         successful_recovery_events[0x20];
1271
1272         u8         reserved_at_640[0x180];
1273 };
1274
1275 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1276         u8         symbol_error_counter[0x10];
1277
1278         u8         link_error_recovery_counter[0x8];
1279
1280         u8         link_downed_counter[0x8];
1281
1282         u8         port_rcv_errors[0x10];
1283
1284         u8         port_rcv_remote_physical_errors[0x10];
1285
1286         u8         port_rcv_switch_relay_errors[0x10];
1287
1288         u8         port_xmit_discards[0x10];
1289
1290         u8         port_xmit_constraint_errors[0x8];
1291
1292         u8         port_rcv_constraint_errors[0x8];
1293
1294         u8         reserved_at_70[0x8];
1295
1296         u8         link_overrun_errors[0x8];
1297
1298         u8         reserved_at_80[0x10];
1299
1300         u8         vl_15_dropped[0x10];
1301
1302         u8         reserved_at_a0[0xa0];
1303 };
1304
1305 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1306         u8         transmit_queue_high[0x20];
1307
1308         u8         transmit_queue_low[0x20];
1309
1310         u8         reserved_at_40[0x780];
1311 };
1312
1313 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1314         u8         rx_octets_high[0x20];
1315
1316         u8         rx_octets_low[0x20];
1317
1318         u8         reserved_at_40[0xc0];
1319
1320         u8         rx_frames_high[0x20];
1321
1322         u8         rx_frames_low[0x20];
1323
1324         u8         tx_octets_high[0x20];
1325
1326         u8         tx_octets_low[0x20];
1327
1328         u8         reserved_at_180[0xc0];
1329
1330         u8         tx_frames_high[0x20];
1331
1332         u8         tx_frames_low[0x20];
1333
1334         u8         rx_pause_high[0x20];
1335
1336         u8         rx_pause_low[0x20];
1337
1338         u8         rx_pause_duration_high[0x20];
1339
1340         u8         rx_pause_duration_low[0x20];
1341
1342         u8         tx_pause_high[0x20];
1343
1344         u8         tx_pause_low[0x20];
1345
1346         u8         tx_pause_duration_high[0x20];
1347
1348         u8         tx_pause_duration_low[0x20];
1349
1350         u8         rx_pause_transition_high[0x20];
1351
1352         u8         rx_pause_transition_low[0x20];
1353
1354         u8         reserved_at_3c0[0x400];
1355 };
1356
1357 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1358         u8         port_transmit_wait_high[0x20];
1359
1360         u8         port_transmit_wait_low[0x20];
1361
1362         u8         reserved_at_40[0x780];
1363 };
1364
1365 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1366         u8         dot3stats_alignment_errors_high[0x20];
1367
1368         u8         dot3stats_alignment_errors_low[0x20];
1369
1370         u8         dot3stats_fcs_errors_high[0x20];
1371
1372         u8         dot3stats_fcs_errors_low[0x20];
1373
1374         u8         dot3stats_single_collision_frames_high[0x20];
1375
1376         u8         dot3stats_single_collision_frames_low[0x20];
1377
1378         u8         dot3stats_multiple_collision_frames_high[0x20];
1379
1380         u8         dot3stats_multiple_collision_frames_low[0x20];
1381
1382         u8         dot3stats_sqe_test_errors_high[0x20];
1383
1384         u8         dot3stats_sqe_test_errors_low[0x20];
1385
1386         u8         dot3stats_deferred_transmissions_high[0x20];
1387
1388         u8         dot3stats_deferred_transmissions_low[0x20];
1389
1390         u8         dot3stats_late_collisions_high[0x20];
1391
1392         u8         dot3stats_late_collisions_low[0x20];
1393
1394         u8         dot3stats_excessive_collisions_high[0x20];
1395
1396         u8         dot3stats_excessive_collisions_low[0x20];
1397
1398         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1399
1400         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1401
1402         u8         dot3stats_carrier_sense_errors_high[0x20];
1403
1404         u8         dot3stats_carrier_sense_errors_low[0x20];
1405
1406         u8         dot3stats_frame_too_longs_high[0x20];
1407
1408         u8         dot3stats_frame_too_longs_low[0x20];
1409
1410         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1411
1412         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1413
1414         u8         dot3stats_symbol_errors_high[0x20];
1415
1416         u8         dot3stats_symbol_errors_low[0x20];
1417
1418         u8         dot3control_in_unknown_opcodes_high[0x20];
1419
1420         u8         dot3control_in_unknown_opcodes_low[0x20];
1421
1422         u8         dot3in_pause_frames_high[0x20];
1423
1424         u8         dot3in_pause_frames_low[0x20];
1425
1426         u8         dot3out_pause_frames_high[0x20];
1427
1428         u8         dot3out_pause_frames_low[0x20];
1429
1430         u8         reserved_at_400[0x3c0];
1431 };
1432
1433 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1434         u8         ether_stats_drop_events_high[0x20];
1435
1436         u8         ether_stats_drop_events_low[0x20];
1437
1438         u8         ether_stats_octets_high[0x20];
1439
1440         u8         ether_stats_octets_low[0x20];
1441
1442         u8         ether_stats_pkts_high[0x20];
1443
1444         u8         ether_stats_pkts_low[0x20];
1445
1446         u8         ether_stats_broadcast_pkts_high[0x20];
1447
1448         u8         ether_stats_broadcast_pkts_low[0x20];
1449
1450         u8         ether_stats_multicast_pkts_high[0x20];
1451
1452         u8         ether_stats_multicast_pkts_low[0x20];
1453
1454         u8         ether_stats_crc_align_errors_high[0x20];
1455
1456         u8         ether_stats_crc_align_errors_low[0x20];
1457
1458         u8         ether_stats_undersize_pkts_high[0x20];
1459
1460         u8         ether_stats_undersize_pkts_low[0x20];
1461
1462         u8         ether_stats_oversize_pkts_high[0x20];
1463
1464         u8         ether_stats_oversize_pkts_low[0x20];
1465
1466         u8         ether_stats_fragments_high[0x20];
1467
1468         u8         ether_stats_fragments_low[0x20];
1469
1470         u8         ether_stats_jabbers_high[0x20];
1471
1472         u8         ether_stats_jabbers_low[0x20];
1473
1474         u8         ether_stats_collisions_high[0x20];
1475
1476         u8         ether_stats_collisions_low[0x20];
1477
1478         u8         ether_stats_pkts64octets_high[0x20];
1479
1480         u8         ether_stats_pkts64octets_low[0x20];
1481
1482         u8         ether_stats_pkts65to127octets_high[0x20];
1483
1484         u8         ether_stats_pkts65to127octets_low[0x20];
1485
1486         u8         ether_stats_pkts128to255octets_high[0x20];
1487
1488         u8         ether_stats_pkts128to255octets_low[0x20];
1489
1490         u8         ether_stats_pkts256to511octets_high[0x20];
1491
1492         u8         ether_stats_pkts256to511octets_low[0x20];
1493
1494         u8         ether_stats_pkts512to1023octets_high[0x20];
1495
1496         u8         ether_stats_pkts512to1023octets_low[0x20];
1497
1498         u8         ether_stats_pkts1024to1518octets_high[0x20];
1499
1500         u8         ether_stats_pkts1024to1518octets_low[0x20];
1501
1502         u8         ether_stats_pkts1519to2047octets_high[0x20];
1503
1504         u8         ether_stats_pkts1519to2047octets_low[0x20];
1505
1506         u8         ether_stats_pkts2048to4095octets_high[0x20];
1507
1508         u8         ether_stats_pkts2048to4095octets_low[0x20];
1509
1510         u8         ether_stats_pkts4096to8191octets_high[0x20];
1511
1512         u8         ether_stats_pkts4096to8191octets_low[0x20];
1513
1514         u8         ether_stats_pkts8192to10239octets_high[0x20];
1515
1516         u8         ether_stats_pkts8192to10239octets_low[0x20];
1517
1518         u8         reserved_at_540[0x280];
1519 };
1520
1521 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1522         u8         if_in_octets_high[0x20];
1523
1524         u8         if_in_octets_low[0x20];
1525
1526         u8         if_in_ucast_pkts_high[0x20];
1527
1528         u8         if_in_ucast_pkts_low[0x20];
1529
1530         u8         if_in_discards_high[0x20];
1531
1532         u8         if_in_discards_low[0x20];
1533
1534         u8         if_in_errors_high[0x20];
1535
1536         u8         if_in_errors_low[0x20];
1537
1538         u8         if_in_unknown_protos_high[0x20];
1539
1540         u8         if_in_unknown_protos_low[0x20];
1541
1542         u8         if_out_octets_high[0x20];
1543
1544         u8         if_out_octets_low[0x20];
1545
1546         u8         if_out_ucast_pkts_high[0x20];
1547
1548         u8         if_out_ucast_pkts_low[0x20];
1549
1550         u8         if_out_discards_high[0x20];
1551
1552         u8         if_out_discards_low[0x20];
1553
1554         u8         if_out_errors_high[0x20];
1555
1556         u8         if_out_errors_low[0x20];
1557
1558         u8         if_in_multicast_pkts_high[0x20];
1559
1560         u8         if_in_multicast_pkts_low[0x20];
1561
1562         u8         if_in_broadcast_pkts_high[0x20];
1563
1564         u8         if_in_broadcast_pkts_low[0x20];
1565
1566         u8         if_out_multicast_pkts_high[0x20];
1567
1568         u8         if_out_multicast_pkts_low[0x20];
1569
1570         u8         if_out_broadcast_pkts_high[0x20];
1571
1572         u8         if_out_broadcast_pkts_low[0x20];
1573
1574         u8         reserved_at_340[0x480];
1575 };
1576
1577 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1578         u8         a_frames_transmitted_ok_high[0x20];
1579
1580         u8         a_frames_transmitted_ok_low[0x20];
1581
1582         u8         a_frames_received_ok_high[0x20];
1583
1584         u8         a_frames_received_ok_low[0x20];
1585
1586         u8         a_frame_check_sequence_errors_high[0x20];
1587
1588         u8         a_frame_check_sequence_errors_low[0x20];
1589
1590         u8         a_alignment_errors_high[0x20];
1591
1592         u8         a_alignment_errors_low[0x20];
1593
1594         u8         a_octets_transmitted_ok_high[0x20];
1595
1596         u8         a_octets_transmitted_ok_low[0x20];
1597
1598         u8         a_octets_received_ok_high[0x20];
1599
1600         u8         a_octets_received_ok_low[0x20];
1601
1602         u8         a_multicast_frames_xmitted_ok_high[0x20];
1603
1604         u8         a_multicast_frames_xmitted_ok_low[0x20];
1605
1606         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1607
1608         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1609
1610         u8         a_multicast_frames_received_ok_high[0x20];
1611
1612         u8         a_multicast_frames_received_ok_low[0x20];
1613
1614         u8         a_broadcast_frames_received_ok_high[0x20];
1615
1616         u8         a_broadcast_frames_received_ok_low[0x20];
1617
1618         u8         a_in_range_length_errors_high[0x20];
1619
1620         u8         a_in_range_length_errors_low[0x20];
1621
1622         u8         a_out_of_range_length_field_high[0x20];
1623
1624         u8         a_out_of_range_length_field_low[0x20];
1625
1626         u8         a_frame_too_long_errors_high[0x20];
1627
1628         u8         a_frame_too_long_errors_low[0x20];
1629
1630         u8         a_symbol_error_during_carrier_high[0x20];
1631
1632         u8         a_symbol_error_during_carrier_low[0x20];
1633
1634         u8         a_mac_control_frames_transmitted_high[0x20];
1635
1636         u8         a_mac_control_frames_transmitted_low[0x20];
1637
1638         u8         a_mac_control_frames_received_high[0x20];
1639
1640         u8         a_mac_control_frames_received_low[0x20];
1641
1642         u8         a_unsupported_opcodes_received_high[0x20];
1643
1644         u8         a_unsupported_opcodes_received_low[0x20];
1645
1646         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1647
1648         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1649
1650         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1651
1652         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1653
1654         u8         reserved_at_4c0[0x300];
1655 };
1656
1657 struct mlx5_ifc_cmd_inter_comp_event_bits {
1658         u8         command_completion_vector[0x20];
1659
1660         u8         reserved_at_20[0xc0];
1661 };
1662
1663 struct mlx5_ifc_stall_vl_event_bits {
1664         u8         reserved_at_0[0x18];
1665         u8         port_num[0x1];
1666         u8         reserved_at_19[0x3];
1667         u8         vl[0x4];
1668
1669         u8         reserved_at_20[0xa0];
1670 };
1671
1672 struct mlx5_ifc_db_bf_congestion_event_bits {
1673         u8         event_subtype[0x8];
1674         u8         reserved_at_8[0x8];
1675         u8         congestion_level[0x8];
1676         u8         reserved_at_18[0x8];
1677
1678         u8         reserved_at_20[0xa0];
1679 };
1680
1681 struct mlx5_ifc_gpio_event_bits {
1682         u8         reserved_at_0[0x60];
1683
1684         u8         gpio_event_hi[0x20];
1685
1686         u8         gpio_event_lo[0x20];
1687
1688         u8         reserved_at_a0[0x40];
1689 };
1690
1691 struct mlx5_ifc_port_state_change_event_bits {
1692         u8         reserved_at_0[0x40];
1693
1694         u8         port_num[0x4];
1695         u8         reserved_at_44[0x1c];
1696
1697         u8         reserved_at_60[0x80];
1698 };
1699
1700 struct mlx5_ifc_dropped_packet_logged_bits {
1701         u8         reserved_at_0[0xe0];
1702 };
1703
1704 enum {
1705         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1706         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1707 };
1708
1709 struct mlx5_ifc_cq_error_bits {
1710         u8         reserved_at_0[0x8];
1711         u8         cqn[0x18];
1712
1713         u8         reserved_at_20[0x20];
1714
1715         u8         reserved_at_40[0x18];
1716         u8         syndrome[0x8];
1717
1718         u8         reserved_at_60[0x80];
1719 };
1720
1721 struct mlx5_ifc_rdma_page_fault_event_bits {
1722         u8         bytes_committed[0x20];
1723
1724         u8         r_key[0x20];
1725
1726         u8         reserved_at_40[0x10];
1727         u8         packet_len[0x10];
1728
1729         u8         rdma_op_len[0x20];
1730
1731         u8         rdma_va[0x40];
1732
1733         u8         reserved_at_c0[0x5];
1734         u8         rdma[0x1];
1735         u8         write[0x1];
1736         u8         requestor[0x1];
1737         u8         qp_number[0x18];
1738 };
1739
1740 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1741         u8         bytes_committed[0x20];
1742
1743         u8         reserved_at_20[0x10];
1744         u8         wqe_index[0x10];
1745
1746         u8         reserved_at_40[0x10];
1747         u8         len[0x10];
1748
1749         u8         reserved_at_60[0x60];
1750
1751         u8         reserved_at_c0[0x5];
1752         u8         rdma[0x1];
1753         u8         write_read[0x1];
1754         u8         requestor[0x1];
1755         u8         qpn[0x18];
1756 };
1757
1758 struct mlx5_ifc_qp_events_bits {
1759         u8         reserved_at_0[0xa0];
1760
1761         u8         type[0x8];
1762         u8         reserved_at_a8[0x18];
1763
1764         u8         reserved_at_c0[0x8];
1765         u8         qpn_rqn_sqn[0x18];
1766 };
1767
1768 struct mlx5_ifc_dct_events_bits {
1769         u8         reserved_at_0[0xc0];
1770
1771         u8         reserved_at_c0[0x8];
1772         u8         dct_number[0x18];
1773 };
1774
1775 struct mlx5_ifc_comp_event_bits {
1776         u8         reserved_at_0[0xc0];
1777
1778         u8         reserved_at_c0[0x8];
1779         u8         cq_number[0x18];
1780 };
1781
1782 enum {
1783         MLX5_QPC_STATE_RST        = 0x0,
1784         MLX5_QPC_STATE_INIT       = 0x1,
1785         MLX5_QPC_STATE_RTR        = 0x2,
1786         MLX5_QPC_STATE_RTS        = 0x3,
1787         MLX5_QPC_STATE_SQER       = 0x4,
1788         MLX5_QPC_STATE_ERR        = 0x6,
1789         MLX5_QPC_STATE_SQD        = 0x7,
1790         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1791 };
1792
1793 enum {
1794         MLX5_QPC_ST_RC            = 0x0,
1795         MLX5_QPC_ST_UC            = 0x1,
1796         MLX5_QPC_ST_UD            = 0x2,
1797         MLX5_QPC_ST_XRC           = 0x3,
1798         MLX5_QPC_ST_DCI           = 0x5,
1799         MLX5_QPC_ST_QP0           = 0x7,
1800         MLX5_QPC_ST_QP1           = 0x8,
1801         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1802         MLX5_QPC_ST_REG_UMR       = 0xc,
1803 };
1804
1805 enum {
1806         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1807         MLX5_QPC_PM_STATE_REARM     = 0x1,
1808         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1809         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1810 };
1811
1812 enum {
1813         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1814         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1815 };
1816
1817 enum {
1818         MLX5_QPC_MTU_256_BYTES        = 0x1,
1819         MLX5_QPC_MTU_512_BYTES        = 0x2,
1820         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1821         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1822         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1823         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1824 };
1825
1826 enum {
1827         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1828         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1829         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1830         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1831         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1832         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1833         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1834         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1835 };
1836
1837 enum {
1838         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1839         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1840         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1841 };
1842
1843 enum {
1844         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1845         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1846         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1847 };
1848
1849 struct mlx5_ifc_qpc_bits {
1850         u8         state[0x4];
1851         u8         reserved_at_4[0x4];
1852         u8         st[0x8];
1853         u8         reserved_at_10[0x3];
1854         u8         pm_state[0x2];
1855         u8         reserved_at_15[0x7];
1856         u8         end_padding_mode[0x2];
1857         u8         reserved_at_1e[0x2];
1858
1859         u8         wq_signature[0x1];
1860         u8         block_lb_mc[0x1];
1861         u8         atomic_like_write_en[0x1];
1862         u8         latency_sensitive[0x1];
1863         u8         reserved_at_24[0x1];
1864         u8         drain_sigerr[0x1];
1865         u8         reserved_at_26[0x2];
1866         u8         pd[0x18];
1867
1868         u8         mtu[0x3];
1869         u8         log_msg_max[0x5];
1870         u8         reserved_at_48[0x1];
1871         u8         log_rq_size[0x4];
1872         u8         log_rq_stride[0x3];
1873         u8         no_sq[0x1];
1874         u8         log_sq_size[0x4];
1875         u8         reserved_at_55[0x6];
1876         u8         rlky[0x1];
1877         u8         ulp_stateless_offload_mode[0x4];
1878
1879         u8         counter_set_id[0x8];
1880         u8         uar_page[0x18];
1881
1882         u8         reserved_at_80[0x8];
1883         u8         user_index[0x18];
1884
1885         u8         reserved_at_a0[0x3];
1886         u8         log_page_size[0x5];
1887         u8         remote_qpn[0x18];
1888
1889         struct mlx5_ifc_ads_bits primary_address_path;
1890
1891         struct mlx5_ifc_ads_bits secondary_address_path;
1892
1893         u8         log_ack_req_freq[0x4];
1894         u8         reserved_at_384[0x4];
1895         u8         log_sra_max[0x3];
1896         u8         reserved_at_38b[0x2];
1897         u8         retry_count[0x3];
1898         u8         rnr_retry[0x3];
1899         u8         reserved_at_393[0x1];
1900         u8         fre[0x1];
1901         u8         cur_rnr_retry[0x3];
1902         u8         cur_retry_count[0x3];
1903         u8         reserved_at_39b[0x5];
1904
1905         u8         reserved_at_3a0[0x20];
1906
1907         u8         reserved_at_3c0[0x8];
1908         u8         next_send_psn[0x18];
1909
1910         u8         reserved_at_3e0[0x8];
1911         u8         cqn_snd[0x18];
1912
1913         u8         reserved_at_400[0x40];
1914
1915         u8         reserved_at_440[0x8];
1916         u8         last_acked_psn[0x18];
1917
1918         u8         reserved_at_460[0x8];
1919         u8         ssn[0x18];
1920
1921         u8         reserved_at_480[0x8];
1922         u8         log_rra_max[0x3];
1923         u8         reserved_at_48b[0x1];
1924         u8         atomic_mode[0x4];
1925         u8         rre[0x1];
1926         u8         rwe[0x1];
1927         u8         rae[0x1];
1928         u8         reserved_at_493[0x1];
1929         u8         page_offset[0x6];
1930         u8         reserved_at_49a[0x3];
1931         u8         cd_slave_receive[0x1];
1932         u8         cd_slave_send[0x1];
1933         u8         cd_master[0x1];
1934
1935         u8         reserved_at_4a0[0x3];
1936         u8         min_rnr_nak[0x5];
1937         u8         next_rcv_psn[0x18];
1938
1939         u8         reserved_at_4c0[0x8];
1940         u8         xrcd[0x18];
1941
1942         u8         reserved_at_4e0[0x8];
1943         u8         cqn_rcv[0x18];
1944
1945         u8         dbr_addr[0x40];
1946
1947         u8         q_key[0x20];
1948
1949         u8         reserved_at_560[0x5];
1950         u8         rq_type[0x3];
1951         u8         srqn_rmpn[0x18];
1952
1953         u8         reserved_at_580[0x8];
1954         u8         rmsn[0x18];
1955
1956         u8         hw_sq_wqebb_counter[0x10];
1957         u8         sw_sq_wqebb_counter[0x10];
1958
1959         u8         hw_rq_counter[0x20];
1960
1961         u8         sw_rq_counter[0x20];
1962
1963         u8         reserved_at_600[0x20];
1964
1965         u8         reserved_at_620[0xf];
1966         u8         cgs[0x1];
1967         u8         cs_req[0x8];
1968         u8         cs_res[0x8];
1969
1970         u8         dc_access_key[0x40];
1971
1972         u8         reserved_at_680[0xc0];
1973 };
1974
1975 struct mlx5_ifc_roce_addr_layout_bits {
1976         u8         source_l3_address[16][0x8];
1977
1978         u8         reserved_at_80[0x3];
1979         u8         vlan_valid[0x1];
1980         u8         vlan_id[0xc];
1981         u8         source_mac_47_32[0x10];
1982
1983         u8         source_mac_31_0[0x20];
1984
1985         u8         reserved_at_c0[0x14];
1986         u8         roce_l3_type[0x4];
1987         u8         roce_version[0x8];
1988
1989         u8         reserved_at_e0[0x20];
1990 };
1991
1992 union mlx5_ifc_hca_cap_union_bits {
1993         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1994         struct mlx5_ifc_odp_cap_bits odp_cap;
1995         struct mlx5_ifc_atomic_caps_bits atomic_caps;
1996         struct mlx5_ifc_roce_cap_bits roce_cap;
1997         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1998         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1999         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2000         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2001         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2002         u8         reserved_at_0[0x8000];
2003 };
2004
2005 enum {
2006         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2007         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2008         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2009 };
2010
2011 struct mlx5_ifc_flow_context_bits {
2012         u8         reserved_at_0[0x20];
2013
2014         u8         group_id[0x20];
2015
2016         u8         reserved_at_40[0x8];
2017         u8         flow_tag[0x18];
2018
2019         u8         reserved_at_60[0x10];
2020         u8         action[0x10];
2021
2022         u8         reserved_at_80[0x8];
2023         u8         destination_list_size[0x18];
2024
2025         u8         reserved_at_a0[0x160];
2026
2027         struct mlx5_ifc_fte_match_param_bits match_value;
2028
2029         u8         reserved_at_1200[0x600];
2030
2031         struct mlx5_ifc_dest_format_struct_bits destination[0];
2032 };
2033
2034 enum {
2035         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2036         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2037 };
2038
2039 struct mlx5_ifc_xrc_srqc_bits {
2040         u8         state[0x4];
2041         u8         log_xrc_srq_size[0x4];
2042         u8         reserved_at_8[0x18];
2043
2044         u8         wq_signature[0x1];
2045         u8         cont_srq[0x1];
2046         u8         reserved_at_22[0x1];
2047         u8         rlky[0x1];
2048         u8         basic_cyclic_rcv_wqe[0x1];
2049         u8         log_rq_stride[0x3];
2050         u8         xrcd[0x18];
2051
2052         u8         page_offset[0x6];
2053         u8         reserved_at_46[0x2];
2054         u8         cqn[0x18];
2055
2056         u8         reserved_at_60[0x20];
2057
2058         u8         user_index_equal_xrc_srqn[0x1];
2059         u8         reserved_at_81[0x1];
2060         u8         log_page_size[0x6];
2061         u8         user_index[0x18];
2062
2063         u8         reserved_at_a0[0x20];
2064
2065         u8         reserved_at_c0[0x8];
2066         u8         pd[0x18];
2067
2068         u8         lwm[0x10];
2069         u8         wqe_cnt[0x10];
2070
2071         u8         reserved_at_100[0x40];
2072
2073         u8         db_record_addr_h[0x20];
2074
2075         u8         db_record_addr_l[0x1e];
2076         u8         reserved_at_17e[0x2];
2077
2078         u8         reserved_at_180[0x80];
2079 };
2080
2081 struct mlx5_ifc_traffic_counter_bits {
2082         u8         packets[0x40];
2083
2084         u8         octets[0x40];
2085 };
2086
2087 struct mlx5_ifc_tisc_bits {
2088         u8         reserved_at_0[0xc];
2089         u8         prio[0x4];
2090         u8         reserved_at_10[0x10];
2091
2092         u8         reserved_at_20[0x100];
2093
2094         u8         reserved_at_120[0x8];
2095         u8         transport_domain[0x18];
2096
2097         u8         reserved_at_140[0x3c0];
2098 };
2099
2100 enum {
2101         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2102         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2103 };
2104
2105 enum {
2106         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2107         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2108 };
2109
2110 enum {
2111         MLX5_RX_HASH_FN_NONE           = 0x0,
2112         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2113         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2114 };
2115
2116 enum {
2117         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2118         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2119 };
2120
2121 struct mlx5_ifc_tirc_bits {
2122         u8         reserved_at_0[0x20];
2123
2124         u8         disp_type[0x4];
2125         u8         reserved_at_24[0x1c];
2126
2127         u8         reserved_at_40[0x40];
2128
2129         u8         reserved_at_80[0x4];
2130         u8         lro_timeout_period_usecs[0x10];
2131         u8         lro_enable_mask[0x4];
2132         u8         lro_max_ip_payload_size[0x8];
2133
2134         u8         reserved_at_a0[0x40];
2135
2136         u8         reserved_at_e0[0x8];
2137         u8         inline_rqn[0x18];
2138
2139         u8         rx_hash_symmetric[0x1];
2140         u8         reserved_at_101[0x1];
2141         u8         tunneled_offload_en[0x1];
2142         u8         reserved_at_103[0x5];
2143         u8         indirect_table[0x18];
2144
2145         u8         rx_hash_fn[0x4];
2146         u8         reserved_at_124[0x2];
2147         u8         self_lb_block[0x2];
2148         u8         transport_domain[0x18];
2149
2150         u8         rx_hash_toeplitz_key[10][0x20];
2151
2152         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2153
2154         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2155
2156         u8         reserved_at_2c0[0x4c0];
2157 };
2158
2159 enum {
2160         MLX5_SRQC_STATE_GOOD   = 0x0,
2161         MLX5_SRQC_STATE_ERROR  = 0x1,
2162 };
2163
2164 struct mlx5_ifc_srqc_bits {
2165         u8         state[0x4];
2166         u8         log_srq_size[0x4];
2167         u8         reserved_at_8[0x18];
2168
2169         u8         wq_signature[0x1];
2170         u8         cont_srq[0x1];
2171         u8         reserved_at_22[0x1];
2172         u8         rlky[0x1];
2173         u8         reserved_at_24[0x1];
2174         u8         log_rq_stride[0x3];
2175         u8         xrcd[0x18];
2176
2177         u8         page_offset[0x6];
2178         u8         reserved_at_46[0x2];
2179         u8         cqn[0x18];
2180
2181         u8         reserved_at_60[0x20];
2182
2183         u8         reserved_at_80[0x2];
2184         u8         log_page_size[0x6];
2185         u8         reserved_at_88[0x18];
2186
2187         u8         reserved_at_a0[0x20];
2188
2189         u8         reserved_at_c0[0x8];
2190         u8         pd[0x18];
2191
2192         u8         lwm[0x10];
2193         u8         wqe_cnt[0x10];
2194
2195         u8         reserved_at_100[0x40];
2196
2197         u8         dbr_addr[0x40];
2198
2199         u8         reserved_at_180[0x80];
2200 };
2201
2202 enum {
2203         MLX5_SQC_STATE_RST  = 0x0,
2204         MLX5_SQC_STATE_RDY  = 0x1,
2205         MLX5_SQC_STATE_ERR  = 0x3,
2206 };
2207
2208 struct mlx5_ifc_sqc_bits {
2209         u8         rlky[0x1];
2210         u8         cd_master[0x1];
2211         u8         fre[0x1];
2212         u8         flush_in_error_en[0x1];
2213         u8         reserved_at_4[0x4];
2214         u8         state[0x4];
2215         u8         reg_umr[0x1];
2216         u8         reserved_at_d[0x13];
2217
2218         u8         reserved_at_20[0x8];
2219         u8         user_index[0x18];
2220
2221         u8         reserved_at_40[0x8];
2222         u8         cqn[0x18];
2223
2224         u8         reserved_at_60[0xa0];
2225
2226         u8         tis_lst_sz[0x10];
2227         u8         reserved_at_110[0x10];
2228
2229         u8         reserved_at_120[0x40];
2230
2231         u8         reserved_at_160[0x8];
2232         u8         tis_num_0[0x18];
2233
2234         struct mlx5_ifc_wq_bits wq;
2235 };
2236
2237 struct mlx5_ifc_rqtc_bits {
2238         u8         reserved_at_0[0xa0];
2239
2240         u8         reserved_at_a0[0x10];
2241         u8         rqt_max_size[0x10];
2242
2243         u8         reserved_at_c0[0x10];
2244         u8         rqt_actual_size[0x10];
2245
2246         u8         reserved_at_e0[0x6a0];
2247
2248         struct mlx5_ifc_rq_num_bits rq_num[0];
2249 };
2250
2251 enum {
2252         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2253         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2254 };
2255
2256 enum {
2257         MLX5_RQC_STATE_RST  = 0x0,
2258         MLX5_RQC_STATE_RDY  = 0x1,
2259         MLX5_RQC_STATE_ERR  = 0x3,
2260 };
2261
2262 struct mlx5_ifc_rqc_bits {
2263         u8         rlky[0x1];
2264         u8         reserved_at_1[0x1];
2265         u8         scatter_fcs[0x1];
2266         u8         vsd[0x1];
2267         u8         mem_rq_type[0x4];
2268         u8         state[0x4];
2269         u8         reserved_at_c[0x1];
2270         u8         flush_in_error_en[0x1];
2271         u8         reserved_at_e[0x12];
2272
2273         u8         reserved_at_20[0x8];
2274         u8         user_index[0x18];
2275
2276         u8         reserved_at_40[0x8];
2277         u8         cqn[0x18];
2278
2279         u8         counter_set_id[0x8];
2280         u8         reserved_at_68[0x18];
2281
2282         u8         reserved_at_80[0x8];
2283         u8         rmpn[0x18];
2284
2285         u8         reserved_at_a0[0xe0];
2286
2287         struct mlx5_ifc_wq_bits wq;
2288 };
2289
2290 enum {
2291         MLX5_RMPC_STATE_RDY  = 0x1,
2292         MLX5_RMPC_STATE_ERR  = 0x3,
2293 };
2294
2295 struct mlx5_ifc_rmpc_bits {
2296         u8         reserved_at_0[0x8];
2297         u8         state[0x4];
2298         u8         reserved_at_c[0x14];
2299
2300         u8         basic_cyclic_rcv_wqe[0x1];
2301         u8         reserved_at_21[0x1f];
2302
2303         u8         reserved_at_40[0x140];
2304
2305         struct mlx5_ifc_wq_bits wq;
2306 };
2307
2308 struct mlx5_ifc_nic_vport_context_bits {
2309         u8         reserved_at_0[0x1f];
2310         u8         roce_en[0x1];
2311
2312         u8         arm_change_event[0x1];
2313         u8         reserved_at_21[0x1a];
2314         u8         event_on_mtu[0x1];
2315         u8         event_on_promisc_change[0x1];
2316         u8         event_on_vlan_change[0x1];
2317         u8         event_on_mc_address_change[0x1];
2318         u8         event_on_uc_address_change[0x1];
2319
2320         u8         reserved_at_40[0xf0];
2321
2322         u8         mtu[0x10];
2323
2324         u8         system_image_guid[0x40];
2325         u8         port_guid[0x40];
2326         u8         node_guid[0x40];
2327
2328         u8         reserved_at_200[0x140];
2329         u8         qkey_violation_counter[0x10];
2330         u8         reserved_at_350[0x430];
2331
2332         u8         promisc_uc[0x1];
2333         u8         promisc_mc[0x1];
2334         u8         promisc_all[0x1];
2335         u8         reserved_at_783[0x2];
2336         u8         allowed_list_type[0x3];
2337         u8         reserved_at_788[0xc];
2338         u8         allowed_list_size[0xc];
2339
2340         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2341
2342         u8         reserved_at_7e0[0x20];
2343
2344         u8         current_uc_mac_address[0][0x40];
2345 };
2346
2347 enum {
2348         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2349         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2350         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2351 };
2352
2353 struct mlx5_ifc_mkc_bits {
2354         u8         reserved_at_0[0x1];
2355         u8         free[0x1];
2356         u8         reserved_at_2[0xd];
2357         u8         small_fence_on_rdma_read_response[0x1];
2358         u8         umr_en[0x1];
2359         u8         a[0x1];
2360         u8         rw[0x1];
2361         u8         rr[0x1];
2362         u8         lw[0x1];
2363         u8         lr[0x1];
2364         u8         access_mode[0x2];
2365         u8         reserved_at_18[0x8];
2366
2367         u8         qpn[0x18];
2368         u8         mkey_7_0[0x8];
2369
2370         u8         reserved_at_40[0x20];
2371
2372         u8         length64[0x1];
2373         u8         bsf_en[0x1];
2374         u8         sync_umr[0x1];
2375         u8         reserved_at_63[0x2];
2376         u8         expected_sigerr_count[0x1];
2377         u8         reserved_at_66[0x1];
2378         u8         en_rinval[0x1];
2379         u8         pd[0x18];
2380
2381         u8         start_addr[0x40];
2382
2383         u8         len[0x40];
2384
2385         u8         bsf_octword_size[0x20];
2386
2387         u8         reserved_at_120[0x80];
2388
2389         u8         translations_octword_size[0x20];
2390
2391         u8         reserved_at_1c0[0x1b];
2392         u8         log_page_size[0x5];
2393
2394         u8         reserved_at_1e0[0x20];
2395 };
2396
2397 struct mlx5_ifc_pkey_bits {
2398         u8         reserved_at_0[0x10];
2399         u8         pkey[0x10];
2400 };
2401
2402 struct mlx5_ifc_array128_auto_bits {
2403         u8         array128_auto[16][0x8];
2404 };
2405
2406 struct mlx5_ifc_hca_vport_context_bits {
2407         u8         field_select[0x20];
2408
2409         u8         reserved_at_20[0xe0];
2410
2411         u8         sm_virt_aware[0x1];
2412         u8         has_smi[0x1];
2413         u8         has_raw[0x1];
2414         u8         grh_required[0x1];
2415         u8         reserved_at_104[0xc];
2416         u8         port_physical_state[0x4];
2417         u8         vport_state_policy[0x4];
2418         u8         port_state[0x4];
2419         u8         vport_state[0x4];
2420
2421         u8         reserved_at_120[0x20];
2422
2423         u8         system_image_guid[0x40];
2424
2425         u8         port_guid[0x40];
2426
2427         u8         node_guid[0x40];
2428
2429         u8         cap_mask1[0x20];
2430
2431         u8         cap_mask1_field_select[0x20];
2432
2433         u8         cap_mask2[0x20];
2434
2435         u8         cap_mask2_field_select[0x20];
2436
2437         u8         reserved_at_280[0x80];
2438
2439         u8         lid[0x10];
2440         u8         reserved_at_310[0x4];
2441         u8         init_type_reply[0x4];
2442         u8         lmc[0x3];
2443         u8         subnet_timeout[0x5];
2444
2445         u8         sm_lid[0x10];
2446         u8         sm_sl[0x4];
2447         u8         reserved_at_334[0xc];
2448
2449         u8         qkey_violation_counter[0x10];
2450         u8         pkey_violation_counter[0x10];
2451
2452         u8         reserved_at_360[0xca0];
2453 };
2454
2455 struct mlx5_ifc_esw_vport_context_bits {
2456         u8         reserved_at_0[0x3];
2457         u8         vport_svlan_strip[0x1];
2458         u8         vport_cvlan_strip[0x1];
2459         u8         vport_svlan_insert[0x1];
2460         u8         vport_cvlan_insert[0x2];
2461         u8         reserved_at_8[0x18];
2462
2463         u8         reserved_at_20[0x20];
2464
2465         u8         svlan_cfi[0x1];
2466         u8         svlan_pcp[0x3];
2467         u8         svlan_id[0xc];
2468         u8         cvlan_cfi[0x1];
2469         u8         cvlan_pcp[0x3];
2470         u8         cvlan_id[0xc];
2471
2472         u8         reserved_at_60[0x7a0];
2473 };
2474
2475 enum {
2476         MLX5_EQC_STATUS_OK                = 0x0,
2477         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2478 };
2479
2480 enum {
2481         MLX5_EQC_ST_ARMED  = 0x9,
2482         MLX5_EQC_ST_FIRED  = 0xa,
2483 };
2484
2485 struct mlx5_ifc_eqc_bits {
2486         u8         status[0x4];
2487         u8         reserved_at_4[0x9];
2488         u8         ec[0x1];
2489         u8         oi[0x1];
2490         u8         reserved_at_f[0x5];
2491         u8         st[0x4];
2492         u8         reserved_at_18[0x8];
2493
2494         u8         reserved_at_20[0x20];
2495
2496         u8         reserved_at_40[0x14];
2497         u8         page_offset[0x6];
2498         u8         reserved_at_5a[0x6];
2499
2500         u8         reserved_at_60[0x3];
2501         u8         log_eq_size[0x5];
2502         u8         uar_page[0x18];
2503
2504         u8         reserved_at_80[0x20];
2505
2506         u8         reserved_at_a0[0x18];
2507         u8         intr[0x8];
2508
2509         u8         reserved_at_c0[0x3];
2510         u8         log_page_size[0x5];
2511         u8         reserved_at_c8[0x18];
2512
2513         u8         reserved_at_e0[0x60];
2514
2515         u8         reserved_at_140[0x8];
2516         u8         consumer_counter[0x18];
2517
2518         u8         reserved_at_160[0x8];
2519         u8         producer_counter[0x18];
2520
2521         u8         reserved_at_180[0x80];
2522 };
2523
2524 enum {
2525         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2526         MLX5_DCTC_STATE_DRAINING  = 0x1,
2527         MLX5_DCTC_STATE_DRAINED   = 0x2,
2528 };
2529
2530 enum {
2531         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2532         MLX5_DCTC_CS_RES_NA         = 0x1,
2533         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2534 };
2535
2536 enum {
2537         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2538         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2539         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2540         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2541         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2542 };
2543
2544 struct mlx5_ifc_dctc_bits {
2545         u8         reserved_at_0[0x4];
2546         u8         state[0x4];
2547         u8         reserved_at_8[0x18];
2548
2549         u8         reserved_at_20[0x8];
2550         u8         user_index[0x18];
2551
2552         u8         reserved_at_40[0x8];
2553         u8         cqn[0x18];
2554
2555         u8         counter_set_id[0x8];
2556         u8         atomic_mode[0x4];
2557         u8         rre[0x1];
2558         u8         rwe[0x1];
2559         u8         rae[0x1];
2560         u8         atomic_like_write_en[0x1];
2561         u8         latency_sensitive[0x1];
2562         u8         rlky[0x1];
2563         u8         free_ar[0x1];
2564         u8         reserved_at_73[0xd];
2565
2566         u8         reserved_at_80[0x8];
2567         u8         cs_res[0x8];
2568         u8         reserved_at_90[0x3];
2569         u8         min_rnr_nak[0x5];
2570         u8         reserved_at_98[0x8];
2571
2572         u8         reserved_at_a0[0x8];
2573         u8         srqn[0x18];
2574
2575         u8         reserved_at_c0[0x8];
2576         u8         pd[0x18];
2577
2578         u8         tclass[0x8];
2579         u8         reserved_at_e8[0x4];
2580         u8         flow_label[0x14];
2581
2582         u8         dc_access_key[0x40];
2583
2584         u8         reserved_at_140[0x5];
2585         u8         mtu[0x3];
2586         u8         port[0x8];
2587         u8         pkey_index[0x10];
2588
2589         u8         reserved_at_160[0x8];
2590         u8         my_addr_index[0x8];
2591         u8         reserved_at_170[0x8];
2592         u8         hop_limit[0x8];
2593
2594         u8         dc_access_key_violation_count[0x20];
2595
2596         u8         reserved_at_1a0[0x14];
2597         u8         dei_cfi[0x1];
2598         u8         eth_prio[0x3];
2599         u8         ecn[0x2];
2600         u8         dscp[0x6];
2601
2602         u8         reserved_at_1c0[0x40];
2603 };
2604
2605 enum {
2606         MLX5_CQC_STATUS_OK             = 0x0,
2607         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2608         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2609 };
2610
2611 enum {
2612         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2613         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2614 };
2615
2616 enum {
2617         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2618         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2619         MLX5_CQC_ST_FIRED                                 = 0xa,
2620 };
2621
2622 enum {
2623         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2624         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2625 };
2626
2627 struct mlx5_ifc_cqc_bits {
2628         u8         status[0x4];
2629         u8         reserved_at_4[0x4];
2630         u8         cqe_sz[0x3];
2631         u8         cc[0x1];
2632         u8         reserved_at_c[0x1];
2633         u8         scqe_break_moderation_en[0x1];
2634         u8         oi[0x1];
2635         u8         cq_period_mode[0x2];
2636         u8         cqe_comp_en[0x1];
2637         u8         mini_cqe_res_format[0x2];
2638         u8         st[0x4];
2639         u8         reserved_at_18[0x8];
2640
2641         u8         reserved_at_20[0x20];
2642
2643         u8         reserved_at_40[0x14];
2644         u8         page_offset[0x6];
2645         u8         reserved_at_5a[0x6];
2646
2647         u8         reserved_at_60[0x3];
2648         u8         log_cq_size[0x5];
2649         u8         uar_page[0x18];
2650
2651         u8         reserved_at_80[0x4];
2652         u8         cq_period[0xc];
2653         u8         cq_max_count[0x10];
2654
2655         u8         reserved_at_a0[0x18];
2656         u8         c_eqn[0x8];
2657
2658         u8         reserved_at_c0[0x3];
2659         u8         log_page_size[0x5];
2660         u8         reserved_at_c8[0x18];
2661
2662         u8         reserved_at_e0[0x20];
2663
2664         u8         reserved_at_100[0x8];
2665         u8         last_notified_index[0x18];
2666
2667         u8         reserved_at_120[0x8];
2668         u8         last_solicit_index[0x18];
2669
2670         u8         reserved_at_140[0x8];
2671         u8         consumer_counter[0x18];
2672
2673         u8         reserved_at_160[0x8];
2674         u8         producer_counter[0x18];
2675
2676         u8         reserved_at_180[0x40];
2677
2678         u8         dbr_addr[0x40];
2679 };
2680
2681 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2682         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2683         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2684         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2685         u8         reserved_at_0[0x800];
2686 };
2687
2688 struct mlx5_ifc_query_adapter_param_block_bits {
2689         u8         reserved_at_0[0xc0];
2690
2691         u8         reserved_at_c0[0x8];
2692         u8         ieee_vendor_id[0x18];
2693
2694         u8         reserved_at_e0[0x10];
2695         u8         vsd_vendor_id[0x10];
2696
2697         u8         vsd[208][0x8];
2698
2699         u8         vsd_contd_psid[16][0x8];
2700 };
2701
2702 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2703         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2704         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2705         u8         reserved_at_0[0x20];
2706 };
2707
2708 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2709         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2710         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2711         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2712         u8         reserved_at_0[0x20];
2713 };
2714
2715 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2716         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2717         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2718         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2719         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2720         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2721         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2722         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2723         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2724         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2725         u8         reserved_at_0[0x7c0];
2726 };
2727
2728 union mlx5_ifc_event_auto_bits {
2729         struct mlx5_ifc_comp_event_bits comp_event;
2730         struct mlx5_ifc_dct_events_bits dct_events;
2731         struct mlx5_ifc_qp_events_bits qp_events;
2732         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2733         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2734         struct mlx5_ifc_cq_error_bits cq_error;
2735         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2736         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2737         struct mlx5_ifc_gpio_event_bits gpio_event;
2738         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2739         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2740         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2741         u8         reserved_at_0[0xe0];
2742 };
2743
2744 struct mlx5_ifc_health_buffer_bits {
2745         u8         reserved_at_0[0x100];
2746
2747         u8         assert_existptr[0x20];
2748
2749         u8         assert_callra[0x20];
2750
2751         u8         reserved_at_140[0x40];
2752
2753         u8         fw_version[0x20];
2754
2755         u8         hw_id[0x20];
2756
2757         u8         reserved_at_1c0[0x20];
2758
2759         u8         irisc_index[0x8];
2760         u8         synd[0x8];
2761         u8         ext_synd[0x10];
2762 };
2763
2764 struct mlx5_ifc_register_loopback_control_bits {
2765         u8         no_lb[0x1];
2766         u8         reserved_at_1[0x7];
2767         u8         port[0x8];
2768         u8         reserved_at_10[0x10];
2769
2770         u8         reserved_at_20[0x60];
2771 };
2772
2773 struct mlx5_ifc_teardown_hca_out_bits {
2774         u8         status[0x8];
2775         u8         reserved_at_8[0x18];
2776
2777         u8         syndrome[0x20];
2778
2779         u8         reserved_at_40[0x40];
2780 };
2781
2782 enum {
2783         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
2784         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
2785 };
2786
2787 struct mlx5_ifc_teardown_hca_in_bits {
2788         u8         opcode[0x10];
2789         u8         reserved_at_10[0x10];
2790
2791         u8         reserved_at_20[0x10];
2792         u8         op_mod[0x10];
2793
2794         u8         reserved_at_40[0x10];
2795         u8         profile[0x10];
2796
2797         u8         reserved_at_60[0x20];
2798 };
2799
2800 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2801         u8         status[0x8];
2802         u8         reserved_at_8[0x18];
2803
2804         u8         syndrome[0x20];
2805
2806         u8         reserved_at_40[0x40];
2807 };
2808
2809 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2810         u8         opcode[0x10];
2811         u8         reserved_at_10[0x10];
2812
2813         u8         reserved_at_20[0x10];
2814         u8         op_mod[0x10];
2815
2816         u8         reserved_at_40[0x8];
2817         u8         qpn[0x18];
2818
2819         u8         reserved_at_60[0x20];
2820
2821         u8         opt_param_mask[0x20];
2822
2823         u8         reserved_at_a0[0x20];
2824
2825         struct mlx5_ifc_qpc_bits qpc;
2826
2827         u8         reserved_at_800[0x80];
2828 };
2829
2830 struct mlx5_ifc_sqd2rts_qp_out_bits {
2831         u8         status[0x8];
2832         u8         reserved_at_8[0x18];
2833
2834         u8         syndrome[0x20];
2835
2836         u8         reserved_at_40[0x40];
2837 };
2838
2839 struct mlx5_ifc_sqd2rts_qp_in_bits {
2840         u8         opcode[0x10];
2841         u8         reserved_at_10[0x10];
2842
2843         u8         reserved_at_20[0x10];
2844         u8         op_mod[0x10];
2845
2846         u8         reserved_at_40[0x8];
2847         u8         qpn[0x18];
2848
2849         u8         reserved_at_60[0x20];
2850
2851         u8         opt_param_mask[0x20];
2852
2853         u8         reserved_at_a0[0x20];
2854
2855         struct mlx5_ifc_qpc_bits qpc;
2856
2857         u8         reserved_at_800[0x80];
2858 };
2859
2860 struct mlx5_ifc_set_roce_address_out_bits {
2861         u8         status[0x8];
2862         u8         reserved_at_8[0x18];
2863
2864         u8         syndrome[0x20];
2865
2866         u8         reserved_at_40[0x40];
2867 };
2868
2869 struct mlx5_ifc_set_roce_address_in_bits {
2870         u8         opcode[0x10];
2871         u8         reserved_at_10[0x10];
2872
2873         u8         reserved_at_20[0x10];
2874         u8         op_mod[0x10];
2875
2876         u8         roce_address_index[0x10];
2877         u8         reserved_at_50[0x10];
2878
2879         u8         reserved_at_60[0x20];
2880
2881         struct mlx5_ifc_roce_addr_layout_bits roce_address;
2882 };
2883
2884 struct mlx5_ifc_set_mad_demux_out_bits {
2885         u8         status[0x8];
2886         u8         reserved_at_8[0x18];
2887
2888         u8         syndrome[0x20];
2889
2890         u8         reserved_at_40[0x40];
2891 };
2892
2893 enum {
2894         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
2895         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
2896 };
2897
2898 struct mlx5_ifc_set_mad_demux_in_bits {
2899         u8         opcode[0x10];
2900         u8         reserved_at_10[0x10];
2901
2902         u8         reserved_at_20[0x10];
2903         u8         op_mod[0x10];
2904
2905         u8         reserved_at_40[0x20];
2906
2907         u8         reserved_at_60[0x6];
2908         u8         demux_mode[0x2];
2909         u8         reserved_at_68[0x18];
2910 };
2911
2912 struct mlx5_ifc_set_l2_table_entry_out_bits {
2913         u8         status[0x8];
2914         u8         reserved_at_8[0x18];
2915
2916         u8         syndrome[0x20];
2917
2918         u8         reserved_at_40[0x40];
2919 };
2920
2921 struct mlx5_ifc_set_l2_table_entry_in_bits {
2922         u8         opcode[0x10];
2923         u8         reserved_at_10[0x10];
2924
2925         u8         reserved_at_20[0x10];
2926         u8         op_mod[0x10];
2927
2928         u8         reserved_at_40[0x60];
2929
2930         u8         reserved_at_a0[0x8];
2931         u8         table_index[0x18];
2932
2933         u8         reserved_at_c0[0x20];
2934
2935         u8         reserved_at_e0[0x13];
2936         u8         vlan_valid[0x1];
2937         u8         vlan[0xc];
2938
2939         struct mlx5_ifc_mac_address_layout_bits mac_address;
2940
2941         u8         reserved_at_140[0xc0];
2942 };
2943
2944 struct mlx5_ifc_set_issi_out_bits {
2945         u8         status[0x8];
2946         u8         reserved_at_8[0x18];
2947
2948         u8         syndrome[0x20];
2949
2950         u8         reserved_at_40[0x40];
2951 };
2952
2953 struct mlx5_ifc_set_issi_in_bits {
2954         u8         opcode[0x10];
2955         u8         reserved_at_10[0x10];
2956
2957         u8         reserved_at_20[0x10];
2958         u8         op_mod[0x10];
2959
2960         u8         reserved_at_40[0x10];
2961         u8         current_issi[0x10];
2962
2963         u8         reserved_at_60[0x20];
2964 };
2965
2966 struct mlx5_ifc_set_hca_cap_out_bits {
2967         u8         status[0x8];
2968         u8         reserved_at_8[0x18];
2969
2970         u8         syndrome[0x20];
2971
2972         u8         reserved_at_40[0x40];
2973 };
2974
2975 struct mlx5_ifc_set_hca_cap_in_bits {
2976         u8         opcode[0x10];
2977         u8         reserved_at_10[0x10];
2978
2979         u8         reserved_at_20[0x10];
2980         u8         op_mod[0x10];
2981
2982         u8         reserved_at_40[0x40];
2983
2984         union mlx5_ifc_hca_cap_union_bits capability;
2985 };
2986
2987 enum {
2988         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
2989         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
2990         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
2991         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
2992 };
2993
2994 struct mlx5_ifc_set_fte_out_bits {
2995         u8         status[0x8];
2996         u8         reserved_at_8[0x18];
2997
2998         u8         syndrome[0x20];
2999
3000         u8         reserved_at_40[0x40];
3001 };
3002
3003 struct mlx5_ifc_set_fte_in_bits {
3004         u8         opcode[0x10];
3005         u8         reserved_at_10[0x10];
3006
3007         u8         reserved_at_20[0x10];
3008         u8         op_mod[0x10];
3009
3010         u8         other_vport[0x1];
3011         u8         reserved_at_41[0xf];
3012         u8         vport_number[0x10];
3013
3014         u8         reserved_at_60[0x20];
3015
3016         u8         table_type[0x8];
3017         u8         reserved_at_88[0x18];
3018
3019         u8         reserved_at_a0[0x8];
3020         u8         table_id[0x18];
3021
3022         u8         reserved_at_c0[0x18];
3023         u8         modify_enable_mask[0x8];
3024
3025         u8         reserved_at_e0[0x20];
3026
3027         u8         flow_index[0x20];
3028
3029         u8         reserved_at_120[0xe0];
3030
3031         struct mlx5_ifc_flow_context_bits flow_context;
3032 };
3033
3034 struct mlx5_ifc_rts2rts_qp_out_bits {
3035         u8         status[0x8];
3036         u8         reserved_at_8[0x18];
3037
3038         u8         syndrome[0x20];
3039
3040         u8         reserved_at_40[0x40];
3041 };
3042
3043 struct mlx5_ifc_rts2rts_qp_in_bits {
3044         u8         opcode[0x10];
3045         u8         reserved_at_10[0x10];
3046
3047         u8         reserved_at_20[0x10];
3048         u8         op_mod[0x10];
3049
3050         u8         reserved_at_40[0x8];
3051         u8         qpn[0x18];
3052
3053         u8         reserved_at_60[0x20];
3054
3055         u8         opt_param_mask[0x20];
3056
3057         u8         reserved_at_a0[0x20];
3058
3059         struct mlx5_ifc_qpc_bits qpc;
3060
3061         u8         reserved_at_800[0x80];
3062 };
3063
3064 struct mlx5_ifc_rtr2rts_qp_out_bits {
3065         u8         status[0x8];
3066         u8         reserved_at_8[0x18];
3067
3068         u8         syndrome[0x20];
3069
3070         u8         reserved_at_40[0x40];
3071 };
3072
3073 struct mlx5_ifc_rtr2rts_qp_in_bits {
3074         u8         opcode[0x10];
3075         u8         reserved_at_10[0x10];
3076
3077         u8         reserved_at_20[0x10];
3078         u8         op_mod[0x10];
3079
3080         u8         reserved_at_40[0x8];
3081         u8         qpn[0x18];
3082
3083         u8         reserved_at_60[0x20];
3084
3085         u8         opt_param_mask[0x20];
3086
3087         u8         reserved_at_a0[0x20];
3088
3089         struct mlx5_ifc_qpc_bits qpc;
3090
3091         u8         reserved_at_800[0x80];
3092 };
3093
3094 struct mlx5_ifc_rst2init_qp_out_bits {
3095         u8         status[0x8];
3096         u8         reserved_at_8[0x18];
3097
3098         u8         syndrome[0x20];
3099
3100         u8         reserved_at_40[0x40];
3101 };
3102
3103 struct mlx5_ifc_rst2init_qp_in_bits {
3104         u8         opcode[0x10];
3105         u8         reserved_at_10[0x10];
3106
3107         u8         reserved_at_20[0x10];
3108         u8         op_mod[0x10];
3109
3110         u8         reserved_at_40[0x8];
3111         u8         qpn[0x18];
3112
3113         u8         reserved_at_60[0x20];
3114
3115         u8         opt_param_mask[0x20];
3116
3117         u8         reserved_at_a0[0x20];
3118
3119         struct mlx5_ifc_qpc_bits qpc;
3120
3121         u8         reserved_at_800[0x80];
3122 };
3123
3124 struct mlx5_ifc_query_xrc_srq_out_bits {
3125         u8         status[0x8];
3126         u8         reserved_at_8[0x18];
3127
3128         u8         syndrome[0x20];
3129
3130         u8         reserved_at_40[0x40];
3131
3132         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3133
3134         u8         reserved_at_280[0x600];
3135
3136         u8         pas[0][0x40];
3137 };
3138
3139 struct mlx5_ifc_query_xrc_srq_in_bits {
3140         u8         opcode[0x10];
3141         u8         reserved_at_10[0x10];
3142
3143         u8         reserved_at_20[0x10];
3144         u8         op_mod[0x10];
3145
3146         u8         reserved_at_40[0x8];
3147         u8         xrc_srqn[0x18];
3148
3149         u8         reserved_at_60[0x20];
3150 };
3151
3152 enum {
3153         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3154         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3155 };
3156
3157 struct mlx5_ifc_query_vport_state_out_bits {
3158         u8         status[0x8];
3159         u8         reserved_at_8[0x18];
3160
3161         u8         syndrome[0x20];
3162
3163         u8         reserved_at_40[0x20];
3164
3165         u8         reserved_at_60[0x18];
3166         u8         admin_state[0x4];
3167         u8         state[0x4];
3168 };
3169
3170 enum {
3171         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3172         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3173 };
3174
3175 struct mlx5_ifc_query_vport_state_in_bits {
3176         u8         opcode[0x10];
3177         u8         reserved_at_10[0x10];
3178
3179         u8         reserved_at_20[0x10];
3180         u8         op_mod[0x10];
3181
3182         u8         other_vport[0x1];
3183         u8         reserved_at_41[0xf];
3184         u8         vport_number[0x10];
3185
3186         u8         reserved_at_60[0x20];
3187 };
3188
3189 struct mlx5_ifc_query_vport_counter_out_bits {
3190         u8         status[0x8];
3191         u8         reserved_at_8[0x18];
3192
3193         u8         syndrome[0x20];
3194
3195         u8         reserved_at_40[0x40];
3196
3197         struct mlx5_ifc_traffic_counter_bits received_errors;
3198
3199         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3200
3201         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3202
3203         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3204
3205         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3206
3207         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3208
3209         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3210
3211         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3212
3213         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3214
3215         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3216
3217         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3218
3219         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3220
3221         u8         reserved_at_680[0xa00];
3222 };
3223
3224 enum {
3225         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3226 };
3227
3228 struct mlx5_ifc_query_vport_counter_in_bits {
3229         u8         opcode[0x10];
3230         u8         reserved_at_10[0x10];
3231
3232         u8         reserved_at_20[0x10];
3233         u8         op_mod[0x10];
3234
3235         u8         other_vport[0x1];
3236         u8         reserved_at_41[0xb];
3237         u8         port_num[0x4];
3238         u8         vport_number[0x10];
3239
3240         u8         reserved_at_60[0x60];
3241
3242         u8         clear[0x1];
3243         u8         reserved_at_c1[0x1f];
3244
3245         u8         reserved_at_e0[0x20];
3246 };
3247
3248 struct mlx5_ifc_query_tis_out_bits {
3249         u8         status[0x8];
3250         u8         reserved_at_8[0x18];
3251
3252         u8         syndrome[0x20];
3253
3254         u8         reserved_at_40[0x40];
3255
3256         struct mlx5_ifc_tisc_bits tis_context;
3257 };
3258
3259 struct mlx5_ifc_query_tis_in_bits {
3260         u8         opcode[0x10];
3261         u8         reserved_at_10[0x10];
3262
3263         u8         reserved_at_20[0x10];
3264         u8         op_mod[0x10];
3265
3266         u8         reserved_at_40[0x8];
3267         u8         tisn[0x18];
3268
3269         u8         reserved_at_60[0x20];
3270 };
3271
3272 struct mlx5_ifc_query_tir_out_bits {
3273         u8         status[0x8];
3274         u8         reserved_at_8[0x18];
3275
3276         u8         syndrome[0x20];
3277
3278         u8         reserved_at_40[0xc0];
3279
3280         struct mlx5_ifc_tirc_bits tir_context;
3281 };
3282
3283 struct mlx5_ifc_query_tir_in_bits {
3284         u8         opcode[0x10];
3285         u8         reserved_at_10[0x10];
3286
3287         u8         reserved_at_20[0x10];
3288         u8         op_mod[0x10];
3289
3290         u8         reserved_at_40[0x8];
3291         u8         tirn[0x18];
3292
3293         u8         reserved_at_60[0x20];
3294 };
3295
3296 struct mlx5_ifc_query_srq_out_bits {
3297         u8         status[0x8];
3298         u8         reserved_at_8[0x18];
3299
3300         u8         syndrome[0x20];
3301
3302         u8         reserved_at_40[0x40];
3303
3304         struct mlx5_ifc_srqc_bits srq_context_entry;
3305
3306         u8         reserved_at_280[0x600];
3307
3308         u8         pas[0][0x40];
3309 };
3310
3311 struct mlx5_ifc_query_srq_in_bits {
3312         u8         opcode[0x10];
3313         u8         reserved_at_10[0x10];
3314
3315         u8         reserved_at_20[0x10];
3316         u8         op_mod[0x10];
3317
3318         u8         reserved_at_40[0x8];
3319         u8         srqn[0x18];
3320
3321         u8         reserved_at_60[0x20];
3322 };
3323
3324 struct mlx5_ifc_query_sq_out_bits {
3325         u8         status[0x8];
3326         u8         reserved_at_8[0x18];
3327
3328         u8         syndrome[0x20];
3329
3330         u8         reserved_at_40[0xc0];
3331
3332         struct mlx5_ifc_sqc_bits sq_context;
3333 };
3334
3335 struct mlx5_ifc_query_sq_in_bits {
3336         u8         opcode[0x10];
3337         u8         reserved_at_10[0x10];
3338
3339         u8         reserved_at_20[0x10];
3340         u8         op_mod[0x10];
3341
3342         u8         reserved_at_40[0x8];
3343         u8         sqn[0x18];
3344
3345         u8         reserved_at_60[0x20];
3346 };
3347
3348 struct mlx5_ifc_query_special_contexts_out_bits {
3349         u8         status[0x8];
3350         u8         reserved_at_8[0x18];
3351
3352         u8         syndrome[0x20];
3353
3354         u8         reserved_at_40[0x20];
3355
3356         u8         resd_lkey[0x20];
3357 };
3358
3359 struct mlx5_ifc_query_special_contexts_in_bits {
3360         u8         opcode[0x10];
3361         u8         reserved_at_10[0x10];
3362
3363         u8         reserved_at_20[0x10];
3364         u8         op_mod[0x10];
3365
3366         u8         reserved_at_40[0x40];
3367 };
3368
3369 struct mlx5_ifc_query_rqt_out_bits {
3370         u8         status[0x8];
3371         u8         reserved_at_8[0x18];
3372
3373         u8         syndrome[0x20];
3374
3375         u8         reserved_at_40[0xc0];
3376
3377         struct mlx5_ifc_rqtc_bits rqt_context;
3378 };
3379
3380 struct mlx5_ifc_query_rqt_in_bits {
3381         u8         opcode[0x10];
3382         u8         reserved_at_10[0x10];
3383
3384         u8         reserved_at_20[0x10];
3385         u8         op_mod[0x10];
3386
3387         u8         reserved_at_40[0x8];
3388         u8         rqtn[0x18];
3389
3390         u8         reserved_at_60[0x20];
3391 };
3392
3393 struct mlx5_ifc_query_rq_out_bits {
3394         u8         status[0x8];
3395         u8         reserved_at_8[0x18];
3396
3397         u8         syndrome[0x20];
3398
3399         u8         reserved_at_40[0xc0];
3400
3401         struct mlx5_ifc_rqc_bits rq_context;
3402 };
3403
3404 struct mlx5_ifc_query_rq_in_bits {
3405         u8         opcode[0x10];
3406         u8         reserved_at_10[0x10];
3407
3408         u8         reserved_at_20[0x10];
3409         u8         op_mod[0x10];
3410
3411         u8         reserved_at_40[0x8];
3412         u8         rqn[0x18];
3413
3414         u8         reserved_at_60[0x20];
3415 };
3416
3417 struct mlx5_ifc_query_roce_address_out_bits {
3418         u8         status[0x8];
3419         u8         reserved_at_8[0x18];
3420
3421         u8         syndrome[0x20];
3422
3423         u8         reserved_at_40[0x40];
3424
3425         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3426 };
3427
3428 struct mlx5_ifc_query_roce_address_in_bits {
3429         u8         opcode[0x10];
3430         u8         reserved_at_10[0x10];
3431
3432         u8         reserved_at_20[0x10];
3433         u8         op_mod[0x10];
3434
3435         u8         roce_address_index[0x10];
3436         u8         reserved_at_50[0x10];
3437
3438         u8         reserved_at_60[0x20];
3439 };
3440
3441 struct mlx5_ifc_query_rmp_out_bits {
3442         u8         status[0x8];
3443         u8         reserved_at_8[0x18];
3444
3445         u8         syndrome[0x20];
3446
3447         u8         reserved_at_40[0xc0];
3448
3449         struct mlx5_ifc_rmpc_bits rmp_context;
3450 };
3451
3452 struct mlx5_ifc_query_rmp_in_bits {
3453         u8         opcode[0x10];
3454         u8         reserved_at_10[0x10];
3455
3456         u8         reserved_at_20[0x10];
3457         u8         op_mod[0x10];
3458
3459         u8         reserved_at_40[0x8];
3460         u8         rmpn[0x18];
3461
3462         u8         reserved_at_60[0x20];
3463 };
3464
3465 struct mlx5_ifc_query_qp_out_bits {
3466         u8         status[0x8];
3467         u8         reserved_at_8[0x18];
3468
3469         u8         syndrome[0x20];
3470
3471         u8         reserved_at_40[0x40];
3472
3473         u8         opt_param_mask[0x20];
3474
3475         u8         reserved_at_a0[0x20];
3476
3477         struct mlx5_ifc_qpc_bits qpc;
3478
3479         u8         reserved_at_800[0x80];
3480
3481         u8         pas[0][0x40];
3482 };
3483
3484 struct mlx5_ifc_query_qp_in_bits {
3485         u8         opcode[0x10];
3486         u8         reserved_at_10[0x10];
3487
3488         u8         reserved_at_20[0x10];
3489         u8         op_mod[0x10];
3490
3491         u8         reserved_at_40[0x8];
3492         u8         qpn[0x18];
3493
3494         u8         reserved_at_60[0x20];
3495 };
3496
3497 struct mlx5_ifc_query_q_counter_out_bits {
3498         u8         status[0x8];
3499         u8         reserved_at_8[0x18];
3500
3501         u8         syndrome[0x20];
3502
3503         u8         reserved_at_40[0x40];
3504
3505         u8         rx_write_requests[0x20];
3506
3507         u8         reserved_at_a0[0x20];
3508
3509         u8         rx_read_requests[0x20];
3510
3511         u8         reserved_at_e0[0x20];
3512
3513         u8         rx_atomic_requests[0x20];
3514
3515         u8         reserved_at_120[0x20];
3516
3517         u8         rx_dct_connect[0x20];
3518
3519         u8         reserved_at_160[0x20];
3520
3521         u8         out_of_buffer[0x20];
3522
3523         u8         reserved_at_1a0[0x20];
3524
3525         u8         out_of_sequence[0x20];
3526
3527         u8         reserved_at_1e0[0x620];
3528 };
3529
3530 struct mlx5_ifc_query_q_counter_in_bits {
3531         u8         opcode[0x10];
3532         u8         reserved_at_10[0x10];
3533
3534         u8         reserved_at_20[0x10];
3535         u8         op_mod[0x10];
3536
3537         u8         reserved_at_40[0x80];
3538
3539         u8         clear[0x1];
3540         u8         reserved_at_c1[0x1f];
3541
3542         u8         reserved_at_e0[0x18];
3543         u8         counter_set_id[0x8];
3544 };
3545
3546 struct mlx5_ifc_query_pages_out_bits {
3547         u8         status[0x8];
3548         u8         reserved_at_8[0x18];
3549
3550         u8         syndrome[0x20];
3551
3552         u8         reserved_at_40[0x10];
3553         u8         function_id[0x10];
3554
3555         u8         num_pages[0x20];
3556 };
3557
3558 enum {
3559         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3560         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3561         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3562 };
3563
3564 struct mlx5_ifc_query_pages_in_bits {
3565         u8         opcode[0x10];
3566         u8         reserved_at_10[0x10];
3567
3568         u8         reserved_at_20[0x10];
3569         u8         op_mod[0x10];
3570
3571         u8         reserved_at_40[0x10];
3572         u8         function_id[0x10];
3573
3574         u8         reserved_at_60[0x20];
3575 };
3576
3577 struct mlx5_ifc_query_nic_vport_context_out_bits {
3578         u8         status[0x8];
3579         u8         reserved_at_8[0x18];
3580
3581         u8         syndrome[0x20];
3582
3583         u8         reserved_at_40[0x40];
3584
3585         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3586 };
3587
3588 struct mlx5_ifc_query_nic_vport_context_in_bits {
3589         u8         opcode[0x10];
3590         u8         reserved_at_10[0x10];
3591
3592         u8         reserved_at_20[0x10];
3593         u8         op_mod[0x10];
3594
3595         u8         other_vport[0x1];
3596         u8         reserved_at_41[0xf];
3597         u8         vport_number[0x10];
3598
3599         u8         reserved_at_60[0x5];
3600         u8         allowed_list_type[0x3];
3601         u8         reserved_at_68[0x18];
3602 };
3603
3604 struct mlx5_ifc_query_mkey_out_bits {
3605         u8         status[0x8];
3606         u8         reserved_at_8[0x18];
3607
3608         u8         syndrome[0x20];
3609
3610         u8         reserved_at_40[0x40];
3611
3612         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3613
3614         u8         reserved_at_280[0x600];
3615
3616         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3617
3618         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3619 };
3620
3621 struct mlx5_ifc_query_mkey_in_bits {
3622         u8         opcode[0x10];
3623         u8         reserved_at_10[0x10];
3624
3625         u8         reserved_at_20[0x10];
3626         u8         op_mod[0x10];
3627
3628         u8         reserved_at_40[0x8];
3629         u8         mkey_index[0x18];
3630
3631         u8         pg_access[0x1];
3632         u8         reserved_at_61[0x1f];
3633 };
3634
3635 struct mlx5_ifc_query_mad_demux_out_bits {
3636         u8         status[0x8];
3637         u8         reserved_at_8[0x18];
3638
3639         u8         syndrome[0x20];
3640
3641         u8         reserved_at_40[0x40];
3642
3643         u8         mad_dumux_parameters_block[0x20];
3644 };
3645
3646 struct mlx5_ifc_query_mad_demux_in_bits {
3647         u8         opcode[0x10];
3648         u8         reserved_at_10[0x10];
3649
3650         u8         reserved_at_20[0x10];
3651         u8         op_mod[0x10];
3652
3653         u8         reserved_at_40[0x40];
3654 };
3655
3656 struct mlx5_ifc_query_l2_table_entry_out_bits {
3657         u8         status[0x8];
3658         u8         reserved_at_8[0x18];
3659
3660         u8         syndrome[0x20];
3661
3662         u8         reserved_at_40[0xa0];
3663
3664         u8         reserved_at_e0[0x13];
3665         u8         vlan_valid[0x1];
3666         u8         vlan[0xc];
3667
3668         struct mlx5_ifc_mac_address_layout_bits mac_address;
3669
3670         u8         reserved_at_140[0xc0];
3671 };
3672
3673 struct mlx5_ifc_query_l2_table_entry_in_bits {
3674         u8         opcode[0x10];
3675         u8         reserved_at_10[0x10];
3676
3677         u8         reserved_at_20[0x10];
3678         u8         op_mod[0x10];
3679
3680         u8         reserved_at_40[0x60];
3681
3682         u8         reserved_at_a0[0x8];
3683         u8         table_index[0x18];
3684
3685         u8         reserved_at_c0[0x140];
3686 };
3687
3688 struct mlx5_ifc_query_issi_out_bits {
3689         u8         status[0x8];
3690         u8         reserved_at_8[0x18];
3691
3692         u8         syndrome[0x20];
3693
3694         u8         reserved_at_40[0x10];
3695         u8         current_issi[0x10];
3696
3697         u8         reserved_at_60[0xa0];
3698
3699         u8         reserved_at_100[76][0x8];
3700         u8         supported_issi_dw0[0x20];
3701 };
3702
3703 struct mlx5_ifc_query_issi_in_bits {
3704         u8         opcode[0x10];
3705         u8         reserved_at_10[0x10];
3706
3707         u8         reserved_at_20[0x10];
3708         u8         op_mod[0x10];
3709
3710         u8         reserved_at_40[0x40];
3711 };
3712
3713 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3714         u8         status[0x8];
3715         u8         reserved_at_8[0x18];
3716
3717         u8         syndrome[0x20];
3718
3719         u8         reserved_at_40[0x40];
3720
3721         struct mlx5_ifc_pkey_bits pkey[0];
3722 };
3723
3724 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3725         u8         opcode[0x10];
3726         u8         reserved_at_10[0x10];
3727
3728         u8         reserved_at_20[0x10];
3729         u8         op_mod[0x10];
3730
3731         u8         other_vport[0x1];
3732         u8         reserved_at_41[0xb];
3733         u8         port_num[0x4];
3734         u8         vport_number[0x10];
3735
3736         u8         reserved_at_60[0x10];
3737         u8         pkey_index[0x10];
3738 };
3739
3740 enum {
3741         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
3742         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
3743         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
3744 };
3745
3746 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3747         u8         status[0x8];
3748         u8         reserved_at_8[0x18];
3749
3750         u8         syndrome[0x20];
3751
3752         u8         reserved_at_40[0x20];
3753
3754         u8         gids_num[0x10];
3755         u8         reserved_at_70[0x10];
3756
3757         struct mlx5_ifc_array128_auto_bits gid[0];
3758 };
3759
3760 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3761         u8         opcode[0x10];
3762         u8         reserved_at_10[0x10];
3763
3764         u8         reserved_at_20[0x10];
3765         u8         op_mod[0x10];
3766
3767         u8         other_vport[0x1];
3768         u8         reserved_at_41[0xb];
3769         u8         port_num[0x4];
3770         u8         vport_number[0x10];
3771
3772         u8         reserved_at_60[0x10];
3773         u8         gid_index[0x10];
3774 };
3775
3776 struct mlx5_ifc_query_hca_vport_context_out_bits {
3777         u8         status[0x8];
3778         u8         reserved_at_8[0x18];
3779
3780         u8         syndrome[0x20];
3781
3782         u8         reserved_at_40[0x40];
3783
3784         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3785 };
3786
3787 struct mlx5_ifc_query_hca_vport_context_in_bits {
3788         u8         opcode[0x10];
3789         u8         reserved_at_10[0x10];
3790
3791         u8         reserved_at_20[0x10];
3792         u8         op_mod[0x10];
3793
3794         u8         other_vport[0x1];
3795         u8         reserved_at_41[0xb];
3796         u8         port_num[0x4];
3797         u8         vport_number[0x10];
3798
3799         u8         reserved_at_60[0x20];
3800 };
3801
3802 struct mlx5_ifc_query_hca_cap_out_bits {
3803         u8         status[0x8];
3804         u8         reserved_at_8[0x18];
3805
3806         u8         syndrome[0x20];
3807
3808         u8         reserved_at_40[0x40];
3809
3810         union mlx5_ifc_hca_cap_union_bits capability;
3811 };
3812
3813 struct mlx5_ifc_query_hca_cap_in_bits {
3814         u8         opcode[0x10];
3815         u8         reserved_at_10[0x10];
3816
3817         u8         reserved_at_20[0x10];
3818         u8         op_mod[0x10];
3819
3820         u8         reserved_at_40[0x40];
3821 };
3822
3823 struct mlx5_ifc_query_flow_table_out_bits {
3824         u8         status[0x8];
3825         u8         reserved_at_8[0x18];
3826
3827         u8         syndrome[0x20];
3828
3829         u8         reserved_at_40[0x80];
3830
3831         u8         reserved_at_c0[0x8];
3832         u8         level[0x8];
3833         u8         reserved_at_d0[0x8];
3834         u8         log_size[0x8];
3835
3836         u8         reserved_at_e0[0x120];
3837 };
3838
3839 struct mlx5_ifc_query_flow_table_in_bits {
3840         u8         opcode[0x10];
3841         u8         reserved_at_10[0x10];
3842
3843         u8         reserved_at_20[0x10];
3844         u8         op_mod[0x10];
3845
3846         u8         reserved_at_40[0x40];
3847
3848         u8         table_type[0x8];
3849         u8         reserved_at_88[0x18];
3850
3851         u8         reserved_at_a0[0x8];
3852         u8         table_id[0x18];
3853
3854         u8         reserved_at_c0[0x140];
3855 };
3856
3857 struct mlx5_ifc_query_fte_out_bits {
3858         u8         status[0x8];
3859         u8         reserved_at_8[0x18];
3860
3861         u8         syndrome[0x20];
3862
3863         u8         reserved_at_40[0x1c0];
3864
3865         struct mlx5_ifc_flow_context_bits flow_context;
3866 };
3867
3868 struct mlx5_ifc_query_fte_in_bits {
3869         u8         opcode[0x10];
3870         u8         reserved_at_10[0x10];
3871
3872         u8         reserved_at_20[0x10];
3873         u8         op_mod[0x10];
3874
3875         u8         reserved_at_40[0x40];
3876
3877         u8         table_type[0x8];
3878         u8         reserved_at_88[0x18];
3879
3880         u8         reserved_at_a0[0x8];
3881         u8         table_id[0x18];
3882
3883         u8         reserved_at_c0[0x40];
3884
3885         u8         flow_index[0x20];
3886
3887         u8         reserved_at_120[0xe0];
3888 };
3889
3890 enum {
3891         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
3892         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
3893         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
3894 };
3895
3896 struct mlx5_ifc_query_flow_group_out_bits {
3897         u8         status[0x8];
3898         u8         reserved_at_8[0x18];
3899
3900         u8         syndrome[0x20];
3901
3902         u8         reserved_at_40[0xa0];
3903
3904         u8         start_flow_index[0x20];
3905
3906         u8         reserved_at_100[0x20];
3907
3908         u8         end_flow_index[0x20];
3909
3910         u8         reserved_at_140[0xa0];
3911
3912         u8         reserved_at_1e0[0x18];
3913         u8         match_criteria_enable[0x8];
3914
3915         struct mlx5_ifc_fte_match_param_bits match_criteria;
3916
3917         u8         reserved_at_1200[0xe00];
3918 };
3919
3920 struct mlx5_ifc_query_flow_group_in_bits {
3921         u8         opcode[0x10];
3922         u8         reserved_at_10[0x10];
3923
3924         u8         reserved_at_20[0x10];
3925         u8         op_mod[0x10];
3926
3927         u8         reserved_at_40[0x40];
3928
3929         u8         table_type[0x8];
3930         u8         reserved_at_88[0x18];
3931
3932         u8         reserved_at_a0[0x8];
3933         u8         table_id[0x18];
3934
3935         u8         group_id[0x20];
3936
3937         u8         reserved_at_e0[0x120];
3938 };
3939
3940 struct mlx5_ifc_query_esw_vport_context_out_bits {
3941         u8         status[0x8];
3942         u8         reserved_at_8[0x18];
3943
3944         u8         syndrome[0x20];
3945
3946         u8         reserved_at_40[0x40];
3947
3948         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3949 };
3950
3951 struct mlx5_ifc_query_esw_vport_context_in_bits {
3952         u8         opcode[0x10];
3953         u8         reserved_at_10[0x10];
3954
3955         u8         reserved_at_20[0x10];
3956         u8         op_mod[0x10];
3957
3958         u8         other_vport[0x1];
3959         u8         reserved_at_41[0xf];
3960         u8         vport_number[0x10];
3961
3962         u8         reserved_at_60[0x20];
3963 };
3964
3965 struct mlx5_ifc_modify_esw_vport_context_out_bits {
3966         u8         status[0x8];
3967         u8         reserved_at_8[0x18];
3968
3969         u8         syndrome[0x20];
3970
3971         u8         reserved_at_40[0x40];
3972 };
3973
3974 struct mlx5_ifc_esw_vport_context_fields_select_bits {
3975         u8         reserved_at_0[0x1c];
3976         u8         vport_cvlan_insert[0x1];
3977         u8         vport_svlan_insert[0x1];
3978         u8         vport_cvlan_strip[0x1];
3979         u8         vport_svlan_strip[0x1];
3980 };
3981
3982 struct mlx5_ifc_modify_esw_vport_context_in_bits {
3983         u8         opcode[0x10];
3984         u8         reserved_at_10[0x10];
3985
3986         u8         reserved_at_20[0x10];
3987         u8         op_mod[0x10];
3988
3989         u8         other_vport[0x1];
3990         u8         reserved_at_41[0xf];
3991         u8         vport_number[0x10];
3992
3993         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
3994
3995         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3996 };
3997
3998 struct mlx5_ifc_query_eq_out_bits {
3999         u8         status[0x8];
4000         u8         reserved_at_8[0x18];
4001
4002         u8         syndrome[0x20];
4003
4004         u8         reserved_at_40[0x40];
4005
4006         struct mlx5_ifc_eqc_bits eq_context_entry;
4007
4008         u8         reserved_at_280[0x40];
4009
4010         u8         event_bitmask[0x40];
4011
4012         u8         reserved_at_300[0x580];
4013
4014         u8         pas[0][0x40];
4015 };
4016
4017 struct mlx5_ifc_query_eq_in_bits {
4018         u8         opcode[0x10];
4019         u8         reserved_at_10[0x10];
4020
4021         u8         reserved_at_20[0x10];
4022         u8         op_mod[0x10];
4023
4024         u8         reserved_at_40[0x18];
4025         u8         eq_number[0x8];
4026
4027         u8         reserved_at_60[0x20];
4028 };
4029
4030 struct mlx5_ifc_query_dct_out_bits {
4031         u8         status[0x8];
4032         u8         reserved_at_8[0x18];
4033
4034         u8         syndrome[0x20];
4035
4036         u8         reserved_at_40[0x40];
4037
4038         struct mlx5_ifc_dctc_bits dct_context_entry;
4039
4040         u8         reserved_at_280[0x180];
4041 };
4042
4043 struct mlx5_ifc_query_dct_in_bits {
4044         u8         opcode[0x10];
4045         u8         reserved_at_10[0x10];
4046
4047         u8         reserved_at_20[0x10];
4048         u8         op_mod[0x10];
4049
4050         u8         reserved_at_40[0x8];
4051         u8         dctn[0x18];
4052
4053         u8         reserved_at_60[0x20];
4054 };
4055
4056 struct mlx5_ifc_query_cq_out_bits {
4057         u8         status[0x8];
4058         u8         reserved_at_8[0x18];
4059
4060         u8         syndrome[0x20];
4061
4062         u8         reserved_at_40[0x40];
4063
4064         struct mlx5_ifc_cqc_bits cq_context;
4065
4066         u8         reserved_at_280[0x600];
4067
4068         u8         pas[0][0x40];
4069 };
4070
4071 struct mlx5_ifc_query_cq_in_bits {
4072         u8         opcode[0x10];
4073         u8         reserved_at_10[0x10];
4074
4075         u8         reserved_at_20[0x10];
4076         u8         op_mod[0x10];
4077
4078         u8         reserved_at_40[0x8];
4079         u8         cqn[0x18];
4080
4081         u8         reserved_at_60[0x20];
4082 };
4083
4084 struct mlx5_ifc_query_cong_status_out_bits {
4085         u8         status[0x8];
4086         u8         reserved_at_8[0x18];
4087
4088         u8         syndrome[0x20];
4089
4090         u8         reserved_at_40[0x20];
4091
4092         u8         enable[0x1];
4093         u8         tag_enable[0x1];
4094         u8         reserved_at_62[0x1e];
4095 };
4096
4097 struct mlx5_ifc_query_cong_status_in_bits {
4098         u8         opcode[0x10];
4099         u8         reserved_at_10[0x10];
4100
4101         u8         reserved_at_20[0x10];
4102         u8         op_mod[0x10];
4103
4104         u8         reserved_at_40[0x18];
4105         u8         priority[0x4];
4106         u8         cong_protocol[0x4];
4107
4108         u8         reserved_at_60[0x20];
4109 };
4110
4111 struct mlx5_ifc_query_cong_statistics_out_bits {
4112         u8         status[0x8];
4113         u8         reserved_at_8[0x18];
4114
4115         u8         syndrome[0x20];
4116
4117         u8         reserved_at_40[0x40];
4118
4119         u8         cur_flows[0x20];
4120
4121         u8         sum_flows[0x20];
4122
4123         u8         cnp_ignored_high[0x20];
4124
4125         u8         cnp_ignored_low[0x20];
4126
4127         u8         cnp_handled_high[0x20];
4128
4129         u8         cnp_handled_low[0x20];
4130
4131         u8         reserved_at_140[0x100];
4132
4133         u8         time_stamp_high[0x20];
4134
4135         u8         time_stamp_low[0x20];
4136
4137         u8         accumulators_period[0x20];
4138
4139         u8         ecn_marked_roce_packets_high[0x20];
4140
4141         u8         ecn_marked_roce_packets_low[0x20];
4142
4143         u8         cnps_sent_high[0x20];
4144
4145         u8         cnps_sent_low[0x20];
4146
4147         u8         reserved_at_320[0x560];
4148 };
4149
4150 struct mlx5_ifc_query_cong_statistics_in_bits {
4151         u8         opcode[0x10];
4152         u8         reserved_at_10[0x10];
4153
4154         u8         reserved_at_20[0x10];
4155         u8         op_mod[0x10];
4156
4157         u8         clear[0x1];
4158         u8         reserved_at_41[0x1f];
4159
4160         u8         reserved_at_60[0x20];
4161 };
4162
4163 struct mlx5_ifc_query_cong_params_out_bits {
4164         u8         status[0x8];
4165         u8         reserved_at_8[0x18];
4166
4167         u8         syndrome[0x20];
4168
4169         u8         reserved_at_40[0x40];
4170
4171         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4172 };
4173
4174 struct mlx5_ifc_query_cong_params_in_bits {
4175         u8         opcode[0x10];
4176         u8         reserved_at_10[0x10];
4177
4178         u8         reserved_at_20[0x10];
4179         u8         op_mod[0x10];
4180
4181         u8         reserved_at_40[0x1c];
4182         u8         cong_protocol[0x4];
4183
4184         u8         reserved_at_60[0x20];
4185 };
4186
4187 struct mlx5_ifc_query_adapter_out_bits {
4188         u8         status[0x8];
4189         u8         reserved_at_8[0x18];
4190
4191         u8         syndrome[0x20];
4192
4193         u8         reserved_at_40[0x40];
4194
4195         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4196 };
4197
4198 struct mlx5_ifc_query_adapter_in_bits {
4199         u8         opcode[0x10];
4200         u8         reserved_at_10[0x10];
4201
4202         u8         reserved_at_20[0x10];
4203         u8         op_mod[0x10];
4204
4205         u8         reserved_at_40[0x40];
4206 };
4207
4208 struct mlx5_ifc_qp_2rst_out_bits {
4209         u8         status[0x8];
4210         u8         reserved_at_8[0x18];
4211
4212         u8         syndrome[0x20];
4213
4214         u8         reserved_at_40[0x40];
4215 };
4216
4217 struct mlx5_ifc_qp_2rst_in_bits {
4218         u8         opcode[0x10];
4219         u8         reserved_at_10[0x10];
4220
4221         u8         reserved_at_20[0x10];
4222         u8         op_mod[0x10];
4223
4224         u8         reserved_at_40[0x8];
4225         u8         qpn[0x18];
4226
4227         u8         reserved_at_60[0x20];
4228 };
4229
4230 struct mlx5_ifc_qp_2err_out_bits {
4231         u8         status[0x8];
4232         u8         reserved_at_8[0x18];
4233
4234         u8         syndrome[0x20];
4235
4236         u8         reserved_at_40[0x40];
4237 };
4238
4239 struct mlx5_ifc_qp_2err_in_bits {
4240         u8         opcode[0x10];
4241         u8         reserved_at_10[0x10];
4242
4243         u8         reserved_at_20[0x10];
4244         u8         op_mod[0x10];
4245
4246         u8         reserved_at_40[0x8];
4247         u8         qpn[0x18];
4248
4249         u8         reserved_at_60[0x20];
4250 };
4251
4252 struct mlx5_ifc_page_fault_resume_out_bits {
4253         u8         status[0x8];
4254         u8         reserved_at_8[0x18];
4255
4256         u8         syndrome[0x20];
4257
4258         u8         reserved_at_40[0x40];
4259 };
4260
4261 struct mlx5_ifc_page_fault_resume_in_bits {
4262         u8         opcode[0x10];
4263         u8         reserved_at_10[0x10];
4264
4265         u8         reserved_at_20[0x10];
4266         u8         op_mod[0x10];
4267
4268         u8         error[0x1];
4269         u8         reserved_at_41[0x4];
4270         u8         rdma[0x1];
4271         u8         read_write[0x1];
4272         u8         req_res[0x1];
4273         u8         qpn[0x18];
4274
4275         u8         reserved_at_60[0x20];
4276 };
4277
4278 struct mlx5_ifc_nop_out_bits {
4279         u8         status[0x8];
4280         u8         reserved_at_8[0x18];
4281
4282         u8         syndrome[0x20];
4283
4284         u8         reserved_at_40[0x40];
4285 };
4286
4287 struct mlx5_ifc_nop_in_bits {
4288         u8         opcode[0x10];
4289         u8         reserved_at_10[0x10];
4290
4291         u8         reserved_at_20[0x10];
4292         u8         op_mod[0x10];
4293
4294         u8         reserved_at_40[0x40];
4295 };
4296
4297 struct mlx5_ifc_modify_vport_state_out_bits {
4298         u8         status[0x8];
4299         u8         reserved_at_8[0x18];
4300
4301         u8         syndrome[0x20];
4302
4303         u8         reserved_at_40[0x40];
4304 };
4305
4306 struct mlx5_ifc_modify_vport_state_in_bits {
4307         u8         opcode[0x10];
4308         u8         reserved_at_10[0x10];
4309
4310         u8         reserved_at_20[0x10];
4311         u8         op_mod[0x10];
4312
4313         u8         other_vport[0x1];
4314         u8         reserved_at_41[0xf];
4315         u8         vport_number[0x10];
4316
4317         u8         reserved_at_60[0x18];
4318         u8         admin_state[0x4];
4319         u8         reserved_at_7c[0x4];
4320 };
4321
4322 struct mlx5_ifc_modify_tis_out_bits {
4323         u8         status[0x8];
4324         u8         reserved_at_8[0x18];
4325
4326         u8         syndrome[0x20];
4327
4328         u8         reserved_at_40[0x40];
4329 };
4330
4331 struct mlx5_ifc_modify_tis_bitmask_bits {
4332         u8         reserved_at_0[0x20];
4333
4334         u8         reserved_at_20[0x1f];
4335         u8         prio[0x1];
4336 };
4337
4338 struct mlx5_ifc_modify_tis_in_bits {
4339         u8         opcode[0x10];
4340         u8         reserved_at_10[0x10];
4341
4342         u8         reserved_at_20[0x10];
4343         u8         op_mod[0x10];
4344
4345         u8         reserved_at_40[0x8];
4346         u8         tisn[0x18];
4347
4348         u8         reserved_at_60[0x20];
4349
4350         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4351
4352         u8         reserved_at_c0[0x40];
4353
4354         struct mlx5_ifc_tisc_bits ctx;
4355 };
4356
4357 struct mlx5_ifc_modify_tir_bitmask_bits {
4358         u8         reserved_at_0[0x20];
4359
4360         u8         reserved_at_20[0x1b];
4361         u8         self_lb_en[0x1];
4362         u8         reserved_at_3c[0x1];
4363         u8         hash[0x1];
4364         u8         reserved_at_3e[0x1];
4365         u8         lro[0x1];
4366 };
4367
4368 struct mlx5_ifc_modify_tir_out_bits {
4369         u8         status[0x8];
4370         u8         reserved_at_8[0x18];
4371
4372         u8         syndrome[0x20];
4373
4374         u8         reserved_at_40[0x40];
4375 };
4376
4377 struct mlx5_ifc_modify_tir_in_bits {
4378         u8         opcode[0x10];
4379         u8         reserved_at_10[0x10];
4380
4381         u8         reserved_at_20[0x10];
4382         u8         op_mod[0x10];
4383
4384         u8         reserved_at_40[0x8];
4385         u8         tirn[0x18];
4386
4387         u8         reserved_at_60[0x20];
4388
4389         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4390
4391         u8         reserved_at_c0[0x40];
4392
4393         struct mlx5_ifc_tirc_bits ctx;
4394 };
4395
4396 struct mlx5_ifc_modify_sq_out_bits {
4397         u8         status[0x8];
4398         u8         reserved_at_8[0x18];
4399
4400         u8         syndrome[0x20];
4401
4402         u8         reserved_at_40[0x40];
4403 };
4404
4405 struct mlx5_ifc_modify_sq_in_bits {
4406         u8         opcode[0x10];
4407         u8         reserved_at_10[0x10];
4408
4409         u8         reserved_at_20[0x10];
4410         u8         op_mod[0x10];
4411
4412         u8         sq_state[0x4];
4413         u8         reserved_at_44[0x4];
4414         u8         sqn[0x18];
4415
4416         u8         reserved_at_60[0x20];
4417
4418         u8         modify_bitmask[0x40];
4419
4420         u8         reserved_at_c0[0x40];
4421
4422         struct mlx5_ifc_sqc_bits ctx;
4423 };
4424
4425 struct mlx5_ifc_modify_rqt_out_bits {
4426         u8         status[0x8];
4427         u8         reserved_at_8[0x18];
4428
4429         u8         syndrome[0x20];
4430
4431         u8         reserved_at_40[0x40];
4432 };
4433
4434 struct mlx5_ifc_rqt_bitmask_bits {
4435         u8         reserved_at_0[0x20];
4436
4437         u8         reserved_at_20[0x1f];
4438         u8         rqn_list[0x1];
4439 };
4440
4441 struct mlx5_ifc_modify_rqt_in_bits {
4442         u8         opcode[0x10];
4443         u8         reserved_at_10[0x10];
4444
4445         u8         reserved_at_20[0x10];
4446         u8         op_mod[0x10];
4447
4448         u8         reserved_at_40[0x8];
4449         u8         rqtn[0x18];
4450
4451         u8         reserved_at_60[0x20];
4452
4453         struct mlx5_ifc_rqt_bitmask_bits bitmask;
4454
4455         u8         reserved_at_c0[0x40];
4456
4457         struct mlx5_ifc_rqtc_bits ctx;
4458 };
4459
4460 struct mlx5_ifc_modify_rq_out_bits {
4461         u8         status[0x8];
4462         u8         reserved_at_8[0x18];
4463
4464         u8         syndrome[0x20];
4465
4466         u8         reserved_at_40[0x40];
4467 };
4468
4469 struct mlx5_ifc_modify_rq_in_bits {
4470         u8         opcode[0x10];
4471         u8         reserved_at_10[0x10];
4472
4473         u8         reserved_at_20[0x10];
4474         u8         op_mod[0x10];
4475
4476         u8         rq_state[0x4];
4477         u8         reserved_at_44[0x4];
4478         u8         rqn[0x18];
4479
4480         u8         reserved_at_60[0x20];
4481
4482         u8         modify_bitmask[0x40];
4483
4484         u8         reserved_at_c0[0x40];
4485
4486         struct mlx5_ifc_rqc_bits ctx;
4487 };
4488
4489 struct mlx5_ifc_modify_rmp_out_bits {
4490         u8         status[0x8];
4491         u8         reserved_at_8[0x18];
4492
4493         u8         syndrome[0x20];
4494
4495         u8         reserved_at_40[0x40];
4496 };
4497
4498 struct mlx5_ifc_rmp_bitmask_bits {
4499         u8         reserved_at_0[0x20];
4500
4501         u8         reserved_at_20[0x1f];
4502         u8         lwm[0x1];
4503 };
4504
4505 struct mlx5_ifc_modify_rmp_in_bits {
4506         u8         opcode[0x10];
4507         u8         reserved_at_10[0x10];
4508
4509         u8         reserved_at_20[0x10];
4510         u8         op_mod[0x10];
4511
4512         u8         rmp_state[0x4];
4513         u8         reserved_at_44[0x4];
4514         u8         rmpn[0x18];
4515
4516         u8         reserved_at_60[0x20];
4517
4518         struct mlx5_ifc_rmp_bitmask_bits bitmask;
4519
4520         u8         reserved_at_c0[0x40];
4521
4522         struct mlx5_ifc_rmpc_bits ctx;
4523 };
4524
4525 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4526         u8         status[0x8];
4527         u8         reserved_at_8[0x18];
4528
4529         u8         syndrome[0x20];
4530
4531         u8         reserved_at_40[0x40];
4532 };
4533
4534 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4535         u8         reserved_at_0[0x19];
4536         u8         mtu[0x1];
4537         u8         change_event[0x1];
4538         u8         promisc[0x1];
4539         u8         permanent_address[0x1];
4540         u8         addresses_list[0x1];
4541         u8         roce_en[0x1];
4542         u8         reserved_at_1f[0x1];
4543 };
4544
4545 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4546         u8         opcode[0x10];
4547         u8         reserved_at_10[0x10];
4548
4549         u8         reserved_at_20[0x10];
4550         u8         op_mod[0x10];
4551
4552         u8         other_vport[0x1];
4553         u8         reserved_at_41[0xf];
4554         u8         vport_number[0x10];
4555
4556         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4557
4558         u8         reserved_at_80[0x780];
4559
4560         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4561 };
4562
4563 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4564         u8         status[0x8];
4565         u8         reserved_at_8[0x18];
4566
4567         u8         syndrome[0x20];
4568
4569         u8         reserved_at_40[0x40];
4570 };
4571
4572 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4573         u8         opcode[0x10];
4574         u8         reserved_at_10[0x10];
4575
4576         u8         reserved_at_20[0x10];
4577         u8         op_mod[0x10];
4578
4579         u8         other_vport[0x1];
4580         u8         reserved_at_41[0xb];
4581         u8         port_num[0x4];
4582         u8         vport_number[0x10];
4583
4584         u8         reserved_at_60[0x20];
4585
4586         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4587 };
4588
4589 struct mlx5_ifc_modify_cq_out_bits {
4590         u8         status[0x8];
4591         u8         reserved_at_8[0x18];
4592
4593         u8         syndrome[0x20];
4594
4595         u8         reserved_at_40[0x40];
4596 };
4597
4598 enum {
4599         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
4600         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
4601 };
4602
4603 struct mlx5_ifc_modify_cq_in_bits {
4604         u8         opcode[0x10];
4605         u8         reserved_at_10[0x10];
4606
4607         u8         reserved_at_20[0x10];
4608         u8         op_mod[0x10];
4609
4610         u8         reserved_at_40[0x8];
4611         u8         cqn[0x18];
4612
4613         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4614
4615         struct mlx5_ifc_cqc_bits cq_context;
4616
4617         u8         reserved_at_280[0x600];
4618
4619         u8         pas[0][0x40];
4620 };
4621
4622 struct mlx5_ifc_modify_cong_status_out_bits {
4623         u8         status[0x8];
4624         u8         reserved_at_8[0x18];
4625
4626         u8         syndrome[0x20];
4627
4628         u8         reserved_at_40[0x40];
4629 };
4630
4631 struct mlx5_ifc_modify_cong_status_in_bits {
4632         u8         opcode[0x10];
4633         u8         reserved_at_10[0x10];
4634
4635         u8         reserved_at_20[0x10];
4636         u8         op_mod[0x10];
4637
4638         u8         reserved_at_40[0x18];
4639         u8         priority[0x4];
4640         u8         cong_protocol[0x4];
4641
4642         u8         enable[0x1];
4643         u8         tag_enable[0x1];
4644         u8         reserved_at_62[0x1e];
4645 };
4646
4647 struct mlx5_ifc_modify_cong_params_out_bits {
4648         u8         status[0x8];
4649         u8         reserved_at_8[0x18];
4650
4651         u8         syndrome[0x20];
4652
4653         u8         reserved_at_40[0x40];
4654 };
4655
4656 struct mlx5_ifc_modify_cong_params_in_bits {
4657         u8         opcode[0x10];
4658         u8         reserved_at_10[0x10];
4659
4660         u8         reserved_at_20[0x10];
4661         u8         op_mod[0x10];
4662
4663         u8         reserved_at_40[0x1c];
4664         u8         cong_protocol[0x4];
4665
4666         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4667
4668         u8         reserved_at_80[0x80];
4669
4670         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4671 };
4672
4673 struct mlx5_ifc_manage_pages_out_bits {
4674         u8         status[0x8];
4675         u8         reserved_at_8[0x18];
4676
4677         u8         syndrome[0x20];
4678
4679         u8         output_num_entries[0x20];
4680
4681         u8         reserved_at_60[0x20];
4682
4683         u8         pas[0][0x40];
4684 };
4685
4686 enum {
4687         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
4688         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
4689         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
4690 };
4691
4692 struct mlx5_ifc_manage_pages_in_bits {
4693         u8         opcode[0x10];
4694         u8         reserved_at_10[0x10];
4695
4696         u8         reserved_at_20[0x10];
4697         u8         op_mod[0x10];
4698
4699         u8         reserved_at_40[0x10];
4700         u8         function_id[0x10];
4701
4702         u8         input_num_entries[0x20];
4703
4704         u8         pas[0][0x40];
4705 };
4706
4707 struct mlx5_ifc_mad_ifc_out_bits {
4708         u8         status[0x8];
4709         u8         reserved_at_8[0x18];
4710
4711         u8         syndrome[0x20];
4712
4713         u8         reserved_at_40[0x40];
4714
4715         u8         response_mad_packet[256][0x8];
4716 };
4717
4718 struct mlx5_ifc_mad_ifc_in_bits {
4719         u8         opcode[0x10];
4720         u8         reserved_at_10[0x10];
4721
4722         u8         reserved_at_20[0x10];
4723         u8         op_mod[0x10];
4724
4725         u8         remote_lid[0x10];
4726         u8         reserved_at_50[0x8];
4727         u8         port[0x8];
4728
4729         u8         reserved_at_60[0x20];
4730
4731         u8         mad[256][0x8];
4732 };
4733
4734 struct mlx5_ifc_init_hca_out_bits {
4735         u8         status[0x8];
4736         u8         reserved_at_8[0x18];
4737
4738         u8         syndrome[0x20];
4739
4740         u8         reserved_at_40[0x40];
4741 };
4742
4743 struct mlx5_ifc_init_hca_in_bits {
4744         u8         opcode[0x10];
4745         u8         reserved_at_10[0x10];
4746
4747         u8         reserved_at_20[0x10];
4748         u8         op_mod[0x10];
4749
4750         u8         reserved_at_40[0x40];
4751 };
4752
4753 struct mlx5_ifc_init2rtr_qp_out_bits {
4754         u8         status[0x8];
4755         u8         reserved_at_8[0x18];
4756
4757         u8         syndrome[0x20];
4758
4759         u8         reserved_at_40[0x40];
4760 };
4761
4762 struct mlx5_ifc_init2rtr_qp_in_bits {
4763         u8         opcode[0x10];
4764         u8         reserved_at_10[0x10];
4765
4766         u8         reserved_at_20[0x10];
4767         u8         op_mod[0x10];
4768
4769         u8         reserved_at_40[0x8];
4770         u8         qpn[0x18];
4771
4772         u8         reserved_at_60[0x20];
4773
4774         u8         opt_param_mask[0x20];
4775
4776         u8         reserved_at_a0[0x20];
4777
4778         struct mlx5_ifc_qpc_bits qpc;
4779
4780         u8         reserved_at_800[0x80];
4781 };
4782
4783 struct mlx5_ifc_init2init_qp_out_bits {
4784         u8         status[0x8];
4785         u8         reserved_at_8[0x18];
4786
4787         u8         syndrome[0x20];
4788
4789         u8         reserved_at_40[0x40];
4790 };
4791
4792 struct mlx5_ifc_init2init_qp_in_bits {
4793         u8         opcode[0x10];
4794         u8         reserved_at_10[0x10];
4795
4796         u8         reserved_at_20[0x10];
4797         u8         op_mod[0x10];
4798
4799         u8         reserved_at_40[0x8];
4800         u8         qpn[0x18];
4801
4802         u8         reserved_at_60[0x20];
4803
4804         u8         opt_param_mask[0x20];
4805
4806         u8         reserved_at_a0[0x20];
4807
4808         struct mlx5_ifc_qpc_bits qpc;
4809
4810         u8         reserved_at_800[0x80];
4811 };
4812
4813 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4814         u8         status[0x8];
4815         u8         reserved_at_8[0x18];
4816
4817         u8         syndrome[0x20];
4818
4819         u8         reserved_at_40[0x40];
4820
4821         u8         packet_headers_log[128][0x8];
4822
4823         u8         packet_syndrome[64][0x8];
4824 };
4825
4826 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4827         u8         opcode[0x10];
4828         u8         reserved_at_10[0x10];
4829
4830         u8         reserved_at_20[0x10];
4831         u8         op_mod[0x10];
4832
4833         u8         reserved_at_40[0x40];
4834 };
4835
4836 struct mlx5_ifc_gen_eqe_in_bits {
4837         u8         opcode[0x10];
4838         u8         reserved_at_10[0x10];
4839
4840         u8         reserved_at_20[0x10];
4841         u8         op_mod[0x10];
4842
4843         u8         reserved_at_40[0x18];
4844         u8         eq_number[0x8];
4845
4846         u8         reserved_at_60[0x20];
4847
4848         u8         eqe[64][0x8];
4849 };
4850
4851 struct mlx5_ifc_gen_eq_out_bits {
4852         u8         status[0x8];
4853         u8         reserved_at_8[0x18];
4854
4855         u8         syndrome[0x20];
4856
4857         u8         reserved_at_40[0x40];
4858 };
4859
4860 struct mlx5_ifc_enable_hca_out_bits {
4861         u8         status[0x8];
4862         u8         reserved_at_8[0x18];
4863
4864         u8         syndrome[0x20];
4865
4866         u8         reserved_at_40[0x20];
4867 };
4868
4869 struct mlx5_ifc_enable_hca_in_bits {
4870         u8         opcode[0x10];
4871         u8         reserved_at_10[0x10];
4872
4873         u8         reserved_at_20[0x10];
4874         u8         op_mod[0x10];
4875
4876         u8         reserved_at_40[0x10];
4877         u8         function_id[0x10];
4878
4879         u8         reserved_at_60[0x20];
4880 };
4881
4882 struct mlx5_ifc_drain_dct_out_bits {
4883         u8         status[0x8];
4884         u8         reserved_at_8[0x18];
4885
4886         u8         syndrome[0x20];
4887
4888         u8         reserved_at_40[0x40];
4889 };
4890
4891 struct mlx5_ifc_drain_dct_in_bits {
4892         u8         opcode[0x10];
4893         u8         reserved_at_10[0x10];
4894
4895         u8         reserved_at_20[0x10];
4896         u8         op_mod[0x10];
4897
4898         u8         reserved_at_40[0x8];
4899         u8         dctn[0x18];
4900
4901         u8         reserved_at_60[0x20];
4902 };
4903
4904 struct mlx5_ifc_disable_hca_out_bits {
4905         u8         status[0x8];
4906         u8         reserved_at_8[0x18];
4907
4908         u8         syndrome[0x20];
4909
4910         u8         reserved_at_40[0x20];
4911 };
4912
4913 struct mlx5_ifc_disable_hca_in_bits {
4914         u8         opcode[0x10];
4915         u8         reserved_at_10[0x10];
4916
4917         u8         reserved_at_20[0x10];
4918         u8         op_mod[0x10];
4919
4920         u8         reserved_at_40[0x10];
4921         u8         function_id[0x10];
4922
4923         u8         reserved_at_60[0x20];
4924 };
4925
4926 struct mlx5_ifc_detach_from_mcg_out_bits {
4927         u8         status[0x8];
4928         u8         reserved_at_8[0x18];
4929
4930         u8         syndrome[0x20];
4931
4932         u8         reserved_at_40[0x40];
4933 };
4934
4935 struct mlx5_ifc_detach_from_mcg_in_bits {
4936         u8         opcode[0x10];
4937         u8         reserved_at_10[0x10];
4938
4939         u8         reserved_at_20[0x10];
4940         u8         op_mod[0x10];
4941
4942         u8         reserved_at_40[0x8];
4943         u8         qpn[0x18];
4944
4945         u8         reserved_at_60[0x20];
4946
4947         u8         multicast_gid[16][0x8];
4948 };
4949
4950 struct mlx5_ifc_destroy_xrc_srq_out_bits {
4951         u8         status[0x8];
4952         u8         reserved_at_8[0x18];
4953
4954         u8         syndrome[0x20];
4955
4956         u8         reserved_at_40[0x40];
4957 };
4958
4959 struct mlx5_ifc_destroy_xrc_srq_in_bits {
4960         u8         opcode[0x10];
4961         u8         reserved_at_10[0x10];
4962
4963         u8         reserved_at_20[0x10];
4964         u8         op_mod[0x10];
4965
4966         u8         reserved_at_40[0x8];
4967         u8         xrc_srqn[0x18];
4968
4969         u8         reserved_at_60[0x20];
4970 };
4971
4972 struct mlx5_ifc_destroy_tis_out_bits {
4973         u8         status[0x8];
4974         u8         reserved_at_8[0x18];
4975
4976         u8         syndrome[0x20];
4977
4978         u8         reserved_at_40[0x40];
4979 };
4980
4981 struct mlx5_ifc_destroy_tis_in_bits {
4982         u8         opcode[0x10];
4983         u8         reserved_at_10[0x10];
4984
4985         u8         reserved_at_20[0x10];
4986         u8         op_mod[0x10];
4987
4988         u8         reserved_at_40[0x8];
4989         u8         tisn[0x18];
4990
4991         u8         reserved_at_60[0x20];
4992 };
4993
4994 struct mlx5_ifc_destroy_tir_out_bits {
4995         u8         status[0x8];
4996         u8         reserved_at_8[0x18];
4997
4998         u8         syndrome[0x20];
4999
5000         u8         reserved_at_40[0x40];
5001 };
5002
5003 struct mlx5_ifc_destroy_tir_in_bits {
5004         u8         opcode[0x10];
5005         u8         reserved_at_10[0x10];
5006
5007         u8         reserved_at_20[0x10];
5008         u8         op_mod[0x10];
5009
5010         u8         reserved_at_40[0x8];
5011         u8         tirn[0x18];
5012
5013         u8         reserved_at_60[0x20];
5014 };
5015
5016 struct mlx5_ifc_destroy_srq_out_bits {
5017         u8         status[0x8];
5018         u8         reserved_at_8[0x18];
5019
5020         u8         syndrome[0x20];
5021
5022         u8         reserved_at_40[0x40];
5023 };
5024
5025 struct mlx5_ifc_destroy_srq_in_bits {
5026         u8         opcode[0x10];
5027         u8         reserved_at_10[0x10];
5028
5029         u8         reserved_at_20[0x10];
5030         u8         op_mod[0x10];
5031
5032         u8         reserved_at_40[0x8];
5033         u8         srqn[0x18];
5034
5035         u8         reserved_at_60[0x20];
5036 };
5037
5038 struct mlx5_ifc_destroy_sq_out_bits {
5039         u8         status[0x8];
5040         u8         reserved_at_8[0x18];
5041
5042         u8         syndrome[0x20];
5043
5044         u8         reserved_at_40[0x40];
5045 };
5046
5047 struct mlx5_ifc_destroy_sq_in_bits {
5048         u8         opcode[0x10];
5049         u8         reserved_at_10[0x10];
5050
5051         u8         reserved_at_20[0x10];
5052         u8         op_mod[0x10];
5053
5054         u8         reserved_at_40[0x8];
5055         u8         sqn[0x18];
5056
5057         u8         reserved_at_60[0x20];
5058 };
5059
5060 struct mlx5_ifc_destroy_rqt_out_bits {
5061         u8         status[0x8];
5062         u8         reserved_at_8[0x18];
5063
5064         u8         syndrome[0x20];
5065
5066         u8         reserved_at_40[0x40];
5067 };
5068
5069 struct mlx5_ifc_destroy_rqt_in_bits {
5070         u8         opcode[0x10];
5071         u8         reserved_at_10[0x10];
5072
5073         u8         reserved_at_20[0x10];
5074         u8         op_mod[0x10];
5075
5076         u8         reserved_at_40[0x8];
5077         u8         rqtn[0x18];
5078
5079         u8         reserved_at_60[0x20];
5080 };
5081
5082 struct mlx5_ifc_destroy_rq_out_bits {
5083         u8         status[0x8];
5084         u8         reserved_at_8[0x18];
5085
5086         u8         syndrome[0x20];
5087
5088         u8         reserved_at_40[0x40];
5089 };
5090
5091 struct mlx5_ifc_destroy_rq_in_bits {
5092         u8         opcode[0x10];
5093         u8         reserved_at_10[0x10];
5094
5095         u8         reserved_at_20[0x10];
5096         u8         op_mod[0x10];
5097
5098         u8         reserved_at_40[0x8];
5099         u8         rqn[0x18];
5100
5101         u8         reserved_at_60[0x20];
5102 };
5103
5104 struct mlx5_ifc_destroy_rmp_out_bits {
5105         u8         status[0x8];
5106         u8         reserved_at_8[0x18];
5107
5108         u8         syndrome[0x20];
5109
5110         u8         reserved_at_40[0x40];
5111 };
5112
5113 struct mlx5_ifc_destroy_rmp_in_bits {
5114         u8         opcode[0x10];
5115         u8         reserved_at_10[0x10];
5116
5117         u8         reserved_at_20[0x10];
5118         u8         op_mod[0x10];
5119
5120         u8         reserved_at_40[0x8];
5121         u8         rmpn[0x18];
5122
5123         u8         reserved_at_60[0x20];
5124 };
5125
5126 struct mlx5_ifc_destroy_qp_out_bits {
5127         u8         status[0x8];
5128         u8         reserved_at_8[0x18];
5129
5130         u8         syndrome[0x20];
5131
5132         u8         reserved_at_40[0x40];
5133 };
5134
5135 struct mlx5_ifc_destroy_qp_in_bits {
5136         u8         opcode[0x10];
5137         u8         reserved_at_10[0x10];
5138
5139         u8         reserved_at_20[0x10];
5140         u8         op_mod[0x10];
5141
5142         u8         reserved_at_40[0x8];
5143         u8         qpn[0x18];
5144
5145         u8         reserved_at_60[0x20];
5146 };
5147
5148 struct mlx5_ifc_destroy_psv_out_bits {
5149         u8         status[0x8];
5150         u8         reserved_at_8[0x18];
5151
5152         u8         syndrome[0x20];
5153
5154         u8         reserved_at_40[0x40];
5155 };
5156
5157 struct mlx5_ifc_destroy_psv_in_bits {
5158         u8         opcode[0x10];
5159         u8         reserved_at_10[0x10];
5160
5161         u8         reserved_at_20[0x10];
5162         u8         op_mod[0x10];
5163
5164         u8         reserved_at_40[0x8];
5165         u8         psvn[0x18];
5166
5167         u8         reserved_at_60[0x20];
5168 };
5169
5170 struct mlx5_ifc_destroy_mkey_out_bits {
5171         u8         status[0x8];
5172         u8         reserved_at_8[0x18];
5173
5174         u8         syndrome[0x20];
5175
5176         u8         reserved_at_40[0x40];
5177 };
5178
5179 struct mlx5_ifc_destroy_mkey_in_bits {
5180         u8         opcode[0x10];
5181         u8         reserved_at_10[0x10];
5182
5183         u8         reserved_at_20[0x10];
5184         u8         op_mod[0x10];
5185
5186         u8         reserved_at_40[0x8];
5187         u8         mkey_index[0x18];
5188
5189         u8         reserved_at_60[0x20];
5190 };
5191
5192 struct mlx5_ifc_destroy_flow_table_out_bits {
5193         u8         status[0x8];
5194         u8         reserved_at_8[0x18];
5195
5196         u8         syndrome[0x20];
5197
5198         u8         reserved_at_40[0x40];
5199 };
5200
5201 struct mlx5_ifc_destroy_flow_table_in_bits {
5202         u8         opcode[0x10];
5203         u8         reserved_at_10[0x10];
5204
5205         u8         reserved_at_20[0x10];
5206         u8         op_mod[0x10];
5207
5208         u8         other_vport[0x1];
5209         u8         reserved_at_41[0xf];
5210         u8         vport_number[0x10];
5211
5212         u8         reserved_at_60[0x20];
5213
5214         u8         table_type[0x8];
5215         u8         reserved_at_88[0x18];
5216
5217         u8         reserved_at_a0[0x8];
5218         u8         table_id[0x18];
5219
5220         u8         reserved_at_c0[0x140];
5221 };
5222
5223 struct mlx5_ifc_destroy_flow_group_out_bits {
5224         u8         status[0x8];
5225         u8         reserved_at_8[0x18];
5226
5227         u8         syndrome[0x20];
5228
5229         u8         reserved_at_40[0x40];
5230 };
5231
5232 struct mlx5_ifc_destroy_flow_group_in_bits {
5233         u8         opcode[0x10];
5234         u8         reserved_at_10[0x10];
5235
5236         u8         reserved_at_20[0x10];
5237         u8         op_mod[0x10];
5238
5239         u8         other_vport[0x1];
5240         u8         reserved_at_41[0xf];
5241         u8         vport_number[0x10];
5242
5243         u8         reserved_at_60[0x20];
5244
5245         u8         table_type[0x8];
5246         u8         reserved_at_88[0x18];
5247
5248         u8         reserved_at_a0[0x8];
5249         u8         table_id[0x18];
5250
5251         u8         group_id[0x20];
5252
5253         u8         reserved_at_e0[0x120];
5254 };
5255
5256 struct mlx5_ifc_destroy_eq_out_bits {
5257         u8         status[0x8];
5258         u8         reserved_at_8[0x18];
5259
5260         u8         syndrome[0x20];
5261
5262         u8         reserved_at_40[0x40];
5263 };
5264
5265 struct mlx5_ifc_destroy_eq_in_bits {
5266         u8         opcode[0x10];
5267         u8         reserved_at_10[0x10];
5268
5269         u8         reserved_at_20[0x10];
5270         u8         op_mod[0x10];
5271
5272         u8         reserved_at_40[0x18];
5273         u8         eq_number[0x8];
5274
5275         u8         reserved_at_60[0x20];
5276 };
5277
5278 struct mlx5_ifc_destroy_dct_out_bits {
5279         u8         status[0x8];
5280         u8         reserved_at_8[0x18];
5281
5282         u8         syndrome[0x20];
5283
5284         u8         reserved_at_40[0x40];
5285 };
5286
5287 struct mlx5_ifc_destroy_dct_in_bits {
5288         u8         opcode[0x10];
5289         u8         reserved_at_10[0x10];
5290
5291         u8         reserved_at_20[0x10];
5292         u8         op_mod[0x10];
5293
5294         u8         reserved_at_40[0x8];
5295         u8         dctn[0x18];
5296
5297         u8         reserved_at_60[0x20];
5298 };
5299
5300 struct mlx5_ifc_destroy_cq_out_bits {
5301         u8         status[0x8];
5302         u8         reserved_at_8[0x18];
5303
5304         u8         syndrome[0x20];
5305
5306         u8         reserved_at_40[0x40];
5307 };
5308
5309 struct mlx5_ifc_destroy_cq_in_bits {
5310         u8         opcode[0x10];
5311         u8         reserved_at_10[0x10];
5312
5313         u8         reserved_at_20[0x10];
5314         u8         op_mod[0x10];
5315
5316         u8         reserved_at_40[0x8];
5317         u8         cqn[0x18];
5318
5319         u8         reserved_at_60[0x20];
5320 };
5321
5322 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5323         u8         status[0x8];
5324         u8         reserved_at_8[0x18];
5325
5326         u8         syndrome[0x20];
5327
5328         u8         reserved_at_40[0x40];
5329 };
5330
5331 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5332         u8         opcode[0x10];
5333         u8         reserved_at_10[0x10];
5334
5335         u8         reserved_at_20[0x10];
5336         u8         op_mod[0x10];
5337
5338         u8         reserved_at_40[0x20];
5339
5340         u8         reserved_at_60[0x10];
5341         u8         vxlan_udp_port[0x10];
5342 };
5343
5344 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5345         u8         status[0x8];
5346         u8         reserved_at_8[0x18];
5347
5348         u8         syndrome[0x20];
5349
5350         u8         reserved_at_40[0x40];
5351 };
5352
5353 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5354         u8         opcode[0x10];
5355         u8         reserved_at_10[0x10];
5356
5357         u8         reserved_at_20[0x10];
5358         u8         op_mod[0x10];
5359
5360         u8         reserved_at_40[0x60];
5361
5362         u8         reserved_at_a0[0x8];
5363         u8         table_index[0x18];
5364
5365         u8         reserved_at_c0[0x140];
5366 };
5367
5368 struct mlx5_ifc_delete_fte_out_bits {
5369         u8         status[0x8];
5370         u8         reserved_at_8[0x18];
5371
5372         u8         syndrome[0x20];
5373
5374         u8         reserved_at_40[0x40];
5375 };
5376
5377 struct mlx5_ifc_delete_fte_in_bits {
5378         u8         opcode[0x10];
5379         u8         reserved_at_10[0x10];
5380
5381         u8         reserved_at_20[0x10];
5382         u8         op_mod[0x10];
5383
5384         u8         other_vport[0x1];
5385         u8         reserved_at_41[0xf];
5386         u8         vport_number[0x10];
5387
5388         u8         reserved_at_60[0x20];
5389
5390         u8         table_type[0x8];
5391         u8         reserved_at_88[0x18];
5392
5393         u8         reserved_at_a0[0x8];
5394         u8         table_id[0x18];
5395
5396         u8         reserved_at_c0[0x40];
5397
5398         u8         flow_index[0x20];
5399
5400         u8         reserved_at_120[0xe0];
5401 };
5402
5403 struct mlx5_ifc_dealloc_xrcd_out_bits {
5404         u8         status[0x8];
5405         u8         reserved_at_8[0x18];
5406
5407         u8         syndrome[0x20];
5408
5409         u8         reserved_at_40[0x40];
5410 };
5411
5412 struct mlx5_ifc_dealloc_xrcd_in_bits {
5413         u8         opcode[0x10];
5414         u8         reserved_at_10[0x10];
5415
5416         u8         reserved_at_20[0x10];
5417         u8         op_mod[0x10];
5418
5419         u8         reserved_at_40[0x8];
5420         u8         xrcd[0x18];
5421
5422         u8         reserved_at_60[0x20];
5423 };
5424
5425 struct mlx5_ifc_dealloc_uar_out_bits {
5426         u8         status[0x8];
5427         u8         reserved_at_8[0x18];
5428
5429         u8         syndrome[0x20];
5430
5431         u8         reserved_at_40[0x40];
5432 };
5433
5434 struct mlx5_ifc_dealloc_uar_in_bits {
5435         u8         opcode[0x10];
5436         u8         reserved_at_10[0x10];
5437
5438         u8         reserved_at_20[0x10];
5439         u8         op_mod[0x10];
5440
5441         u8         reserved_at_40[0x8];
5442         u8         uar[0x18];
5443
5444         u8         reserved_at_60[0x20];
5445 };
5446
5447 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5448         u8         status[0x8];
5449         u8         reserved_at_8[0x18];
5450
5451         u8         syndrome[0x20];
5452
5453         u8         reserved_at_40[0x40];
5454 };
5455
5456 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5457         u8         opcode[0x10];
5458         u8         reserved_at_10[0x10];
5459
5460         u8         reserved_at_20[0x10];
5461         u8         op_mod[0x10];
5462
5463         u8         reserved_at_40[0x8];
5464         u8         transport_domain[0x18];
5465
5466         u8         reserved_at_60[0x20];
5467 };
5468
5469 struct mlx5_ifc_dealloc_q_counter_out_bits {
5470         u8         status[0x8];
5471         u8         reserved_at_8[0x18];
5472
5473         u8         syndrome[0x20];
5474
5475         u8         reserved_at_40[0x40];
5476 };
5477
5478 struct mlx5_ifc_dealloc_q_counter_in_bits {
5479         u8         opcode[0x10];
5480         u8         reserved_at_10[0x10];
5481
5482         u8         reserved_at_20[0x10];
5483         u8         op_mod[0x10];
5484
5485         u8         reserved_at_40[0x18];
5486         u8         counter_set_id[0x8];
5487
5488         u8         reserved_at_60[0x20];
5489 };
5490
5491 struct mlx5_ifc_dealloc_pd_out_bits {
5492         u8         status[0x8];
5493         u8         reserved_at_8[0x18];
5494
5495         u8         syndrome[0x20];
5496
5497         u8         reserved_at_40[0x40];
5498 };
5499
5500 struct mlx5_ifc_dealloc_pd_in_bits {
5501         u8         opcode[0x10];
5502         u8         reserved_at_10[0x10];
5503
5504         u8         reserved_at_20[0x10];
5505         u8         op_mod[0x10];
5506
5507         u8         reserved_at_40[0x8];
5508         u8         pd[0x18];
5509
5510         u8         reserved_at_60[0x20];
5511 };
5512
5513 struct mlx5_ifc_create_xrc_srq_out_bits {
5514         u8         status[0x8];
5515         u8         reserved_at_8[0x18];
5516
5517         u8         syndrome[0x20];
5518
5519         u8         reserved_at_40[0x8];
5520         u8         xrc_srqn[0x18];
5521
5522         u8         reserved_at_60[0x20];
5523 };
5524
5525 struct mlx5_ifc_create_xrc_srq_in_bits {
5526         u8         opcode[0x10];
5527         u8         reserved_at_10[0x10];
5528
5529         u8         reserved_at_20[0x10];
5530         u8         op_mod[0x10];
5531
5532         u8         reserved_at_40[0x40];
5533
5534         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5535
5536         u8         reserved_at_280[0x600];
5537
5538         u8         pas[0][0x40];
5539 };
5540
5541 struct mlx5_ifc_create_tis_out_bits {
5542         u8         status[0x8];
5543         u8         reserved_at_8[0x18];
5544
5545         u8         syndrome[0x20];
5546
5547         u8         reserved_at_40[0x8];
5548         u8         tisn[0x18];
5549
5550         u8         reserved_at_60[0x20];
5551 };
5552
5553 struct mlx5_ifc_create_tis_in_bits {
5554         u8         opcode[0x10];
5555         u8         reserved_at_10[0x10];
5556
5557         u8         reserved_at_20[0x10];
5558         u8         op_mod[0x10];
5559
5560         u8         reserved_at_40[0xc0];
5561
5562         struct mlx5_ifc_tisc_bits ctx;
5563 };
5564
5565 struct mlx5_ifc_create_tir_out_bits {
5566         u8         status[0x8];
5567         u8         reserved_at_8[0x18];
5568
5569         u8         syndrome[0x20];
5570
5571         u8         reserved_at_40[0x8];
5572         u8         tirn[0x18];
5573
5574         u8         reserved_at_60[0x20];
5575 };
5576
5577 struct mlx5_ifc_create_tir_in_bits {
5578         u8         opcode[0x10];
5579         u8         reserved_at_10[0x10];
5580
5581         u8         reserved_at_20[0x10];
5582         u8         op_mod[0x10];
5583
5584         u8         reserved_at_40[0xc0];
5585
5586         struct mlx5_ifc_tirc_bits ctx;
5587 };
5588
5589 struct mlx5_ifc_create_srq_out_bits {
5590         u8         status[0x8];
5591         u8         reserved_at_8[0x18];
5592
5593         u8         syndrome[0x20];
5594
5595         u8         reserved_at_40[0x8];
5596         u8         srqn[0x18];
5597
5598         u8         reserved_at_60[0x20];
5599 };
5600
5601 struct mlx5_ifc_create_srq_in_bits {
5602         u8         opcode[0x10];
5603         u8         reserved_at_10[0x10];
5604
5605         u8         reserved_at_20[0x10];
5606         u8         op_mod[0x10];
5607
5608         u8         reserved_at_40[0x40];
5609
5610         struct mlx5_ifc_srqc_bits srq_context_entry;
5611
5612         u8         reserved_at_280[0x600];
5613
5614         u8         pas[0][0x40];
5615 };
5616
5617 struct mlx5_ifc_create_sq_out_bits {
5618         u8         status[0x8];
5619         u8         reserved_at_8[0x18];
5620
5621         u8         syndrome[0x20];
5622
5623         u8         reserved_at_40[0x8];
5624         u8         sqn[0x18];
5625
5626         u8         reserved_at_60[0x20];
5627 };
5628
5629 struct mlx5_ifc_create_sq_in_bits {
5630         u8         opcode[0x10];
5631         u8         reserved_at_10[0x10];
5632
5633         u8         reserved_at_20[0x10];
5634         u8         op_mod[0x10];
5635
5636         u8         reserved_at_40[0xc0];
5637
5638         struct mlx5_ifc_sqc_bits ctx;
5639 };
5640
5641 struct mlx5_ifc_create_rqt_out_bits {
5642         u8         status[0x8];
5643         u8         reserved_at_8[0x18];
5644
5645         u8         syndrome[0x20];
5646
5647         u8         reserved_at_40[0x8];
5648         u8         rqtn[0x18];
5649
5650         u8         reserved_at_60[0x20];
5651 };
5652
5653 struct mlx5_ifc_create_rqt_in_bits {
5654         u8         opcode[0x10];
5655         u8         reserved_at_10[0x10];
5656
5657         u8         reserved_at_20[0x10];
5658         u8         op_mod[0x10];
5659
5660         u8         reserved_at_40[0xc0];
5661
5662         struct mlx5_ifc_rqtc_bits rqt_context;
5663 };
5664
5665 struct mlx5_ifc_create_rq_out_bits {
5666         u8         status[0x8];
5667         u8         reserved_at_8[0x18];
5668
5669         u8         syndrome[0x20];
5670
5671         u8         reserved_at_40[0x8];
5672         u8         rqn[0x18];
5673
5674         u8         reserved_at_60[0x20];
5675 };
5676
5677 struct mlx5_ifc_create_rq_in_bits {
5678         u8         opcode[0x10];
5679         u8         reserved_at_10[0x10];
5680
5681         u8         reserved_at_20[0x10];
5682         u8         op_mod[0x10];
5683
5684         u8         reserved_at_40[0xc0];
5685
5686         struct mlx5_ifc_rqc_bits ctx;
5687 };
5688
5689 struct mlx5_ifc_create_rmp_out_bits {
5690         u8         status[0x8];
5691         u8         reserved_at_8[0x18];
5692
5693         u8         syndrome[0x20];
5694
5695         u8         reserved_at_40[0x8];
5696         u8         rmpn[0x18];
5697
5698         u8         reserved_at_60[0x20];
5699 };
5700
5701 struct mlx5_ifc_create_rmp_in_bits {
5702         u8         opcode[0x10];
5703         u8         reserved_at_10[0x10];
5704
5705         u8         reserved_at_20[0x10];
5706         u8         op_mod[0x10];
5707
5708         u8         reserved_at_40[0xc0];
5709
5710         struct mlx5_ifc_rmpc_bits ctx;
5711 };
5712
5713 struct mlx5_ifc_create_qp_out_bits {
5714         u8         status[0x8];
5715         u8         reserved_at_8[0x18];
5716
5717         u8         syndrome[0x20];
5718
5719         u8         reserved_at_40[0x8];
5720         u8         qpn[0x18];
5721
5722         u8         reserved_at_60[0x20];
5723 };
5724
5725 struct mlx5_ifc_create_qp_in_bits {
5726         u8         opcode[0x10];
5727         u8         reserved_at_10[0x10];
5728
5729         u8         reserved_at_20[0x10];
5730         u8         op_mod[0x10];
5731
5732         u8         reserved_at_40[0x40];
5733
5734         u8         opt_param_mask[0x20];
5735
5736         u8         reserved_at_a0[0x20];
5737
5738         struct mlx5_ifc_qpc_bits qpc;
5739
5740         u8         reserved_at_800[0x80];
5741
5742         u8         pas[0][0x40];
5743 };
5744
5745 struct mlx5_ifc_create_psv_out_bits {
5746         u8         status[0x8];
5747         u8         reserved_at_8[0x18];
5748
5749         u8         syndrome[0x20];
5750
5751         u8         reserved_at_40[0x40];
5752
5753         u8         reserved_at_80[0x8];
5754         u8         psv0_index[0x18];
5755
5756         u8         reserved_at_a0[0x8];
5757         u8         psv1_index[0x18];
5758
5759         u8         reserved_at_c0[0x8];
5760         u8         psv2_index[0x18];
5761
5762         u8         reserved_at_e0[0x8];
5763         u8         psv3_index[0x18];
5764 };
5765
5766 struct mlx5_ifc_create_psv_in_bits {
5767         u8         opcode[0x10];
5768         u8         reserved_at_10[0x10];
5769
5770         u8         reserved_at_20[0x10];
5771         u8         op_mod[0x10];
5772
5773         u8         num_psv[0x4];
5774         u8         reserved_at_44[0x4];
5775         u8         pd[0x18];
5776
5777         u8         reserved_at_60[0x20];
5778 };
5779
5780 struct mlx5_ifc_create_mkey_out_bits {
5781         u8         status[0x8];
5782         u8         reserved_at_8[0x18];
5783
5784         u8         syndrome[0x20];
5785
5786         u8         reserved_at_40[0x8];
5787         u8         mkey_index[0x18];
5788
5789         u8         reserved_at_60[0x20];
5790 };
5791
5792 struct mlx5_ifc_create_mkey_in_bits {
5793         u8         opcode[0x10];
5794         u8         reserved_at_10[0x10];
5795
5796         u8         reserved_at_20[0x10];
5797         u8         op_mod[0x10];
5798
5799         u8         reserved_at_40[0x20];
5800
5801         u8         pg_access[0x1];
5802         u8         reserved_at_61[0x1f];
5803
5804         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5805
5806         u8         reserved_at_280[0x80];
5807
5808         u8         translations_octword_actual_size[0x20];
5809
5810         u8         reserved_at_320[0x560];
5811
5812         u8         klm_pas_mtt[0][0x20];
5813 };
5814
5815 struct mlx5_ifc_create_flow_table_out_bits {
5816         u8         status[0x8];
5817         u8         reserved_at_8[0x18];
5818
5819         u8         syndrome[0x20];
5820
5821         u8         reserved_at_40[0x8];
5822         u8         table_id[0x18];
5823
5824         u8         reserved_at_60[0x20];
5825 };
5826
5827 struct mlx5_ifc_create_flow_table_in_bits {
5828         u8         opcode[0x10];
5829         u8         reserved_at_10[0x10];
5830
5831         u8         reserved_at_20[0x10];
5832         u8         op_mod[0x10];
5833
5834         u8         other_vport[0x1];
5835         u8         reserved_at_41[0xf];
5836         u8         vport_number[0x10];
5837
5838         u8         reserved_at_60[0x20];
5839
5840         u8         table_type[0x8];
5841         u8         reserved_at_88[0x18];
5842
5843         u8         reserved_at_a0[0x20];
5844
5845         u8         reserved_at_c0[0x4];
5846         u8         table_miss_mode[0x4];
5847         u8         level[0x8];
5848         u8         reserved_at_d0[0x8];
5849         u8         log_size[0x8];
5850
5851         u8         reserved_at_e0[0x8];
5852         u8         table_miss_id[0x18];
5853
5854         u8         reserved_at_100[0x100];
5855 };
5856
5857 struct mlx5_ifc_create_flow_group_out_bits {
5858         u8         status[0x8];
5859         u8         reserved_at_8[0x18];
5860
5861         u8         syndrome[0x20];
5862
5863         u8         reserved_at_40[0x8];
5864         u8         group_id[0x18];
5865
5866         u8         reserved_at_60[0x20];
5867 };
5868
5869 enum {
5870         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5871         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5872         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5873 };
5874
5875 struct mlx5_ifc_create_flow_group_in_bits {
5876         u8         opcode[0x10];
5877         u8         reserved_at_10[0x10];
5878
5879         u8         reserved_at_20[0x10];
5880         u8         op_mod[0x10];
5881
5882         u8         other_vport[0x1];
5883         u8         reserved_at_41[0xf];
5884         u8         vport_number[0x10];
5885
5886         u8         reserved_at_60[0x20];
5887
5888         u8         table_type[0x8];
5889         u8         reserved_at_88[0x18];
5890
5891         u8         reserved_at_a0[0x8];
5892         u8         table_id[0x18];
5893
5894         u8         reserved_at_c0[0x20];
5895
5896         u8         start_flow_index[0x20];
5897
5898         u8         reserved_at_100[0x20];
5899
5900         u8         end_flow_index[0x20];
5901
5902         u8         reserved_at_140[0xa0];
5903
5904         u8         reserved_at_1e0[0x18];
5905         u8         match_criteria_enable[0x8];
5906
5907         struct mlx5_ifc_fte_match_param_bits match_criteria;
5908
5909         u8         reserved_at_1200[0xe00];
5910 };
5911
5912 struct mlx5_ifc_create_eq_out_bits {
5913         u8         status[0x8];
5914         u8         reserved_at_8[0x18];
5915
5916         u8         syndrome[0x20];
5917
5918         u8         reserved_at_40[0x18];
5919         u8         eq_number[0x8];
5920
5921         u8         reserved_at_60[0x20];
5922 };
5923
5924 struct mlx5_ifc_create_eq_in_bits {
5925         u8         opcode[0x10];
5926         u8         reserved_at_10[0x10];
5927
5928         u8         reserved_at_20[0x10];
5929         u8         op_mod[0x10];
5930
5931         u8         reserved_at_40[0x40];
5932
5933         struct mlx5_ifc_eqc_bits eq_context_entry;
5934
5935         u8         reserved_at_280[0x40];
5936
5937         u8         event_bitmask[0x40];
5938
5939         u8         reserved_at_300[0x580];
5940
5941         u8         pas[0][0x40];
5942 };
5943
5944 struct mlx5_ifc_create_dct_out_bits {
5945         u8         status[0x8];
5946         u8         reserved_at_8[0x18];
5947
5948         u8         syndrome[0x20];
5949
5950         u8         reserved_at_40[0x8];
5951         u8         dctn[0x18];
5952
5953         u8         reserved_at_60[0x20];
5954 };
5955
5956 struct mlx5_ifc_create_dct_in_bits {
5957         u8         opcode[0x10];
5958         u8         reserved_at_10[0x10];
5959
5960         u8         reserved_at_20[0x10];
5961         u8         op_mod[0x10];
5962
5963         u8         reserved_at_40[0x40];
5964
5965         struct mlx5_ifc_dctc_bits dct_context_entry;
5966
5967         u8         reserved_at_280[0x180];
5968 };
5969
5970 struct mlx5_ifc_create_cq_out_bits {
5971         u8         status[0x8];
5972         u8         reserved_at_8[0x18];
5973
5974         u8         syndrome[0x20];
5975
5976         u8         reserved_at_40[0x8];
5977         u8         cqn[0x18];
5978
5979         u8         reserved_at_60[0x20];
5980 };
5981
5982 struct mlx5_ifc_create_cq_in_bits {
5983         u8         opcode[0x10];
5984         u8         reserved_at_10[0x10];
5985
5986         u8         reserved_at_20[0x10];
5987         u8         op_mod[0x10];
5988
5989         u8         reserved_at_40[0x40];
5990
5991         struct mlx5_ifc_cqc_bits cq_context;
5992
5993         u8         reserved_at_280[0x600];
5994
5995         u8         pas[0][0x40];
5996 };
5997
5998 struct mlx5_ifc_config_int_moderation_out_bits {
5999         u8         status[0x8];
6000         u8         reserved_at_8[0x18];
6001
6002         u8         syndrome[0x20];
6003
6004         u8         reserved_at_40[0x4];
6005         u8         min_delay[0xc];
6006         u8         int_vector[0x10];
6007
6008         u8         reserved_at_60[0x20];
6009 };
6010
6011 enum {
6012         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6013         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6014 };
6015
6016 struct mlx5_ifc_config_int_moderation_in_bits {
6017         u8         opcode[0x10];
6018         u8         reserved_at_10[0x10];
6019
6020         u8         reserved_at_20[0x10];
6021         u8         op_mod[0x10];
6022
6023         u8         reserved_at_40[0x4];
6024         u8         min_delay[0xc];
6025         u8         int_vector[0x10];
6026
6027         u8         reserved_at_60[0x20];
6028 };
6029
6030 struct mlx5_ifc_attach_to_mcg_out_bits {
6031         u8         status[0x8];
6032         u8         reserved_at_8[0x18];
6033
6034         u8         syndrome[0x20];
6035
6036         u8         reserved_at_40[0x40];
6037 };
6038
6039 struct mlx5_ifc_attach_to_mcg_in_bits {
6040         u8         opcode[0x10];
6041         u8         reserved_at_10[0x10];
6042
6043         u8         reserved_at_20[0x10];
6044         u8         op_mod[0x10];
6045
6046         u8         reserved_at_40[0x8];
6047         u8         qpn[0x18];
6048
6049         u8         reserved_at_60[0x20];
6050
6051         u8         multicast_gid[16][0x8];
6052 };
6053
6054 struct mlx5_ifc_arm_xrc_srq_out_bits {
6055         u8         status[0x8];
6056         u8         reserved_at_8[0x18];
6057
6058         u8         syndrome[0x20];
6059
6060         u8         reserved_at_40[0x40];
6061 };
6062
6063 enum {
6064         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
6065 };
6066
6067 struct mlx5_ifc_arm_xrc_srq_in_bits {
6068         u8         opcode[0x10];
6069         u8         reserved_at_10[0x10];
6070
6071         u8         reserved_at_20[0x10];
6072         u8         op_mod[0x10];
6073
6074         u8         reserved_at_40[0x8];
6075         u8         xrc_srqn[0x18];
6076
6077         u8         reserved_at_60[0x10];
6078         u8         lwm[0x10];
6079 };
6080
6081 struct mlx5_ifc_arm_rq_out_bits {
6082         u8         status[0x8];
6083         u8         reserved_at_8[0x18];
6084
6085         u8         syndrome[0x20];
6086
6087         u8         reserved_at_40[0x40];
6088 };
6089
6090 enum {
6091         MLX5_ARM_RQ_IN_OP_MOD_SRQ_  = 0x1,
6092 };
6093
6094 struct mlx5_ifc_arm_rq_in_bits {
6095         u8         opcode[0x10];
6096         u8         reserved_at_10[0x10];
6097
6098         u8         reserved_at_20[0x10];
6099         u8         op_mod[0x10];
6100
6101         u8         reserved_at_40[0x8];
6102         u8         srq_number[0x18];
6103
6104         u8         reserved_at_60[0x10];
6105         u8         lwm[0x10];
6106 };
6107
6108 struct mlx5_ifc_arm_dct_out_bits {
6109         u8         status[0x8];
6110         u8         reserved_at_8[0x18];
6111
6112         u8         syndrome[0x20];
6113
6114         u8         reserved_at_40[0x40];
6115 };
6116
6117 struct mlx5_ifc_arm_dct_in_bits {
6118         u8         opcode[0x10];
6119         u8         reserved_at_10[0x10];
6120
6121         u8         reserved_at_20[0x10];
6122         u8         op_mod[0x10];
6123
6124         u8         reserved_at_40[0x8];
6125         u8         dct_number[0x18];
6126
6127         u8         reserved_at_60[0x20];
6128 };
6129
6130 struct mlx5_ifc_alloc_xrcd_out_bits {
6131         u8         status[0x8];
6132         u8         reserved_at_8[0x18];
6133
6134         u8         syndrome[0x20];
6135
6136         u8         reserved_at_40[0x8];
6137         u8         xrcd[0x18];
6138
6139         u8         reserved_at_60[0x20];
6140 };
6141
6142 struct mlx5_ifc_alloc_xrcd_in_bits {
6143         u8         opcode[0x10];
6144         u8         reserved_at_10[0x10];
6145
6146         u8         reserved_at_20[0x10];
6147         u8         op_mod[0x10];
6148
6149         u8         reserved_at_40[0x40];
6150 };
6151
6152 struct mlx5_ifc_alloc_uar_out_bits {
6153         u8         status[0x8];
6154         u8         reserved_at_8[0x18];
6155
6156         u8         syndrome[0x20];
6157
6158         u8         reserved_at_40[0x8];
6159         u8         uar[0x18];
6160
6161         u8         reserved_at_60[0x20];
6162 };
6163
6164 struct mlx5_ifc_alloc_uar_in_bits {
6165         u8         opcode[0x10];
6166         u8         reserved_at_10[0x10];
6167
6168         u8         reserved_at_20[0x10];
6169         u8         op_mod[0x10];
6170
6171         u8         reserved_at_40[0x40];
6172 };
6173
6174 struct mlx5_ifc_alloc_transport_domain_out_bits {
6175         u8         status[0x8];
6176         u8         reserved_at_8[0x18];
6177
6178         u8         syndrome[0x20];
6179
6180         u8         reserved_at_40[0x8];
6181         u8         transport_domain[0x18];
6182
6183         u8         reserved_at_60[0x20];
6184 };
6185
6186 struct mlx5_ifc_alloc_transport_domain_in_bits {
6187         u8         opcode[0x10];
6188         u8         reserved_at_10[0x10];
6189
6190         u8         reserved_at_20[0x10];
6191         u8         op_mod[0x10];
6192
6193         u8         reserved_at_40[0x40];
6194 };
6195
6196 struct mlx5_ifc_alloc_q_counter_out_bits {
6197         u8         status[0x8];
6198         u8         reserved_at_8[0x18];
6199
6200         u8         syndrome[0x20];
6201
6202         u8         reserved_at_40[0x18];
6203         u8         counter_set_id[0x8];
6204
6205         u8         reserved_at_60[0x20];
6206 };
6207
6208 struct mlx5_ifc_alloc_q_counter_in_bits {
6209         u8         opcode[0x10];
6210         u8         reserved_at_10[0x10];
6211
6212         u8         reserved_at_20[0x10];
6213         u8         op_mod[0x10];
6214
6215         u8         reserved_at_40[0x40];
6216 };
6217
6218 struct mlx5_ifc_alloc_pd_out_bits {
6219         u8         status[0x8];
6220         u8         reserved_at_8[0x18];
6221
6222         u8         syndrome[0x20];
6223
6224         u8         reserved_at_40[0x8];
6225         u8         pd[0x18];
6226
6227         u8         reserved_at_60[0x20];
6228 };
6229
6230 struct mlx5_ifc_alloc_pd_in_bits {
6231         u8         opcode[0x10];
6232         u8         reserved_at_10[0x10];
6233
6234         u8         reserved_at_20[0x10];
6235         u8         op_mod[0x10];
6236
6237         u8         reserved_at_40[0x40];
6238 };
6239
6240 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6241         u8         status[0x8];
6242         u8         reserved_at_8[0x18];
6243
6244         u8         syndrome[0x20];
6245
6246         u8         reserved_at_40[0x40];
6247 };
6248
6249 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6250         u8         opcode[0x10];
6251         u8         reserved_at_10[0x10];
6252
6253         u8         reserved_at_20[0x10];
6254         u8         op_mod[0x10];
6255
6256         u8         reserved_at_40[0x20];
6257
6258         u8         reserved_at_60[0x10];
6259         u8         vxlan_udp_port[0x10];
6260 };
6261
6262 struct mlx5_ifc_access_register_out_bits {
6263         u8         status[0x8];
6264         u8         reserved_at_8[0x18];
6265
6266         u8         syndrome[0x20];
6267
6268         u8         reserved_at_40[0x40];
6269
6270         u8         register_data[0][0x20];
6271 };
6272
6273 enum {
6274         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
6275         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
6276 };
6277
6278 struct mlx5_ifc_access_register_in_bits {
6279         u8         opcode[0x10];
6280         u8         reserved_at_10[0x10];
6281
6282         u8         reserved_at_20[0x10];
6283         u8         op_mod[0x10];
6284
6285         u8         reserved_at_40[0x10];
6286         u8         register_id[0x10];
6287
6288         u8         argument[0x20];
6289
6290         u8         register_data[0][0x20];
6291 };
6292
6293 struct mlx5_ifc_sltp_reg_bits {
6294         u8         status[0x4];
6295         u8         version[0x4];
6296         u8         local_port[0x8];
6297         u8         pnat[0x2];
6298         u8         reserved_at_12[0x2];
6299         u8         lane[0x4];
6300         u8         reserved_at_18[0x8];
6301
6302         u8         reserved_at_20[0x20];
6303
6304         u8         reserved_at_40[0x7];
6305         u8         polarity[0x1];
6306         u8         ob_tap0[0x8];
6307         u8         ob_tap1[0x8];
6308         u8         ob_tap2[0x8];
6309
6310         u8         reserved_at_60[0xc];
6311         u8         ob_preemp_mode[0x4];
6312         u8         ob_reg[0x8];
6313         u8         ob_bias[0x8];
6314
6315         u8         reserved_at_80[0x20];
6316 };
6317
6318 struct mlx5_ifc_slrg_reg_bits {
6319         u8         status[0x4];
6320         u8         version[0x4];
6321         u8         local_port[0x8];
6322         u8         pnat[0x2];
6323         u8         reserved_at_12[0x2];
6324         u8         lane[0x4];
6325         u8         reserved_at_18[0x8];
6326
6327         u8         time_to_link_up[0x10];
6328         u8         reserved_at_30[0xc];
6329         u8         grade_lane_speed[0x4];
6330
6331         u8         grade_version[0x8];
6332         u8         grade[0x18];
6333
6334         u8         reserved_at_60[0x4];
6335         u8         height_grade_type[0x4];
6336         u8         height_grade[0x18];
6337
6338         u8         height_dz[0x10];
6339         u8         height_dv[0x10];
6340
6341         u8         reserved_at_a0[0x10];
6342         u8         height_sigma[0x10];
6343
6344         u8         reserved_at_c0[0x20];
6345
6346         u8         reserved_at_e0[0x4];
6347         u8         phase_grade_type[0x4];
6348         u8         phase_grade[0x18];
6349
6350         u8         reserved_at_100[0x8];
6351         u8         phase_eo_pos[0x8];
6352         u8         reserved_at_110[0x8];
6353         u8         phase_eo_neg[0x8];
6354
6355         u8         ffe_set_tested[0x10];
6356         u8         test_errors_per_lane[0x10];
6357 };
6358
6359 struct mlx5_ifc_pvlc_reg_bits {
6360         u8         reserved_at_0[0x8];
6361         u8         local_port[0x8];
6362         u8         reserved_at_10[0x10];
6363
6364         u8         reserved_at_20[0x1c];
6365         u8         vl_hw_cap[0x4];
6366
6367         u8         reserved_at_40[0x1c];
6368         u8         vl_admin[0x4];
6369
6370         u8         reserved_at_60[0x1c];
6371         u8         vl_operational[0x4];
6372 };
6373
6374 struct mlx5_ifc_pude_reg_bits {
6375         u8         swid[0x8];
6376         u8         local_port[0x8];
6377         u8         reserved_at_10[0x4];
6378         u8         admin_status[0x4];
6379         u8         reserved_at_18[0x4];
6380         u8         oper_status[0x4];
6381
6382         u8         reserved_at_20[0x60];
6383 };
6384
6385 struct mlx5_ifc_ptys_reg_bits {
6386         u8         reserved_at_0[0x8];
6387         u8         local_port[0x8];
6388         u8         reserved_at_10[0xd];
6389         u8         proto_mask[0x3];
6390
6391         u8         reserved_at_20[0x40];
6392
6393         u8         eth_proto_capability[0x20];
6394
6395         u8         ib_link_width_capability[0x10];
6396         u8         ib_proto_capability[0x10];
6397
6398         u8         reserved_at_a0[0x20];
6399
6400         u8         eth_proto_admin[0x20];
6401
6402         u8         ib_link_width_admin[0x10];
6403         u8         ib_proto_admin[0x10];
6404
6405         u8         reserved_at_100[0x20];
6406
6407         u8         eth_proto_oper[0x20];
6408
6409         u8         ib_link_width_oper[0x10];
6410         u8         ib_proto_oper[0x10];
6411
6412         u8         reserved_at_160[0x20];
6413
6414         u8         eth_proto_lp_advertise[0x20];
6415
6416         u8         reserved_at_1a0[0x60];
6417 };
6418
6419 struct mlx5_ifc_mlcr_reg_bits {
6420         u8         reserved_at_0[0x8];
6421         u8         local_port[0x8];
6422         u8         reserved_at_10[0x20];
6423
6424         u8         beacon_duration[0x10];
6425         u8         reserved_at_40[0x10];
6426
6427         u8         beacon_remain[0x10];
6428 };
6429
6430 struct mlx5_ifc_ptas_reg_bits {
6431         u8         reserved_at_0[0x20];
6432
6433         u8         algorithm_options[0x10];
6434         u8         reserved_at_30[0x4];
6435         u8         repetitions_mode[0x4];
6436         u8         num_of_repetitions[0x8];
6437
6438         u8         grade_version[0x8];
6439         u8         height_grade_type[0x4];
6440         u8         phase_grade_type[0x4];
6441         u8         height_grade_weight[0x8];
6442         u8         phase_grade_weight[0x8];
6443
6444         u8         gisim_measure_bits[0x10];
6445         u8         adaptive_tap_measure_bits[0x10];
6446
6447         u8         ber_bath_high_error_threshold[0x10];
6448         u8         ber_bath_mid_error_threshold[0x10];
6449
6450         u8         ber_bath_low_error_threshold[0x10];
6451         u8         one_ratio_high_threshold[0x10];
6452
6453         u8         one_ratio_high_mid_threshold[0x10];
6454         u8         one_ratio_low_mid_threshold[0x10];
6455
6456         u8         one_ratio_low_threshold[0x10];
6457         u8         ndeo_error_threshold[0x10];
6458
6459         u8         mixer_offset_step_size[0x10];
6460         u8         reserved_at_110[0x8];
6461         u8         mix90_phase_for_voltage_bath[0x8];
6462
6463         u8         mixer_offset_start[0x10];
6464         u8         mixer_offset_end[0x10];
6465
6466         u8         reserved_at_140[0x15];
6467         u8         ber_test_time[0xb];
6468 };
6469
6470 struct mlx5_ifc_pspa_reg_bits {
6471         u8         swid[0x8];
6472         u8         local_port[0x8];
6473         u8         sub_port[0x8];
6474         u8         reserved_at_18[0x8];
6475
6476         u8         reserved_at_20[0x20];
6477 };
6478
6479 struct mlx5_ifc_pqdr_reg_bits {
6480         u8         reserved_at_0[0x8];
6481         u8         local_port[0x8];
6482         u8         reserved_at_10[0x5];
6483         u8         prio[0x3];
6484         u8         reserved_at_18[0x6];
6485         u8         mode[0x2];
6486
6487         u8         reserved_at_20[0x20];
6488
6489         u8         reserved_at_40[0x10];
6490         u8         min_threshold[0x10];
6491
6492         u8         reserved_at_60[0x10];
6493         u8         max_threshold[0x10];
6494
6495         u8         reserved_at_80[0x10];
6496         u8         mark_probability_denominator[0x10];
6497
6498         u8         reserved_at_a0[0x60];
6499 };
6500
6501 struct mlx5_ifc_ppsc_reg_bits {
6502         u8         reserved_at_0[0x8];
6503         u8         local_port[0x8];
6504         u8         reserved_at_10[0x10];
6505
6506         u8         reserved_at_20[0x60];
6507
6508         u8         reserved_at_80[0x1c];
6509         u8         wrps_admin[0x4];
6510
6511         u8         reserved_at_a0[0x1c];
6512         u8         wrps_status[0x4];
6513
6514         u8         reserved_at_c0[0x8];
6515         u8         up_threshold[0x8];
6516         u8         reserved_at_d0[0x8];
6517         u8         down_threshold[0x8];
6518
6519         u8         reserved_at_e0[0x20];
6520
6521         u8         reserved_at_100[0x1c];
6522         u8         srps_admin[0x4];
6523
6524         u8         reserved_at_120[0x1c];
6525         u8         srps_status[0x4];
6526
6527         u8         reserved_at_140[0x40];
6528 };
6529
6530 struct mlx5_ifc_pplr_reg_bits {
6531         u8         reserved_at_0[0x8];
6532         u8         local_port[0x8];
6533         u8         reserved_at_10[0x10];
6534
6535         u8         reserved_at_20[0x8];
6536         u8         lb_cap[0x8];
6537         u8         reserved_at_30[0x8];
6538         u8         lb_en[0x8];
6539 };
6540
6541 struct mlx5_ifc_pplm_reg_bits {
6542         u8         reserved_at_0[0x8];
6543         u8         local_port[0x8];
6544         u8         reserved_at_10[0x10];
6545
6546         u8         reserved_at_20[0x20];
6547
6548         u8         port_profile_mode[0x8];
6549         u8         static_port_profile[0x8];
6550         u8         active_port_profile[0x8];
6551         u8         reserved_at_58[0x8];
6552
6553         u8         retransmission_active[0x8];
6554         u8         fec_mode_active[0x18];
6555
6556         u8         reserved_at_80[0x20];
6557 };
6558
6559 struct mlx5_ifc_ppcnt_reg_bits {
6560         u8         swid[0x8];
6561         u8         local_port[0x8];
6562         u8         pnat[0x2];
6563         u8         reserved_at_12[0x8];
6564         u8         grp[0x6];
6565
6566         u8         clr[0x1];
6567         u8         reserved_at_21[0x1c];
6568         u8         prio_tc[0x3];
6569
6570         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6571 };
6572
6573 struct mlx5_ifc_ppad_reg_bits {
6574         u8         reserved_at_0[0x3];
6575         u8         single_mac[0x1];
6576         u8         reserved_at_4[0x4];
6577         u8         local_port[0x8];
6578         u8         mac_47_32[0x10];
6579
6580         u8         mac_31_0[0x20];
6581
6582         u8         reserved_at_40[0x40];
6583 };
6584
6585 struct mlx5_ifc_pmtu_reg_bits {
6586         u8         reserved_at_0[0x8];
6587         u8         local_port[0x8];
6588         u8         reserved_at_10[0x10];
6589
6590         u8         max_mtu[0x10];
6591         u8         reserved_at_30[0x10];
6592
6593         u8         admin_mtu[0x10];
6594         u8         reserved_at_50[0x10];
6595
6596         u8         oper_mtu[0x10];
6597         u8         reserved_at_70[0x10];
6598 };
6599
6600 struct mlx5_ifc_pmpr_reg_bits {
6601         u8         reserved_at_0[0x8];
6602         u8         module[0x8];
6603         u8         reserved_at_10[0x10];
6604
6605         u8         reserved_at_20[0x18];
6606         u8         attenuation_5g[0x8];
6607
6608         u8         reserved_at_40[0x18];
6609         u8         attenuation_7g[0x8];
6610
6611         u8         reserved_at_60[0x18];
6612         u8         attenuation_12g[0x8];
6613 };
6614
6615 struct mlx5_ifc_pmpe_reg_bits {
6616         u8         reserved_at_0[0x8];
6617         u8         module[0x8];
6618         u8         reserved_at_10[0xc];
6619         u8         module_status[0x4];
6620
6621         u8         reserved_at_20[0x60];
6622 };
6623
6624 struct mlx5_ifc_pmpc_reg_bits {
6625         u8         module_state_updated[32][0x8];
6626 };
6627
6628 struct mlx5_ifc_pmlpn_reg_bits {
6629         u8         reserved_at_0[0x4];
6630         u8         mlpn_status[0x4];
6631         u8         local_port[0x8];
6632         u8         reserved_at_10[0x10];
6633
6634         u8         e[0x1];
6635         u8         reserved_at_21[0x1f];
6636 };
6637
6638 struct mlx5_ifc_pmlp_reg_bits {
6639         u8         rxtx[0x1];
6640         u8         reserved_at_1[0x7];
6641         u8         local_port[0x8];
6642         u8         reserved_at_10[0x8];
6643         u8         width[0x8];
6644
6645         u8         lane0_module_mapping[0x20];
6646
6647         u8         lane1_module_mapping[0x20];
6648
6649         u8         lane2_module_mapping[0x20];
6650
6651         u8         lane3_module_mapping[0x20];
6652
6653         u8         reserved_at_a0[0x160];
6654 };
6655
6656 struct mlx5_ifc_pmaos_reg_bits {
6657         u8         reserved_at_0[0x8];
6658         u8         module[0x8];
6659         u8         reserved_at_10[0x4];
6660         u8         admin_status[0x4];
6661         u8         reserved_at_18[0x4];
6662         u8         oper_status[0x4];
6663
6664         u8         ase[0x1];
6665         u8         ee[0x1];
6666         u8         reserved_at_22[0x1c];
6667         u8         e[0x2];
6668
6669         u8         reserved_at_40[0x40];
6670 };
6671
6672 struct mlx5_ifc_plpc_reg_bits {
6673         u8         reserved_at_0[0x4];
6674         u8         profile_id[0xc];
6675         u8         reserved_at_10[0x4];
6676         u8         proto_mask[0x4];
6677         u8         reserved_at_18[0x8];
6678
6679         u8         reserved_at_20[0x10];
6680         u8         lane_speed[0x10];
6681
6682         u8         reserved_at_40[0x17];
6683         u8         lpbf[0x1];
6684         u8         fec_mode_policy[0x8];
6685
6686         u8         retransmission_capability[0x8];
6687         u8         fec_mode_capability[0x18];
6688
6689         u8         retransmission_support_admin[0x8];
6690         u8         fec_mode_support_admin[0x18];
6691
6692         u8         retransmission_request_admin[0x8];
6693         u8         fec_mode_request_admin[0x18];
6694
6695         u8         reserved_at_c0[0x80];
6696 };
6697
6698 struct mlx5_ifc_plib_reg_bits {
6699         u8         reserved_at_0[0x8];
6700         u8         local_port[0x8];
6701         u8         reserved_at_10[0x8];
6702         u8         ib_port[0x8];
6703
6704         u8         reserved_at_20[0x60];
6705 };
6706
6707 struct mlx5_ifc_plbf_reg_bits {
6708         u8         reserved_at_0[0x8];
6709         u8         local_port[0x8];
6710         u8         reserved_at_10[0xd];
6711         u8         lbf_mode[0x3];
6712
6713         u8         reserved_at_20[0x20];
6714 };
6715
6716 struct mlx5_ifc_pipg_reg_bits {
6717         u8         reserved_at_0[0x8];
6718         u8         local_port[0x8];
6719         u8         reserved_at_10[0x10];
6720
6721         u8         dic[0x1];
6722         u8         reserved_at_21[0x19];
6723         u8         ipg[0x4];
6724         u8         reserved_at_3e[0x2];
6725 };
6726
6727 struct mlx5_ifc_pifr_reg_bits {
6728         u8         reserved_at_0[0x8];
6729         u8         local_port[0x8];
6730         u8         reserved_at_10[0x10];
6731
6732         u8         reserved_at_20[0xe0];
6733
6734         u8         port_filter[8][0x20];
6735
6736         u8         port_filter_update_en[8][0x20];
6737 };
6738
6739 struct mlx5_ifc_pfcc_reg_bits {
6740         u8         reserved_at_0[0x8];
6741         u8         local_port[0x8];
6742         u8         reserved_at_10[0x10];
6743
6744         u8         ppan[0x4];
6745         u8         reserved_at_24[0x4];
6746         u8         prio_mask_tx[0x8];
6747         u8         reserved_at_30[0x8];
6748         u8         prio_mask_rx[0x8];
6749
6750         u8         pptx[0x1];
6751         u8         aptx[0x1];
6752         u8         reserved_at_42[0x6];
6753         u8         pfctx[0x8];
6754         u8         reserved_at_50[0x10];
6755
6756         u8         pprx[0x1];
6757         u8         aprx[0x1];
6758         u8         reserved_at_62[0x6];
6759         u8         pfcrx[0x8];
6760         u8         reserved_at_70[0x10];
6761
6762         u8         reserved_at_80[0x80];
6763 };
6764
6765 struct mlx5_ifc_pelc_reg_bits {
6766         u8         op[0x4];
6767         u8         reserved_at_4[0x4];
6768         u8         local_port[0x8];
6769         u8         reserved_at_10[0x10];
6770
6771         u8         op_admin[0x8];
6772         u8         op_capability[0x8];
6773         u8         op_request[0x8];
6774         u8         op_active[0x8];
6775
6776         u8         admin[0x40];
6777
6778         u8         capability[0x40];
6779
6780         u8         request[0x40];
6781
6782         u8         active[0x40];
6783
6784         u8         reserved_at_140[0x80];
6785 };
6786
6787 struct mlx5_ifc_peir_reg_bits {
6788         u8         reserved_at_0[0x8];
6789         u8         local_port[0x8];
6790         u8         reserved_at_10[0x10];
6791
6792         u8         reserved_at_20[0xc];
6793         u8         error_count[0x4];
6794         u8         reserved_at_30[0x10];
6795
6796         u8         reserved_at_40[0xc];
6797         u8         lane[0x4];
6798         u8         reserved_at_50[0x8];
6799         u8         error_type[0x8];
6800 };
6801
6802 struct mlx5_ifc_pcap_reg_bits {
6803         u8         reserved_at_0[0x8];
6804         u8         local_port[0x8];
6805         u8         reserved_at_10[0x10];
6806
6807         u8         port_capability_mask[4][0x20];
6808 };
6809
6810 struct mlx5_ifc_paos_reg_bits {
6811         u8         swid[0x8];
6812         u8         local_port[0x8];
6813         u8         reserved_at_10[0x4];
6814         u8         admin_status[0x4];
6815         u8         reserved_at_18[0x4];
6816         u8         oper_status[0x4];
6817
6818         u8         ase[0x1];
6819         u8         ee[0x1];
6820         u8         reserved_at_22[0x1c];
6821         u8         e[0x2];
6822
6823         u8         reserved_at_40[0x40];
6824 };
6825
6826 struct mlx5_ifc_pamp_reg_bits {
6827         u8         reserved_at_0[0x8];
6828         u8         opamp_group[0x8];
6829         u8         reserved_at_10[0xc];
6830         u8         opamp_group_type[0x4];
6831
6832         u8         start_index[0x10];
6833         u8         reserved_at_30[0x4];
6834         u8         num_of_indices[0xc];
6835
6836         u8         index_data[18][0x10];
6837 };
6838
6839 struct mlx5_ifc_pcmr_reg_bits {
6840         u8         reserved_at_0[0x8];
6841         u8         local_port[0x8];
6842         u8         reserved_at_10[0x2e];
6843         u8         fcs_cap[0x1];
6844         u8         reserved_at_3f[0x1f];
6845         u8         fcs_chk[0x1];
6846         u8         reserved_at_5f[0x1];
6847 };
6848
6849 struct mlx5_ifc_lane_2_module_mapping_bits {
6850         u8         reserved_at_0[0x6];
6851         u8         rx_lane[0x2];
6852         u8         reserved_at_8[0x6];
6853         u8         tx_lane[0x2];
6854         u8         reserved_at_10[0x8];
6855         u8         module[0x8];
6856 };
6857
6858 struct mlx5_ifc_bufferx_reg_bits {
6859         u8         reserved_at_0[0x6];
6860         u8         lossy[0x1];
6861         u8         epsb[0x1];
6862         u8         reserved_at_8[0xc];
6863         u8         size[0xc];
6864
6865         u8         xoff_threshold[0x10];
6866         u8         xon_threshold[0x10];
6867 };
6868
6869 struct mlx5_ifc_set_node_in_bits {
6870         u8         node_description[64][0x8];
6871 };
6872
6873 struct mlx5_ifc_register_power_settings_bits {
6874         u8         reserved_at_0[0x18];
6875         u8         power_settings_level[0x8];
6876
6877         u8         reserved_at_20[0x60];
6878 };
6879
6880 struct mlx5_ifc_register_host_endianness_bits {
6881         u8         he[0x1];
6882         u8         reserved_at_1[0x1f];
6883
6884         u8         reserved_at_20[0x60];
6885 };
6886
6887 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6888         u8         reserved_at_0[0x20];
6889
6890         u8         mkey[0x20];
6891
6892         u8         addressh_63_32[0x20];
6893
6894         u8         addressl_31_0[0x20];
6895 };
6896
6897 struct mlx5_ifc_ud_adrs_vector_bits {
6898         u8         dc_key[0x40];
6899
6900         u8         ext[0x1];
6901         u8         reserved_at_41[0x7];
6902         u8         destination_qp_dct[0x18];
6903
6904         u8         static_rate[0x4];
6905         u8         sl_eth_prio[0x4];
6906         u8         fl[0x1];
6907         u8         mlid[0x7];
6908         u8         rlid_udp_sport[0x10];
6909
6910         u8         reserved_at_80[0x20];
6911
6912         u8         rmac_47_16[0x20];
6913
6914         u8         rmac_15_0[0x10];
6915         u8         tclass[0x8];
6916         u8         hop_limit[0x8];
6917
6918         u8         reserved_at_e0[0x1];
6919         u8         grh[0x1];
6920         u8         reserved_at_e2[0x2];
6921         u8         src_addr_index[0x8];
6922         u8         flow_label[0x14];
6923
6924         u8         rgid_rip[16][0x8];
6925 };
6926
6927 struct mlx5_ifc_pages_req_event_bits {
6928         u8         reserved_at_0[0x10];
6929         u8         function_id[0x10];
6930
6931         u8         num_pages[0x20];
6932
6933         u8         reserved_at_40[0xa0];
6934 };
6935
6936 struct mlx5_ifc_eqe_bits {
6937         u8         reserved_at_0[0x8];
6938         u8         event_type[0x8];
6939         u8         reserved_at_10[0x8];
6940         u8         event_sub_type[0x8];
6941
6942         u8         reserved_at_20[0xe0];
6943
6944         union mlx5_ifc_event_auto_bits event_data;
6945
6946         u8         reserved_at_1e0[0x10];
6947         u8         signature[0x8];
6948         u8         reserved_at_1f8[0x7];
6949         u8         owner[0x1];
6950 };
6951
6952 enum {
6953         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
6954 };
6955
6956 struct mlx5_ifc_cmd_queue_entry_bits {
6957         u8         type[0x8];
6958         u8         reserved_at_8[0x18];
6959
6960         u8         input_length[0x20];
6961
6962         u8         input_mailbox_pointer_63_32[0x20];
6963
6964         u8         input_mailbox_pointer_31_9[0x17];
6965         u8         reserved_at_77[0x9];
6966
6967         u8         command_input_inline_data[16][0x8];
6968
6969         u8         command_output_inline_data[16][0x8];
6970
6971         u8         output_mailbox_pointer_63_32[0x20];
6972
6973         u8         output_mailbox_pointer_31_9[0x17];
6974         u8         reserved_at_1b7[0x9];
6975
6976         u8         output_length[0x20];
6977
6978         u8         token[0x8];
6979         u8         signature[0x8];
6980         u8         reserved_at_1f0[0x8];
6981         u8         status[0x7];
6982         u8         ownership[0x1];
6983 };
6984
6985 struct mlx5_ifc_cmd_out_bits {
6986         u8         status[0x8];
6987         u8         reserved_at_8[0x18];
6988
6989         u8         syndrome[0x20];
6990
6991         u8         command_output[0x20];
6992 };
6993
6994 struct mlx5_ifc_cmd_in_bits {
6995         u8         opcode[0x10];
6996         u8         reserved_at_10[0x10];
6997
6998         u8         reserved_at_20[0x10];
6999         u8         op_mod[0x10];
7000
7001         u8         command[0][0x20];
7002 };
7003
7004 struct mlx5_ifc_cmd_if_box_bits {
7005         u8         mailbox_data[512][0x8];
7006
7007         u8         reserved_at_1000[0x180];
7008
7009         u8         next_pointer_63_32[0x20];
7010
7011         u8         next_pointer_31_10[0x16];
7012         u8         reserved_at_11b6[0xa];
7013
7014         u8         block_number[0x20];
7015
7016         u8         reserved_at_11e0[0x8];
7017         u8         token[0x8];
7018         u8         ctrl_signature[0x8];
7019         u8         signature[0x8];
7020 };
7021
7022 struct mlx5_ifc_mtt_bits {
7023         u8         ptag_63_32[0x20];
7024
7025         u8         ptag_31_8[0x18];
7026         u8         reserved_at_38[0x6];
7027         u8         wr_en[0x1];
7028         u8         rd_en[0x1];
7029 };
7030
7031 struct mlx5_ifc_query_wol_rol_out_bits {
7032         u8         status[0x8];
7033         u8         reserved_at_8[0x18];
7034
7035         u8         syndrome[0x20];
7036
7037         u8         reserved_at_40[0x10];
7038         u8         rol_mode[0x8];
7039         u8         wol_mode[0x8];
7040
7041         u8         reserved_at_60[0x20];
7042 };
7043
7044 struct mlx5_ifc_query_wol_rol_in_bits {
7045         u8         opcode[0x10];
7046         u8         reserved_at_10[0x10];
7047
7048         u8         reserved_at_20[0x10];
7049         u8         op_mod[0x10];
7050
7051         u8         reserved_at_40[0x40];
7052 };
7053
7054 struct mlx5_ifc_set_wol_rol_out_bits {
7055         u8         status[0x8];
7056         u8         reserved_at_8[0x18];
7057
7058         u8         syndrome[0x20];
7059
7060         u8         reserved_at_40[0x40];
7061 };
7062
7063 struct mlx5_ifc_set_wol_rol_in_bits {
7064         u8         opcode[0x10];
7065         u8         reserved_at_10[0x10];
7066
7067         u8         reserved_at_20[0x10];
7068         u8         op_mod[0x10];
7069
7070         u8         rol_mode_valid[0x1];
7071         u8         wol_mode_valid[0x1];
7072         u8         reserved_at_42[0xe];
7073         u8         rol_mode[0x8];
7074         u8         wol_mode[0x8];
7075
7076         u8         reserved_at_60[0x20];
7077 };
7078
7079 enum {
7080         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
7081         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
7082         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
7083 };
7084
7085 enum {
7086         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
7087         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
7088         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
7089 };
7090
7091 enum {
7092         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
7093         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
7094         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
7095         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
7096         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
7097         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
7098         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
7099         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
7100         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
7101         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
7102         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
7103 };
7104
7105 struct mlx5_ifc_initial_seg_bits {
7106         u8         fw_rev_minor[0x10];
7107         u8         fw_rev_major[0x10];
7108
7109         u8         cmd_interface_rev[0x10];
7110         u8         fw_rev_subminor[0x10];
7111
7112         u8         reserved_at_40[0x40];
7113
7114         u8         cmdq_phy_addr_63_32[0x20];
7115
7116         u8         cmdq_phy_addr_31_12[0x14];
7117         u8         reserved_at_b4[0x2];
7118         u8         nic_interface[0x2];
7119         u8         log_cmdq_size[0x4];
7120         u8         log_cmdq_stride[0x4];
7121
7122         u8         command_doorbell_vector[0x20];
7123
7124         u8         reserved_at_e0[0xf00];
7125
7126         u8         initializing[0x1];
7127         u8         reserved_at_fe1[0x4];
7128         u8         nic_interface_supported[0x3];
7129         u8         reserved_at_fe8[0x18];
7130
7131         struct mlx5_ifc_health_buffer_bits health_buffer;
7132
7133         u8         no_dram_nic_offset[0x20];
7134
7135         u8         reserved_at_1220[0x6e40];
7136
7137         u8         reserved_at_8060[0x1f];
7138         u8         clear_int[0x1];
7139
7140         u8         health_syndrome[0x8];
7141         u8         health_counter[0x18];
7142
7143         u8         reserved_at_80a0[0x17fc0];
7144 };
7145
7146 union mlx5_ifc_ports_control_registers_document_bits {
7147         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7148         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7149         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7150         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7151         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7152         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7153         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7154         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7155         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7156         struct mlx5_ifc_pamp_reg_bits pamp_reg;
7157         struct mlx5_ifc_paos_reg_bits paos_reg;
7158         struct mlx5_ifc_pcap_reg_bits pcap_reg;
7159         struct mlx5_ifc_peir_reg_bits peir_reg;
7160         struct mlx5_ifc_pelc_reg_bits pelc_reg;
7161         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7162         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7163         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7164         struct mlx5_ifc_pifr_reg_bits pifr_reg;
7165         struct mlx5_ifc_pipg_reg_bits pipg_reg;
7166         struct mlx5_ifc_plbf_reg_bits plbf_reg;
7167         struct mlx5_ifc_plib_reg_bits plib_reg;
7168         struct mlx5_ifc_plpc_reg_bits plpc_reg;
7169         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7170         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7171         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7172         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7173         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7174         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7175         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7176         struct mlx5_ifc_ppad_reg_bits ppad_reg;
7177         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7178         struct mlx5_ifc_pplm_reg_bits pplm_reg;
7179         struct mlx5_ifc_pplr_reg_bits pplr_reg;
7180         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7181         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7182         struct mlx5_ifc_pspa_reg_bits pspa_reg;
7183         struct mlx5_ifc_ptas_reg_bits ptas_reg;
7184         struct mlx5_ifc_ptys_reg_bits ptys_reg;
7185         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
7186         struct mlx5_ifc_pude_reg_bits pude_reg;
7187         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7188         struct mlx5_ifc_slrg_reg_bits slrg_reg;
7189         struct mlx5_ifc_sltp_reg_bits sltp_reg;
7190         u8         reserved_at_0[0x60e0];
7191 };
7192
7193 union mlx5_ifc_debug_enhancements_document_bits {
7194         struct mlx5_ifc_health_buffer_bits health_buffer;
7195         u8         reserved_at_0[0x200];
7196 };
7197
7198 union mlx5_ifc_uplink_pci_interface_document_bits {
7199         struct mlx5_ifc_initial_seg_bits initial_seg;
7200         u8         reserved_at_0[0x20060];
7201 };
7202
7203 struct mlx5_ifc_set_flow_table_root_out_bits {
7204         u8         status[0x8];
7205         u8         reserved_at_8[0x18];
7206
7207         u8         syndrome[0x20];
7208
7209         u8         reserved_at_40[0x40];
7210 };
7211
7212 struct mlx5_ifc_set_flow_table_root_in_bits {
7213         u8         opcode[0x10];
7214         u8         reserved_at_10[0x10];
7215
7216         u8         reserved_at_20[0x10];
7217         u8         op_mod[0x10];
7218
7219         u8         other_vport[0x1];
7220         u8         reserved_at_41[0xf];
7221         u8         vport_number[0x10];
7222
7223         u8         reserved_at_60[0x20];
7224
7225         u8         table_type[0x8];
7226         u8         reserved_at_88[0x18];
7227
7228         u8         reserved_at_a0[0x8];
7229         u8         table_id[0x18];
7230
7231         u8         reserved_at_c0[0x140];
7232 };
7233
7234 enum {
7235         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7236 };
7237
7238 struct mlx5_ifc_modify_flow_table_out_bits {
7239         u8         status[0x8];
7240         u8         reserved_at_8[0x18];
7241
7242         u8         syndrome[0x20];
7243
7244         u8         reserved_at_40[0x40];
7245 };
7246
7247 struct mlx5_ifc_modify_flow_table_in_bits {
7248         u8         opcode[0x10];
7249         u8         reserved_at_10[0x10];
7250
7251         u8         reserved_at_20[0x10];
7252         u8         op_mod[0x10];
7253
7254         u8         other_vport[0x1];
7255         u8         reserved_at_41[0xf];
7256         u8         vport_number[0x10];
7257
7258         u8         reserved_at_60[0x10];
7259         u8         modify_field_select[0x10];
7260
7261         u8         table_type[0x8];
7262         u8         reserved_at_88[0x18];
7263
7264         u8         reserved_at_a0[0x8];
7265         u8         table_id[0x18];
7266
7267         u8         reserved_at_c0[0x4];
7268         u8         table_miss_mode[0x4];
7269         u8         reserved_at_c8[0x18];
7270
7271         u8         reserved_at_e0[0x8];
7272         u8         table_miss_id[0x18];
7273
7274         u8         reserved_at_100[0x100];
7275 };
7276
7277 struct mlx5_ifc_ets_tcn_config_reg_bits {
7278         u8         g[0x1];
7279         u8         b[0x1];
7280         u8         r[0x1];
7281         u8         reserved_at_3[0x9];
7282         u8         group[0x4];
7283         u8         reserved_at_10[0x9];
7284         u8         bw_allocation[0x7];
7285
7286         u8         reserved_at_20[0xc];
7287         u8         max_bw_units[0x4];
7288         u8         reserved_at_30[0x8];
7289         u8         max_bw_value[0x8];
7290 };
7291
7292 struct mlx5_ifc_ets_global_config_reg_bits {
7293         u8         reserved_at_0[0x2];
7294         u8         r[0x1];
7295         u8         reserved_at_3[0x1d];
7296
7297         u8         reserved_at_20[0xc];
7298         u8         max_bw_units[0x4];
7299         u8         reserved_at_30[0x8];
7300         u8         max_bw_value[0x8];
7301 };
7302
7303 struct mlx5_ifc_qetc_reg_bits {
7304         u8                                         reserved_at_0[0x8];
7305         u8                                         port_number[0x8];
7306         u8                                         reserved_at_10[0x30];
7307
7308         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
7309         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7310 };
7311
7312 struct mlx5_ifc_qtct_reg_bits {
7313         u8         reserved_at_0[0x8];
7314         u8         port_number[0x8];
7315         u8         reserved_at_10[0xd];
7316         u8         prio[0x3];
7317
7318         u8         reserved_at_20[0x1d];
7319         u8         tclass[0x3];
7320 };
7321
7322 struct mlx5_ifc_mcia_reg_bits {
7323         u8         l[0x1];
7324         u8         reserved_at_1[0x7];
7325         u8         module[0x8];
7326         u8         reserved_at_10[0x8];
7327         u8         status[0x8];
7328
7329         u8         i2c_device_address[0x8];
7330         u8         page_number[0x8];
7331         u8         device_address[0x10];
7332
7333         u8         reserved_at_40[0x10];
7334         u8         size[0x10];
7335
7336         u8         reserved_at_60[0x20];
7337
7338         u8         dword_0[0x20];
7339         u8         dword_1[0x20];
7340         u8         dword_2[0x20];
7341         u8         dword_3[0x20];
7342         u8         dword_4[0x20];
7343         u8         dword_5[0x20];
7344         u8         dword_6[0x20];
7345         u8         dword_7[0x20];
7346         u8         dword_8[0x20];
7347         u8         dword_9[0x20];
7348         u8         dword_10[0x20];
7349         u8         dword_11[0x20];
7350 };
7351
7352 #endif /* MLX5_IFC_H */