include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  71         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  72 };
  73
  74 enum {
  75         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  76         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  77         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  78         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  79         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  80         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  81         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  82         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  83         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  84         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  85         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  86         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  87         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  88         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  89         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  90         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  91         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  92         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  93         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  94         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  95         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  96         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  97         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  98         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
  99         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 100         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 101         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 102         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 103         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 104         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 105         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 106         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 107         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 108         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 109         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 110         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 111         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 112         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 113         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 114         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 115         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 116         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 117         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 118         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 119         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 120         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 121         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 122         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 123         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 124         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 125         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 126         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 127         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 128         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 129         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 130         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 131         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 132         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 133         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 134         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 135         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 136         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 137         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 138         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 139         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 140         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 141         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 142         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 143         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 144         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 145         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 146         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 147         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 148         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 149         MLX5_CMD_OP_DETTACH_FROM_MCG              = 0x807,
 150         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 151         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 152         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 153         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 154         MLX5_CMD_OP_NOP                           = 0x80d,
 155         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 156         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 157         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 158         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 159         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 160         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 161         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 162         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 163         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 164         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 165         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 166         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 167         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 168         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 169         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 170         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 171         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 172         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 173         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 174         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 175         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 176         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 177         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 178         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 179         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 180         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 181         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 182         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 183         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 184         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 185         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 186         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 187         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 188         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 189         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 190         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 191         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 192         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 193         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 194         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 195         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 196         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 197         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 198         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 199         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 200         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 201         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 202         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 203         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c
 204 };
 205
 206 struct mlx5_ifc_flow_table_fields_supported_bits {
 207         u8         outer_dmac[0x1];
 208         u8         outer_smac[0x1];
 209         u8         outer_ether_type[0x1];
 210         u8         reserved_at_3[0x1];
 211         u8         outer_first_prio[0x1];
 212         u8         outer_first_cfi[0x1];
 213         u8         outer_first_vid[0x1];
 214         u8         reserved_at_7[0x1];
 215         u8         outer_second_prio[0x1];
 216         u8         outer_second_cfi[0x1];
 217         u8         outer_second_vid[0x1];
 218         u8         reserved_at_b[0x1];
 219         u8         outer_sip[0x1];
 220         u8         outer_dip[0x1];
 221         u8         outer_frag[0x1];
 222         u8         outer_ip_protocol[0x1];
 223         u8         outer_ip_ecn[0x1];
 224         u8         outer_ip_dscp[0x1];
 225         u8         outer_udp_sport[0x1];
 226         u8         outer_udp_dport[0x1];
 227         u8         outer_tcp_sport[0x1];
 228         u8         outer_tcp_dport[0x1];
 229         u8         outer_tcp_flags[0x1];
 230         u8         outer_gre_protocol[0x1];
 231         u8         outer_gre_key[0x1];
 232         u8         outer_vxlan_vni[0x1];
 233         u8         reserved_at_1a[0x5];
 234         u8         source_eswitch_port[0x1];
 235
 236         u8         inner_dmac[0x1];
 237         u8         inner_smac[0x1];
 238         u8         inner_ether_type[0x1];
 239         u8         reserved_at_23[0x1];
 240         u8         inner_first_prio[0x1];
 241         u8         inner_first_cfi[0x1];
 242         u8         inner_first_vid[0x1];
 243         u8         reserved_at_27[0x1];
 244         u8         inner_second_prio[0x1];
 245         u8         inner_second_cfi[0x1];
 246         u8         inner_second_vid[0x1];
 247         u8         reserved_at_2b[0x1];
 248         u8         inner_sip[0x1];
 249         u8         inner_dip[0x1];
 250         u8         inner_frag[0x1];
 251         u8         inner_ip_protocol[0x1];
 252         u8         inner_ip_ecn[0x1];
 253         u8         inner_ip_dscp[0x1];
 254         u8         inner_udp_sport[0x1];
 255         u8         inner_udp_dport[0x1];
 256         u8         inner_tcp_sport[0x1];
 257         u8         inner_tcp_dport[0x1];
 258         u8         inner_tcp_flags[0x1];
 259         u8         reserved_at_37[0x9];
 260
 261         u8         reserved_at_40[0x40];
 262 };
 263
 264 struct mlx5_ifc_flow_table_prop_layout_bits {
 265         u8         ft_support[0x1];
 266         u8         reserved_at_1[0x2];
 267         u8         flow_modify_en[0x1];
 268         u8         modify_root[0x1];
 269         u8         identified_miss_table_mode[0x1];
 270         u8         flow_table_modify[0x1];
 271         u8         reserved_at_7[0x19];
 272
 273         u8         reserved_at_20[0x2];
 274         u8         log_max_ft_size[0x6];
 275         u8         reserved_at_28[0x10];
 276         u8         max_ft_level[0x8];
 277
 278         u8         reserved_at_40[0x20];
 279
 280         u8         reserved_at_60[0x18];
 281         u8         log_max_ft_num[0x8];
 282
 283         u8         reserved_at_80[0x18];
 284         u8         log_max_destination[0x8];
 285
 286         u8         reserved_at_a0[0x18];
 287         u8         log_max_flow[0x8];
 288
 289         u8         reserved_at_c0[0x40];
 290
 291         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 292
 293         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 294 };
 295
 296 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 297         u8         send[0x1];
 298         u8         receive[0x1];
 299         u8         write[0x1];
 300         u8         read[0x1];
 301         u8         reserved_at_4[0x1];
 302         u8         srq_receive[0x1];
 303         u8         reserved_at_6[0x1a];
 304 };
 305
 306 struct mlx5_ifc_ipv4_layout_bits {
 307         u8         reserved_at_0[0x60];
 308
 309         u8         ipv4[0x20];
 310 };
 311
 312 struct mlx5_ifc_ipv6_layout_bits {
 313         u8         ipv6[16][0x8];
 314 };
 315
 316 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 317         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 318         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 319         u8         reserved_at_0[0x80];
 320 };
 321
 322 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 323         u8         smac_47_16[0x20];
 324
 325         u8         smac_15_0[0x10];
 326         u8         ethertype[0x10];
 327
 328         u8         dmac_47_16[0x20];
 329
 330         u8         dmac_15_0[0x10];
 331         u8         first_prio[0x3];
 332         u8         first_cfi[0x1];
 333         u8         first_vid[0xc];
 334
 335         u8         ip_protocol[0x8];
 336         u8         ip_dscp[0x6];
 337         u8         ip_ecn[0x2];
 338         u8         vlan_tag[0x1];
 339         u8         reserved_at_91[0x1];
 340         u8         frag[0x1];
 341         u8         reserved_at_93[0x4];
 342         u8         tcp_flags[0x9];
 343
 344         u8         tcp_sport[0x10];
 345         u8         tcp_dport[0x10];
 346
 347         u8         reserved_at_c0[0x20];
 348
 349         u8         udp_sport[0x10];
 350         u8         udp_dport[0x10];
 351
 352         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 353
 354         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 355 };
 356
 357 struct mlx5_ifc_fte_match_set_misc_bits {
 358         u8         reserved_at_0[0x20];
 359
 360         u8         reserved_at_20[0x10];
 361         u8         source_port[0x10];
 362
 363         u8         outer_second_prio[0x3];
 364         u8         outer_second_cfi[0x1];
 365         u8         outer_second_vid[0xc];
 366         u8         inner_second_prio[0x3];
 367         u8         inner_second_cfi[0x1];
 368         u8         inner_second_vid[0xc];
 369
 370         u8         outer_second_vlan_tag[0x1];
 371         u8         inner_second_vlan_tag[0x1];
 372         u8         reserved_at_62[0xe];
 373         u8         gre_protocol[0x10];
 374
 375         u8         gre_key_h[0x18];
 376         u8         gre_key_l[0x8];
 377
 378         u8         vxlan_vni[0x18];
 379         u8         reserved_at_b8[0x8];
 380
 381         u8         reserved_at_c0[0x20];
 382
 383         u8         reserved_at_e0[0xc];
 384         u8         outer_ipv6_flow_label[0x14];
 385
 386         u8         reserved_at_100[0xc];
 387         u8         inner_ipv6_flow_label[0x14];
 388
 389         u8         reserved_at_120[0xe0];
 390 };
 391
 392 struct mlx5_ifc_cmd_pas_bits {
 393         u8         pa_h[0x20];
 394
 395         u8         pa_l[0x14];
 396         u8         reserved_at_34[0xc];
 397 };
 398
 399 struct mlx5_ifc_uint64_bits {
 400         u8         hi[0x20];
 401
 402         u8         lo[0x20];
 403 };
 404
 405 enum {
 406         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 407         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 408         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 409         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 410         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 411         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 412         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 413         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 414         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 415         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 416 };
 417
 418 struct mlx5_ifc_ads_bits {
 419         u8         fl[0x1];
 420         u8         free_ar[0x1];
 421         u8         reserved_at_2[0xe];
 422         u8         pkey_index[0x10];
 423
 424         u8         reserved_at_20[0x8];
 425         u8         grh[0x1];
 426         u8         mlid[0x7];
 427         u8         rlid[0x10];
 428
 429         u8         ack_timeout[0x5];
 430         u8         reserved_at_45[0x3];
 431         u8         src_addr_index[0x8];
 432         u8         reserved_at_50[0x4];
 433         u8         stat_rate[0x4];
 434         u8         hop_limit[0x8];
 435
 436         u8         reserved_at_60[0x4];
 437         u8         tclass[0x8];
 438         u8         flow_label[0x14];
 439
 440         u8         rgid_rip[16][0x8];
 441
 442         u8         reserved_at_100[0x4];
 443         u8         f_dscp[0x1];
 444         u8         f_ecn[0x1];
 445         u8         reserved_at_106[0x1];
 446         u8         f_eth_prio[0x1];
 447         u8         ecn[0x2];
 448         u8         dscp[0x6];
 449         u8         udp_sport[0x10];
 450
 451         u8         dei_cfi[0x1];
 452         u8         eth_prio[0x3];
 453         u8         sl[0x4];
 454         u8         port[0x8];
 455         u8         rmac_47_32[0x10];
 456
 457         u8         rmac_31_0[0x20];
 458 };
 459
 460 struct mlx5_ifc_flow_table_nic_cap_bits {
 461         u8         reserved_at_0[0x200];
 462
 463         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 464
 465         u8         reserved_at_400[0x200];
 466
 467         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 468
 469         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 470
 471         u8         reserved_at_a00[0x200];
 472
 473         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 474
 475         u8         reserved_at_e00[0x7200];
 476 };
 477
 478 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 479         u8     reserved_at_0[0x200];
 480
 481         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 482
 483         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 484
 485         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 486
 487         u8      reserved_at_800[0x7800];
 488 };
 489
 490 struct mlx5_ifc_e_switch_cap_bits {
 491         u8         vport_svlan_strip[0x1];
 492         u8         vport_cvlan_strip[0x1];
 493         u8         vport_svlan_insert[0x1];
 494         u8         vport_cvlan_insert_if_not_exist[0x1];
 495         u8         vport_cvlan_insert_overwrite[0x1];
 496         u8         reserved_at_5[0x1b];
 497
 498         u8         reserved_at_20[0x7e0];
 499 };
 500
 501 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 502         u8         csum_cap[0x1];
 503         u8         vlan_cap[0x1];
 504         u8         lro_cap[0x1];
 505         u8         lro_psh_flag[0x1];
 506         u8         lro_time_stamp[0x1];
 507         u8         reserved_at_5[0x3];
 508         u8         self_lb_en_modifiable[0x1];
 509         u8         reserved_at_9[0x2];
 510         u8         max_lso_cap[0x5];
 511         u8         reserved_at_10[0x4];
 512         u8         rss_ind_tbl_cap[0x4];
 513         u8         reserved_at_18[0x3];
 514         u8         tunnel_lso_const_out_ip_id[0x1];
 515         u8         reserved_at_1c[0x2];
 516         u8         tunnel_statless_gre[0x1];
 517         u8         tunnel_stateless_vxlan[0x1];
 518
 519         u8         reserved_at_20[0x20];
 520
 521         u8         reserved_at_40[0x10];
 522         u8         lro_min_mss_size[0x10];
 523
 524         u8         reserved_at_60[0x120];
 525
 526         u8         lro_timer_supported_periods[4][0x20];
 527
 528         u8         reserved_at_200[0x600];
 529 };
 530
 531 struct mlx5_ifc_roce_cap_bits {
 532         u8         roce_apm[0x1];
 533         u8         reserved_at_1[0x1f];
 534
 535         u8         reserved_at_20[0x60];
 536
 537         u8         reserved_at_80[0xc];
 538         u8         l3_type[0x4];
 539         u8         reserved_at_90[0x8];
 540         u8         roce_version[0x8];
 541
 542         u8         reserved_at_a0[0x10];
 543         u8         r_roce_dest_udp_port[0x10];
 544
 545         u8         r_roce_max_src_udp_port[0x10];
 546         u8         r_roce_min_src_udp_port[0x10];
 547
 548         u8         reserved_at_e0[0x10];
 549         u8         roce_address_table_size[0x10];
 550
 551         u8         reserved_at_100[0x700];
 552 };
 553
 554 enum {
 555         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 556         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 557         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 558         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 559         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 560         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 561         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 562         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 563         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 564 };
 565
 566 enum {
 567         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 568         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 569         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 570         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 571         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 572         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 573         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 574         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 575         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 576 };
 577
 578 struct mlx5_ifc_atomic_caps_bits {
 579         u8         reserved_at_0[0x40];
 580
 581         u8         atomic_req_8B_endianess_mode[0x2];
 582         u8         reserved_at_42[0x4];
 583         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 584
 585         u8         reserved_at_47[0x19];
 586
 587         u8         reserved_at_60[0x20];
 588
 589         u8         reserved_at_80[0x10];
 590         u8         atomic_operations[0x10];
 591
 592         u8         reserved_at_a0[0x10];
 593         u8         atomic_size_qp[0x10];
 594
 595         u8         reserved_at_c0[0x10];
 596         u8         atomic_size_dc[0x10];
 597
 598         u8         reserved_at_e0[0x720];
 599 };
 600
 601 struct mlx5_ifc_odp_cap_bits {
 602         u8         reserved_at_0[0x40];
 603
 604         u8         sig[0x1];
 605         u8         reserved_at_41[0x1f];
 606
 607         u8         reserved_at_60[0x20];
 608
 609         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 610
 611         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 612
 613         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 614
 615         u8         reserved_at_e0[0x720];
 616 };
 617
 618 enum {
 619         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 620         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 621         MLX5_WQ_TYPE_STRQ         = 0x2,
 622 };
 623
 624 enum {
 625         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 626         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 627 };
 628
 629 enum {
 630         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 631         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 632         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 633         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 634         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 635 };
 636
 637 enum {
 638         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 639         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 640         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 641         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 642         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 643         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 644 };
 645
 646 enum {
 647         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 648         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 649 };
 650
 651 enum {
 652         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 653         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 654         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 655 };
 656
 657 enum {
 658         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 659         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 660 };
 661
 662 struct mlx5_ifc_cmd_hca_cap_bits {
 663         u8         reserved_at_0[0x80];
 664
 665         u8         log_max_srq_sz[0x8];
 666         u8         log_max_qp_sz[0x8];
 667         u8         reserved_at_90[0xb];
 668         u8         log_max_qp[0x5];
 669
 670         u8         reserved_at_a0[0xb];
 671         u8         log_max_srq[0x5];
 672         u8         reserved_at_b0[0x10];
 673
 674         u8         reserved_at_c0[0x8];
 675         u8         log_max_cq_sz[0x8];
 676         u8         reserved_at_d0[0xb];
 677         u8         log_max_cq[0x5];
 678
 679         u8         log_max_eq_sz[0x8];
 680         u8         reserved_at_e8[0x2];
 681         u8         log_max_mkey[0x6];
 682         u8         reserved_at_f0[0xc];
 683         u8         log_max_eq[0x4];
 684
 685         u8         max_indirection[0x8];
 686         u8         reserved_at_108[0x1];
 687         u8         log_max_mrw_sz[0x7];
 688         u8         reserved_at_110[0x2];
 689         u8         log_max_bsf_list_size[0x6];
 690         u8         reserved_at_118[0x2];
 691         u8         log_max_klm_list_size[0x6];
 692
 693         u8         reserved_at_120[0xa];
 694         u8         log_max_ra_req_dc[0x6];
 695         u8         reserved_at_130[0xa];
 696         u8         log_max_ra_res_dc[0x6];
 697
 698         u8         reserved_at_140[0xa];
 699         u8         log_max_ra_req_qp[0x6];
 700         u8         reserved_at_150[0xa];
 701         u8         log_max_ra_res_qp[0x6];
 702
 703         u8         pad_cap[0x1];
 704         u8         cc_query_allowed[0x1];
 705         u8         cc_modify_allowed[0x1];
 706         u8         reserved_at_163[0xd];
 707         u8         gid_table_size[0x10];
 708
 709         u8         out_of_seq_cnt[0x1];
 710         u8         vport_counters[0x1];
 711         u8         reserved_at_182[0x4];
 712         u8         max_qp_cnt[0xa];
 713         u8         pkey_table_size[0x10];
 714
 715         u8         vport_group_manager[0x1];
 716         u8         vhca_group_manager[0x1];
 717         u8         ib_virt[0x1];
 718         u8         eth_virt[0x1];
 719         u8         reserved_at_1a4[0x1];
 720         u8         ets[0x1];
 721         u8         nic_flow_table[0x1];
 722         u8         eswitch_flow_table[0x1];
 723         u8         early_vf_enable;
 724         u8         reserved_at_1a8[0x2];
 725         u8         local_ca_ack_delay[0x5];
 726         u8         reserved_at_1af[0x6];
 727         u8         port_type[0x2];
 728         u8         num_ports[0x8];
 729
 730         u8         reserved_at_1bf[0x3];
 731         u8         log_max_msg[0x5];
 732         u8         reserved_at_1c7[0x18];
 733
 734         u8         stat_rate_support[0x10];
 735         u8         reserved_at_1ef[0xc];
 736         u8         cqe_version[0x4];
 737
 738         u8         compact_address_vector[0x1];
 739         u8         reserved_at_200[0x3];
 740         u8         ipoib_basic_offloads[0x1];
 741         u8         reserved_at_204[0xa];
 742         u8         drain_sigerr[0x1];
 743         u8         cmdif_checksum[0x2];
 744         u8         sigerr_cqe[0x1];
 745         u8         reserved_at_212[0x1];
 746         u8         wq_signature[0x1];
 747         u8         sctr_data_cqe[0x1];
 748         u8         reserved_at_215[0x1];
 749         u8         sho[0x1];
 750         u8         tph[0x1];
 751         u8         rf[0x1];
 752         u8         dct[0x1];
 753         u8         reserved_at_21a[0x1];
 754         u8         eth_net_offloads[0x1];
 755         u8         roce[0x1];
 756         u8         atomic[0x1];
 757         u8         reserved_at_21e[0x1];
 758
 759         u8         cq_oi[0x1];
 760         u8         cq_resize[0x1];
 761         u8         cq_moderation[0x1];
 762         u8         reserved_at_222[0x3];
 763         u8         cq_eq_remap[0x1];
 764         u8         pg[0x1];
 765         u8         block_lb_mc[0x1];
 766         u8         reserved_at_228[0x1];
 767         u8         scqe_break_moderation[0x1];
 768         u8         reserved_at_22a[0x1];
 769         u8         cd[0x1];
 770         u8         reserved_at_22c[0x1];
 771         u8         apm[0x1];
 772         u8         reserved_at_22e[0x7];
 773         u8         qkv[0x1];
 774         u8         pkv[0x1];
 775         u8         reserved_at_237[0x4];
 776         u8         xrc[0x1];
 777         u8         ud[0x1];
 778         u8         uc[0x1];
 779         u8         rc[0x1];
 780
 781         u8         reserved_at_23f[0xa];
 782         u8         uar_sz[0x6];
 783         u8         reserved_at_24f[0x8];
 784         u8         log_pg_sz[0x8];
 785
 786         u8         bf[0x1];
 787         u8         reserved_at_260[0x1];
 788         u8         pad_tx_eth_packet[0x1];
 789         u8         reserved_at_262[0x8];
 790         u8         log_bf_reg_size[0x5];
 791         u8         reserved_at_26f[0x10];
 792
 793         u8         reserved_at_27f[0x10];
 794         u8         max_wqe_sz_sq[0x10];
 795
 796         u8         reserved_at_29f[0x10];
 797         u8         max_wqe_sz_rq[0x10];
 798
 799         u8         reserved_at_2bf[0x10];
 800         u8         max_wqe_sz_sq_dc[0x10];
 801
 802         u8         reserved_at_2df[0x7];
 803         u8         max_qp_mcg[0x19];
 804
 805         u8         reserved_at_2ff[0x18];
 806         u8         log_max_mcg[0x8];
 807
 808         u8         reserved_at_31f[0x3];
 809         u8         log_max_transport_domain[0x5];
 810         u8         reserved_at_327[0x3];
 811         u8         log_max_pd[0x5];
 812         u8         reserved_at_32f[0xb];
 813         u8         log_max_xrcd[0x5];
 814
 815         u8         reserved_at_33f[0x20];
 816
 817         u8         reserved_at_35f[0x3];
 818         u8         log_max_rq[0x5];
 819         u8         reserved_at_367[0x3];
 820         u8         log_max_sq[0x5];
 821         u8         reserved_at_36f[0x3];
 822         u8         log_max_tir[0x5];
 823         u8         reserved_at_377[0x3];
 824         u8         log_max_tis[0x5];
 825
 826         u8         basic_cyclic_rcv_wqe[0x1];
 827         u8         reserved_at_380[0x2];
 828         u8         log_max_rmp[0x5];
 829         u8         reserved_at_387[0x3];
 830         u8         log_max_rqt[0x5];
 831         u8         reserved_at_38f[0x3];
 832         u8         log_max_rqt_size[0x5];
 833         u8         reserved_at_397[0x3];
 834         u8         log_max_tis_per_sq[0x5];
 835
 836         u8         reserved_at_39f[0x3];
 837         u8         log_max_stride_sz_rq[0x5];
 838         u8         reserved_at_3a7[0x3];
 839         u8         log_min_stride_sz_rq[0x5];
 840         u8         reserved_at_3af[0x3];
 841         u8         log_max_stride_sz_sq[0x5];
 842         u8         reserved_at_3b7[0x3];
 843         u8         log_min_stride_sz_sq[0x5];
 844
 845         u8         reserved_at_3bf[0x1b];
 846         u8         log_max_wq_sz[0x5];
 847
 848         u8         nic_vport_change_event[0x1];
 849         u8         reserved_at_3e0[0xa];
 850         u8         log_max_vlan_list[0x5];
 851         u8         reserved_at_3ef[0x3];
 852         u8         log_max_current_mc_list[0x5];
 853         u8         reserved_at_3f7[0x3];
 854         u8         log_max_current_uc_list[0x5];
 855
 856         u8         reserved_at_3ff[0x80];
 857
 858         u8         reserved_at_47f[0x3];
 859         u8         log_max_l2_table[0x5];
 860         u8         reserved_at_487[0x8];
 861         u8         log_uar_page_sz[0x10];
 862
 863         u8         reserved_at_49f[0x20];
 864         u8         device_frequency_mhz[0x20];
 865         u8         device_frequency_khz[0x20];
 866         u8         reserved_at_4ff[0x5f];
 867         u8         cqe_zip[0x1];
 868
 869         u8         cqe_zip_timeout[0x10];
 870         u8         cqe_zip_max_num[0x10];
 871
 872         u8         reserved_at_57f[0x220];
 873 };
 874
 875 enum mlx5_flow_destination_type {
 876         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
 877         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
 878         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
 879 };
 880
 881 struct mlx5_ifc_dest_format_struct_bits {
 882         u8         destination_type[0x8];
 883         u8         destination_id[0x18];
 884
 885         u8         reserved_at_20[0x20];
 886 };
 887
 888 struct mlx5_ifc_fte_match_param_bits {
 889         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
 890
 891         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
 892
 893         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 894
 895         u8         reserved_at_600[0xa00];
 896 };
 897
 898 enum {
 899         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
 900         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
 901         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
 902         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
 903         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
 904 };
 905
 906 struct mlx5_ifc_rx_hash_field_select_bits {
 907         u8         l3_prot_type[0x1];
 908         u8         l4_prot_type[0x1];
 909         u8         selected_fields[0x1e];
 910 };
 911
 912 enum {
 913         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
 914         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
 915 };
 916
 917 enum {
 918         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
 919         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
 920 };
 921
 922 struct mlx5_ifc_wq_bits {
 923         u8         wq_type[0x4];
 924         u8         wq_signature[0x1];
 925         u8         end_padding_mode[0x2];
 926         u8         cd_slave[0x1];
 927         u8         reserved_at_8[0x18];
 928
 929         u8         hds_skip_first_sge[0x1];
 930         u8         log2_hds_buf_size[0x3];
 931         u8         reserved_at_24[0x7];
 932         u8         page_offset[0x5];
 933         u8         lwm[0x10];
 934
 935         u8         reserved_at_40[0x8];
 936         u8         pd[0x18];
 937
 938         u8         reserved_at_60[0x8];
 939         u8         uar_page[0x18];
 940
 941         u8         dbr_addr[0x40];
 942
 943         u8         hw_counter[0x20];
 944
 945         u8         sw_counter[0x20];
 946
 947         u8         reserved_at_100[0xc];
 948         u8         log_wq_stride[0x4];
 949         u8         reserved_at_110[0x3];
 950         u8         log_wq_pg_sz[0x5];
 951         u8         reserved_at_118[0x3];
 952         u8         log_wq_sz[0x5];
 953
 954         u8         reserved_at_120[0x4e0];
 955
 956         struct mlx5_ifc_cmd_pas_bits pas[0];
 957 };
 958
 959 struct mlx5_ifc_rq_num_bits {
 960         u8         reserved_at_0[0x8];
 961         u8         rq_num[0x18];
 962 };
 963
 964 struct mlx5_ifc_mac_address_layout_bits {
 965         u8         reserved_at_0[0x10];
 966         u8         mac_addr_47_32[0x10];
 967
 968         u8         mac_addr_31_0[0x20];
 969 };
 970
 971 struct mlx5_ifc_vlan_layout_bits {
 972         u8         reserved_at_0[0x14];
 973         u8         vlan[0x0c];
 974
 975         u8         reserved_at_20[0x20];
 976 };
 977
 978 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
 979         u8         reserved_at_0[0xa0];
 980
 981         u8         min_time_between_cnps[0x20];
 982
 983         u8         reserved_at_c0[0x12];
 984         u8         cnp_dscp[0x6];
 985         u8         reserved_at_d8[0x5];
 986         u8         cnp_802p_prio[0x3];
 987
 988         u8         reserved_at_e0[0x720];
 989 };
 990
 991 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
 992         u8         reserved_at_0[0x60];
 993
 994         u8         reserved_at_60[0x4];
 995         u8         clamp_tgt_rate[0x1];
 996         u8         reserved_at_65[0x3];
 997         u8         clamp_tgt_rate_after_time_inc[0x1];
 998         u8         reserved_at_69[0x17];
 999
1000         u8         reserved_at_80[0x20];
1001
1002         u8         rpg_time_reset[0x20];
1003
1004         u8         rpg_byte_reset[0x20];
1005
1006         u8         rpg_threshold[0x20];
1007
1008         u8         rpg_max_rate[0x20];
1009
1010         u8         rpg_ai_rate[0x20];
1011
1012         u8         rpg_hai_rate[0x20];
1013
1014         u8         rpg_gd[0x20];
1015
1016         u8         rpg_min_dec_fac[0x20];
1017
1018         u8         rpg_min_rate[0x20];
1019
1020         u8         reserved_at_1c0[0xe0];
1021
1022         u8         rate_to_set_on_first_cnp[0x20];
1023
1024         u8         dce_tcp_g[0x20];
1025
1026         u8         dce_tcp_rtt[0x20];
1027
1028         u8         rate_reduce_monitor_period[0x20];
1029
1030         u8         reserved_at_320[0x20];
1031
1032         u8         initial_alpha_value[0x20];
1033
1034         u8         reserved_at_360[0x4a0];
1035 };
1036
1037 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1038         u8         reserved_at_0[0x80];
1039
1040         u8         rppp_max_rps[0x20];
1041
1042         u8         rpg_time_reset[0x20];
1043
1044         u8         rpg_byte_reset[0x20];
1045
1046         u8         rpg_threshold[0x20];
1047
1048         u8         rpg_max_rate[0x20];
1049
1050         u8         rpg_ai_rate[0x20];
1051
1052         u8         rpg_hai_rate[0x20];
1053
1054         u8         rpg_gd[0x20];
1055
1056         u8         rpg_min_dec_fac[0x20];
1057
1058         u8         rpg_min_rate[0x20];
1059
1060         u8         reserved_at_1c0[0x640];
1061 };
1062
1063 enum {
1064         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1065         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1066         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1067 };
1068
1069 struct mlx5_ifc_resize_field_select_bits {
1070         u8         resize_field_select[0x20];
1071 };
1072
1073 enum {
1074         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1075         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1076         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1077         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1078 };
1079
1080 struct mlx5_ifc_modify_field_select_bits {
1081         u8         modify_field_select[0x20];
1082 };
1083
1084 struct mlx5_ifc_field_select_r_roce_np_bits {
1085         u8         field_select_r_roce_np[0x20];
1086 };
1087
1088 struct mlx5_ifc_field_select_r_roce_rp_bits {
1089         u8         field_select_r_roce_rp[0x20];
1090 };
1091
1092 enum {
1093         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1094         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1095         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1096         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1097         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1098         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1099         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1100         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1101         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1102         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1103 };
1104
1105 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1106         u8         field_select_8021qaurp[0x20];
1107 };
1108
1109 struct mlx5_ifc_phys_layer_cntrs_bits {
1110         u8         time_since_last_clear_high[0x20];
1111
1112         u8         time_since_last_clear_low[0x20];
1113
1114         u8         symbol_errors_high[0x20];
1115
1116         u8         symbol_errors_low[0x20];
1117
1118         u8         sync_headers_errors_high[0x20];
1119
1120         u8         sync_headers_errors_low[0x20];
1121
1122         u8         edpl_bip_errors_lane0_high[0x20];
1123
1124         u8         edpl_bip_errors_lane0_low[0x20];
1125
1126         u8         edpl_bip_errors_lane1_high[0x20];
1127
1128         u8         edpl_bip_errors_lane1_low[0x20];
1129
1130         u8         edpl_bip_errors_lane2_high[0x20];
1131
1132         u8         edpl_bip_errors_lane2_low[0x20];
1133
1134         u8         edpl_bip_errors_lane3_high[0x20];
1135
1136         u8         edpl_bip_errors_lane3_low[0x20];
1137
1138         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1139
1140         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1141
1142         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1143
1144         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1145
1146         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1147
1148         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1149
1150         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1151
1152         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1153
1154         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1155
1156         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1157
1158         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1159
1160         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1161
1162         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1163
1164         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1165
1166         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1167
1168         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1169
1170         u8         rs_fec_corrected_blocks_high[0x20];
1171
1172         u8         rs_fec_corrected_blocks_low[0x20];
1173
1174         u8         rs_fec_uncorrectable_blocks_high[0x20];
1175
1176         u8         rs_fec_uncorrectable_blocks_low[0x20];
1177
1178         u8         rs_fec_no_errors_blocks_high[0x20];
1179
1180         u8         rs_fec_no_errors_blocks_low[0x20];
1181
1182         u8         rs_fec_single_error_blocks_high[0x20];
1183
1184         u8         rs_fec_single_error_blocks_low[0x20];
1185
1186         u8         rs_fec_corrected_symbols_total_high[0x20];
1187
1188         u8         rs_fec_corrected_symbols_total_low[0x20];
1189
1190         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1191
1192         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1193
1194         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1195
1196         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1197
1198         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1199
1200         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1201
1202         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1203
1204         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1205
1206         u8         link_down_events[0x20];
1207
1208         u8         successful_recovery_events[0x20];
1209
1210         u8         reserved_at_640[0x180];
1211 };
1212
1213 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1214         u8         symbol_error_counter[0x10];
1215
1216         u8         link_error_recovery_counter[0x8];
1217
1218         u8         link_downed_counter[0x8];
1219
1220         u8         port_rcv_errors[0x10];
1221
1222         u8         port_rcv_remote_physical_errors[0x10];
1223
1224         u8         port_rcv_switch_relay_errors[0x10];
1225
1226         u8         port_xmit_discards[0x10];
1227
1228         u8         port_xmit_constraint_errors[0x8];
1229
1230         u8         port_rcv_constraint_errors[0x8];
1231
1232         u8         reserved_at_70[0x8];
1233
1234         u8         link_overrun_errors[0x8];
1235
1236         u8         reserved_at_80[0x10];
1237
1238         u8         vl_15_dropped[0x10];
1239
1240         u8         reserved_at_a0[0xa0];
1241 };
1242
1243 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1244         u8         transmit_queue_high[0x20];
1245
1246         u8         transmit_queue_low[0x20];
1247
1248         u8         reserved_at_40[0x780];
1249 };
1250
1251 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1252         u8         rx_octets_high[0x20];
1253
1254         u8         rx_octets_low[0x20];
1255
1256         u8         reserved_at_40[0xc0];
1257
1258         u8         rx_frames_high[0x20];
1259
1260         u8         rx_frames_low[0x20];
1261
1262         u8         tx_octets_high[0x20];
1263
1264         u8         tx_octets_low[0x20];
1265
1266         u8         reserved_at_180[0xc0];
1267
1268         u8         tx_frames_high[0x20];
1269
1270         u8         tx_frames_low[0x20];
1271
1272         u8         rx_pause_high[0x20];
1273
1274         u8         rx_pause_low[0x20];
1275
1276         u8         rx_pause_duration_high[0x20];
1277
1278         u8         rx_pause_duration_low[0x20];
1279
1280         u8         tx_pause_high[0x20];
1281
1282         u8         tx_pause_low[0x20];
1283
1284         u8         tx_pause_duration_high[0x20];
1285
1286         u8         tx_pause_duration_low[0x20];
1287
1288         u8         rx_pause_transition_high[0x20];
1289
1290         u8         rx_pause_transition_low[0x20];
1291
1292         u8         reserved_at_3c0[0x400];
1293 };
1294
1295 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1296         u8         port_transmit_wait_high[0x20];
1297
1298         u8         port_transmit_wait_low[0x20];
1299
1300         u8         reserved_at_40[0x780];
1301 };
1302
1303 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1304         u8         dot3stats_alignment_errors_high[0x20];
1305
1306         u8         dot3stats_alignment_errors_low[0x20];
1307
1308         u8         dot3stats_fcs_errors_high[0x20];
1309
1310         u8         dot3stats_fcs_errors_low[0x20];
1311
1312         u8         dot3stats_single_collision_frames_high[0x20];
1313
1314         u8         dot3stats_single_collision_frames_low[0x20];
1315
1316         u8         dot3stats_multiple_collision_frames_high[0x20];
1317
1318         u8         dot3stats_multiple_collision_frames_low[0x20];
1319
1320         u8         dot3stats_sqe_test_errors_high[0x20];
1321
1322         u8         dot3stats_sqe_test_errors_low[0x20];
1323
1324         u8         dot3stats_deferred_transmissions_high[0x20];
1325
1326         u8         dot3stats_deferred_transmissions_low[0x20];
1327
1328         u8         dot3stats_late_collisions_high[0x20];
1329
1330         u8         dot3stats_late_collisions_low[0x20];
1331
1332         u8         dot3stats_excessive_collisions_high[0x20];
1333
1334         u8         dot3stats_excessive_collisions_low[0x20];
1335
1336         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1337
1338         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1339
1340         u8         dot3stats_carrier_sense_errors_high[0x20];
1341
1342         u8         dot3stats_carrier_sense_errors_low[0x20];
1343
1344         u8         dot3stats_frame_too_longs_high[0x20];
1345
1346         u8         dot3stats_frame_too_longs_low[0x20];
1347
1348         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1349
1350         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1351
1352         u8         dot3stats_symbol_errors_high[0x20];
1353
1354         u8         dot3stats_symbol_errors_low[0x20];
1355
1356         u8         dot3control_in_unknown_opcodes_high[0x20];
1357
1358         u8         dot3control_in_unknown_opcodes_low[0x20];
1359
1360         u8         dot3in_pause_frames_high[0x20];
1361
1362         u8         dot3in_pause_frames_low[0x20];
1363
1364         u8         dot3out_pause_frames_high[0x20];
1365
1366         u8         dot3out_pause_frames_low[0x20];
1367
1368         u8         reserved_at_400[0x3c0];
1369 };
1370
1371 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1372         u8         ether_stats_drop_events_high[0x20];
1373
1374         u8         ether_stats_drop_events_low[0x20];
1375
1376         u8         ether_stats_octets_high[0x20];
1377
1378         u8         ether_stats_octets_low[0x20];
1379
1380         u8         ether_stats_pkts_high[0x20];
1381
1382         u8         ether_stats_pkts_low[0x20];
1383
1384         u8         ether_stats_broadcast_pkts_high[0x20];
1385
1386         u8         ether_stats_broadcast_pkts_low[0x20];
1387
1388         u8         ether_stats_multicast_pkts_high[0x20];
1389
1390         u8         ether_stats_multicast_pkts_low[0x20];
1391
1392         u8         ether_stats_crc_align_errors_high[0x20];
1393
1394         u8         ether_stats_crc_align_errors_low[0x20];
1395
1396         u8         ether_stats_undersize_pkts_high[0x20];
1397
1398         u8         ether_stats_undersize_pkts_low[0x20];
1399
1400         u8         ether_stats_oversize_pkts_high[0x20];
1401
1402         u8         ether_stats_oversize_pkts_low[0x20];
1403
1404         u8         ether_stats_fragments_high[0x20];
1405
1406         u8         ether_stats_fragments_low[0x20];
1407
1408         u8         ether_stats_jabbers_high[0x20];
1409
1410         u8         ether_stats_jabbers_low[0x20];
1411
1412         u8         ether_stats_collisions_high[0x20];
1413
1414         u8         ether_stats_collisions_low[0x20];
1415
1416         u8         ether_stats_pkts64octets_high[0x20];
1417
1418         u8         ether_stats_pkts64octets_low[0x20];
1419
1420         u8         ether_stats_pkts65to127octets_high[0x20];
1421
1422         u8         ether_stats_pkts65to127octets_low[0x20];
1423
1424         u8         ether_stats_pkts128to255octets_high[0x20];
1425
1426         u8         ether_stats_pkts128to255octets_low[0x20];
1427
1428         u8         ether_stats_pkts256to511octets_high[0x20];
1429
1430         u8         ether_stats_pkts256to511octets_low[0x20];
1431
1432         u8         ether_stats_pkts512to1023octets_high[0x20];
1433
1434         u8         ether_stats_pkts512to1023octets_low[0x20];
1435
1436         u8         ether_stats_pkts1024to1518octets_high[0x20];
1437
1438         u8         ether_stats_pkts1024to1518octets_low[0x20];
1439
1440         u8         ether_stats_pkts1519to2047octets_high[0x20];
1441
1442         u8         ether_stats_pkts1519to2047octets_low[0x20];
1443
1444         u8         ether_stats_pkts2048to4095octets_high[0x20];
1445
1446         u8         ether_stats_pkts2048to4095octets_low[0x20];
1447
1448         u8         ether_stats_pkts4096to8191octets_high[0x20];
1449
1450         u8         ether_stats_pkts4096to8191octets_low[0x20];
1451
1452         u8         ether_stats_pkts8192to10239octets_high[0x20];
1453
1454         u8         ether_stats_pkts8192to10239octets_low[0x20];
1455
1456         u8         reserved_at_540[0x280];
1457 };
1458
1459 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1460         u8         if_in_octets_high[0x20];
1461
1462         u8         if_in_octets_low[0x20];
1463
1464         u8         if_in_ucast_pkts_high[0x20];
1465
1466         u8         if_in_ucast_pkts_low[0x20];
1467
1468         u8         if_in_discards_high[0x20];
1469
1470         u8         if_in_discards_low[0x20];
1471
1472         u8         if_in_errors_high[0x20];
1473
1474         u8         if_in_errors_low[0x20];
1475
1476         u8         if_in_unknown_protos_high[0x20];
1477
1478         u8         if_in_unknown_protos_low[0x20];
1479
1480         u8         if_out_octets_high[0x20];
1481
1482         u8         if_out_octets_low[0x20];
1483
1484         u8         if_out_ucast_pkts_high[0x20];
1485
1486         u8         if_out_ucast_pkts_low[0x20];
1487
1488         u8         if_out_discards_high[0x20];
1489
1490         u8         if_out_discards_low[0x20];
1491
1492         u8         if_out_errors_high[0x20];
1493
1494         u8         if_out_errors_low[0x20];
1495
1496         u8         if_in_multicast_pkts_high[0x20];
1497
1498         u8         if_in_multicast_pkts_low[0x20];
1499
1500         u8         if_in_broadcast_pkts_high[0x20];
1501
1502         u8         if_in_broadcast_pkts_low[0x20];
1503
1504         u8         if_out_multicast_pkts_high[0x20];
1505
1506         u8         if_out_multicast_pkts_low[0x20];
1507
1508         u8         if_out_broadcast_pkts_high[0x20];
1509
1510         u8         if_out_broadcast_pkts_low[0x20];
1511
1512         u8         reserved_at_340[0x480];
1513 };
1514
1515 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1516         u8         a_frames_transmitted_ok_high[0x20];
1517
1518         u8         a_frames_transmitted_ok_low[0x20];
1519
1520         u8         a_frames_received_ok_high[0x20];
1521
1522         u8         a_frames_received_ok_low[0x20];
1523
1524         u8         a_frame_check_sequence_errors_high[0x20];
1525
1526         u8         a_frame_check_sequence_errors_low[0x20];
1527
1528         u8         a_alignment_errors_high[0x20];
1529
1530         u8         a_alignment_errors_low[0x20];
1531
1532         u8         a_octets_transmitted_ok_high[0x20];
1533
1534         u8         a_octets_transmitted_ok_low[0x20];
1535
1536         u8         a_octets_received_ok_high[0x20];
1537
1538         u8         a_octets_received_ok_low[0x20];
1539
1540         u8         a_multicast_frames_xmitted_ok_high[0x20];
1541
1542         u8         a_multicast_frames_xmitted_ok_low[0x20];
1543
1544         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1545
1546         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1547
1548         u8         a_multicast_frames_received_ok_high[0x20];
1549
1550         u8         a_multicast_frames_received_ok_low[0x20];
1551
1552         u8         a_broadcast_frames_received_ok_high[0x20];
1553
1554         u8         a_broadcast_frames_received_ok_low[0x20];
1555
1556         u8         a_in_range_length_errors_high[0x20];
1557
1558         u8         a_in_range_length_errors_low[0x20];
1559
1560         u8         a_out_of_range_length_field_high[0x20];
1561
1562         u8         a_out_of_range_length_field_low[0x20];
1563
1564         u8         a_frame_too_long_errors_high[0x20];
1565
1566         u8         a_frame_too_long_errors_low[0x20];
1567
1568         u8         a_symbol_error_during_carrier_high[0x20];
1569
1570         u8         a_symbol_error_during_carrier_low[0x20];
1571
1572         u8         a_mac_control_frames_transmitted_high[0x20];
1573
1574         u8         a_mac_control_frames_transmitted_low[0x20];
1575
1576         u8         a_mac_control_frames_received_high[0x20];
1577
1578         u8         a_mac_control_frames_received_low[0x20];
1579
1580         u8         a_unsupported_opcodes_received_high[0x20];
1581
1582         u8         a_unsupported_opcodes_received_low[0x20];
1583
1584         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1585
1586         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1587
1588         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1589
1590         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1591
1592         u8         reserved_at_4c0[0x300];
1593 };
1594
1595 struct mlx5_ifc_cmd_inter_comp_event_bits {
1596         u8         command_completion_vector[0x20];
1597
1598         u8         reserved_at_20[0xc0];
1599 };
1600
1601 struct mlx5_ifc_stall_vl_event_bits {
1602         u8         reserved_at_0[0x18];
1603         u8         port_num[0x1];
1604         u8         reserved_at_19[0x3];
1605         u8         vl[0x4];
1606
1607         u8         reserved_at_20[0xa0];
1608 };
1609
1610 struct mlx5_ifc_db_bf_congestion_event_bits {
1611         u8         event_subtype[0x8];
1612         u8         reserved_at_8[0x8];
1613         u8         congestion_level[0x8];
1614         u8         reserved_at_18[0x8];
1615
1616         u8         reserved_at_20[0xa0];
1617 };
1618
1619 struct mlx5_ifc_gpio_event_bits {
1620         u8         reserved_at_0[0x60];
1621
1622         u8         gpio_event_hi[0x20];
1623
1624         u8         gpio_event_lo[0x20];
1625
1626         u8         reserved_at_a0[0x40];
1627 };
1628
1629 struct mlx5_ifc_port_state_change_event_bits {
1630         u8         reserved_at_0[0x40];
1631
1632         u8         port_num[0x4];
1633         u8         reserved_at_44[0x1c];
1634
1635         u8         reserved_at_60[0x80];
1636 };
1637
1638 struct mlx5_ifc_dropped_packet_logged_bits {
1639         u8         reserved_at_0[0xe0];
1640 };
1641
1642 enum {
1643         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1644         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1645 };
1646
1647 struct mlx5_ifc_cq_error_bits {
1648         u8         reserved_at_0[0x8];
1649         u8         cqn[0x18];
1650
1651         u8         reserved_at_20[0x20];
1652
1653         u8         reserved_at_40[0x18];
1654         u8         syndrome[0x8];
1655
1656         u8         reserved_at_60[0x80];
1657 };
1658
1659 struct mlx5_ifc_rdma_page_fault_event_bits {
1660         u8         bytes_committed[0x20];
1661
1662         u8         r_key[0x20];
1663
1664         u8         reserved_at_40[0x10];
1665         u8         packet_len[0x10];
1666
1667         u8         rdma_op_len[0x20];
1668
1669         u8         rdma_va[0x40];
1670
1671         u8         reserved_at_c0[0x5];
1672         u8         rdma[0x1];
1673         u8         write[0x1];
1674         u8         requestor[0x1];
1675         u8         qp_number[0x18];
1676 };
1677
1678 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1679         u8         bytes_committed[0x20];
1680
1681         u8         reserved_at_20[0x10];
1682         u8         wqe_index[0x10];
1683
1684         u8         reserved_at_40[0x10];
1685         u8         len[0x10];
1686
1687         u8         reserved_at_60[0x60];
1688
1689         u8         reserved_at_c0[0x5];
1690         u8         rdma[0x1];
1691         u8         write_read[0x1];
1692         u8         requestor[0x1];
1693         u8         qpn[0x18];
1694 };
1695
1696 struct mlx5_ifc_qp_events_bits {
1697         u8         reserved_at_0[0xa0];
1698
1699         u8         type[0x8];
1700         u8         reserved_at_a8[0x18];
1701
1702         u8         reserved_at_c0[0x8];
1703         u8         qpn_rqn_sqn[0x18];
1704 };
1705
1706 struct mlx5_ifc_dct_events_bits {
1707         u8         reserved_at_0[0xc0];
1708
1709         u8         reserved_at_c0[0x8];
1710         u8         dct_number[0x18];
1711 };
1712
1713 struct mlx5_ifc_comp_event_bits {
1714         u8         reserved_at_0[0xc0];
1715
1716         u8         reserved_at_c0[0x8];
1717         u8         cq_number[0x18];
1718 };
1719
1720 enum {
1721         MLX5_QPC_STATE_RST        = 0x0,
1722         MLX5_QPC_STATE_INIT       = 0x1,
1723         MLX5_QPC_STATE_RTR        = 0x2,
1724         MLX5_QPC_STATE_RTS        = 0x3,
1725         MLX5_QPC_STATE_SQER       = 0x4,
1726         MLX5_QPC_STATE_ERR        = 0x6,
1727         MLX5_QPC_STATE_SQD        = 0x7,
1728         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1729 };
1730
1731 enum {
1732         MLX5_QPC_ST_RC            = 0x0,
1733         MLX5_QPC_ST_UC            = 0x1,
1734         MLX5_QPC_ST_UD            = 0x2,
1735         MLX5_QPC_ST_XRC           = 0x3,
1736         MLX5_QPC_ST_DCI           = 0x5,
1737         MLX5_QPC_ST_QP0           = 0x7,
1738         MLX5_QPC_ST_QP1           = 0x8,
1739         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1740         MLX5_QPC_ST_REG_UMR       = 0xc,
1741 };
1742
1743 enum {
1744         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1745         MLX5_QPC_PM_STATE_REARM     = 0x1,
1746         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1747         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1748 };
1749
1750 enum {
1751         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1752         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1753 };
1754
1755 enum {
1756         MLX5_QPC_MTU_256_BYTES        = 0x1,
1757         MLX5_QPC_MTU_512_BYTES        = 0x2,
1758         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1759         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1760         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1761         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1762 };
1763
1764 enum {
1765         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1766         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1767         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1768         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1769         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1770         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1771         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1772         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1773 };
1774
1775 enum {
1776         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1777         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1778         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1779 };
1780
1781 enum {
1782         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1783         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1784         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1785 };
1786
1787 struct mlx5_ifc_qpc_bits {
1788         u8         state[0x4];
1789         u8         reserved_at_4[0x4];
1790         u8         st[0x8];
1791         u8         reserved_at_10[0x3];
1792         u8         pm_state[0x2];
1793         u8         reserved_at_15[0x7];
1794         u8         end_padding_mode[0x2];
1795         u8         reserved_at_1e[0x2];
1796
1797         u8         wq_signature[0x1];
1798         u8         block_lb_mc[0x1];
1799         u8         atomic_like_write_en[0x1];
1800         u8         latency_sensitive[0x1];
1801         u8         reserved_at_24[0x1];
1802         u8         drain_sigerr[0x1];
1803         u8         reserved_at_26[0x2];
1804         u8         pd[0x18];
1805
1806         u8         mtu[0x3];
1807         u8         log_msg_max[0x5];
1808         u8         reserved_at_48[0x1];
1809         u8         log_rq_size[0x4];
1810         u8         log_rq_stride[0x3];
1811         u8         no_sq[0x1];
1812         u8         log_sq_size[0x4];
1813         u8         reserved_at_55[0x6];
1814         u8         rlky[0x1];
1815         u8         ulp_stateless_offload_mode[0x4];
1816
1817         u8         counter_set_id[0x8];
1818         u8         uar_page[0x18];
1819
1820         u8         reserved_at_80[0x8];
1821         u8         user_index[0x18];
1822
1823         u8         reserved_at_a0[0x3];
1824         u8         log_page_size[0x5];
1825         u8         remote_qpn[0x18];
1826
1827         struct mlx5_ifc_ads_bits primary_address_path;
1828
1829         struct mlx5_ifc_ads_bits secondary_address_path;
1830
1831         u8         log_ack_req_freq[0x4];
1832         u8         reserved_at_384[0x4];
1833         u8         log_sra_max[0x3];
1834         u8         reserved_at_38b[0x2];
1835         u8         retry_count[0x3];
1836         u8         rnr_retry[0x3];
1837         u8         reserved_at_393[0x1];
1838         u8         fre[0x1];
1839         u8         cur_rnr_retry[0x3];
1840         u8         cur_retry_count[0x3];
1841         u8         reserved_at_39b[0x5];
1842
1843         u8         reserved_at_3a0[0x20];
1844
1845         u8         reserved_at_3c0[0x8];
1846         u8         next_send_psn[0x18];
1847
1848         u8         reserved_at_3e0[0x8];
1849         u8         cqn_snd[0x18];
1850
1851         u8         reserved_at_400[0x40];
1852
1853         u8         reserved_at_440[0x8];
1854         u8         last_acked_psn[0x18];
1855
1856         u8         reserved_at_460[0x8];
1857         u8         ssn[0x18];
1858
1859         u8         reserved_at_480[0x8];
1860         u8         log_rra_max[0x3];
1861         u8         reserved_at_48b[0x1];
1862         u8         atomic_mode[0x4];
1863         u8         rre[0x1];
1864         u8         rwe[0x1];
1865         u8         rae[0x1];
1866         u8         reserved_at_493[0x1];
1867         u8         page_offset[0x6];
1868         u8         reserved_at_49a[0x3];
1869         u8         cd_slave_receive[0x1];
1870         u8         cd_slave_send[0x1];
1871         u8         cd_master[0x1];
1872
1873         u8         reserved_at_4a0[0x3];
1874         u8         min_rnr_nak[0x5];
1875         u8         next_rcv_psn[0x18];
1876
1877         u8         reserved_at_4c0[0x8];
1878         u8         xrcd[0x18];
1879
1880         u8         reserved_at_4e0[0x8];
1881         u8         cqn_rcv[0x18];
1882
1883         u8         dbr_addr[0x40];
1884
1885         u8         q_key[0x20];
1886
1887         u8         reserved_at_560[0x5];
1888         u8         rq_type[0x3];
1889         u8         srqn_rmpn[0x18];
1890
1891         u8         reserved_at_580[0x8];
1892         u8         rmsn[0x18];
1893
1894         u8         hw_sq_wqebb_counter[0x10];
1895         u8         sw_sq_wqebb_counter[0x10];
1896
1897         u8         hw_rq_counter[0x20];
1898
1899         u8         sw_rq_counter[0x20];
1900
1901         u8         reserved_at_600[0x20];
1902
1903         u8         reserved_at_620[0xf];
1904         u8         cgs[0x1];
1905         u8         cs_req[0x8];
1906         u8         cs_res[0x8];
1907
1908         u8         dc_access_key[0x40];
1909
1910         u8         reserved_at_680[0xc0];
1911 };
1912
1913 struct mlx5_ifc_roce_addr_layout_bits {
1914         u8         source_l3_address[16][0x8];
1915
1916         u8         reserved_at_80[0x3];
1917         u8         vlan_valid[0x1];
1918         u8         vlan_id[0xc];
1919         u8         source_mac_47_32[0x10];
1920
1921         u8         source_mac_31_0[0x20];
1922
1923         u8         reserved_at_c0[0x14];
1924         u8         roce_l3_type[0x4];
1925         u8         roce_version[0x8];
1926
1927         u8         reserved_at_e0[0x20];
1928 };
1929
1930 union mlx5_ifc_hca_cap_union_bits {
1931         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1932         struct mlx5_ifc_odp_cap_bits odp_cap;
1933         struct mlx5_ifc_atomic_caps_bits atomic_caps;
1934         struct mlx5_ifc_roce_cap_bits roce_cap;
1935         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1936         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1937         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
1938         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
1939         u8         reserved_at_0[0x8000];
1940 };
1941
1942 enum {
1943         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
1944         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
1945         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
1946 };
1947
1948 struct mlx5_ifc_flow_context_bits {
1949         u8         reserved_at_0[0x20];
1950
1951         u8         group_id[0x20];
1952
1953         u8         reserved_at_40[0x8];
1954         u8         flow_tag[0x18];
1955
1956         u8         reserved_at_60[0x10];
1957         u8         action[0x10];
1958
1959         u8         reserved_at_80[0x8];
1960         u8         destination_list_size[0x18];
1961
1962         u8         reserved_at_a0[0x160];
1963
1964         struct mlx5_ifc_fte_match_param_bits match_value;
1965
1966         u8         reserved_at_1200[0x600];
1967
1968         struct mlx5_ifc_dest_format_struct_bits destination[0];
1969 };
1970
1971 enum {
1972         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
1973         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
1974 };
1975
1976 struct mlx5_ifc_xrc_srqc_bits {
1977         u8         state[0x4];
1978         u8         log_xrc_srq_size[0x4];
1979         u8         reserved_at_8[0x18];
1980
1981         u8         wq_signature[0x1];
1982         u8         cont_srq[0x1];
1983         u8         reserved_at_22[0x1];
1984         u8         rlky[0x1];
1985         u8         basic_cyclic_rcv_wqe[0x1];
1986         u8         log_rq_stride[0x3];
1987         u8         xrcd[0x18];
1988
1989         u8         page_offset[0x6];
1990         u8         reserved_at_46[0x2];
1991         u8         cqn[0x18];
1992
1993         u8         reserved_at_60[0x20];
1994
1995         u8         user_index_equal_xrc_srqn[0x1];
1996         u8         reserved_at_81[0x1];
1997         u8         log_page_size[0x6];
1998         u8         user_index[0x18];
1999
2000         u8         reserved_at_a0[0x20];
2001
2002         u8         reserved_at_c0[0x8];
2003         u8         pd[0x18];
2004
2005         u8         lwm[0x10];
2006         u8         wqe_cnt[0x10];
2007
2008         u8         reserved_at_100[0x40];
2009
2010         u8         db_record_addr_h[0x20];
2011
2012         u8         db_record_addr_l[0x1e];
2013         u8         reserved_at_17e[0x2];
2014
2015         u8         reserved_at_180[0x80];
2016 };
2017
2018 struct mlx5_ifc_traffic_counter_bits {
2019         u8         packets[0x40];
2020
2021         u8         octets[0x40];
2022 };
2023
2024 struct mlx5_ifc_tisc_bits {
2025         u8         reserved_at_0[0xc];
2026         u8         prio[0x4];
2027         u8         reserved_at_10[0x10];
2028
2029         u8         reserved_at_20[0x100];
2030
2031         u8         reserved_at_120[0x8];
2032         u8         transport_domain[0x18];
2033
2034         u8         reserved_at_140[0x3c0];
2035 };
2036
2037 enum {
2038         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2039         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2040 };
2041
2042 enum {
2043         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2044         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2045 };
2046
2047 enum {
2048         MLX5_RX_HASH_FN_NONE           = 0x0,
2049         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2050         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2051 };
2052
2053 enum {
2054         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2055         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2056 };
2057
2058 struct mlx5_ifc_tirc_bits {
2059         u8         reserved_at_0[0x20];
2060
2061         u8         disp_type[0x4];
2062         u8         reserved_at_24[0x1c];
2063
2064         u8         reserved_at_40[0x40];
2065
2066         u8         reserved_at_80[0x4];
2067         u8         lro_timeout_period_usecs[0x10];
2068         u8         lro_enable_mask[0x4];
2069         u8         lro_max_ip_payload_size[0x8];
2070
2071         u8         reserved_at_a0[0x40];
2072
2073         u8         reserved_at_e0[0x8];
2074         u8         inline_rqn[0x18];
2075
2076         u8         rx_hash_symmetric[0x1];
2077         u8         reserved_at_101[0x1];
2078         u8         tunneled_offload_en[0x1];
2079         u8         reserved_at_103[0x5];
2080         u8         indirect_table[0x18];
2081
2082         u8         rx_hash_fn[0x4];
2083         u8         reserved_at_124[0x2];
2084         u8         self_lb_block[0x2];
2085         u8         transport_domain[0x18];
2086
2087         u8         rx_hash_toeplitz_key[10][0x20];
2088
2089         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2090
2091         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2092
2093         u8         reserved_at_2c0[0x4c0];
2094 };
2095
2096 enum {
2097         MLX5_SRQC_STATE_GOOD   = 0x0,
2098         MLX5_SRQC_STATE_ERROR  = 0x1,
2099 };
2100
2101 struct mlx5_ifc_srqc_bits {
2102         u8         state[0x4];
2103         u8         log_srq_size[0x4];
2104         u8         reserved_at_8[0x18];
2105
2106         u8         wq_signature[0x1];
2107         u8         cont_srq[0x1];
2108         u8         reserved_at_22[0x1];
2109         u8         rlky[0x1];
2110         u8         reserved_at_24[0x1];
2111         u8         log_rq_stride[0x3];
2112         u8         xrcd[0x18];
2113
2114         u8         page_offset[0x6];
2115         u8         reserved_at_46[0x2];
2116         u8         cqn[0x18];
2117
2118         u8         reserved_at_60[0x20];
2119
2120         u8         reserved_at_80[0x2];
2121         u8         log_page_size[0x6];
2122         u8         reserved_at_88[0x18];
2123
2124         u8         reserved_at_a0[0x20];
2125
2126         u8         reserved_at_c0[0x8];
2127         u8         pd[0x18];
2128
2129         u8         lwm[0x10];
2130         u8         wqe_cnt[0x10];
2131
2132         u8         reserved_at_100[0x40];
2133
2134         u8         dbr_addr[0x40];
2135
2136         u8         reserved_at_180[0x80];
2137 };
2138
2139 enum {
2140         MLX5_SQC_STATE_RST  = 0x0,
2141         MLX5_SQC_STATE_RDY  = 0x1,
2142         MLX5_SQC_STATE_ERR  = 0x3,
2143 };
2144
2145 struct mlx5_ifc_sqc_bits {
2146         u8         rlky[0x1];
2147         u8         cd_master[0x1];
2148         u8         fre[0x1];
2149         u8         flush_in_error_en[0x1];
2150         u8         reserved_at_4[0x4];
2151         u8         state[0x4];
2152         u8         reserved_at_c[0x14];
2153
2154         u8         reserved_at_20[0x8];
2155         u8         user_index[0x18];
2156
2157         u8         reserved_at_40[0x8];
2158         u8         cqn[0x18];
2159
2160         u8         reserved_at_60[0xa0];
2161
2162         u8         tis_lst_sz[0x10];
2163         u8         reserved_at_110[0x10];
2164
2165         u8         reserved_at_120[0x40];
2166
2167         u8         reserved_at_160[0x8];
2168         u8         tis_num_0[0x18];
2169
2170         struct mlx5_ifc_wq_bits wq;
2171 };
2172
2173 struct mlx5_ifc_rqtc_bits {
2174         u8         reserved_at_0[0xa0];
2175
2176         u8         reserved_at_a0[0x10];
2177         u8         rqt_max_size[0x10];
2178
2179         u8         reserved_at_c0[0x10];
2180         u8         rqt_actual_size[0x10];
2181
2182         u8         reserved_at_e0[0x6a0];
2183
2184         struct mlx5_ifc_rq_num_bits rq_num[0];
2185 };
2186
2187 enum {
2188         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2189         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2190 };
2191
2192 enum {
2193         MLX5_RQC_STATE_RST  = 0x0,
2194         MLX5_RQC_STATE_RDY  = 0x1,
2195         MLX5_RQC_STATE_ERR  = 0x3,
2196 };
2197
2198 struct mlx5_ifc_rqc_bits {
2199         u8         rlky[0x1];
2200         u8         reserved_at_1[0x2];
2201         u8         vsd[0x1];
2202         u8         mem_rq_type[0x4];
2203         u8         state[0x4];
2204         u8         reserved_at_c[0x1];
2205         u8         flush_in_error_en[0x1];
2206         u8         reserved_at_e[0x12];
2207
2208         u8         reserved_at_20[0x8];
2209         u8         user_index[0x18];
2210
2211         u8         reserved_at_40[0x8];
2212         u8         cqn[0x18];
2213
2214         u8         counter_set_id[0x8];
2215         u8         reserved_at_68[0x18];
2216
2217         u8         reserved_at_80[0x8];
2218         u8         rmpn[0x18];
2219
2220         u8         reserved_at_a0[0xe0];
2221
2222         struct mlx5_ifc_wq_bits wq;
2223 };
2224
2225 enum {
2226         MLX5_RMPC_STATE_RDY  = 0x1,
2227         MLX5_RMPC_STATE_ERR  = 0x3,
2228 };
2229
2230 struct mlx5_ifc_rmpc_bits {
2231         u8         reserved_at_0[0x8];
2232         u8         state[0x4];
2233         u8         reserved_at_c[0x14];
2234
2235         u8         basic_cyclic_rcv_wqe[0x1];
2236         u8         reserved_at_21[0x1f];
2237
2238         u8         reserved_at_40[0x140];
2239
2240         struct mlx5_ifc_wq_bits wq;
2241 };
2242
2243 struct mlx5_ifc_nic_vport_context_bits {
2244         u8         reserved_at_0[0x1f];
2245         u8         roce_en[0x1];
2246
2247         u8         arm_change_event[0x1];
2248         u8         reserved_at_21[0x1a];
2249         u8         event_on_mtu[0x1];
2250         u8         event_on_promisc_change[0x1];
2251         u8         event_on_vlan_change[0x1];
2252         u8         event_on_mc_address_change[0x1];
2253         u8         event_on_uc_address_change[0x1];
2254
2255         u8         reserved_at_40[0xf0];
2256
2257         u8         mtu[0x10];
2258
2259         u8         system_image_guid[0x40];
2260         u8         port_guid[0x40];
2261         u8         node_guid[0x40];
2262
2263         u8         reserved_at_200[0x140];
2264         u8         qkey_violation_counter[0x10];
2265         u8         reserved_at_350[0x430];
2266
2267         u8         promisc_uc[0x1];
2268         u8         promisc_mc[0x1];
2269         u8         promisc_all[0x1];
2270         u8         reserved_at_783[0x2];
2271         u8         allowed_list_type[0x3];
2272         u8         reserved_at_788[0xc];
2273         u8         allowed_list_size[0xc];
2274
2275         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2276
2277         u8         reserved_at_7e0[0x20];
2278
2279         u8         current_uc_mac_address[0][0x40];
2280 };
2281
2282 enum {
2283         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2284         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2285         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2286 };
2287
2288 struct mlx5_ifc_mkc_bits {
2289         u8         reserved_at_0[0x1];
2290         u8         free[0x1];
2291         u8         reserved_at_2[0xd];
2292         u8         small_fence_on_rdma_read_response[0x1];
2293         u8         umr_en[0x1];
2294         u8         a[0x1];
2295         u8         rw[0x1];
2296         u8         rr[0x1];
2297         u8         lw[0x1];
2298         u8         lr[0x1];
2299         u8         access_mode[0x2];
2300         u8         reserved_at_18[0x8];
2301
2302         u8         qpn[0x18];
2303         u8         mkey_7_0[0x8];
2304
2305         u8         reserved_at_40[0x20];
2306
2307         u8         length64[0x1];
2308         u8         bsf_en[0x1];
2309         u8         sync_umr[0x1];
2310         u8         reserved_at_63[0x2];
2311         u8         expected_sigerr_count[0x1];
2312         u8         reserved_at_66[0x1];
2313         u8         en_rinval[0x1];
2314         u8         pd[0x18];
2315
2316         u8         start_addr[0x40];
2317
2318         u8         len[0x40];
2319
2320         u8         bsf_octword_size[0x20];
2321
2322         u8         reserved_at_120[0x80];
2323
2324         u8         translations_octword_size[0x20];
2325
2326         u8         reserved_at_1c0[0x1b];
2327         u8         log_page_size[0x5];
2328
2329         u8         reserved_at_1e0[0x20];
2330 };
2331
2332 struct mlx5_ifc_pkey_bits {
2333         u8         reserved_at_0[0x10];
2334         u8         pkey[0x10];
2335 };
2336
2337 struct mlx5_ifc_array128_auto_bits {
2338         u8         array128_auto[16][0x8];
2339 };
2340
2341 struct mlx5_ifc_hca_vport_context_bits {
2342         u8         field_select[0x20];
2343
2344         u8         reserved_at_20[0xe0];
2345
2346         u8         sm_virt_aware[0x1];
2347         u8         has_smi[0x1];
2348         u8         has_raw[0x1];
2349         u8         grh_required[0x1];
2350         u8         reserved_at_104[0xc];
2351         u8         port_physical_state[0x4];
2352         u8         vport_state_policy[0x4];
2353         u8         port_state[0x4];
2354         u8         vport_state[0x4];
2355
2356         u8         reserved_at_120[0x20];
2357
2358         u8         system_image_guid[0x40];
2359
2360         u8         port_guid[0x40];
2361
2362         u8         node_guid[0x40];
2363
2364         u8         cap_mask1[0x20];
2365
2366         u8         cap_mask1_field_select[0x20];
2367
2368         u8         cap_mask2[0x20];
2369
2370         u8         cap_mask2_field_select[0x20];
2371
2372         u8         reserved_at_280[0x80];
2373
2374         u8         lid[0x10];
2375         u8         reserved_at_310[0x4];
2376         u8         init_type_reply[0x4];
2377         u8         lmc[0x3];
2378         u8         subnet_timeout[0x5];
2379
2380         u8         sm_lid[0x10];
2381         u8         sm_sl[0x4];
2382         u8         reserved_at_334[0xc];
2383
2384         u8         qkey_violation_counter[0x10];
2385         u8         pkey_violation_counter[0x10];
2386
2387         u8         reserved_at_360[0xca0];
2388 };
2389
2390 struct mlx5_ifc_esw_vport_context_bits {
2391         u8         reserved_at_0[0x3];
2392         u8         vport_svlan_strip[0x1];
2393         u8         vport_cvlan_strip[0x1];
2394         u8         vport_svlan_insert[0x1];
2395         u8         vport_cvlan_insert[0x2];
2396         u8         reserved_at_8[0x18];
2397
2398         u8         reserved_at_20[0x20];
2399
2400         u8         svlan_cfi[0x1];
2401         u8         svlan_pcp[0x3];
2402         u8         svlan_id[0xc];
2403         u8         cvlan_cfi[0x1];
2404         u8         cvlan_pcp[0x3];
2405         u8         cvlan_id[0xc];
2406
2407         u8         reserved_at_60[0x7a0];
2408 };
2409
2410 enum {
2411         MLX5_EQC_STATUS_OK                = 0x0,
2412         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2413 };
2414
2415 enum {
2416         MLX5_EQC_ST_ARMED  = 0x9,
2417         MLX5_EQC_ST_FIRED  = 0xa,
2418 };
2419
2420 struct mlx5_ifc_eqc_bits {
2421         u8         status[0x4];
2422         u8         reserved_at_4[0x9];
2423         u8         ec[0x1];
2424         u8         oi[0x1];
2425         u8         reserved_at_f[0x5];
2426         u8         st[0x4];
2427         u8         reserved_at_18[0x8];
2428
2429         u8         reserved_at_20[0x20];
2430
2431         u8         reserved_at_40[0x14];
2432         u8         page_offset[0x6];
2433         u8         reserved_at_5a[0x6];
2434
2435         u8         reserved_at_60[0x3];
2436         u8         log_eq_size[0x5];
2437         u8         uar_page[0x18];
2438
2439         u8         reserved_at_80[0x20];
2440
2441         u8         reserved_at_a0[0x18];
2442         u8         intr[0x8];
2443
2444         u8         reserved_at_c0[0x3];
2445         u8         log_page_size[0x5];
2446         u8         reserved_at_c8[0x18];
2447
2448         u8         reserved_at_e0[0x60];
2449
2450         u8         reserved_at_140[0x8];
2451         u8         consumer_counter[0x18];
2452
2453         u8         reserved_at_160[0x8];
2454         u8         producer_counter[0x18];
2455
2456         u8         reserved_at_180[0x80];
2457 };
2458
2459 enum {
2460         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2461         MLX5_DCTC_STATE_DRAINING  = 0x1,
2462         MLX5_DCTC_STATE_DRAINED   = 0x2,
2463 };
2464
2465 enum {
2466         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2467         MLX5_DCTC_CS_RES_NA         = 0x1,
2468         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2469 };
2470
2471 enum {
2472         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2473         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2474         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2475         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2476         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2477 };
2478
2479 struct mlx5_ifc_dctc_bits {
2480         u8         reserved_at_0[0x4];
2481         u8         state[0x4];
2482         u8         reserved_at_8[0x18];
2483
2484         u8         reserved_at_20[0x8];
2485         u8         user_index[0x18];
2486
2487         u8         reserved_at_40[0x8];
2488         u8         cqn[0x18];
2489
2490         u8         counter_set_id[0x8];
2491         u8         atomic_mode[0x4];
2492         u8         rre[0x1];
2493         u8         rwe[0x1];
2494         u8         rae[0x1];
2495         u8         atomic_like_write_en[0x1];
2496         u8         latency_sensitive[0x1];
2497         u8         rlky[0x1];
2498         u8         free_ar[0x1];
2499         u8         reserved_at_73[0xd];
2500
2501         u8         reserved_at_80[0x8];
2502         u8         cs_res[0x8];
2503         u8         reserved_at_90[0x3];
2504         u8         min_rnr_nak[0x5];
2505         u8         reserved_at_98[0x8];
2506
2507         u8         reserved_at_a0[0x8];
2508         u8         srqn[0x18];
2509
2510         u8         reserved_at_c0[0x8];
2511         u8         pd[0x18];
2512
2513         u8         tclass[0x8];
2514         u8         reserved_at_e8[0x4];
2515         u8         flow_label[0x14];
2516
2517         u8         dc_access_key[0x40];
2518
2519         u8         reserved_at_140[0x5];
2520         u8         mtu[0x3];
2521         u8         port[0x8];
2522         u8         pkey_index[0x10];
2523
2524         u8         reserved_at_160[0x8];
2525         u8         my_addr_index[0x8];
2526         u8         reserved_at_170[0x8];
2527         u8         hop_limit[0x8];
2528
2529         u8         dc_access_key_violation_count[0x20];
2530
2531         u8         reserved_at_1a0[0x14];
2532         u8         dei_cfi[0x1];
2533         u8         eth_prio[0x3];
2534         u8         ecn[0x2];
2535         u8         dscp[0x6];
2536
2537         u8         reserved_at_1c0[0x40];
2538 };
2539
2540 enum {
2541         MLX5_CQC_STATUS_OK             = 0x0,
2542         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2543         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2544 };
2545
2546 enum {
2547         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2548         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2549 };
2550
2551 enum {
2552         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2553         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2554         MLX5_CQC_ST_FIRED                                 = 0xa,
2555 };
2556
2557 struct mlx5_ifc_cqc_bits {
2558         u8         status[0x4];
2559         u8         reserved_at_4[0x4];
2560         u8         cqe_sz[0x3];
2561         u8         cc[0x1];
2562         u8         reserved_at_c[0x1];
2563         u8         scqe_break_moderation_en[0x1];
2564         u8         oi[0x1];
2565         u8         reserved_at_f[0x2];
2566         u8         cqe_zip_en[0x1];
2567         u8         mini_cqe_res_format[0x2];
2568         u8         st[0x4];
2569         u8         reserved_at_18[0x8];
2570
2571         u8         reserved_at_20[0x20];
2572
2573         u8         reserved_at_40[0x14];
2574         u8         page_offset[0x6];
2575         u8         reserved_at_5a[0x6];
2576
2577         u8         reserved_at_60[0x3];
2578         u8         log_cq_size[0x5];
2579         u8         uar_page[0x18];
2580
2581         u8         reserved_at_80[0x4];
2582         u8         cq_period[0xc];
2583         u8         cq_max_count[0x10];
2584
2585         u8         reserved_at_a0[0x18];
2586         u8         c_eqn[0x8];
2587
2588         u8         reserved_at_c0[0x3];
2589         u8         log_page_size[0x5];
2590         u8         reserved_at_c8[0x18];
2591
2592         u8         reserved_at_e0[0x20];
2593
2594         u8         reserved_at_100[0x8];
2595         u8         last_notified_index[0x18];
2596
2597         u8         reserved_at_120[0x8];
2598         u8         last_solicit_index[0x18];
2599
2600         u8         reserved_at_140[0x8];
2601         u8         consumer_counter[0x18];
2602
2603         u8         reserved_at_160[0x8];
2604         u8         producer_counter[0x18];
2605
2606         u8         reserved_at_180[0x40];
2607
2608         u8         dbr_addr[0x40];
2609 };
2610
2611 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2612         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2613         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2614         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2615         u8         reserved_at_0[0x800];
2616 };
2617
2618 struct mlx5_ifc_query_adapter_param_block_bits {
2619         u8         reserved_at_0[0xc0];
2620
2621         u8         reserved_at_c0[0x8];
2622         u8         ieee_vendor_id[0x18];
2623
2624         u8         reserved_at_e0[0x10];
2625         u8         vsd_vendor_id[0x10];
2626
2627         u8         vsd[208][0x8];
2628
2629         u8         vsd_contd_psid[16][0x8];
2630 };
2631
2632 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2633         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2634         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2635         u8         reserved_at_0[0x20];
2636 };
2637
2638 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2639         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2640         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2641         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2642         u8         reserved_at_0[0x20];
2643 };
2644
2645 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2646         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2647         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2648         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2649         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2650         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2651         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2652         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2653         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2654         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2655         u8         reserved_at_0[0x7c0];
2656 };
2657
2658 union mlx5_ifc_event_auto_bits {
2659         struct mlx5_ifc_comp_event_bits comp_event;
2660         struct mlx5_ifc_dct_events_bits dct_events;
2661         struct mlx5_ifc_qp_events_bits qp_events;
2662         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2663         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2664         struct mlx5_ifc_cq_error_bits cq_error;
2665         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2666         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2667         struct mlx5_ifc_gpio_event_bits gpio_event;
2668         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2669         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2670         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2671         u8         reserved_at_0[0xe0];
2672 };
2673
2674 struct mlx5_ifc_health_buffer_bits {
2675         u8         reserved_at_0[0x100];
2676
2677         u8         assert_existptr[0x20];
2678
2679         u8         assert_callra[0x20];
2680
2681         u8         reserved_at_140[0x40];
2682
2683         u8         fw_version[0x20];
2684
2685         u8         hw_id[0x20];
2686
2687         u8         reserved_at_1c0[0x20];
2688
2689         u8         irisc_index[0x8];
2690         u8         synd[0x8];
2691         u8         ext_synd[0x10];
2692 };
2693
2694 struct mlx5_ifc_register_loopback_control_bits {
2695         u8         no_lb[0x1];
2696         u8         reserved_at_1[0x7];
2697         u8         port[0x8];
2698         u8         reserved_at_10[0x10];
2699
2700         u8         reserved_at_20[0x60];
2701 };
2702
2703 struct mlx5_ifc_teardown_hca_out_bits {
2704         u8         status[0x8];
2705         u8         reserved_at_8[0x18];
2706
2707         u8         syndrome[0x20];
2708
2709         u8         reserved_at_40[0x40];
2710 };
2711
2712 enum {
2713         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
2714         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
2715 };
2716
2717 struct mlx5_ifc_teardown_hca_in_bits {
2718         u8         opcode[0x10];
2719         u8         reserved_at_10[0x10];
2720
2721         u8         reserved_at_20[0x10];
2722         u8         op_mod[0x10];
2723
2724         u8         reserved_at_40[0x10];
2725         u8         profile[0x10];
2726
2727         u8         reserved_at_60[0x20];
2728 };
2729
2730 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2731         u8         status[0x8];
2732         u8         reserved_at_8[0x18];
2733
2734         u8         syndrome[0x20];
2735
2736         u8         reserved_at_40[0x40];
2737 };
2738
2739 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2740         u8         opcode[0x10];
2741         u8         reserved_at_10[0x10];
2742
2743         u8         reserved_at_20[0x10];
2744         u8         op_mod[0x10];
2745
2746         u8         reserved_at_40[0x8];
2747         u8         qpn[0x18];
2748
2749         u8         reserved_at_60[0x20];
2750
2751         u8         opt_param_mask[0x20];
2752
2753         u8         reserved_at_a0[0x20];
2754
2755         struct mlx5_ifc_qpc_bits qpc;
2756
2757         u8         reserved_at_800[0x80];
2758 };
2759
2760 struct mlx5_ifc_sqd2rts_qp_out_bits {
2761         u8         status[0x8];
2762         u8         reserved_at_8[0x18];
2763
2764         u8         syndrome[0x20];
2765
2766         u8         reserved_at_40[0x40];
2767 };
2768
2769 struct mlx5_ifc_sqd2rts_qp_in_bits {
2770         u8         opcode[0x10];
2771         u8         reserved_at_10[0x10];
2772
2773         u8         reserved_at_20[0x10];
2774         u8         op_mod[0x10];
2775
2776         u8         reserved_at_40[0x8];
2777         u8         qpn[0x18];
2778
2779         u8         reserved_at_60[0x20];
2780
2781         u8         opt_param_mask[0x20];
2782
2783         u8         reserved_at_a0[0x20];
2784
2785         struct mlx5_ifc_qpc_bits qpc;
2786
2787         u8         reserved_at_800[0x80];
2788 };
2789
2790 struct mlx5_ifc_set_roce_address_out_bits {
2791         u8         status[0x8];
2792         u8         reserved_at_8[0x18];
2793
2794         u8         syndrome[0x20];
2795
2796         u8         reserved_at_40[0x40];
2797 };
2798
2799 struct mlx5_ifc_set_roce_address_in_bits {
2800         u8         opcode[0x10];
2801         u8         reserved_at_10[0x10];
2802
2803         u8         reserved_at_20[0x10];
2804         u8         op_mod[0x10];
2805
2806         u8         roce_address_index[0x10];
2807         u8         reserved_at_50[0x10];
2808
2809         u8         reserved_at_60[0x20];
2810
2811         struct mlx5_ifc_roce_addr_layout_bits roce_address;
2812 };
2813
2814 struct mlx5_ifc_set_mad_demux_out_bits {
2815         u8         status[0x8];
2816         u8         reserved_at_8[0x18];
2817
2818         u8         syndrome[0x20];
2819
2820         u8         reserved_at_40[0x40];
2821 };
2822
2823 enum {
2824         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
2825         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
2826 };
2827
2828 struct mlx5_ifc_set_mad_demux_in_bits {
2829         u8         opcode[0x10];
2830         u8         reserved_at_10[0x10];
2831
2832         u8         reserved_at_20[0x10];
2833         u8         op_mod[0x10];
2834
2835         u8         reserved_at_40[0x20];
2836
2837         u8         reserved_at_60[0x6];
2838         u8         demux_mode[0x2];
2839         u8         reserved_at_68[0x18];
2840 };
2841
2842 struct mlx5_ifc_set_l2_table_entry_out_bits {
2843         u8         status[0x8];
2844         u8         reserved_at_8[0x18];
2845
2846         u8         syndrome[0x20];
2847
2848         u8         reserved_at_40[0x40];
2849 };
2850
2851 struct mlx5_ifc_set_l2_table_entry_in_bits {
2852         u8         opcode[0x10];
2853         u8         reserved_at_10[0x10];
2854
2855         u8         reserved_at_20[0x10];
2856         u8         op_mod[0x10];
2857
2858         u8         reserved_at_40[0x60];
2859
2860         u8         reserved_at_a0[0x8];
2861         u8         table_index[0x18];
2862
2863         u8         reserved_at_c0[0x20];
2864
2865         u8         reserved_at_e0[0x13];
2866         u8         vlan_valid[0x1];
2867         u8         vlan[0xc];
2868
2869         struct mlx5_ifc_mac_address_layout_bits mac_address;
2870
2871         u8         reserved_at_140[0xc0];
2872 };
2873
2874 struct mlx5_ifc_set_issi_out_bits {
2875         u8         status[0x8];
2876         u8         reserved_at_8[0x18];
2877
2878         u8         syndrome[0x20];
2879
2880         u8         reserved_at_40[0x40];
2881 };
2882
2883 struct mlx5_ifc_set_issi_in_bits {
2884         u8         opcode[0x10];
2885         u8         reserved_at_10[0x10];
2886
2887         u8         reserved_at_20[0x10];
2888         u8         op_mod[0x10];
2889
2890         u8         reserved_at_40[0x10];
2891         u8         current_issi[0x10];
2892
2893         u8         reserved_at_60[0x20];
2894 };
2895
2896 struct mlx5_ifc_set_hca_cap_out_bits {
2897         u8         status[0x8];
2898         u8         reserved_at_8[0x18];
2899
2900         u8         syndrome[0x20];
2901
2902         u8         reserved_at_40[0x40];
2903 };
2904
2905 struct mlx5_ifc_set_hca_cap_in_bits {
2906         u8         opcode[0x10];
2907         u8         reserved_at_10[0x10];
2908
2909         u8         reserved_at_20[0x10];
2910         u8         op_mod[0x10];
2911
2912         u8         reserved_at_40[0x40];
2913
2914         union mlx5_ifc_hca_cap_union_bits capability;
2915 };
2916
2917 enum {
2918         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
2919         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
2920         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
2921         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
2922 };
2923
2924 struct mlx5_ifc_set_fte_out_bits {
2925         u8         status[0x8];
2926         u8         reserved_at_8[0x18];
2927
2928         u8         syndrome[0x20];
2929
2930         u8         reserved_at_40[0x40];
2931 };
2932
2933 struct mlx5_ifc_set_fte_in_bits {
2934         u8         opcode[0x10];
2935         u8         reserved_at_10[0x10];
2936
2937         u8         reserved_at_20[0x10];
2938         u8         op_mod[0x10];
2939
2940         u8         reserved_at_40[0x40];
2941
2942         u8         table_type[0x8];
2943         u8         reserved_at_88[0x18];
2944
2945         u8         reserved_at_a0[0x8];
2946         u8         table_id[0x18];
2947
2948         u8         reserved_at_c0[0x18];
2949         u8         modify_enable_mask[0x8];
2950
2951         u8         reserved_at_e0[0x20];
2952
2953         u8         flow_index[0x20];
2954
2955         u8         reserved_at_120[0xe0];
2956
2957         struct mlx5_ifc_flow_context_bits flow_context;
2958 };
2959
2960 struct mlx5_ifc_rts2rts_qp_out_bits {
2961         u8         status[0x8];
2962         u8         reserved_at_8[0x18];
2963
2964         u8         syndrome[0x20];
2965
2966         u8         reserved_at_40[0x40];
2967 };
2968
2969 struct mlx5_ifc_rts2rts_qp_in_bits {
2970         u8         opcode[0x10];
2971         u8         reserved_at_10[0x10];
2972
2973         u8         reserved_at_20[0x10];
2974         u8         op_mod[0x10];
2975
2976         u8         reserved_at_40[0x8];
2977         u8         qpn[0x18];
2978
2979         u8         reserved_at_60[0x20];
2980
2981         u8         opt_param_mask[0x20];
2982
2983         u8         reserved_at_a0[0x20];
2984
2985         struct mlx5_ifc_qpc_bits qpc;
2986
2987         u8         reserved_at_800[0x80];
2988 };
2989
2990 struct mlx5_ifc_rtr2rts_qp_out_bits {
2991         u8         status[0x8];
2992         u8         reserved_at_8[0x18];
2993
2994         u8         syndrome[0x20];
2995
2996         u8         reserved_at_40[0x40];
2997 };
2998
2999 struct mlx5_ifc_rtr2rts_qp_in_bits {
3000         u8         opcode[0x10];
3001         u8         reserved_at_10[0x10];
3002
3003         u8         reserved_at_20[0x10];
3004         u8         op_mod[0x10];
3005
3006         u8         reserved_at_40[0x8];
3007         u8         qpn[0x18];
3008
3009         u8         reserved_at_60[0x20];
3010
3011         u8         opt_param_mask[0x20];
3012
3013         u8         reserved_at_a0[0x20];
3014
3015         struct mlx5_ifc_qpc_bits qpc;
3016
3017         u8         reserved_at_800[0x80];
3018 };
3019
3020 struct mlx5_ifc_rst2init_qp_out_bits {
3021         u8         status[0x8];
3022         u8         reserved_at_8[0x18];
3023
3024         u8         syndrome[0x20];
3025
3026         u8         reserved_at_40[0x40];
3027 };
3028
3029 struct mlx5_ifc_rst2init_qp_in_bits {
3030         u8         opcode[0x10];
3031         u8         reserved_at_10[0x10];
3032
3033         u8         reserved_at_20[0x10];
3034         u8         op_mod[0x10];
3035
3036         u8         reserved_at_40[0x8];
3037         u8         qpn[0x18];
3038
3039         u8         reserved_at_60[0x20];
3040
3041         u8         opt_param_mask[0x20];
3042
3043         u8         reserved_at_a0[0x20];
3044
3045         struct mlx5_ifc_qpc_bits qpc;
3046
3047         u8         reserved_at_800[0x80];
3048 };
3049
3050 struct mlx5_ifc_query_xrc_srq_out_bits {
3051         u8         status[0x8];
3052         u8         reserved_at_8[0x18];
3053
3054         u8         syndrome[0x20];
3055
3056         u8         reserved_at_40[0x40];
3057
3058         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3059
3060         u8         reserved_at_280[0x600];
3061
3062         u8         pas[0][0x40];
3063 };
3064
3065 struct mlx5_ifc_query_xrc_srq_in_bits {
3066         u8         opcode[0x10];
3067         u8         reserved_at_10[0x10];
3068
3069         u8         reserved_at_20[0x10];
3070         u8         op_mod[0x10];
3071
3072         u8         reserved_at_40[0x8];
3073         u8         xrc_srqn[0x18];
3074
3075         u8         reserved_at_60[0x20];
3076 };
3077
3078 enum {
3079         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3080         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3081 };
3082
3083 struct mlx5_ifc_query_vport_state_out_bits {
3084         u8         status[0x8];
3085         u8         reserved_at_8[0x18];
3086
3087         u8         syndrome[0x20];
3088
3089         u8         reserved_at_40[0x20];
3090
3091         u8         reserved_at_60[0x18];
3092         u8         admin_state[0x4];
3093         u8         state[0x4];
3094 };
3095
3096 enum {
3097         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3098         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3099 };
3100
3101 struct mlx5_ifc_query_vport_state_in_bits {
3102         u8         opcode[0x10];
3103         u8         reserved_at_10[0x10];
3104
3105         u8         reserved_at_20[0x10];
3106         u8         op_mod[0x10];
3107
3108         u8         other_vport[0x1];
3109         u8         reserved_at_41[0xf];
3110         u8         vport_number[0x10];
3111
3112         u8         reserved_at_60[0x20];
3113 };
3114
3115 struct mlx5_ifc_query_vport_counter_out_bits {
3116         u8         status[0x8];
3117         u8         reserved_at_8[0x18];
3118
3119         u8         syndrome[0x20];
3120
3121         u8         reserved_at_40[0x40];
3122
3123         struct mlx5_ifc_traffic_counter_bits received_errors;
3124
3125         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3126
3127         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3128
3129         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3130
3131         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3132
3133         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3134
3135         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3136
3137         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3138
3139         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3140
3141         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3142
3143         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3144
3145         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3146
3147         u8         reserved_at_680[0xa00];
3148 };
3149
3150 enum {
3151         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3152 };
3153
3154 struct mlx5_ifc_query_vport_counter_in_bits {
3155         u8         opcode[0x10];
3156         u8         reserved_at_10[0x10];
3157
3158         u8         reserved_at_20[0x10];
3159         u8         op_mod[0x10];
3160
3161         u8         other_vport[0x1];
3162         u8         reserved_at_41[0xb];
3163         u8         port_num[0x4];
3164         u8         vport_number[0x10];
3165
3166         u8         reserved_at_60[0x60];
3167
3168         u8         clear[0x1];
3169         u8         reserved_at_c1[0x1f];
3170
3171         u8         reserved_at_e0[0x20];
3172 };
3173
3174 struct mlx5_ifc_query_tis_out_bits {
3175         u8         status[0x8];
3176         u8         reserved_at_8[0x18];
3177
3178         u8         syndrome[0x20];
3179
3180         u8         reserved_at_40[0x40];
3181
3182         struct mlx5_ifc_tisc_bits tis_context;
3183 };
3184
3185 struct mlx5_ifc_query_tis_in_bits {
3186         u8         opcode[0x10];
3187         u8         reserved_at_10[0x10];
3188
3189         u8         reserved_at_20[0x10];
3190         u8         op_mod[0x10];
3191
3192         u8         reserved_at_40[0x8];
3193         u8         tisn[0x18];
3194
3195         u8         reserved_at_60[0x20];
3196 };
3197
3198 struct mlx5_ifc_query_tir_out_bits {
3199         u8         status[0x8];
3200         u8         reserved_at_8[0x18];
3201
3202         u8         syndrome[0x20];
3203
3204         u8         reserved_at_40[0xc0];
3205
3206         struct mlx5_ifc_tirc_bits tir_context;
3207 };
3208
3209 struct mlx5_ifc_query_tir_in_bits {
3210         u8         opcode[0x10];
3211         u8         reserved_at_10[0x10];
3212
3213         u8         reserved_at_20[0x10];
3214         u8         op_mod[0x10];
3215
3216         u8         reserved_at_40[0x8];
3217         u8         tirn[0x18];
3218
3219         u8         reserved_at_60[0x20];
3220 };
3221
3222 struct mlx5_ifc_query_srq_out_bits {
3223         u8         status[0x8];
3224         u8         reserved_at_8[0x18];
3225
3226         u8         syndrome[0x20];
3227
3228         u8         reserved_at_40[0x40];
3229
3230         struct mlx5_ifc_srqc_bits srq_context_entry;
3231
3232         u8         reserved_at_280[0x600];
3233
3234         u8         pas[0][0x40];
3235 };
3236
3237 struct mlx5_ifc_query_srq_in_bits {
3238         u8         opcode[0x10];
3239         u8         reserved_at_10[0x10];
3240
3241         u8         reserved_at_20[0x10];
3242         u8         op_mod[0x10];
3243
3244         u8         reserved_at_40[0x8];
3245         u8         srqn[0x18];
3246
3247         u8         reserved_at_60[0x20];
3248 };
3249
3250 struct mlx5_ifc_query_sq_out_bits {
3251         u8         status[0x8];
3252         u8         reserved_at_8[0x18];
3253
3254         u8         syndrome[0x20];
3255
3256         u8         reserved_at_40[0xc0];
3257
3258         struct mlx5_ifc_sqc_bits sq_context;
3259 };
3260
3261 struct mlx5_ifc_query_sq_in_bits {
3262         u8         opcode[0x10];
3263         u8         reserved_at_10[0x10];
3264
3265         u8         reserved_at_20[0x10];
3266         u8         op_mod[0x10];
3267
3268         u8         reserved_at_40[0x8];
3269         u8         sqn[0x18];
3270
3271         u8         reserved_at_60[0x20];
3272 };
3273
3274 struct mlx5_ifc_query_special_contexts_out_bits {
3275         u8         status[0x8];
3276         u8         reserved_at_8[0x18];
3277
3278         u8         syndrome[0x20];
3279
3280         u8         reserved_at_40[0x20];
3281
3282         u8         resd_lkey[0x20];
3283 };
3284
3285 struct mlx5_ifc_query_special_contexts_in_bits {
3286         u8         opcode[0x10];
3287         u8         reserved_at_10[0x10];
3288
3289         u8         reserved_at_20[0x10];
3290         u8         op_mod[0x10];
3291
3292         u8         reserved_at_40[0x40];
3293 };
3294
3295 struct mlx5_ifc_query_rqt_out_bits {
3296         u8         status[0x8];
3297         u8         reserved_at_8[0x18];
3298
3299         u8         syndrome[0x20];
3300
3301         u8         reserved_at_40[0xc0];
3302
3303         struct mlx5_ifc_rqtc_bits rqt_context;
3304 };
3305
3306 struct mlx5_ifc_query_rqt_in_bits {
3307         u8         opcode[0x10];
3308         u8         reserved_at_10[0x10];
3309
3310         u8         reserved_at_20[0x10];
3311         u8         op_mod[0x10];
3312
3313         u8         reserved_at_40[0x8];
3314         u8         rqtn[0x18];
3315
3316         u8         reserved_at_60[0x20];
3317 };
3318
3319 struct mlx5_ifc_query_rq_out_bits {
3320         u8         status[0x8];
3321         u8         reserved_at_8[0x18];
3322
3323         u8         syndrome[0x20];
3324
3325         u8         reserved_at_40[0xc0];
3326
3327         struct mlx5_ifc_rqc_bits rq_context;
3328 };
3329
3330 struct mlx5_ifc_query_rq_in_bits {
3331         u8         opcode[0x10];
3332         u8         reserved_at_10[0x10];
3333
3334         u8         reserved_at_20[0x10];
3335         u8         op_mod[0x10];
3336
3337         u8         reserved_at_40[0x8];
3338         u8         rqn[0x18];
3339
3340         u8         reserved_at_60[0x20];
3341 };
3342
3343 struct mlx5_ifc_query_roce_address_out_bits {
3344         u8         status[0x8];
3345         u8         reserved_at_8[0x18];
3346
3347         u8         syndrome[0x20];
3348
3349         u8         reserved_at_40[0x40];
3350
3351         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3352 };
3353
3354 struct mlx5_ifc_query_roce_address_in_bits {
3355         u8         opcode[0x10];
3356         u8         reserved_at_10[0x10];
3357
3358         u8         reserved_at_20[0x10];
3359         u8         op_mod[0x10];
3360
3361         u8         roce_address_index[0x10];
3362         u8         reserved_at_50[0x10];
3363
3364         u8         reserved_at_60[0x20];
3365 };
3366
3367 struct mlx5_ifc_query_rmp_out_bits {
3368         u8         status[0x8];
3369         u8         reserved_at_8[0x18];
3370
3371         u8         syndrome[0x20];
3372
3373         u8         reserved_at_40[0xc0];
3374
3375         struct mlx5_ifc_rmpc_bits rmp_context;
3376 };
3377
3378 struct mlx5_ifc_query_rmp_in_bits {
3379         u8         opcode[0x10];
3380         u8         reserved_at_10[0x10];
3381
3382         u8         reserved_at_20[0x10];
3383         u8         op_mod[0x10];
3384
3385         u8         reserved_at_40[0x8];
3386         u8         rmpn[0x18];
3387
3388         u8         reserved_at_60[0x20];
3389 };
3390
3391 struct mlx5_ifc_query_qp_out_bits {
3392         u8         status[0x8];
3393         u8         reserved_at_8[0x18];
3394
3395         u8         syndrome[0x20];
3396
3397         u8         reserved_at_40[0x40];
3398
3399         u8         opt_param_mask[0x20];
3400
3401         u8         reserved_at_a0[0x20];
3402
3403         struct mlx5_ifc_qpc_bits qpc;
3404
3405         u8         reserved_at_800[0x80];
3406
3407         u8         pas[0][0x40];
3408 };
3409
3410 struct mlx5_ifc_query_qp_in_bits {
3411         u8         opcode[0x10];
3412         u8         reserved_at_10[0x10];
3413
3414         u8         reserved_at_20[0x10];
3415         u8         op_mod[0x10];
3416
3417         u8         reserved_at_40[0x8];
3418         u8         qpn[0x18];
3419
3420         u8         reserved_at_60[0x20];
3421 };
3422
3423 struct mlx5_ifc_query_q_counter_out_bits {
3424         u8         status[0x8];
3425         u8         reserved_at_8[0x18];
3426
3427         u8         syndrome[0x20];
3428
3429         u8         reserved_at_40[0x40];
3430
3431         u8         rx_write_requests[0x20];
3432
3433         u8         reserved_at_a0[0x20];
3434
3435         u8         rx_read_requests[0x20];
3436
3437         u8         reserved_at_e0[0x20];
3438
3439         u8         rx_atomic_requests[0x20];
3440
3441         u8         reserved_at_120[0x20];
3442
3443         u8         rx_dct_connect[0x20];
3444
3445         u8         reserved_at_160[0x20];
3446
3447         u8         out_of_buffer[0x20];
3448
3449         u8         reserved_at_1a0[0x20];
3450
3451         u8         out_of_sequence[0x20];
3452
3453         u8         reserved_at_1e0[0x620];
3454 };
3455
3456 struct mlx5_ifc_query_q_counter_in_bits {
3457         u8         opcode[0x10];
3458         u8         reserved_at_10[0x10];
3459
3460         u8         reserved_at_20[0x10];
3461         u8         op_mod[0x10];
3462
3463         u8         reserved_at_40[0x80];
3464
3465         u8         clear[0x1];
3466         u8         reserved_at_c1[0x1f];
3467
3468         u8         reserved_at_e0[0x18];
3469         u8         counter_set_id[0x8];
3470 };
3471
3472 struct mlx5_ifc_query_pages_out_bits {
3473         u8         status[0x8];
3474         u8         reserved_at_8[0x18];
3475
3476         u8         syndrome[0x20];
3477
3478         u8         reserved_at_40[0x10];
3479         u8         function_id[0x10];
3480
3481         u8         num_pages[0x20];
3482 };
3483
3484 enum {
3485         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3486         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3487         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3488 };
3489
3490 struct mlx5_ifc_query_pages_in_bits {
3491         u8         opcode[0x10];
3492         u8         reserved_at_10[0x10];
3493
3494         u8         reserved_at_20[0x10];
3495         u8         op_mod[0x10];
3496
3497         u8         reserved_at_40[0x10];
3498         u8         function_id[0x10];
3499
3500         u8         reserved_at_60[0x20];
3501 };
3502
3503 struct mlx5_ifc_query_nic_vport_context_out_bits {
3504         u8         status[0x8];
3505         u8         reserved_at_8[0x18];
3506
3507         u8         syndrome[0x20];
3508
3509         u8         reserved_at_40[0x40];
3510
3511         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3512 };
3513
3514 struct mlx5_ifc_query_nic_vport_context_in_bits {
3515         u8         opcode[0x10];
3516         u8         reserved_at_10[0x10];
3517
3518         u8         reserved_at_20[0x10];
3519         u8         op_mod[0x10];
3520
3521         u8         other_vport[0x1];
3522         u8         reserved_at_41[0xf];
3523         u8         vport_number[0x10];
3524
3525         u8         reserved_at_60[0x5];
3526         u8         allowed_list_type[0x3];
3527         u8         reserved_at_68[0x18];
3528 };
3529
3530 struct mlx5_ifc_query_mkey_out_bits {
3531         u8         status[0x8];
3532         u8         reserved_at_8[0x18];
3533
3534         u8         syndrome[0x20];
3535
3536         u8         reserved_at_40[0x40];
3537
3538         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3539
3540         u8         reserved_at_280[0x600];
3541
3542         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3543
3544         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3545 };
3546
3547 struct mlx5_ifc_query_mkey_in_bits {
3548         u8         opcode[0x10];
3549         u8         reserved_at_10[0x10];
3550
3551         u8         reserved_at_20[0x10];
3552         u8         op_mod[0x10];
3553
3554         u8         reserved_at_40[0x8];
3555         u8         mkey_index[0x18];
3556
3557         u8         pg_access[0x1];
3558         u8         reserved_at_61[0x1f];
3559 };
3560
3561 struct mlx5_ifc_query_mad_demux_out_bits {
3562         u8         status[0x8];
3563         u8         reserved_at_8[0x18];
3564
3565         u8         syndrome[0x20];
3566
3567         u8         reserved_at_40[0x40];
3568
3569         u8         mad_dumux_parameters_block[0x20];
3570 };
3571
3572 struct mlx5_ifc_query_mad_demux_in_bits {
3573         u8         opcode[0x10];
3574         u8         reserved_at_10[0x10];
3575
3576         u8         reserved_at_20[0x10];
3577         u8         op_mod[0x10];
3578
3579         u8         reserved_at_40[0x40];
3580 };
3581
3582 struct mlx5_ifc_query_l2_table_entry_out_bits {
3583         u8         status[0x8];
3584         u8         reserved_at_8[0x18];
3585
3586         u8         syndrome[0x20];
3587
3588         u8         reserved_at_40[0xa0];
3589
3590         u8         reserved_at_e0[0x13];
3591         u8         vlan_valid[0x1];
3592         u8         vlan[0xc];
3593
3594         struct mlx5_ifc_mac_address_layout_bits mac_address;
3595
3596         u8         reserved_at_140[0xc0];
3597 };
3598
3599 struct mlx5_ifc_query_l2_table_entry_in_bits {
3600         u8         opcode[0x10];
3601         u8         reserved_at_10[0x10];
3602
3603         u8         reserved_at_20[0x10];
3604         u8         op_mod[0x10];
3605
3606         u8         reserved_at_40[0x60];
3607
3608         u8         reserved_at_a0[0x8];
3609         u8         table_index[0x18];
3610
3611         u8         reserved_at_c0[0x140];
3612 };
3613
3614 struct mlx5_ifc_query_issi_out_bits {
3615         u8         status[0x8];
3616         u8         reserved_at_8[0x18];
3617
3618         u8         syndrome[0x20];
3619
3620         u8         reserved_at_40[0x10];
3621         u8         current_issi[0x10];
3622
3623         u8         reserved_at_60[0xa0];
3624
3625         u8         reserved_at_100[76][0x8];
3626         u8         supported_issi_dw0[0x20];
3627 };
3628
3629 struct mlx5_ifc_query_issi_in_bits {
3630         u8         opcode[0x10];
3631         u8         reserved_at_10[0x10];
3632
3633         u8         reserved_at_20[0x10];
3634         u8         op_mod[0x10];
3635
3636         u8         reserved_at_40[0x40];
3637 };
3638
3639 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3640         u8         status[0x8];
3641         u8         reserved_at_8[0x18];
3642
3643         u8         syndrome[0x20];
3644
3645         u8         reserved_at_40[0x40];
3646
3647         struct mlx5_ifc_pkey_bits pkey[0];
3648 };
3649
3650 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3651         u8         opcode[0x10];
3652         u8         reserved_at_10[0x10];
3653
3654         u8         reserved_at_20[0x10];
3655         u8         op_mod[0x10];
3656
3657         u8         other_vport[0x1];
3658         u8         reserved_at_41[0xb];
3659         u8         port_num[0x4];
3660         u8         vport_number[0x10];
3661
3662         u8         reserved_at_60[0x10];
3663         u8         pkey_index[0x10];
3664 };
3665
3666 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3667         u8         status[0x8];
3668         u8         reserved_at_8[0x18];
3669
3670         u8         syndrome[0x20];
3671
3672         u8         reserved_at_40[0x20];
3673
3674         u8         gids_num[0x10];
3675         u8         reserved_at_70[0x10];
3676
3677         struct mlx5_ifc_array128_auto_bits gid[0];
3678 };
3679
3680 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3681         u8         opcode[0x10];
3682         u8         reserved_at_10[0x10];
3683
3684         u8         reserved_at_20[0x10];
3685         u8         op_mod[0x10];
3686
3687         u8         other_vport[0x1];
3688         u8         reserved_at_41[0xb];
3689         u8         port_num[0x4];
3690         u8         vport_number[0x10];
3691
3692         u8         reserved_at_60[0x10];
3693         u8         gid_index[0x10];
3694 };
3695
3696 struct mlx5_ifc_query_hca_vport_context_out_bits {
3697         u8         status[0x8];
3698         u8         reserved_at_8[0x18];
3699
3700         u8         syndrome[0x20];
3701
3702         u8         reserved_at_40[0x40];
3703
3704         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3705 };
3706
3707 struct mlx5_ifc_query_hca_vport_context_in_bits {
3708         u8         opcode[0x10];
3709         u8         reserved_at_10[0x10];
3710
3711         u8         reserved_at_20[0x10];
3712         u8         op_mod[0x10];
3713
3714         u8         other_vport[0x1];
3715         u8         reserved_at_41[0xb];
3716         u8         port_num[0x4];
3717         u8         vport_number[0x10];
3718
3719         u8         reserved_at_60[0x20];
3720 };
3721
3722 struct mlx5_ifc_query_hca_cap_out_bits {
3723         u8         status[0x8];
3724         u8         reserved_at_8[0x18];
3725
3726         u8         syndrome[0x20];
3727
3728         u8         reserved_at_40[0x40];
3729
3730         union mlx5_ifc_hca_cap_union_bits capability;
3731 };
3732
3733 struct mlx5_ifc_query_hca_cap_in_bits {
3734         u8         opcode[0x10];
3735         u8         reserved_at_10[0x10];
3736
3737         u8         reserved_at_20[0x10];
3738         u8         op_mod[0x10];
3739
3740         u8         reserved_at_40[0x40];
3741 };
3742
3743 struct mlx5_ifc_query_flow_table_out_bits {
3744         u8         status[0x8];
3745         u8         reserved_at_8[0x18];
3746
3747         u8         syndrome[0x20];
3748
3749         u8         reserved_at_40[0x80];
3750
3751         u8         reserved_at_c0[0x8];
3752         u8         level[0x8];
3753         u8         reserved_at_d0[0x8];
3754         u8         log_size[0x8];
3755
3756         u8         reserved_at_e0[0x120];
3757 };
3758
3759 struct mlx5_ifc_query_flow_table_in_bits {
3760         u8         opcode[0x10];
3761         u8         reserved_at_10[0x10];
3762
3763         u8         reserved_at_20[0x10];
3764         u8         op_mod[0x10];
3765
3766         u8         reserved_at_40[0x40];
3767
3768         u8         table_type[0x8];
3769         u8         reserved_at_88[0x18];
3770
3771         u8         reserved_at_a0[0x8];
3772         u8         table_id[0x18];
3773
3774         u8         reserved_at_c0[0x140];
3775 };
3776
3777 struct mlx5_ifc_query_fte_out_bits {
3778         u8         status[0x8];
3779         u8         reserved_at_8[0x18];
3780
3781         u8         syndrome[0x20];
3782
3783         u8         reserved_at_40[0x1c0];
3784
3785         struct mlx5_ifc_flow_context_bits flow_context;
3786 };
3787
3788 struct mlx5_ifc_query_fte_in_bits {
3789         u8         opcode[0x10];
3790         u8         reserved_at_10[0x10];
3791
3792         u8         reserved_at_20[0x10];
3793         u8         op_mod[0x10];
3794
3795         u8         reserved_at_40[0x40];
3796
3797         u8         table_type[0x8];
3798         u8         reserved_at_88[0x18];
3799
3800         u8         reserved_at_a0[0x8];
3801         u8         table_id[0x18];
3802
3803         u8         reserved_at_c0[0x40];
3804
3805         u8         flow_index[0x20];
3806
3807         u8         reserved_at_120[0xe0];
3808 };
3809
3810 enum {
3811         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
3812         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
3813         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
3814 };
3815
3816 struct mlx5_ifc_query_flow_group_out_bits {
3817         u8         status[0x8];
3818         u8         reserved_at_8[0x18];
3819
3820         u8         syndrome[0x20];
3821
3822         u8         reserved_at_40[0xa0];
3823
3824         u8         start_flow_index[0x20];
3825
3826         u8         reserved_at_100[0x20];
3827
3828         u8         end_flow_index[0x20];
3829
3830         u8         reserved_at_140[0xa0];
3831
3832         u8         reserved_at_1e0[0x18];
3833         u8         match_criteria_enable[0x8];
3834
3835         struct mlx5_ifc_fte_match_param_bits match_criteria;
3836
3837         u8         reserved_at_1200[0xe00];
3838 };
3839
3840 struct mlx5_ifc_query_flow_group_in_bits {
3841         u8         opcode[0x10];
3842         u8         reserved_at_10[0x10];
3843
3844         u8         reserved_at_20[0x10];
3845         u8         op_mod[0x10];
3846
3847         u8         reserved_at_40[0x40];
3848
3849         u8         table_type[0x8];
3850         u8         reserved_at_88[0x18];
3851
3852         u8         reserved_at_a0[0x8];
3853         u8         table_id[0x18];
3854
3855         u8         group_id[0x20];
3856
3857         u8         reserved_at_e0[0x120];
3858 };
3859
3860 struct mlx5_ifc_query_esw_vport_context_out_bits {
3861         u8         status[0x8];
3862         u8         reserved_at_8[0x18];
3863
3864         u8         syndrome[0x20];
3865
3866         u8         reserved_at_40[0x40];
3867
3868         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3869 };
3870
3871 struct mlx5_ifc_query_esw_vport_context_in_bits {
3872         u8         opcode[0x10];
3873         u8         reserved_at_10[0x10];
3874
3875         u8         reserved_at_20[0x10];
3876         u8         op_mod[0x10];
3877
3878         u8         other_vport[0x1];
3879         u8         reserved_at_41[0xf];
3880         u8         vport_number[0x10];
3881
3882         u8         reserved_at_60[0x20];
3883 };
3884
3885 struct mlx5_ifc_modify_esw_vport_context_out_bits {
3886         u8         status[0x8];
3887         u8         reserved_at_8[0x18];
3888
3889         u8         syndrome[0x20];
3890
3891         u8         reserved_at_40[0x40];
3892 };
3893
3894 struct mlx5_ifc_esw_vport_context_fields_select_bits {
3895         u8         reserved_at_0[0x1c];
3896         u8         vport_cvlan_insert[0x1];
3897         u8         vport_svlan_insert[0x1];
3898         u8         vport_cvlan_strip[0x1];
3899         u8         vport_svlan_strip[0x1];
3900 };
3901
3902 struct mlx5_ifc_modify_esw_vport_context_in_bits {
3903         u8         opcode[0x10];
3904         u8         reserved_at_10[0x10];
3905
3906         u8         reserved_at_20[0x10];
3907         u8         op_mod[0x10];
3908
3909         u8         other_vport[0x1];
3910         u8         reserved_at_41[0xf];
3911         u8         vport_number[0x10];
3912
3913         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
3914
3915         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3916 };
3917
3918 struct mlx5_ifc_query_eq_out_bits {
3919         u8         status[0x8];
3920         u8         reserved_at_8[0x18];
3921
3922         u8         syndrome[0x20];
3923
3924         u8         reserved_at_40[0x40];
3925
3926         struct mlx5_ifc_eqc_bits eq_context_entry;
3927
3928         u8         reserved_at_280[0x40];
3929
3930         u8         event_bitmask[0x40];
3931
3932         u8         reserved_at_300[0x580];
3933
3934         u8         pas[0][0x40];
3935 };
3936
3937 struct mlx5_ifc_query_eq_in_bits {
3938         u8         opcode[0x10];
3939         u8         reserved_at_10[0x10];
3940
3941         u8         reserved_at_20[0x10];
3942         u8         op_mod[0x10];
3943
3944         u8         reserved_at_40[0x18];
3945         u8         eq_number[0x8];
3946
3947         u8         reserved_at_60[0x20];
3948 };
3949
3950 struct mlx5_ifc_query_dct_out_bits {
3951         u8         status[0x8];
3952         u8         reserved_at_8[0x18];
3953
3954         u8         syndrome[0x20];
3955
3956         u8         reserved_at_40[0x40];
3957
3958         struct mlx5_ifc_dctc_bits dct_context_entry;
3959
3960         u8         reserved_at_280[0x180];
3961 };
3962
3963 struct mlx5_ifc_query_dct_in_bits {
3964         u8         opcode[0x10];
3965         u8         reserved_at_10[0x10];
3966
3967         u8         reserved_at_20[0x10];
3968         u8         op_mod[0x10];
3969
3970         u8         reserved_at_40[0x8];
3971         u8         dctn[0x18];
3972
3973         u8         reserved_at_60[0x20];
3974 };
3975
3976 struct mlx5_ifc_query_cq_out_bits {
3977         u8         status[0x8];
3978         u8         reserved_at_8[0x18];
3979
3980         u8         syndrome[0x20];
3981
3982         u8         reserved_at_40[0x40];
3983
3984         struct mlx5_ifc_cqc_bits cq_context;
3985
3986         u8         reserved_at_280[0x600];
3987
3988         u8         pas[0][0x40];
3989 };
3990
3991 struct mlx5_ifc_query_cq_in_bits {
3992         u8         opcode[0x10];
3993         u8         reserved_at_10[0x10];
3994
3995         u8         reserved_at_20[0x10];
3996         u8         op_mod[0x10];
3997
3998         u8         reserved_at_40[0x8];
3999         u8         cqn[0x18];
4000
4001         u8         reserved_at_60[0x20];
4002 };
4003
4004 struct mlx5_ifc_query_cong_status_out_bits {
4005         u8         status[0x8];
4006         u8         reserved_at_8[0x18];
4007
4008         u8         syndrome[0x20];
4009
4010         u8         reserved_at_40[0x20];
4011
4012         u8         enable[0x1];
4013         u8         tag_enable[0x1];
4014         u8         reserved_at_62[0x1e];
4015 };
4016
4017 struct mlx5_ifc_query_cong_status_in_bits {
4018         u8         opcode[0x10];
4019         u8         reserved_at_10[0x10];
4020
4021         u8         reserved_at_20[0x10];
4022         u8         op_mod[0x10];
4023
4024         u8         reserved_at_40[0x18];
4025         u8         priority[0x4];
4026         u8         cong_protocol[0x4];
4027
4028         u8         reserved_at_60[0x20];
4029 };
4030
4031 struct mlx5_ifc_query_cong_statistics_out_bits {
4032         u8         status[0x8];
4033         u8         reserved_at_8[0x18];
4034
4035         u8         syndrome[0x20];
4036
4037         u8         reserved_at_40[0x40];
4038
4039         u8         cur_flows[0x20];
4040
4041         u8         sum_flows[0x20];
4042
4043         u8         cnp_ignored_high[0x20];
4044
4045         u8         cnp_ignored_low[0x20];
4046
4047         u8         cnp_handled_high[0x20];
4048
4049         u8         cnp_handled_low[0x20];
4050
4051         u8         reserved_at_140[0x100];
4052
4053         u8         time_stamp_high[0x20];
4054
4055         u8         time_stamp_low[0x20];
4056
4057         u8         accumulators_period[0x20];
4058
4059         u8         ecn_marked_roce_packets_high[0x20];
4060
4061         u8         ecn_marked_roce_packets_low[0x20];
4062
4063         u8         cnps_sent_high[0x20];
4064
4065         u8         cnps_sent_low[0x20];
4066
4067         u8         reserved_at_320[0x560];
4068 };
4069
4070 struct mlx5_ifc_query_cong_statistics_in_bits {
4071         u8         opcode[0x10];
4072         u8         reserved_at_10[0x10];
4073
4074         u8         reserved_at_20[0x10];
4075         u8         op_mod[0x10];
4076
4077         u8         clear[0x1];
4078         u8         reserved_at_41[0x1f];
4079
4080         u8         reserved_at_60[0x20];
4081 };
4082
4083 struct mlx5_ifc_query_cong_params_out_bits {
4084         u8         status[0x8];
4085         u8         reserved_at_8[0x18];
4086
4087         u8         syndrome[0x20];
4088
4089         u8         reserved_at_40[0x40];
4090
4091         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4092 };
4093
4094 struct mlx5_ifc_query_cong_params_in_bits {
4095         u8         opcode[0x10];
4096         u8         reserved_at_10[0x10];
4097
4098         u8         reserved_at_20[0x10];
4099         u8         op_mod[0x10];
4100
4101         u8         reserved_at_40[0x1c];
4102         u8         cong_protocol[0x4];
4103
4104         u8         reserved_at_60[0x20];
4105 };
4106
4107 struct mlx5_ifc_query_adapter_out_bits {
4108         u8         status[0x8];
4109         u8         reserved_at_8[0x18];
4110
4111         u8         syndrome[0x20];
4112
4113         u8         reserved_at_40[0x40];
4114
4115         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4116 };
4117
4118 struct mlx5_ifc_query_adapter_in_bits {
4119         u8         opcode[0x10];
4120         u8         reserved_at_10[0x10];
4121
4122         u8         reserved_at_20[0x10];
4123         u8         op_mod[0x10];
4124
4125         u8         reserved_at_40[0x40];
4126 };
4127
4128 struct mlx5_ifc_qp_2rst_out_bits {
4129         u8         status[0x8];
4130         u8         reserved_at_8[0x18];
4131
4132         u8         syndrome[0x20];
4133
4134         u8         reserved_at_40[0x40];
4135 };
4136
4137 struct mlx5_ifc_qp_2rst_in_bits {
4138         u8         opcode[0x10];
4139         u8         reserved_at_10[0x10];
4140
4141         u8         reserved_at_20[0x10];
4142         u8         op_mod[0x10];
4143
4144         u8         reserved_at_40[0x8];
4145         u8         qpn[0x18];
4146
4147         u8         reserved_at_60[0x20];
4148 };
4149
4150 struct mlx5_ifc_qp_2err_out_bits {
4151         u8         status[0x8];
4152         u8         reserved_at_8[0x18];
4153
4154         u8         syndrome[0x20];
4155
4156         u8         reserved_at_40[0x40];
4157 };
4158
4159 struct mlx5_ifc_qp_2err_in_bits {
4160         u8         opcode[0x10];
4161         u8         reserved_at_10[0x10];
4162
4163         u8         reserved_at_20[0x10];
4164         u8         op_mod[0x10];
4165
4166         u8         reserved_at_40[0x8];
4167         u8         qpn[0x18];
4168
4169         u8         reserved_at_60[0x20];
4170 };
4171
4172 struct mlx5_ifc_page_fault_resume_out_bits {
4173         u8         status[0x8];
4174         u8         reserved_at_8[0x18];
4175
4176         u8         syndrome[0x20];
4177
4178         u8         reserved_at_40[0x40];
4179 };
4180
4181 struct mlx5_ifc_page_fault_resume_in_bits {
4182         u8         opcode[0x10];
4183         u8         reserved_at_10[0x10];
4184
4185         u8         reserved_at_20[0x10];
4186         u8         op_mod[0x10];
4187
4188         u8         error[0x1];
4189         u8         reserved_at_41[0x4];
4190         u8         rdma[0x1];
4191         u8         read_write[0x1];
4192         u8         req_res[0x1];
4193         u8         qpn[0x18];
4194
4195         u8         reserved_at_60[0x20];
4196 };
4197
4198 struct mlx5_ifc_nop_out_bits {
4199         u8         status[0x8];
4200         u8         reserved_at_8[0x18];
4201
4202         u8         syndrome[0x20];
4203
4204         u8         reserved_at_40[0x40];
4205 };
4206
4207 struct mlx5_ifc_nop_in_bits {
4208         u8         opcode[0x10];
4209         u8         reserved_at_10[0x10];
4210
4211         u8         reserved_at_20[0x10];
4212         u8         op_mod[0x10];
4213
4214         u8         reserved_at_40[0x40];
4215 };
4216
4217 struct mlx5_ifc_modify_vport_state_out_bits {
4218         u8         status[0x8];
4219         u8         reserved_at_8[0x18];
4220
4221         u8         syndrome[0x20];
4222
4223         u8         reserved_at_40[0x40];
4224 };
4225
4226 struct mlx5_ifc_modify_vport_state_in_bits {
4227         u8         opcode[0x10];
4228         u8         reserved_at_10[0x10];
4229
4230         u8         reserved_at_20[0x10];
4231         u8         op_mod[0x10];
4232
4233         u8         other_vport[0x1];
4234         u8         reserved_at_41[0xf];
4235         u8         vport_number[0x10];
4236
4237         u8         reserved_at_60[0x18];
4238         u8         admin_state[0x4];
4239         u8         reserved_at_7c[0x4];
4240 };
4241
4242 struct mlx5_ifc_modify_tis_out_bits {
4243         u8         status[0x8];
4244         u8         reserved_at_8[0x18];
4245
4246         u8         syndrome[0x20];
4247
4248         u8         reserved_at_40[0x40];
4249 };
4250
4251 struct mlx5_ifc_modify_tis_bitmask_bits {
4252         u8         reserved_at_0[0x20];
4253
4254         u8         reserved_at_20[0x1f];
4255         u8         prio[0x1];
4256 };
4257
4258 struct mlx5_ifc_modify_tis_in_bits {
4259         u8         opcode[0x10];
4260         u8         reserved_at_10[0x10];
4261
4262         u8         reserved_at_20[0x10];
4263         u8         op_mod[0x10];
4264
4265         u8         reserved_at_40[0x8];
4266         u8         tisn[0x18];
4267
4268         u8         reserved_at_60[0x20];
4269
4270         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4271
4272         u8         reserved_at_c0[0x40];
4273
4274         struct mlx5_ifc_tisc_bits ctx;
4275 };
4276
4277 struct mlx5_ifc_modify_tir_bitmask_bits {
4278         u8         reserved_at_0[0x20];
4279
4280         u8         reserved_at_20[0x1b];
4281         u8         self_lb_en[0x1];
4282         u8         reserved_at_3c[0x3];
4283         u8         lro[0x1];
4284 };
4285
4286 struct mlx5_ifc_modify_tir_out_bits {
4287         u8         status[0x8];
4288         u8         reserved_at_8[0x18];
4289
4290         u8         syndrome[0x20];
4291
4292         u8         reserved_at_40[0x40];
4293 };
4294
4295 struct mlx5_ifc_modify_tir_in_bits {
4296         u8         opcode[0x10];
4297         u8         reserved_at_10[0x10];
4298
4299         u8         reserved_at_20[0x10];
4300         u8         op_mod[0x10];
4301
4302         u8         reserved_at_40[0x8];
4303         u8         tirn[0x18];
4304
4305         u8         reserved_at_60[0x20];
4306
4307         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4308
4309         u8         reserved_at_c0[0x40];
4310
4311         struct mlx5_ifc_tirc_bits ctx;
4312 };
4313
4314 struct mlx5_ifc_modify_sq_out_bits {
4315         u8         status[0x8];
4316         u8         reserved_at_8[0x18];
4317
4318         u8         syndrome[0x20];
4319
4320         u8         reserved_at_40[0x40];
4321 };
4322
4323 struct mlx5_ifc_modify_sq_in_bits {
4324         u8         opcode[0x10];
4325         u8         reserved_at_10[0x10];
4326
4327         u8         reserved_at_20[0x10];
4328         u8         op_mod[0x10];
4329
4330         u8         sq_state[0x4];
4331         u8         reserved_at_44[0x4];
4332         u8         sqn[0x18];
4333
4334         u8         reserved_at_60[0x20];
4335
4336         u8         modify_bitmask[0x40];
4337
4338         u8         reserved_at_c0[0x40];
4339
4340         struct mlx5_ifc_sqc_bits ctx;
4341 };
4342
4343 struct mlx5_ifc_modify_rqt_out_bits {
4344         u8         status[0x8];
4345         u8         reserved_at_8[0x18];
4346
4347         u8         syndrome[0x20];
4348
4349         u8         reserved_at_40[0x40];
4350 };
4351
4352 struct mlx5_ifc_rqt_bitmask_bits {
4353         u8         reserved_at_0[0x20];
4354
4355         u8         reserved_at_20[0x1f];
4356         u8         rqn_list[0x1];
4357 };
4358
4359 struct mlx5_ifc_modify_rqt_in_bits {
4360         u8         opcode[0x10];
4361         u8         reserved_at_10[0x10];
4362
4363         u8         reserved_at_20[0x10];
4364         u8         op_mod[0x10];
4365
4366         u8         reserved_at_40[0x8];
4367         u8         rqtn[0x18];
4368
4369         u8         reserved_at_60[0x20];
4370
4371         struct mlx5_ifc_rqt_bitmask_bits bitmask;
4372
4373         u8         reserved_at_c0[0x40];
4374
4375         struct mlx5_ifc_rqtc_bits ctx;
4376 };
4377
4378 struct mlx5_ifc_modify_rq_out_bits {
4379         u8         status[0x8];
4380         u8         reserved_at_8[0x18];
4381
4382         u8         syndrome[0x20];
4383
4384         u8         reserved_at_40[0x40];
4385 };
4386
4387 struct mlx5_ifc_modify_rq_in_bits {
4388         u8         opcode[0x10];
4389         u8         reserved_at_10[0x10];
4390
4391         u8         reserved_at_20[0x10];
4392         u8         op_mod[0x10];
4393
4394         u8         rq_state[0x4];
4395         u8         reserved_at_44[0x4];
4396         u8         rqn[0x18];
4397
4398         u8         reserved_at_60[0x20];
4399
4400         u8         modify_bitmask[0x40];
4401
4402         u8         reserved_at_c0[0x40];
4403
4404         struct mlx5_ifc_rqc_bits ctx;
4405 };
4406
4407 struct mlx5_ifc_modify_rmp_out_bits {
4408         u8         status[0x8];
4409         u8         reserved_at_8[0x18];
4410
4411         u8         syndrome[0x20];
4412
4413         u8         reserved_at_40[0x40];
4414 };
4415
4416 struct mlx5_ifc_rmp_bitmask_bits {
4417         u8         reserved_at_0[0x20];
4418
4419         u8         reserved_at_20[0x1f];
4420         u8         lwm[0x1];
4421 };
4422
4423 struct mlx5_ifc_modify_rmp_in_bits {
4424         u8         opcode[0x10];
4425         u8         reserved_at_10[0x10];
4426
4427         u8         reserved_at_20[0x10];
4428         u8         op_mod[0x10];
4429
4430         u8         rmp_state[0x4];
4431         u8         reserved_at_44[0x4];
4432         u8         rmpn[0x18];
4433
4434         u8         reserved_at_60[0x20];
4435
4436         struct mlx5_ifc_rmp_bitmask_bits bitmask;
4437
4438         u8         reserved_at_c0[0x40];
4439
4440         struct mlx5_ifc_rmpc_bits ctx;
4441 };
4442
4443 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4444         u8         status[0x8];
4445         u8         reserved_at_8[0x18];
4446
4447         u8         syndrome[0x20];
4448
4449         u8         reserved_at_40[0x40];
4450 };
4451
4452 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4453         u8         reserved_at_0[0x19];
4454         u8         mtu[0x1];
4455         u8         change_event[0x1];
4456         u8         promisc[0x1];
4457         u8         permanent_address[0x1];
4458         u8         addresses_list[0x1];
4459         u8         roce_en[0x1];
4460         u8         reserved_at_1f[0x1];
4461 };
4462
4463 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4464         u8         opcode[0x10];
4465         u8         reserved_at_10[0x10];
4466
4467         u8         reserved_at_20[0x10];
4468         u8         op_mod[0x10];
4469
4470         u8         other_vport[0x1];
4471         u8         reserved_at_41[0xf];
4472         u8         vport_number[0x10];
4473
4474         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4475
4476         u8         reserved_at_80[0x780];
4477
4478         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4479 };
4480
4481 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4482         u8         status[0x8];
4483         u8         reserved_at_8[0x18];
4484
4485         u8         syndrome[0x20];
4486
4487         u8         reserved_at_40[0x40];
4488 };
4489
4490 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4491         u8         opcode[0x10];
4492         u8         reserved_at_10[0x10];
4493
4494         u8         reserved_at_20[0x10];
4495         u8         op_mod[0x10];
4496
4497         u8         other_vport[0x1];
4498         u8         reserved_at_41[0xb];
4499         u8         port_num[0x4];
4500         u8         vport_number[0x10];
4501
4502         u8         reserved_at_60[0x20];
4503
4504         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4505 };
4506
4507 struct mlx5_ifc_modify_cq_out_bits {
4508         u8         status[0x8];
4509         u8         reserved_at_8[0x18];
4510
4511         u8         syndrome[0x20];
4512
4513         u8         reserved_at_40[0x40];
4514 };
4515
4516 enum {
4517         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
4518         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
4519 };
4520
4521 struct mlx5_ifc_modify_cq_in_bits {
4522         u8         opcode[0x10];
4523         u8         reserved_at_10[0x10];
4524
4525         u8         reserved_at_20[0x10];
4526         u8         op_mod[0x10];
4527
4528         u8         reserved_at_40[0x8];
4529         u8         cqn[0x18];
4530
4531         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4532
4533         struct mlx5_ifc_cqc_bits cq_context;
4534
4535         u8         reserved_at_280[0x600];
4536
4537         u8         pas[0][0x40];
4538 };
4539
4540 struct mlx5_ifc_modify_cong_status_out_bits {
4541         u8         status[0x8];
4542         u8         reserved_at_8[0x18];
4543
4544         u8         syndrome[0x20];
4545
4546         u8         reserved_at_40[0x40];
4547 };
4548
4549 struct mlx5_ifc_modify_cong_status_in_bits {
4550         u8         opcode[0x10];
4551         u8         reserved_at_10[0x10];
4552
4553         u8         reserved_at_20[0x10];
4554         u8         op_mod[0x10];
4555
4556         u8         reserved_at_40[0x18];
4557         u8         priority[0x4];
4558         u8         cong_protocol[0x4];
4559
4560         u8         enable[0x1];
4561         u8         tag_enable[0x1];
4562         u8         reserved_at_62[0x1e];
4563 };
4564
4565 struct mlx5_ifc_modify_cong_params_out_bits {
4566         u8         status[0x8];
4567         u8         reserved_at_8[0x18];
4568
4569         u8         syndrome[0x20];
4570
4571         u8         reserved_at_40[0x40];
4572 };
4573
4574 struct mlx5_ifc_modify_cong_params_in_bits {
4575         u8         opcode[0x10];
4576         u8         reserved_at_10[0x10];
4577
4578         u8         reserved_at_20[0x10];
4579         u8         op_mod[0x10];
4580
4581         u8         reserved_at_40[0x1c];
4582         u8         cong_protocol[0x4];
4583
4584         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4585
4586         u8         reserved_at_80[0x80];
4587
4588         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4589 };
4590
4591 struct mlx5_ifc_manage_pages_out_bits {
4592         u8         status[0x8];
4593         u8         reserved_at_8[0x18];
4594
4595         u8         syndrome[0x20];
4596
4597         u8         output_num_entries[0x20];
4598
4599         u8         reserved_at_60[0x20];
4600
4601         u8         pas[0][0x40];
4602 };
4603
4604 enum {
4605         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
4606         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
4607         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
4608 };
4609
4610 struct mlx5_ifc_manage_pages_in_bits {
4611         u8         opcode[0x10];
4612         u8         reserved_at_10[0x10];
4613
4614         u8         reserved_at_20[0x10];
4615         u8         op_mod[0x10];
4616
4617         u8         reserved_at_40[0x10];
4618         u8         function_id[0x10];
4619
4620         u8         input_num_entries[0x20];
4621
4622         u8         pas[0][0x40];
4623 };
4624
4625 struct mlx5_ifc_mad_ifc_out_bits {
4626         u8         status[0x8];
4627         u8         reserved_at_8[0x18];
4628
4629         u8         syndrome[0x20];
4630
4631         u8         reserved_at_40[0x40];
4632
4633         u8         response_mad_packet[256][0x8];
4634 };
4635
4636 struct mlx5_ifc_mad_ifc_in_bits {
4637         u8         opcode[0x10];
4638         u8         reserved_at_10[0x10];
4639
4640         u8         reserved_at_20[0x10];
4641         u8         op_mod[0x10];
4642
4643         u8         remote_lid[0x10];
4644         u8         reserved_at_50[0x8];
4645         u8         port[0x8];
4646
4647         u8         reserved_at_60[0x20];
4648
4649         u8         mad[256][0x8];
4650 };
4651
4652 struct mlx5_ifc_init_hca_out_bits {
4653         u8         status[0x8];
4654         u8         reserved_at_8[0x18];
4655
4656         u8         syndrome[0x20];
4657
4658         u8         reserved_at_40[0x40];
4659 };
4660
4661 struct mlx5_ifc_init_hca_in_bits {
4662         u8         opcode[0x10];
4663         u8         reserved_at_10[0x10];
4664
4665         u8         reserved_at_20[0x10];
4666         u8         op_mod[0x10];
4667
4668         u8         reserved_at_40[0x40];
4669 };
4670
4671 struct mlx5_ifc_init2rtr_qp_out_bits {
4672         u8         status[0x8];
4673         u8         reserved_at_8[0x18];
4674
4675         u8         syndrome[0x20];
4676
4677         u8         reserved_at_40[0x40];
4678 };
4679
4680 struct mlx5_ifc_init2rtr_qp_in_bits {
4681         u8         opcode[0x10];
4682         u8         reserved_at_10[0x10];
4683
4684         u8         reserved_at_20[0x10];
4685         u8         op_mod[0x10];
4686
4687         u8         reserved_at_40[0x8];
4688         u8         qpn[0x18];
4689
4690         u8         reserved_at_60[0x20];
4691
4692         u8         opt_param_mask[0x20];
4693
4694         u8         reserved_at_a0[0x20];
4695
4696         struct mlx5_ifc_qpc_bits qpc;
4697
4698         u8         reserved_at_800[0x80];
4699 };
4700
4701 struct mlx5_ifc_init2init_qp_out_bits {
4702         u8         status[0x8];
4703         u8         reserved_at_8[0x18];
4704
4705         u8         syndrome[0x20];
4706
4707         u8         reserved_at_40[0x40];
4708 };
4709
4710 struct mlx5_ifc_init2init_qp_in_bits {
4711         u8         opcode[0x10];
4712         u8         reserved_at_10[0x10];
4713
4714         u8         reserved_at_20[0x10];
4715         u8         op_mod[0x10];
4716
4717         u8         reserved_at_40[0x8];
4718         u8         qpn[0x18];
4719
4720         u8         reserved_at_60[0x20];
4721
4722         u8         opt_param_mask[0x20];
4723
4724         u8         reserved_at_a0[0x20];
4725
4726         struct mlx5_ifc_qpc_bits qpc;
4727
4728         u8         reserved_at_800[0x80];
4729 };
4730
4731 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4732         u8         status[0x8];
4733         u8         reserved_at_8[0x18];
4734
4735         u8         syndrome[0x20];
4736
4737         u8         reserved_at_40[0x40];
4738
4739         u8         packet_headers_log[128][0x8];
4740
4741         u8         packet_syndrome[64][0x8];
4742 };
4743
4744 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4745         u8         opcode[0x10];
4746         u8         reserved_at_10[0x10];
4747
4748         u8         reserved_at_20[0x10];
4749         u8         op_mod[0x10];
4750
4751         u8         reserved_at_40[0x40];
4752 };
4753
4754 struct mlx5_ifc_gen_eqe_in_bits {
4755         u8         opcode[0x10];
4756         u8         reserved_at_10[0x10];
4757
4758         u8         reserved_at_20[0x10];
4759         u8         op_mod[0x10];
4760
4761         u8         reserved_at_40[0x18];
4762         u8         eq_number[0x8];
4763
4764         u8         reserved_at_60[0x20];
4765
4766         u8         eqe[64][0x8];
4767 };
4768
4769 struct mlx5_ifc_gen_eq_out_bits {
4770         u8         status[0x8];
4771         u8         reserved_at_8[0x18];
4772
4773         u8         syndrome[0x20];
4774
4775         u8         reserved_at_40[0x40];
4776 };
4777
4778 struct mlx5_ifc_enable_hca_out_bits {
4779         u8         status[0x8];
4780         u8         reserved_at_8[0x18];
4781
4782         u8         syndrome[0x20];
4783
4784         u8         reserved_at_40[0x20];
4785 };
4786
4787 struct mlx5_ifc_enable_hca_in_bits {
4788         u8         opcode[0x10];
4789         u8         reserved_at_10[0x10];
4790
4791         u8         reserved_at_20[0x10];
4792         u8         op_mod[0x10];
4793
4794         u8         reserved_at_40[0x10];
4795         u8         function_id[0x10];
4796
4797         u8         reserved_at_60[0x20];
4798 };
4799
4800 struct mlx5_ifc_drain_dct_out_bits {
4801         u8         status[0x8];
4802         u8         reserved_at_8[0x18];
4803
4804         u8         syndrome[0x20];
4805
4806         u8         reserved_at_40[0x40];
4807 };
4808
4809 struct mlx5_ifc_drain_dct_in_bits {
4810         u8         opcode[0x10];
4811         u8         reserved_at_10[0x10];
4812
4813         u8         reserved_at_20[0x10];
4814         u8         op_mod[0x10];
4815
4816         u8         reserved_at_40[0x8];
4817         u8         dctn[0x18];
4818
4819         u8         reserved_at_60[0x20];
4820 };
4821
4822 struct mlx5_ifc_disable_hca_out_bits {
4823         u8         status[0x8];
4824         u8         reserved_at_8[0x18];
4825
4826         u8         syndrome[0x20];
4827
4828         u8         reserved_at_40[0x20];
4829 };
4830
4831 struct mlx5_ifc_disable_hca_in_bits {
4832         u8         opcode[0x10];
4833         u8         reserved_at_10[0x10];
4834
4835         u8         reserved_at_20[0x10];
4836         u8         op_mod[0x10];
4837
4838         u8         reserved_at_40[0x10];
4839         u8         function_id[0x10];
4840
4841         u8         reserved_at_60[0x20];
4842 };
4843
4844 struct mlx5_ifc_detach_from_mcg_out_bits {
4845         u8         status[0x8];
4846         u8         reserved_at_8[0x18];
4847
4848         u8         syndrome[0x20];
4849
4850         u8         reserved_at_40[0x40];
4851 };
4852
4853 struct mlx5_ifc_detach_from_mcg_in_bits {
4854         u8         opcode[0x10];
4855         u8         reserved_at_10[0x10];
4856
4857         u8         reserved_at_20[0x10];
4858         u8         op_mod[0x10];
4859
4860         u8         reserved_at_40[0x8];
4861         u8         qpn[0x18];
4862
4863         u8         reserved_at_60[0x20];
4864
4865         u8         multicast_gid[16][0x8];
4866 };
4867
4868 struct mlx5_ifc_destroy_xrc_srq_out_bits {
4869         u8         status[0x8];
4870         u8         reserved_at_8[0x18];
4871
4872         u8         syndrome[0x20];
4873
4874         u8         reserved_at_40[0x40];
4875 };
4876
4877 struct mlx5_ifc_destroy_xrc_srq_in_bits {
4878         u8         opcode[0x10];
4879         u8         reserved_at_10[0x10];
4880
4881         u8         reserved_at_20[0x10];
4882         u8         op_mod[0x10];
4883
4884         u8         reserved_at_40[0x8];
4885         u8         xrc_srqn[0x18];
4886
4887         u8         reserved_at_60[0x20];
4888 };
4889
4890 struct mlx5_ifc_destroy_tis_out_bits {
4891         u8         status[0x8];
4892         u8         reserved_at_8[0x18];
4893
4894         u8         syndrome[0x20];
4895
4896         u8         reserved_at_40[0x40];
4897 };
4898
4899 struct mlx5_ifc_destroy_tis_in_bits {
4900         u8         opcode[0x10];
4901         u8         reserved_at_10[0x10];
4902
4903         u8         reserved_at_20[0x10];
4904         u8         op_mod[0x10];
4905
4906         u8         reserved_at_40[0x8];
4907         u8         tisn[0x18];
4908
4909         u8         reserved_at_60[0x20];
4910 };
4911
4912 struct mlx5_ifc_destroy_tir_out_bits {
4913         u8         status[0x8];
4914         u8         reserved_at_8[0x18];
4915
4916         u8         syndrome[0x20];
4917
4918         u8         reserved_at_40[0x40];
4919 };
4920
4921 struct mlx5_ifc_destroy_tir_in_bits {
4922         u8         opcode[0x10];
4923         u8         reserved_at_10[0x10];
4924
4925         u8         reserved_at_20[0x10];
4926         u8         op_mod[0x10];
4927
4928         u8         reserved_at_40[0x8];
4929         u8         tirn[0x18];
4930
4931         u8         reserved_at_60[0x20];
4932 };
4933
4934 struct mlx5_ifc_destroy_srq_out_bits {
4935         u8         status[0x8];
4936         u8         reserved_at_8[0x18];
4937
4938         u8         syndrome[0x20];
4939
4940         u8         reserved_at_40[0x40];
4941 };
4942
4943 struct mlx5_ifc_destroy_srq_in_bits {
4944         u8         opcode[0x10];
4945         u8         reserved_at_10[0x10];
4946
4947         u8         reserved_at_20[0x10];
4948         u8         op_mod[0x10];
4949
4950         u8         reserved_at_40[0x8];
4951         u8         srqn[0x18];
4952
4953         u8         reserved_at_60[0x20];
4954 };
4955
4956 struct mlx5_ifc_destroy_sq_out_bits {
4957         u8         status[0x8];
4958         u8         reserved_at_8[0x18];
4959
4960         u8         syndrome[0x20];
4961
4962         u8         reserved_at_40[0x40];
4963 };
4964
4965 struct mlx5_ifc_destroy_sq_in_bits {
4966         u8         opcode[0x10];
4967         u8         reserved_at_10[0x10];
4968
4969         u8         reserved_at_20[0x10];
4970         u8         op_mod[0x10];
4971
4972         u8         reserved_at_40[0x8];
4973         u8         sqn[0x18];
4974
4975         u8         reserved_at_60[0x20];
4976 };
4977
4978 struct mlx5_ifc_destroy_rqt_out_bits {
4979         u8         status[0x8];
4980         u8         reserved_at_8[0x18];
4981
4982         u8         syndrome[0x20];
4983
4984         u8         reserved_at_40[0x40];
4985 };
4986
4987 struct mlx5_ifc_destroy_rqt_in_bits {
4988         u8         opcode[0x10];
4989         u8         reserved_at_10[0x10];
4990
4991         u8         reserved_at_20[0x10];
4992         u8         op_mod[0x10];
4993
4994         u8         reserved_at_40[0x8];
4995         u8         rqtn[0x18];
4996
4997         u8         reserved_at_60[0x20];
4998 };
4999
5000 struct mlx5_ifc_destroy_rq_out_bits {
5001         u8         status[0x8];
5002         u8         reserved_at_8[0x18];
5003
5004         u8         syndrome[0x20];
5005
5006         u8         reserved_at_40[0x40];
5007 };
5008
5009 struct mlx5_ifc_destroy_rq_in_bits {
5010         u8         opcode[0x10];
5011         u8         reserved_at_10[0x10];
5012
5013         u8         reserved_at_20[0x10];
5014         u8         op_mod[0x10];
5015
5016         u8         reserved_at_40[0x8];
5017         u8         rqn[0x18];
5018
5019         u8         reserved_at_60[0x20];
5020 };
5021
5022 struct mlx5_ifc_destroy_rmp_out_bits {
5023         u8         status[0x8];
5024         u8         reserved_at_8[0x18];
5025
5026         u8         syndrome[0x20];
5027
5028         u8         reserved_at_40[0x40];
5029 };
5030
5031 struct mlx5_ifc_destroy_rmp_in_bits {
5032         u8         opcode[0x10];
5033         u8         reserved_at_10[0x10];
5034
5035         u8         reserved_at_20[0x10];
5036         u8         op_mod[0x10];
5037
5038         u8         reserved_at_40[0x8];
5039         u8         rmpn[0x18];
5040
5041         u8         reserved_at_60[0x20];
5042 };
5043
5044 struct mlx5_ifc_destroy_qp_out_bits {
5045         u8         status[0x8];
5046         u8         reserved_at_8[0x18];
5047
5048         u8         syndrome[0x20];
5049
5050         u8         reserved_at_40[0x40];
5051 };
5052
5053 struct mlx5_ifc_destroy_qp_in_bits {
5054         u8         opcode[0x10];
5055         u8         reserved_at_10[0x10];
5056
5057         u8         reserved_at_20[0x10];
5058         u8         op_mod[0x10];
5059
5060         u8         reserved_at_40[0x8];
5061         u8         qpn[0x18];
5062
5063         u8         reserved_at_60[0x20];
5064 };
5065
5066 struct mlx5_ifc_destroy_psv_out_bits {
5067         u8         status[0x8];
5068         u8         reserved_at_8[0x18];
5069
5070         u8         syndrome[0x20];
5071
5072         u8         reserved_at_40[0x40];
5073 };
5074
5075 struct mlx5_ifc_destroy_psv_in_bits {
5076         u8         opcode[0x10];
5077         u8         reserved_at_10[0x10];
5078
5079         u8         reserved_at_20[0x10];
5080         u8         op_mod[0x10];
5081
5082         u8         reserved_at_40[0x8];
5083         u8         psvn[0x18];
5084
5085         u8         reserved_at_60[0x20];
5086 };
5087
5088 struct mlx5_ifc_destroy_mkey_out_bits {
5089         u8         status[0x8];
5090         u8         reserved_at_8[0x18];
5091
5092         u8         syndrome[0x20];
5093
5094         u8         reserved_at_40[0x40];
5095 };
5096
5097 struct mlx5_ifc_destroy_mkey_in_bits {
5098         u8         opcode[0x10];
5099         u8         reserved_at_10[0x10];
5100
5101         u8         reserved_at_20[0x10];
5102         u8         op_mod[0x10];
5103
5104         u8         reserved_at_40[0x8];
5105         u8         mkey_index[0x18];
5106
5107         u8         reserved_at_60[0x20];
5108 };
5109
5110 struct mlx5_ifc_destroy_flow_table_out_bits {
5111         u8         status[0x8];
5112         u8         reserved_at_8[0x18];
5113
5114         u8         syndrome[0x20];
5115
5116         u8         reserved_at_40[0x40];
5117 };
5118
5119 struct mlx5_ifc_destroy_flow_table_in_bits {
5120         u8         opcode[0x10];
5121         u8         reserved_at_10[0x10];
5122
5123         u8         reserved_at_20[0x10];
5124         u8         op_mod[0x10];
5125
5126         u8         reserved_at_40[0x40];
5127
5128         u8         table_type[0x8];
5129         u8         reserved_at_88[0x18];
5130
5131         u8         reserved_at_a0[0x8];
5132         u8         table_id[0x18];
5133
5134         u8         reserved_at_c0[0x140];
5135 };
5136
5137 struct mlx5_ifc_destroy_flow_group_out_bits {
5138         u8         status[0x8];
5139         u8         reserved_at_8[0x18];
5140
5141         u8         syndrome[0x20];
5142
5143         u8         reserved_at_40[0x40];
5144 };
5145
5146 struct mlx5_ifc_destroy_flow_group_in_bits {
5147         u8         opcode[0x10];
5148         u8         reserved_at_10[0x10];
5149
5150         u8         reserved_at_20[0x10];
5151         u8         op_mod[0x10];
5152
5153         u8         reserved_at_40[0x40];
5154
5155         u8         table_type[0x8];
5156         u8         reserved_at_88[0x18];
5157
5158         u8         reserved_at_a0[0x8];
5159         u8         table_id[0x18];
5160
5161         u8         group_id[0x20];
5162
5163         u8         reserved_at_e0[0x120];
5164 };
5165
5166 struct mlx5_ifc_destroy_eq_out_bits {
5167         u8         status[0x8];
5168         u8         reserved_at_8[0x18];
5169
5170         u8         syndrome[0x20];
5171
5172         u8         reserved_at_40[0x40];
5173 };
5174
5175 struct mlx5_ifc_destroy_eq_in_bits {
5176         u8         opcode[0x10];
5177         u8         reserved_at_10[0x10];
5178
5179         u8         reserved_at_20[0x10];
5180         u8         op_mod[0x10];
5181
5182         u8         reserved_at_40[0x18];
5183         u8         eq_number[0x8];
5184
5185         u8         reserved_at_60[0x20];
5186 };
5187
5188 struct mlx5_ifc_destroy_dct_out_bits {
5189         u8         status[0x8];
5190         u8         reserved_at_8[0x18];
5191
5192         u8         syndrome[0x20];
5193
5194         u8         reserved_at_40[0x40];
5195 };
5196
5197 struct mlx5_ifc_destroy_dct_in_bits {
5198         u8         opcode[0x10];
5199         u8         reserved_at_10[0x10];
5200
5201         u8         reserved_at_20[0x10];
5202         u8         op_mod[0x10];
5203
5204         u8         reserved_at_40[0x8];
5205         u8         dctn[0x18];
5206
5207         u8         reserved_at_60[0x20];
5208 };
5209
5210 struct mlx5_ifc_destroy_cq_out_bits {
5211         u8         status[0x8];
5212         u8         reserved_at_8[0x18];
5213
5214         u8         syndrome[0x20];
5215
5216         u8         reserved_at_40[0x40];
5217 };
5218
5219 struct mlx5_ifc_destroy_cq_in_bits {
5220         u8         opcode[0x10];
5221         u8         reserved_at_10[0x10];
5222
5223         u8         reserved_at_20[0x10];
5224         u8         op_mod[0x10];
5225
5226         u8         reserved_at_40[0x8];
5227         u8         cqn[0x18];
5228
5229         u8         reserved_at_60[0x20];
5230 };
5231
5232 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5233         u8         status[0x8];
5234         u8         reserved_at_8[0x18];
5235
5236         u8         syndrome[0x20];
5237
5238         u8         reserved_at_40[0x40];
5239 };
5240
5241 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5242         u8         opcode[0x10];
5243         u8         reserved_at_10[0x10];
5244
5245         u8         reserved_at_20[0x10];
5246         u8         op_mod[0x10];
5247
5248         u8         reserved_at_40[0x20];
5249
5250         u8         reserved_at_60[0x10];
5251         u8         vxlan_udp_port[0x10];
5252 };
5253
5254 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5255         u8         status[0x8];
5256         u8         reserved_at_8[0x18];
5257
5258         u8         syndrome[0x20];
5259
5260         u8         reserved_at_40[0x40];
5261 };
5262
5263 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5264         u8         opcode[0x10];
5265         u8         reserved_at_10[0x10];
5266
5267         u8         reserved_at_20[0x10];
5268         u8         op_mod[0x10];
5269
5270         u8         reserved_at_40[0x60];
5271
5272         u8         reserved_at_a0[0x8];
5273         u8         table_index[0x18];
5274
5275         u8         reserved_at_c0[0x140];
5276 };
5277
5278 struct mlx5_ifc_delete_fte_out_bits {
5279         u8         status[0x8];
5280         u8         reserved_at_8[0x18];
5281
5282         u8         syndrome[0x20];
5283
5284         u8         reserved_at_40[0x40];
5285 };
5286
5287 struct mlx5_ifc_delete_fte_in_bits {
5288         u8         opcode[0x10];
5289         u8         reserved_at_10[0x10];
5290
5291         u8         reserved_at_20[0x10];
5292         u8         op_mod[0x10];
5293
5294         u8         reserved_at_40[0x40];
5295
5296         u8         table_type[0x8];
5297         u8         reserved_at_88[0x18];
5298
5299         u8         reserved_at_a0[0x8];
5300         u8         table_id[0x18];
5301
5302         u8         reserved_at_c0[0x40];
5303
5304         u8         flow_index[0x20];
5305
5306         u8         reserved_at_120[0xe0];
5307 };
5308
5309 struct mlx5_ifc_dealloc_xrcd_out_bits {
5310         u8         status[0x8];
5311         u8         reserved_at_8[0x18];
5312
5313         u8         syndrome[0x20];
5314
5315         u8         reserved_at_40[0x40];
5316 };
5317
5318 struct mlx5_ifc_dealloc_xrcd_in_bits {
5319         u8         opcode[0x10];
5320         u8         reserved_at_10[0x10];
5321
5322         u8         reserved_at_20[0x10];
5323         u8         op_mod[0x10];
5324
5325         u8         reserved_at_40[0x8];
5326         u8         xrcd[0x18];
5327
5328         u8         reserved_at_60[0x20];
5329 };
5330
5331 struct mlx5_ifc_dealloc_uar_out_bits {
5332         u8         status[0x8];
5333         u8         reserved_at_8[0x18];
5334
5335         u8         syndrome[0x20];
5336
5337         u8         reserved_at_40[0x40];
5338 };
5339
5340 struct mlx5_ifc_dealloc_uar_in_bits {
5341         u8         opcode[0x10];
5342         u8         reserved_at_10[0x10];
5343
5344         u8         reserved_at_20[0x10];
5345         u8         op_mod[0x10];
5346
5347         u8         reserved_at_40[0x8];
5348         u8         uar[0x18];
5349
5350         u8         reserved_at_60[0x20];
5351 };
5352
5353 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5354         u8         status[0x8];
5355         u8         reserved_at_8[0x18];
5356
5357         u8         syndrome[0x20];
5358
5359         u8         reserved_at_40[0x40];
5360 };
5361
5362 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5363         u8         opcode[0x10];
5364         u8         reserved_at_10[0x10];
5365
5366         u8         reserved_at_20[0x10];
5367         u8         op_mod[0x10];
5368
5369         u8         reserved_at_40[0x8];
5370         u8         transport_domain[0x18];
5371
5372         u8         reserved_at_60[0x20];
5373 };
5374
5375 struct mlx5_ifc_dealloc_q_counter_out_bits {
5376         u8         status[0x8];
5377         u8         reserved_at_8[0x18];
5378
5379         u8         syndrome[0x20];
5380
5381         u8         reserved_at_40[0x40];
5382 };
5383
5384 struct mlx5_ifc_dealloc_q_counter_in_bits {
5385         u8         opcode[0x10];
5386         u8         reserved_at_10[0x10];
5387
5388         u8         reserved_at_20[0x10];
5389         u8         op_mod[0x10];
5390
5391         u8         reserved_at_40[0x18];
5392         u8         counter_set_id[0x8];
5393
5394         u8         reserved_at_60[0x20];
5395 };
5396
5397 struct mlx5_ifc_dealloc_pd_out_bits {
5398         u8         status[0x8];
5399         u8         reserved_at_8[0x18];
5400
5401         u8         syndrome[0x20];
5402
5403         u8         reserved_at_40[0x40];
5404 };
5405
5406 struct mlx5_ifc_dealloc_pd_in_bits {
5407         u8         opcode[0x10];
5408         u8         reserved_at_10[0x10];
5409
5410         u8         reserved_at_20[0x10];
5411         u8         op_mod[0x10];
5412
5413         u8         reserved_at_40[0x8];
5414         u8         pd[0x18];
5415
5416         u8         reserved_at_60[0x20];
5417 };
5418
5419 struct mlx5_ifc_create_xrc_srq_out_bits {
5420         u8         status[0x8];
5421         u8         reserved_at_8[0x18];
5422
5423         u8         syndrome[0x20];
5424
5425         u8         reserved_at_40[0x8];
5426         u8         xrc_srqn[0x18];
5427
5428         u8         reserved_at_60[0x20];
5429 };
5430
5431 struct mlx5_ifc_create_xrc_srq_in_bits {
5432         u8         opcode[0x10];
5433         u8         reserved_at_10[0x10];
5434
5435         u8         reserved_at_20[0x10];
5436         u8         op_mod[0x10];
5437
5438         u8         reserved_at_40[0x40];
5439
5440         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5441
5442         u8         reserved_at_280[0x600];
5443
5444         u8         pas[0][0x40];
5445 };
5446
5447 struct mlx5_ifc_create_tis_out_bits {
5448         u8         status[0x8];
5449         u8         reserved_at_8[0x18];
5450
5451         u8         syndrome[0x20];
5452
5453         u8         reserved_at_40[0x8];
5454         u8         tisn[0x18];
5455
5456         u8         reserved_at_60[0x20];
5457 };
5458
5459 struct mlx5_ifc_create_tis_in_bits {
5460         u8         opcode[0x10];
5461         u8         reserved_at_10[0x10];
5462
5463         u8         reserved_at_20[0x10];
5464         u8         op_mod[0x10];
5465
5466         u8         reserved_at_40[0xc0];
5467
5468         struct mlx5_ifc_tisc_bits ctx;
5469 };
5470
5471 struct mlx5_ifc_create_tir_out_bits {
5472         u8         status[0x8];
5473         u8         reserved_at_8[0x18];
5474
5475         u8         syndrome[0x20];
5476
5477         u8         reserved_at_40[0x8];
5478         u8         tirn[0x18];
5479
5480         u8         reserved_at_60[0x20];
5481 };
5482
5483 struct mlx5_ifc_create_tir_in_bits {
5484         u8         opcode[0x10];
5485         u8         reserved_at_10[0x10];
5486
5487         u8         reserved_at_20[0x10];
5488         u8         op_mod[0x10];
5489
5490         u8         reserved_at_40[0xc0];
5491
5492         struct mlx5_ifc_tirc_bits ctx;
5493 };
5494
5495 struct mlx5_ifc_create_srq_out_bits {
5496         u8         status[0x8];
5497         u8         reserved_at_8[0x18];
5498
5499         u8         syndrome[0x20];
5500
5501         u8         reserved_at_40[0x8];
5502         u8         srqn[0x18];
5503
5504         u8         reserved_at_60[0x20];
5505 };
5506
5507 struct mlx5_ifc_create_srq_in_bits {
5508         u8         opcode[0x10];
5509         u8         reserved_at_10[0x10];
5510
5511         u8         reserved_at_20[0x10];
5512         u8         op_mod[0x10];
5513
5514         u8         reserved_at_40[0x40];
5515
5516         struct mlx5_ifc_srqc_bits srq_context_entry;
5517
5518         u8         reserved_at_280[0x600];
5519
5520         u8         pas[0][0x40];
5521 };
5522
5523 struct mlx5_ifc_create_sq_out_bits {
5524         u8         status[0x8];
5525         u8         reserved_at_8[0x18];
5526
5527         u8         syndrome[0x20];
5528
5529         u8         reserved_at_40[0x8];
5530         u8         sqn[0x18];
5531
5532         u8         reserved_at_60[0x20];
5533 };
5534
5535 struct mlx5_ifc_create_sq_in_bits {
5536         u8         opcode[0x10];
5537         u8         reserved_at_10[0x10];
5538
5539         u8         reserved_at_20[0x10];
5540         u8         op_mod[0x10];
5541
5542         u8         reserved_at_40[0xc0];
5543
5544         struct mlx5_ifc_sqc_bits ctx;
5545 };
5546
5547 struct mlx5_ifc_create_rqt_out_bits {
5548         u8         status[0x8];
5549         u8         reserved_at_8[0x18];
5550
5551         u8         syndrome[0x20];
5552
5553         u8         reserved_at_40[0x8];
5554         u8         rqtn[0x18];
5555
5556         u8         reserved_at_60[0x20];
5557 };
5558
5559 struct mlx5_ifc_create_rqt_in_bits {
5560         u8         opcode[0x10];
5561         u8         reserved_at_10[0x10];
5562
5563         u8         reserved_at_20[0x10];
5564         u8         op_mod[0x10];
5565
5566         u8         reserved_at_40[0xc0];
5567
5568         struct mlx5_ifc_rqtc_bits rqt_context;
5569 };
5570
5571 struct mlx5_ifc_create_rq_out_bits {
5572         u8         status[0x8];
5573         u8         reserved_at_8[0x18];
5574
5575         u8         syndrome[0x20];
5576
5577         u8         reserved_at_40[0x8];
5578         u8         rqn[0x18];
5579
5580         u8         reserved_at_60[0x20];
5581 };
5582
5583 struct mlx5_ifc_create_rq_in_bits {
5584         u8         opcode[0x10];
5585         u8         reserved_at_10[0x10];
5586
5587         u8         reserved_at_20[0x10];
5588         u8         op_mod[0x10];
5589
5590         u8         reserved_at_40[0xc0];
5591
5592         struct mlx5_ifc_rqc_bits ctx;
5593 };
5594
5595 struct mlx5_ifc_create_rmp_out_bits {
5596         u8         status[0x8];
5597         u8         reserved_at_8[0x18];
5598
5599         u8         syndrome[0x20];
5600
5601         u8         reserved_at_40[0x8];
5602         u8         rmpn[0x18];
5603
5604         u8         reserved_at_60[0x20];
5605 };
5606
5607 struct mlx5_ifc_create_rmp_in_bits {
5608         u8         opcode[0x10];
5609         u8         reserved_at_10[0x10];
5610
5611         u8         reserved_at_20[0x10];
5612         u8         op_mod[0x10];
5613
5614         u8         reserved_at_40[0xc0];
5615
5616         struct mlx5_ifc_rmpc_bits ctx;
5617 };
5618
5619 struct mlx5_ifc_create_qp_out_bits {
5620         u8         status[0x8];
5621         u8         reserved_at_8[0x18];
5622
5623         u8         syndrome[0x20];
5624
5625         u8         reserved_at_40[0x8];
5626         u8         qpn[0x18];
5627
5628         u8         reserved_at_60[0x20];
5629 };
5630
5631 struct mlx5_ifc_create_qp_in_bits {
5632         u8         opcode[0x10];
5633         u8         reserved_at_10[0x10];
5634
5635         u8         reserved_at_20[0x10];
5636         u8         op_mod[0x10];
5637
5638         u8         reserved_at_40[0x40];
5639
5640         u8         opt_param_mask[0x20];
5641
5642         u8         reserved_at_a0[0x20];
5643
5644         struct mlx5_ifc_qpc_bits qpc;
5645
5646         u8         reserved_at_800[0x80];
5647
5648         u8         pas[0][0x40];
5649 };
5650
5651 struct mlx5_ifc_create_psv_out_bits {
5652         u8         status[0x8];
5653         u8         reserved_at_8[0x18];
5654
5655         u8         syndrome[0x20];
5656
5657         u8         reserved_at_40[0x40];
5658
5659         u8         reserved_at_80[0x8];
5660         u8         psv0_index[0x18];
5661
5662         u8         reserved_at_a0[0x8];
5663         u8         psv1_index[0x18];
5664
5665         u8         reserved_at_c0[0x8];
5666         u8         psv2_index[0x18];
5667
5668         u8         reserved_at_e0[0x8];
5669         u8         psv3_index[0x18];
5670 };
5671
5672 struct mlx5_ifc_create_psv_in_bits {
5673         u8         opcode[0x10];
5674         u8         reserved_at_10[0x10];
5675
5676         u8         reserved_at_20[0x10];
5677         u8         op_mod[0x10];
5678
5679         u8         num_psv[0x4];
5680         u8         reserved_at_44[0x4];
5681         u8         pd[0x18];
5682
5683         u8         reserved_at_60[0x20];
5684 };
5685
5686 struct mlx5_ifc_create_mkey_out_bits {
5687         u8         status[0x8];
5688         u8         reserved_at_8[0x18];
5689
5690         u8         syndrome[0x20];
5691
5692         u8         reserved_at_40[0x8];
5693         u8         mkey_index[0x18];
5694
5695         u8         reserved_at_60[0x20];
5696 };
5697
5698 struct mlx5_ifc_create_mkey_in_bits {
5699         u8         opcode[0x10];
5700         u8         reserved_at_10[0x10];
5701
5702         u8         reserved_at_20[0x10];
5703         u8         op_mod[0x10];
5704
5705         u8         reserved_at_40[0x20];
5706
5707         u8         pg_access[0x1];
5708         u8         reserved_at_61[0x1f];
5709
5710         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5711
5712         u8         reserved_at_280[0x80];
5713
5714         u8         translations_octword_actual_size[0x20];
5715
5716         u8         reserved_at_320[0x560];
5717
5718         u8         klm_pas_mtt[0][0x20];
5719 };
5720
5721 struct mlx5_ifc_create_flow_table_out_bits {
5722         u8         status[0x8];
5723         u8         reserved_at_8[0x18];
5724
5725         u8         syndrome[0x20];
5726
5727         u8         reserved_at_40[0x8];
5728         u8         table_id[0x18];
5729
5730         u8         reserved_at_60[0x20];
5731 };
5732
5733 struct mlx5_ifc_create_flow_table_in_bits {
5734         u8         opcode[0x10];
5735         u8         reserved_at_10[0x10];
5736
5737         u8         reserved_at_20[0x10];
5738         u8         op_mod[0x10];
5739
5740         u8         reserved_at_40[0x40];
5741
5742         u8         table_type[0x8];
5743         u8         reserved_at_88[0x18];
5744
5745         u8         reserved_at_a0[0x20];
5746
5747         u8         reserved_at_c0[0x4];
5748         u8         table_miss_mode[0x4];
5749         u8         level[0x8];
5750         u8         reserved_at_d0[0x8];
5751         u8         log_size[0x8];
5752
5753         u8         reserved_at_e0[0x8];
5754         u8         table_miss_id[0x18];
5755
5756         u8         reserved_at_100[0x100];
5757 };
5758
5759 struct mlx5_ifc_create_flow_group_out_bits {
5760         u8         status[0x8];
5761         u8         reserved_at_8[0x18];
5762
5763         u8         syndrome[0x20];
5764
5765         u8         reserved_at_40[0x8];
5766         u8         group_id[0x18];
5767
5768         u8         reserved_at_60[0x20];
5769 };
5770
5771 enum {
5772         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5773         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5774         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5775 };
5776
5777 struct mlx5_ifc_create_flow_group_in_bits {
5778         u8         opcode[0x10];
5779         u8         reserved_at_10[0x10];
5780
5781         u8         reserved_at_20[0x10];
5782         u8         op_mod[0x10];
5783
5784         u8         reserved_at_40[0x40];
5785
5786         u8         table_type[0x8];
5787         u8         reserved_at_88[0x18];
5788
5789         u8         reserved_at_a0[0x8];
5790         u8         table_id[0x18];
5791
5792         u8         reserved_at_c0[0x20];
5793
5794         u8         start_flow_index[0x20];
5795
5796         u8         reserved_at_100[0x20];
5797
5798         u8         end_flow_index[0x20];
5799
5800         u8         reserved_at_140[0xa0];
5801
5802         u8         reserved_at_1e0[0x18];
5803         u8         match_criteria_enable[0x8];
5804
5805         struct mlx5_ifc_fte_match_param_bits match_criteria;
5806
5807         u8         reserved_at_1200[0xe00];
5808 };
5809
5810 struct mlx5_ifc_create_eq_out_bits {
5811         u8         status[0x8];
5812         u8         reserved_at_8[0x18];
5813
5814         u8         syndrome[0x20];
5815
5816         u8         reserved_at_40[0x18];
5817         u8         eq_number[0x8];
5818
5819         u8         reserved_at_60[0x20];
5820 };
5821
5822 struct mlx5_ifc_create_eq_in_bits {
5823         u8         opcode[0x10];
5824         u8         reserved_at_10[0x10];
5825
5826         u8         reserved_at_20[0x10];
5827         u8         op_mod[0x10];
5828
5829         u8         reserved_at_40[0x40];
5830
5831         struct mlx5_ifc_eqc_bits eq_context_entry;
5832
5833         u8         reserved_at_280[0x40];
5834
5835         u8         event_bitmask[0x40];
5836
5837         u8         reserved_at_300[0x580];
5838
5839         u8         pas[0][0x40];
5840 };
5841
5842 struct mlx5_ifc_create_dct_out_bits {
5843         u8         status[0x8];
5844         u8         reserved_at_8[0x18];
5845
5846         u8         syndrome[0x20];
5847
5848         u8         reserved_at_40[0x8];
5849         u8         dctn[0x18];
5850
5851         u8         reserved_at_60[0x20];
5852 };
5853
5854 struct mlx5_ifc_create_dct_in_bits {
5855         u8         opcode[0x10];
5856         u8         reserved_at_10[0x10];
5857
5858         u8         reserved_at_20[0x10];
5859         u8         op_mod[0x10];
5860
5861         u8         reserved_at_40[0x40];
5862
5863         struct mlx5_ifc_dctc_bits dct_context_entry;
5864
5865         u8         reserved_at_280[0x180];
5866 };
5867
5868 struct mlx5_ifc_create_cq_out_bits {
5869         u8         status[0x8];
5870         u8         reserved_at_8[0x18];
5871
5872         u8         syndrome[0x20];
5873
5874         u8         reserved_at_40[0x8];
5875         u8         cqn[0x18];
5876
5877         u8         reserved_at_60[0x20];
5878 };
5879
5880 struct mlx5_ifc_create_cq_in_bits {
5881         u8         opcode[0x10];
5882         u8         reserved_at_10[0x10];
5883
5884         u8         reserved_at_20[0x10];
5885         u8         op_mod[0x10];
5886
5887         u8         reserved_at_40[0x40];
5888
5889         struct mlx5_ifc_cqc_bits cq_context;
5890
5891         u8         reserved_at_280[0x600];
5892
5893         u8         pas[0][0x40];
5894 };
5895
5896 struct mlx5_ifc_config_int_moderation_out_bits {
5897         u8         status[0x8];
5898         u8         reserved_at_8[0x18];
5899
5900         u8         syndrome[0x20];
5901
5902         u8         reserved_at_40[0x4];
5903         u8         min_delay[0xc];
5904         u8         int_vector[0x10];
5905
5906         u8         reserved_at_60[0x20];
5907 };
5908
5909 enum {
5910         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
5911         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
5912 };
5913
5914 struct mlx5_ifc_config_int_moderation_in_bits {
5915         u8         opcode[0x10];
5916         u8         reserved_at_10[0x10];
5917
5918         u8         reserved_at_20[0x10];
5919         u8         op_mod[0x10];
5920
5921         u8         reserved_at_40[0x4];
5922         u8         min_delay[0xc];
5923         u8         int_vector[0x10];
5924
5925         u8         reserved_at_60[0x20];
5926 };
5927
5928 struct mlx5_ifc_attach_to_mcg_out_bits {
5929         u8         status[0x8];
5930         u8         reserved_at_8[0x18];
5931
5932         u8         syndrome[0x20];
5933
5934         u8         reserved_at_40[0x40];
5935 };
5936
5937 struct mlx5_ifc_attach_to_mcg_in_bits {
5938         u8         opcode[0x10];
5939         u8         reserved_at_10[0x10];
5940
5941         u8         reserved_at_20[0x10];
5942         u8         op_mod[0x10];
5943
5944         u8         reserved_at_40[0x8];
5945         u8         qpn[0x18];
5946
5947         u8         reserved_at_60[0x20];
5948
5949         u8         multicast_gid[16][0x8];
5950 };
5951
5952 struct mlx5_ifc_arm_xrc_srq_out_bits {
5953         u8         status[0x8];
5954         u8         reserved_at_8[0x18];
5955
5956         u8         syndrome[0x20];
5957
5958         u8         reserved_at_40[0x40];
5959 };
5960
5961 enum {
5962         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
5963 };
5964
5965 struct mlx5_ifc_arm_xrc_srq_in_bits {
5966         u8         opcode[0x10];
5967         u8         reserved_at_10[0x10];
5968
5969         u8         reserved_at_20[0x10];
5970         u8         op_mod[0x10];
5971
5972         u8         reserved_at_40[0x8];
5973         u8         xrc_srqn[0x18];
5974
5975         u8         reserved_at_60[0x10];
5976         u8         lwm[0x10];
5977 };
5978
5979 struct mlx5_ifc_arm_rq_out_bits {
5980         u8         status[0x8];
5981         u8         reserved_at_8[0x18];
5982
5983         u8         syndrome[0x20];
5984
5985         u8         reserved_at_40[0x40];
5986 };
5987
5988 enum {
5989         MLX5_ARM_RQ_IN_OP_MOD_SRQ_  = 0x1,
5990 };
5991
5992 struct mlx5_ifc_arm_rq_in_bits {
5993         u8         opcode[0x10];
5994         u8         reserved_at_10[0x10];
5995
5996         u8         reserved_at_20[0x10];
5997         u8         op_mod[0x10];
5998
5999         u8         reserved_at_40[0x8];
6000         u8         srq_number[0x18];
6001
6002         u8         reserved_at_60[0x10];
6003         u8         lwm[0x10];
6004 };
6005
6006 struct mlx5_ifc_arm_dct_out_bits {
6007         u8         status[0x8];
6008         u8         reserved_at_8[0x18];
6009
6010         u8         syndrome[0x20];
6011
6012         u8         reserved_at_40[0x40];
6013 };
6014
6015 struct mlx5_ifc_arm_dct_in_bits {
6016         u8         opcode[0x10];
6017         u8         reserved_at_10[0x10];
6018
6019         u8         reserved_at_20[0x10];
6020         u8         op_mod[0x10];
6021
6022         u8         reserved_at_40[0x8];
6023         u8         dct_number[0x18];
6024
6025         u8         reserved_at_60[0x20];
6026 };
6027
6028 struct mlx5_ifc_alloc_xrcd_out_bits {
6029         u8         status[0x8];
6030         u8         reserved_at_8[0x18];
6031
6032         u8         syndrome[0x20];
6033
6034         u8         reserved_at_40[0x8];
6035         u8         xrcd[0x18];
6036
6037         u8         reserved_at_60[0x20];
6038 };
6039
6040 struct mlx5_ifc_alloc_xrcd_in_bits {
6041         u8         opcode[0x10];
6042         u8         reserved_at_10[0x10];
6043
6044         u8         reserved_at_20[0x10];
6045         u8         op_mod[0x10];
6046
6047         u8         reserved_at_40[0x40];
6048 };
6049
6050 struct mlx5_ifc_alloc_uar_out_bits {
6051         u8         status[0x8];
6052         u8         reserved_at_8[0x18];
6053
6054         u8         syndrome[0x20];
6055
6056         u8         reserved_at_40[0x8];
6057         u8         uar[0x18];
6058
6059         u8         reserved_at_60[0x20];
6060 };
6061
6062 struct mlx5_ifc_alloc_uar_in_bits {
6063         u8         opcode[0x10];
6064         u8         reserved_at_10[0x10];
6065
6066         u8         reserved_at_20[0x10];
6067         u8         op_mod[0x10];
6068
6069         u8         reserved_at_40[0x40];
6070 };
6071
6072 struct mlx5_ifc_alloc_transport_domain_out_bits {
6073         u8         status[0x8];
6074         u8         reserved_at_8[0x18];
6075
6076         u8         syndrome[0x20];
6077
6078         u8         reserved_at_40[0x8];
6079         u8         transport_domain[0x18];
6080
6081         u8         reserved_at_60[0x20];
6082 };
6083
6084 struct mlx5_ifc_alloc_transport_domain_in_bits {
6085         u8         opcode[0x10];
6086         u8         reserved_at_10[0x10];
6087
6088         u8         reserved_at_20[0x10];
6089         u8         op_mod[0x10];
6090
6091         u8         reserved_at_40[0x40];
6092 };
6093
6094 struct mlx5_ifc_alloc_q_counter_out_bits {
6095         u8         status[0x8];
6096         u8         reserved_at_8[0x18];
6097
6098         u8         syndrome[0x20];
6099
6100         u8         reserved_at_40[0x18];
6101         u8         counter_set_id[0x8];
6102
6103         u8         reserved_at_60[0x20];
6104 };
6105
6106 struct mlx5_ifc_alloc_q_counter_in_bits {
6107         u8         opcode[0x10];
6108         u8         reserved_at_10[0x10];
6109
6110         u8         reserved_at_20[0x10];
6111         u8         op_mod[0x10];
6112
6113         u8         reserved_at_40[0x40];
6114 };
6115
6116 struct mlx5_ifc_alloc_pd_out_bits {
6117         u8         status[0x8];
6118         u8         reserved_at_8[0x18];
6119
6120         u8         syndrome[0x20];
6121
6122         u8         reserved_at_40[0x8];
6123         u8         pd[0x18];
6124
6125         u8         reserved_at_60[0x20];
6126 };
6127
6128 struct mlx5_ifc_alloc_pd_in_bits {
6129         u8         opcode[0x10];
6130         u8         reserved_at_10[0x10];
6131
6132         u8         reserved_at_20[0x10];
6133         u8         op_mod[0x10];
6134
6135         u8         reserved_at_40[0x40];
6136 };
6137
6138 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6139         u8         status[0x8];
6140         u8         reserved_at_8[0x18];
6141
6142         u8         syndrome[0x20];
6143
6144         u8         reserved_at_40[0x40];
6145 };
6146
6147 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6148         u8         opcode[0x10];
6149         u8         reserved_at_10[0x10];
6150
6151         u8         reserved_at_20[0x10];
6152         u8         op_mod[0x10];
6153
6154         u8         reserved_at_40[0x20];
6155
6156         u8         reserved_at_60[0x10];
6157         u8         vxlan_udp_port[0x10];
6158 };
6159
6160 struct mlx5_ifc_access_register_out_bits {
6161         u8         status[0x8];
6162         u8         reserved_at_8[0x18];
6163
6164         u8         syndrome[0x20];
6165
6166         u8         reserved_at_40[0x40];
6167
6168         u8         register_data[0][0x20];
6169 };
6170
6171 enum {
6172         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
6173         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
6174 };
6175
6176 struct mlx5_ifc_access_register_in_bits {
6177         u8         opcode[0x10];
6178         u8         reserved_at_10[0x10];
6179
6180         u8         reserved_at_20[0x10];
6181         u8         op_mod[0x10];
6182
6183         u8         reserved_at_40[0x10];
6184         u8         register_id[0x10];
6185
6186         u8         argument[0x20];
6187
6188         u8         register_data[0][0x20];
6189 };
6190
6191 struct mlx5_ifc_sltp_reg_bits {
6192         u8         status[0x4];
6193         u8         version[0x4];
6194         u8         local_port[0x8];
6195         u8         pnat[0x2];
6196         u8         reserved_at_12[0x2];
6197         u8         lane[0x4];
6198         u8         reserved_at_18[0x8];
6199
6200         u8         reserved_at_20[0x20];
6201
6202         u8         reserved_at_40[0x7];
6203         u8         polarity[0x1];
6204         u8         ob_tap0[0x8];
6205         u8         ob_tap1[0x8];
6206         u8         ob_tap2[0x8];
6207
6208         u8         reserved_at_60[0xc];
6209         u8         ob_preemp_mode[0x4];
6210         u8         ob_reg[0x8];
6211         u8         ob_bias[0x8];
6212
6213         u8         reserved_at_80[0x20];
6214 };
6215
6216 struct mlx5_ifc_slrg_reg_bits {
6217         u8         status[0x4];
6218         u8         version[0x4];
6219         u8         local_port[0x8];
6220         u8         pnat[0x2];
6221         u8         reserved_at_12[0x2];
6222         u8         lane[0x4];
6223         u8         reserved_at_18[0x8];
6224
6225         u8         time_to_link_up[0x10];
6226         u8         reserved_at_30[0xc];
6227         u8         grade_lane_speed[0x4];
6228
6229         u8         grade_version[0x8];
6230         u8         grade[0x18];
6231
6232         u8         reserved_at_60[0x4];
6233         u8         height_grade_type[0x4];
6234         u8         height_grade[0x18];
6235
6236         u8         height_dz[0x10];
6237         u8         height_dv[0x10];
6238
6239         u8         reserved_at_a0[0x10];
6240         u8         height_sigma[0x10];
6241
6242         u8         reserved_at_c0[0x20];
6243
6244         u8         reserved_at_e0[0x4];
6245         u8         phase_grade_type[0x4];
6246         u8         phase_grade[0x18];
6247
6248         u8         reserved_at_100[0x8];
6249         u8         phase_eo_pos[0x8];
6250         u8         reserved_at_110[0x8];
6251         u8         phase_eo_neg[0x8];
6252
6253         u8         ffe_set_tested[0x10];
6254         u8         test_errors_per_lane[0x10];
6255 };
6256
6257 struct mlx5_ifc_pvlc_reg_bits {
6258         u8         reserved_at_0[0x8];
6259         u8         local_port[0x8];
6260         u8         reserved_at_10[0x10];
6261
6262         u8         reserved_at_20[0x1c];
6263         u8         vl_hw_cap[0x4];
6264
6265         u8         reserved_at_40[0x1c];
6266         u8         vl_admin[0x4];
6267
6268         u8         reserved_at_60[0x1c];
6269         u8         vl_operational[0x4];
6270 };
6271
6272 struct mlx5_ifc_pude_reg_bits {
6273         u8         swid[0x8];
6274         u8         local_port[0x8];
6275         u8         reserved_at_10[0x4];
6276         u8         admin_status[0x4];
6277         u8         reserved_at_18[0x4];
6278         u8         oper_status[0x4];
6279
6280         u8         reserved_at_20[0x60];
6281 };
6282
6283 struct mlx5_ifc_ptys_reg_bits {
6284         u8         reserved_at_0[0x8];
6285         u8         local_port[0x8];
6286         u8         reserved_at_10[0xd];
6287         u8         proto_mask[0x3];
6288
6289         u8         reserved_at_20[0x40];
6290
6291         u8         eth_proto_capability[0x20];
6292
6293         u8         ib_link_width_capability[0x10];
6294         u8         ib_proto_capability[0x10];
6295
6296         u8         reserved_at_a0[0x20];
6297
6298         u8         eth_proto_admin[0x20];
6299
6300         u8         ib_link_width_admin[0x10];
6301         u8         ib_proto_admin[0x10];
6302
6303         u8         reserved_at_100[0x20];
6304
6305         u8         eth_proto_oper[0x20];
6306
6307         u8         ib_link_width_oper[0x10];
6308         u8         ib_proto_oper[0x10];
6309
6310         u8         reserved_at_160[0x20];
6311
6312         u8         eth_proto_lp_advertise[0x20];
6313
6314         u8         reserved_at_1a0[0x60];
6315 };
6316
6317 struct mlx5_ifc_ptas_reg_bits {
6318         u8         reserved_at_0[0x20];
6319
6320         u8         algorithm_options[0x10];
6321         u8         reserved_at_30[0x4];
6322         u8         repetitions_mode[0x4];
6323         u8         num_of_repetitions[0x8];
6324
6325         u8         grade_version[0x8];
6326         u8         height_grade_type[0x4];
6327         u8         phase_grade_type[0x4];
6328         u8         height_grade_weight[0x8];
6329         u8         phase_grade_weight[0x8];
6330
6331         u8         gisim_measure_bits[0x10];
6332         u8         adaptive_tap_measure_bits[0x10];
6333
6334         u8         ber_bath_high_error_threshold[0x10];
6335         u8         ber_bath_mid_error_threshold[0x10];
6336
6337         u8         ber_bath_low_error_threshold[0x10];
6338         u8         one_ratio_high_threshold[0x10];
6339
6340         u8         one_ratio_high_mid_threshold[0x10];
6341         u8         one_ratio_low_mid_threshold[0x10];
6342
6343         u8         one_ratio_low_threshold[0x10];
6344         u8         ndeo_error_threshold[0x10];
6345
6346         u8         mixer_offset_step_size[0x10];
6347         u8         reserved_at_110[0x8];
6348         u8         mix90_phase_for_voltage_bath[0x8];
6349
6350         u8         mixer_offset_start[0x10];
6351         u8         mixer_offset_end[0x10];
6352
6353         u8         reserved_at_140[0x15];
6354         u8         ber_test_time[0xb];
6355 };
6356
6357 struct mlx5_ifc_pspa_reg_bits {
6358         u8         swid[0x8];
6359         u8         local_port[0x8];
6360         u8         sub_port[0x8];
6361         u8         reserved_at_18[0x8];
6362
6363         u8         reserved_at_20[0x20];
6364 };
6365
6366 struct mlx5_ifc_pqdr_reg_bits {
6367         u8         reserved_at_0[0x8];
6368         u8         local_port[0x8];
6369         u8         reserved_at_10[0x5];
6370         u8         prio[0x3];
6371         u8         reserved_at_18[0x6];
6372         u8         mode[0x2];
6373
6374         u8         reserved_at_20[0x20];
6375
6376         u8         reserved_at_40[0x10];
6377         u8         min_threshold[0x10];
6378
6379         u8         reserved_at_60[0x10];
6380         u8         max_threshold[0x10];
6381
6382         u8         reserved_at_80[0x10];
6383         u8         mark_probability_denominator[0x10];
6384
6385         u8         reserved_at_a0[0x60];
6386 };
6387
6388 struct mlx5_ifc_ppsc_reg_bits {
6389         u8         reserved_at_0[0x8];
6390         u8         local_port[0x8];
6391         u8         reserved_at_10[0x10];
6392
6393         u8         reserved_at_20[0x60];
6394
6395         u8         reserved_at_80[0x1c];
6396         u8         wrps_admin[0x4];
6397
6398         u8         reserved_at_a0[0x1c];
6399         u8         wrps_status[0x4];
6400
6401         u8         reserved_at_c0[0x8];
6402         u8         up_threshold[0x8];
6403         u8         reserved_at_d0[0x8];
6404         u8         down_threshold[0x8];
6405
6406         u8         reserved_at_e0[0x20];
6407
6408         u8         reserved_at_100[0x1c];
6409         u8         srps_admin[0x4];
6410
6411         u8         reserved_at_120[0x1c];
6412         u8         srps_status[0x4];
6413
6414         u8         reserved_at_140[0x40];
6415 };
6416
6417 struct mlx5_ifc_pplr_reg_bits {
6418         u8         reserved_at_0[0x8];
6419         u8         local_port[0x8];
6420         u8         reserved_at_10[0x10];
6421
6422         u8         reserved_at_20[0x8];
6423         u8         lb_cap[0x8];
6424         u8         reserved_at_30[0x8];
6425         u8         lb_en[0x8];
6426 };
6427
6428 struct mlx5_ifc_pplm_reg_bits {
6429         u8         reserved_at_0[0x8];
6430         u8         local_port[0x8];
6431         u8         reserved_at_10[0x10];
6432
6433         u8         reserved_at_20[0x20];
6434
6435         u8         port_profile_mode[0x8];
6436         u8         static_port_profile[0x8];
6437         u8         active_port_profile[0x8];
6438         u8         reserved_at_58[0x8];
6439
6440         u8         retransmission_active[0x8];
6441         u8         fec_mode_active[0x18];
6442
6443         u8         reserved_at_80[0x20];
6444 };
6445
6446 struct mlx5_ifc_ppcnt_reg_bits {
6447         u8         swid[0x8];
6448         u8         local_port[0x8];
6449         u8         pnat[0x2];
6450         u8         reserved_at_12[0x8];
6451         u8         grp[0x6];
6452
6453         u8         clr[0x1];
6454         u8         reserved_at_21[0x1c];
6455         u8         prio_tc[0x3];
6456
6457         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6458 };
6459
6460 struct mlx5_ifc_ppad_reg_bits {
6461         u8         reserved_at_0[0x3];
6462         u8         single_mac[0x1];
6463         u8         reserved_at_4[0x4];
6464         u8         local_port[0x8];
6465         u8         mac_47_32[0x10];
6466
6467         u8         mac_31_0[0x20];
6468
6469         u8         reserved_at_40[0x40];
6470 };
6471
6472 struct mlx5_ifc_pmtu_reg_bits {
6473         u8         reserved_at_0[0x8];
6474         u8         local_port[0x8];
6475         u8         reserved_at_10[0x10];
6476
6477         u8         max_mtu[0x10];
6478         u8         reserved_at_30[0x10];
6479
6480         u8         admin_mtu[0x10];
6481         u8         reserved_at_50[0x10];
6482
6483         u8         oper_mtu[0x10];
6484         u8         reserved_at_70[0x10];
6485 };
6486
6487 struct mlx5_ifc_pmpr_reg_bits {
6488         u8         reserved_at_0[0x8];
6489         u8         module[0x8];
6490         u8         reserved_at_10[0x10];
6491
6492         u8         reserved_at_20[0x18];
6493         u8         attenuation_5g[0x8];
6494
6495         u8         reserved_at_40[0x18];
6496         u8         attenuation_7g[0x8];
6497
6498         u8         reserved_at_60[0x18];
6499         u8         attenuation_12g[0x8];
6500 };
6501
6502 struct mlx5_ifc_pmpe_reg_bits {
6503         u8         reserved_at_0[0x8];
6504         u8         module[0x8];
6505         u8         reserved_at_10[0xc];
6506         u8         module_status[0x4];
6507
6508         u8         reserved_at_20[0x60];
6509 };
6510
6511 struct mlx5_ifc_pmpc_reg_bits {
6512         u8         module_state_updated[32][0x8];
6513 };
6514
6515 struct mlx5_ifc_pmlpn_reg_bits {
6516         u8         reserved_at_0[0x4];
6517         u8         mlpn_status[0x4];
6518         u8         local_port[0x8];
6519         u8         reserved_at_10[0x10];
6520
6521         u8         e[0x1];
6522         u8         reserved_at_21[0x1f];
6523 };
6524
6525 struct mlx5_ifc_pmlp_reg_bits {
6526         u8         rxtx[0x1];
6527         u8         reserved_at_1[0x7];
6528         u8         local_port[0x8];
6529         u8         reserved_at_10[0x8];
6530         u8         width[0x8];
6531
6532         u8         lane0_module_mapping[0x20];
6533
6534         u8         lane1_module_mapping[0x20];
6535
6536         u8         lane2_module_mapping[0x20];
6537
6538         u8         lane3_module_mapping[0x20];
6539
6540         u8         reserved_at_a0[0x160];
6541 };
6542
6543 struct mlx5_ifc_pmaos_reg_bits {
6544         u8         reserved_at_0[0x8];
6545         u8         module[0x8];
6546         u8         reserved_at_10[0x4];
6547         u8         admin_status[0x4];
6548         u8         reserved_at_18[0x4];
6549         u8         oper_status[0x4];
6550
6551         u8         ase[0x1];
6552         u8         ee[0x1];
6553         u8         reserved_at_22[0x1c];
6554         u8         e[0x2];
6555
6556         u8         reserved_at_40[0x40];
6557 };
6558
6559 struct mlx5_ifc_plpc_reg_bits {
6560         u8         reserved_at_0[0x4];
6561         u8         profile_id[0xc];
6562         u8         reserved_at_10[0x4];
6563         u8         proto_mask[0x4];
6564         u8         reserved_at_18[0x8];
6565
6566         u8         reserved_at_20[0x10];
6567         u8         lane_speed[0x10];
6568
6569         u8         reserved_at_40[0x17];
6570         u8         lpbf[0x1];
6571         u8         fec_mode_policy[0x8];
6572
6573         u8         retransmission_capability[0x8];
6574         u8         fec_mode_capability[0x18];
6575
6576         u8         retransmission_support_admin[0x8];
6577         u8         fec_mode_support_admin[0x18];
6578
6579         u8         retransmission_request_admin[0x8];
6580         u8         fec_mode_request_admin[0x18];
6581
6582         u8         reserved_at_c0[0x80];
6583 };
6584
6585 struct mlx5_ifc_plib_reg_bits {
6586         u8         reserved_at_0[0x8];
6587         u8         local_port[0x8];
6588         u8         reserved_at_10[0x8];
6589         u8         ib_port[0x8];
6590
6591         u8         reserved_at_20[0x60];
6592 };
6593
6594 struct mlx5_ifc_plbf_reg_bits {
6595         u8         reserved_at_0[0x8];
6596         u8         local_port[0x8];
6597         u8         reserved_at_10[0xd];
6598         u8         lbf_mode[0x3];
6599
6600         u8         reserved_at_20[0x20];
6601 };
6602
6603 struct mlx5_ifc_pipg_reg_bits {
6604         u8         reserved_at_0[0x8];
6605         u8         local_port[0x8];
6606         u8         reserved_at_10[0x10];
6607
6608         u8         dic[0x1];
6609         u8         reserved_at_21[0x19];
6610         u8         ipg[0x4];
6611         u8         reserved_at_3e[0x2];
6612 };
6613
6614 struct mlx5_ifc_pifr_reg_bits {
6615         u8         reserved_at_0[0x8];
6616         u8         local_port[0x8];
6617         u8         reserved_at_10[0x10];
6618
6619         u8         reserved_at_20[0xe0];
6620
6621         u8         port_filter[8][0x20];
6622
6623         u8         port_filter_update_en[8][0x20];
6624 };
6625
6626 struct mlx5_ifc_pfcc_reg_bits {
6627         u8         reserved_at_0[0x8];
6628         u8         local_port[0x8];
6629         u8         reserved_at_10[0x10];
6630
6631         u8         ppan[0x4];
6632         u8         reserved_at_24[0x4];
6633         u8         prio_mask_tx[0x8];
6634         u8         reserved_at_30[0x8];
6635         u8         prio_mask_rx[0x8];
6636
6637         u8         pptx[0x1];
6638         u8         aptx[0x1];
6639         u8         reserved_at_42[0x6];
6640         u8         pfctx[0x8];
6641         u8         reserved_at_50[0x10];
6642
6643         u8         pprx[0x1];
6644         u8         aprx[0x1];
6645         u8         reserved_at_62[0x6];
6646         u8         pfcrx[0x8];
6647         u8         reserved_at_70[0x10];
6648
6649         u8         reserved_at_80[0x80];
6650 };
6651
6652 struct mlx5_ifc_pelc_reg_bits {
6653         u8         op[0x4];
6654         u8         reserved_at_4[0x4];
6655         u8         local_port[0x8];
6656         u8         reserved_at_10[0x10];
6657
6658         u8         op_admin[0x8];
6659         u8         op_capability[0x8];
6660         u8         op_request[0x8];
6661         u8         op_active[0x8];
6662
6663         u8         admin[0x40];
6664
6665         u8         capability[0x40];
6666
6667         u8         request[0x40];
6668
6669         u8         active[0x40];
6670
6671         u8         reserved_at_140[0x80];
6672 };
6673
6674 struct mlx5_ifc_peir_reg_bits {
6675         u8         reserved_at_0[0x8];
6676         u8         local_port[0x8];
6677         u8         reserved_at_10[0x10];
6678
6679         u8         reserved_at_20[0xc];
6680         u8         error_count[0x4];
6681         u8         reserved_at_30[0x10];
6682
6683         u8         reserved_at_40[0xc];
6684         u8         lane[0x4];
6685         u8         reserved_at_50[0x8];
6686         u8         error_type[0x8];
6687 };
6688
6689 struct mlx5_ifc_pcap_reg_bits {
6690         u8         reserved_at_0[0x8];
6691         u8         local_port[0x8];
6692         u8         reserved_at_10[0x10];
6693
6694         u8         port_capability_mask[4][0x20];
6695 };
6696
6697 struct mlx5_ifc_paos_reg_bits {
6698         u8         swid[0x8];
6699         u8         local_port[0x8];
6700         u8         reserved_at_10[0x4];
6701         u8         admin_status[0x4];
6702         u8         reserved_at_18[0x4];
6703         u8         oper_status[0x4];
6704
6705         u8         ase[0x1];
6706         u8         ee[0x1];
6707         u8         reserved_at_22[0x1c];
6708         u8         e[0x2];
6709
6710         u8         reserved_at_40[0x40];
6711 };
6712
6713 struct mlx5_ifc_pamp_reg_bits {
6714         u8         reserved_at_0[0x8];
6715         u8         opamp_group[0x8];
6716         u8         reserved_at_10[0xc];
6717         u8         opamp_group_type[0x4];
6718
6719         u8         start_index[0x10];
6720         u8         reserved_at_30[0x4];
6721         u8         num_of_indices[0xc];
6722
6723         u8         index_data[18][0x10];
6724 };
6725
6726 struct mlx5_ifc_lane_2_module_mapping_bits {
6727         u8         reserved_at_0[0x6];
6728         u8         rx_lane[0x2];
6729         u8         reserved_at_8[0x6];
6730         u8         tx_lane[0x2];
6731         u8         reserved_at_10[0x8];
6732         u8         module[0x8];
6733 };
6734
6735 struct mlx5_ifc_bufferx_reg_bits {
6736         u8         reserved_at_0[0x6];
6737         u8         lossy[0x1];
6738         u8         epsb[0x1];
6739         u8         reserved_at_8[0xc];
6740         u8         size[0xc];
6741
6742         u8         xoff_threshold[0x10];
6743         u8         xon_threshold[0x10];
6744 };
6745
6746 struct mlx5_ifc_set_node_in_bits {
6747         u8         node_description[64][0x8];
6748 };
6749
6750 struct mlx5_ifc_register_power_settings_bits {
6751         u8         reserved_at_0[0x18];
6752         u8         power_settings_level[0x8];
6753
6754         u8         reserved_at_20[0x60];
6755 };
6756
6757 struct mlx5_ifc_register_host_endianness_bits {
6758         u8         he[0x1];
6759         u8         reserved_at_1[0x1f];
6760
6761         u8         reserved_at_20[0x60];
6762 };
6763
6764 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6765         u8         reserved_at_0[0x20];
6766
6767         u8         mkey[0x20];
6768
6769         u8         addressh_63_32[0x20];
6770
6771         u8         addressl_31_0[0x20];
6772 };
6773
6774 struct mlx5_ifc_ud_adrs_vector_bits {
6775         u8         dc_key[0x40];
6776
6777         u8         ext[0x1];
6778         u8         reserved_at_41[0x7];
6779         u8         destination_qp_dct[0x18];
6780
6781         u8         static_rate[0x4];
6782         u8         sl_eth_prio[0x4];
6783         u8         fl[0x1];
6784         u8         mlid[0x7];
6785         u8         rlid_udp_sport[0x10];
6786
6787         u8         reserved_at_80[0x20];
6788
6789         u8         rmac_47_16[0x20];
6790
6791         u8         rmac_15_0[0x10];
6792         u8         tclass[0x8];
6793         u8         hop_limit[0x8];
6794
6795         u8         reserved_at_e0[0x1];
6796         u8         grh[0x1];
6797         u8         reserved_at_e2[0x2];
6798         u8         src_addr_index[0x8];
6799         u8         flow_label[0x14];
6800
6801         u8         rgid_rip[16][0x8];
6802 };
6803
6804 struct mlx5_ifc_pages_req_event_bits {
6805         u8         reserved_at_0[0x10];
6806         u8         function_id[0x10];
6807
6808         u8         num_pages[0x20];
6809
6810         u8         reserved_at_40[0xa0];
6811 };
6812
6813 struct mlx5_ifc_eqe_bits {
6814         u8         reserved_at_0[0x8];
6815         u8         event_type[0x8];
6816         u8         reserved_at_10[0x8];
6817         u8         event_sub_type[0x8];
6818
6819         u8         reserved_at_20[0xe0];
6820
6821         union mlx5_ifc_event_auto_bits event_data;
6822
6823         u8         reserved_at_1e0[0x10];
6824         u8         signature[0x8];
6825         u8         reserved_at_1f8[0x7];
6826         u8         owner[0x1];
6827 };
6828
6829 enum {
6830         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
6831 };
6832
6833 struct mlx5_ifc_cmd_queue_entry_bits {
6834         u8         type[0x8];
6835         u8         reserved_at_8[0x18];
6836
6837         u8         input_length[0x20];
6838
6839         u8         input_mailbox_pointer_63_32[0x20];
6840
6841         u8         input_mailbox_pointer_31_9[0x17];
6842         u8         reserved_at_77[0x9];
6843
6844         u8         command_input_inline_data[16][0x8];
6845
6846         u8         command_output_inline_data[16][0x8];
6847
6848         u8         output_mailbox_pointer_63_32[0x20];
6849
6850         u8         output_mailbox_pointer_31_9[0x17];
6851         u8         reserved_at_1b7[0x9];
6852
6853         u8         output_length[0x20];
6854
6855         u8         token[0x8];
6856         u8         signature[0x8];
6857         u8         reserved_at_1f0[0x8];
6858         u8         status[0x7];
6859         u8         ownership[0x1];
6860 };
6861
6862 struct mlx5_ifc_cmd_out_bits {
6863         u8         status[0x8];
6864         u8         reserved_at_8[0x18];
6865
6866         u8         syndrome[0x20];
6867
6868         u8         command_output[0x20];
6869 };
6870
6871 struct mlx5_ifc_cmd_in_bits {
6872         u8         opcode[0x10];
6873         u8         reserved_at_10[0x10];
6874
6875         u8         reserved_at_20[0x10];
6876         u8         op_mod[0x10];
6877
6878         u8         command[0][0x20];
6879 };
6880
6881 struct mlx5_ifc_cmd_if_box_bits {
6882         u8         mailbox_data[512][0x8];
6883
6884         u8         reserved_at_1000[0x180];
6885
6886         u8         next_pointer_63_32[0x20];
6887
6888         u8         next_pointer_31_10[0x16];
6889         u8         reserved_at_11b6[0xa];
6890
6891         u8         block_number[0x20];
6892
6893         u8         reserved_at_11e0[0x8];
6894         u8         token[0x8];
6895         u8         ctrl_signature[0x8];
6896         u8         signature[0x8];
6897 };
6898
6899 struct mlx5_ifc_mtt_bits {
6900         u8         ptag_63_32[0x20];
6901
6902         u8         ptag_31_8[0x18];
6903         u8         reserved_at_38[0x6];
6904         u8         wr_en[0x1];
6905         u8         rd_en[0x1];
6906 };
6907
6908 enum {
6909         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
6910         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
6911         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
6912 };
6913
6914 enum {
6915         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
6916         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
6917         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
6918 };
6919
6920 enum {
6921         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
6922         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
6923         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
6924         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
6925         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
6926         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
6927         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
6928         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
6929         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
6930         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
6931         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
6932 };
6933
6934 struct mlx5_ifc_initial_seg_bits {
6935         u8         fw_rev_minor[0x10];
6936         u8         fw_rev_major[0x10];
6937
6938         u8         cmd_interface_rev[0x10];
6939         u8         fw_rev_subminor[0x10];
6940
6941         u8         reserved_at_40[0x40];
6942
6943         u8         cmdq_phy_addr_63_32[0x20];
6944
6945         u8         cmdq_phy_addr_31_12[0x14];
6946         u8         reserved_at_b4[0x2];
6947         u8         nic_interface[0x2];
6948         u8         log_cmdq_size[0x4];
6949         u8         log_cmdq_stride[0x4];
6950
6951         u8         command_doorbell_vector[0x20];
6952
6953         u8         reserved_at_e0[0xf00];
6954
6955         u8         initializing[0x1];
6956         u8         reserved_at_fe1[0x4];
6957         u8         nic_interface_supported[0x3];
6958         u8         reserved_at_fe8[0x18];
6959
6960         struct mlx5_ifc_health_buffer_bits health_buffer;
6961
6962         u8         no_dram_nic_offset[0x20];
6963
6964         u8         reserved_at_1220[0x6e40];
6965
6966         u8         reserved_at_8060[0x1f];
6967         u8         clear_int[0x1];
6968
6969         u8         health_syndrome[0x8];
6970         u8         health_counter[0x18];
6971
6972         u8         reserved_at_80a0[0x17fc0];
6973 };
6974
6975 union mlx5_ifc_ports_control_registers_document_bits {
6976         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6977         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6978         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6979         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6980         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6981         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6982         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6983         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6984         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6985         struct mlx5_ifc_pamp_reg_bits pamp_reg;
6986         struct mlx5_ifc_paos_reg_bits paos_reg;
6987         struct mlx5_ifc_pcap_reg_bits pcap_reg;
6988         struct mlx5_ifc_peir_reg_bits peir_reg;
6989         struct mlx5_ifc_pelc_reg_bits pelc_reg;
6990         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
6991         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
6992         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6993         struct mlx5_ifc_pifr_reg_bits pifr_reg;
6994         struct mlx5_ifc_pipg_reg_bits pipg_reg;
6995         struct mlx5_ifc_plbf_reg_bits plbf_reg;
6996         struct mlx5_ifc_plib_reg_bits plib_reg;
6997         struct mlx5_ifc_plpc_reg_bits plpc_reg;
6998         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
6999         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7000         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7001         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7002         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7003         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7004         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7005         struct mlx5_ifc_ppad_reg_bits ppad_reg;
7006         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7007         struct mlx5_ifc_pplm_reg_bits pplm_reg;
7008         struct mlx5_ifc_pplr_reg_bits pplr_reg;
7009         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7010         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7011         struct mlx5_ifc_pspa_reg_bits pspa_reg;
7012         struct mlx5_ifc_ptas_reg_bits ptas_reg;
7013         struct mlx5_ifc_ptys_reg_bits ptys_reg;
7014         struct mlx5_ifc_pude_reg_bits pude_reg;
7015         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7016         struct mlx5_ifc_slrg_reg_bits slrg_reg;
7017         struct mlx5_ifc_sltp_reg_bits sltp_reg;
7018         u8         reserved_at_0[0x60e0];
7019 };
7020
7021 union mlx5_ifc_debug_enhancements_document_bits {
7022         struct mlx5_ifc_health_buffer_bits health_buffer;
7023         u8         reserved_at_0[0x200];
7024 };
7025
7026 union mlx5_ifc_uplink_pci_interface_document_bits {
7027         struct mlx5_ifc_initial_seg_bits initial_seg;
7028         u8         reserved_at_0[0x20060];
7029 };
7030
7031 struct mlx5_ifc_set_flow_table_root_out_bits {
7032         u8         status[0x8];
7033         u8         reserved_at_8[0x18];
7034
7035         u8         syndrome[0x20];
7036
7037         u8         reserved_at_40[0x40];
7038 };
7039
7040 struct mlx5_ifc_set_flow_table_root_in_bits {
7041         u8         opcode[0x10];
7042         u8         reserved_at_10[0x10];
7043
7044         u8         reserved_at_20[0x10];
7045         u8         op_mod[0x10];
7046
7047         u8         reserved_at_40[0x40];
7048
7049         u8         table_type[0x8];
7050         u8         reserved_at_88[0x18];
7051
7052         u8         reserved_at_a0[0x8];
7053         u8         table_id[0x18];
7054
7055         u8         reserved_at_c0[0x140];
7056 };
7057
7058 enum {
7059         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7060 };
7061
7062 struct mlx5_ifc_modify_flow_table_out_bits {
7063         u8         status[0x8];
7064         u8         reserved_at_8[0x18];
7065
7066         u8         syndrome[0x20];
7067
7068         u8         reserved_at_40[0x40];
7069 };
7070
7071 struct mlx5_ifc_modify_flow_table_in_bits {
7072         u8         opcode[0x10];
7073         u8         reserved_at_10[0x10];
7074
7075         u8         reserved_at_20[0x10];
7076         u8         op_mod[0x10];
7077
7078         u8         reserved_at_40[0x20];
7079
7080         u8         reserved_at_60[0x10];
7081         u8         modify_field_select[0x10];
7082
7083         u8         table_type[0x8];
7084         u8         reserved_at_88[0x18];
7085
7086         u8         reserved_at_a0[0x8];
7087         u8         table_id[0x18];
7088
7089         u8         reserved_at_c0[0x4];
7090         u8         table_miss_mode[0x4];
7091         u8         reserved_at_c8[0x18];
7092
7093         u8         reserved_at_e0[0x8];
7094         u8         table_miss_id[0x18];
7095
7096         u8         reserved_at_100[0x100];
7097 };
7098
7099 #endif /* MLX5_IFC_H */