include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  71         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  72 };
  73
  74 enum {
  75         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  76         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  77         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  78         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  79         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  80         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  81         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  82         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  83         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  84         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  85         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  86         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  87         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  88         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  89         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  90         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  91         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  92         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  93         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  94         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  95         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  96         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  97         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  98         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
  99         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 100         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 101         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 102         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 103         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 104         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 105         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 106         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 107         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 108         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 109         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 110         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 111         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 112         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 113         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 114         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 115         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 116         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 117         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 118         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 119         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 120         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 121         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 122         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 123         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 124         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 125         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 126         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 127         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 128         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 129         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 130         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 131         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 132         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 133         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 134         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 135         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 136         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 137         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 138         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 139         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 140         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 141         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 142         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 143         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 144         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 145         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 146         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 147         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 148         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 149         MLX5_CMD_OP_DETTACH_FROM_MCG              = 0x807,
 150         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 151         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 152         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 153         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 154         MLX5_CMD_OP_NOP                           = 0x80d,
 155         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 156         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 157         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 158         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 159         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 160         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 161         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 162         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 163         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 164         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 165         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 166         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 167         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 168         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 169         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 170         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 171         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 172         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 173         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 174         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 175         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 176         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 177         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 178         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 179         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 180         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 181         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 182         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 183         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 184         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 185         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 186         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 187         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 188         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 189         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 190         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 191         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 192         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 193         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 194         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 195         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 196         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 197         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 198         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 199         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 200         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 201         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 202         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 203         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c
 204 };
 205
 206 struct mlx5_ifc_flow_table_fields_supported_bits {
 207         u8         outer_dmac[0x1];
 208         u8         outer_smac[0x1];
 209         u8         outer_ether_type[0x1];
 210         u8         reserved_at_3[0x1];
 211         u8         outer_first_prio[0x1];
 212         u8         outer_first_cfi[0x1];
 213         u8         outer_first_vid[0x1];
 214         u8         reserved_at_7[0x1];
 215         u8         outer_second_prio[0x1];
 216         u8         outer_second_cfi[0x1];
 217         u8         outer_second_vid[0x1];
 218         u8         reserved_at_b[0x1];
 219         u8         outer_sip[0x1];
 220         u8         outer_dip[0x1];
 221         u8         outer_frag[0x1];
 222         u8         outer_ip_protocol[0x1];
 223         u8         outer_ip_ecn[0x1];
 224         u8         outer_ip_dscp[0x1];
 225         u8         outer_udp_sport[0x1];
 226         u8         outer_udp_dport[0x1];
 227         u8         outer_tcp_sport[0x1];
 228         u8         outer_tcp_dport[0x1];
 229         u8         outer_tcp_flags[0x1];
 230         u8         outer_gre_protocol[0x1];
 231         u8         outer_gre_key[0x1];
 232         u8         outer_vxlan_vni[0x1];
 233         u8         reserved_at_1a[0x5];
 234         u8         source_eswitch_port[0x1];
 235
 236         u8         inner_dmac[0x1];
 237         u8         inner_smac[0x1];
 238         u8         inner_ether_type[0x1];
 239         u8         reserved_at_23[0x1];
 240         u8         inner_first_prio[0x1];
 241         u8         inner_first_cfi[0x1];
 242         u8         inner_first_vid[0x1];
 243         u8         reserved_at_27[0x1];
 244         u8         inner_second_prio[0x1];
 245         u8         inner_second_cfi[0x1];
 246         u8         inner_second_vid[0x1];
 247         u8         reserved_at_2b[0x1];
 248         u8         inner_sip[0x1];
 249         u8         inner_dip[0x1];
 250         u8         inner_frag[0x1];
 251         u8         inner_ip_protocol[0x1];
 252         u8         inner_ip_ecn[0x1];
 253         u8         inner_ip_dscp[0x1];
 254         u8         inner_udp_sport[0x1];
 255         u8         inner_udp_dport[0x1];
 256         u8         inner_tcp_sport[0x1];
 257         u8         inner_tcp_dport[0x1];
 258         u8         inner_tcp_flags[0x1];
 259         u8         reserved_at_37[0x9];
 260
 261         u8         reserved_at_40[0x40];
 262 };
 263
 264 struct mlx5_ifc_flow_table_prop_layout_bits {
 265         u8         ft_support[0x1];
 266         u8         reserved_at_1[0x2];
 267         u8         flow_modify_en[0x1];
 268         u8         modify_root[0x1];
 269         u8         identified_miss_table_mode[0x1];
 270         u8         flow_table_modify[0x1];
 271         u8         reserved_at_7[0x19];
 272
 273         u8         reserved_at_20[0x2];
 274         u8         log_max_ft_size[0x6];
 275         u8         reserved_at_28[0x10];
 276         u8         max_ft_level[0x8];
 277
 278         u8         reserved_at_40[0x20];
 279
 280         u8         reserved_at_60[0x18];
 281         u8         log_max_ft_num[0x8];
 282
 283         u8         reserved_at_80[0x18];
 284         u8         log_max_destination[0x8];
 285
 286         u8         reserved_at_a0[0x18];
 287         u8         log_max_flow[0x8];
 288
 289         u8         reserved_at_c0[0x40];
 290
 291         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 292
 293         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 294 };
 295
 296 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 297         u8         send[0x1];
 298         u8         receive[0x1];
 299         u8         write[0x1];
 300         u8         read[0x1];
 301         u8         reserved_at_4[0x1];
 302         u8         srq_receive[0x1];
 303         u8         reserved_at_6[0x1a];
 304 };
 305
 306 struct mlx5_ifc_ipv4_layout_bits {
 307         u8         reserved_at_0[0x60];
 308
 309         u8         ipv4[0x20];
 310 };
 311
 312 struct mlx5_ifc_ipv6_layout_bits {
 313         u8         ipv6[16][0x8];
 314 };
 315
 316 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 317         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 318         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 319         u8         reserved_at_0[0x80];
 320 };
 321
 322 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 323         u8         smac_47_16[0x20];
 324
 325         u8         smac_15_0[0x10];
 326         u8         ethertype[0x10];
 327
 328         u8         dmac_47_16[0x20];
 329
 330         u8         dmac_15_0[0x10];
 331         u8         first_prio[0x3];
 332         u8         first_cfi[0x1];
 333         u8         first_vid[0xc];
 334
 335         u8         ip_protocol[0x8];
 336         u8         ip_dscp[0x6];
 337         u8         ip_ecn[0x2];
 338         u8         vlan_tag[0x1];
 339         u8         reserved_at_91[0x1];
 340         u8         frag[0x1];
 341         u8         reserved_at_93[0x4];
 342         u8         tcp_flags[0x9];
 343
 344         u8         tcp_sport[0x10];
 345         u8         tcp_dport[0x10];
 346
 347         u8         reserved_at_c0[0x20];
 348
 349         u8         udp_sport[0x10];
 350         u8         udp_dport[0x10];
 351
 352         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 353
 354         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 355 };
 356
 357 struct mlx5_ifc_fte_match_set_misc_bits {
 358         u8         reserved_at_0[0x20];
 359
 360         u8         reserved_at_20[0x10];
 361         u8         source_port[0x10];
 362
 363         u8         outer_second_prio[0x3];
 364         u8         outer_second_cfi[0x1];
 365         u8         outer_second_vid[0xc];
 366         u8         inner_second_prio[0x3];
 367         u8         inner_second_cfi[0x1];
 368         u8         inner_second_vid[0xc];
 369
 370         u8         outer_second_vlan_tag[0x1];
 371         u8         inner_second_vlan_tag[0x1];
 372         u8         reserved_at_62[0xe];
 373         u8         gre_protocol[0x10];
 374
 375         u8         gre_key_h[0x18];
 376         u8         gre_key_l[0x8];
 377
 378         u8         vxlan_vni[0x18];
 379         u8         reserved_at_b8[0x8];
 380
 381         u8         reserved_at_c0[0x20];
 382
 383         u8         reserved_at_e0[0xc];
 384         u8         outer_ipv6_flow_label[0x14];
 385
 386         u8         reserved_at_100[0xc];
 387         u8         inner_ipv6_flow_label[0x14];
 388
 389         u8         reserved_at_120[0xe0];
 390 };
 391
 392 struct mlx5_ifc_cmd_pas_bits {
 393         u8         pa_h[0x20];
 394
 395         u8         pa_l[0x14];
 396         u8         reserved_at_34[0xc];
 397 };
 398
 399 struct mlx5_ifc_uint64_bits {
 400         u8         hi[0x20];
 401
 402         u8         lo[0x20];
 403 };
 404
 405 enum {
 406         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 407         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 408         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 409         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 410         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 411         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 412         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 413         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 414         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 415         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 416 };
 417
 418 struct mlx5_ifc_ads_bits {
 419         u8         fl[0x1];
 420         u8         free_ar[0x1];
 421         u8         reserved_at_2[0xe];
 422         u8         pkey_index[0x10];
 423
 424         u8         reserved_at_20[0x8];
 425         u8         grh[0x1];
 426         u8         mlid[0x7];
 427         u8         rlid[0x10];
 428
 429         u8         ack_timeout[0x5];
 430         u8         reserved_at_45[0x3];
 431         u8         src_addr_index[0x8];
 432         u8         reserved_at_50[0x4];
 433         u8         stat_rate[0x4];
 434         u8         hop_limit[0x8];
 435
 436         u8         reserved_at_60[0x4];
 437         u8         tclass[0x8];
 438         u8         flow_label[0x14];
 439
 440         u8         rgid_rip[16][0x8];
 441
 442         u8         reserved_at_100[0x4];
 443         u8         f_dscp[0x1];
 444         u8         f_ecn[0x1];
 445         u8         reserved_at_106[0x1];
 446         u8         f_eth_prio[0x1];
 447         u8         ecn[0x2];
 448         u8         dscp[0x6];
 449         u8         udp_sport[0x10];
 450
 451         u8         dei_cfi[0x1];
 452         u8         eth_prio[0x3];
 453         u8         sl[0x4];
 454         u8         port[0x8];
 455         u8         rmac_47_32[0x10];
 456
 457         u8         rmac_31_0[0x20];
 458 };
 459
 460 struct mlx5_ifc_flow_table_nic_cap_bits {
 461         u8         reserved_at_0[0x200];
 462
 463         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 464
 465         u8         reserved_at_400[0x200];
 466
 467         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 468
 469         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 470
 471         u8         reserved_at_a00[0x200];
 472
 473         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 474
 475         u8         reserved_at_e00[0x7200];
 476 };
 477
 478 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 479         u8     reserved_at_0[0x200];
 480
 481         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 482
 483         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 484
 485         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 486
 487         u8      reserved_at_800[0x7800];
 488 };
 489
 490 struct mlx5_ifc_e_switch_cap_bits {
 491         u8         vport_svlan_strip[0x1];
 492         u8         vport_cvlan_strip[0x1];
 493         u8         vport_svlan_insert[0x1];
 494         u8         vport_cvlan_insert_if_not_exist[0x1];
 495         u8         vport_cvlan_insert_overwrite[0x1];
 496         u8         reserved_at_5[0x1b];
 497
 498         u8         reserved_at_20[0x7e0];
 499 };
 500
 501 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 502         u8         csum_cap[0x1];
 503         u8         vlan_cap[0x1];
 504         u8         lro_cap[0x1];
 505         u8         lro_psh_flag[0x1];
 506         u8         lro_time_stamp[0x1];
 507         u8         reserved_at_5[0x3];
 508         u8         self_lb_en_modifiable[0x1];
 509         u8         reserved_at_9[0x2];
 510         u8         max_lso_cap[0x5];
 511         u8         reserved_at_10[0x4];
 512         u8         rss_ind_tbl_cap[0x4];
 513         u8         reserved_at_18[0x3];
 514         u8         tunnel_lso_const_out_ip_id[0x1];
 515         u8         reserved_at_1c[0x2];
 516         u8         tunnel_statless_gre[0x1];
 517         u8         tunnel_stateless_vxlan[0x1];
 518
 519         u8         reserved_at_20[0x20];
 520
 521         u8         reserved_at_40[0x10];
 522         u8         lro_min_mss_size[0x10];
 523
 524         u8         reserved_at_60[0x120];
 525
 526         u8         lro_timer_supported_periods[4][0x20];
 527
 528         u8         reserved_at_200[0x600];
 529 };
 530
 531 struct mlx5_ifc_roce_cap_bits {
 532         u8         roce_apm[0x1];
 533         u8         reserved_at_1[0x1f];
 534
 535         u8         reserved_at_20[0x60];
 536
 537         u8         reserved_at_80[0xc];
 538         u8         l3_type[0x4];
 539         u8         reserved_at_90[0x8];
 540         u8         roce_version[0x8];
 541
 542         u8         reserved_at_a0[0x10];
 543         u8         r_roce_dest_udp_port[0x10];
 544
 545         u8         r_roce_max_src_udp_port[0x10];
 546         u8         r_roce_min_src_udp_port[0x10];
 547
 548         u8         reserved_at_e0[0x10];
 549         u8         roce_address_table_size[0x10];
 550
 551         u8         reserved_at_100[0x700];
 552 };
 553
 554 enum {
 555         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 556         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 557         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 558         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 559         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 560         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 561         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 562         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 563         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 564 };
 565
 566 enum {
 567         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 568         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 569         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 570         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 571         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 572         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 573         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 574         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 575         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 576 };
 577
 578 struct mlx5_ifc_atomic_caps_bits {
 579         u8         reserved_at_0[0x40];
 580
 581         u8         atomic_req_8B_endianess_mode[0x2];
 582         u8         reserved_at_42[0x4];
 583         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 584
 585         u8         reserved_at_47[0x19];
 586
 587         u8         reserved_at_60[0x20];
 588
 589         u8         reserved_at_80[0x10];
 590         u8         atomic_operations[0x10];
 591
 592         u8         reserved_at_a0[0x10];
 593         u8         atomic_size_qp[0x10];
 594
 595         u8         reserved_at_c0[0x10];
 596         u8         atomic_size_dc[0x10];
 597
 598         u8         reserved_at_e0[0x720];
 599 };
 600
 601 struct mlx5_ifc_odp_cap_bits {
 602         u8         reserved_at_0[0x40];
 603
 604         u8         sig[0x1];
 605         u8         reserved_at_41[0x1f];
 606
 607         u8         reserved_at_60[0x20];
 608
 609         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 610
 611         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 612
 613         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 614
 615         u8         reserved_at_e0[0x720];
 616 };
 617
 618 enum {
 619         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 620         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 621         MLX5_WQ_TYPE_STRQ         = 0x2,
 622 };
 623
 624 enum {
 625         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 626         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 627 };
 628
 629 enum {
 630         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 631         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 632         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 633         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 634         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 635 };
 636
 637 enum {
 638         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 639         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 640         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 641         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 642         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 643         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 644 };
 645
 646 enum {
 647         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 648         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 649 };
 650
 651 enum {
 652         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 653         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 654         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 655 };
 656
 657 enum {
 658         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 659         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 660 };
 661
 662 struct mlx5_ifc_cmd_hca_cap_bits {
 663         u8         reserved_at_0[0x80];
 664
 665         u8         log_max_srq_sz[0x8];
 666         u8         log_max_qp_sz[0x8];
 667         u8         reserved_at_90[0xb];
 668         u8         log_max_qp[0x5];
 669
 670         u8         reserved_at_a0[0xb];
 671         u8         log_max_srq[0x5];
 672         u8         reserved_at_b0[0x10];
 673
 674         u8         reserved_at_c0[0x8];
 675         u8         log_max_cq_sz[0x8];
 676         u8         reserved_at_d0[0xb];
 677         u8         log_max_cq[0x5];
 678
 679         u8         log_max_eq_sz[0x8];
 680         u8         reserved_at_e8[0x2];
 681         u8         log_max_mkey[0x6];
 682         u8         reserved_at_f0[0xc];
 683         u8         log_max_eq[0x4];
 684
 685         u8         max_indirection[0x8];
 686         u8         reserved_at_108[0x1];
 687         u8         log_max_mrw_sz[0x7];
 688         u8         reserved_at_110[0x2];
 689         u8         log_max_bsf_list_size[0x6];
 690         u8         reserved_at_118[0x2];
 691         u8         log_max_klm_list_size[0x6];
 692
 693         u8         reserved_at_120[0xa];
 694         u8         log_max_ra_req_dc[0x6];
 695         u8         reserved_at_130[0xa];
 696         u8         log_max_ra_res_dc[0x6];
 697
 698         u8         reserved_at_140[0xa];
 699         u8         log_max_ra_req_qp[0x6];
 700         u8         reserved_at_150[0xa];
 701         u8         log_max_ra_res_qp[0x6];
 702
 703         u8         pad_cap[0x1];
 704         u8         cc_query_allowed[0x1];
 705         u8         cc_modify_allowed[0x1];
 706         u8         reserved_at_163[0xd];
 707         u8         gid_table_size[0x10];
 708
 709         u8         out_of_seq_cnt[0x1];
 710         u8         vport_counters[0x1];
 711         u8         reserved_at_182[0x4];
 712         u8         max_qp_cnt[0xa];
 713         u8         pkey_table_size[0x10];
 714
 715         u8         vport_group_manager[0x1];
 716         u8         vhca_group_manager[0x1];
 717         u8         ib_virt[0x1];
 718         u8         eth_virt[0x1];
 719         u8         reserved_at_1a4[0x1];
 720         u8         ets[0x1];
 721         u8         nic_flow_table[0x1];
 722         u8         eswitch_flow_table[0x1];
 723         u8         early_vf_enable;
 724         u8         reserved_at_1a8[0x2];
 725         u8         local_ca_ack_delay[0x5];
 726         u8         reserved_at_1af[0x6];
 727         u8         port_type[0x2];
 728         u8         num_ports[0x8];
 729
 730         u8         reserved_at_1bf[0x3];
 731         u8         log_max_msg[0x5];
 732         u8         reserved_at_1c7[0x18];
 733
 734         u8         stat_rate_support[0x10];
 735         u8         reserved_at_1ef[0xc];
 736         u8         cqe_version[0x4];
 737
 738         u8         compact_address_vector[0x1];
 739         u8         reserved_at_200[0xe];
 740         u8         drain_sigerr[0x1];
 741         u8         cmdif_checksum[0x2];
 742         u8         sigerr_cqe[0x1];
 743         u8         reserved_at_212[0x1];
 744         u8         wq_signature[0x1];
 745         u8         sctr_data_cqe[0x1];
 746         u8         reserved_at_215[0x1];
 747         u8         sho[0x1];
 748         u8         tph[0x1];
 749         u8         rf[0x1];
 750         u8         dct[0x1];
 751         u8         reserved_at_21a[0x1];
 752         u8         eth_net_offloads[0x1];
 753         u8         roce[0x1];
 754         u8         atomic[0x1];
 755         u8         reserved_at_21e[0x1];
 756
 757         u8         cq_oi[0x1];
 758         u8         cq_resize[0x1];
 759         u8         cq_moderation[0x1];
 760         u8         reserved_at_222[0x3];
 761         u8         cq_eq_remap[0x1];
 762         u8         pg[0x1];
 763         u8         block_lb_mc[0x1];
 764         u8         reserved_at_228[0x1];
 765         u8         scqe_break_moderation[0x1];
 766         u8         reserved_at_22a[0x1];
 767         u8         cd[0x1];
 768         u8         reserved_at_22c[0x1];
 769         u8         apm[0x1];
 770         u8         reserved_at_22e[0x7];
 771         u8         qkv[0x1];
 772         u8         pkv[0x1];
 773         u8         reserved_at_237[0x4];
 774         u8         xrc[0x1];
 775         u8         ud[0x1];
 776         u8         uc[0x1];
 777         u8         rc[0x1];
 778
 779         u8         reserved_at_23f[0xa];
 780         u8         uar_sz[0x6];
 781         u8         reserved_at_24f[0x8];
 782         u8         log_pg_sz[0x8];
 783
 784         u8         bf[0x1];
 785         u8         reserved_at_260[0x1];
 786         u8         pad_tx_eth_packet[0x1];
 787         u8         reserved_at_262[0x8];
 788         u8         log_bf_reg_size[0x5];
 789         u8         reserved_at_26f[0x10];
 790
 791         u8         reserved_at_27f[0x10];
 792         u8         max_wqe_sz_sq[0x10];
 793
 794         u8         reserved_at_29f[0x10];
 795         u8         max_wqe_sz_rq[0x10];
 796
 797         u8         reserved_at_2bf[0x10];
 798         u8         max_wqe_sz_sq_dc[0x10];
 799
 800         u8         reserved_at_2df[0x7];
 801         u8         max_qp_mcg[0x19];
 802
 803         u8         reserved_at_2ff[0x18];
 804         u8         log_max_mcg[0x8];
 805
 806         u8         reserved_at_31f[0x3];
 807         u8         log_max_transport_domain[0x5];
 808         u8         reserved_at_327[0x3];
 809         u8         log_max_pd[0x5];
 810         u8         reserved_at_32f[0xb];
 811         u8         log_max_xrcd[0x5];
 812
 813         u8         reserved_at_33f[0x20];
 814
 815         u8         reserved_at_35f[0x3];
 816         u8         log_max_rq[0x5];
 817         u8         reserved_at_367[0x3];
 818         u8         log_max_sq[0x5];
 819         u8         reserved_at_36f[0x3];
 820         u8         log_max_tir[0x5];
 821         u8         reserved_at_377[0x3];
 822         u8         log_max_tis[0x5];
 823
 824         u8         basic_cyclic_rcv_wqe[0x1];
 825         u8         reserved_at_380[0x2];
 826         u8         log_max_rmp[0x5];
 827         u8         reserved_at_387[0x3];
 828         u8         log_max_rqt[0x5];
 829         u8         reserved_at_38f[0x3];
 830         u8         log_max_rqt_size[0x5];
 831         u8         reserved_at_397[0x3];
 832         u8         log_max_tis_per_sq[0x5];
 833
 834         u8         reserved_at_39f[0x3];
 835         u8         log_max_stride_sz_rq[0x5];
 836         u8         reserved_at_3a7[0x3];
 837         u8         log_min_stride_sz_rq[0x5];
 838         u8         reserved_at_3af[0x3];
 839         u8         log_max_stride_sz_sq[0x5];
 840         u8         reserved_at_3b7[0x3];
 841         u8         log_min_stride_sz_sq[0x5];
 842
 843         u8         reserved_at_3bf[0x1b];
 844         u8         log_max_wq_sz[0x5];
 845
 846         u8         nic_vport_change_event[0x1];
 847         u8         reserved_at_3e0[0xa];
 848         u8         log_max_vlan_list[0x5];
 849         u8         reserved_at_3ef[0x3];
 850         u8         log_max_current_mc_list[0x5];
 851         u8         reserved_at_3f7[0x3];
 852         u8         log_max_current_uc_list[0x5];
 853
 854         u8         reserved_at_3ff[0x80];
 855
 856         u8         reserved_at_47f[0x3];
 857         u8         log_max_l2_table[0x5];
 858         u8         reserved_at_487[0x8];
 859         u8         log_uar_page_sz[0x10];
 860
 861         u8         reserved_at_49f[0x20];
 862         u8         device_frequency_mhz[0x20];
 863         u8         device_frequency_khz[0x20];
 864         u8         reserved_at_4ff[0x5f];
 865         u8         cqe_zip[0x1];
 866
 867         u8         cqe_zip_timeout[0x10];
 868         u8         cqe_zip_max_num[0x10];
 869
 870         u8         reserved_at_57f[0x220];
 871 };
 872
 873 enum mlx5_flow_destination_type {
 874         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
 875         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
 876         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
 877 };
 878
 879 struct mlx5_ifc_dest_format_struct_bits {
 880         u8         destination_type[0x8];
 881         u8         destination_id[0x18];
 882
 883         u8         reserved_at_20[0x20];
 884 };
 885
 886 struct mlx5_ifc_fte_match_param_bits {
 887         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
 888
 889         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
 890
 891         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 892
 893         u8         reserved_at_600[0xa00];
 894 };
 895
 896 enum {
 897         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
 898         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
 899         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
 900         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
 901         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
 902 };
 903
 904 struct mlx5_ifc_rx_hash_field_select_bits {
 905         u8         l3_prot_type[0x1];
 906         u8         l4_prot_type[0x1];
 907         u8         selected_fields[0x1e];
 908 };
 909
 910 enum {
 911         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
 912         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
 913 };
 914
 915 enum {
 916         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
 917         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
 918 };
 919
 920 struct mlx5_ifc_wq_bits {
 921         u8         wq_type[0x4];
 922         u8         wq_signature[0x1];
 923         u8         end_padding_mode[0x2];
 924         u8         cd_slave[0x1];
 925         u8         reserved_at_8[0x18];
 926
 927         u8         hds_skip_first_sge[0x1];
 928         u8         log2_hds_buf_size[0x3];
 929         u8         reserved_at_24[0x7];
 930         u8         page_offset[0x5];
 931         u8         lwm[0x10];
 932
 933         u8         reserved_at_40[0x8];
 934         u8         pd[0x18];
 935
 936         u8         reserved_at_60[0x8];
 937         u8         uar_page[0x18];
 938
 939         u8         dbr_addr[0x40];
 940
 941         u8         hw_counter[0x20];
 942
 943         u8         sw_counter[0x20];
 944
 945         u8         reserved_at_100[0xc];
 946         u8         log_wq_stride[0x4];
 947         u8         reserved_at_110[0x3];
 948         u8         log_wq_pg_sz[0x5];
 949         u8         reserved_at_118[0x3];
 950         u8         log_wq_sz[0x5];
 951
 952         u8         reserved_at_120[0x4e0];
 953
 954         struct mlx5_ifc_cmd_pas_bits pas[0];
 955 };
 956
 957 struct mlx5_ifc_rq_num_bits {
 958         u8         reserved_at_0[0x8];
 959         u8         rq_num[0x18];
 960 };
 961
 962 struct mlx5_ifc_mac_address_layout_bits {
 963         u8         reserved_at_0[0x10];
 964         u8         mac_addr_47_32[0x10];
 965
 966         u8         mac_addr_31_0[0x20];
 967 };
 968
 969 struct mlx5_ifc_vlan_layout_bits {
 970         u8         reserved_at_0[0x14];
 971         u8         vlan[0x0c];
 972
 973         u8         reserved_at_20[0x20];
 974 };
 975
 976 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
 977         u8         reserved_at_0[0xa0];
 978
 979         u8         min_time_between_cnps[0x20];
 980
 981         u8         reserved_at_c0[0x12];
 982         u8         cnp_dscp[0x6];
 983         u8         reserved_at_d8[0x5];
 984         u8         cnp_802p_prio[0x3];
 985
 986         u8         reserved_at_e0[0x720];
 987 };
 988
 989 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
 990         u8         reserved_at_0[0x60];
 991
 992         u8         reserved_at_60[0x4];
 993         u8         clamp_tgt_rate[0x1];
 994         u8         reserved_at_65[0x3];
 995         u8         clamp_tgt_rate_after_time_inc[0x1];
 996         u8         reserved_at_69[0x17];
 997
 998         u8         reserved_at_80[0x20];
 999
1000         u8         rpg_time_reset[0x20];
1001
1002         u8         rpg_byte_reset[0x20];
1003
1004         u8         rpg_threshold[0x20];
1005
1006         u8         rpg_max_rate[0x20];
1007
1008         u8         rpg_ai_rate[0x20];
1009
1010         u8         rpg_hai_rate[0x20];
1011
1012         u8         rpg_gd[0x20];
1013
1014         u8         rpg_min_dec_fac[0x20];
1015
1016         u8         rpg_min_rate[0x20];
1017
1018         u8         reserved_at_1c0[0xe0];
1019
1020         u8         rate_to_set_on_first_cnp[0x20];
1021
1022         u8         dce_tcp_g[0x20];
1023
1024         u8         dce_tcp_rtt[0x20];
1025
1026         u8         rate_reduce_monitor_period[0x20];
1027
1028         u8         reserved_at_320[0x20];
1029
1030         u8         initial_alpha_value[0x20];
1031
1032         u8         reserved_at_360[0x4a0];
1033 };
1034
1035 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1036         u8         reserved_at_0[0x80];
1037
1038         u8         rppp_max_rps[0x20];
1039
1040         u8         rpg_time_reset[0x20];
1041
1042         u8         rpg_byte_reset[0x20];
1043
1044         u8         rpg_threshold[0x20];
1045
1046         u8         rpg_max_rate[0x20];
1047
1048         u8         rpg_ai_rate[0x20];
1049
1050         u8         rpg_hai_rate[0x20];
1051
1052         u8         rpg_gd[0x20];
1053
1054         u8         rpg_min_dec_fac[0x20];
1055
1056         u8         rpg_min_rate[0x20];
1057
1058         u8         reserved_at_1c0[0x640];
1059 };
1060
1061 enum {
1062         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1063         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1064         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1065 };
1066
1067 struct mlx5_ifc_resize_field_select_bits {
1068         u8         resize_field_select[0x20];
1069 };
1070
1071 enum {
1072         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1073         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1074         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1075         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1076 };
1077
1078 struct mlx5_ifc_modify_field_select_bits {
1079         u8         modify_field_select[0x20];
1080 };
1081
1082 struct mlx5_ifc_field_select_r_roce_np_bits {
1083         u8         field_select_r_roce_np[0x20];
1084 };
1085
1086 struct mlx5_ifc_field_select_r_roce_rp_bits {
1087         u8         field_select_r_roce_rp[0x20];
1088 };
1089
1090 enum {
1091         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1092         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1093         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1094         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1095         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1096         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1097         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1098         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1099         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1100         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1101 };
1102
1103 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1104         u8         field_select_8021qaurp[0x20];
1105 };
1106
1107 struct mlx5_ifc_phys_layer_cntrs_bits {
1108         u8         time_since_last_clear_high[0x20];
1109
1110         u8         time_since_last_clear_low[0x20];
1111
1112         u8         symbol_errors_high[0x20];
1113
1114         u8         symbol_errors_low[0x20];
1115
1116         u8         sync_headers_errors_high[0x20];
1117
1118         u8         sync_headers_errors_low[0x20];
1119
1120         u8         edpl_bip_errors_lane0_high[0x20];
1121
1122         u8         edpl_bip_errors_lane0_low[0x20];
1123
1124         u8         edpl_bip_errors_lane1_high[0x20];
1125
1126         u8         edpl_bip_errors_lane1_low[0x20];
1127
1128         u8         edpl_bip_errors_lane2_high[0x20];
1129
1130         u8         edpl_bip_errors_lane2_low[0x20];
1131
1132         u8         edpl_bip_errors_lane3_high[0x20];
1133
1134         u8         edpl_bip_errors_lane3_low[0x20];
1135
1136         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1137
1138         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1139
1140         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1141
1142         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1143
1144         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1145
1146         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1147
1148         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1149
1150         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1151
1152         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1153
1154         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1155
1156         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1157
1158         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1159
1160         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1161
1162         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1163
1164         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1165
1166         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1167
1168         u8         rs_fec_corrected_blocks_high[0x20];
1169
1170         u8         rs_fec_corrected_blocks_low[0x20];
1171
1172         u8         rs_fec_uncorrectable_blocks_high[0x20];
1173
1174         u8         rs_fec_uncorrectable_blocks_low[0x20];
1175
1176         u8         rs_fec_no_errors_blocks_high[0x20];
1177
1178         u8         rs_fec_no_errors_blocks_low[0x20];
1179
1180         u8         rs_fec_single_error_blocks_high[0x20];
1181
1182         u8         rs_fec_single_error_blocks_low[0x20];
1183
1184         u8         rs_fec_corrected_symbols_total_high[0x20];
1185
1186         u8         rs_fec_corrected_symbols_total_low[0x20];
1187
1188         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1189
1190         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1191
1192         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1193
1194         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1195
1196         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1197
1198         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1199
1200         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1201
1202         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1203
1204         u8         link_down_events[0x20];
1205
1206         u8         successful_recovery_events[0x20];
1207
1208         u8         reserved_at_640[0x180];
1209 };
1210
1211 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1212         u8         symbol_error_counter[0x10];
1213
1214         u8         link_error_recovery_counter[0x8];
1215
1216         u8         link_downed_counter[0x8];
1217
1218         u8         port_rcv_errors[0x10];
1219
1220         u8         port_rcv_remote_physical_errors[0x10];
1221
1222         u8         port_rcv_switch_relay_errors[0x10];
1223
1224         u8         port_xmit_discards[0x10];
1225
1226         u8         port_xmit_constraint_errors[0x8];
1227
1228         u8         port_rcv_constraint_errors[0x8];
1229
1230         u8         reserved_at_70[0x8];
1231
1232         u8         link_overrun_errors[0x8];
1233
1234         u8         reserved_at_80[0x10];
1235
1236         u8         vl_15_dropped[0x10];
1237
1238         u8         reserved_at_a0[0xa0];
1239 };
1240
1241 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1242         u8         transmit_queue_high[0x20];
1243
1244         u8         transmit_queue_low[0x20];
1245
1246         u8         reserved_at_40[0x780];
1247 };
1248
1249 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1250         u8         rx_octets_high[0x20];
1251
1252         u8         rx_octets_low[0x20];
1253
1254         u8         reserved_at_40[0xc0];
1255
1256         u8         rx_frames_high[0x20];
1257
1258         u8         rx_frames_low[0x20];
1259
1260         u8         tx_octets_high[0x20];
1261
1262         u8         tx_octets_low[0x20];
1263
1264         u8         reserved_at_180[0xc0];
1265
1266         u8         tx_frames_high[0x20];
1267
1268         u8         tx_frames_low[0x20];
1269
1270         u8         rx_pause_high[0x20];
1271
1272         u8         rx_pause_low[0x20];
1273
1274         u8         rx_pause_duration_high[0x20];
1275
1276         u8         rx_pause_duration_low[0x20];
1277
1278         u8         tx_pause_high[0x20];
1279
1280         u8         tx_pause_low[0x20];
1281
1282         u8         tx_pause_duration_high[0x20];
1283
1284         u8         tx_pause_duration_low[0x20];
1285
1286         u8         rx_pause_transition_high[0x20];
1287
1288         u8         rx_pause_transition_low[0x20];
1289
1290         u8         reserved_at_3c0[0x400];
1291 };
1292
1293 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1294         u8         port_transmit_wait_high[0x20];
1295
1296         u8         port_transmit_wait_low[0x20];
1297
1298         u8         reserved_at_40[0x780];
1299 };
1300
1301 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1302         u8         dot3stats_alignment_errors_high[0x20];
1303
1304         u8         dot3stats_alignment_errors_low[0x20];
1305
1306         u8         dot3stats_fcs_errors_high[0x20];
1307
1308         u8         dot3stats_fcs_errors_low[0x20];
1309
1310         u8         dot3stats_single_collision_frames_high[0x20];
1311
1312         u8         dot3stats_single_collision_frames_low[0x20];
1313
1314         u8         dot3stats_multiple_collision_frames_high[0x20];
1315
1316         u8         dot3stats_multiple_collision_frames_low[0x20];
1317
1318         u8         dot3stats_sqe_test_errors_high[0x20];
1319
1320         u8         dot3stats_sqe_test_errors_low[0x20];
1321
1322         u8         dot3stats_deferred_transmissions_high[0x20];
1323
1324         u8         dot3stats_deferred_transmissions_low[0x20];
1325
1326         u8         dot3stats_late_collisions_high[0x20];
1327
1328         u8         dot3stats_late_collisions_low[0x20];
1329
1330         u8         dot3stats_excessive_collisions_high[0x20];
1331
1332         u8         dot3stats_excessive_collisions_low[0x20];
1333
1334         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1335
1336         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1337
1338         u8         dot3stats_carrier_sense_errors_high[0x20];
1339
1340         u8         dot3stats_carrier_sense_errors_low[0x20];
1341
1342         u8         dot3stats_frame_too_longs_high[0x20];
1343
1344         u8         dot3stats_frame_too_longs_low[0x20];
1345
1346         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1347
1348         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1349
1350         u8         dot3stats_symbol_errors_high[0x20];
1351
1352         u8         dot3stats_symbol_errors_low[0x20];
1353
1354         u8         dot3control_in_unknown_opcodes_high[0x20];
1355
1356         u8         dot3control_in_unknown_opcodes_low[0x20];
1357
1358         u8         dot3in_pause_frames_high[0x20];
1359
1360         u8         dot3in_pause_frames_low[0x20];
1361
1362         u8         dot3out_pause_frames_high[0x20];
1363
1364         u8         dot3out_pause_frames_low[0x20];
1365
1366         u8         reserved_at_400[0x3c0];
1367 };
1368
1369 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1370         u8         ether_stats_drop_events_high[0x20];
1371
1372         u8         ether_stats_drop_events_low[0x20];
1373
1374         u8         ether_stats_octets_high[0x20];
1375
1376         u8         ether_stats_octets_low[0x20];
1377
1378         u8         ether_stats_pkts_high[0x20];
1379
1380         u8         ether_stats_pkts_low[0x20];
1381
1382         u8         ether_stats_broadcast_pkts_high[0x20];
1383
1384         u8         ether_stats_broadcast_pkts_low[0x20];
1385
1386         u8         ether_stats_multicast_pkts_high[0x20];
1387
1388         u8         ether_stats_multicast_pkts_low[0x20];
1389
1390         u8         ether_stats_crc_align_errors_high[0x20];
1391
1392         u8         ether_stats_crc_align_errors_low[0x20];
1393
1394         u8         ether_stats_undersize_pkts_high[0x20];
1395
1396         u8         ether_stats_undersize_pkts_low[0x20];
1397
1398         u8         ether_stats_oversize_pkts_high[0x20];
1399
1400         u8         ether_stats_oversize_pkts_low[0x20];
1401
1402         u8         ether_stats_fragments_high[0x20];
1403
1404         u8         ether_stats_fragments_low[0x20];
1405
1406         u8         ether_stats_jabbers_high[0x20];
1407
1408         u8         ether_stats_jabbers_low[0x20];
1409
1410         u8         ether_stats_collisions_high[0x20];
1411
1412         u8         ether_stats_collisions_low[0x20];
1413
1414         u8         ether_stats_pkts64octets_high[0x20];
1415
1416         u8         ether_stats_pkts64octets_low[0x20];
1417
1418         u8         ether_stats_pkts65to127octets_high[0x20];
1419
1420         u8         ether_stats_pkts65to127octets_low[0x20];
1421
1422         u8         ether_stats_pkts128to255octets_high[0x20];
1423
1424         u8         ether_stats_pkts128to255octets_low[0x20];
1425
1426         u8         ether_stats_pkts256to511octets_high[0x20];
1427
1428         u8         ether_stats_pkts256to511octets_low[0x20];
1429
1430         u8         ether_stats_pkts512to1023octets_high[0x20];
1431
1432         u8         ether_stats_pkts512to1023octets_low[0x20];
1433
1434         u8         ether_stats_pkts1024to1518octets_high[0x20];
1435
1436         u8         ether_stats_pkts1024to1518octets_low[0x20];
1437
1438         u8         ether_stats_pkts1519to2047octets_high[0x20];
1439
1440         u8         ether_stats_pkts1519to2047octets_low[0x20];
1441
1442         u8         ether_stats_pkts2048to4095octets_high[0x20];
1443
1444         u8         ether_stats_pkts2048to4095octets_low[0x20];
1445
1446         u8         ether_stats_pkts4096to8191octets_high[0x20];
1447
1448         u8         ether_stats_pkts4096to8191octets_low[0x20];
1449
1450         u8         ether_stats_pkts8192to10239octets_high[0x20];
1451
1452         u8         ether_stats_pkts8192to10239octets_low[0x20];
1453
1454         u8         reserved_at_540[0x280];
1455 };
1456
1457 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1458         u8         if_in_octets_high[0x20];
1459
1460         u8         if_in_octets_low[0x20];
1461
1462         u8         if_in_ucast_pkts_high[0x20];
1463
1464         u8         if_in_ucast_pkts_low[0x20];
1465
1466         u8         if_in_discards_high[0x20];
1467
1468         u8         if_in_discards_low[0x20];
1469
1470         u8         if_in_errors_high[0x20];
1471
1472         u8         if_in_errors_low[0x20];
1473
1474         u8         if_in_unknown_protos_high[0x20];
1475
1476         u8         if_in_unknown_protos_low[0x20];
1477
1478         u8         if_out_octets_high[0x20];
1479
1480         u8         if_out_octets_low[0x20];
1481
1482         u8         if_out_ucast_pkts_high[0x20];
1483
1484         u8         if_out_ucast_pkts_low[0x20];
1485
1486         u8         if_out_discards_high[0x20];
1487
1488         u8         if_out_discards_low[0x20];
1489
1490         u8         if_out_errors_high[0x20];
1491
1492         u8         if_out_errors_low[0x20];
1493
1494         u8         if_in_multicast_pkts_high[0x20];
1495
1496         u8         if_in_multicast_pkts_low[0x20];
1497
1498         u8         if_in_broadcast_pkts_high[0x20];
1499
1500         u8         if_in_broadcast_pkts_low[0x20];
1501
1502         u8         if_out_multicast_pkts_high[0x20];
1503
1504         u8         if_out_multicast_pkts_low[0x20];
1505
1506         u8         if_out_broadcast_pkts_high[0x20];
1507
1508         u8         if_out_broadcast_pkts_low[0x20];
1509
1510         u8         reserved_at_340[0x480];
1511 };
1512
1513 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1514         u8         a_frames_transmitted_ok_high[0x20];
1515
1516         u8         a_frames_transmitted_ok_low[0x20];
1517
1518         u8         a_frames_received_ok_high[0x20];
1519
1520         u8         a_frames_received_ok_low[0x20];
1521
1522         u8         a_frame_check_sequence_errors_high[0x20];
1523
1524         u8         a_frame_check_sequence_errors_low[0x20];
1525
1526         u8         a_alignment_errors_high[0x20];
1527
1528         u8         a_alignment_errors_low[0x20];
1529
1530         u8         a_octets_transmitted_ok_high[0x20];
1531
1532         u8         a_octets_transmitted_ok_low[0x20];
1533
1534         u8         a_octets_received_ok_high[0x20];
1535
1536         u8         a_octets_received_ok_low[0x20];
1537
1538         u8         a_multicast_frames_xmitted_ok_high[0x20];
1539
1540         u8         a_multicast_frames_xmitted_ok_low[0x20];
1541
1542         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1543
1544         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1545
1546         u8         a_multicast_frames_received_ok_high[0x20];
1547
1548         u8         a_multicast_frames_received_ok_low[0x20];
1549
1550         u8         a_broadcast_frames_received_ok_high[0x20];
1551
1552         u8         a_broadcast_frames_received_ok_low[0x20];
1553
1554         u8         a_in_range_length_errors_high[0x20];
1555
1556         u8         a_in_range_length_errors_low[0x20];
1557
1558         u8         a_out_of_range_length_field_high[0x20];
1559
1560         u8         a_out_of_range_length_field_low[0x20];
1561
1562         u8         a_frame_too_long_errors_high[0x20];
1563
1564         u8         a_frame_too_long_errors_low[0x20];
1565
1566         u8         a_symbol_error_during_carrier_high[0x20];
1567
1568         u8         a_symbol_error_during_carrier_low[0x20];
1569
1570         u8         a_mac_control_frames_transmitted_high[0x20];
1571
1572         u8         a_mac_control_frames_transmitted_low[0x20];
1573
1574         u8         a_mac_control_frames_received_high[0x20];
1575
1576         u8         a_mac_control_frames_received_low[0x20];
1577
1578         u8         a_unsupported_opcodes_received_high[0x20];
1579
1580         u8         a_unsupported_opcodes_received_low[0x20];
1581
1582         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1583
1584         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1585
1586         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1587
1588         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1589
1590         u8         reserved_at_4c0[0x300];
1591 };
1592
1593 struct mlx5_ifc_cmd_inter_comp_event_bits {
1594         u8         command_completion_vector[0x20];
1595
1596         u8         reserved_at_20[0xc0];
1597 };
1598
1599 struct mlx5_ifc_stall_vl_event_bits {
1600         u8         reserved_at_0[0x18];
1601         u8         port_num[0x1];
1602         u8         reserved_at_19[0x3];
1603         u8         vl[0x4];
1604
1605         u8         reserved_at_20[0xa0];
1606 };
1607
1608 struct mlx5_ifc_db_bf_congestion_event_bits {
1609         u8         event_subtype[0x8];
1610         u8         reserved_at_8[0x8];
1611         u8         congestion_level[0x8];
1612         u8         reserved_at_18[0x8];
1613
1614         u8         reserved_at_20[0xa0];
1615 };
1616
1617 struct mlx5_ifc_gpio_event_bits {
1618         u8         reserved_at_0[0x60];
1619
1620         u8         gpio_event_hi[0x20];
1621
1622         u8         gpio_event_lo[0x20];
1623
1624         u8         reserved_at_a0[0x40];
1625 };
1626
1627 struct mlx5_ifc_port_state_change_event_bits {
1628         u8         reserved_at_0[0x40];
1629
1630         u8         port_num[0x4];
1631         u8         reserved_at_44[0x1c];
1632
1633         u8         reserved_at_60[0x80];
1634 };
1635
1636 struct mlx5_ifc_dropped_packet_logged_bits {
1637         u8         reserved_at_0[0xe0];
1638 };
1639
1640 enum {
1641         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1642         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1643 };
1644
1645 struct mlx5_ifc_cq_error_bits {
1646         u8         reserved_at_0[0x8];
1647         u8         cqn[0x18];
1648
1649         u8         reserved_at_20[0x20];
1650
1651         u8         reserved_at_40[0x18];
1652         u8         syndrome[0x8];
1653
1654         u8         reserved_at_60[0x80];
1655 };
1656
1657 struct mlx5_ifc_rdma_page_fault_event_bits {
1658         u8         bytes_committed[0x20];
1659
1660         u8         r_key[0x20];
1661
1662         u8         reserved_at_40[0x10];
1663         u8         packet_len[0x10];
1664
1665         u8         rdma_op_len[0x20];
1666
1667         u8         rdma_va[0x40];
1668
1669         u8         reserved_at_c0[0x5];
1670         u8         rdma[0x1];
1671         u8         write[0x1];
1672         u8         requestor[0x1];
1673         u8         qp_number[0x18];
1674 };
1675
1676 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1677         u8         bytes_committed[0x20];
1678
1679         u8         reserved_at_20[0x10];
1680         u8         wqe_index[0x10];
1681
1682         u8         reserved_at_40[0x10];
1683         u8         len[0x10];
1684
1685         u8         reserved_at_60[0x60];
1686
1687         u8         reserved_at_c0[0x5];
1688         u8         rdma[0x1];
1689         u8         write_read[0x1];
1690         u8         requestor[0x1];
1691         u8         qpn[0x18];
1692 };
1693
1694 struct mlx5_ifc_qp_events_bits {
1695         u8         reserved_at_0[0xa0];
1696
1697         u8         type[0x8];
1698         u8         reserved_at_a8[0x18];
1699
1700         u8         reserved_at_c0[0x8];
1701         u8         qpn_rqn_sqn[0x18];
1702 };
1703
1704 struct mlx5_ifc_dct_events_bits {
1705         u8         reserved_at_0[0xc0];
1706
1707         u8         reserved_at_c0[0x8];
1708         u8         dct_number[0x18];
1709 };
1710
1711 struct mlx5_ifc_comp_event_bits {
1712         u8         reserved_at_0[0xc0];
1713
1714         u8         reserved_at_c0[0x8];
1715         u8         cq_number[0x18];
1716 };
1717
1718 enum {
1719         MLX5_QPC_STATE_RST        = 0x0,
1720         MLX5_QPC_STATE_INIT       = 0x1,
1721         MLX5_QPC_STATE_RTR        = 0x2,
1722         MLX5_QPC_STATE_RTS        = 0x3,
1723         MLX5_QPC_STATE_SQER       = 0x4,
1724         MLX5_QPC_STATE_ERR        = 0x6,
1725         MLX5_QPC_STATE_SQD        = 0x7,
1726         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1727 };
1728
1729 enum {
1730         MLX5_QPC_ST_RC            = 0x0,
1731         MLX5_QPC_ST_UC            = 0x1,
1732         MLX5_QPC_ST_UD            = 0x2,
1733         MLX5_QPC_ST_XRC           = 0x3,
1734         MLX5_QPC_ST_DCI           = 0x5,
1735         MLX5_QPC_ST_QP0           = 0x7,
1736         MLX5_QPC_ST_QP1           = 0x8,
1737         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1738         MLX5_QPC_ST_REG_UMR       = 0xc,
1739 };
1740
1741 enum {
1742         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1743         MLX5_QPC_PM_STATE_REARM     = 0x1,
1744         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1745         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1746 };
1747
1748 enum {
1749         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1750         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1751 };
1752
1753 enum {
1754         MLX5_QPC_MTU_256_BYTES        = 0x1,
1755         MLX5_QPC_MTU_512_BYTES        = 0x2,
1756         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1757         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1758         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1759         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1760 };
1761
1762 enum {
1763         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1764         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1765         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1766         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1767         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1768         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1769         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1770         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1771 };
1772
1773 enum {
1774         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1775         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1776         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1777 };
1778
1779 enum {
1780         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1781         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1782         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1783 };
1784
1785 struct mlx5_ifc_qpc_bits {
1786         u8         state[0x4];
1787         u8         reserved_at_4[0x4];
1788         u8         st[0x8];
1789         u8         reserved_at_10[0x3];
1790         u8         pm_state[0x2];
1791         u8         reserved_at_15[0x7];
1792         u8         end_padding_mode[0x2];
1793         u8         reserved_at_1e[0x2];
1794
1795         u8         wq_signature[0x1];
1796         u8         block_lb_mc[0x1];
1797         u8         atomic_like_write_en[0x1];
1798         u8         latency_sensitive[0x1];
1799         u8         reserved_at_24[0x1];
1800         u8         drain_sigerr[0x1];
1801         u8         reserved_at_26[0x2];
1802         u8         pd[0x18];
1803
1804         u8         mtu[0x3];
1805         u8         log_msg_max[0x5];
1806         u8         reserved_at_48[0x1];
1807         u8         log_rq_size[0x4];
1808         u8         log_rq_stride[0x3];
1809         u8         no_sq[0x1];
1810         u8         log_sq_size[0x4];
1811         u8         reserved_at_55[0x6];
1812         u8         rlky[0x1];
1813         u8         reserved_at_5c[0x4];
1814
1815         u8         counter_set_id[0x8];
1816         u8         uar_page[0x18];
1817
1818         u8         reserved_at_80[0x8];
1819         u8         user_index[0x18];
1820
1821         u8         reserved_at_a0[0x3];
1822         u8         log_page_size[0x5];
1823         u8         remote_qpn[0x18];
1824
1825         struct mlx5_ifc_ads_bits primary_address_path;
1826
1827         struct mlx5_ifc_ads_bits secondary_address_path;
1828
1829         u8         log_ack_req_freq[0x4];
1830         u8         reserved_at_384[0x4];
1831         u8         log_sra_max[0x3];
1832         u8         reserved_at_38b[0x2];
1833         u8         retry_count[0x3];
1834         u8         rnr_retry[0x3];
1835         u8         reserved_at_393[0x1];
1836         u8         fre[0x1];
1837         u8         cur_rnr_retry[0x3];
1838         u8         cur_retry_count[0x3];
1839         u8         reserved_at_39b[0x5];
1840
1841         u8         reserved_at_3a0[0x20];
1842
1843         u8         reserved_at_3c0[0x8];
1844         u8         next_send_psn[0x18];
1845
1846         u8         reserved_at_3e0[0x8];
1847         u8         cqn_snd[0x18];
1848
1849         u8         reserved_at_400[0x40];
1850
1851         u8         reserved_at_440[0x8];
1852         u8         last_acked_psn[0x18];
1853
1854         u8         reserved_at_460[0x8];
1855         u8         ssn[0x18];
1856
1857         u8         reserved_at_480[0x8];
1858         u8         log_rra_max[0x3];
1859         u8         reserved_at_48b[0x1];
1860         u8         atomic_mode[0x4];
1861         u8         rre[0x1];
1862         u8         rwe[0x1];
1863         u8         rae[0x1];
1864         u8         reserved_at_493[0x1];
1865         u8         page_offset[0x6];
1866         u8         reserved_at_49a[0x3];
1867         u8         cd_slave_receive[0x1];
1868         u8         cd_slave_send[0x1];
1869         u8         cd_master[0x1];
1870
1871         u8         reserved_at_4a0[0x3];
1872         u8         min_rnr_nak[0x5];
1873         u8         next_rcv_psn[0x18];
1874
1875         u8         reserved_at_4c0[0x8];
1876         u8         xrcd[0x18];
1877
1878         u8         reserved_at_4e0[0x8];
1879         u8         cqn_rcv[0x18];
1880
1881         u8         dbr_addr[0x40];
1882
1883         u8         q_key[0x20];
1884
1885         u8         reserved_at_560[0x5];
1886         u8         rq_type[0x3];
1887         u8         srqn_rmpn[0x18];
1888
1889         u8         reserved_at_580[0x8];
1890         u8         rmsn[0x18];
1891
1892         u8         hw_sq_wqebb_counter[0x10];
1893         u8         sw_sq_wqebb_counter[0x10];
1894
1895         u8         hw_rq_counter[0x20];
1896
1897         u8         sw_rq_counter[0x20];
1898
1899         u8         reserved_at_600[0x20];
1900
1901         u8         reserved_at_620[0xf];
1902         u8         cgs[0x1];
1903         u8         cs_req[0x8];
1904         u8         cs_res[0x8];
1905
1906         u8         dc_access_key[0x40];
1907
1908         u8         reserved_at_680[0xc0];
1909 };
1910
1911 struct mlx5_ifc_roce_addr_layout_bits {
1912         u8         source_l3_address[16][0x8];
1913
1914         u8         reserved_at_80[0x3];
1915         u8         vlan_valid[0x1];
1916         u8         vlan_id[0xc];
1917         u8         source_mac_47_32[0x10];
1918
1919         u8         source_mac_31_0[0x20];
1920
1921         u8         reserved_at_c0[0x14];
1922         u8         roce_l3_type[0x4];
1923         u8         roce_version[0x8];
1924
1925         u8         reserved_at_e0[0x20];
1926 };
1927
1928 union mlx5_ifc_hca_cap_union_bits {
1929         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1930         struct mlx5_ifc_odp_cap_bits odp_cap;
1931         struct mlx5_ifc_atomic_caps_bits atomic_caps;
1932         struct mlx5_ifc_roce_cap_bits roce_cap;
1933         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1934         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1935         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
1936         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
1937         u8         reserved_at_0[0x8000];
1938 };
1939
1940 enum {
1941         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
1942         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
1943         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
1944 };
1945
1946 struct mlx5_ifc_flow_context_bits {
1947         u8         reserved_at_0[0x20];
1948
1949         u8         group_id[0x20];
1950
1951         u8         reserved_at_40[0x8];
1952         u8         flow_tag[0x18];
1953
1954         u8         reserved_at_60[0x10];
1955         u8         action[0x10];
1956
1957         u8         reserved_at_80[0x8];
1958         u8         destination_list_size[0x18];
1959
1960         u8         reserved_at_a0[0x160];
1961
1962         struct mlx5_ifc_fte_match_param_bits match_value;
1963
1964         u8         reserved_at_1200[0x600];
1965
1966         struct mlx5_ifc_dest_format_struct_bits destination[0];
1967 };
1968
1969 enum {
1970         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
1971         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
1972 };
1973
1974 struct mlx5_ifc_xrc_srqc_bits {
1975         u8         state[0x4];
1976         u8         log_xrc_srq_size[0x4];
1977         u8         reserved_at_8[0x18];
1978
1979         u8         wq_signature[0x1];
1980         u8         cont_srq[0x1];
1981         u8         reserved_at_22[0x1];
1982         u8         rlky[0x1];
1983         u8         basic_cyclic_rcv_wqe[0x1];
1984         u8         log_rq_stride[0x3];
1985         u8         xrcd[0x18];
1986
1987         u8         page_offset[0x6];
1988         u8         reserved_at_46[0x2];
1989         u8         cqn[0x18];
1990
1991         u8         reserved_at_60[0x20];
1992
1993         u8         user_index_equal_xrc_srqn[0x1];
1994         u8         reserved_at_81[0x1];
1995         u8         log_page_size[0x6];
1996         u8         user_index[0x18];
1997
1998         u8         reserved_at_a0[0x20];
1999
2000         u8         reserved_at_c0[0x8];
2001         u8         pd[0x18];
2002
2003         u8         lwm[0x10];
2004         u8         wqe_cnt[0x10];
2005
2006         u8         reserved_at_100[0x40];
2007
2008         u8         db_record_addr_h[0x20];
2009
2010         u8         db_record_addr_l[0x1e];
2011         u8         reserved_at_17e[0x2];
2012
2013         u8         reserved_at_180[0x80];
2014 };
2015
2016 struct mlx5_ifc_traffic_counter_bits {
2017         u8         packets[0x40];
2018
2019         u8         octets[0x40];
2020 };
2021
2022 struct mlx5_ifc_tisc_bits {
2023         u8         reserved_at_0[0xc];
2024         u8         prio[0x4];
2025         u8         reserved_at_10[0x10];
2026
2027         u8         reserved_at_20[0x100];
2028
2029         u8         reserved_at_120[0x8];
2030         u8         transport_domain[0x18];
2031
2032         u8         reserved_at_140[0x3c0];
2033 };
2034
2035 enum {
2036         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2037         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2038 };
2039
2040 enum {
2041         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2042         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2043 };
2044
2045 enum {
2046         MLX5_RX_HASH_FN_NONE           = 0x0,
2047         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2048         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2049 };
2050
2051 enum {
2052         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2053         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2054 };
2055
2056 struct mlx5_ifc_tirc_bits {
2057         u8         reserved_at_0[0x20];
2058
2059         u8         disp_type[0x4];
2060         u8         reserved_at_24[0x1c];
2061
2062         u8         reserved_at_40[0x40];
2063
2064         u8         reserved_at_80[0x4];
2065         u8         lro_timeout_period_usecs[0x10];
2066         u8         lro_enable_mask[0x4];
2067         u8         lro_max_ip_payload_size[0x8];
2068
2069         u8         reserved_at_a0[0x40];
2070
2071         u8         reserved_at_e0[0x8];
2072         u8         inline_rqn[0x18];
2073
2074         u8         rx_hash_symmetric[0x1];
2075         u8         reserved_at_101[0x1];
2076         u8         tunneled_offload_en[0x1];
2077         u8         reserved_at_103[0x5];
2078         u8         indirect_table[0x18];
2079
2080         u8         rx_hash_fn[0x4];
2081         u8         reserved_at_124[0x2];
2082         u8         self_lb_block[0x2];
2083         u8         transport_domain[0x18];
2084
2085         u8         rx_hash_toeplitz_key[10][0x20];
2086
2087         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2088
2089         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2090
2091         u8         reserved_at_2c0[0x4c0];
2092 };
2093
2094 enum {
2095         MLX5_SRQC_STATE_GOOD   = 0x0,
2096         MLX5_SRQC_STATE_ERROR  = 0x1,
2097 };
2098
2099 struct mlx5_ifc_srqc_bits {
2100         u8         state[0x4];
2101         u8         log_srq_size[0x4];
2102         u8         reserved_at_8[0x18];
2103
2104         u8         wq_signature[0x1];
2105         u8         cont_srq[0x1];
2106         u8         reserved_at_22[0x1];
2107         u8         rlky[0x1];
2108         u8         reserved_at_24[0x1];
2109         u8         log_rq_stride[0x3];
2110         u8         xrcd[0x18];
2111
2112         u8         page_offset[0x6];
2113         u8         reserved_at_46[0x2];
2114         u8         cqn[0x18];
2115
2116         u8         reserved_at_60[0x20];
2117
2118         u8         reserved_at_80[0x2];
2119         u8         log_page_size[0x6];
2120         u8         reserved_at_88[0x18];
2121
2122         u8         reserved_at_a0[0x20];
2123
2124         u8         reserved_at_c0[0x8];
2125         u8         pd[0x18];
2126
2127         u8         lwm[0x10];
2128         u8         wqe_cnt[0x10];
2129
2130         u8         reserved_at_100[0x40];
2131
2132         u8         dbr_addr[0x40];
2133
2134         u8         reserved_at_180[0x80];
2135 };
2136
2137 enum {
2138         MLX5_SQC_STATE_RST  = 0x0,
2139         MLX5_SQC_STATE_RDY  = 0x1,
2140         MLX5_SQC_STATE_ERR  = 0x3,
2141 };
2142
2143 struct mlx5_ifc_sqc_bits {
2144         u8         rlky[0x1];
2145         u8         cd_master[0x1];
2146         u8         fre[0x1];
2147         u8         flush_in_error_en[0x1];
2148         u8         reserved_at_4[0x4];
2149         u8         state[0x4];
2150         u8         reserved_at_c[0x14];
2151
2152         u8         reserved_at_20[0x8];
2153         u8         user_index[0x18];
2154
2155         u8         reserved_at_40[0x8];
2156         u8         cqn[0x18];
2157
2158         u8         reserved_at_60[0xa0];
2159
2160         u8         tis_lst_sz[0x10];
2161         u8         reserved_at_110[0x10];
2162
2163         u8         reserved_at_120[0x40];
2164
2165         u8         reserved_at_160[0x8];
2166         u8         tis_num_0[0x18];
2167
2168         struct mlx5_ifc_wq_bits wq;
2169 };
2170
2171 struct mlx5_ifc_rqtc_bits {
2172         u8         reserved_at_0[0xa0];
2173
2174         u8         reserved_at_a0[0x10];
2175         u8         rqt_max_size[0x10];
2176
2177         u8         reserved_at_c0[0x10];
2178         u8         rqt_actual_size[0x10];
2179
2180         u8         reserved_at_e0[0x6a0];
2181
2182         struct mlx5_ifc_rq_num_bits rq_num[0];
2183 };
2184
2185 enum {
2186         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2187         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2188 };
2189
2190 enum {
2191         MLX5_RQC_STATE_RST  = 0x0,
2192         MLX5_RQC_STATE_RDY  = 0x1,
2193         MLX5_RQC_STATE_ERR  = 0x3,
2194 };
2195
2196 struct mlx5_ifc_rqc_bits {
2197         u8         rlky[0x1];
2198         u8         reserved_at_1[0x2];
2199         u8         vsd[0x1];
2200         u8         mem_rq_type[0x4];
2201         u8         state[0x4];
2202         u8         reserved_at_c[0x1];
2203         u8         flush_in_error_en[0x1];
2204         u8         reserved_at_e[0x12];
2205
2206         u8         reserved_at_20[0x8];
2207         u8         user_index[0x18];
2208
2209         u8         reserved_at_40[0x8];
2210         u8         cqn[0x18];
2211
2212         u8         counter_set_id[0x8];
2213         u8         reserved_at_68[0x18];
2214
2215         u8         reserved_at_80[0x8];
2216         u8         rmpn[0x18];
2217
2218         u8         reserved_at_a0[0xe0];
2219
2220         struct mlx5_ifc_wq_bits wq;
2221 };
2222
2223 enum {
2224         MLX5_RMPC_STATE_RDY  = 0x1,
2225         MLX5_RMPC_STATE_ERR  = 0x3,
2226 };
2227
2228 struct mlx5_ifc_rmpc_bits {
2229         u8         reserved_at_0[0x8];
2230         u8         state[0x4];
2231         u8         reserved_at_c[0x14];
2232
2233         u8         basic_cyclic_rcv_wqe[0x1];
2234         u8         reserved_at_21[0x1f];
2235
2236         u8         reserved_at_40[0x140];
2237
2238         struct mlx5_ifc_wq_bits wq;
2239 };
2240
2241 struct mlx5_ifc_nic_vport_context_bits {
2242         u8         reserved_at_0[0x1f];
2243         u8         roce_en[0x1];
2244
2245         u8         arm_change_event[0x1];
2246         u8         reserved_at_21[0x1a];
2247         u8         event_on_mtu[0x1];
2248         u8         event_on_promisc_change[0x1];
2249         u8         event_on_vlan_change[0x1];
2250         u8         event_on_mc_address_change[0x1];
2251         u8         event_on_uc_address_change[0x1];
2252
2253         u8         reserved_at_40[0xf0];
2254
2255         u8         mtu[0x10];
2256
2257         u8         system_image_guid[0x40];
2258         u8         port_guid[0x40];
2259         u8         node_guid[0x40];
2260
2261         u8         reserved_at_200[0x140];
2262         u8         qkey_violation_counter[0x10];
2263         u8         reserved_at_350[0x430];
2264
2265         u8         promisc_uc[0x1];
2266         u8         promisc_mc[0x1];
2267         u8         promisc_all[0x1];
2268         u8         reserved_at_783[0x2];
2269         u8         allowed_list_type[0x3];
2270         u8         reserved_at_788[0xc];
2271         u8         allowed_list_size[0xc];
2272
2273         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2274
2275         u8         reserved_at_7e0[0x20];
2276
2277         u8         current_uc_mac_address[0][0x40];
2278 };
2279
2280 enum {
2281         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2282         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2283         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2284 };
2285
2286 struct mlx5_ifc_mkc_bits {
2287         u8         reserved_at_0[0x1];
2288         u8         free[0x1];
2289         u8         reserved_at_2[0xd];
2290         u8         small_fence_on_rdma_read_response[0x1];
2291         u8         umr_en[0x1];
2292         u8         a[0x1];
2293         u8         rw[0x1];
2294         u8         rr[0x1];
2295         u8         lw[0x1];
2296         u8         lr[0x1];
2297         u8         access_mode[0x2];
2298         u8         reserved_at_18[0x8];
2299
2300         u8         qpn[0x18];
2301         u8         mkey_7_0[0x8];
2302
2303         u8         reserved_at_40[0x20];
2304
2305         u8         length64[0x1];
2306         u8         bsf_en[0x1];
2307         u8         sync_umr[0x1];
2308         u8         reserved_at_63[0x2];
2309         u8         expected_sigerr_count[0x1];
2310         u8         reserved_at_66[0x1];
2311         u8         en_rinval[0x1];
2312         u8         pd[0x18];
2313
2314         u8         start_addr[0x40];
2315
2316         u8         len[0x40];
2317
2318         u8         bsf_octword_size[0x20];
2319
2320         u8         reserved_at_120[0x80];
2321
2322         u8         translations_octword_size[0x20];
2323
2324         u8         reserved_at_1c0[0x1b];
2325         u8         log_page_size[0x5];
2326
2327         u8         reserved_at_1e0[0x20];
2328 };
2329
2330 struct mlx5_ifc_pkey_bits {
2331         u8         reserved_at_0[0x10];
2332         u8         pkey[0x10];
2333 };
2334
2335 struct mlx5_ifc_array128_auto_bits {
2336         u8         array128_auto[16][0x8];
2337 };
2338
2339 struct mlx5_ifc_hca_vport_context_bits {
2340         u8         field_select[0x20];
2341
2342         u8         reserved_at_20[0xe0];
2343
2344         u8         sm_virt_aware[0x1];
2345         u8         has_smi[0x1];
2346         u8         has_raw[0x1];
2347         u8         grh_required[0x1];
2348         u8         reserved_at_104[0xc];
2349         u8         port_physical_state[0x4];
2350         u8         vport_state_policy[0x4];
2351         u8         port_state[0x4];
2352         u8         vport_state[0x4];
2353
2354         u8         reserved_at_120[0x20];
2355
2356         u8         system_image_guid[0x40];
2357
2358         u8         port_guid[0x40];
2359
2360         u8         node_guid[0x40];
2361
2362         u8         cap_mask1[0x20];
2363
2364         u8         cap_mask1_field_select[0x20];
2365
2366         u8         cap_mask2[0x20];
2367
2368         u8         cap_mask2_field_select[0x20];
2369
2370         u8         reserved_at_280[0x80];
2371
2372         u8         lid[0x10];
2373         u8         reserved_at_310[0x4];
2374         u8         init_type_reply[0x4];
2375         u8         lmc[0x3];
2376         u8         subnet_timeout[0x5];
2377
2378         u8         sm_lid[0x10];
2379         u8         sm_sl[0x4];
2380         u8         reserved_at_334[0xc];
2381
2382         u8         qkey_violation_counter[0x10];
2383         u8         pkey_violation_counter[0x10];
2384
2385         u8         reserved_at_360[0xca0];
2386 };
2387
2388 struct mlx5_ifc_esw_vport_context_bits {
2389         u8         reserved_at_0[0x3];
2390         u8         vport_svlan_strip[0x1];
2391         u8         vport_cvlan_strip[0x1];
2392         u8         vport_svlan_insert[0x1];
2393         u8         vport_cvlan_insert[0x2];
2394         u8         reserved_at_8[0x18];
2395
2396         u8         reserved_at_20[0x20];
2397
2398         u8         svlan_cfi[0x1];
2399         u8         svlan_pcp[0x3];
2400         u8         svlan_id[0xc];
2401         u8         cvlan_cfi[0x1];
2402         u8         cvlan_pcp[0x3];
2403         u8         cvlan_id[0xc];
2404
2405         u8         reserved_at_60[0x7a0];
2406 };
2407
2408 enum {
2409         MLX5_EQC_STATUS_OK                = 0x0,
2410         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2411 };
2412
2413 enum {
2414         MLX5_EQC_ST_ARMED  = 0x9,
2415         MLX5_EQC_ST_FIRED  = 0xa,
2416 };
2417
2418 struct mlx5_ifc_eqc_bits {
2419         u8         status[0x4];
2420         u8         reserved_at_4[0x9];
2421         u8         ec[0x1];
2422         u8         oi[0x1];
2423         u8         reserved_at_f[0x5];
2424         u8         st[0x4];
2425         u8         reserved_at_18[0x8];
2426
2427         u8         reserved_at_20[0x20];
2428
2429         u8         reserved_at_40[0x14];
2430         u8         page_offset[0x6];
2431         u8         reserved_at_5a[0x6];
2432
2433         u8         reserved_at_60[0x3];
2434         u8         log_eq_size[0x5];
2435         u8         uar_page[0x18];
2436
2437         u8         reserved_at_80[0x20];
2438
2439         u8         reserved_at_a0[0x18];
2440         u8         intr[0x8];
2441
2442         u8         reserved_at_c0[0x3];
2443         u8         log_page_size[0x5];
2444         u8         reserved_at_c8[0x18];
2445
2446         u8         reserved_at_e0[0x60];
2447
2448         u8         reserved_at_140[0x8];
2449         u8         consumer_counter[0x18];
2450
2451         u8         reserved_at_160[0x8];
2452         u8         producer_counter[0x18];
2453
2454         u8         reserved_at_180[0x80];
2455 };
2456
2457 enum {
2458         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2459         MLX5_DCTC_STATE_DRAINING  = 0x1,
2460         MLX5_DCTC_STATE_DRAINED   = 0x2,
2461 };
2462
2463 enum {
2464         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2465         MLX5_DCTC_CS_RES_NA         = 0x1,
2466         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2467 };
2468
2469 enum {
2470         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2471         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2472         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2473         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2474         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2475 };
2476
2477 struct mlx5_ifc_dctc_bits {
2478         u8         reserved_at_0[0x4];
2479         u8         state[0x4];
2480         u8         reserved_at_8[0x18];
2481
2482         u8         reserved_at_20[0x8];
2483         u8         user_index[0x18];
2484
2485         u8         reserved_at_40[0x8];
2486         u8         cqn[0x18];
2487
2488         u8         counter_set_id[0x8];
2489         u8         atomic_mode[0x4];
2490         u8         rre[0x1];
2491         u8         rwe[0x1];
2492         u8         rae[0x1];
2493         u8         atomic_like_write_en[0x1];
2494         u8         latency_sensitive[0x1];
2495         u8         rlky[0x1];
2496         u8         free_ar[0x1];
2497         u8         reserved_at_73[0xd];
2498
2499         u8         reserved_at_80[0x8];
2500         u8         cs_res[0x8];
2501         u8         reserved_at_90[0x3];
2502         u8         min_rnr_nak[0x5];
2503         u8         reserved_at_98[0x8];
2504
2505         u8         reserved_at_a0[0x8];
2506         u8         srqn[0x18];
2507
2508         u8         reserved_at_c0[0x8];
2509         u8         pd[0x18];
2510
2511         u8         tclass[0x8];
2512         u8         reserved_at_e8[0x4];
2513         u8         flow_label[0x14];
2514
2515         u8         dc_access_key[0x40];
2516
2517         u8         reserved_at_140[0x5];
2518         u8         mtu[0x3];
2519         u8         port[0x8];
2520         u8         pkey_index[0x10];
2521
2522         u8         reserved_at_160[0x8];
2523         u8         my_addr_index[0x8];
2524         u8         reserved_at_170[0x8];
2525         u8         hop_limit[0x8];
2526
2527         u8         dc_access_key_violation_count[0x20];
2528
2529         u8         reserved_at_1a0[0x14];
2530         u8         dei_cfi[0x1];
2531         u8         eth_prio[0x3];
2532         u8         ecn[0x2];
2533         u8         dscp[0x6];
2534
2535         u8         reserved_at_1c0[0x40];
2536 };
2537
2538 enum {
2539         MLX5_CQC_STATUS_OK             = 0x0,
2540         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2541         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2542 };
2543
2544 enum {
2545         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2546         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2547 };
2548
2549 enum {
2550         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2551         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2552         MLX5_CQC_ST_FIRED                                 = 0xa,
2553 };
2554
2555 struct mlx5_ifc_cqc_bits {
2556         u8         status[0x4];
2557         u8         reserved_at_4[0x4];
2558         u8         cqe_sz[0x3];
2559         u8         cc[0x1];
2560         u8         reserved_at_c[0x1];
2561         u8         scqe_break_moderation_en[0x1];
2562         u8         oi[0x1];
2563         u8         reserved_at_f[0x2];
2564         u8         cqe_zip_en[0x1];
2565         u8         mini_cqe_res_format[0x2];
2566         u8         st[0x4];
2567         u8         reserved_at_18[0x8];
2568
2569         u8         reserved_at_20[0x20];
2570
2571         u8         reserved_at_40[0x14];
2572         u8         page_offset[0x6];
2573         u8         reserved_at_5a[0x6];
2574
2575         u8         reserved_at_60[0x3];
2576         u8         log_cq_size[0x5];
2577         u8         uar_page[0x18];
2578
2579         u8         reserved_at_80[0x4];
2580         u8         cq_period[0xc];
2581         u8         cq_max_count[0x10];
2582
2583         u8         reserved_at_a0[0x18];
2584         u8         c_eqn[0x8];
2585
2586         u8         reserved_at_c0[0x3];
2587         u8         log_page_size[0x5];
2588         u8         reserved_at_c8[0x18];
2589
2590         u8         reserved_at_e0[0x20];
2591
2592         u8         reserved_at_100[0x8];
2593         u8         last_notified_index[0x18];
2594
2595         u8         reserved_at_120[0x8];
2596         u8         last_solicit_index[0x18];
2597
2598         u8         reserved_at_140[0x8];
2599         u8         consumer_counter[0x18];
2600
2601         u8         reserved_at_160[0x8];
2602         u8         producer_counter[0x18];
2603
2604         u8         reserved_at_180[0x40];
2605
2606         u8         dbr_addr[0x40];
2607 };
2608
2609 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2610         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2611         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2612         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2613         u8         reserved_at_0[0x800];
2614 };
2615
2616 struct mlx5_ifc_query_adapter_param_block_bits {
2617         u8         reserved_at_0[0xc0];
2618
2619         u8         reserved_at_c0[0x8];
2620         u8         ieee_vendor_id[0x18];
2621
2622         u8         reserved_at_e0[0x10];
2623         u8         vsd_vendor_id[0x10];
2624
2625         u8         vsd[208][0x8];
2626
2627         u8         vsd_contd_psid[16][0x8];
2628 };
2629
2630 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2631         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2632         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2633         u8         reserved_at_0[0x20];
2634 };
2635
2636 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2637         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2638         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2639         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2640         u8         reserved_at_0[0x20];
2641 };
2642
2643 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2644         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2645         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2646         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2647         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2648         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2649         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2650         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2651         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2652         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2653         u8         reserved_at_0[0x7c0];
2654 };
2655
2656 union mlx5_ifc_event_auto_bits {
2657         struct mlx5_ifc_comp_event_bits comp_event;
2658         struct mlx5_ifc_dct_events_bits dct_events;
2659         struct mlx5_ifc_qp_events_bits qp_events;
2660         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2661         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2662         struct mlx5_ifc_cq_error_bits cq_error;
2663         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2664         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2665         struct mlx5_ifc_gpio_event_bits gpio_event;
2666         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2667         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2668         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2669         u8         reserved_at_0[0xe0];
2670 };
2671
2672 struct mlx5_ifc_health_buffer_bits {
2673         u8         reserved_at_0[0x100];
2674
2675         u8         assert_existptr[0x20];
2676
2677         u8         assert_callra[0x20];
2678
2679         u8         reserved_at_140[0x40];
2680
2681         u8         fw_version[0x20];
2682
2683         u8         hw_id[0x20];
2684
2685         u8         reserved_at_1c0[0x20];
2686
2687         u8         irisc_index[0x8];
2688         u8         synd[0x8];
2689         u8         ext_synd[0x10];
2690 };
2691
2692 struct mlx5_ifc_register_loopback_control_bits {
2693         u8         no_lb[0x1];
2694         u8         reserved_at_1[0x7];
2695         u8         port[0x8];
2696         u8         reserved_at_10[0x10];
2697
2698         u8         reserved_at_20[0x60];
2699 };
2700
2701 struct mlx5_ifc_teardown_hca_out_bits {
2702         u8         status[0x8];
2703         u8         reserved_at_8[0x18];
2704
2705         u8         syndrome[0x20];
2706
2707         u8         reserved_at_40[0x40];
2708 };
2709
2710 enum {
2711         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
2712         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
2713 };
2714
2715 struct mlx5_ifc_teardown_hca_in_bits {
2716         u8         opcode[0x10];
2717         u8         reserved_at_10[0x10];
2718
2719         u8         reserved_at_20[0x10];
2720         u8         op_mod[0x10];
2721
2722         u8         reserved_at_40[0x10];
2723         u8         profile[0x10];
2724
2725         u8         reserved_at_60[0x20];
2726 };
2727
2728 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2729         u8         status[0x8];
2730         u8         reserved_at_8[0x18];
2731
2732         u8         syndrome[0x20];
2733
2734         u8         reserved_at_40[0x40];
2735 };
2736
2737 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2738         u8         opcode[0x10];
2739         u8         reserved_at_10[0x10];
2740
2741         u8         reserved_at_20[0x10];
2742         u8         op_mod[0x10];
2743
2744         u8         reserved_at_40[0x8];
2745         u8         qpn[0x18];
2746
2747         u8         reserved_at_60[0x20];
2748
2749         u8         opt_param_mask[0x20];
2750
2751         u8         reserved_at_a0[0x20];
2752
2753         struct mlx5_ifc_qpc_bits qpc;
2754
2755         u8         reserved_at_800[0x80];
2756 };
2757
2758 struct mlx5_ifc_sqd2rts_qp_out_bits {
2759         u8         status[0x8];
2760         u8         reserved_at_8[0x18];
2761
2762         u8         syndrome[0x20];
2763
2764         u8         reserved_at_40[0x40];
2765 };
2766
2767 struct mlx5_ifc_sqd2rts_qp_in_bits {
2768         u8         opcode[0x10];
2769         u8         reserved_at_10[0x10];
2770
2771         u8         reserved_at_20[0x10];
2772         u8         op_mod[0x10];
2773
2774         u8         reserved_at_40[0x8];
2775         u8         qpn[0x18];
2776
2777         u8         reserved_at_60[0x20];
2778
2779         u8         opt_param_mask[0x20];
2780
2781         u8         reserved_at_a0[0x20];
2782
2783         struct mlx5_ifc_qpc_bits qpc;
2784
2785         u8         reserved_at_800[0x80];
2786 };
2787
2788 struct mlx5_ifc_set_roce_address_out_bits {
2789         u8         status[0x8];
2790         u8         reserved_at_8[0x18];
2791
2792         u8         syndrome[0x20];
2793
2794         u8         reserved_at_40[0x40];
2795 };
2796
2797 struct mlx5_ifc_set_roce_address_in_bits {
2798         u8         opcode[0x10];
2799         u8         reserved_at_10[0x10];
2800
2801         u8         reserved_at_20[0x10];
2802         u8         op_mod[0x10];
2803
2804         u8         roce_address_index[0x10];
2805         u8         reserved_at_50[0x10];
2806
2807         u8         reserved_at_60[0x20];
2808
2809         struct mlx5_ifc_roce_addr_layout_bits roce_address;
2810 };
2811
2812 struct mlx5_ifc_set_mad_demux_out_bits {
2813         u8         status[0x8];
2814         u8         reserved_at_8[0x18];
2815
2816         u8         syndrome[0x20];
2817
2818         u8         reserved_at_40[0x40];
2819 };
2820
2821 enum {
2822         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
2823         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
2824 };
2825
2826 struct mlx5_ifc_set_mad_demux_in_bits {
2827         u8         opcode[0x10];
2828         u8         reserved_at_10[0x10];
2829
2830         u8         reserved_at_20[0x10];
2831         u8         op_mod[0x10];
2832
2833         u8         reserved_at_40[0x20];
2834
2835         u8         reserved_at_60[0x6];
2836         u8         demux_mode[0x2];
2837         u8         reserved_at_68[0x18];
2838 };
2839
2840 struct mlx5_ifc_set_l2_table_entry_out_bits {
2841         u8         status[0x8];
2842         u8         reserved_at_8[0x18];
2843
2844         u8         syndrome[0x20];
2845
2846         u8         reserved_at_40[0x40];
2847 };
2848
2849 struct mlx5_ifc_set_l2_table_entry_in_bits {
2850         u8         opcode[0x10];
2851         u8         reserved_at_10[0x10];
2852
2853         u8         reserved_at_20[0x10];
2854         u8         op_mod[0x10];
2855
2856         u8         reserved_at_40[0x60];
2857
2858         u8         reserved_at_a0[0x8];
2859         u8         table_index[0x18];
2860
2861         u8         reserved_at_c0[0x20];
2862
2863         u8         reserved_at_e0[0x13];
2864         u8         vlan_valid[0x1];
2865         u8         vlan[0xc];
2866
2867         struct mlx5_ifc_mac_address_layout_bits mac_address;
2868
2869         u8         reserved_at_140[0xc0];
2870 };
2871
2872 struct mlx5_ifc_set_issi_out_bits {
2873         u8         status[0x8];
2874         u8         reserved_at_8[0x18];
2875
2876         u8         syndrome[0x20];
2877
2878         u8         reserved_at_40[0x40];
2879 };
2880
2881 struct mlx5_ifc_set_issi_in_bits {
2882         u8         opcode[0x10];
2883         u8         reserved_at_10[0x10];
2884
2885         u8         reserved_at_20[0x10];
2886         u8         op_mod[0x10];
2887
2888         u8         reserved_at_40[0x10];
2889         u8         current_issi[0x10];
2890
2891         u8         reserved_at_60[0x20];
2892 };
2893
2894 struct mlx5_ifc_set_hca_cap_out_bits {
2895         u8         status[0x8];
2896         u8         reserved_at_8[0x18];
2897
2898         u8         syndrome[0x20];
2899
2900         u8         reserved_at_40[0x40];
2901 };
2902
2903 struct mlx5_ifc_set_hca_cap_in_bits {
2904         u8         opcode[0x10];
2905         u8         reserved_at_10[0x10];
2906
2907         u8         reserved_at_20[0x10];
2908         u8         op_mod[0x10];
2909
2910         u8         reserved_at_40[0x40];
2911
2912         union mlx5_ifc_hca_cap_union_bits capability;
2913 };
2914
2915 enum {
2916         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
2917         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
2918         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
2919         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
2920 };
2921
2922 struct mlx5_ifc_set_fte_out_bits {
2923         u8         status[0x8];
2924         u8         reserved_at_8[0x18];
2925
2926         u8         syndrome[0x20];
2927
2928         u8         reserved_at_40[0x40];
2929 };
2930
2931 struct mlx5_ifc_set_fte_in_bits {
2932         u8         opcode[0x10];
2933         u8         reserved_at_10[0x10];
2934
2935         u8         reserved_at_20[0x10];
2936         u8         op_mod[0x10];
2937
2938         u8         reserved_at_40[0x40];
2939
2940         u8         table_type[0x8];
2941         u8         reserved_at_88[0x18];
2942
2943         u8         reserved_at_a0[0x8];
2944         u8         table_id[0x18];
2945
2946         u8         reserved_at_c0[0x18];
2947         u8         modify_enable_mask[0x8];
2948
2949         u8         reserved_at_e0[0x20];
2950
2951         u8         flow_index[0x20];
2952
2953         u8         reserved_at_120[0xe0];
2954
2955         struct mlx5_ifc_flow_context_bits flow_context;
2956 };
2957
2958 struct mlx5_ifc_rts2rts_qp_out_bits {
2959         u8         status[0x8];
2960         u8         reserved_at_8[0x18];
2961
2962         u8         syndrome[0x20];
2963
2964         u8         reserved_at_40[0x40];
2965 };
2966
2967 struct mlx5_ifc_rts2rts_qp_in_bits {
2968         u8         opcode[0x10];
2969         u8         reserved_at_10[0x10];
2970
2971         u8         reserved_at_20[0x10];
2972         u8         op_mod[0x10];
2973
2974         u8         reserved_at_40[0x8];
2975         u8         qpn[0x18];
2976
2977         u8         reserved_at_60[0x20];
2978
2979         u8         opt_param_mask[0x20];
2980
2981         u8         reserved_at_a0[0x20];
2982
2983         struct mlx5_ifc_qpc_bits qpc;
2984
2985         u8         reserved_at_800[0x80];
2986 };
2987
2988 struct mlx5_ifc_rtr2rts_qp_out_bits {
2989         u8         status[0x8];
2990         u8         reserved_at_8[0x18];
2991
2992         u8         syndrome[0x20];
2993
2994         u8         reserved_at_40[0x40];
2995 };
2996
2997 struct mlx5_ifc_rtr2rts_qp_in_bits {
2998         u8         opcode[0x10];
2999         u8         reserved_at_10[0x10];
3000
3001         u8         reserved_at_20[0x10];
3002         u8         op_mod[0x10];
3003
3004         u8         reserved_at_40[0x8];
3005         u8         qpn[0x18];
3006
3007         u8         reserved_at_60[0x20];
3008
3009         u8         opt_param_mask[0x20];
3010
3011         u8         reserved_at_a0[0x20];
3012
3013         struct mlx5_ifc_qpc_bits qpc;
3014
3015         u8         reserved_at_800[0x80];
3016 };
3017
3018 struct mlx5_ifc_rst2init_qp_out_bits {
3019         u8         status[0x8];
3020         u8         reserved_at_8[0x18];
3021
3022         u8         syndrome[0x20];
3023
3024         u8         reserved_at_40[0x40];
3025 };
3026
3027 struct mlx5_ifc_rst2init_qp_in_bits {
3028         u8         opcode[0x10];
3029         u8         reserved_at_10[0x10];
3030
3031         u8         reserved_at_20[0x10];
3032         u8         op_mod[0x10];
3033
3034         u8         reserved_at_40[0x8];
3035         u8         qpn[0x18];
3036
3037         u8         reserved_at_60[0x20];
3038
3039         u8         opt_param_mask[0x20];
3040
3041         u8         reserved_at_a0[0x20];
3042
3043         struct mlx5_ifc_qpc_bits qpc;
3044
3045         u8         reserved_at_800[0x80];
3046 };
3047
3048 struct mlx5_ifc_query_xrc_srq_out_bits {
3049         u8         status[0x8];
3050         u8         reserved_at_8[0x18];
3051
3052         u8         syndrome[0x20];
3053
3054         u8         reserved_at_40[0x40];
3055
3056         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3057
3058         u8         reserved_at_280[0x600];
3059
3060         u8         pas[0][0x40];
3061 };
3062
3063 struct mlx5_ifc_query_xrc_srq_in_bits {
3064         u8         opcode[0x10];
3065         u8         reserved_at_10[0x10];
3066
3067         u8         reserved_at_20[0x10];
3068         u8         op_mod[0x10];
3069
3070         u8         reserved_at_40[0x8];
3071         u8         xrc_srqn[0x18];
3072
3073         u8         reserved_at_60[0x20];
3074 };
3075
3076 enum {
3077         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3078         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3079 };
3080
3081 struct mlx5_ifc_query_vport_state_out_bits {
3082         u8         status[0x8];
3083         u8         reserved_at_8[0x18];
3084
3085         u8         syndrome[0x20];
3086
3087         u8         reserved_at_40[0x20];
3088
3089         u8         reserved_at_60[0x18];
3090         u8         admin_state[0x4];
3091         u8         state[0x4];
3092 };
3093
3094 enum {
3095         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3096         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3097 };
3098
3099 struct mlx5_ifc_query_vport_state_in_bits {
3100         u8         opcode[0x10];
3101         u8         reserved_at_10[0x10];
3102
3103         u8         reserved_at_20[0x10];
3104         u8         op_mod[0x10];
3105
3106         u8         other_vport[0x1];
3107         u8         reserved_at_41[0xf];
3108         u8         vport_number[0x10];
3109
3110         u8         reserved_at_60[0x20];
3111 };
3112
3113 struct mlx5_ifc_query_vport_counter_out_bits {
3114         u8         status[0x8];
3115         u8         reserved_at_8[0x18];
3116
3117         u8         syndrome[0x20];
3118
3119         u8         reserved_at_40[0x40];
3120
3121         struct mlx5_ifc_traffic_counter_bits received_errors;
3122
3123         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3124
3125         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3126
3127         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3128
3129         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3130
3131         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3132
3133         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3134
3135         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3136
3137         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3138
3139         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3140
3141         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3142
3143         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3144
3145         u8         reserved_at_680[0xa00];
3146 };
3147
3148 enum {
3149         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3150 };
3151
3152 struct mlx5_ifc_query_vport_counter_in_bits {
3153         u8         opcode[0x10];
3154         u8         reserved_at_10[0x10];
3155
3156         u8         reserved_at_20[0x10];
3157         u8         op_mod[0x10];
3158
3159         u8         other_vport[0x1];
3160         u8         reserved_at_41[0xb];
3161         u8         port_num[0x4];
3162         u8         vport_number[0x10];
3163
3164         u8         reserved_at_60[0x60];
3165
3166         u8         clear[0x1];
3167         u8         reserved_at_c1[0x1f];
3168
3169         u8         reserved_at_e0[0x20];
3170 };
3171
3172 struct mlx5_ifc_query_tis_out_bits {
3173         u8         status[0x8];
3174         u8         reserved_at_8[0x18];
3175
3176         u8         syndrome[0x20];
3177
3178         u8         reserved_at_40[0x40];
3179
3180         struct mlx5_ifc_tisc_bits tis_context;
3181 };
3182
3183 struct mlx5_ifc_query_tis_in_bits {
3184         u8         opcode[0x10];
3185         u8         reserved_at_10[0x10];
3186
3187         u8         reserved_at_20[0x10];
3188         u8         op_mod[0x10];
3189
3190         u8         reserved_at_40[0x8];
3191         u8         tisn[0x18];
3192
3193         u8         reserved_at_60[0x20];
3194 };
3195
3196 struct mlx5_ifc_query_tir_out_bits {
3197         u8         status[0x8];
3198         u8         reserved_at_8[0x18];
3199
3200         u8         syndrome[0x20];
3201
3202         u8         reserved_at_40[0xc0];
3203
3204         struct mlx5_ifc_tirc_bits tir_context;
3205 };
3206
3207 struct mlx5_ifc_query_tir_in_bits {
3208         u8         opcode[0x10];
3209         u8         reserved_at_10[0x10];
3210
3211         u8         reserved_at_20[0x10];
3212         u8         op_mod[0x10];
3213
3214         u8         reserved_at_40[0x8];
3215         u8         tirn[0x18];
3216
3217         u8         reserved_at_60[0x20];
3218 };
3219
3220 struct mlx5_ifc_query_srq_out_bits {
3221         u8         status[0x8];
3222         u8         reserved_at_8[0x18];
3223
3224         u8         syndrome[0x20];
3225
3226         u8         reserved_at_40[0x40];
3227
3228         struct mlx5_ifc_srqc_bits srq_context_entry;
3229
3230         u8         reserved_at_280[0x600];
3231
3232         u8         pas[0][0x40];
3233 };
3234
3235 struct mlx5_ifc_query_srq_in_bits {
3236         u8         opcode[0x10];
3237         u8         reserved_at_10[0x10];
3238
3239         u8         reserved_at_20[0x10];
3240         u8         op_mod[0x10];
3241
3242         u8         reserved_at_40[0x8];
3243         u8         srqn[0x18];
3244
3245         u8         reserved_at_60[0x20];
3246 };
3247
3248 struct mlx5_ifc_query_sq_out_bits {
3249         u8         status[0x8];
3250         u8         reserved_at_8[0x18];
3251
3252         u8         syndrome[0x20];
3253
3254         u8         reserved_at_40[0xc0];
3255
3256         struct mlx5_ifc_sqc_bits sq_context;
3257 };
3258
3259 struct mlx5_ifc_query_sq_in_bits {
3260         u8         opcode[0x10];
3261         u8         reserved_at_10[0x10];
3262
3263         u8         reserved_at_20[0x10];
3264         u8         op_mod[0x10];
3265
3266         u8         reserved_at_40[0x8];
3267         u8         sqn[0x18];
3268
3269         u8         reserved_at_60[0x20];
3270 };
3271
3272 struct mlx5_ifc_query_special_contexts_out_bits {
3273         u8         status[0x8];
3274         u8         reserved_at_8[0x18];
3275
3276         u8         syndrome[0x20];
3277
3278         u8         reserved_at_40[0x20];
3279
3280         u8         resd_lkey[0x20];
3281 };
3282
3283 struct mlx5_ifc_query_special_contexts_in_bits {
3284         u8         opcode[0x10];
3285         u8         reserved_at_10[0x10];
3286
3287         u8         reserved_at_20[0x10];
3288         u8         op_mod[0x10];
3289
3290         u8         reserved_at_40[0x40];
3291 };
3292
3293 struct mlx5_ifc_query_rqt_out_bits {
3294         u8         status[0x8];
3295         u8         reserved_at_8[0x18];
3296
3297         u8         syndrome[0x20];
3298
3299         u8         reserved_at_40[0xc0];
3300
3301         struct mlx5_ifc_rqtc_bits rqt_context;
3302 };
3303
3304 struct mlx5_ifc_query_rqt_in_bits {
3305         u8         opcode[0x10];
3306         u8         reserved_at_10[0x10];
3307
3308         u8         reserved_at_20[0x10];
3309         u8         op_mod[0x10];
3310
3311         u8         reserved_at_40[0x8];
3312         u8         rqtn[0x18];
3313
3314         u8         reserved_at_60[0x20];
3315 };
3316
3317 struct mlx5_ifc_query_rq_out_bits {
3318         u8         status[0x8];
3319         u8         reserved_at_8[0x18];
3320
3321         u8         syndrome[0x20];
3322
3323         u8         reserved_at_40[0xc0];
3324
3325         struct mlx5_ifc_rqc_bits rq_context;
3326 };
3327
3328 struct mlx5_ifc_query_rq_in_bits {
3329         u8         opcode[0x10];
3330         u8         reserved_at_10[0x10];
3331
3332         u8         reserved_at_20[0x10];
3333         u8         op_mod[0x10];
3334
3335         u8         reserved_at_40[0x8];
3336         u8         rqn[0x18];
3337
3338         u8         reserved_at_60[0x20];
3339 };
3340
3341 struct mlx5_ifc_query_roce_address_out_bits {
3342         u8         status[0x8];
3343         u8         reserved_at_8[0x18];
3344
3345         u8         syndrome[0x20];
3346
3347         u8         reserved_at_40[0x40];
3348
3349         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3350 };
3351
3352 struct mlx5_ifc_query_roce_address_in_bits {
3353         u8         opcode[0x10];
3354         u8         reserved_at_10[0x10];
3355
3356         u8         reserved_at_20[0x10];
3357         u8         op_mod[0x10];
3358
3359         u8         roce_address_index[0x10];
3360         u8         reserved_at_50[0x10];
3361
3362         u8         reserved_at_60[0x20];
3363 };
3364
3365 struct mlx5_ifc_query_rmp_out_bits {
3366         u8         status[0x8];
3367         u8         reserved_at_8[0x18];
3368
3369         u8         syndrome[0x20];
3370
3371         u8         reserved_at_40[0xc0];
3372
3373         struct mlx5_ifc_rmpc_bits rmp_context;
3374 };
3375
3376 struct mlx5_ifc_query_rmp_in_bits {
3377         u8         opcode[0x10];
3378         u8         reserved_at_10[0x10];
3379
3380         u8         reserved_at_20[0x10];
3381         u8         op_mod[0x10];
3382
3383         u8         reserved_at_40[0x8];
3384         u8         rmpn[0x18];
3385
3386         u8         reserved_at_60[0x20];
3387 };
3388
3389 struct mlx5_ifc_query_qp_out_bits {
3390         u8         status[0x8];
3391         u8         reserved_at_8[0x18];
3392
3393         u8         syndrome[0x20];
3394
3395         u8         reserved_at_40[0x40];
3396
3397         u8         opt_param_mask[0x20];
3398
3399         u8         reserved_at_a0[0x20];
3400
3401         struct mlx5_ifc_qpc_bits qpc;
3402
3403         u8         reserved_at_800[0x80];
3404
3405         u8         pas[0][0x40];
3406 };
3407
3408 struct mlx5_ifc_query_qp_in_bits {
3409         u8         opcode[0x10];
3410         u8         reserved_at_10[0x10];
3411
3412         u8         reserved_at_20[0x10];
3413         u8         op_mod[0x10];
3414
3415         u8         reserved_at_40[0x8];
3416         u8         qpn[0x18];
3417
3418         u8         reserved_at_60[0x20];
3419 };
3420
3421 struct mlx5_ifc_query_q_counter_out_bits {
3422         u8         status[0x8];
3423         u8         reserved_at_8[0x18];
3424
3425         u8         syndrome[0x20];
3426
3427         u8         reserved_at_40[0x40];
3428
3429         u8         rx_write_requests[0x20];
3430
3431         u8         reserved_at_a0[0x20];
3432
3433         u8         rx_read_requests[0x20];
3434
3435         u8         reserved_at_e0[0x20];
3436
3437         u8         rx_atomic_requests[0x20];
3438
3439         u8         reserved_at_120[0x20];
3440
3441         u8         rx_dct_connect[0x20];
3442
3443         u8         reserved_at_160[0x20];
3444
3445         u8         out_of_buffer[0x20];
3446
3447         u8         reserved_at_1a0[0x20];
3448
3449         u8         out_of_sequence[0x20];
3450
3451         u8         reserved_at_1e0[0x620];
3452 };
3453
3454 struct mlx5_ifc_query_q_counter_in_bits {
3455         u8         opcode[0x10];
3456         u8         reserved_at_10[0x10];
3457
3458         u8         reserved_at_20[0x10];
3459         u8         op_mod[0x10];
3460
3461         u8         reserved_at_40[0x80];
3462
3463         u8         clear[0x1];
3464         u8         reserved_at_c1[0x1f];
3465
3466         u8         reserved_at_e0[0x18];
3467         u8         counter_set_id[0x8];
3468 };
3469
3470 struct mlx5_ifc_query_pages_out_bits {
3471         u8         status[0x8];
3472         u8         reserved_at_8[0x18];
3473
3474         u8         syndrome[0x20];
3475
3476         u8         reserved_at_40[0x10];
3477         u8         function_id[0x10];
3478
3479         u8         num_pages[0x20];
3480 };
3481
3482 enum {
3483         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3484         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3485         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3486 };
3487
3488 struct mlx5_ifc_query_pages_in_bits {
3489         u8         opcode[0x10];
3490         u8         reserved_at_10[0x10];
3491
3492         u8         reserved_at_20[0x10];
3493         u8         op_mod[0x10];
3494
3495         u8         reserved_at_40[0x10];
3496         u8         function_id[0x10];
3497
3498         u8         reserved_at_60[0x20];
3499 };
3500
3501 struct mlx5_ifc_query_nic_vport_context_out_bits {
3502         u8         status[0x8];
3503         u8         reserved_at_8[0x18];
3504
3505         u8         syndrome[0x20];
3506
3507         u8         reserved_at_40[0x40];
3508
3509         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3510 };
3511
3512 struct mlx5_ifc_query_nic_vport_context_in_bits {
3513         u8         opcode[0x10];
3514         u8         reserved_at_10[0x10];
3515
3516         u8         reserved_at_20[0x10];
3517         u8         op_mod[0x10];
3518
3519         u8         other_vport[0x1];
3520         u8         reserved_at_41[0xf];
3521         u8         vport_number[0x10];
3522
3523         u8         reserved_at_60[0x5];
3524         u8         allowed_list_type[0x3];
3525         u8         reserved_at_68[0x18];
3526 };
3527
3528 struct mlx5_ifc_query_mkey_out_bits {
3529         u8         status[0x8];
3530         u8         reserved_at_8[0x18];
3531
3532         u8         syndrome[0x20];
3533
3534         u8         reserved_at_40[0x40];
3535
3536         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3537
3538         u8         reserved_at_280[0x600];
3539
3540         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3541
3542         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3543 };
3544
3545 struct mlx5_ifc_query_mkey_in_bits {
3546         u8         opcode[0x10];
3547         u8         reserved_at_10[0x10];
3548
3549         u8         reserved_at_20[0x10];
3550         u8         op_mod[0x10];
3551
3552         u8         reserved_at_40[0x8];
3553         u8         mkey_index[0x18];
3554
3555         u8         pg_access[0x1];
3556         u8         reserved_at_61[0x1f];
3557 };
3558
3559 struct mlx5_ifc_query_mad_demux_out_bits {
3560         u8         status[0x8];
3561         u8         reserved_at_8[0x18];
3562
3563         u8         syndrome[0x20];
3564
3565         u8         reserved_at_40[0x40];
3566
3567         u8         mad_dumux_parameters_block[0x20];
3568 };
3569
3570 struct mlx5_ifc_query_mad_demux_in_bits {
3571         u8         opcode[0x10];
3572         u8         reserved_at_10[0x10];
3573
3574         u8         reserved_at_20[0x10];
3575         u8         op_mod[0x10];
3576
3577         u8         reserved_at_40[0x40];
3578 };
3579
3580 struct mlx5_ifc_query_l2_table_entry_out_bits {
3581         u8         status[0x8];
3582         u8         reserved_at_8[0x18];
3583
3584         u8         syndrome[0x20];
3585
3586         u8         reserved_at_40[0xa0];
3587
3588         u8         reserved_at_e0[0x13];
3589         u8         vlan_valid[0x1];
3590         u8         vlan[0xc];
3591
3592         struct mlx5_ifc_mac_address_layout_bits mac_address;
3593
3594         u8         reserved_at_140[0xc0];
3595 };
3596
3597 struct mlx5_ifc_query_l2_table_entry_in_bits {
3598         u8         opcode[0x10];
3599         u8         reserved_at_10[0x10];
3600
3601         u8         reserved_at_20[0x10];
3602         u8         op_mod[0x10];
3603
3604         u8         reserved_at_40[0x60];
3605
3606         u8         reserved_at_a0[0x8];
3607         u8         table_index[0x18];
3608
3609         u8         reserved_at_c0[0x140];
3610 };
3611
3612 struct mlx5_ifc_query_issi_out_bits {
3613         u8         status[0x8];
3614         u8         reserved_at_8[0x18];
3615
3616         u8         syndrome[0x20];
3617
3618         u8         reserved_at_40[0x10];
3619         u8         current_issi[0x10];
3620
3621         u8         reserved_at_60[0xa0];
3622
3623         u8         reserved_at_100[76][0x8];
3624         u8         supported_issi_dw0[0x20];
3625 };
3626
3627 struct mlx5_ifc_query_issi_in_bits {
3628         u8         opcode[0x10];
3629         u8         reserved_at_10[0x10];
3630
3631         u8         reserved_at_20[0x10];
3632         u8         op_mod[0x10];
3633
3634         u8         reserved_at_40[0x40];
3635 };
3636
3637 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3638         u8         status[0x8];
3639         u8         reserved_at_8[0x18];
3640
3641         u8         syndrome[0x20];
3642
3643         u8         reserved_at_40[0x40];
3644
3645         struct mlx5_ifc_pkey_bits pkey[0];
3646 };
3647
3648 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3649         u8         opcode[0x10];
3650         u8         reserved_at_10[0x10];
3651
3652         u8         reserved_at_20[0x10];
3653         u8         op_mod[0x10];
3654
3655         u8         other_vport[0x1];
3656         u8         reserved_at_41[0xb];
3657         u8         port_num[0x4];
3658         u8         vport_number[0x10];
3659
3660         u8         reserved_at_60[0x10];
3661         u8         pkey_index[0x10];
3662 };
3663
3664 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3665         u8         status[0x8];
3666         u8         reserved_at_8[0x18];
3667
3668         u8         syndrome[0x20];
3669
3670         u8         reserved_at_40[0x20];
3671
3672         u8         gids_num[0x10];
3673         u8         reserved_at_70[0x10];
3674
3675         struct mlx5_ifc_array128_auto_bits gid[0];
3676 };
3677
3678 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3679         u8         opcode[0x10];
3680         u8         reserved_at_10[0x10];
3681
3682         u8         reserved_at_20[0x10];
3683         u8         op_mod[0x10];
3684
3685         u8         other_vport[0x1];
3686         u8         reserved_at_41[0xb];
3687         u8         port_num[0x4];
3688         u8         vport_number[0x10];
3689
3690         u8         reserved_at_60[0x10];
3691         u8         gid_index[0x10];
3692 };
3693
3694 struct mlx5_ifc_query_hca_vport_context_out_bits {
3695         u8         status[0x8];
3696         u8         reserved_at_8[0x18];
3697
3698         u8         syndrome[0x20];
3699
3700         u8         reserved_at_40[0x40];
3701
3702         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3703 };
3704
3705 struct mlx5_ifc_query_hca_vport_context_in_bits {
3706         u8         opcode[0x10];
3707         u8         reserved_at_10[0x10];
3708
3709         u8         reserved_at_20[0x10];
3710         u8         op_mod[0x10];
3711
3712         u8         other_vport[0x1];
3713         u8         reserved_at_41[0xb];
3714         u8         port_num[0x4];
3715         u8         vport_number[0x10];
3716
3717         u8         reserved_at_60[0x20];
3718 };
3719
3720 struct mlx5_ifc_query_hca_cap_out_bits {
3721         u8         status[0x8];
3722         u8         reserved_at_8[0x18];
3723
3724         u8         syndrome[0x20];
3725
3726         u8         reserved_at_40[0x40];
3727
3728         union mlx5_ifc_hca_cap_union_bits capability;
3729 };
3730
3731 struct mlx5_ifc_query_hca_cap_in_bits {
3732         u8         opcode[0x10];
3733         u8         reserved_at_10[0x10];
3734
3735         u8         reserved_at_20[0x10];
3736         u8         op_mod[0x10];
3737
3738         u8         reserved_at_40[0x40];
3739 };
3740
3741 struct mlx5_ifc_query_flow_table_out_bits {
3742         u8         status[0x8];
3743         u8         reserved_at_8[0x18];
3744
3745         u8         syndrome[0x20];
3746
3747         u8         reserved_at_40[0x80];
3748
3749         u8         reserved_at_c0[0x8];
3750         u8         level[0x8];
3751         u8         reserved_at_d0[0x8];
3752         u8         log_size[0x8];
3753
3754         u8         reserved_at_e0[0x120];
3755 };
3756
3757 struct mlx5_ifc_query_flow_table_in_bits {
3758         u8         opcode[0x10];
3759         u8         reserved_at_10[0x10];
3760
3761         u8         reserved_at_20[0x10];
3762         u8         op_mod[0x10];
3763
3764         u8         reserved_at_40[0x40];
3765
3766         u8         table_type[0x8];
3767         u8         reserved_at_88[0x18];
3768
3769         u8         reserved_at_a0[0x8];
3770         u8         table_id[0x18];
3771
3772         u8         reserved_at_c0[0x140];
3773 };
3774
3775 struct mlx5_ifc_query_fte_out_bits {
3776         u8         status[0x8];
3777         u8         reserved_at_8[0x18];
3778
3779         u8         syndrome[0x20];
3780
3781         u8         reserved_at_40[0x1c0];
3782
3783         struct mlx5_ifc_flow_context_bits flow_context;
3784 };
3785
3786 struct mlx5_ifc_query_fte_in_bits {
3787         u8         opcode[0x10];
3788         u8         reserved_at_10[0x10];
3789
3790         u8         reserved_at_20[0x10];
3791         u8         op_mod[0x10];
3792
3793         u8         reserved_at_40[0x40];
3794
3795         u8         table_type[0x8];
3796         u8         reserved_at_88[0x18];
3797
3798         u8         reserved_at_a0[0x8];
3799         u8         table_id[0x18];
3800
3801         u8         reserved_at_c0[0x40];
3802
3803         u8         flow_index[0x20];
3804
3805         u8         reserved_at_120[0xe0];
3806 };
3807
3808 enum {
3809         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
3810         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
3811         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
3812 };
3813
3814 struct mlx5_ifc_query_flow_group_out_bits {
3815         u8         status[0x8];
3816         u8         reserved_at_8[0x18];
3817
3818         u8         syndrome[0x20];
3819
3820         u8         reserved_at_40[0xa0];
3821
3822         u8         start_flow_index[0x20];
3823
3824         u8         reserved_at_100[0x20];
3825
3826         u8         end_flow_index[0x20];
3827
3828         u8         reserved_at_140[0xa0];
3829
3830         u8         reserved_at_1e0[0x18];
3831         u8         match_criteria_enable[0x8];
3832
3833         struct mlx5_ifc_fte_match_param_bits match_criteria;
3834
3835         u8         reserved_at_1200[0xe00];
3836 };
3837
3838 struct mlx5_ifc_query_flow_group_in_bits {
3839         u8         opcode[0x10];
3840         u8         reserved_at_10[0x10];
3841
3842         u8         reserved_at_20[0x10];
3843         u8         op_mod[0x10];
3844
3845         u8         reserved_at_40[0x40];
3846
3847         u8         table_type[0x8];
3848         u8         reserved_at_88[0x18];
3849
3850         u8         reserved_at_a0[0x8];
3851         u8         table_id[0x18];
3852
3853         u8         group_id[0x20];
3854
3855         u8         reserved_at_e0[0x120];
3856 };
3857
3858 struct mlx5_ifc_query_esw_vport_context_out_bits {
3859         u8         status[0x8];
3860         u8         reserved_at_8[0x18];
3861
3862         u8         syndrome[0x20];
3863
3864         u8         reserved_at_40[0x40];
3865
3866         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3867 };
3868
3869 struct mlx5_ifc_query_esw_vport_context_in_bits {
3870         u8         opcode[0x10];
3871         u8         reserved_at_10[0x10];
3872
3873         u8         reserved_at_20[0x10];
3874         u8         op_mod[0x10];
3875
3876         u8         other_vport[0x1];
3877         u8         reserved_at_41[0xf];
3878         u8         vport_number[0x10];
3879
3880         u8         reserved_at_60[0x20];
3881 };
3882
3883 struct mlx5_ifc_modify_esw_vport_context_out_bits {
3884         u8         status[0x8];
3885         u8         reserved_at_8[0x18];
3886
3887         u8         syndrome[0x20];
3888
3889         u8         reserved_at_40[0x40];
3890 };
3891
3892 struct mlx5_ifc_esw_vport_context_fields_select_bits {
3893         u8         reserved_at_0[0x1c];
3894         u8         vport_cvlan_insert[0x1];
3895         u8         vport_svlan_insert[0x1];
3896         u8         vport_cvlan_strip[0x1];
3897         u8         vport_svlan_strip[0x1];
3898 };
3899
3900 struct mlx5_ifc_modify_esw_vport_context_in_bits {
3901         u8         opcode[0x10];
3902         u8         reserved_at_10[0x10];
3903
3904         u8         reserved_at_20[0x10];
3905         u8         op_mod[0x10];
3906
3907         u8         other_vport[0x1];
3908         u8         reserved_at_41[0xf];
3909         u8         vport_number[0x10];
3910
3911         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
3912
3913         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3914 };
3915
3916 struct mlx5_ifc_query_eq_out_bits {
3917         u8         status[0x8];
3918         u8         reserved_at_8[0x18];
3919
3920         u8         syndrome[0x20];
3921
3922         u8         reserved_at_40[0x40];
3923
3924         struct mlx5_ifc_eqc_bits eq_context_entry;
3925
3926         u8         reserved_at_280[0x40];
3927
3928         u8         event_bitmask[0x40];
3929
3930         u8         reserved_at_300[0x580];
3931
3932         u8         pas[0][0x40];
3933 };
3934
3935 struct mlx5_ifc_query_eq_in_bits {
3936         u8         opcode[0x10];
3937         u8         reserved_at_10[0x10];
3938
3939         u8         reserved_at_20[0x10];
3940         u8         op_mod[0x10];
3941
3942         u8         reserved_at_40[0x18];
3943         u8         eq_number[0x8];
3944
3945         u8         reserved_at_60[0x20];
3946 };
3947
3948 struct mlx5_ifc_query_dct_out_bits {
3949         u8         status[0x8];
3950         u8         reserved_at_8[0x18];
3951
3952         u8         syndrome[0x20];
3953
3954         u8         reserved_at_40[0x40];
3955
3956         struct mlx5_ifc_dctc_bits dct_context_entry;
3957
3958         u8         reserved_at_280[0x180];
3959 };
3960
3961 struct mlx5_ifc_query_dct_in_bits {
3962         u8         opcode[0x10];
3963         u8         reserved_at_10[0x10];
3964
3965         u8         reserved_at_20[0x10];
3966         u8         op_mod[0x10];
3967
3968         u8         reserved_at_40[0x8];
3969         u8         dctn[0x18];
3970
3971         u8         reserved_at_60[0x20];
3972 };
3973
3974 struct mlx5_ifc_query_cq_out_bits {
3975         u8         status[0x8];
3976         u8         reserved_at_8[0x18];
3977
3978         u8         syndrome[0x20];
3979
3980         u8         reserved_at_40[0x40];
3981
3982         struct mlx5_ifc_cqc_bits cq_context;
3983
3984         u8         reserved_at_280[0x600];
3985
3986         u8         pas[0][0x40];
3987 };
3988
3989 struct mlx5_ifc_query_cq_in_bits {
3990         u8         opcode[0x10];
3991         u8         reserved_at_10[0x10];
3992
3993         u8         reserved_at_20[0x10];
3994         u8         op_mod[0x10];
3995
3996         u8         reserved_at_40[0x8];
3997         u8         cqn[0x18];
3998
3999         u8         reserved_at_60[0x20];
4000 };
4001
4002 struct mlx5_ifc_query_cong_status_out_bits {
4003         u8         status[0x8];
4004         u8         reserved_at_8[0x18];
4005
4006         u8         syndrome[0x20];
4007
4008         u8         reserved_at_40[0x20];
4009
4010         u8         enable[0x1];
4011         u8         tag_enable[0x1];
4012         u8         reserved_at_62[0x1e];
4013 };
4014
4015 struct mlx5_ifc_query_cong_status_in_bits {
4016         u8         opcode[0x10];
4017         u8         reserved_at_10[0x10];
4018
4019         u8         reserved_at_20[0x10];
4020         u8         op_mod[0x10];
4021
4022         u8         reserved_at_40[0x18];
4023         u8         priority[0x4];
4024         u8         cong_protocol[0x4];
4025
4026         u8         reserved_at_60[0x20];
4027 };
4028
4029 struct mlx5_ifc_query_cong_statistics_out_bits {
4030         u8         status[0x8];
4031         u8         reserved_at_8[0x18];
4032
4033         u8         syndrome[0x20];
4034
4035         u8         reserved_at_40[0x40];
4036
4037         u8         cur_flows[0x20];
4038
4039         u8         sum_flows[0x20];
4040
4041         u8         cnp_ignored_high[0x20];
4042
4043         u8         cnp_ignored_low[0x20];
4044
4045         u8         cnp_handled_high[0x20];
4046
4047         u8         cnp_handled_low[0x20];
4048
4049         u8         reserved_at_140[0x100];
4050
4051         u8         time_stamp_high[0x20];
4052
4053         u8         time_stamp_low[0x20];
4054
4055         u8         accumulators_period[0x20];
4056
4057         u8         ecn_marked_roce_packets_high[0x20];
4058
4059         u8         ecn_marked_roce_packets_low[0x20];
4060
4061         u8         cnps_sent_high[0x20];
4062
4063         u8         cnps_sent_low[0x20];
4064
4065         u8         reserved_at_320[0x560];
4066 };
4067
4068 struct mlx5_ifc_query_cong_statistics_in_bits {
4069         u8         opcode[0x10];
4070         u8         reserved_at_10[0x10];
4071
4072         u8         reserved_at_20[0x10];
4073         u8         op_mod[0x10];
4074
4075         u8         clear[0x1];
4076         u8         reserved_at_41[0x1f];
4077
4078         u8         reserved_at_60[0x20];
4079 };
4080
4081 struct mlx5_ifc_query_cong_params_out_bits {
4082         u8         status[0x8];
4083         u8         reserved_at_8[0x18];
4084
4085         u8         syndrome[0x20];
4086
4087         u8         reserved_at_40[0x40];
4088
4089         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4090 };
4091
4092 struct mlx5_ifc_query_cong_params_in_bits {
4093         u8         opcode[0x10];
4094         u8         reserved_at_10[0x10];
4095
4096         u8         reserved_at_20[0x10];
4097         u8         op_mod[0x10];
4098
4099         u8         reserved_at_40[0x1c];
4100         u8         cong_protocol[0x4];
4101
4102         u8         reserved_at_60[0x20];
4103 };
4104
4105 struct mlx5_ifc_query_adapter_out_bits {
4106         u8         status[0x8];
4107         u8         reserved_at_8[0x18];
4108
4109         u8         syndrome[0x20];
4110
4111         u8         reserved_at_40[0x40];
4112
4113         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4114 };
4115
4116 struct mlx5_ifc_query_adapter_in_bits {
4117         u8         opcode[0x10];
4118         u8         reserved_at_10[0x10];
4119
4120         u8         reserved_at_20[0x10];
4121         u8         op_mod[0x10];
4122
4123         u8         reserved_at_40[0x40];
4124 };
4125
4126 struct mlx5_ifc_qp_2rst_out_bits {
4127         u8         status[0x8];
4128         u8         reserved_at_8[0x18];
4129
4130         u8         syndrome[0x20];
4131
4132         u8         reserved_at_40[0x40];
4133 };
4134
4135 struct mlx5_ifc_qp_2rst_in_bits {
4136         u8         opcode[0x10];
4137         u8         reserved_at_10[0x10];
4138
4139         u8         reserved_at_20[0x10];
4140         u8         op_mod[0x10];
4141
4142         u8         reserved_at_40[0x8];
4143         u8         qpn[0x18];
4144
4145         u8         reserved_at_60[0x20];
4146 };
4147
4148 struct mlx5_ifc_qp_2err_out_bits {
4149         u8         status[0x8];
4150         u8         reserved_at_8[0x18];
4151
4152         u8         syndrome[0x20];
4153
4154         u8         reserved_at_40[0x40];
4155 };
4156
4157 struct mlx5_ifc_qp_2err_in_bits {
4158         u8         opcode[0x10];
4159         u8         reserved_at_10[0x10];
4160
4161         u8         reserved_at_20[0x10];
4162         u8         op_mod[0x10];
4163
4164         u8         reserved_at_40[0x8];
4165         u8         qpn[0x18];
4166
4167         u8         reserved_at_60[0x20];
4168 };
4169
4170 struct mlx5_ifc_page_fault_resume_out_bits {
4171         u8         status[0x8];
4172         u8         reserved_at_8[0x18];
4173
4174         u8         syndrome[0x20];
4175
4176         u8         reserved_at_40[0x40];
4177 };
4178
4179 struct mlx5_ifc_page_fault_resume_in_bits {
4180         u8         opcode[0x10];
4181         u8         reserved_at_10[0x10];
4182
4183         u8         reserved_at_20[0x10];
4184         u8         op_mod[0x10];
4185
4186         u8         error[0x1];
4187         u8         reserved_at_41[0x4];
4188         u8         rdma[0x1];
4189         u8         read_write[0x1];
4190         u8         req_res[0x1];
4191         u8         qpn[0x18];
4192
4193         u8         reserved_at_60[0x20];
4194 };
4195
4196 struct mlx5_ifc_nop_out_bits {
4197         u8         status[0x8];
4198         u8         reserved_at_8[0x18];
4199
4200         u8         syndrome[0x20];
4201
4202         u8         reserved_at_40[0x40];
4203 };
4204
4205 struct mlx5_ifc_nop_in_bits {
4206         u8         opcode[0x10];
4207         u8         reserved_at_10[0x10];
4208
4209         u8         reserved_at_20[0x10];
4210         u8         op_mod[0x10];
4211
4212         u8         reserved_at_40[0x40];
4213 };
4214
4215 struct mlx5_ifc_modify_vport_state_out_bits {
4216         u8         status[0x8];
4217         u8         reserved_at_8[0x18];
4218
4219         u8         syndrome[0x20];
4220
4221         u8         reserved_at_40[0x40];
4222 };
4223
4224 struct mlx5_ifc_modify_vport_state_in_bits {
4225         u8         opcode[0x10];
4226         u8         reserved_at_10[0x10];
4227
4228         u8         reserved_at_20[0x10];
4229         u8         op_mod[0x10];
4230
4231         u8         other_vport[0x1];
4232         u8         reserved_at_41[0xf];
4233         u8         vport_number[0x10];
4234
4235         u8         reserved_at_60[0x18];
4236         u8         admin_state[0x4];
4237         u8         reserved_at_7c[0x4];
4238 };
4239
4240 struct mlx5_ifc_modify_tis_out_bits {
4241         u8         status[0x8];
4242         u8         reserved_at_8[0x18];
4243
4244         u8         syndrome[0x20];
4245
4246         u8         reserved_at_40[0x40];
4247 };
4248
4249 struct mlx5_ifc_modify_tis_bitmask_bits {
4250         u8         reserved_at_0[0x20];
4251
4252         u8         reserved_at_20[0x1f];
4253         u8         prio[0x1];
4254 };
4255
4256 struct mlx5_ifc_modify_tis_in_bits {
4257         u8         opcode[0x10];
4258         u8         reserved_at_10[0x10];
4259
4260         u8         reserved_at_20[0x10];
4261         u8         op_mod[0x10];
4262
4263         u8         reserved_at_40[0x8];
4264         u8         tisn[0x18];
4265
4266         u8         reserved_at_60[0x20];
4267
4268         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4269
4270         u8         reserved_at_c0[0x40];
4271
4272         struct mlx5_ifc_tisc_bits ctx;
4273 };
4274
4275 struct mlx5_ifc_modify_tir_bitmask_bits {
4276         u8         reserved_at_0[0x20];
4277
4278         u8         reserved_at_20[0x1b];
4279         u8         self_lb_en[0x1];
4280         u8         reserved_at_3c[0x3];
4281         u8         lro[0x1];
4282 };
4283
4284 struct mlx5_ifc_modify_tir_out_bits {
4285         u8         status[0x8];
4286         u8         reserved_at_8[0x18];
4287
4288         u8         syndrome[0x20];
4289
4290         u8         reserved_at_40[0x40];
4291 };
4292
4293 struct mlx5_ifc_modify_tir_in_bits {
4294         u8         opcode[0x10];
4295         u8         reserved_at_10[0x10];
4296
4297         u8         reserved_at_20[0x10];
4298         u8         op_mod[0x10];
4299
4300         u8         reserved_at_40[0x8];
4301         u8         tirn[0x18];
4302
4303         u8         reserved_at_60[0x20];
4304
4305         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4306
4307         u8         reserved_at_c0[0x40];
4308
4309         struct mlx5_ifc_tirc_bits ctx;
4310 };
4311
4312 struct mlx5_ifc_modify_sq_out_bits {
4313         u8         status[0x8];
4314         u8         reserved_at_8[0x18];
4315
4316         u8         syndrome[0x20];
4317
4318         u8         reserved_at_40[0x40];
4319 };
4320
4321 struct mlx5_ifc_modify_sq_in_bits {
4322         u8         opcode[0x10];
4323         u8         reserved_at_10[0x10];
4324
4325         u8         reserved_at_20[0x10];
4326         u8         op_mod[0x10];
4327
4328         u8         sq_state[0x4];
4329         u8         reserved_at_44[0x4];
4330         u8         sqn[0x18];
4331
4332         u8         reserved_at_60[0x20];
4333
4334         u8         modify_bitmask[0x40];
4335
4336         u8         reserved_at_c0[0x40];
4337
4338         struct mlx5_ifc_sqc_bits ctx;
4339 };
4340
4341 struct mlx5_ifc_modify_rqt_out_bits {
4342         u8         status[0x8];
4343         u8         reserved_at_8[0x18];
4344
4345         u8         syndrome[0x20];
4346
4347         u8         reserved_at_40[0x40];
4348 };
4349
4350 struct mlx5_ifc_rqt_bitmask_bits {
4351         u8         reserved_at_0[0x20];
4352
4353         u8         reserved_at_20[0x1f];
4354         u8         rqn_list[0x1];
4355 };
4356
4357 struct mlx5_ifc_modify_rqt_in_bits {
4358         u8         opcode[0x10];
4359         u8         reserved_at_10[0x10];
4360
4361         u8         reserved_at_20[0x10];
4362         u8         op_mod[0x10];
4363
4364         u8         reserved_at_40[0x8];
4365         u8         rqtn[0x18];
4366
4367         u8         reserved_at_60[0x20];
4368
4369         struct mlx5_ifc_rqt_bitmask_bits bitmask;
4370
4371         u8         reserved_at_c0[0x40];
4372
4373         struct mlx5_ifc_rqtc_bits ctx;
4374 };
4375
4376 struct mlx5_ifc_modify_rq_out_bits {
4377         u8         status[0x8];
4378         u8         reserved_at_8[0x18];
4379
4380         u8         syndrome[0x20];
4381
4382         u8         reserved_at_40[0x40];
4383 };
4384
4385 struct mlx5_ifc_modify_rq_in_bits {
4386         u8         opcode[0x10];
4387         u8         reserved_at_10[0x10];
4388
4389         u8         reserved_at_20[0x10];
4390         u8         op_mod[0x10];
4391
4392         u8         rq_state[0x4];
4393         u8         reserved_at_44[0x4];
4394         u8         rqn[0x18];
4395
4396         u8         reserved_at_60[0x20];
4397
4398         u8         modify_bitmask[0x40];
4399
4400         u8         reserved_at_c0[0x40];
4401
4402         struct mlx5_ifc_rqc_bits ctx;
4403 };
4404
4405 struct mlx5_ifc_modify_rmp_out_bits {
4406         u8         status[0x8];
4407         u8         reserved_at_8[0x18];
4408
4409         u8         syndrome[0x20];
4410
4411         u8         reserved_at_40[0x40];
4412 };
4413
4414 struct mlx5_ifc_rmp_bitmask_bits {
4415         u8         reserved_at_0[0x20];
4416
4417         u8         reserved_at_20[0x1f];
4418         u8         lwm[0x1];
4419 };
4420
4421 struct mlx5_ifc_modify_rmp_in_bits {
4422         u8         opcode[0x10];
4423         u8         reserved_at_10[0x10];
4424
4425         u8         reserved_at_20[0x10];
4426         u8         op_mod[0x10];
4427
4428         u8         rmp_state[0x4];
4429         u8         reserved_at_44[0x4];
4430         u8         rmpn[0x18];
4431
4432         u8         reserved_at_60[0x20];
4433
4434         struct mlx5_ifc_rmp_bitmask_bits bitmask;
4435
4436         u8         reserved_at_c0[0x40];
4437
4438         struct mlx5_ifc_rmpc_bits ctx;
4439 };
4440
4441 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4442         u8         status[0x8];
4443         u8         reserved_at_8[0x18];
4444
4445         u8         syndrome[0x20];
4446
4447         u8         reserved_at_40[0x40];
4448 };
4449
4450 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4451         u8         reserved_at_0[0x19];
4452         u8         mtu[0x1];
4453         u8         change_event[0x1];
4454         u8         promisc[0x1];
4455         u8         permanent_address[0x1];
4456         u8         addresses_list[0x1];
4457         u8         roce_en[0x1];
4458         u8         reserved_at_1f[0x1];
4459 };
4460
4461 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4462         u8         opcode[0x10];
4463         u8         reserved_at_10[0x10];
4464
4465         u8         reserved_at_20[0x10];
4466         u8         op_mod[0x10];
4467
4468         u8         other_vport[0x1];
4469         u8         reserved_at_41[0xf];
4470         u8         vport_number[0x10];
4471
4472         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4473
4474         u8         reserved_at_80[0x780];
4475
4476         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4477 };
4478
4479 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4480         u8         status[0x8];
4481         u8         reserved_at_8[0x18];
4482
4483         u8         syndrome[0x20];
4484
4485         u8         reserved_at_40[0x40];
4486 };
4487
4488 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4489         u8         opcode[0x10];
4490         u8         reserved_at_10[0x10];
4491
4492         u8         reserved_at_20[0x10];
4493         u8         op_mod[0x10];
4494
4495         u8         other_vport[0x1];
4496         u8         reserved_at_41[0xb];
4497         u8         port_num[0x4];
4498         u8         vport_number[0x10];
4499
4500         u8         reserved_at_60[0x20];
4501
4502         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4503 };
4504
4505 struct mlx5_ifc_modify_cq_out_bits {
4506         u8         status[0x8];
4507         u8         reserved_at_8[0x18];
4508
4509         u8         syndrome[0x20];
4510
4511         u8         reserved_at_40[0x40];
4512 };
4513
4514 enum {
4515         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
4516         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
4517 };
4518
4519 struct mlx5_ifc_modify_cq_in_bits {
4520         u8         opcode[0x10];
4521         u8         reserved_at_10[0x10];
4522
4523         u8         reserved_at_20[0x10];
4524         u8         op_mod[0x10];
4525
4526         u8         reserved_at_40[0x8];
4527         u8         cqn[0x18];
4528
4529         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4530
4531         struct mlx5_ifc_cqc_bits cq_context;
4532
4533         u8         reserved_at_280[0x600];
4534
4535         u8         pas[0][0x40];
4536 };
4537
4538 struct mlx5_ifc_modify_cong_status_out_bits {
4539         u8         status[0x8];
4540         u8         reserved_at_8[0x18];
4541
4542         u8         syndrome[0x20];
4543
4544         u8         reserved_at_40[0x40];
4545 };
4546
4547 struct mlx5_ifc_modify_cong_status_in_bits {
4548         u8         opcode[0x10];
4549         u8         reserved_at_10[0x10];
4550
4551         u8         reserved_at_20[0x10];
4552         u8         op_mod[0x10];
4553
4554         u8         reserved_at_40[0x18];
4555         u8         priority[0x4];
4556         u8         cong_protocol[0x4];
4557
4558         u8         enable[0x1];
4559         u8         tag_enable[0x1];
4560         u8         reserved_at_62[0x1e];
4561 };
4562
4563 struct mlx5_ifc_modify_cong_params_out_bits {
4564         u8         status[0x8];
4565         u8         reserved_at_8[0x18];
4566
4567         u8         syndrome[0x20];
4568
4569         u8         reserved_at_40[0x40];
4570 };
4571
4572 struct mlx5_ifc_modify_cong_params_in_bits {
4573         u8         opcode[0x10];
4574         u8         reserved_at_10[0x10];
4575
4576         u8         reserved_at_20[0x10];
4577         u8         op_mod[0x10];
4578
4579         u8         reserved_at_40[0x1c];
4580         u8         cong_protocol[0x4];
4581
4582         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4583
4584         u8         reserved_at_80[0x80];
4585
4586         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4587 };
4588
4589 struct mlx5_ifc_manage_pages_out_bits {
4590         u8         status[0x8];
4591         u8         reserved_at_8[0x18];
4592
4593         u8         syndrome[0x20];
4594
4595         u8         output_num_entries[0x20];
4596
4597         u8         reserved_at_60[0x20];
4598
4599         u8         pas[0][0x40];
4600 };
4601
4602 enum {
4603         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
4604         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
4605         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
4606 };
4607
4608 struct mlx5_ifc_manage_pages_in_bits {
4609         u8         opcode[0x10];
4610         u8         reserved_at_10[0x10];
4611
4612         u8         reserved_at_20[0x10];
4613         u8         op_mod[0x10];
4614
4615         u8         reserved_at_40[0x10];
4616         u8         function_id[0x10];
4617
4618         u8         input_num_entries[0x20];
4619
4620         u8         pas[0][0x40];
4621 };
4622
4623 struct mlx5_ifc_mad_ifc_out_bits {
4624         u8         status[0x8];
4625         u8         reserved_at_8[0x18];
4626
4627         u8         syndrome[0x20];
4628
4629         u8         reserved_at_40[0x40];
4630
4631         u8         response_mad_packet[256][0x8];
4632 };
4633
4634 struct mlx5_ifc_mad_ifc_in_bits {
4635         u8         opcode[0x10];
4636         u8         reserved_at_10[0x10];
4637
4638         u8         reserved_at_20[0x10];
4639         u8         op_mod[0x10];
4640
4641         u8         remote_lid[0x10];
4642         u8         reserved_at_50[0x8];
4643         u8         port[0x8];
4644
4645         u8         reserved_at_60[0x20];
4646
4647         u8         mad[256][0x8];
4648 };
4649
4650 struct mlx5_ifc_init_hca_out_bits {
4651         u8         status[0x8];
4652         u8         reserved_at_8[0x18];
4653
4654         u8         syndrome[0x20];
4655
4656         u8         reserved_at_40[0x40];
4657 };
4658
4659 struct mlx5_ifc_init_hca_in_bits {
4660         u8         opcode[0x10];
4661         u8         reserved_at_10[0x10];
4662
4663         u8         reserved_at_20[0x10];
4664         u8         op_mod[0x10];
4665
4666         u8         reserved_at_40[0x40];
4667 };
4668
4669 struct mlx5_ifc_init2rtr_qp_out_bits {
4670         u8         status[0x8];
4671         u8         reserved_at_8[0x18];
4672
4673         u8         syndrome[0x20];
4674
4675         u8         reserved_at_40[0x40];
4676 };
4677
4678 struct mlx5_ifc_init2rtr_qp_in_bits {
4679         u8         opcode[0x10];
4680         u8         reserved_at_10[0x10];
4681
4682         u8         reserved_at_20[0x10];
4683         u8         op_mod[0x10];
4684
4685         u8         reserved_at_40[0x8];
4686         u8         qpn[0x18];
4687
4688         u8         reserved_at_60[0x20];
4689
4690         u8         opt_param_mask[0x20];
4691
4692         u8         reserved_at_a0[0x20];
4693
4694         struct mlx5_ifc_qpc_bits qpc;
4695
4696         u8         reserved_at_800[0x80];
4697 };
4698
4699 struct mlx5_ifc_init2init_qp_out_bits {
4700         u8         status[0x8];
4701         u8         reserved_at_8[0x18];
4702
4703         u8         syndrome[0x20];
4704
4705         u8         reserved_at_40[0x40];
4706 };
4707
4708 struct mlx5_ifc_init2init_qp_in_bits {
4709         u8         opcode[0x10];
4710         u8         reserved_at_10[0x10];
4711
4712         u8         reserved_at_20[0x10];
4713         u8         op_mod[0x10];
4714
4715         u8         reserved_at_40[0x8];
4716         u8         qpn[0x18];
4717
4718         u8         reserved_at_60[0x20];
4719
4720         u8         opt_param_mask[0x20];
4721
4722         u8         reserved_at_a0[0x20];
4723
4724         struct mlx5_ifc_qpc_bits qpc;
4725
4726         u8         reserved_at_800[0x80];
4727 };
4728
4729 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4730         u8         status[0x8];
4731         u8         reserved_at_8[0x18];
4732
4733         u8         syndrome[0x20];
4734
4735         u8         reserved_at_40[0x40];
4736
4737         u8         packet_headers_log[128][0x8];
4738
4739         u8         packet_syndrome[64][0x8];
4740 };
4741
4742 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4743         u8         opcode[0x10];
4744         u8         reserved_at_10[0x10];
4745
4746         u8         reserved_at_20[0x10];
4747         u8         op_mod[0x10];
4748
4749         u8         reserved_at_40[0x40];
4750 };
4751
4752 struct mlx5_ifc_gen_eqe_in_bits {
4753         u8         opcode[0x10];
4754         u8         reserved_at_10[0x10];
4755
4756         u8         reserved_at_20[0x10];
4757         u8         op_mod[0x10];
4758
4759         u8         reserved_at_40[0x18];
4760         u8         eq_number[0x8];
4761
4762         u8         reserved_at_60[0x20];
4763
4764         u8         eqe[64][0x8];
4765 };
4766
4767 struct mlx5_ifc_gen_eq_out_bits {
4768         u8         status[0x8];
4769         u8         reserved_at_8[0x18];
4770
4771         u8         syndrome[0x20];
4772
4773         u8         reserved_at_40[0x40];
4774 };
4775
4776 struct mlx5_ifc_enable_hca_out_bits {
4777         u8         status[0x8];
4778         u8         reserved_at_8[0x18];
4779
4780         u8         syndrome[0x20];
4781
4782         u8         reserved_at_40[0x20];
4783 };
4784
4785 struct mlx5_ifc_enable_hca_in_bits {
4786         u8         opcode[0x10];
4787         u8         reserved_at_10[0x10];
4788
4789         u8         reserved_at_20[0x10];
4790         u8         op_mod[0x10];
4791
4792         u8         reserved_at_40[0x10];
4793         u8         function_id[0x10];
4794
4795         u8         reserved_at_60[0x20];
4796 };
4797
4798 struct mlx5_ifc_drain_dct_out_bits {
4799         u8         status[0x8];
4800         u8         reserved_at_8[0x18];
4801
4802         u8         syndrome[0x20];
4803
4804         u8         reserved_at_40[0x40];
4805 };
4806
4807 struct mlx5_ifc_drain_dct_in_bits {
4808         u8         opcode[0x10];
4809         u8         reserved_at_10[0x10];
4810
4811         u8         reserved_at_20[0x10];
4812         u8         op_mod[0x10];
4813
4814         u8         reserved_at_40[0x8];
4815         u8         dctn[0x18];
4816
4817         u8         reserved_at_60[0x20];
4818 };
4819
4820 struct mlx5_ifc_disable_hca_out_bits {
4821         u8         status[0x8];
4822         u8         reserved_at_8[0x18];
4823
4824         u8         syndrome[0x20];
4825
4826         u8         reserved_at_40[0x20];
4827 };
4828
4829 struct mlx5_ifc_disable_hca_in_bits {
4830         u8         opcode[0x10];
4831         u8         reserved_at_10[0x10];
4832
4833         u8         reserved_at_20[0x10];
4834         u8         op_mod[0x10];
4835
4836         u8         reserved_at_40[0x10];
4837         u8         function_id[0x10];
4838
4839         u8         reserved_at_60[0x20];
4840 };
4841
4842 struct mlx5_ifc_detach_from_mcg_out_bits {
4843         u8         status[0x8];
4844         u8         reserved_at_8[0x18];
4845
4846         u8         syndrome[0x20];
4847
4848         u8         reserved_at_40[0x40];
4849 };
4850
4851 struct mlx5_ifc_detach_from_mcg_in_bits {
4852         u8         opcode[0x10];
4853         u8         reserved_at_10[0x10];
4854
4855         u8         reserved_at_20[0x10];
4856         u8         op_mod[0x10];
4857
4858         u8         reserved_at_40[0x8];
4859         u8         qpn[0x18];
4860
4861         u8         reserved_at_60[0x20];
4862
4863         u8         multicast_gid[16][0x8];
4864 };
4865
4866 struct mlx5_ifc_destroy_xrc_srq_out_bits {
4867         u8         status[0x8];
4868         u8         reserved_at_8[0x18];
4869
4870         u8         syndrome[0x20];
4871
4872         u8         reserved_at_40[0x40];
4873 };
4874
4875 struct mlx5_ifc_destroy_xrc_srq_in_bits {
4876         u8         opcode[0x10];
4877         u8         reserved_at_10[0x10];
4878
4879         u8         reserved_at_20[0x10];
4880         u8         op_mod[0x10];
4881
4882         u8         reserved_at_40[0x8];
4883         u8         xrc_srqn[0x18];
4884
4885         u8         reserved_at_60[0x20];
4886 };
4887
4888 struct mlx5_ifc_destroy_tis_out_bits {
4889         u8         status[0x8];
4890         u8         reserved_at_8[0x18];
4891
4892         u8         syndrome[0x20];
4893
4894         u8         reserved_at_40[0x40];
4895 };
4896
4897 struct mlx5_ifc_destroy_tis_in_bits {
4898         u8         opcode[0x10];
4899         u8         reserved_at_10[0x10];
4900
4901         u8         reserved_at_20[0x10];
4902         u8         op_mod[0x10];
4903
4904         u8         reserved_at_40[0x8];
4905         u8         tisn[0x18];
4906
4907         u8         reserved_at_60[0x20];
4908 };
4909
4910 struct mlx5_ifc_destroy_tir_out_bits {
4911         u8         status[0x8];
4912         u8         reserved_at_8[0x18];
4913
4914         u8         syndrome[0x20];
4915
4916         u8         reserved_at_40[0x40];
4917 };
4918
4919 struct mlx5_ifc_destroy_tir_in_bits {
4920         u8         opcode[0x10];
4921         u8         reserved_at_10[0x10];
4922
4923         u8         reserved_at_20[0x10];
4924         u8         op_mod[0x10];
4925
4926         u8         reserved_at_40[0x8];
4927         u8         tirn[0x18];
4928
4929         u8         reserved_at_60[0x20];
4930 };
4931
4932 struct mlx5_ifc_destroy_srq_out_bits {
4933         u8         status[0x8];
4934         u8         reserved_at_8[0x18];
4935
4936         u8         syndrome[0x20];
4937
4938         u8         reserved_at_40[0x40];
4939 };
4940
4941 struct mlx5_ifc_destroy_srq_in_bits {
4942         u8         opcode[0x10];
4943         u8         reserved_at_10[0x10];
4944
4945         u8         reserved_at_20[0x10];
4946         u8         op_mod[0x10];
4947
4948         u8         reserved_at_40[0x8];
4949         u8         srqn[0x18];
4950
4951         u8         reserved_at_60[0x20];
4952 };
4953
4954 struct mlx5_ifc_destroy_sq_out_bits {
4955         u8         status[0x8];
4956         u8         reserved_at_8[0x18];
4957
4958         u8         syndrome[0x20];
4959
4960         u8         reserved_at_40[0x40];
4961 };
4962
4963 struct mlx5_ifc_destroy_sq_in_bits {
4964         u8         opcode[0x10];
4965         u8         reserved_at_10[0x10];
4966
4967         u8         reserved_at_20[0x10];
4968         u8         op_mod[0x10];
4969
4970         u8         reserved_at_40[0x8];
4971         u8         sqn[0x18];
4972
4973         u8         reserved_at_60[0x20];
4974 };
4975
4976 struct mlx5_ifc_destroy_rqt_out_bits {
4977         u8         status[0x8];
4978         u8         reserved_at_8[0x18];
4979
4980         u8         syndrome[0x20];
4981
4982         u8         reserved_at_40[0x40];
4983 };
4984
4985 struct mlx5_ifc_destroy_rqt_in_bits {
4986         u8         opcode[0x10];
4987         u8         reserved_at_10[0x10];
4988
4989         u8         reserved_at_20[0x10];
4990         u8         op_mod[0x10];
4991
4992         u8         reserved_at_40[0x8];
4993         u8         rqtn[0x18];
4994
4995         u8         reserved_at_60[0x20];
4996 };
4997
4998 struct mlx5_ifc_destroy_rq_out_bits {
4999         u8         status[0x8];
5000         u8         reserved_at_8[0x18];
5001
5002         u8         syndrome[0x20];
5003
5004         u8         reserved_at_40[0x40];
5005 };
5006
5007 struct mlx5_ifc_destroy_rq_in_bits {
5008         u8         opcode[0x10];
5009         u8         reserved_at_10[0x10];
5010
5011         u8         reserved_at_20[0x10];
5012         u8         op_mod[0x10];
5013
5014         u8         reserved_at_40[0x8];
5015         u8         rqn[0x18];
5016
5017         u8         reserved_at_60[0x20];
5018 };
5019
5020 struct mlx5_ifc_destroy_rmp_out_bits {
5021         u8         status[0x8];
5022         u8         reserved_at_8[0x18];
5023
5024         u8         syndrome[0x20];
5025
5026         u8         reserved_at_40[0x40];
5027 };
5028
5029 struct mlx5_ifc_destroy_rmp_in_bits {
5030         u8         opcode[0x10];
5031         u8         reserved_at_10[0x10];
5032
5033         u8         reserved_at_20[0x10];
5034         u8         op_mod[0x10];
5035
5036         u8         reserved_at_40[0x8];
5037         u8         rmpn[0x18];
5038
5039         u8         reserved_at_60[0x20];
5040 };
5041
5042 struct mlx5_ifc_destroy_qp_out_bits {
5043         u8         status[0x8];
5044         u8         reserved_at_8[0x18];
5045
5046         u8         syndrome[0x20];
5047
5048         u8         reserved_at_40[0x40];
5049 };
5050
5051 struct mlx5_ifc_destroy_qp_in_bits {
5052         u8         opcode[0x10];
5053         u8         reserved_at_10[0x10];
5054
5055         u8         reserved_at_20[0x10];
5056         u8         op_mod[0x10];
5057
5058         u8         reserved_at_40[0x8];
5059         u8         qpn[0x18];
5060
5061         u8         reserved_at_60[0x20];
5062 };
5063
5064 struct mlx5_ifc_destroy_psv_out_bits {
5065         u8         status[0x8];
5066         u8         reserved_at_8[0x18];
5067
5068         u8         syndrome[0x20];
5069
5070         u8         reserved_at_40[0x40];
5071 };
5072
5073 struct mlx5_ifc_destroy_psv_in_bits {
5074         u8         opcode[0x10];
5075         u8         reserved_at_10[0x10];
5076
5077         u8         reserved_at_20[0x10];
5078         u8         op_mod[0x10];
5079
5080         u8         reserved_at_40[0x8];
5081         u8         psvn[0x18];
5082
5083         u8         reserved_at_60[0x20];
5084 };
5085
5086 struct mlx5_ifc_destroy_mkey_out_bits {
5087         u8         status[0x8];
5088         u8         reserved_at_8[0x18];
5089
5090         u8         syndrome[0x20];
5091
5092         u8         reserved_at_40[0x40];
5093 };
5094
5095 struct mlx5_ifc_destroy_mkey_in_bits {
5096         u8         opcode[0x10];
5097         u8         reserved_at_10[0x10];
5098
5099         u8         reserved_at_20[0x10];
5100         u8         op_mod[0x10];
5101
5102         u8         reserved_at_40[0x8];
5103         u8         mkey_index[0x18];
5104
5105         u8         reserved_at_60[0x20];
5106 };
5107
5108 struct mlx5_ifc_destroy_flow_table_out_bits {
5109         u8         status[0x8];
5110         u8         reserved_at_8[0x18];
5111
5112         u8         syndrome[0x20];
5113
5114         u8         reserved_at_40[0x40];
5115 };
5116
5117 struct mlx5_ifc_destroy_flow_table_in_bits {
5118         u8         opcode[0x10];
5119         u8         reserved_at_10[0x10];
5120
5121         u8         reserved_at_20[0x10];
5122         u8         op_mod[0x10];
5123
5124         u8         reserved_at_40[0x40];
5125
5126         u8         table_type[0x8];
5127         u8         reserved_at_88[0x18];
5128
5129         u8         reserved_at_a0[0x8];
5130         u8         table_id[0x18];
5131
5132         u8         reserved_at_c0[0x140];
5133 };
5134
5135 struct mlx5_ifc_destroy_flow_group_out_bits {
5136         u8         status[0x8];
5137         u8         reserved_at_8[0x18];
5138
5139         u8         syndrome[0x20];
5140
5141         u8         reserved_at_40[0x40];
5142 };
5143
5144 struct mlx5_ifc_destroy_flow_group_in_bits {
5145         u8         opcode[0x10];
5146         u8         reserved_at_10[0x10];
5147
5148         u8         reserved_at_20[0x10];
5149         u8         op_mod[0x10];
5150
5151         u8         reserved_at_40[0x40];
5152
5153         u8         table_type[0x8];
5154         u8         reserved_at_88[0x18];
5155
5156         u8         reserved_at_a0[0x8];
5157         u8         table_id[0x18];
5158
5159         u8         group_id[0x20];
5160
5161         u8         reserved_at_e0[0x120];
5162 };
5163
5164 struct mlx5_ifc_destroy_eq_out_bits {
5165         u8         status[0x8];
5166         u8         reserved_at_8[0x18];
5167
5168         u8         syndrome[0x20];
5169
5170         u8         reserved_at_40[0x40];
5171 };
5172
5173 struct mlx5_ifc_destroy_eq_in_bits {
5174         u8         opcode[0x10];
5175         u8         reserved_at_10[0x10];
5176
5177         u8         reserved_at_20[0x10];
5178         u8         op_mod[0x10];
5179
5180         u8         reserved_at_40[0x18];
5181         u8         eq_number[0x8];
5182
5183         u8         reserved_at_60[0x20];
5184 };
5185
5186 struct mlx5_ifc_destroy_dct_out_bits {
5187         u8         status[0x8];
5188         u8         reserved_at_8[0x18];
5189
5190         u8         syndrome[0x20];
5191
5192         u8         reserved_at_40[0x40];
5193 };
5194
5195 struct mlx5_ifc_destroy_dct_in_bits {
5196         u8         opcode[0x10];
5197         u8         reserved_at_10[0x10];
5198
5199         u8         reserved_at_20[0x10];
5200         u8         op_mod[0x10];
5201
5202         u8         reserved_at_40[0x8];
5203         u8         dctn[0x18];
5204
5205         u8         reserved_at_60[0x20];
5206 };
5207
5208 struct mlx5_ifc_destroy_cq_out_bits {
5209         u8         status[0x8];
5210         u8         reserved_at_8[0x18];
5211
5212         u8         syndrome[0x20];
5213
5214         u8         reserved_at_40[0x40];
5215 };
5216
5217 struct mlx5_ifc_destroy_cq_in_bits {
5218         u8         opcode[0x10];
5219         u8         reserved_at_10[0x10];
5220
5221         u8         reserved_at_20[0x10];
5222         u8         op_mod[0x10];
5223
5224         u8         reserved_at_40[0x8];
5225         u8         cqn[0x18];
5226
5227         u8         reserved_at_60[0x20];
5228 };
5229
5230 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5231         u8         status[0x8];
5232         u8         reserved_at_8[0x18];
5233
5234         u8         syndrome[0x20];
5235
5236         u8         reserved_at_40[0x40];
5237 };
5238
5239 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5240         u8         opcode[0x10];
5241         u8         reserved_at_10[0x10];
5242
5243         u8         reserved_at_20[0x10];
5244         u8         op_mod[0x10];
5245
5246         u8         reserved_at_40[0x20];
5247
5248         u8         reserved_at_60[0x10];
5249         u8         vxlan_udp_port[0x10];
5250 };
5251
5252 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5253         u8         status[0x8];
5254         u8         reserved_at_8[0x18];
5255
5256         u8         syndrome[0x20];
5257
5258         u8         reserved_at_40[0x40];
5259 };
5260
5261 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5262         u8         opcode[0x10];
5263         u8         reserved_at_10[0x10];
5264
5265         u8         reserved_at_20[0x10];
5266         u8         op_mod[0x10];
5267
5268         u8         reserved_at_40[0x60];
5269
5270         u8         reserved_at_a0[0x8];
5271         u8         table_index[0x18];
5272
5273         u8         reserved_at_c0[0x140];
5274 };
5275
5276 struct mlx5_ifc_delete_fte_out_bits {
5277         u8         status[0x8];
5278         u8         reserved_at_8[0x18];
5279
5280         u8         syndrome[0x20];
5281
5282         u8         reserved_at_40[0x40];
5283 };
5284
5285 struct mlx5_ifc_delete_fte_in_bits {
5286         u8         opcode[0x10];
5287         u8         reserved_at_10[0x10];
5288
5289         u8         reserved_at_20[0x10];
5290         u8         op_mod[0x10];
5291
5292         u8         reserved_at_40[0x40];
5293
5294         u8         table_type[0x8];
5295         u8         reserved_at_88[0x18];
5296
5297         u8         reserved_at_a0[0x8];
5298         u8         table_id[0x18];
5299
5300         u8         reserved_at_c0[0x40];
5301
5302         u8         flow_index[0x20];
5303
5304         u8         reserved_at_120[0xe0];
5305 };
5306
5307 struct mlx5_ifc_dealloc_xrcd_out_bits {
5308         u8         status[0x8];
5309         u8         reserved_at_8[0x18];
5310
5311         u8         syndrome[0x20];
5312
5313         u8         reserved_at_40[0x40];
5314 };
5315
5316 struct mlx5_ifc_dealloc_xrcd_in_bits {
5317         u8         opcode[0x10];
5318         u8         reserved_at_10[0x10];
5319
5320         u8         reserved_at_20[0x10];
5321         u8         op_mod[0x10];
5322
5323         u8         reserved_at_40[0x8];
5324         u8         xrcd[0x18];
5325
5326         u8         reserved_at_60[0x20];
5327 };
5328
5329 struct mlx5_ifc_dealloc_uar_out_bits {
5330         u8         status[0x8];
5331         u8         reserved_at_8[0x18];
5332
5333         u8         syndrome[0x20];
5334
5335         u8         reserved_at_40[0x40];
5336 };
5337
5338 struct mlx5_ifc_dealloc_uar_in_bits {
5339         u8         opcode[0x10];
5340         u8         reserved_at_10[0x10];
5341
5342         u8         reserved_at_20[0x10];
5343         u8         op_mod[0x10];
5344
5345         u8         reserved_at_40[0x8];
5346         u8         uar[0x18];
5347
5348         u8         reserved_at_60[0x20];
5349 };
5350
5351 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5352         u8         status[0x8];
5353         u8         reserved_at_8[0x18];
5354
5355         u8         syndrome[0x20];
5356
5357         u8         reserved_at_40[0x40];
5358 };
5359
5360 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5361         u8         opcode[0x10];
5362         u8         reserved_at_10[0x10];
5363
5364         u8         reserved_at_20[0x10];
5365         u8         op_mod[0x10];
5366
5367         u8         reserved_at_40[0x8];
5368         u8         transport_domain[0x18];
5369
5370         u8         reserved_at_60[0x20];
5371 };
5372
5373 struct mlx5_ifc_dealloc_q_counter_out_bits {
5374         u8         status[0x8];
5375         u8         reserved_at_8[0x18];
5376
5377         u8         syndrome[0x20];
5378
5379         u8         reserved_at_40[0x40];
5380 };
5381
5382 struct mlx5_ifc_dealloc_q_counter_in_bits {
5383         u8         opcode[0x10];
5384         u8         reserved_at_10[0x10];
5385
5386         u8         reserved_at_20[0x10];
5387         u8         op_mod[0x10];
5388
5389         u8         reserved_at_40[0x18];
5390         u8         counter_set_id[0x8];
5391
5392         u8         reserved_at_60[0x20];
5393 };
5394
5395 struct mlx5_ifc_dealloc_pd_out_bits {
5396         u8         status[0x8];
5397         u8         reserved_at_8[0x18];
5398
5399         u8         syndrome[0x20];
5400
5401         u8         reserved_at_40[0x40];
5402 };
5403
5404 struct mlx5_ifc_dealloc_pd_in_bits {
5405         u8         opcode[0x10];
5406         u8         reserved_at_10[0x10];
5407
5408         u8         reserved_at_20[0x10];
5409         u8         op_mod[0x10];
5410
5411         u8         reserved_at_40[0x8];
5412         u8         pd[0x18];
5413
5414         u8         reserved_at_60[0x20];
5415 };
5416
5417 struct mlx5_ifc_create_xrc_srq_out_bits {
5418         u8         status[0x8];
5419         u8         reserved_at_8[0x18];
5420
5421         u8         syndrome[0x20];
5422
5423         u8         reserved_at_40[0x8];
5424         u8         xrc_srqn[0x18];
5425
5426         u8         reserved_at_60[0x20];
5427 };
5428
5429 struct mlx5_ifc_create_xrc_srq_in_bits {
5430         u8         opcode[0x10];
5431         u8         reserved_at_10[0x10];
5432
5433         u8         reserved_at_20[0x10];
5434         u8         op_mod[0x10];
5435
5436         u8         reserved_at_40[0x40];
5437
5438         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5439
5440         u8         reserved_at_280[0x600];
5441
5442         u8         pas[0][0x40];
5443 };
5444
5445 struct mlx5_ifc_create_tis_out_bits {
5446         u8         status[0x8];
5447         u8         reserved_at_8[0x18];
5448
5449         u8         syndrome[0x20];
5450
5451         u8         reserved_at_40[0x8];
5452         u8         tisn[0x18];
5453
5454         u8         reserved_at_60[0x20];
5455 };
5456
5457 struct mlx5_ifc_create_tis_in_bits {
5458         u8         opcode[0x10];
5459         u8         reserved_at_10[0x10];
5460
5461         u8         reserved_at_20[0x10];
5462         u8         op_mod[0x10];
5463
5464         u8         reserved_at_40[0xc0];
5465
5466         struct mlx5_ifc_tisc_bits ctx;
5467 };
5468
5469 struct mlx5_ifc_create_tir_out_bits {
5470         u8         status[0x8];
5471         u8         reserved_at_8[0x18];
5472
5473         u8         syndrome[0x20];
5474
5475         u8         reserved_at_40[0x8];
5476         u8         tirn[0x18];
5477
5478         u8         reserved_at_60[0x20];
5479 };
5480
5481 struct mlx5_ifc_create_tir_in_bits {
5482         u8         opcode[0x10];
5483         u8         reserved_at_10[0x10];
5484
5485         u8         reserved_at_20[0x10];
5486         u8         op_mod[0x10];
5487
5488         u8         reserved_at_40[0xc0];
5489
5490         struct mlx5_ifc_tirc_bits ctx;
5491 };
5492
5493 struct mlx5_ifc_create_srq_out_bits {
5494         u8         status[0x8];
5495         u8         reserved_at_8[0x18];
5496
5497         u8         syndrome[0x20];
5498
5499         u8         reserved_at_40[0x8];
5500         u8         srqn[0x18];
5501
5502         u8         reserved_at_60[0x20];
5503 };
5504
5505 struct mlx5_ifc_create_srq_in_bits {
5506         u8         opcode[0x10];
5507         u8         reserved_at_10[0x10];
5508
5509         u8         reserved_at_20[0x10];
5510         u8         op_mod[0x10];
5511
5512         u8         reserved_at_40[0x40];
5513
5514         struct mlx5_ifc_srqc_bits srq_context_entry;
5515
5516         u8         reserved_at_280[0x600];
5517
5518         u8         pas[0][0x40];
5519 };
5520
5521 struct mlx5_ifc_create_sq_out_bits {
5522         u8         status[0x8];
5523         u8         reserved_at_8[0x18];
5524
5525         u8         syndrome[0x20];
5526
5527         u8         reserved_at_40[0x8];
5528         u8         sqn[0x18];
5529
5530         u8         reserved_at_60[0x20];
5531 };
5532
5533 struct mlx5_ifc_create_sq_in_bits {
5534         u8         opcode[0x10];
5535         u8         reserved_at_10[0x10];
5536
5537         u8         reserved_at_20[0x10];
5538         u8         op_mod[0x10];
5539
5540         u8         reserved_at_40[0xc0];
5541
5542         struct mlx5_ifc_sqc_bits ctx;
5543 };
5544
5545 struct mlx5_ifc_create_rqt_out_bits {
5546         u8         status[0x8];
5547         u8         reserved_at_8[0x18];
5548
5549         u8         syndrome[0x20];
5550
5551         u8         reserved_at_40[0x8];
5552         u8         rqtn[0x18];
5553
5554         u8         reserved_at_60[0x20];
5555 };
5556
5557 struct mlx5_ifc_create_rqt_in_bits {
5558         u8         opcode[0x10];
5559         u8         reserved_at_10[0x10];
5560
5561         u8         reserved_at_20[0x10];
5562         u8         op_mod[0x10];
5563
5564         u8         reserved_at_40[0xc0];
5565
5566         struct mlx5_ifc_rqtc_bits rqt_context;
5567 };
5568
5569 struct mlx5_ifc_create_rq_out_bits {
5570         u8         status[0x8];
5571         u8         reserved_at_8[0x18];
5572
5573         u8         syndrome[0x20];
5574
5575         u8         reserved_at_40[0x8];
5576         u8         rqn[0x18];
5577
5578         u8         reserved_at_60[0x20];
5579 };
5580
5581 struct mlx5_ifc_create_rq_in_bits {
5582         u8         opcode[0x10];
5583         u8         reserved_at_10[0x10];
5584
5585         u8         reserved_at_20[0x10];
5586         u8         op_mod[0x10];
5587
5588         u8         reserved_at_40[0xc0];
5589
5590         struct mlx5_ifc_rqc_bits ctx;
5591 };
5592
5593 struct mlx5_ifc_create_rmp_out_bits {
5594         u8         status[0x8];
5595         u8         reserved_at_8[0x18];
5596
5597         u8         syndrome[0x20];
5598
5599         u8         reserved_at_40[0x8];
5600         u8         rmpn[0x18];
5601
5602         u8         reserved_at_60[0x20];
5603 };
5604
5605 struct mlx5_ifc_create_rmp_in_bits {
5606         u8         opcode[0x10];
5607         u8         reserved_at_10[0x10];
5608
5609         u8         reserved_at_20[0x10];
5610         u8         op_mod[0x10];
5611
5612         u8         reserved_at_40[0xc0];
5613
5614         struct mlx5_ifc_rmpc_bits ctx;
5615 };
5616
5617 struct mlx5_ifc_create_qp_out_bits {
5618         u8         status[0x8];
5619         u8         reserved_at_8[0x18];
5620
5621         u8         syndrome[0x20];
5622
5623         u8         reserved_at_40[0x8];
5624         u8         qpn[0x18];
5625
5626         u8         reserved_at_60[0x20];
5627 };
5628
5629 struct mlx5_ifc_create_qp_in_bits {
5630         u8         opcode[0x10];
5631         u8         reserved_at_10[0x10];
5632
5633         u8         reserved_at_20[0x10];
5634         u8         op_mod[0x10];
5635
5636         u8         reserved_at_40[0x40];
5637
5638         u8         opt_param_mask[0x20];
5639
5640         u8         reserved_at_a0[0x20];
5641
5642         struct mlx5_ifc_qpc_bits qpc;
5643
5644         u8         reserved_at_800[0x80];
5645
5646         u8         pas[0][0x40];
5647 };
5648
5649 struct mlx5_ifc_create_psv_out_bits {
5650         u8         status[0x8];
5651         u8         reserved_at_8[0x18];
5652
5653         u8         syndrome[0x20];
5654
5655         u8         reserved_at_40[0x40];
5656
5657         u8         reserved_at_80[0x8];
5658         u8         psv0_index[0x18];
5659
5660         u8         reserved_at_a0[0x8];
5661         u8         psv1_index[0x18];
5662
5663         u8         reserved_at_c0[0x8];
5664         u8         psv2_index[0x18];
5665
5666         u8         reserved_at_e0[0x8];
5667         u8         psv3_index[0x18];
5668 };
5669
5670 struct mlx5_ifc_create_psv_in_bits {
5671         u8         opcode[0x10];
5672         u8         reserved_at_10[0x10];
5673
5674         u8         reserved_at_20[0x10];
5675         u8         op_mod[0x10];
5676
5677         u8         num_psv[0x4];
5678         u8         reserved_at_44[0x4];
5679         u8         pd[0x18];
5680
5681         u8         reserved_at_60[0x20];
5682 };
5683
5684 struct mlx5_ifc_create_mkey_out_bits {
5685         u8         status[0x8];
5686         u8         reserved_at_8[0x18];
5687
5688         u8         syndrome[0x20];
5689
5690         u8         reserved_at_40[0x8];
5691         u8         mkey_index[0x18];
5692
5693         u8         reserved_at_60[0x20];
5694 };
5695
5696 struct mlx5_ifc_create_mkey_in_bits {
5697         u8         opcode[0x10];
5698         u8         reserved_at_10[0x10];
5699
5700         u8         reserved_at_20[0x10];
5701         u8         op_mod[0x10];
5702
5703         u8         reserved_at_40[0x20];
5704
5705         u8         pg_access[0x1];
5706         u8         reserved_at_61[0x1f];
5707
5708         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5709
5710         u8         reserved_at_280[0x80];
5711
5712         u8         translations_octword_actual_size[0x20];
5713
5714         u8         reserved_at_320[0x560];
5715
5716         u8         klm_pas_mtt[0][0x20];
5717 };
5718
5719 struct mlx5_ifc_create_flow_table_out_bits {
5720         u8         status[0x8];
5721         u8         reserved_at_8[0x18];
5722
5723         u8         syndrome[0x20];
5724
5725         u8         reserved_at_40[0x8];
5726         u8         table_id[0x18];
5727
5728         u8         reserved_at_60[0x20];
5729 };
5730
5731 struct mlx5_ifc_create_flow_table_in_bits {
5732         u8         opcode[0x10];
5733         u8         reserved_at_10[0x10];
5734
5735         u8         reserved_at_20[0x10];
5736         u8         op_mod[0x10];
5737
5738         u8         reserved_at_40[0x40];
5739
5740         u8         table_type[0x8];
5741         u8         reserved_at_88[0x18];
5742
5743         u8         reserved_at_a0[0x20];
5744
5745         u8         reserved_at_c0[0x4];
5746         u8         table_miss_mode[0x4];
5747         u8         level[0x8];
5748         u8         reserved_at_d0[0x8];
5749         u8         log_size[0x8];
5750
5751         u8         reserved_at_e0[0x8];
5752         u8         table_miss_id[0x18];
5753
5754         u8         reserved_at_100[0x100];
5755 };
5756
5757 struct mlx5_ifc_create_flow_group_out_bits {
5758         u8         status[0x8];
5759         u8         reserved_at_8[0x18];
5760
5761         u8         syndrome[0x20];
5762
5763         u8         reserved_at_40[0x8];
5764         u8         group_id[0x18];
5765
5766         u8         reserved_at_60[0x20];
5767 };
5768
5769 enum {
5770         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5771         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5772         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5773 };
5774
5775 struct mlx5_ifc_create_flow_group_in_bits {
5776         u8         opcode[0x10];
5777         u8         reserved_at_10[0x10];
5778
5779         u8         reserved_at_20[0x10];
5780         u8         op_mod[0x10];
5781
5782         u8         reserved_at_40[0x40];
5783
5784         u8         table_type[0x8];
5785         u8         reserved_at_88[0x18];
5786
5787         u8         reserved_at_a0[0x8];
5788         u8         table_id[0x18];
5789
5790         u8         reserved_at_c0[0x20];
5791
5792         u8         start_flow_index[0x20];
5793
5794         u8         reserved_at_100[0x20];
5795
5796         u8         end_flow_index[0x20];
5797
5798         u8         reserved_at_140[0xa0];
5799
5800         u8         reserved_at_1e0[0x18];
5801         u8         match_criteria_enable[0x8];
5802
5803         struct mlx5_ifc_fte_match_param_bits match_criteria;
5804
5805         u8         reserved_at_1200[0xe00];
5806 };
5807
5808 struct mlx5_ifc_create_eq_out_bits {
5809         u8         status[0x8];
5810         u8         reserved_at_8[0x18];
5811
5812         u8         syndrome[0x20];
5813
5814         u8         reserved_at_40[0x18];
5815         u8         eq_number[0x8];
5816
5817         u8         reserved_at_60[0x20];
5818 };
5819
5820 struct mlx5_ifc_create_eq_in_bits {
5821         u8         opcode[0x10];
5822         u8         reserved_at_10[0x10];
5823
5824         u8         reserved_at_20[0x10];
5825         u8         op_mod[0x10];
5826
5827         u8         reserved_at_40[0x40];
5828
5829         struct mlx5_ifc_eqc_bits eq_context_entry;
5830
5831         u8         reserved_at_280[0x40];
5832
5833         u8         event_bitmask[0x40];
5834
5835         u8         reserved_at_300[0x580];
5836
5837         u8         pas[0][0x40];
5838 };
5839
5840 struct mlx5_ifc_create_dct_out_bits {
5841         u8         status[0x8];
5842         u8         reserved_at_8[0x18];
5843
5844         u8         syndrome[0x20];
5845
5846         u8         reserved_at_40[0x8];
5847         u8         dctn[0x18];
5848
5849         u8         reserved_at_60[0x20];
5850 };
5851
5852 struct mlx5_ifc_create_dct_in_bits {
5853         u8         opcode[0x10];
5854         u8         reserved_at_10[0x10];
5855
5856         u8         reserved_at_20[0x10];
5857         u8         op_mod[0x10];
5858
5859         u8         reserved_at_40[0x40];
5860
5861         struct mlx5_ifc_dctc_bits dct_context_entry;
5862
5863         u8         reserved_at_280[0x180];
5864 };
5865
5866 struct mlx5_ifc_create_cq_out_bits {
5867         u8         status[0x8];
5868         u8         reserved_at_8[0x18];
5869
5870         u8         syndrome[0x20];
5871
5872         u8         reserved_at_40[0x8];
5873         u8         cqn[0x18];
5874
5875         u8         reserved_at_60[0x20];
5876 };
5877
5878 struct mlx5_ifc_create_cq_in_bits {
5879         u8         opcode[0x10];
5880         u8         reserved_at_10[0x10];
5881
5882         u8         reserved_at_20[0x10];
5883         u8         op_mod[0x10];
5884
5885         u8         reserved_at_40[0x40];
5886
5887         struct mlx5_ifc_cqc_bits cq_context;
5888
5889         u8         reserved_at_280[0x600];
5890
5891         u8         pas[0][0x40];
5892 };
5893
5894 struct mlx5_ifc_config_int_moderation_out_bits {
5895         u8         status[0x8];
5896         u8         reserved_at_8[0x18];
5897
5898         u8         syndrome[0x20];
5899
5900         u8         reserved_at_40[0x4];
5901         u8         min_delay[0xc];
5902         u8         int_vector[0x10];
5903
5904         u8         reserved_at_60[0x20];
5905 };
5906
5907 enum {
5908         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
5909         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
5910 };
5911
5912 struct mlx5_ifc_config_int_moderation_in_bits {
5913         u8         opcode[0x10];
5914         u8         reserved_at_10[0x10];
5915
5916         u8         reserved_at_20[0x10];
5917         u8         op_mod[0x10];
5918
5919         u8         reserved_at_40[0x4];
5920         u8         min_delay[0xc];
5921         u8         int_vector[0x10];
5922
5923         u8         reserved_at_60[0x20];
5924 };
5925
5926 struct mlx5_ifc_attach_to_mcg_out_bits {
5927         u8         status[0x8];
5928         u8         reserved_at_8[0x18];
5929
5930         u8         syndrome[0x20];
5931
5932         u8         reserved_at_40[0x40];
5933 };
5934
5935 struct mlx5_ifc_attach_to_mcg_in_bits {
5936         u8         opcode[0x10];
5937         u8         reserved_at_10[0x10];
5938
5939         u8         reserved_at_20[0x10];
5940         u8         op_mod[0x10];
5941
5942         u8         reserved_at_40[0x8];
5943         u8         qpn[0x18];
5944
5945         u8         reserved_at_60[0x20];
5946
5947         u8         multicast_gid[16][0x8];
5948 };
5949
5950 struct mlx5_ifc_arm_xrc_srq_out_bits {
5951         u8         status[0x8];
5952         u8         reserved_at_8[0x18];
5953
5954         u8         syndrome[0x20];
5955
5956         u8         reserved_at_40[0x40];
5957 };
5958
5959 enum {
5960         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
5961 };
5962
5963 struct mlx5_ifc_arm_xrc_srq_in_bits {
5964         u8         opcode[0x10];
5965         u8         reserved_at_10[0x10];
5966
5967         u8         reserved_at_20[0x10];
5968         u8         op_mod[0x10];
5969
5970         u8         reserved_at_40[0x8];
5971         u8         xrc_srqn[0x18];
5972
5973         u8         reserved_at_60[0x10];
5974         u8         lwm[0x10];
5975 };
5976
5977 struct mlx5_ifc_arm_rq_out_bits {
5978         u8         status[0x8];
5979         u8         reserved_at_8[0x18];
5980
5981         u8         syndrome[0x20];
5982
5983         u8         reserved_at_40[0x40];
5984 };
5985
5986 enum {
5987         MLX5_ARM_RQ_IN_OP_MOD_SRQ_  = 0x1,
5988 };
5989
5990 struct mlx5_ifc_arm_rq_in_bits {
5991         u8         opcode[0x10];
5992         u8         reserved_at_10[0x10];
5993
5994         u8         reserved_at_20[0x10];
5995         u8         op_mod[0x10];
5996
5997         u8         reserved_at_40[0x8];
5998         u8         srq_number[0x18];
5999
6000         u8         reserved_at_60[0x10];
6001         u8         lwm[0x10];
6002 };
6003
6004 struct mlx5_ifc_arm_dct_out_bits {
6005         u8         status[0x8];
6006         u8         reserved_at_8[0x18];
6007
6008         u8         syndrome[0x20];
6009
6010         u8         reserved_at_40[0x40];
6011 };
6012
6013 struct mlx5_ifc_arm_dct_in_bits {
6014         u8         opcode[0x10];
6015         u8         reserved_at_10[0x10];
6016
6017         u8         reserved_at_20[0x10];
6018         u8         op_mod[0x10];
6019
6020         u8         reserved_at_40[0x8];
6021         u8         dct_number[0x18];
6022
6023         u8         reserved_at_60[0x20];
6024 };
6025
6026 struct mlx5_ifc_alloc_xrcd_out_bits {
6027         u8         status[0x8];
6028         u8         reserved_at_8[0x18];
6029
6030         u8         syndrome[0x20];
6031
6032         u8         reserved_at_40[0x8];
6033         u8         xrcd[0x18];
6034
6035         u8         reserved_at_60[0x20];
6036 };
6037
6038 struct mlx5_ifc_alloc_xrcd_in_bits {
6039         u8         opcode[0x10];
6040         u8         reserved_at_10[0x10];
6041
6042         u8         reserved_at_20[0x10];
6043         u8         op_mod[0x10];
6044
6045         u8         reserved_at_40[0x40];
6046 };
6047
6048 struct mlx5_ifc_alloc_uar_out_bits {
6049         u8         status[0x8];
6050         u8         reserved_at_8[0x18];
6051
6052         u8         syndrome[0x20];
6053
6054         u8         reserved_at_40[0x8];
6055         u8         uar[0x18];
6056
6057         u8         reserved_at_60[0x20];
6058 };
6059
6060 struct mlx5_ifc_alloc_uar_in_bits {
6061         u8         opcode[0x10];
6062         u8         reserved_at_10[0x10];
6063
6064         u8         reserved_at_20[0x10];
6065         u8         op_mod[0x10];
6066
6067         u8         reserved_at_40[0x40];
6068 };
6069
6070 struct mlx5_ifc_alloc_transport_domain_out_bits {
6071         u8         status[0x8];
6072         u8         reserved_at_8[0x18];
6073
6074         u8         syndrome[0x20];
6075
6076         u8         reserved_at_40[0x8];
6077         u8         transport_domain[0x18];
6078
6079         u8         reserved_at_60[0x20];
6080 };
6081
6082 struct mlx5_ifc_alloc_transport_domain_in_bits {
6083         u8         opcode[0x10];
6084         u8         reserved_at_10[0x10];
6085
6086         u8         reserved_at_20[0x10];
6087         u8         op_mod[0x10];
6088
6089         u8         reserved_at_40[0x40];
6090 };
6091
6092 struct mlx5_ifc_alloc_q_counter_out_bits {
6093         u8         status[0x8];
6094         u8         reserved_at_8[0x18];
6095
6096         u8         syndrome[0x20];
6097
6098         u8         reserved_at_40[0x18];
6099         u8         counter_set_id[0x8];
6100
6101         u8         reserved_at_60[0x20];
6102 };
6103
6104 struct mlx5_ifc_alloc_q_counter_in_bits {
6105         u8         opcode[0x10];
6106         u8         reserved_at_10[0x10];
6107
6108         u8         reserved_at_20[0x10];
6109         u8         op_mod[0x10];
6110
6111         u8         reserved_at_40[0x40];
6112 };
6113
6114 struct mlx5_ifc_alloc_pd_out_bits {
6115         u8         status[0x8];
6116         u8         reserved_at_8[0x18];
6117
6118         u8         syndrome[0x20];
6119
6120         u8         reserved_at_40[0x8];
6121         u8         pd[0x18];
6122
6123         u8         reserved_at_60[0x20];
6124 };
6125
6126 struct mlx5_ifc_alloc_pd_in_bits {
6127         u8         opcode[0x10];
6128         u8         reserved_at_10[0x10];
6129
6130         u8         reserved_at_20[0x10];
6131         u8         op_mod[0x10];
6132
6133         u8         reserved_at_40[0x40];
6134 };
6135
6136 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6137         u8         status[0x8];
6138         u8         reserved_at_8[0x18];
6139
6140         u8         syndrome[0x20];
6141
6142         u8         reserved_at_40[0x40];
6143 };
6144
6145 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6146         u8         opcode[0x10];
6147         u8         reserved_at_10[0x10];
6148
6149         u8         reserved_at_20[0x10];
6150         u8         op_mod[0x10];
6151
6152         u8         reserved_at_40[0x20];
6153
6154         u8         reserved_at_60[0x10];
6155         u8         vxlan_udp_port[0x10];
6156 };
6157
6158 struct mlx5_ifc_access_register_out_bits {
6159         u8         status[0x8];
6160         u8         reserved_at_8[0x18];
6161
6162         u8         syndrome[0x20];
6163
6164         u8         reserved_at_40[0x40];
6165
6166         u8         register_data[0][0x20];
6167 };
6168
6169 enum {
6170         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
6171         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
6172 };
6173
6174 struct mlx5_ifc_access_register_in_bits {
6175         u8         opcode[0x10];
6176         u8         reserved_at_10[0x10];
6177
6178         u8         reserved_at_20[0x10];
6179         u8         op_mod[0x10];
6180
6181         u8         reserved_at_40[0x10];
6182         u8         register_id[0x10];
6183
6184         u8         argument[0x20];
6185
6186         u8         register_data[0][0x20];
6187 };
6188
6189 struct mlx5_ifc_sltp_reg_bits {
6190         u8         status[0x4];
6191         u8         version[0x4];
6192         u8         local_port[0x8];
6193         u8         pnat[0x2];
6194         u8         reserved_at_12[0x2];
6195         u8         lane[0x4];
6196         u8         reserved_at_18[0x8];
6197
6198         u8         reserved_at_20[0x20];
6199
6200         u8         reserved_at_40[0x7];
6201         u8         polarity[0x1];
6202         u8         ob_tap0[0x8];
6203         u8         ob_tap1[0x8];
6204         u8         ob_tap2[0x8];
6205
6206         u8         reserved_at_60[0xc];
6207         u8         ob_preemp_mode[0x4];
6208         u8         ob_reg[0x8];
6209         u8         ob_bias[0x8];
6210
6211         u8         reserved_at_80[0x20];
6212 };
6213
6214 struct mlx5_ifc_slrg_reg_bits {
6215         u8         status[0x4];
6216         u8         version[0x4];
6217         u8         local_port[0x8];
6218         u8         pnat[0x2];
6219         u8         reserved_at_12[0x2];
6220         u8         lane[0x4];
6221         u8         reserved_at_18[0x8];
6222
6223         u8         time_to_link_up[0x10];
6224         u8         reserved_at_30[0xc];
6225         u8         grade_lane_speed[0x4];
6226
6227         u8         grade_version[0x8];
6228         u8         grade[0x18];
6229
6230         u8         reserved_at_60[0x4];
6231         u8         height_grade_type[0x4];
6232         u8         height_grade[0x18];
6233
6234         u8         height_dz[0x10];
6235         u8         height_dv[0x10];
6236
6237         u8         reserved_at_a0[0x10];
6238         u8         height_sigma[0x10];
6239
6240         u8         reserved_at_c0[0x20];
6241
6242         u8         reserved_at_e0[0x4];
6243         u8         phase_grade_type[0x4];
6244         u8         phase_grade[0x18];
6245
6246         u8         reserved_at_100[0x8];
6247         u8         phase_eo_pos[0x8];
6248         u8         reserved_at_110[0x8];
6249         u8         phase_eo_neg[0x8];
6250
6251         u8         ffe_set_tested[0x10];
6252         u8         test_errors_per_lane[0x10];
6253 };
6254
6255 struct mlx5_ifc_pvlc_reg_bits {
6256         u8         reserved_at_0[0x8];
6257         u8         local_port[0x8];
6258         u8         reserved_at_10[0x10];
6259
6260         u8         reserved_at_20[0x1c];
6261         u8         vl_hw_cap[0x4];
6262
6263         u8         reserved_at_40[0x1c];
6264         u8         vl_admin[0x4];
6265
6266         u8         reserved_at_60[0x1c];
6267         u8         vl_operational[0x4];
6268 };
6269
6270 struct mlx5_ifc_pude_reg_bits {
6271         u8         swid[0x8];
6272         u8         local_port[0x8];
6273         u8         reserved_at_10[0x4];
6274         u8         admin_status[0x4];
6275         u8         reserved_at_18[0x4];
6276         u8         oper_status[0x4];
6277
6278         u8         reserved_at_20[0x60];
6279 };
6280
6281 struct mlx5_ifc_ptys_reg_bits {
6282         u8         reserved_at_0[0x8];
6283         u8         local_port[0x8];
6284         u8         reserved_at_10[0xd];
6285         u8         proto_mask[0x3];
6286
6287         u8         reserved_at_20[0x40];
6288
6289         u8         eth_proto_capability[0x20];
6290
6291         u8         ib_link_width_capability[0x10];
6292         u8         ib_proto_capability[0x10];
6293
6294         u8         reserved_at_a0[0x20];
6295
6296         u8         eth_proto_admin[0x20];
6297
6298         u8         ib_link_width_admin[0x10];
6299         u8         ib_proto_admin[0x10];
6300
6301         u8         reserved_at_100[0x20];
6302
6303         u8         eth_proto_oper[0x20];
6304
6305         u8         ib_link_width_oper[0x10];
6306         u8         ib_proto_oper[0x10];
6307
6308         u8         reserved_at_160[0x20];
6309
6310         u8         eth_proto_lp_advertise[0x20];
6311
6312         u8         reserved_at_1a0[0x60];
6313 };
6314
6315 struct mlx5_ifc_ptas_reg_bits {
6316         u8         reserved_at_0[0x20];
6317
6318         u8         algorithm_options[0x10];
6319         u8         reserved_at_30[0x4];
6320         u8         repetitions_mode[0x4];
6321         u8         num_of_repetitions[0x8];
6322
6323         u8         grade_version[0x8];
6324         u8         height_grade_type[0x4];
6325         u8         phase_grade_type[0x4];
6326         u8         height_grade_weight[0x8];
6327         u8         phase_grade_weight[0x8];
6328
6329         u8         gisim_measure_bits[0x10];
6330         u8         adaptive_tap_measure_bits[0x10];
6331
6332         u8         ber_bath_high_error_threshold[0x10];
6333         u8         ber_bath_mid_error_threshold[0x10];
6334
6335         u8         ber_bath_low_error_threshold[0x10];
6336         u8         one_ratio_high_threshold[0x10];
6337
6338         u8         one_ratio_high_mid_threshold[0x10];
6339         u8         one_ratio_low_mid_threshold[0x10];
6340
6341         u8         one_ratio_low_threshold[0x10];
6342         u8         ndeo_error_threshold[0x10];
6343
6344         u8         mixer_offset_step_size[0x10];
6345         u8         reserved_at_110[0x8];
6346         u8         mix90_phase_for_voltage_bath[0x8];
6347
6348         u8         mixer_offset_start[0x10];
6349         u8         mixer_offset_end[0x10];
6350
6351         u8         reserved_at_140[0x15];
6352         u8         ber_test_time[0xb];
6353 };
6354
6355 struct mlx5_ifc_pspa_reg_bits {
6356         u8         swid[0x8];
6357         u8         local_port[0x8];
6358         u8         sub_port[0x8];
6359         u8         reserved_at_18[0x8];
6360
6361         u8         reserved_at_20[0x20];
6362 };
6363
6364 struct mlx5_ifc_pqdr_reg_bits {
6365         u8         reserved_at_0[0x8];
6366         u8         local_port[0x8];
6367         u8         reserved_at_10[0x5];
6368         u8         prio[0x3];
6369         u8         reserved_at_18[0x6];
6370         u8         mode[0x2];
6371
6372         u8         reserved_at_20[0x20];
6373
6374         u8         reserved_at_40[0x10];
6375         u8         min_threshold[0x10];
6376
6377         u8         reserved_at_60[0x10];
6378         u8         max_threshold[0x10];
6379
6380         u8         reserved_at_80[0x10];
6381         u8         mark_probability_denominator[0x10];
6382
6383         u8         reserved_at_a0[0x60];
6384 };
6385
6386 struct mlx5_ifc_ppsc_reg_bits {
6387         u8         reserved_at_0[0x8];
6388         u8         local_port[0x8];
6389         u8         reserved_at_10[0x10];
6390
6391         u8         reserved_at_20[0x60];
6392
6393         u8         reserved_at_80[0x1c];
6394         u8         wrps_admin[0x4];
6395
6396         u8         reserved_at_a0[0x1c];
6397         u8         wrps_status[0x4];
6398
6399         u8         reserved_at_c0[0x8];
6400         u8         up_threshold[0x8];
6401         u8         reserved_at_d0[0x8];
6402         u8         down_threshold[0x8];
6403
6404         u8         reserved_at_e0[0x20];
6405
6406         u8         reserved_at_100[0x1c];
6407         u8         srps_admin[0x4];
6408
6409         u8         reserved_at_120[0x1c];
6410         u8         srps_status[0x4];
6411
6412         u8         reserved_at_140[0x40];
6413 };
6414
6415 struct mlx5_ifc_pplr_reg_bits {
6416         u8         reserved_at_0[0x8];
6417         u8         local_port[0x8];
6418         u8         reserved_at_10[0x10];
6419
6420         u8         reserved_at_20[0x8];
6421         u8         lb_cap[0x8];
6422         u8         reserved_at_30[0x8];
6423         u8         lb_en[0x8];
6424 };
6425
6426 struct mlx5_ifc_pplm_reg_bits {
6427         u8         reserved_at_0[0x8];
6428         u8         local_port[0x8];
6429         u8         reserved_at_10[0x10];
6430
6431         u8         reserved_at_20[0x20];
6432
6433         u8         port_profile_mode[0x8];
6434         u8         static_port_profile[0x8];
6435         u8         active_port_profile[0x8];
6436         u8         reserved_at_58[0x8];
6437
6438         u8         retransmission_active[0x8];
6439         u8         fec_mode_active[0x18];
6440
6441         u8         reserved_at_80[0x20];
6442 };
6443
6444 struct mlx5_ifc_ppcnt_reg_bits {
6445         u8         swid[0x8];
6446         u8         local_port[0x8];
6447         u8         pnat[0x2];
6448         u8         reserved_at_12[0x8];
6449         u8         grp[0x6];
6450
6451         u8         clr[0x1];
6452         u8         reserved_at_21[0x1c];
6453         u8         prio_tc[0x3];
6454
6455         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6456 };
6457
6458 struct mlx5_ifc_ppad_reg_bits {
6459         u8         reserved_at_0[0x3];
6460         u8         single_mac[0x1];
6461         u8         reserved_at_4[0x4];
6462         u8         local_port[0x8];
6463         u8         mac_47_32[0x10];
6464
6465         u8         mac_31_0[0x20];
6466
6467         u8         reserved_at_40[0x40];
6468 };
6469
6470 struct mlx5_ifc_pmtu_reg_bits {
6471         u8         reserved_at_0[0x8];
6472         u8         local_port[0x8];
6473         u8         reserved_at_10[0x10];
6474
6475         u8         max_mtu[0x10];
6476         u8         reserved_at_30[0x10];
6477
6478         u8         admin_mtu[0x10];
6479         u8         reserved_at_50[0x10];
6480
6481         u8         oper_mtu[0x10];
6482         u8         reserved_at_70[0x10];
6483 };
6484
6485 struct mlx5_ifc_pmpr_reg_bits {
6486         u8         reserved_at_0[0x8];
6487         u8         module[0x8];
6488         u8         reserved_at_10[0x10];
6489
6490         u8         reserved_at_20[0x18];
6491         u8         attenuation_5g[0x8];
6492
6493         u8         reserved_at_40[0x18];
6494         u8         attenuation_7g[0x8];
6495
6496         u8         reserved_at_60[0x18];
6497         u8         attenuation_12g[0x8];
6498 };
6499
6500 struct mlx5_ifc_pmpe_reg_bits {
6501         u8         reserved_at_0[0x8];
6502         u8         module[0x8];
6503         u8         reserved_at_10[0xc];
6504         u8         module_status[0x4];
6505
6506         u8         reserved_at_20[0x60];
6507 };
6508
6509 struct mlx5_ifc_pmpc_reg_bits {
6510         u8         module_state_updated[32][0x8];
6511 };
6512
6513 struct mlx5_ifc_pmlpn_reg_bits {
6514         u8         reserved_at_0[0x4];
6515         u8         mlpn_status[0x4];
6516         u8         local_port[0x8];
6517         u8         reserved_at_10[0x10];
6518
6519         u8         e[0x1];
6520         u8         reserved_at_21[0x1f];
6521 };
6522
6523 struct mlx5_ifc_pmlp_reg_bits {
6524         u8         rxtx[0x1];
6525         u8         reserved_at_1[0x7];
6526         u8         local_port[0x8];
6527         u8         reserved_at_10[0x8];
6528         u8         width[0x8];
6529
6530         u8         lane0_module_mapping[0x20];
6531
6532         u8         lane1_module_mapping[0x20];
6533
6534         u8         lane2_module_mapping[0x20];
6535
6536         u8         lane3_module_mapping[0x20];
6537
6538         u8         reserved_at_a0[0x160];
6539 };
6540
6541 struct mlx5_ifc_pmaos_reg_bits {
6542         u8         reserved_at_0[0x8];
6543         u8         module[0x8];
6544         u8         reserved_at_10[0x4];
6545         u8         admin_status[0x4];
6546         u8         reserved_at_18[0x4];
6547         u8         oper_status[0x4];
6548
6549         u8         ase[0x1];
6550         u8         ee[0x1];
6551         u8         reserved_at_22[0x1c];
6552         u8         e[0x2];
6553
6554         u8         reserved_at_40[0x40];
6555 };
6556
6557 struct mlx5_ifc_plpc_reg_bits {
6558         u8         reserved_at_0[0x4];
6559         u8         profile_id[0xc];
6560         u8         reserved_at_10[0x4];
6561         u8         proto_mask[0x4];
6562         u8         reserved_at_18[0x8];
6563
6564         u8         reserved_at_20[0x10];
6565         u8         lane_speed[0x10];
6566
6567         u8         reserved_at_40[0x17];
6568         u8         lpbf[0x1];
6569         u8         fec_mode_policy[0x8];
6570
6571         u8         retransmission_capability[0x8];
6572         u8         fec_mode_capability[0x18];
6573
6574         u8         retransmission_support_admin[0x8];
6575         u8         fec_mode_support_admin[0x18];
6576
6577         u8         retransmission_request_admin[0x8];
6578         u8         fec_mode_request_admin[0x18];
6579
6580         u8         reserved_at_c0[0x80];
6581 };
6582
6583 struct mlx5_ifc_plib_reg_bits {
6584         u8         reserved_at_0[0x8];
6585         u8         local_port[0x8];
6586         u8         reserved_at_10[0x8];
6587         u8         ib_port[0x8];
6588
6589         u8         reserved_at_20[0x60];
6590 };
6591
6592 struct mlx5_ifc_plbf_reg_bits {
6593         u8         reserved_at_0[0x8];
6594         u8         local_port[0x8];
6595         u8         reserved_at_10[0xd];
6596         u8         lbf_mode[0x3];
6597
6598         u8         reserved_at_20[0x20];
6599 };
6600
6601 struct mlx5_ifc_pipg_reg_bits {
6602         u8         reserved_at_0[0x8];
6603         u8         local_port[0x8];
6604         u8         reserved_at_10[0x10];
6605
6606         u8         dic[0x1];
6607         u8         reserved_at_21[0x19];
6608         u8         ipg[0x4];
6609         u8         reserved_at_3e[0x2];
6610 };
6611
6612 struct mlx5_ifc_pifr_reg_bits {
6613         u8         reserved_at_0[0x8];
6614         u8         local_port[0x8];
6615         u8         reserved_at_10[0x10];
6616
6617         u8         reserved_at_20[0xe0];
6618
6619         u8         port_filter[8][0x20];
6620
6621         u8         port_filter_update_en[8][0x20];
6622 };
6623
6624 struct mlx5_ifc_pfcc_reg_bits {
6625         u8         reserved_at_0[0x8];
6626         u8         local_port[0x8];
6627         u8         reserved_at_10[0x10];
6628
6629         u8         ppan[0x4];
6630         u8         reserved_at_24[0x4];
6631         u8         prio_mask_tx[0x8];
6632         u8         reserved_at_30[0x8];
6633         u8         prio_mask_rx[0x8];
6634
6635         u8         pptx[0x1];
6636         u8         aptx[0x1];
6637         u8         reserved_at_42[0x6];
6638         u8         pfctx[0x8];
6639         u8         reserved_at_50[0x10];
6640
6641         u8         pprx[0x1];
6642         u8         aprx[0x1];
6643         u8         reserved_at_62[0x6];
6644         u8         pfcrx[0x8];
6645         u8         reserved_at_70[0x10];
6646
6647         u8         reserved_at_80[0x80];
6648 };
6649
6650 struct mlx5_ifc_pelc_reg_bits {
6651         u8         op[0x4];
6652         u8         reserved_at_4[0x4];
6653         u8         local_port[0x8];
6654         u8         reserved_at_10[0x10];
6655
6656         u8         op_admin[0x8];
6657         u8         op_capability[0x8];
6658         u8         op_request[0x8];
6659         u8         op_active[0x8];
6660
6661         u8         admin[0x40];
6662
6663         u8         capability[0x40];
6664
6665         u8         request[0x40];
6666
6667         u8         active[0x40];
6668
6669         u8         reserved_at_140[0x80];
6670 };
6671
6672 struct mlx5_ifc_peir_reg_bits {
6673         u8         reserved_at_0[0x8];
6674         u8         local_port[0x8];
6675         u8         reserved_at_10[0x10];
6676
6677         u8         reserved_at_20[0xc];
6678         u8         error_count[0x4];
6679         u8         reserved_at_30[0x10];
6680
6681         u8         reserved_at_40[0xc];
6682         u8         lane[0x4];
6683         u8         reserved_at_50[0x8];
6684         u8         error_type[0x8];
6685 };
6686
6687 struct mlx5_ifc_pcap_reg_bits {
6688         u8         reserved_at_0[0x8];
6689         u8         local_port[0x8];
6690         u8         reserved_at_10[0x10];
6691
6692         u8         port_capability_mask[4][0x20];
6693 };
6694
6695 struct mlx5_ifc_paos_reg_bits {
6696         u8         swid[0x8];
6697         u8         local_port[0x8];
6698         u8         reserved_at_10[0x4];
6699         u8         admin_status[0x4];
6700         u8         reserved_at_18[0x4];
6701         u8         oper_status[0x4];
6702
6703         u8         ase[0x1];
6704         u8         ee[0x1];
6705         u8         reserved_at_22[0x1c];
6706         u8         e[0x2];
6707
6708         u8         reserved_at_40[0x40];
6709 };
6710
6711 struct mlx5_ifc_pamp_reg_bits {
6712         u8         reserved_at_0[0x8];
6713         u8         opamp_group[0x8];
6714         u8         reserved_at_10[0xc];
6715         u8         opamp_group_type[0x4];
6716
6717         u8         start_index[0x10];
6718         u8         reserved_at_30[0x4];
6719         u8         num_of_indices[0xc];
6720
6721         u8         index_data[18][0x10];
6722 };
6723
6724 struct mlx5_ifc_lane_2_module_mapping_bits {
6725         u8         reserved_at_0[0x6];
6726         u8         rx_lane[0x2];
6727         u8         reserved_at_8[0x6];
6728         u8         tx_lane[0x2];
6729         u8         reserved_at_10[0x8];
6730         u8         module[0x8];
6731 };
6732
6733 struct mlx5_ifc_bufferx_reg_bits {
6734         u8         reserved_at_0[0x6];
6735         u8         lossy[0x1];
6736         u8         epsb[0x1];
6737         u8         reserved_at_8[0xc];
6738         u8         size[0xc];
6739
6740         u8         xoff_threshold[0x10];
6741         u8         xon_threshold[0x10];
6742 };
6743
6744 struct mlx5_ifc_set_node_in_bits {
6745         u8         node_description[64][0x8];
6746 };
6747
6748 struct mlx5_ifc_register_power_settings_bits {
6749         u8         reserved_at_0[0x18];
6750         u8         power_settings_level[0x8];
6751
6752         u8         reserved_at_20[0x60];
6753 };
6754
6755 struct mlx5_ifc_register_host_endianness_bits {
6756         u8         he[0x1];
6757         u8         reserved_at_1[0x1f];
6758
6759         u8         reserved_at_20[0x60];
6760 };
6761
6762 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6763         u8         reserved_at_0[0x20];
6764
6765         u8         mkey[0x20];
6766
6767         u8         addressh_63_32[0x20];
6768
6769         u8         addressl_31_0[0x20];
6770 };
6771
6772 struct mlx5_ifc_ud_adrs_vector_bits {
6773         u8         dc_key[0x40];
6774
6775         u8         ext[0x1];
6776         u8         reserved_at_41[0x7];
6777         u8         destination_qp_dct[0x18];
6778
6779         u8         static_rate[0x4];
6780         u8         sl_eth_prio[0x4];
6781         u8         fl[0x1];
6782         u8         mlid[0x7];
6783         u8         rlid_udp_sport[0x10];
6784
6785         u8         reserved_at_80[0x20];
6786
6787         u8         rmac_47_16[0x20];
6788
6789         u8         rmac_15_0[0x10];
6790         u8         tclass[0x8];
6791         u8         hop_limit[0x8];
6792
6793         u8         reserved_at_e0[0x1];
6794         u8         grh[0x1];
6795         u8         reserved_at_e2[0x2];
6796         u8         src_addr_index[0x8];
6797         u8         flow_label[0x14];
6798
6799         u8         rgid_rip[16][0x8];
6800 };
6801
6802 struct mlx5_ifc_pages_req_event_bits {
6803         u8         reserved_at_0[0x10];
6804         u8         function_id[0x10];
6805
6806         u8         num_pages[0x20];
6807
6808         u8         reserved_at_40[0xa0];
6809 };
6810
6811 struct mlx5_ifc_eqe_bits {
6812         u8         reserved_at_0[0x8];
6813         u8         event_type[0x8];
6814         u8         reserved_at_10[0x8];
6815         u8         event_sub_type[0x8];
6816
6817         u8         reserved_at_20[0xe0];
6818
6819         union mlx5_ifc_event_auto_bits event_data;
6820
6821         u8         reserved_at_1e0[0x10];
6822         u8         signature[0x8];
6823         u8         reserved_at_1f8[0x7];
6824         u8         owner[0x1];
6825 };
6826
6827 enum {
6828         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
6829 };
6830
6831 struct mlx5_ifc_cmd_queue_entry_bits {
6832         u8         type[0x8];
6833         u8         reserved_at_8[0x18];
6834
6835         u8         input_length[0x20];
6836
6837         u8         input_mailbox_pointer_63_32[0x20];
6838
6839         u8         input_mailbox_pointer_31_9[0x17];
6840         u8         reserved_at_77[0x9];
6841
6842         u8         command_input_inline_data[16][0x8];
6843
6844         u8         command_output_inline_data[16][0x8];
6845
6846         u8         output_mailbox_pointer_63_32[0x20];
6847
6848         u8         output_mailbox_pointer_31_9[0x17];
6849         u8         reserved_at_1b7[0x9];
6850
6851         u8         output_length[0x20];
6852
6853         u8         token[0x8];
6854         u8         signature[0x8];
6855         u8         reserved_at_1f0[0x8];
6856         u8         status[0x7];
6857         u8         ownership[0x1];
6858 };
6859
6860 struct mlx5_ifc_cmd_out_bits {
6861         u8         status[0x8];
6862         u8         reserved_at_8[0x18];
6863
6864         u8         syndrome[0x20];
6865
6866         u8         command_output[0x20];
6867 };
6868
6869 struct mlx5_ifc_cmd_in_bits {
6870         u8         opcode[0x10];
6871         u8         reserved_at_10[0x10];
6872
6873         u8         reserved_at_20[0x10];
6874         u8         op_mod[0x10];
6875
6876         u8         command[0][0x20];
6877 };
6878
6879 struct mlx5_ifc_cmd_if_box_bits {
6880         u8         mailbox_data[512][0x8];
6881
6882         u8         reserved_at_1000[0x180];
6883
6884         u8         next_pointer_63_32[0x20];
6885
6886         u8         next_pointer_31_10[0x16];
6887         u8         reserved_at_11b6[0xa];
6888
6889         u8         block_number[0x20];
6890
6891         u8         reserved_at_11e0[0x8];
6892         u8         token[0x8];
6893         u8         ctrl_signature[0x8];
6894         u8         signature[0x8];
6895 };
6896
6897 struct mlx5_ifc_mtt_bits {
6898         u8         ptag_63_32[0x20];
6899
6900         u8         ptag_31_8[0x18];
6901         u8         reserved_at_38[0x6];
6902         u8         wr_en[0x1];
6903         u8         rd_en[0x1];
6904 };
6905
6906 enum {
6907         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
6908         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
6909         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
6910 };
6911
6912 enum {
6913         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
6914         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
6915         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
6916 };
6917
6918 enum {
6919         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
6920         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
6921         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
6922         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
6923         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
6924         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
6925         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
6926         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
6927         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
6928         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
6929         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
6930 };
6931
6932 struct mlx5_ifc_initial_seg_bits {
6933         u8         fw_rev_minor[0x10];
6934         u8         fw_rev_major[0x10];
6935
6936         u8         cmd_interface_rev[0x10];
6937         u8         fw_rev_subminor[0x10];
6938
6939         u8         reserved_at_40[0x40];
6940
6941         u8         cmdq_phy_addr_63_32[0x20];
6942
6943         u8         cmdq_phy_addr_31_12[0x14];
6944         u8         reserved_at_b4[0x2];
6945         u8         nic_interface[0x2];
6946         u8         log_cmdq_size[0x4];
6947         u8         log_cmdq_stride[0x4];
6948
6949         u8         command_doorbell_vector[0x20];
6950
6951         u8         reserved_at_e0[0xf00];
6952
6953         u8         initializing[0x1];
6954         u8         reserved_at_fe1[0x4];
6955         u8         nic_interface_supported[0x3];
6956         u8         reserved_at_fe8[0x18];
6957
6958         struct mlx5_ifc_health_buffer_bits health_buffer;
6959
6960         u8         no_dram_nic_offset[0x20];
6961
6962         u8         reserved_at_1220[0x6e40];
6963
6964         u8         reserved_at_8060[0x1f];
6965         u8         clear_int[0x1];
6966
6967         u8         health_syndrome[0x8];
6968         u8         health_counter[0x18];
6969
6970         u8         reserved_at_80a0[0x17fc0];
6971 };
6972
6973 union mlx5_ifc_ports_control_registers_document_bits {
6974         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6975         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6976         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6977         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6978         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6979         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6980         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6981         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6982         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6983         struct mlx5_ifc_pamp_reg_bits pamp_reg;
6984         struct mlx5_ifc_paos_reg_bits paos_reg;
6985         struct mlx5_ifc_pcap_reg_bits pcap_reg;
6986         struct mlx5_ifc_peir_reg_bits peir_reg;
6987         struct mlx5_ifc_pelc_reg_bits pelc_reg;
6988         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
6989         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
6990         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6991         struct mlx5_ifc_pifr_reg_bits pifr_reg;
6992         struct mlx5_ifc_pipg_reg_bits pipg_reg;
6993         struct mlx5_ifc_plbf_reg_bits plbf_reg;
6994         struct mlx5_ifc_plib_reg_bits plib_reg;
6995         struct mlx5_ifc_plpc_reg_bits plpc_reg;
6996         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
6997         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
6998         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
6999         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7000         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7001         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7002         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7003         struct mlx5_ifc_ppad_reg_bits ppad_reg;
7004         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7005         struct mlx5_ifc_pplm_reg_bits pplm_reg;
7006         struct mlx5_ifc_pplr_reg_bits pplr_reg;
7007         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7008         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7009         struct mlx5_ifc_pspa_reg_bits pspa_reg;
7010         struct mlx5_ifc_ptas_reg_bits ptas_reg;
7011         struct mlx5_ifc_ptys_reg_bits ptys_reg;
7012         struct mlx5_ifc_pude_reg_bits pude_reg;
7013         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7014         struct mlx5_ifc_slrg_reg_bits slrg_reg;
7015         struct mlx5_ifc_sltp_reg_bits sltp_reg;
7016         u8         reserved_at_0[0x60e0];
7017 };
7018
7019 union mlx5_ifc_debug_enhancements_document_bits {
7020         struct mlx5_ifc_health_buffer_bits health_buffer;
7021         u8         reserved_at_0[0x200];
7022 };
7023
7024 union mlx5_ifc_uplink_pci_interface_document_bits {
7025         struct mlx5_ifc_initial_seg_bits initial_seg;
7026         u8         reserved_at_0[0x20060];
7027 };
7028
7029 struct mlx5_ifc_set_flow_table_root_out_bits {
7030         u8         status[0x8];
7031         u8         reserved_at_8[0x18];
7032
7033         u8         syndrome[0x20];
7034
7035         u8         reserved_at_40[0x40];
7036 };
7037
7038 struct mlx5_ifc_set_flow_table_root_in_bits {
7039         u8         opcode[0x10];
7040         u8         reserved_at_10[0x10];
7041
7042         u8         reserved_at_20[0x10];
7043         u8         op_mod[0x10];
7044
7045         u8         reserved_at_40[0x40];
7046
7047         u8         table_type[0x8];
7048         u8         reserved_at_88[0x18];
7049
7050         u8         reserved_at_a0[0x8];
7051         u8         table_id[0x18];
7052
7053         u8         reserved_at_c0[0x140];
7054 };
7055
7056 enum {
7057         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7058 };
7059
7060 struct mlx5_ifc_modify_flow_table_out_bits {
7061         u8         status[0x8];
7062         u8         reserved_at_8[0x18];
7063
7064         u8         syndrome[0x20];
7065
7066         u8         reserved_at_40[0x40];
7067 };
7068
7069 struct mlx5_ifc_modify_flow_table_in_bits {
7070         u8         opcode[0x10];
7071         u8         reserved_at_10[0x10];
7072
7073         u8         reserved_at_20[0x10];
7074         u8         op_mod[0x10];
7075
7076         u8         reserved_at_40[0x20];
7077
7078         u8         reserved_at_60[0x10];
7079         u8         modify_field_select[0x10];
7080
7081         u8         table_type[0x8];
7082         u8         reserved_at_88[0x18];
7083
7084         u8         reserved_at_a0[0x8];
7085         u8         table_id[0x18];
7086
7087         u8         reserved_at_c0[0x4];
7088         u8         table_miss_mode[0x4];
7089         u8         reserved_at_c8[0x18];
7090
7091         u8         reserved_at_e0[0x8];
7092         u8         table_miss_id[0x18];
7093
7094         u8         reserved_at_100[0x100];
7095 };
7096
7097 #endif /* MLX5_IFC_H */