include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  71         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  72         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  73         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  74         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  75         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  76         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  77         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  78         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  79         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  80         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  81         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  82         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  83         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  84         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  85         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  86         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  87         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  88         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  89         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  90         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  91         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  92         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  93         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
  94         MLX5_CMD_OP_CREATE_QP                     = 0x500,
  95         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
  96         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
  97         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
  98         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
  99         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 100         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 101         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 102         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 103         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 104         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 105         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 106         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 107         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 108         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 109         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 110         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 111         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 112         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 113         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 114         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 115         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 116         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 117         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 118         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 119         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 120         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 121         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 122         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 123         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 124         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 125         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 126         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 127         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 128         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 129         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 130         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 131         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 132         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 133         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 134         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 135         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 136         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 137         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 138         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 139         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 140         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 141         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 142         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 143         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 144         MLX5_CMD_OP_DETTACH_FROM_MCG              = 0x807,
 145         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 146         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 147         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 148         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 149         MLX5_CMD_OP_NOP                           = 0x80d,
 150         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 151         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 152         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 153         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 154         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 155         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 156         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 157         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 158         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 159         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 160         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 161         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 162         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 163         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 164         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 165         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 166         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 167         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 168         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 169         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 170         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 171         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 172         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 173         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 174         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 175         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 176         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 177         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 178         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 179         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 180         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 181         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 182         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 183         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 184         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 185         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 186         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 187         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 188         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 189         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 190         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 191         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 192         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 193         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 194         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 195         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 196         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938
 197 };
 198
 199 struct mlx5_ifc_flow_table_fields_supported_bits {
 200         u8         outer_dmac[0x1];
 201         u8         outer_smac[0x1];
 202         u8         outer_ether_type[0x1];
 203         u8         reserved_0[0x1];
 204         u8         outer_first_prio[0x1];
 205         u8         outer_first_cfi[0x1];
 206         u8         outer_first_vid[0x1];
 207         u8         reserved_1[0x1];
 208         u8         outer_second_prio[0x1];
 209         u8         outer_second_cfi[0x1];
 210         u8         outer_second_vid[0x1];
 211         u8         reserved_2[0x1];
 212         u8         outer_sip[0x1];
 213         u8         outer_dip[0x1];
 214         u8         outer_frag[0x1];
 215         u8         outer_ip_protocol[0x1];
 216         u8         outer_ip_ecn[0x1];
 217         u8         outer_ip_dscp[0x1];
 218         u8         outer_udp_sport[0x1];
 219         u8         outer_udp_dport[0x1];
 220         u8         outer_tcp_sport[0x1];
 221         u8         outer_tcp_dport[0x1];
 222         u8         outer_tcp_flags[0x1];
 223         u8         outer_gre_protocol[0x1];
 224         u8         outer_gre_key[0x1];
 225         u8         outer_vxlan_vni[0x1];
 226         u8         reserved_3[0x5];
 227         u8         source_eswitch_port[0x1];
 228
 229         u8         inner_dmac[0x1];
 230         u8         inner_smac[0x1];
 231         u8         inner_ether_type[0x1];
 232         u8         reserved_4[0x1];
 233         u8         inner_first_prio[0x1];
 234         u8         inner_first_cfi[0x1];
 235         u8         inner_first_vid[0x1];
 236         u8         reserved_5[0x1];
 237         u8         inner_second_prio[0x1];
 238         u8         inner_second_cfi[0x1];
 239         u8         inner_second_vid[0x1];
 240         u8         reserved_6[0x1];
 241         u8         inner_sip[0x1];
 242         u8         inner_dip[0x1];
 243         u8         inner_frag[0x1];
 244         u8         inner_ip_protocol[0x1];
 245         u8         inner_ip_ecn[0x1];
 246         u8         inner_ip_dscp[0x1];
 247         u8         inner_udp_sport[0x1];
 248         u8         inner_udp_dport[0x1];
 249         u8         inner_tcp_sport[0x1];
 250         u8         inner_tcp_dport[0x1];
 251         u8         inner_tcp_flags[0x1];
 252         u8         reserved_7[0x9];
 253
 254         u8         reserved_8[0x40];
 255 };
 256
 257 struct mlx5_ifc_flow_table_prop_layout_bits {
 258         u8         ft_support[0x1];
 259         u8         reserved_0[0x1f];
 260
 261         u8         reserved_1[0x2];
 262         u8         log_max_ft_size[0x6];
 263         u8         reserved_2[0x10];
 264         u8         max_ft_level[0x8];
 265
 266         u8         reserved_3[0x20];
 267
 268         u8         reserved_4[0x18];
 269         u8         log_max_ft_num[0x8];
 270
 271         u8         reserved_5[0x18];
 272         u8         log_max_destination[0x8];
 273
 274         u8         reserved_6[0x18];
 275         u8         log_max_flow[0x8];
 276
 277         u8         reserved_7[0x40];
 278
 279         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 280
 281         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 282 };
 283
 284 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 285         u8         send[0x1];
 286         u8         receive[0x1];
 287         u8         write[0x1];
 288         u8         read[0x1];
 289         u8         reserved_0[0x1];
 290         u8         srq_receive[0x1];
 291         u8         reserved_1[0x1a];
 292 };
 293
 294 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 295         u8         smac_47_16[0x20];
 296
 297         u8         smac_15_0[0x10];
 298         u8         ethertype[0x10];
 299
 300         u8         dmac_47_16[0x20];
 301
 302         u8         dmac_15_0[0x10];
 303         u8         first_prio[0x3];
 304         u8         first_cfi[0x1];
 305         u8         first_vid[0xc];
 306
 307         u8         ip_protocol[0x8];
 308         u8         ip_dscp[0x6];
 309         u8         ip_ecn[0x2];
 310         u8         vlan_tag[0x1];
 311         u8         reserved_0[0x1];
 312         u8         frag[0x1];
 313         u8         reserved_1[0x4];
 314         u8         tcp_flags[0x9];
 315
 316         u8         tcp_sport[0x10];
 317         u8         tcp_dport[0x10];
 318
 319         u8         reserved_2[0x20];
 320
 321         u8         udp_sport[0x10];
 322         u8         udp_dport[0x10];
 323
 324         u8         src_ip[4][0x20];
 325
 326         u8         dst_ip[4][0x20];
 327 };
 328
 329 struct mlx5_ifc_fte_match_set_misc_bits {
 330         u8         reserved_0[0x20];
 331
 332         u8         reserved_1[0x10];
 333         u8         source_port[0x10];
 334
 335         u8         outer_second_prio[0x3];
 336         u8         outer_second_cfi[0x1];
 337         u8         outer_second_vid[0xc];
 338         u8         inner_second_prio[0x3];
 339         u8         inner_second_cfi[0x1];
 340         u8         inner_second_vid[0xc];
 341
 342         u8         outer_second_vlan_tag[0x1];
 343         u8         inner_second_vlan_tag[0x1];
 344         u8         reserved_2[0xe];
 345         u8         gre_protocol[0x10];
 346
 347         u8         gre_key_h[0x18];
 348         u8         gre_key_l[0x8];
 349
 350         u8         vxlan_vni[0x18];
 351         u8         reserved_3[0x8];
 352
 353         u8         reserved_4[0x20];
 354
 355         u8         reserved_5[0xc];
 356         u8         outer_ipv6_flow_label[0x14];
 357
 358         u8         reserved_6[0xc];
 359         u8         inner_ipv6_flow_label[0x14];
 360
 361         u8         reserved_7[0xe0];
 362 };
 363
 364 struct mlx5_ifc_cmd_pas_bits {
 365         u8         pa_h[0x20];
 366
 367         u8         pa_l[0x14];
 368         u8         reserved_0[0xc];
 369 };
 370
 371 struct mlx5_ifc_uint64_bits {
 372         u8         hi[0x20];
 373
 374         u8         lo[0x20];
 375 };
 376
 377 enum {
 378         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 379         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 380         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 381         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 382         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 383         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 384         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 385         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 386         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 387         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 388 };
 389
 390 struct mlx5_ifc_ads_bits {
 391         u8         fl[0x1];
 392         u8         free_ar[0x1];
 393         u8         reserved_0[0xe];
 394         u8         pkey_index[0x10];
 395
 396         u8         reserved_1[0x8];
 397         u8         grh[0x1];
 398         u8         mlid[0x7];
 399         u8         rlid[0x10];
 400
 401         u8         ack_timeout[0x5];
 402         u8         reserved_2[0x3];
 403         u8         src_addr_index[0x8];
 404         u8         reserved_3[0x4];
 405         u8         stat_rate[0x4];
 406         u8         hop_limit[0x8];
 407
 408         u8         reserved_4[0x4];
 409         u8         tclass[0x8];
 410         u8         flow_label[0x14];
 411
 412         u8         rgid_rip[16][0x8];
 413
 414         u8         reserved_5[0x4];
 415         u8         f_dscp[0x1];
 416         u8         f_ecn[0x1];
 417         u8         reserved_6[0x1];
 418         u8         f_eth_prio[0x1];
 419         u8         ecn[0x2];
 420         u8         dscp[0x6];
 421         u8         udp_sport[0x10];
 422
 423         u8         dei_cfi[0x1];
 424         u8         eth_prio[0x3];
 425         u8         sl[0x4];
 426         u8         port[0x8];
 427         u8         rmac_47_32[0x10];
 428
 429         u8         rmac_31_0[0x20];
 430 };
 431
 432 struct mlx5_ifc_flow_table_nic_cap_bits {
 433         u8         reserved_0[0x200];
 434
 435         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 436
 437         u8         reserved_1[0x200];
 438
 439         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 440
 441         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 442
 443         u8         reserved_2[0x200];
 444
 445         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 446
 447         u8         reserved_3[0x7200];
 448 };
 449
 450 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 451         u8     reserved_0[0x200];
 452
 453         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 454
 455         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 456
 457         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 458
 459         u8      reserved_1[0x7800];
 460 };
 461
 462 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 463         u8         csum_cap[0x1];
 464         u8         vlan_cap[0x1];
 465         u8         lro_cap[0x1];
 466         u8         lro_psh_flag[0x1];
 467         u8         lro_time_stamp[0x1];
 468         u8         reserved_0[0x3];
 469         u8         self_lb_en_modifiable[0x1];
 470         u8         reserved_1[0x2];
 471         u8         max_lso_cap[0x5];
 472         u8         reserved_2[0x4];
 473         u8         rss_ind_tbl_cap[0x4];
 474         u8         reserved_3[0x3];
 475         u8         tunnel_lso_const_out_ip_id[0x1];
 476         u8         reserved_4[0x2];
 477         u8         tunnel_statless_gre[0x1];
 478         u8         tunnel_stateless_vxlan[0x1];
 479
 480         u8         reserved_5[0x20];
 481
 482         u8         reserved_6[0x10];
 483         u8         lro_min_mss_size[0x10];
 484
 485         u8         reserved_7[0x120];
 486
 487         u8         lro_timer_supported_periods[4][0x20];
 488
 489         u8         reserved_8[0x600];
 490 };
 491
 492 struct mlx5_ifc_roce_cap_bits {
 493         u8         roce_apm[0x1];
 494         u8         reserved_0[0x1f];
 495
 496         u8         reserved_1[0x60];
 497
 498         u8         reserved_2[0xc];
 499         u8         l3_type[0x4];
 500         u8         reserved_3[0x8];
 501         u8         roce_version[0x8];
 502
 503         u8         reserved_4[0x10];
 504         u8         r_roce_dest_udp_port[0x10];
 505
 506         u8         r_roce_max_src_udp_port[0x10];
 507         u8         r_roce_min_src_udp_port[0x10];
 508
 509         u8         reserved_5[0x10];
 510         u8         roce_address_table_size[0x10];
 511
 512         u8         reserved_6[0x700];
 513 };
 514
 515 enum {
 516         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 517         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 518         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 519         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 520         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 521         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 522         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 523         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 524         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 525 };
 526
 527 enum {
 528         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 529         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 530         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 531         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 532         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 533         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 534         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 535         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 536         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 537 };
 538
 539 struct mlx5_ifc_atomic_caps_bits {
 540         u8         reserved_0[0x40];
 541
 542         u8         atomic_req_endianness[0x1];
 543         u8         reserved_1[0x1f];
 544
 545         u8         reserved_2[0x20];
 546
 547         u8         reserved_3[0x10];
 548         u8         atomic_operations[0x10];
 549
 550         u8         reserved_4[0x10];
 551         u8         atomic_size_qp[0x10];
 552
 553         u8         reserved_5[0x10];
 554         u8         atomic_size_dc[0x10];
 555
 556         u8         reserved_6[0x720];
 557 };
 558
 559 struct mlx5_ifc_odp_cap_bits {
 560         u8         reserved_0[0x40];
 561
 562         u8         sig[0x1];
 563         u8         reserved_1[0x1f];
 564
 565         u8         reserved_2[0x20];
 566
 567         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 568
 569         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 570
 571         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 572
 573         u8         reserved_3[0x720];
 574 };
 575
 576 enum {
 577         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 578         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 579         MLX5_WQ_TYPE_STRQ         = 0x2,
 580 };
 581
 582 enum {
 583         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 584         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 585 };
 586
 587 enum {
 588         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 589         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 590         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 591         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 592         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 593 };
 594
 595 enum {
 596         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 597         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 598         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 599         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 600         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 601         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 602 };
 603
 604 enum {
 605         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 606         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 607 };
 608
 609 enum {
 610         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 611         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 612         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 613 };
 614
 615 enum {
 616         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 617         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 618 };
 619
 620 struct mlx5_ifc_cmd_hca_cap_bits {
 621         u8         reserved_0[0x80];
 622
 623         u8         log_max_srq_sz[0x8];
 624         u8         log_max_qp_sz[0x8];
 625         u8         reserved_1[0xb];
 626         u8         log_max_qp[0x5];
 627
 628         u8         reserved_2[0xb];
 629         u8         log_max_srq[0x5];
 630         u8         reserved_3[0x10];
 631
 632         u8         reserved_4[0x8];
 633         u8         log_max_cq_sz[0x8];
 634         u8         reserved_5[0xb];
 635         u8         log_max_cq[0x5];
 636
 637         u8         log_max_eq_sz[0x8];
 638         u8         reserved_6[0x2];
 639         u8         log_max_mkey[0x6];
 640         u8         reserved_7[0xc];
 641         u8         log_max_eq[0x4];
 642
 643         u8         max_indirection[0x8];
 644         u8         reserved_8[0x1];
 645         u8         log_max_mrw_sz[0x7];
 646         u8         reserved_9[0x2];
 647         u8         log_max_bsf_list_size[0x6];
 648         u8         reserved_10[0x2];
 649         u8         log_max_klm_list_size[0x6];
 650
 651         u8         reserved_11[0xa];
 652         u8         log_max_ra_req_dc[0x6];
 653         u8         reserved_12[0xa];
 654         u8         log_max_ra_res_dc[0x6];
 655
 656         u8         reserved_13[0xa];
 657         u8         log_max_ra_req_qp[0x6];
 658         u8         reserved_14[0xa];
 659         u8         log_max_ra_res_qp[0x6];
 660
 661         u8         pad_cap[0x1];
 662         u8         cc_query_allowed[0x1];
 663         u8         cc_modify_allowed[0x1];
 664         u8         reserved_15[0xd];
 665         u8         gid_table_size[0x10];
 666
 667         u8         out_of_seq_cnt[0x1];
 668         u8         vport_counters[0x1];
 669         u8         reserved_16[0x4];
 670         u8         max_qp_cnt[0xa];
 671         u8         pkey_table_size[0x10];
 672
 673         u8         vport_group_manager[0x1];
 674         u8         vhca_group_manager[0x1];
 675         u8         ib_virt[0x1];
 676         u8         eth_virt[0x1];
 677         u8         reserved_17[0x1];
 678         u8         ets[0x1];
 679         u8         nic_flow_table[0x1];
 680         u8         eswitch_flow_table[0x1];
 681         u8         early_vf_enable;
 682         u8         reserved_18[0x2];
 683         u8         local_ca_ack_delay[0x5];
 684         u8         reserved_19[0x6];
 685         u8         port_type[0x2];
 686         u8         num_ports[0x8];
 687
 688         u8         reserved_20[0x3];
 689         u8         log_max_msg[0x5];
 690         u8         reserved_21[0x18];
 691
 692         u8         stat_rate_support[0x10];
 693         u8         reserved_22[0xc];
 694         u8         cqe_version[0x4];
 695
 696         u8         compact_address_vector[0x1];
 697         u8         reserved_23[0xe];
 698         u8         drain_sigerr[0x1];
 699         u8         cmdif_checksum[0x2];
 700         u8         sigerr_cqe[0x1];
 701         u8         reserved_24[0x1];
 702         u8         wq_signature[0x1];
 703         u8         sctr_data_cqe[0x1];
 704         u8         reserved_25[0x1];
 705         u8         sho[0x1];
 706         u8         tph[0x1];
 707         u8         rf[0x1];
 708         u8         dct[0x1];
 709         u8         reserved_26[0x1];
 710         u8         eth_net_offloads[0x1];
 711         u8         roce[0x1];
 712         u8         atomic[0x1];
 713         u8         reserved_27[0x1];
 714
 715         u8         cq_oi[0x1];
 716         u8         cq_resize[0x1];
 717         u8         cq_moderation[0x1];
 718         u8         reserved_28[0x3];
 719         u8         cq_eq_remap[0x1];
 720         u8         pg[0x1];
 721         u8         block_lb_mc[0x1];
 722         u8         reserved_29[0x1];
 723         u8         scqe_break_moderation[0x1];
 724         u8         reserved_30[0x1];
 725         u8         cd[0x1];
 726         u8         reserved_31[0x1];
 727         u8         apm[0x1];
 728         u8         reserved_32[0x7];
 729         u8         qkv[0x1];
 730         u8         pkv[0x1];
 731         u8         reserved_33[0x4];
 732         u8         xrc[0x1];
 733         u8         ud[0x1];
 734         u8         uc[0x1];
 735         u8         rc[0x1];
 736
 737         u8         reserved_34[0xa];
 738         u8         uar_sz[0x6];
 739         u8         reserved_35[0x8];
 740         u8         log_pg_sz[0x8];
 741
 742         u8         bf[0x1];
 743         u8         reserved_36[0x1];
 744         u8         pad_tx_eth_packet[0x1];
 745         u8         reserved_37[0x8];
 746         u8         log_bf_reg_size[0x5];
 747         u8         reserved_38[0x10];
 748
 749         u8         reserved_39[0x10];
 750         u8         max_wqe_sz_sq[0x10];
 751
 752         u8         reserved_40[0x10];
 753         u8         max_wqe_sz_rq[0x10];
 754
 755         u8         reserved_41[0x10];
 756         u8         max_wqe_sz_sq_dc[0x10];
 757
 758         u8         reserved_42[0x7];
 759         u8         max_qp_mcg[0x19];
 760
 761         u8         reserved_43[0x18];
 762         u8         log_max_mcg[0x8];
 763
 764         u8         reserved_44[0x3];
 765         u8         log_max_transport_domain[0x5];
 766         u8         reserved_45[0x3];
 767         u8         log_max_pd[0x5];
 768         u8         reserved_46[0xb];
 769         u8         log_max_xrcd[0x5];
 770
 771         u8         reserved_47[0x20];
 772
 773         u8         reserved_48[0x3];
 774         u8         log_max_rq[0x5];
 775         u8         reserved_49[0x3];
 776         u8         log_max_sq[0x5];
 777         u8         reserved_50[0x3];
 778         u8         log_max_tir[0x5];
 779         u8         reserved_51[0x3];
 780         u8         log_max_tis[0x5];
 781
 782         u8         basic_cyclic_rcv_wqe[0x1];
 783         u8         reserved_52[0x2];
 784         u8         log_max_rmp[0x5];
 785         u8         reserved_53[0x3];
 786         u8         log_max_rqt[0x5];
 787         u8         reserved_54[0x3];
 788         u8         log_max_rqt_size[0x5];
 789         u8         reserved_55[0x3];
 790         u8         log_max_tis_per_sq[0x5];
 791
 792         u8         reserved_56[0x3];
 793         u8         log_max_stride_sz_rq[0x5];
 794         u8         reserved_57[0x3];
 795         u8         log_min_stride_sz_rq[0x5];
 796         u8         reserved_58[0x3];
 797         u8         log_max_stride_sz_sq[0x5];
 798         u8         reserved_59[0x3];
 799         u8         log_min_stride_sz_sq[0x5];
 800
 801         u8         reserved_60[0x1b];
 802         u8         log_max_wq_sz[0x5];
 803
 804         u8         nic_vport_change_event[0x1];
 805         u8         reserved_61[0xa];
 806         u8         log_max_vlan_list[0x5];
 807         u8         reserved_62[0x3];
 808         u8         log_max_current_mc_list[0x5];
 809         u8         reserved_63[0x3];
 810         u8         log_max_current_uc_list[0x5];
 811
 812         u8         reserved_64[0x80];
 813
 814         u8         reserved_65[0x3];
 815         u8         log_max_l2_table[0x5];
 816         u8         reserved_66[0x8];
 817         u8         log_uar_page_sz[0x10];
 818
 819         u8         reserved_67[0xe0];
 820
 821         u8         reserved_68[0x1f];
 822         u8         cqe_zip[0x1];
 823
 824         u8         cqe_zip_timeout[0x10];
 825         u8         cqe_zip_max_num[0x10];
 826
 827         u8         reserved_69[0x220];
 828 };
 829
 830 enum mlx5_flow_destination_type {
 831         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
 832         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
 833         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
 834 };
 835
 836 struct mlx5_ifc_dest_format_struct_bits {
 837         u8         destination_type[0x8];
 838         u8         destination_id[0x18];
 839
 840         u8         reserved_0[0x20];
 841 };
 842
 843 struct mlx5_ifc_fte_match_param_bits {
 844         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
 845
 846         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
 847
 848         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 849
 850         u8         reserved_0[0xa00];
 851 };
 852
 853 enum {
 854         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
 855         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
 856         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
 857         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
 858         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
 859 };
 860
 861 struct mlx5_ifc_rx_hash_field_select_bits {
 862         u8         l3_prot_type[0x1];
 863         u8         l4_prot_type[0x1];
 864         u8         selected_fields[0x1e];
 865 };
 866
 867 enum {
 868         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
 869         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
 870 };
 871
 872 enum {
 873         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
 874         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
 875 };
 876
 877 struct mlx5_ifc_wq_bits {
 878         u8         wq_type[0x4];
 879         u8         wq_signature[0x1];
 880         u8         end_padding_mode[0x2];
 881         u8         cd_slave[0x1];
 882         u8         reserved_0[0x18];
 883
 884         u8         hds_skip_first_sge[0x1];
 885         u8         log2_hds_buf_size[0x3];
 886         u8         reserved_1[0x7];
 887         u8         page_offset[0x5];
 888         u8         lwm[0x10];
 889
 890         u8         reserved_2[0x8];
 891         u8         pd[0x18];
 892
 893         u8         reserved_3[0x8];
 894         u8         uar_page[0x18];
 895
 896         u8         dbr_addr[0x40];
 897
 898         u8         hw_counter[0x20];
 899
 900         u8         sw_counter[0x20];
 901
 902         u8         reserved_4[0xc];
 903         u8         log_wq_stride[0x4];
 904         u8         reserved_5[0x3];
 905         u8         log_wq_pg_sz[0x5];
 906         u8         reserved_6[0x3];
 907         u8         log_wq_sz[0x5];
 908
 909         u8         reserved_7[0x4e0];
 910
 911         struct mlx5_ifc_cmd_pas_bits pas[0];
 912 };
 913
 914 struct mlx5_ifc_rq_num_bits {
 915         u8         reserved_0[0x8];
 916         u8         rq_num[0x18];
 917 };
 918
 919 struct mlx5_ifc_mac_address_layout_bits {
 920         u8         reserved_0[0x10];
 921         u8         mac_addr_47_32[0x10];
 922
 923         u8         mac_addr_31_0[0x20];
 924 };
 925
 926 struct mlx5_ifc_vlan_layout_bits {
 927         u8         reserved_0[0x14];
 928         u8         vlan[0x0c];
 929
 930         u8         reserved_1[0x20];
 931 };
 932
 933 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
 934         u8         reserved_0[0xa0];
 935
 936         u8         min_time_between_cnps[0x20];
 937
 938         u8         reserved_1[0x12];
 939         u8         cnp_dscp[0x6];
 940         u8         reserved_2[0x5];
 941         u8         cnp_802p_prio[0x3];
 942
 943         u8         reserved_3[0x720];
 944 };
 945
 946 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
 947         u8         reserved_0[0x60];
 948
 949         u8         reserved_1[0x4];
 950         u8         clamp_tgt_rate[0x1];
 951         u8         reserved_2[0x3];
 952         u8         clamp_tgt_rate_after_time_inc[0x1];
 953         u8         reserved_3[0x17];
 954
 955         u8         reserved_4[0x20];
 956
 957         u8         rpg_time_reset[0x20];
 958
 959         u8         rpg_byte_reset[0x20];
 960
 961         u8         rpg_threshold[0x20];
 962
 963         u8         rpg_max_rate[0x20];
 964
 965         u8         rpg_ai_rate[0x20];
 966
 967         u8         rpg_hai_rate[0x20];
 968
 969         u8         rpg_gd[0x20];
 970
 971         u8         rpg_min_dec_fac[0x20];
 972
 973         u8         rpg_min_rate[0x20];
 974
 975         u8         reserved_5[0xe0];
 976
 977         u8         rate_to_set_on_first_cnp[0x20];
 978
 979         u8         dce_tcp_g[0x20];
 980
 981         u8         dce_tcp_rtt[0x20];
 982
 983         u8         rate_reduce_monitor_period[0x20];
 984
 985         u8         reserved_6[0x20];
 986
 987         u8         initial_alpha_value[0x20];
 988
 989         u8         reserved_7[0x4a0];
 990 };
 991
 992 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
 993         u8         reserved_0[0x80];
 994
 995         u8         rppp_max_rps[0x20];
 996
 997         u8         rpg_time_reset[0x20];
 998
 999         u8         rpg_byte_reset[0x20];
1000
1001         u8         rpg_threshold[0x20];
1002
1003         u8         rpg_max_rate[0x20];
1004
1005         u8         rpg_ai_rate[0x20];
1006
1007         u8         rpg_hai_rate[0x20];
1008
1009         u8         rpg_gd[0x20];
1010
1011         u8         rpg_min_dec_fac[0x20];
1012
1013         u8         rpg_min_rate[0x20];
1014
1015         u8         reserved_1[0x640];
1016 };
1017
1018 enum {
1019         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1020         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1021         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1022 };
1023
1024 struct mlx5_ifc_resize_field_select_bits {
1025         u8         resize_field_select[0x20];
1026 };
1027
1028 enum {
1029         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1030         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1031         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1032         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1033 };
1034
1035 struct mlx5_ifc_modify_field_select_bits {
1036         u8         modify_field_select[0x20];
1037 };
1038
1039 struct mlx5_ifc_field_select_r_roce_np_bits {
1040         u8         field_select_r_roce_np[0x20];
1041 };
1042
1043 struct mlx5_ifc_field_select_r_roce_rp_bits {
1044         u8         field_select_r_roce_rp[0x20];
1045 };
1046
1047 enum {
1048         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1049         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1050         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1051         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1052         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1053         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1054         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1055         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1056         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1057         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1058 };
1059
1060 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1061         u8         field_select_8021qaurp[0x20];
1062 };
1063
1064 struct mlx5_ifc_phys_layer_cntrs_bits {
1065         u8         time_since_last_clear_high[0x20];
1066
1067         u8         time_since_last_clear_low[0x20];
1068
1069         u8         symbol_errors_high[0x20];
1070
1071         u8         symbol_errors_low[0x20];
1072
1073         u8         sync_headers_errors_high[0x20];
1074
1075         u8         sync_headers_errors_low[0x20];
1076
1077         u8         edpl_bip_errors_lane0_high[0x20];
1078
1079         u8         edpl_bip_errors_lane0_low[0x20];
1080
1081         u8         edpl_bip_errors_lane1_high[0x20];
1082
1083         u8         edpl_bip_errors_lane1_low[0x20];
1084
1085         u8         edpl_bip_errors_lane2_high[0x20];
1086
1087         u8         edpl_bip_errors_lane2_low[0x20];
1088
1089         u8         edpl_bip_errors_lane3_high[0x20];
1090
1091         u8         edpl_bip_errors_lane3_low[0x20];
1092
1093         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1094
1095         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1096
1097         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1098
1099         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1100
1101         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1102
1103         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1104
1105         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1106
1107         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1108
1109         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1110
1111         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1112
1113         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1114
1115         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1116
1117         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1118
1119         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1120
1121         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1122
1123         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1124
1125         u8         rs_fec_corrected_blocks_high[0x20];
1126
1127         u8         rs_fec_corrected_blocks_low[0x20];
1128
1129         u8         rs_fec_uncorrectable_blocks_high[0x20];
1130
1131         u8         rs_fec_uncorrectable_blocks_low[0x20];
1132
1133         u8         rs_fec_no_errors_blocks_high[0x20];
1134
1135         u8         rs_fec_no_errors_blocks_low[0x20];
1136
1137         u8         rs_fec_single_error_blocks_high[0x20];
1138
1139         u8         rs_fec_single_error_blocks_low[0x20];
1140
1141         u8         rs_fec_corrected_symbols_total_high[0x20];
1142
1143         u8         rs_fec_corrected_symbols_total_low[0x20];
1144
1145         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1146
1147         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1148
1149         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1150
1151         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1152
1153         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1154
1155         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1156
1157         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1158
1159         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1160
1161         u8         link_down_events[0x20];
1162
1163         u8         successful_recovery_events[0x20];
1164
1165         u8         reserved_0[0x180];
1166 };
1167
1168 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1169         u8         transmit_queue_high[0x20];
1170
1171         u8         transmit_queue_low[0x20];
1172
1173         u8         reserved_0[0x780];
1174 };
1175
1176 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1177         u8         rx_octets_high[0x20];
1178
1179         u8         rx_octets_low[0x20];
1180
1181         u8         reserved_0[0xc0];
1182
1183         u8         rx_frames_high[0x20];
1184
1185         u8         rx_frames_low[0x20];
1186
1187         u8         tx_octets_high[0x20];
1188
1189         u8         tx_octets_low[0x20];
1190
1191         u8         reserved_1[0xc0];
1192
1193         u8         tx_frames_high[0x20];
1194
1195         u8         tx_frames_low[0x20];
1196
1197         u8         rx_pause_high[0x20];
1198
1199         u8         rx_pause_low[0x20];
1200
1201         u8         rx_pause_duration_high[0x20];
1202
1203         u8         rx_pause_duration_low[0x20];
1204
1205         u8         tx_pause_high[0x20];
1206
1207         u8         tx_pause_low[0x20];
1208
1209         u8         tx_pause_duration_high[0x20];
1210
1211         u8         tx_pause_duration_low[0x20];
1212
1213         u8         rx_pause_transition_high[0x20];
1214
1215         u8         rx_pause_transition_low[0x20];
1216
1217         u8         reserved_2[0x400];
1218 };
1219
1220 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1221         u8         port_transmit_wait_high[0x20];
1222
1223         u8         port_transmit_wait_low[0x20];
1224
1225         u8         reserved_0[0x780];
1226 };
1227
1228 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1229         u8         dot3stats_alignment_errors_high[0x20];
1230
1231         u8         dot3stats_alignment_errors_low[0x20];
1232
1233         u8         dot3stats_fcs_errors_high[0x20];
1234
1235         u8         dot3stats_fcs_errors_low[0x20];
1236
1237         u8         dot3stats_single_collision_frames_high[0x20];
1238
1239         u8         dot3stats_single_collision_frames_low[0x20];
1240
1241         u8         dot3stats_multiple_collision_frames_high[0x20];
1242
1243         u8         dot3stats_multiple_collision_frames_low[0x20];
1244
1245         u8         dot3stats_sqe_test_errors_high[0x20];
1246
1247         u8         dot3stats_sqe_test_errors_low[0x20];
1248
1249         u8         dot3stats_deferred_transmissions_high[0x20];
1250
1251         u8         dot3stats_deferred_transmissions_low[0x20];
1252
1253         u8         dot3stats_late_collisions_high[0x20];
1254
1255         u8         dot3stats_late_collisions_low[0x20];
1256
1257         u8         dot3stats_excessive_collisions_high[0x20];
1258
1259         u8         dot3stats_excessive_collisions_low[0x20];
1260
1261         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1262
1263         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1264
1265         u8         dot3stats_carrier_sense_errors_high[0x20];
1266
1267         u8         dot3stats_carrier_sense_errors_low[0x20];
1268
1269         u8         dot3stats_frame_too_longs_high[0x20];
1270
1271         u8         dot3stats_frame_too_longs_low[0x20];
1272
1273         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1274
1275         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1276
1277         u8         dot3stats_symbol_errors_high[0x20];
1278
1279         u8         dot3stats_symbol_errors_low[0x20];
1280
1281         u8         dot3control_in_unknown_opcodes_high[0x20];
1282
1283         u8         dot3control_in_unknown_opcodes_low[0x20];
1284
1285         u8         dot3in_pause_frames_high[0x20];
1286
1287         u8         dot3in_pause_frames_low[0x20];
1288
1289         u8         dot3out_pause_frames_high[0x20];
1290
1291         u8         dot3out_pause_frames_low[0x20];
1292
1293         u8         reserved_0[0x3c0];
1294 };
1295
1296 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1297         u8         ether_stats_drop_events_high[0x20];
1298
1299         u8         ether_stats_drop_events_low[0x20];
1300
1301         u8         ether_stats_octets_high[0x20];
1302
1303         u8         ether_stats_octets_low[0x20];
1304
1305         u8         ether_stats_pkts_high[0x20];
1306
1307         u8         ether_stats_pkts_low[0x20];
1308
1309         u8         ether_stats_broadcast_pkts_high[0x20];
1310
1311         u8         ether_stats_broadcast_pkts_low[0x20];
1312
1313         u8         ether_stats_multicast_pkts_high[0x20];
1314
1315         u8         ether_stats_multicast_pkts_low[0x20];
1316
1317         u8         ether_stats_crc_align_errors_high[0x20];
1318
1319         u8         ether_stats_crc_align_errors_low[0x20];
1320
1321         u8         ether_stats_undersize_pkts_high[0x20];
1322
1323         u8         ether_stats_undersize_pkts_low[0x20];
1324
1325         u8         ether_stats_oversize_pkts_high[0x20];
1326
1327         u8         ether_stats_oversize_pkts_low[0x20];
1328
1329         u8         ether_stats_fragments_high[0x20];
1330
1331         u8         ether_stats_fragments_low[0x20];
1332
1333         u8         ether_stats_jabbers_high[0x20];
1334
1335         u8         ether_stats_jabbers_low[0x20];
1336
1337         u8         ether_stats_collisions_high[0x20];
1338
1339         u8         ether_stats_collisions_low[0x20];
1340
1341         u8         ether_stats_pkts64octets_high[0x20];
1342
1343         u8         ether_stats_pkts64octets_low[0x20];
1344
1345         u8         ether_stats_pkts65to127octets_high[0x20];
1346
1347         u8         ether_stats_pkts65to127octets_low[0x20];
1348
1349         u8         ether_stats_pkts128to255octets_high[0x20];
1350
1351         u8         ether_stats_pkts128to255octets_low[0x20];
1352
1353         u8         ether_stats_pkts256to511octets_high[0x20];
1354
1355         u8         ether_stats_pkts256to511octets_low[0x20];
1356
1357         u8         ether_stats_pkts512to1023octets_high[0x20];
1358
1359         u8         ether_stats_pkts512to1023octets_low[0x20];
1360
1361         u8         ether_stats_pkts1024to1518octets_high[0x20];
1362
1363         u8         ether_stats_pkts1024to1518octets_low[0x20];
1364
1365         u8         ether_stats_pkts1519to2047octets_high[0x20];
1366
1367         u8         ether_stats_pkts1519to2047octets_low[0x20];
1368
1369         u8         ether_stats_pkts2048to4095octets_high[0x20];
1370
1371         u8         ether_stats_pkts2048to4095octets_low[0x20];
1372
1373         u8         ether_stats_pkts4096to8191octets_high[0x20];
1374
1375         u8         ether_stats_pkts4096to8191octets_low[0x20];
1376
1377         u8         ether_stats_pkts8192to10239octets_high[0x20];
1378
1379         u8         ether_stats_pkts8192to10239octets_low[0x20];
1380
1381         u8         reserved_0[0x280];
1382 };
1383
1384 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1385         u8         if_in_octets_high[0x20];
1386
1387         u8         if_in_octets_low[0x20];
1388
1389         u8         if_in_ucast_pkts_high[0x20];
1390
1391         u8         if_in_ucast_pkts_low[0x20];
1392
1393         u8         if_in_discards_high[0x20];
1394
1395         u8         if_in_discards_low[0x20];
1396
1397         u8         if_in_errors_high[0x20];
1398
1399         u8         if_in_errors_low[0x20];
1400
1401         u8         if_in_unknown_protos_high[0x20];
1402
1403         u8         if_in_unknown_protos_low[0x20];
1404
1405         u8         if_out_octets_high[0x20];
1406
1407         u8         if_out_octets_low[0x20];
1408
1409         u8         if_out_ucast_pkts_high[0x20];
1410
1411         u8         if_out_ucast_pkts_low[0x20];
1412
1413         u8         if_out_discards_high[0x20];
1414
1415         u8         if_out_discards_low[0x20];
1416
1417         u8         if_out_errors_high[0x20];
1418
1419         u8         if_out_errors_low[0x20];
1420
1421         u8         if_in_multicast_pkts_high[0x20];
1422
1423         u8         if_in_multicast_pkts_low[0x20];
1424
1425         u8         if_in_broadcast_pkts_high[0x20];
1426
1427         u8         if_in_broadcast_pkts_low[0x20];
1428
1429         u8         if_out_multicast_pkts_high[0x20];
1430
1431         u8         if_out_multicast_pkts_low[0x20];
1432
1433         u8         if_out_broadcast_pkts_high[0x20];
1434
1435         u8         if_out_broadcast_pkts_low[0x20];
1436
1437         u8         reserved_0[0x480];
1438 };
1439
1440 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1441         u8         a_frames_transmitted_ok_high[0x20];
1442
1443         u8         a_frames_transmitted_ok_low[0x20];
1444
1445         u8         a_frames_received_ok_high[0x20];
1446
1447         u8         a_frames_received_ok_low[0x20];
1448
1449         u8         a_frame_check_sequence_errors_high[0x20];
1450
1451         u8         a_frame_check_sequence_errors_low[0x20];
1452
1453         u8         a_alignment_errors_high[0x20];
1454
1455         u8         a_alignment_errors_low[0x20];
1456
1457         u8         a_octets_transmitted_ok_high[0x20];
1458
1459         u8         a_octets_transmitted_ok_low[0x20];
1460
1461         u8         a_octets_received_ok_high[0x20];
1462
1463         u8         a_octets_received_ok_low[0x20];
1464
1465         u8         a_multicast_frames_xmitted_ok_high[0x20];
1466
1467         u8         a_multicast_frames_xmitted_ok_low[0x20];
1468
1469         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1470
1471         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1472
1473         u8         a_multicast_frames_received_ok_high[0x20];
1474
1475         u8         a_multicast_frames_received_ok_low[0x20];
1476
1477         u8         a_broadcast_frames_received_ok_high[0x20];
1478
1479         u8         a_broadcast_frames_received_ok_low[0x20];
1480
1481         u8         a_in_range_length_errors_high[0x20];
1482
1483         u8         a_in_range_length_errors_low[0x20];
1484
1485         u8         a_out_of_range_length_field_high[0x20];
1486
1487         u8         a_out_of_range_length_field_low[0x20];
1488
1489         u8         a_frame_too_long_errors_high[0x20];
1490
1491         u8         a_frame_too_long_errors_low[0x20];
1492
1493         u8         a_symbol_error_during_carrier_high[0x20];
1494
1495         u8         a_symbol_error_during_carrier_low[0x20];
1496
1497         u8         a_mac_control_frames_transmitted_high[0x20];
1498
1499         u8         a_mac_control_frames_transmitted_low[0x20];
1500
1501         u8         a_mac_control_frames_received_high[0x20];
1502
1503         u8         a_mac_control_frames_received_low[0x20];
1504
1505         u8         a_unsupported_opcodes_received_high[0x20];
1506
1507         u8         a_unsupported_opcodes_received_low[0x20];
1508
1509         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1510
1511         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1512
1513         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1514
1515         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1516
1517         u8         reserved_0[0x300];
1518 };
1519
1520 struct mlx5_ifc_cmd_inter_comp_event_bits {
1521         u8         command_completion_vector[0x20];
1522
1523         u8         reserved_0[0xc0];
1524 };
1525
1526 struct mlx5_ifc_stall_vl_event_bits {
1527         u8         reserved_0[0x18];
1528         u8         port_num[0x1];
1529         u8         reserved_1[0x3];
1530         u8         vl[0x4];
1531
1532         u8         reserved_2[0xa0];
1533 };
1534
1535 struct mlx5_ifc_db_bf_congestion_event_bits {
1536         u8         event_subtype[0x8];
1537         u8         reserved_0[0x8];
1538         u8         congestion_level[0x8];
1539         u8         reserved_1[0x8];
1540
1541         u8         reserved_2[0xa0];
1542 };
1543
1544 struct mlx5_ifc_gpio_event_bits {
1545         u8         reserved_0[0x60];
1546
1547         u8         gpio_event_hi[0x20];
1548
1549         u8         gpio_event_lo[0x20];
1550
1551         u8         reserved_1[0x40];
1552 };
1553
1554 struct mlx5_ifc_port_state_change_event_bits {
1555         u8         reserved_0[0x40];
1556
1557         u8         port_num[0x4];
1558         u8         reserved_1[0x1c];
1559
1560         u8         reserved_2[0x80];
1561 };
1562
1563 struct mlx5_ifc_dropped_packet_logged_bits {
1564         u8         reserved_0[0xe0];
1565 };
1566
1567 enum {
1568         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1569         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1570 };
1571
1572 struct mlx5_ifc_cq_error_bits {
1573         u8         reserved_0[0x8];
1574         u8         cqn[0x18];
1575
1576         u8         reserved_1[0x20];
1577
1578         u8         reserved_2[0x18];
1579         u8         syndrome[0x8];
1580
1581         u8         reserved_3[0x80];
1582 };
1583
1584 struct mlx5_ifc_rdma_page_fault_event_bits {
1585         u8         bytes_committed[0x20];
1586
1587         u8         r_key[0x20];
1588
1589         u8         reserved_0[0x10];
1590         u8         packet_len[0x10];
1591
1592         u8         rdma_op_len[0x20];
1593
1594         u8         rdma_va[0x40];
1595
1596         u8         reserved_1[0x5];
1597         u8         rdma[0x1];
1598         u8         write[0x1];
1599         u8         requestor[0x1];
1600         u8         qp_number[0x18];
1601 };
1602
1603 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1604         u8         bytes_committed[0x20];
1605
1606         u8         reserved_0[0x10];
1607         u8         wqe_index[0x10];
1608
1609         u8         reserved_1[0x10];
1610         u8         len[0x10];
1611
1612         u8         reserved_2[0x60];
1613
1614         u8         reserved_3[0x5];
1615         u8         rdma[0x1];
1616         u8         write_read[0x1];
1617         u8         requestor[0x1];
1618         u8         qpn[0x18];
1619 };
1620
1621 struct mlx5_ifc_qp_events_bits {
1622         u8         reserved_0[0xa0];
1623
1624         u8         type[0x8];
1625         u8         reserved_1[0x18];
1626
1627         u8         reserved_2[0x8];
1628         u8         qpn_rqn_sqn[0x18];
1629 };
1630
1631 struct mlx5_ifc_dct_events_bits {
1632         u8         reserved_0[0xc0];
1633
1634         u8         reserved_1[0x8];
1635         u8         dct_number[0x18];
1636 };
1637
1638 struct mlx5_ifc_comp_event_bits {
1639         u8         reserved_0[0xc0];
1640
1641         u8         reserved_1[0x8];
1642         u8         cq_number[0x18];
1643 };
1644
1645 enum {
1646         MLX5_QPC_STATE_RST        = 0x0,
1647         MLX5_QPC_STATE_INIT       = 0x1,
1648         MLX5_QPC_STATE_RTR        = 0x2,
1649         MLX5_QPC_STATE_RTS        = 0x3,
1650         MLX5_QPC_STATE_SQER       = 0x4,
1651         MLX5_QPC_STATE_ERR        = 0x6,
1652         MLX5_QPC_STATE_SQD        = 0x7,
1653         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1654 };
1655
1656 enum {
1657         MLX5_QPC_ST_RC            = 0x0,
1658         MLX5_QPC_ST_UC            = 0x1,
1659         MLX5_QPC_ST_UD            = 0x2,
1660         MLX5_QPC_ST_XRC           = 0x3,
1661         MLX5_QPC_ST_DCI           = 0x5,
1662         MLX5_QPC_ST_QP0           = 0x7,
1663         MLX5_QPC_ST_QP1           = 0x8,
1664         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1665         MLX5_QPC_ST_REG_UMR       = 0xc,
1666 };
1667
1668 enum {
1669         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1670         MLX5_QPC_PM_STATE_REARM     = 0x1,
1671         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1672         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1673 };
1674
1675 enum {
1676         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1677         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1678 };
1679
1680 enum {
1681         MLX5_QPC_MTU_256_BYTES        = 0x1,
1682         MLX5_QPC_MTU_512_BYTES        = 0x2,
1683         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1684         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1685         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1686         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1687 };
1688
1689 enum {
1690         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1691         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1692         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1693         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1694         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1695         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1696         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1697         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1698 };
1699
1700 enum {
1701         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1702         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1703         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1704 };
1705
1706 enum {
1707         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1708         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1709         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1710 };
1711
1712 struct mlx5_ifc_qpc_bits {
1713         u8         state[0x4];
1714         u8         reserved_0[0x4];
1715         u8         st[0x8];
1716         u8         reserved_1[0x3];
1717         u8         pm_state[0x2];
1718         u8         reserved_2[0x7];
1719         u8         end_padding_mode[0x2];
1720         u8         reserved_3[0x2];
1721
1722         u8         wq_signature[0x1];
1723         u8         block_lb_mc[0x1];
1724         u8         atomic_like_write_en[0x1];
1725         u8         latency_sensitive[0x1];
1726         u8         reserved_4[0x1];
1727         u8         drain_sigerr[0x1];
1728         u8         reserved_5[0x2];
1729         u8         pd[0x18];
1730
1731         u8         mtu[0x3];
1732         u8         log_msg_max[0x5];
1733         u8         reserved_6[0x1];
1734         u8         log_rq_size[0x4];
1735         u8         log_rq_stride[0x3];
1736         u8         no_sq[0x1];
1737         u8         log_sq_size[0x4];
1738         u8         reserved_7[0x6];
1739         u8         rlky[0x1];
1740         u8         reserved_8[0x4];
1741
1742         u8         counter_set_id[0x8];
1743         u8         uar_page[0x18];
1744
1745         u8         reserved_9[0x8];
1746         u8         user_index[0x18];
1747
1748         u8         reserved_10[0x3];
1749         u8         log_page_size[0x5];
1750         u8         remote_qpn[0x18];
1751
1752         struct mlx5_ifc_ads_bits primary_address_path;
1753
1754         struct mlx5_ifc_ads_bits secondary_address_path;
1755
1756         u8         log_ack_req_freq[0x4];
1757         u8         reserved_11[0x4];
1758         u8         log_sra_max[0x3];
1759         u8         reserved_12[0x2];
1760         u8         retry_count[0x3];
1761         u8         rnr_retry[0x3];
1762         u8         reserved_13[0x1];
1763         u8         fre[0x1];
1764         u8         cur_rnr_retry[0x3];
1765         u8         cur_retry_count[0x3];
1766         u8         reserved_14[0x5];
1767
1768         u8         reserved_15[0x20];
1769
1770         u8         reserved_16[0x8];
1771         u8         next_send_psn[0x18];
1772
1773         u8         reserved_17[0x8];
1774         u8         cqn_snd[0x18];
1775
1776         u8         reserved_18[0x40];
1777
1778         u8         reserved_19[0x8];
1779         u8         last_acked_psn[0x18];
1780
1781         u8         reserved_20[0x8];
1782         u8         ssn[0x18];
1783
1784         u8         reserved_21[0x8];
1785         u8         log_rra_max[0x3];
1786         u8         reserved_22[0x1];
1787         u8         atomic_mode[0x4];
1788         u8         rre[0x1];
1789         u8         rwe[0x1];
1790         u8         rae[0x1];
1791         u8         reserved_23[0x1];
1792         u8         page_offset[0x6];
1793         u8         reserved_24[0x3];
1794         u8         cd_slave_receive[0x1];
1795         u8         cd_slave_send[0x1];
1796         u8         cd_master[0x1];
1797
1798         u8         reserved_25[0x3];
1799         u8         min_rnr_nak[0x5];
1800         u8         next_rcv_psn[0x18];
1801
1802         u8         reserved_26[0x8];
1803         u8         xrcd[0x18];
1804
1805         u8         reserved_27[0x8];
1806         u8         cqn_rcv[0x18];
1807
1808         u8         dbr_addr[0x40];
1809
1810         u8         q_key[0x20];
1811
1812         u8         reserved_28[0x5];
1813         u8         rq_type[0x3];
1814         u8         srqn_rmpn[0x18];
1815
1816         u8         reserved_29[0x8];
1817         u8         rmsn[0x18];
1818
1819         u8         hw_sq_wqebb_counter[0x10];
1820         u8         sw_sq_wqebb_counter[0x10];
1821
1822         u8         hw_rq_counter[0x20];
1823
1824         u8         sw_rq_counter[0x20];
1825
1826         u8         reserved_30[0x20];
1827
1828         u8         reserved_31[0xf];
1829         u8         cgs[0x1];
1830         u8         cs_req[0x8];
1831         u8         cs_res[0x8];
1832
1833         u8         dc_access_key[0x40];
1834
1835         u8         reserved_32[0xc0];
1836 };
1837
1838 struct mlx5_ifc_roce_addr_layout_bits {
1839         u8         source_l3_address[16][0x8];
1840
1841         u8         reserved_0[0x3];
1842         u8         vlan_valid[0x1];
1843         u8         vlan_id[0xc];
1844         u8         source_mac_47_32[0x10];
1845
1846         u8         source_mac_31_0[0x20];
1847
1848         u8         reserved_1[0x14];
1849         u8         roce_l3_type[0x4];
1850         u8         roce_version[0x8];
1851
1852         u8         reserved_2[0x20];
1853 };
1854
1855 union mlx5_ifc_hca_cap_union_bits {
1856         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1857         struct mlx5_ifc_odp_cap_bits odp_cap;
1858         struct mlx5_ifc_atomic_caps_bits atomic_caps;
1859         struct mlx5_ifc_roce_cap_bits roce_cap;
1860         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1861         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1862         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
1863         u8         reserved_0[0x8000];
1864 };
1865
1866 enum {
1867         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
1868         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
1869         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
1870 };
1871
1872 struct mlx5_ifc_flow_context_bits {
1873         u8         reserved_0[0x20];
1874
1875         u8         group_id[0x20];
1876
1877         u8         reserved_1[0x8];
1878         u8         flow_tag[0x18];
1879
1880         u8         reserved_2[0x10];
1881         u8         action[0x10];
1882
1883         u8         reserved_3[0x8];
1884         u8         destination_list_size[0x18];
1885
1886         u8         reserved_4[0x160];
1887
1888         struct mlx5_ifc_fte_match_param_bits match_value;
1889
1890         u8         reserved_5[0x600];
1891
1892         struct mlx5_ifc_dest_format_struct_bits destination[0];
1893 };
1894
1895 enum {
1896         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
1897         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
1898 };
1899
1900 struct mlx5_ifc_xrc_srqc_bits {
1901         u8         state[0x4];
1902         u8         log_xrc_srq_size[0x4];
1903         u8         reserved_0[0x18];
1904
1905         u8         wq_signature[0x1];
1906         u8         cont_srq[0x1];
1907         u8         reserved_1[0x1];
1908         u8         rlky[0x1];
1909         u8         basic_cyclic_rcv_wqe[0x1];
1910         u8         log_rq_stride[0x3];
1911         u8         xrcd[0x18];
1912
1913         u8         page_offset[0x6];
1914         u8         reserved_2[0x2];
1915         u8         cqn[0x18];
1916
1917         u8         reserved_3[0x20];
1918
1919         u8         user_index_equal_xrc_srqn[0x1];
1920         u8         reserved_4[0x1];
1921         u8         log_page_size[0x6];
1922         u8         user_index[0x18];
1923
1924         u8         reserved_5[0x20];
1925
1926         u8         reserved_6[0x8];
1927         u8         pd[0x18];
1928
1929         u8         lwm[0x10];
1930         u8         wqe_cnt[0x10];
1931
1932         u8         reserved_7[0x40];
1933
1934         u8         db_record_addr_h[0x20];
1935
1936         u8         db_record_addr_l[0x1e];
1937         u8         reserved_8[0x2];
1938
1939         u8         reserved_9[0x80];
1940 };
1941
1942 struct mlx5_ifc_traffic_counter_bits {
1943         u8         packets[0x40];
1944
1945         u8         octets[0x40];
1946 };
1947
1948 struct mlx5_ifc_tisc_bits {
1949         u8         reserved_0[0xc];
1950         u8         prio[0x4];
1951         u8         reserved_1[0x10];
1952
1953         u8         reserved_2[0x100];
1954
1955         u8         reserved_3[0x8];
1956         u8         transport_domain[0x18];
1957
1958         u8         reserved_4[0x3c0];
1959 };
1960
1961 enum {
1962         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
1963         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
1964 };
1965
1966 enum {
1967         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
1968         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
1969 };
1970
1971 enum {
1972         MLX5_RX_HASH_FN_NONE           = 0x0,
1973         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
1974         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
1975 };
1976
1977 enum {
1978         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
1979         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
1980 };
1981
1982 struct mlx5_ifc_tirc_bits {
1983         u8         reserved_0[0x20];
1984
1985         u8         disp_type[0x4];
1986         u8         reserved_1[0x1c];
1987
1988         u8         reserved_2[0x40];
1989
1990         u8         reserved_3[0x4];
1991         u8         lro_timeout_period_usecs[0x10];
1992         u8         lro_enable_mask[0x4];
1993         u8         lro_max_ip_payload_size[0x8];
1994
1995         u8         reserved_4[0x40];
1996
1997         u8         reserved_5[0x8];
1998         u8         inline_rqn[0x18];
1999
2000         u8         rx_hash_symmetric[0x1];
2001         u8         reserved_6[0x1];
2002         u8         tunneled_offload_en[0x1];
2003         u8         reserved_7[0x5];
2004         u8         indirect_table[0x18];
2005
2006         u8         rx_hash_fn[0x4];
2007         u8         reserved_8[0x2];
2008         u8         self_lb_block[0x2];
2009         u8         transport_domain[0x18];
2010
2011         u8         rx_hash_toeplitz_key[10][0x20];
2012
2013         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2014
2015         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2016
2017         u8         reserved_9[0x4c0];
2018 };
2019
2020 enum {
2021         MLX5_SRQC_STATE_GOOD   = 0x0,
2022         MLX5_SRQC_STATE_ERROR  = 0x1,
2023 };
2024
2025 struct mlx5_ifc_srqc_bits {
2026         u8         state[0x4];
2027         u8         log_srq_size[0x4];
2028         u8         reserved_0[0x18];
2029
2030         u8         wq_signature[0x1];
2031         u8         cont_srq[0x1];
2032         u8         reserved_1[0x1];
2033         u8         rlky[0x1];
2034         u8         reserved_2[0x1];
2035         u8         log_rq_stride[0x3];
2036         u8         xrcd[0x18];
2037
2038         u8         page_offset[0x6];
2039         u8         reserved_3[0x2];
2040         u8         cqn[0x18];
2041
2042         u8         reserved_4[0x20];
2043
2044         u8         reserved_5[0x2];
2045         u8         log_page_size[0x6];
2046         u8         reserved_6[0x18];
2047
2048         u8         reserved_7[0x20];
2049
2050         u8         reserved_8[0x8];
2051         u8         pd[0x18];
2052
2053         u8         lwm[0x10];
2054         u8         wqe_cnt[0x10];
2055
2056         u8         reserved_9[0x40];
2057
2058         u8         dbr_addr[0x40];
2059
2060         u8         reserved_10[0x80];
2061 };
2062
2063 enum {
2064         MLX5_SQC_STATE_RST  = 0x0,
2065         MLX5_SQC_STATE_RDY  = 0x1,
2066         MLX5_SQC_STATE_ERR  = 0x3,
2067 };
2068
2069 struct mlx5_ifc_sqc_bits {
2070         u8         rlky[0x1];
2071         u8         cd_master[0x1];
2072         u8         fre[0x1];
2073         u8         flush_in_error_en[0x1];
2074         u8         reserved_0[0x4];
2075         u8         state[0x4];
2076         u8         reserved_1[0x14];
2077
2078         u8         reserved_2[0x8];
2079         u8         user_index[0x18];
2080
2081         u8         reserved_3[0x8];
2082         u8         cqn[0x18];
2083
2084         u8         reserved_4[0xa0];
2085
2086         u8         tis_lst_sz[0x10];
2087         u8         reserved_5[0x10];
2088
2089         u8         reserved_6[0x40];
2090
2091         u8         reserved_7[0x8];
2092         u8         tis_num_0[0x18];
2093
2094         struct mlx5_ifc_wq_bits wq;
2095 };
2096
2097 struct mlx5_ifc_rqtc_bits {
2098         u8         reserved_0[0xa0];
2099
2100         u8         reserved_1[0x10];
2101         u8         rqt_max_size[0x10];
2102
2103         u8         reserved_2[0x10];
2104         u8         rqt_actual_size[0x10];
2105
2106         u8         reserved_3[0x6a0];
2107
2108         struct mlx5_ifc_rq_num_bits rq_num[0];
2109 };
2110
2111 enum {
2112         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2113         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2114 };
2115
2116 enum {
2117         MLX5_RQC_STATE_RST  = 0x0,
2118         MLX5_RQC_STATE_RDY  = 0x1,
2119         MLX5_RQC_STATE_ERR  = 0x3,
2120 };
2121
2122 struct mlx5_ifc_rqc_bits {
2123         u8         rlky[0x1];
2124         u8         reserved_0[0x2];
2125         u8         vsd[0x1];
2126         u8         mem_rq_type[0x4];
2127         u8         state[0x4];
2128         u8         reserved_1[0x1];
2129         u8         flush_in_error_en[0x1];
2130         u8         reserved_2[0x12];
2131
2132         u8         reserved_3[0x8];
2133         u8         user_index[0x18];
2134
2135         u8         reserved_4[0x8];
2136         u8         cqn[0x18];
2137
2138         u8         counter_set_id[0x8];
2139         u8         reserved_5[0x18];
2140
2141         u8         reserved_6[0x8];
2142         u8         rmpn[0x18];
2143
2144         u8         reserved_7[0xe0];
2145
2146         struct mlx5_ifc_wq_bits wq;
2147 };
2148
2149 enum {
2150         MLX5_RMPC_STATE_RDY  = 0x1,
2151         MLX5_RMPC_STATE_ERR  = 0x3,
2152 };
2153
2154 struct mlx5_ifc_rmpc_bits {
2155         u8         reserved_0[0x8];
2156         u8         state[0x4];
2157         u8         reserved_1[0x14];
2158
2159         u8         basic_cyclic_rcv_wqe[0x1];
2160         u8         reserved_2[0x1f];
2161
2162         u8         reserved_3[0x140];
2163
2164         struct mlx5_ifc_wq_bits wq;
2165 };
2166
2167 struct mlx5_ifc_nic_vport_context_bits {
2168         u8         reserved_0[0x1f];
2169         u8         roce_en[0x1];
2170
2171         u8         arm_change_event[0x1];
2172         u8         reserved_1[0x1a];
2173         u8         event_on_mtu[0x1];
2174         u8         event_on_promisc_change[0x1];
2175         u8         event_on_vlan_change[0x1];
2176         u8         event_on_mc_address_change[0x1];
2177         u8         event_on_uc_address_change[0x1];
2178
2179         u8         reserved_2[0xf0];
2180
2181         u8         mtu[0x10];
2182
2183         u8         reserved_3[0x640];
2184
2185         u8         promisc_uc[0x1];
2186         u8         promisc_mc[0x1];
2187         u8         promisc_all[0x1];
2188         u8         reserved_4[0x2];
2189         u8         allowed_list_type[0x3];
2190         u8         reserved_5[0xc];
2191         u8         allowed_list_size[0xc];
2192
2193         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2194
2195         u8         reserved_6[0x20];
2196
2197         u8         current_uc_mac_address[0][0x40];
2198 };
2199
2200 enum {
2201         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2202         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2203         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2204 };
2205
2206 struct mlx5_ifc_mkc_bits {
2207         u8         reserved_0[0x1];
2208         u8         free[0x1];
2209         u8         reserved_1[0xd];
2210         u8         small_fence_on_rdma_read_response[0x1];
2211         u8         umr_en[0x1];
2212         u8         a[0x1];
2213         u8         rw[0x1];
2214         u8         rr[0x1];
2215         u8         lw[0x1];
2216         u8         lr[0x1];
2217         u8         access_mode[0x2];
2218         u8         reserved_2[0x8];
2219
2220         u8         qpn[0x18];
2221         u8         mkey_7_0[0x8];
2222
2223         u8         reserved_3[0x20];
2224
2225         u8         length64[0x1];
2226         u8         bsf_en[0x1];
2227         u8         sync_umr[0x1];
2228         u8         reserved_4[0x2];
2229         u8         expected_sigerr_count[0x1];
2230         u8         reserved_5[0x1];
2231         u8         en_rinval[0x1];
2232         u8         pd[0x18];
2233
2234         u8         start_addr[0x40];
2235
2236         u8         len[0x40];
2237
2238         u8         bsf_octword_size[0x20];
2239
2240         u8         reserved_6[0x80];
2241
2242         u8         translations_octword_size[0x20];
2243
2244         u8         reserved_7[0x1b];
2245         u8         log_page_size[0x5];
2246
2247         u8         reserved_8[0x20];
2248 };
2249
2250 struct mlx5_ifc_pkey_bits {
2251         u8         reserved_0[0x10];
2252         u8         pkey[0x10];
2253 };
2254
2255 struct mlx5_ifc_array128_auto_bits {
2256         u8         array128_auto[16][0x8];
2257 };
2258
2259 struct mlx5_ifc_hca_vport_context_bits {
2260         u8         field_select[0x20];
2261
2262         u8         reserved_0[0xe0];
2263
2264         u8         sm_virt_aware[0x1];
2265         u8         has_smi[0x1];
2266         u8         has_raw[0x1];
2267         u8         grh_required[0x1];
2268         u8         reserved_1[0xc];
2269         u8         port_physical_state[0x4];
2270         u8         vport_state_policy[0x4];
2271         u8         port_state[0x4];
2272         u8         vport_state[0x4];
2273
2274         u8         reserved_2[0x20];
2275
2276         u8         system_image_guid[0x40];
2277
2278         u8         port_guid[0x40];
2279
2280         u8         node_guid[0x40];
2281
2282         u8         cap_mask1[0x20];
2283
2284         u8         cap_mask1_field_select[0x20];
2285
2286         u8         cap_mask2[0x20];
2287
2288         u8         cap_mask2_field_select[0x20];
2289
2290         u8         reserved_3[0x80];
2291
2292         u8         lid[0x10];
2293         u8         reserved_4[0x4];
2294         u8         init_type_reply[0x4];
2295         u8         lmc[0x3];
2296         u8         subnet_timeout[0x5];
2297
2298         u8         sm_lid[0x10];
2299         u8         sm_sl[0x4];
2300         u8         reserved_5[0xc];
2301
2302         u8         qkey_violation_counter[0x10];
2303         u8         pkey_violation_counter[0x10];
2304
2305         u8         reserved_6[0xca0];
2306 };
2307
2308 enum {
2309         MLX5_EQC_STATUS_OK                = 0x0,
2310         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2311 };
2312
2313 enum {
2314         MLX5_EQC_ST_ARMED  = 0x9,
2315         MLX5_EQC_ST_FIRED  = 0xa,
2316 };
2317
2318 struct mlx5_ifc_eqc_bits {
2319         u8         status[0x4];
2320         u8         reserved_0[0x9];
2321         u8         ec[0x1];
2322         u8         oi[0x1];
2323         u8         reserved_1[0x5];
2324         u8         st[0x4];
2325         u8         reserved_2[0x8];
2326
2327         u8         reserved_3[0x20];
2328
2329         u8         reserved_4[0x14];
2330         u8         page_offset[0x6];
2331         u8         reserved_5[0x6];
2332
2333         u8         reserved_6[0x3];
2334         u8         log_eq_size[0x5];
2335         u8         uar_page[0x18];
2336
2337         u8         reserved_7[0x20];
2338
2339         u8         reserved_8[0x18];
2340         u8         intr[0x8];
2341
2342         u8         reserved_9[0x3];
2343         u8         log_page_size[0x5];
2344         u8         reserved_10[0x18];
2345
2346         u8         reserved_11[0x60];
2347
2348         u8         reserved_12[0x8];
2349         u8         consumer_counter[0x18];
2350
2351         u8         reserved_13[0x8];
2352         u8         producer_counter[0x18];
2353
2354         u8         reserved_14[0x80];
2355 };
2356
2357 enum {
2358         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2359         MLX5_DCTC_STATE_DRAINING  = 0x1,
2360         MLX5_DCTC_STATE_DRAINED   = 0x2,
2361 };
2362
2363 enum {
2364         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2365         MLX5_DCTC_CS_RES_NA         = 0x1,
2366         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2367 };
2368
2369 enum {
2370         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2371         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2372         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2373         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2374         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2375 };
2376
2377 struct mlx5_ifc_dctc_bits {
2378         u8         reserved_0[0x4];
2379         u8         state[0x4];
2380         u8         reserved_1[0x18];
2381
2382         u8         reserved_2[0x8];
2383         u8         user_index[0x18];
2384
2385         u8         reserved_3[0x8];
2386         u8         cqn[0x18];
2387
2388         u8         counter_set_id[0x8];
2389         u8         atomic_mode[0x4];
2390         u8         rre[0x1];
2391         u8         rwe[0x1];
2392         u8         rae[0x1];
2393         u8         atomic_like_write_en[0x1];
2394         u8         latency_sensitive[0x1];
2395         u8         rlky[0x1];
2396         u8         free_ar[0x1];
2397         u8         reserved_4[0xd];
2398
2399         u8         reserved_5[0x8];
2400         u8         cs_res[0x8];
2401         u8         reserved_6[0x3];
2402         u8         min_rnr_nak[0x5];
2403         u8         reserved_7[0x8];
2404
2405         u8         reserved_8[0x8];
2406         u8         srqn[0x18];
2407
2408         u8         reserved_9[0x8];
2409         u8         pd[0x18];
2410
2411         u8         tclass[0x8];
2412         u8         reserved_10[0x4];
2413         u8         flow_label[0x14];
2414
2415         u8         dc_access_key[0x40];
2416
2417         u8         reserved_11[0x5];
2418         u8         mtu[0x3];
2419         u8         port[0x8];
2420         u8         pkey_index[0x10];
2421
2422         u8         reserved_12[0x8];
2423         u8         my_addr_index[0x8];
2424         u8         reserved_13[0x8];
2425         u8         hop_limit[0x8];
2426
2427         u8         dc_access_key_violation_count[0x20];
2428
2429         u8         reserved_14[0x14];
2430         u8         dei_cfi[0x1];
2431         u8         eth_prio[0x3];
2432         u8         ecn[0x2];
2433         u8         dscp[0x6];
2434
2435         u8         reserved_15[0x40];
2436 };
2437
2438 enum {
2439         MLX5_CQC_STATUS_OK             = 0x0,
2440         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2441         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2442 };
2443
2444 enum {
2445         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2446         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2447 };
2448
2449 enum {
2450         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2451         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2452         MLX5_CQC_ST_FIRED                                 = 0xa,
2453 };
2454
2455 struct mlx5_ifc_cqc_bits {
2456         u8         status[0x4];
2457         u8         reserved_0[0x4];
2458         u8         cqe_sz[0x3];
2459         u8         cc[0x1];
2460         u8         reserved_1[0x1];
2461         u8         scqe_break_moderation_en[0x1];
2462         u8         oi[0x1];
2463         u8         reserved_2[0x2];
2464         u8         cqe_zip_en[0x1];
2465         u8         mini_cqe_res_format[0x2];
2466         u8         st[0x4];
2467         u8         reserved_3[0x8];
2468
2469         u8         reserved_4[0x20];
2470
2471         u8         reserved_5[0x14];
2472         u8         page_offset[0x6];
2473         u8         reserved_6[0x6];
2474
2475         u8         reserved_7[0x3];
2476         u8         log_cq_size[0x5];
2477         u8         uar_page[0x18];
2478
2479         u8         reserved_8[0x4];
2480         u8         cq_period[0xc];
2481         u8         cq_max_count[0x10];
2482
2483         u8         reserved_9[0x18];
2484         u8         c_eqn[0x8];
2485
2486         u8         reserved_10[0x3];
2487         u8         log_page_size[0x5];
2488         u8         reserved_11[0x18];
2489
2490         u8         reserved_12[0x20];
2491
2492         u8         reserved_13[0x8];
2493         u8         last_notified_index[0x18];
2494
2495         u8         reserved_14[0x8];
2496         u8         last_solicit_index[0x18];
2497
2498         u8         reserved_15[0x8];
2499         u8         consumer_counter[0x18];
2500
2501         u8         reserved_16[0x8];
2502         u8         producer_counter[0x18];
2503
2504         u8         reserved_17[0x40];
2505
2506         u8         dbr_addr[0x40];
2507 };
2508
2509 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2510         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2511         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2512         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2513         u8         reserved_0[0x800];
2514 };
2515
2516 struct mlx5_ifc_query_adapter_param_block_bits {
2517         u8         reserved_0[0xc0];
2518
2519         u8         reserved_1[0x8];
2520         u8         ieee_vendor_id[0x18];
2521
2522         u8         reserved_2[0x10];
2523         u8         vsd_vendor_id[0x10];
2524
2525         u8         vsd[208][0x8];
2526
2527         u8         vsd_contd_psid[16][0x8];
2528 };
2529
2530 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2531         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2532         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2533         u8         reserved_0[0x20];
2534 };
2535
2536 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2537         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2538         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2539         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2540         u8         reserved_0[0x20];
2541 };
2542
2543 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2544         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2545         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2546         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2547         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2548         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2549         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2550         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2551         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2552         u8         reserved_0[0x7c0];
2553 };
2554
2555 union mlx5_ifc_event_auto_bits {
2556         struct mlx5_ifc_comp_event_bits comp_event;
2557         struct mlx5_ifc_dct_events_bits dct_events;
2558         struct mlx5_ifc_qp_events_bits qp_events;
2559         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2560         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2561         struct mlx5_ifc_cq_error_bits cq_error;
2562         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2563         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2564         struct mlx5_ifc_gpio_event_bits gpio_event;
2565         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2566         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2567         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2568         u8         reserved_0[0xe0];
2569 };
2570
2571 struct mlx5_ifc_health_buffer_bits {
2572         u8         reserved_0[0x100];
2573
2574         u8         assert_existptr[0x20];
2575
2576         u8         assert_callra[0x20];
2577
2578         u8         reserved_1[0x40];
2579
2580         u8         fw_version[0x20];
2581
2582         u8         hw_id[0x20];
2583
2584         u8         reserved_2[0x20];
2585
2586         u8         irisc_index[0x8];
2587         u8         synd[0x8];
2588         u8         ext_synd[0x10];
2589 };
2590
2591 struct mlx5_ifc_register_loopback_control_bits {
2592         u8         no_lb[0x1];
2593         u8         reserved_0[0x7];
2594         u8         port[0x8];
2595         u8         reserved_1[0x10];
2596
2597         u8         reserved_2[0x60];
2598 };
2599
2600 struct mlx5_ifc_teardown_hca_out_bits {
2601         u8         status[0x8];
2602         u8         reserved_0[0x18];
2603
2604         u8         syndrome[0x20];
2605
2606         u8         reserved_1[0x40];
2607 };
2608
2609 enum {
2610         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
2611         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
2612 };
2613
2614 struct mlx5_ifc_teardown_hca_in_bits {
2615         u8         opcode[0x10];
2616         u8         reserved_0[0x10];
2617
2618         u8         reserved_1[0x10];
2619         u8         op_mod[0x10];
2620
2621         u8         reserved_2[0x10];
2622         u8         profile[0x10];
2623
2624         u8         reserved_3[0x20];
2625 };
2626
2627 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2628         u8         status[0x8];
2629         u8         reserved_0[0x18];
2630
2631         u8         syndrome[0x20];
2632
2633         u8         reserved_1[0x40];
2634 };
2635
2636 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2637         u8         opcode[0x10];
2638         u8         reserved_0[0x10];
2639
2640         u8         reserved_1[0x10];
2641         u8         op_mod[0x10];
2642
2643         u8         reserved_2[0x8];
2644         u8         qpn[0x18];
2645
2646         u8         reserved_3[0x20];
2647
2648         u8         opt_param_mask[0x20];
2649
2650         u8         reserved_4[0x20];
2651
2652         struct mlx5_ifc_qpc_bits qpc;
2653
2654         u8         reserved_5[0x80];
2655 };
2656
2657 struct mlx5_ifc_sqd2rts_qp_out_bits {
2658         u8         status[0x8];
2659         u8         reserved_0[0x18];
2660
2661         u8         syndrome[0x20];
2662
2663         u8         reserved_1[0x40];
2664 };
2665
2666 struct mlx5_ifc_sqd2rts_qp_in_bits {
2667         u8         opcode[0x10];
2668         u8         reserved_0[0x10];
2669
2670         u8         reserved_1[0x10];
2671         u8         op_mod[0x10];
2672
2673         u8         reserved_2[0x8];
2674         u8         qpn[0x18];
2675
2676         u8         reserved_3[0x20];
2677
2678         u8         opt_param_mask[0x20];
2679
2680         u8         reserved_4[0x20];
2681
2682         struct mlx5_ifc_qpc_bits qpc;
2683
2684         u8         reserved_5[0x80];
2685 };
2686
2687 struct mlx5_ifc_set_roce_address_out_bits {
2688         u8         status[0x8];
2689         u8         reserved_0[0x18];
2690
2691         u8         syndrome[0x20];
2692
2693         u8         reserved_1[0x40];
2694 };
2695
2696 struct mlx5_ifc_set_roce_address_in_bits {
2697         u8         opcode[0x10];
2698         u8         reserved_0[0x10];
2699
2700         u8         reserved_1[0x10];
2701         u8         op_mod[0x10];
2702
2703         u8         roce_address_index[0x10];
2704         u8         reserved_2[0x10];
2705
2706         u8         reserved_3[0x20];
2707
2708         struct mlx5_ifc_roce_addr_layout_bits roce_address;
2709 };
2710
2711 struct mlx5_ifc_set_mad_demux_out_bits {
2712         u8         status[0x8];
2713         u8         reserved_0[0x18];
2714
2715         u8         syndrome[0x20];
2716
2717         u8         reserved_1[0x40];
2718 };
2719
2720 enum {
2721         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
2722         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
2723 };
2724
2725 struct mlx5_ifc_set_mad_demux_in_bits {
2726         u8         opcode[0x10];
2727         u8         reserved_0[0x10];
2728
2729         u8         reserved_1[0x10];
2730         u8         op_mod[0x10];
2731
2732         u8         reserved_2[0x20];
2733
2734         u8         reserved_3[0x6];
2735         u8         demux_mode[0x2];
2736         u8         reserved_4[0x18];
2737 };
2738
2739 struct mlx5_ifc_set_l2_table_entry_out_bits {
2740         u8         status[0x8];
2741         u8         reserved_0[0x18];
2742
2743         u8         syndrome[0x20];
2744
2745         u8         reserved_1[0x40];
2746 };
2747
2748 struct mlx5_ifc_set_l2_table_entry_in_bits {
2749         u8         opcode[0x10];
2750         u8         reserved_0[0x10];
2751
2752         u8         reserved_1[0x10];
2753         u8         op_mod[0x10];
2754
2755         u8         reserved_2[0x60];
2756
2757         u8         reserved_3[0x8];
2758         u8         table_index[0x18];
2759
2760         u8         reserved_4[0x20];
2761
2762         u8         reserved_5[0x13];
2763         u8         vlan_valid[0x1];
2764         u8         vlan[0xc];
2765
2766         struct mlx5_ifc_mac_address_layout_bits mac_address;
2767
2768         u8         reserved_6[0xc0];
2769 };
2770
2771 struct mlx5_ifc_set_issi_out_bits {
2772         u8         status[0x8];
2773         u8         reserved_0[0x18];
2774
2775         u8         syndrome[0x20];
2776
2777         u8         reserved_1[0x40];
2778 };
2779
2780 struct mlx5_ifc_set_issi_in_bits {
2781         u8         opcode[0x10];
2782         u8         reserved_0[0x10];
2783
2784         u8         reserved_1[0x10];
2785         u8         op_mod[0x10];
2786
2787         u8         reserved_2[0x10];
2788         u8         current_issi[0x10];
2789
2790         u8         reserved_3[0x20];
2791 };
2792
2793 struct mlx5_ifc_set_hca_cap_out_bits {
2794         u8         status[0x8];
2795         u8         reserved_0[0x18];
2796
2797         u8         syndrome[0x20];
2798
2799         u8         reserved_1[0x40];
2800 };
2801
2802 struct mlx5_ifc_set_hca_cap_in_bits {
2803         u8         opcode[0x10];
2804         u8         reserved_0[0x10];
2805
2806         u8         reserved_1[0x10];
2807         u8         op_mod[0x10];
2808
2809         u8         reserved_2[0x40];
2810
2811         union mlx5_ifc_hca_cap_union_bits capability;
2812 };
2813
2814 struct mlx5_ifc_set_fte_out_bits {
2815         u8         status[0x8];
2816         u8         reserved_0[0x18];
2817
2818         u8         syndrome[0x20];
2819
2820         u8         reserved_1[0x40];
2821 };
2822
2823 struct mlx5_ifc_set_fte_in_bits {
2824         u8         opcode[0x10];
2825         u8         reserved_0[0x10];
2826
2827         u8         reserved_1[0x10];
2828         u8         op_mod[0x10];
2829
2830         u8         reserved_2[0x40];
2831
2832         u8         table_type[0x8];
2833         u8         reserved_3[0x18];
2834
2835         u8         reserved_4[0x8];
2836         u8         table_id[0x18];
2837
2838         u8         reserved_5[0x40];
2839
2840         u8         flow_index[0x20];
2841
2842         u8         reserved_6[0xe0];
2843
2844         struct mlx5_ifc_flow_context_bits flow_context;
2845 };
2846
2847 struct mlx5_ifc_rts2rts_qp_out_bits {
2848         u8         status[0x8];
2849         u8         reserved_0[0x18];
2850
2851         u8         syndrome[0x20];
2852
2853         u8         reserved_1[0x40];
2854 };
2855
2856 struct mlx5_ifc_rts2rts_qp_in_bits {
2857         u8         opcode[0x10];
2858         u8         reserved_0[0x10];
2859
2860         u8         reserved_1[0x10];
2861         u8         op_mod[0x10];
2862
2863         u8         reserved_2[0x8];
2864         u8         qpn[0x18];
2865
2866         u8         reserved_3[0x20];
2867
2868         u8         opt_param_mask[0x20];
2869
2870         u8         reserved_4[0x20];
2871
2872         struct mlx5_ifc_qpc_bits qpc;
2873
2874         u8         reserved_5[0x80];
2875 };
2876
2877 struct mlx5_ifc_rtr2rts_qp_out_bits {
2878         u8         status[0x8];
2879         u8         reserved_0[0x18];
2880
2881         u8         syndrome[0x20];
2882
2883         u8         reserved_1[0x40];
2884 };
2885
2886 struct mlx5_ifc_rtr2rts_qp_in_bits {
2887         u8         opcode[0x10];
2888         u8         reserved_0[0x10];
2889
2890         u8         reserved_1[0x10];
2891         u8         op_mod[0x10];
2892
2893         u8         reserved_2[0x8];
2894         u8         qpn[0x18];
2895
2896         u8         reserved_3[0x20];
2897
2898         u8         opt_param_mask[0x20];
2899
2900         u8         reserved_4[0x20];
2901
2902         struct mlx5_ifc_qpc_bits qpc;
2903
2904         u8         reserved_5[0x80];
2905 };
2906
2907 struct mlx5_ifc_rst2init_qp_out_bits {
2908         u8         status[0x8];
2909         u8         reserved_0[0x18];
2910
2911         u8         syndrome[0x20];
2912
2913         u8         reserved_1[0x40];
2914 };
2915
2916 struct mlx5_ifc_rst2init_qp_in_bits {
2917         u8         opcode[0x10];
2918         u8         reserved_0[0x10];
2919
2920         u8         reserved_1[0x10];
2921         u8         op_mod[0x10];
2922
2923         u8         reserved_2[0x8];
2924         u8         qpn[0x18];
2925
2926         u8         reserved_3[0x20];
2927
2928         u8         opt_param_mask[0x20];
2929
2930         u8         reserved_4[0x20];
2931
2932         struct mlx5_ifc_qpc_bits qpc;
2933
2934         u8         reserved_5[0x80];
2935 };
2936
2937 struct mlx5_ifc_query_xrc_srq_out_bits {
2938         u8         status[0x8];
2939         u8         reserved_0[0x18];
2940
2941         u8         syndrome[0x20];
2942
2943         u8         reserved_1[0x40];
2944
2945         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
2946
2947         u8         reserved_2[0x600];
2948
2949         u8         pas[0][0x40];
2950 };
2951
2952 struct mlx5_ifc_query_xrc_srq_in_bits {
2953         u8         opcode[0x10];
2954         u8         reserved_0[0x10];
2955
2956         u8         reserved_1[0x10];
2957         u8         op_mod[0x10];
2958
2959         u8         reserved_2[0x8];
2960         u8         xrc_srqn[0x18];
2961
2962         u8         reserved_3[0x20];
2963 };
2964
2965 enum {
2966         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
2967         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
2968 };
2969
2970 struct mlx5_ifc_query_vport_state_out_bits {
2971         u8         status[0x8];
2972         u8         reserved_0[0x18];
2973
2974         u8         syndrome[0x20];
2975
2976         u8         reserved_1[0x20];
2977
2978         u8         reserved_2[0x18];
2979         u8         admin_state[0x4];
2980         u8         state[0x4];
2981 };
2982
2983 enum {
2984         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
2985         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
2986 };
2987
2988 struct mlx5_ifc_query_vport_state_in_bits {
2989         u8         opcode[0x10];
2990         u8         reserved_0[0x10];
2991
2992         u8         reserved_1[0x10];
2993         u8         op_mod[0x10];
2994
2995         u8         other_vport[0x1];
2996         u8         reserved_2[0xf];
2997         u8         vport_number[0x10];
2998
2999         u8         reserved_3[0x20];
3000 };
3001
3002 struct mlx5_ifc_query_vport_counter_out_bits {
3003         u8         status[0x8];
3004         u8         reserved_0[0x18];
3005
3006         u8         syndrome[0x20];
3007
3008         u8         reserved_1[0x40];
3009
3010         struct mlx5_ifc_traffic_counter_bits received_errors;
3011
3012         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3013
3014         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3015
3016         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3017
3018         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3019
3020         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3021
3022         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3023
3024         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3025
3026         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3027
3028         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3029
3030         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3031
3032         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3033
3034         u8         reserved_2[0xa00];
3035 };
3036
3037 enum {
3038         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3039 };
3040
3041 struct mlx5_ifc_query_vport_counter_in_bits {
3042         u8         opcode[0x10];
3043         u8         reserved_0[0x10];
3044
3045         u8         reserved_1[0x10];
3046         u8         op_mod[0x10];
3047
3048         u8         other_vport[0x1];
3049         u8         reserved_2[0xf];
3050         u8         vport_number[0x10];
3051
3052         u8         reserved_3[0x60];
3053
3054         u8         clear[0x1];
3055         u8         reserved_4[0x1f];
3056
3057         u8         reserved_5[0x20];
3058 };
3059
3060 struct mlx5_ifc_query_tis_out_bits {
3061         u8         status[0x8];
3062         u8         reserved_0[0x18];
3063
3064         u8         syndrome[0x20];
3065
3066         u8         reserved_1[0x40];
3067
3068         struct mlx5_ifc_tisc_bits tis_context;
3069 };
3070
3071 struct mlx5_ifc_query_tis_in_bits {
3072         u8         opcode[0x10];
3073         u8         reserved_0[0x10];
3074
3075         u8         reserved_1[0x10];
3076         u8         op_mod[0x10];
3077
3078         u8         reserved_2[0x8];
3079         u8         tisn[0x18];
3080
3081         u8         reserved_3[0x20];
3082 };
3083
3084 struct mlx5_ifc_query_tir_out_bits {
3085         u8         status[0x8];
3086         u8         reserved_0[0x18];
3087
3088         u8         syndrome[0x20];
3089
3090         u8         reserved_1[0xc0];
3091
3092         struct mlx5_ifc_tirc_bits tir_context;
3093 };
3094
3095 struct mlx5_ifc_query_tir_in_bits {
3096         u8         opcode[0x10];
3097         u8         reserved_0[0x10];
3098
3099         u8         reserved_1[0x10];
3100         u8         op_mod[0x10];
3101
3102         u8         reserved_2[0x8];
3103         u8         tirn[0x18];
3104
3105         u8         reserved_3[0x20];
3106 };
3107
3108 struct mlx5_ifc_query_srq_out_bits {
3109         u8         status[0x8];
3110         u8         reserved_0[0x18];
3111
3112         u8         syndrome[0x20];
3113
3114         u8         reserved_1[0x40];
3115
3116         struct mlx5_ifc_srqc_bits srq_context_entry;
3117
3118         u8         reserved_2[0x600];
3119
3120         u8         pas[0][0x40];
3121 };
3122
3123 struct mlx5_ifc_query_srq_in_bits {
3124         u8         opcode[0x10];
3125         u8         reserved_0[0x10];
3126
3127         u8         reserved_1[0x10];
3128         u8         op_mod[0x10];
3129
3130         u8         reserved_2[0x8];
3131         u8         srqn[0x18];
3132
3133         u8         reserved_3[0x20];
3134 };
3135
3136 struct mlx5_ifc_query_sq_out_bits {
3137         u8         status[0x8];
3138         u8         reserved_0[0x18];
3139
3140         u8         syndrome[0x20];
3141
3142         u8         reserved_1[0xc0];
3143
3144         struct mlx5_ifc_sqc_bits sq_context;
3145 };
3146
3147 struct mlx5_ifc_query_sq_in_bits {
3148         u8         opcode[0x10];
3149         u8         reserved_0[0x10];
3150
3151         u8         reserved_1[0x10];
3152         u8         op_mod[0x10];
3153
3154         u8         reserved_2[0x8];
3155         u8         sqn[0x18];
3156
3157         u8         reserved_3[0x20];
3158 };
3159
3160 struct mlx5_ifc_query_special_contexts_out_bits {
3161         u8         status[0x8];
3162         u8         reserved_0[0x18];
3163
3164         u8         syndrome[0x20];
3165
3166         u8         reserved_1[0x20];
3167
3168         u8         resd_lkey[0x20];
3169 };
3170
3171 struct mlx5_ifc_query_special_contexts_in_bits {
3172         u8         opcode[0x10];
3173         u8         reserved_0[0x10];
3174
3175         u8         reserved_1[0x10];
3176         u8         op_mod[0x10];
3177
3178         u8         reserved_2[0x40];
3179 };
3180
3181 struct mlx5_ifc_query_rqt_out_bits {
3182         u8         status[0x8];
3183         u8         reserved_0[0x18];
3184
3185         u8         syndrome[0x20];
3186
3187         u8         reserved_1[0xc0];
3188
3189         struct mlx5_ifc_rqtc_bits rqt_context;
3190 };
3191
3192 struct mlx5_ifc_query_rqt_in_bits {
3193         u8         opcode[0x10];
3194         u8         reserved_0[0x10];
3195
3196         u8         reserved_1[0x10];
3197         u8         op_mod[0x10];
3198
3199         u8         reserved_2[0x8];
3200         u8         rqtn[0x18];
3201
3202         u8         reserved_3[0x20];
3203 };
3204
3205 struct mlx5_ifc_query_rq_out_bits {
3206         u8         status[0x8];
3207         u8         reserved_0[0x18];
3208
3209         u8         syndrome[0x20];
3210
3211         u8         reserved_1[0xc0];
3212
3213         struct mlx5_ifc_rqc_bits rq_context;
3214 };
3215
3216 struct mlx5_ifc_query_rq_in_bits {
3217         u8         opcode[0x10];
3218         u8         reserved_0[0x10];
3219
3220         u8         reserved_1[0x10];
3221         u8         op_mod[0x10];
3222
3223         u8         reserved_2[0x8];
3224         u8         rqn[0x18];
3225
3226         u8         reserved_3[0x20];
3227 };
3228
3229 struct mlx5_ifc_query_roce_address_out_bits {
3230         u8         status[0x8];
3231         u8         reserved_0[0x18];
3232
3233         u8         syndrome[0x20];
3234
3235         u8         reserved_1[0x40];
3236
3237         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3238 };
3239
3240 struct mlx5_ifc_query_roce_address_in_bits {
3241         u8         opcode[0x10];
3242         u8         reserved_0[0x10];
3243
3244         u8         reserved_1[0x10];
3245         u8         op_mod[0x10];
3246
3247         u8         roce_address_index[0x10];
3248         u8         reserved_2[0x10];
3249
3250         u8         reserved_3[0x20];
3251 };
3252
3253 struct mlx5_ifc_query_rmp_out_bits {
3254         u8         status[0x8];
3255         u8         reserved_0[0x18];
3256
3257         u8         syndrome[0x20];
3258
3259         u8         reserved_1[0xc0];
3260
3261         struct mlx5_ifc_rmpc_bits rmp_context;
3262 };
3263
3264 struct mlx5_ifc_query_rmp_in_bits {
3265         u8         opcode[0x10];
3266         u8         reserved_0[0x10];
3267
3268         u8         reserved_1[0x10];
3269         u8         op_mod[0x10];
3270
3271         u8         reserved_2[0x8];
3272         u8         rmpn[0x18];
3273
3274         u8         reserved_3[0x20];
3275 };
3276
3277 struct mlx5_ifc_query_qp_out_bits {
3278         u8         status[0x8];
3279         u8         reserved_0[0x18];
3280
3281         u8         syndrome[0x20];
3282
3283         u8         reserved_1[0x40];
3284
3285         u8         opt_param_mask[0x20];
3286
3287         u8         reserved_2[0x20];
3288
3289         struct mlx5_ifc_qpc_bits qpc;
3290
3291         u8         reserved_3[0x80];
3292
3293         u8         pas[0][0x40];
3294 };
3295
3296 struct mlx5_ifc_query_qp_in_bits {
3297         u8         opcode[0x10];
3298         u8         reserved_0[0x10];
3299
3300         u8         reserved_1[0x10];
3301         u8         op_mod[0x10];
3302
3303         u8         reserved_2[0x8];
3304         u8         qpn[0x18];
3305
3306         u8         reserved_3[0x20];
3307 };
3308
3309 struct mlx5_ifc_query_q_counter_out_bits {
3310         u8         status[0x8];
3311         u8         reserved_0[0x18];
3312
3313         u8         syndrome[0x20];
3314
3315         u8         reserved_1[0x40];
3316
3317         u8         rx_write_requests[0x20];
3318
3319         u8         reserved_2[0x20];
3320
3321         u8         rx_read_requests[0x20];
3322
3323         u8         reserved_3[0x20];
3324
3325         u8         rx_atomic_requests[0x20];
3326
3327         u8         reserved_4[0x20];
3328
3329         u8         rx_dct_connect[0x20];
3330
3331         u8         reserved_5[0x20];
3332
3333         u8         out_of_buffer[0x20];
3334
3335         u8         reserved_6[0x20];
3336
3337         u8         out_of_sequence[0x20];
3338
3339         u8         reserved_7[0x620];
3340 };
3341
3342 struct mlx5_ifc_query_q_counter_in_bits {
3343         u8         opcode[0x10];
3344         u8         reserved_0[0x10];
3345
3346         u8         reserved_1[0x10];
3347         u8         op_mod[0x10];
3348
3349         u8         reserved_2[0x80];
3350
3351         u8         clear[0x1];
3352         u8         reserved_3[0x1f];
3353
3354         u8         reserved_4[0x18];
3355         u8         counter_set_id[0x8];
3356 };
3357
3358 struct mlx5_ifc_query_pages_out_bits {
3359         u8         status[0x8];
3360         u8         reserved_0[0x18];
3361
3362         u8         syndrome[0x20];
3363
3364         u8         reserved_1[0x10];
3365         u8         function_id[0x10];
3366
3367         u8         num_pages[0x20];
3368 };
3369
3370 enum {
3371         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3372         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3373         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3374 };
3375
3376 struct mlx5_ifc_query_pages_in_bits {
3377         u8         opcode[0x10];
3378         u8         reserved_0[0x10];
3379
3380         u8         reserved_1[0x10];
3381         u8         op_mod[0x10];
3382
3383         u8         reserved_2[0x10];
3384         u8         function_id[0x10];
3385
3386         u8         reserved_3[0x20];
3387 };
3388
3389 struct mlx5_ifc_query_nic_vport_context_out_bits {
3390         u8         status[0x8];
3391         u8         reserved_0[0x18];
3392
3393         u8         syndrome[0x20];
3394
3395         u8         reserved_1[0x40];
3396
3397         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3398 };
3399
3400 struct mlx5_ifc_query_nic_vport_context_in_bits {
3401         u8         opcode[0x10];
3402         u8         reserved_0[0x10];
3403
3404         u8         reserved_1[0x10];
3405         u8         op_mod[0x10];
3406
3407         u8         other_vport[0x1];
3408         u8         reserved_2[0xf];
3409         u8         vport_number[0x10];
3410
3411         u8         reserved_3[0x5];
3412         u8         allowed_list_type[0x3];
3413         u8         reserved_4[0x18];
3414 };
3415
3416 struct mlx5_ifc_query_mkey_out_bits {
3417         u8         status[0x8];
3418         u8         reserved_0[0x18];
3419
3420         u8         syndrome[0x20];
3421
3422         u8         reserved_1[0x40];
3423
3424         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3425
3426         u8         reserved_2[0x600];
3427
3428         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3429
3430         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3431 };
3432
3433 struct mlx5_ifc_query_mkey_in_bits {
3434         u8         opcode[0x10];
3435         u8         reserved_0[0x10];
3436
3437         u8         reserved_1[0x10];
3438         u8         op_mod[0x10];
3439
3440         u8         reserved_2[0x8];
3441         u8         mkey_index[0x18];
3442
3443         u8         pg_access[0x1];
3444         u8         reserved_3[0x1f];
3445 };
3446
3447 struct mlx5_ifc_query_mad_demux_out_bits {
3448         u8         status[0x8];
3449         u8         reserved_0[0x18];
3450
3451         u8         syndrome[0x20];
3452
3453         u8         reserved_1[0x40];
3454
3455         u8         mad_dumux_parameters_block[0x20];
3456 };
3457
3458 struct mlx5_ifc_query_mad_demux_in_bits {
3459         u8         opcode[0x10];
3460         u8         reserved_0[0x10];
3461
3462         u8         reserved_1[0x10];
3463         u8         op_mod[0x10];
3464
3465         u8         reserved_2[0x40];
3466 };
3467
3468 struct mlx5_ifc_query_l2_table_entry_out_bits {
3469         u8         status[0x8];
3470         u8         reserved_0[0x18];
3471
3472         u8         syndrome[0x20];
3473
3474         u8         reserved_1[0xa0];
3475
3476         u8         reserved_2[0x13];
3477         u8         vlan_valid[0x1];
3478         u8         vlan[0xc];
3479
3480         struct mlx5_ifc_mac_address_layout_bits mac_address;
3481
3482         u8         reserved_3[0xc0];
3483 };
3484
3485 struct mlx5_ifc_query_l2_table_entry_in_bits {
3486         u8         opcode[0x10];
3487         u8         reserved_0[0x10];
3488
3489         u8         reserved_1[0x10];
3490         u8         op_mod[0x10];
3491
3492         u8         reserved_2[0x60];
3493
3494         u8         reserved_3[0x8];
3495         u8         table_index[0x18];
3496
3497         u8         reserved_4[0x140];
3498 };
3499
3500 struct mlx5_ifc_query_issi_out_bits {
3501         u8         status[0x8];
3502         u8         reserved_0[0x18];
3503
3504         u8         syndrome[0x20];
3505
3506         u8         reserved_1[0x10];
3507         u8         current_issi[0x10];
3508
3509         u8         reserved_2[0xa0];
3510
3511         u8         supported_issi_reserved[76][0x8];
3512         u8         supported_issi_dw0[0x20];
3513 };
3514
3515 struct mlx5_ifc_query_issi_in_bits {
3516         u8         opcode[0x10];
3517         u8         reserved_0[0x10];
3518
3519         u8         reserved_1[0x10];
3520         u8         op_mod[0x10];
3521
3522         u8         reserved_2[0x40];
3523 };
3524
3525 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3526         u8         status[0x8];
3527         u8         reserved_0[0x18];
3528
3529         u8         syndrome[0x20];
3530
3531         u8         reserved_1[0x40];
3532
3533         struct mlx5_ifc_pkey_bits pkey[0];
3534 };
3535
3536 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3537         u8         opcode[0x10];
3538         u8         reserved_0[0x10];
3539
3540         u8         reserved_1[0x10];
3541         u8         op_mod[0x10];
3542
3543         u8         other_vport[0x1];
3544         u8         reserved_2[0xb];
3545         u8         port_num[0x4];
3546         u8         vport_number[0x10];
3547
3548         u8         reserved_3[0x10];
3549         u8         pkey_index[0x10];
3550 };
3551
3552 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3553         u8         status[0x8];
3554         u8         reserved_0[0x18];
3555
3556         u8         syndrome[0x20];
3557
3558         u8         reserved_1[0x20];
3559
3560         u8         gids_num[0x10];
3561         u8         reserved_2[0x10];
3562
3563         struct mlx5_ifc_array128_auto_bits gid[0];
3564 };
3565
3566 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3567         u8         opcode[0x10];
3568         u8         reserved_0[0x10];
3569
3570         u8         reserved_1[0x10];
3571         u8         op_mod[0x10];
3572
3573         u8         other_vport[0x1];
3574         u8         reserved_2[0xb];
3575         u8         port_num[0x4];
3576         u8         vport_number[0x10];
3577
3578         u8         reserved_3[0x10];
3579         u8         gid_index[0x10];
3580 };
3581
3582 struct mlx5_ifc_query_hca_vport_context_out_bits {
3583         u8         status[0x8];
3584         u8         reserved_0[0x18];
3585
3586         u8         syndrome[0x20];
3587
3588         u8         reserved_1[0x40];
3589
3590         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3591 };
3592
3593 struct mlx5_ifc_query_hca_vport_context_in_bits {
3594         u8         opcode[0x10];
3595         u8         reserved_0[0x10];
3596
3597         u8         reserved_1[0x10];
3598         u8         op_mod[0x10];
3599
3600         u8         other_vport[0x1];
3601         u8         reserved_2[0xb];
3602         u8         port_num[0x4];
3603         u8         vport_number[0x10];
3604
3605         u8         reserved_3[0x20];
3606 };
3607
3608 struct mlx5_ifc_query_hca_cap_out_bits {
3609         u8         status[0x8];
3610         u8         reserved_0[0x18];
3611
3612         u8         syndrome[0x20];
3613
3614         u8         reserved_1[0x40];
3615
3616         union mlx5_ifc_hca_cap_union_bits capability;
3617 };
3618
3619 struct mlx5_ifc_query_hca_cap_in_bits {
3620         u8         opcode[0x10];
3621         u8         reserved_0[0x10];
3622
3623         u8         reserved_1[0x10];
3624         u8         op_mod[0x10];
3625
3626         u8         reserved_2[0x40];
3627 };
3628
3629 struct mlx5_ifc_query_flow_table_out_bits {
3630         u8         status[0x8];
3631         u8         reserved_0[0x18];
3632
3633         u8         syndrome[0x20];
3634
3635         u8         reserved_1[0x80];
3636
3637         u8         reserved_2[0x8];
3638         u8         level[0x8];
3639         u8         reserved_3[0x8];
3640         u8         log_size[0x8];
3641
3642         u8         reserved_4[0x120];
3643 };
3644
3645 struct mlx5_ifc_query_flow_table_in_bits {
3646         u8         opcode[0x10];
3647         u8         reserved_0[0x10];
3648
3649         u8         reserved_1[0x10];
3650         u8         op_mod[0x10];
3651
3652         u8         reserved_2[0x40];
3653
3654         u8         table_type[0x8];
3655         u8         reserved_3[0x18];
3656
3657         u8         reserved_4[0x8];
3658         u8         table_id[0x18];
3659
3660         u8         reserved_5[0x140];
3661 };
3662
3663 struct mlx5_ifc_query_fte_out_bits {
3664         u8         status[0x8];
3665         u8         reserved_0[0x18];
3666
3667         u8         syndrome[0x20];
3668
3669         u8         reserved_1[0x1c0];
3670
3671         struct mlx5_ifc_flow_context_bits flow_context;
3672 };
3673
3674 struct mlx5_ifc_query_fte_in_bits {
3675         u8         opcode[0x10];
3676         u8         reserved_0[0x10];
3677
3678         u8         reserved_1[0x10];
3679         u8         op_mod[0x10];
3680
3681         u8         reserved_2[0x40];
3682
3683         u8         table_type[0x8];
3684         u8         reserved_3[0x18];
3685
3686         u8         reserved_4[0x8];
3687         u8         table_id[0x18];
3688
3689         u8         reserved_5[0x40];
3690
3691         u8         flow_index[0x20];
3692
3693         u8         reserved_6[0xe0];
3694 };
3695
3696 enum {
3697         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
3698         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
3699         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
3700 };
3701
3702 struct mlx5_ifc_query_flow_group_out_bits {
3703         u8         status[0x8];
3704         u8         reserved_0[0x18];
3705
3706         u8         syndrome[0x20];
3707
3708         u8         reserved_1[0xa0];
3709
3710         u8         start_flow_index[0x20];
3711
3712         u8         reserved_2[0x20];
3713
3714         u8         end_flow_index[0x20];
3715
3716         u8         reserved_3[0xa0];
3717
3718         u8         reserved_4[0x18];
3719         u8         match_criteria_enable[0x8];
3720
3721         struct mlx5_ifc_fte_match_param_bits match_criteria;
3722
3723         u8         reserved_5[0xe00];
3724 };
3725
3726 struct mlx5_ifc_query_flow_group_in_bits {
3727         u8         opcode[0x10];
3728         u8         reserved_0[0x10];
3729
3730         u8         reserved_1[0x10];
3731         u8         op_mod[0x10];
3732
3733         u8         reserved_2[0x40];
3734
3735         u8         table_type[0x8];
3736         u8         reserved_3[0x18];
3737
3738         u8         reserved_4[0x8];
3739         u8         table_id[0x18];
3740
3741         u8         group_id[0x20];
3742
3743         u8         reserved_5[0x120];
3744 };
3745
3746 struct mlx5_ifc_query_eq_out_bits {
3747         u8         status[0x8];
3748         u8         reserved_0[0x18];
3749
3750         u8         syndrome[0x20];
3751
3752         u8         reserved_1[0x40];
3753
3754         struct mlx5_ifc_eqc_bits eq_context_entry;
3755
3756         u8         reserved_2[0x40];
3757
3758         u8         event_bitmask[0x40];
3759
3760         u8         reserved_3[0x580];
3761
3762         u8         pas[0][0x40];
3763 };
3764
3765 struct mlx5_ifc_query_eq_in_bits {
3766         u8         opcode[0x10];
3767         u8         reserved_0[0x10];
3768
3769         u8         reserved_1[0x10];
3770         u8         op_mod[0x10];
3771
3772         u8         reserved_2[0x18];
3773         u8         eq_number[0x8];
3774
3775         u8         reserved_3[0x20];
3776 };
3777
3778 struct mlx5_ifc_query_dct_out_bits {
3779         u8         status[0x8];
3780         u8         reserved_0[0x18];
3781
3782         u8         syndrome[0x20];
3783
3784         u8         reserved_1[0x40];
3785
3786         struct mlx5_ifc_dctc_bits dct_context_entry;
3787
3788         u8         reserved_2[0x180];
3789 };
3790
3791 struct mlx5_ifc_query_dct_in_bits {
3792         u8         opcode[0x10];
3793         u8         reserved_0[0x10];
3794
3795         u8         reserved_1[0x10];
3796         u8         op_mod[0x10];
3797
3798         u8         reserved_2[0x8];
3799         u8         dctn[0x18];
3800
3801         u8         reserved_3[0x20];
3802 };
3803
3804 struct mlx5_ifc_query_cq_out_bits {
3805         u8         status[0x8];
3806         u8         reserved_0[0x18];
3807
3808         u8         syndrome[0x20];
3809
3810         u8         reserved_1[0x40];
3811
3812         struct mlx5_ifc_cqc_bits cq_context;
3813
3814         u8         reserved_2[0x600];
3815
3816         u8         pas[0][0x40];
3817 };
3818
3819 struct mlx5_ifc_query_cq_in_bits {
3820         u8         opcode[0x10];
3821         u8         reserved_0[0x10];
3822
3823         u8         reserved_1[0x10];
3824         u8         op_mod[0x10];
3825
3826         u8         reserved_2[0x8];
3827         u8         cqn[0x18];
3828
3829         u8         reserved_3[0x20];
3830 };
3831
3832 struct mlx5_ifc_query_cong_status_out_bits {
3833         u8         status[0x8];
3834         u8         reserved_0[0x18];
3835
3836         u8         syndrome[0x20];
3837
3838         u8         reserved_1[0x20];
3839
3840         u8         enable[0x1];
3841         u8         tag_enable[0x1];
3842         u8         reserved_2[0x1e];
3843 };
3844
3845 struct mlx5_ifc_query_cong_status_in_bits {
3846         u8         opcode[0x10];
3847         u8         reserved_0[0x10];
3848
3849         u8         reserved_1[0x10];
3850         u8         op_mod[0x10];
3851
3852         u8         reserved_2[0x18];
3853         u8         priority[0x4];
3854         u8         cong_protocol[0x4];
3855
3856         u8         reserved_3[0x20];
3857 };
3858
3859 struct mlx5_ifc_query_cong_statistics_out_bits {
3860         u8         status[0x8];
3861         u8         reserved_0[0x18];
3862
3863         u8         syndrome[0x20];
3864
3865         u8         reserved_1[0x40];
3866
3867         u8         cur_flows[0x20];
3868
3869         u8         sum_flows[0x20];
3870
3871         u8         cnp_ignored_high[0x20];
3872
3873         u8         cnp_ignored_low[0x20];
3874
3875         u8         cnp_handled_high[0x20];
3876
3877         u8         cnp_handled_low[0x20];
3878
3879         u8         reserved_2[0x100];
3880
3881         u8         time_stamp_high[0x20];
3882
3883         u8         time_stamp_low[0x20];
3884
3885         u8         accumulators_period[0x20];
3886
3887         u8         ecn_marked_roce_packets_high[0x20];
3888
3889         u8         ecn_marked_roce_packets_low[0x20];
3890
3891         u8         cnps_sent_high[0x20];
3892
3893         u8         cnps_sent_low[0x20];
3894
3895         u8         reserved_3[0x560];
3896 };
3897
3898 struct mlx5_ifc_query_cong_statistics_in_bits {
3899         u8         opcode[0x10];
3900         u8         reserved_0[0x10];
3901
3902         u8         reserved_1[0x10];
3903         u8         op_mod[0x10];
3904
3905         u8         clear[0x1];
3906         u8         reserved_2[0x1f];
3907
3908         u8         reserved_3[0x20];
3909 };
3910
3911 struct mlx5_ifc_query_cong_params_out_bits {
3912         u8         status[0x8];
3913         u8         reserved_0[0x18];
3914
3915         u8         syndrome[0x20];
3916
3917         u8         reserved_1[0x40];
3918
3919         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
3920 };
3921
3922 struct mlx5_ifc_query_cong_params_in_bits {
3923         u8         opcode[0x10];
3924         u8         reserved_0[0x10];
3925
3926         u8         reserved_1[0x10];
3927         u8         op_mod[0x10];
3928
3929         u8         reserved_2[0x1c];
3930         u8         cong_protocol[0x4];
3931
3932         u8         reserved_3[0x20];
3933 };
3934
3935 struct mlx5_ifc_query_adapter_out_bits {
3936         u8         status[0x8];
3937         u8         reserved_0[0x18];
3938
3939         u8         syndrome[0x20];
3940
3941         u8         reserved_1[0x40];
3942
3943         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
3944 };
3945
3946 struct mlx5_ifc_query_adapter_in_bits {
3947         u8         opcode[0x10];
3948         u8         reserved_0[0x10];
3949
3950         u8         reserved_1[0x10];
3951         u8         op_mod[0x10];
3952
3953         u8         reserved_2[0x40];
3954 };
3955
3956 struct mlx5_ifc_qp_2rst_out_bits {
3957         u8         status[0x8];
3958         u8         reserved_0[0x18];
3959
3960         u8         syndrome[0x20];
3961
3962         u8         reserved_1[0x40];
3963 };
3964
3965 struct mlx5_ifc_qp_2rst_in_bits {
3966         u8         opcode[0x10];
3967         u8         reserved_0[0x10];
3968
3969         u8         reserved_1[0x10];
3970         u8         op_mod[0x10];
3971
3972         u8         reserved_2[0x8];
3973         u8         qpn[0x18];
3974
3975         u8         reserved_3[0x20];
3976 };
3977
3978 struct mlx5_ifc_qp_2err_out_bits {
3979         u8         status[0x8];
3980         u8         reserved_0[0x18];
3981
3982         u8         syndrome[0x20];
3983
3984         u8         reserved_1[0x40];
3985 };
3986
3987 struct mlx5_ifc_qp_2err_in_bits {
3988         u8         opcode[0x10];
3989         u8         reserved_0[0x10];
3990
3991         u8         reserved_1[0x10];
3992         u8         op_mod[0x10];
3993
3994         u8         reserved_2[0x8];
3995         u8         qpn[0x18];
3996
3997         u8         reserved_3[0x20];
3998 };
3999
4000 struct mlx5_ifc_page_fault_resume_out_bits {
4001         u8         status[0x8];
4002         u8         reserved_0[0x18];
4003
4004         u8         syndrome[0x20];
4005
4006         u8         reserved_1[0x40];
4007 };
4008
4009 struct mlx5_ifc_page_fault_resume_in_bits {
4010         u8         opcode[0x10];
4011         u8         reserved_0[0x10];
4012
4013         u8         reserved_1[0x10];
4014         u8         op_mod[0x10];
4015
4016         u8         error[0x1];
4017         u8         reserved_2[0x4];
4018         u8         rdma[0x1];
4019         u8         read_write[0x1];
4020         u8         req_res[0x1];
4021         u8         qpn[0x18];
4022
4023         u8         reserved_3[0x20];
4024 };
4025
4026 struct mlx5_ifc_nop_out_bits {
4027         u8         status[0x8];
4028         u8         reserved_0[0x18];
4029
4030         u8         syndrome[0x20];
4031
4032         u8         reserved_1[0x40];
4033 };
4034
4035 struct mlx5_ifc_nop_in_bits {
4036         u8         opcode[0x10];
4037         u8         reserved_0[0x10];
4038
4039         u8         reserved_1[0x10];
4040         u8         op_mod[0x10];
4041
4042         u8         reserved_2[0x40];
4043 };
4044
4045 struct mlx5_ifc_modify_vport_state_out_bits {
4046         u8         status[0x8];
4047         u8         reserved_0[0x18];
4048
4049         u8         syndrome[0x20];
4050
4051         u8         reserved_1[0x40];
4052 };
4053
4054 struct mlx5_ifc_modify_vport_state_in_bits {
4055         u8         opcode[0x10];
4056         u8         reserved_0[0x10];
4057
4058         u8         reserved_1[0x10];
4059         u8         op_mod[0x10];
4060
4061         u8         other_vport[0x1];
4062         u8         reserved_2[0xf];
4063         u8         vport_number[0x10];
4064
4065         u8         reserved_3[0x18];
4066         u8         admin_state[0x4];
4067         u8         reserved_4[0x4];
4068 };
4069
4070 struct mlx5_ifc_modify_tis_out_bits {
4071         u8         status[0x8];
4072         u8         reserved_0[0x18];
4073
4074         u8         syndrome[0x20];
4075
4076         u8         reserved_1[0x40];
4077 };
4078
4079 struct mlx5_ifc_modify_tis_in_bits {
4080         u8         opcode[0x10];
4081         u8         reserved_0[0x10];
4082
4083         u8         reserved_1[0x10];
4084         u8         op_mod[0x10];
4085
4086         u8         reserved_2[0x8];
4087         u8         tisn[0x18];
4088
4089         u8         reserved_3[0x20];
4090
4091         u8         modify_bitmask[0x40];
4092
4093         u8         reserved_4[0x40];
4094
4095         struct mlx5_ifc_tisc_bits ctx;
4096 };
4097
4098 struct mlx5_ifc_modify_tir_bitmask_bits {
4099         u8         reserved_0[0x20];
4100
4101         u8         reserved_1[0x1b];
4102         u8         self_lb_en[0x1];
4103         u8         reserved_2[0x3];
4104         u8         lro[0x1];
4105 };
4106
4107 struct mlx5_ifc_modify_tir_out_bits {
4108         u8         status[0x8];
4109         u8         reserved_0[0x18];
4110
4111         u8         syndrome[0x20];
4112
4113         u8         reserved_1[0x40];
4114 };
4115
4116 struct mlx5_ifc_modify_tir_in_bits {
4117         u8         opcode[0x10];
4118         u8         reserved_0[0x10];
4119
4120         u8         reserved_1[0x10];
4121         u8         op_mod[0x10];
4122
4123         u8         reserved_2[0x8];
4124         u8         tirn[0x18];
4125
4126         u8         reserved_3[0x20];
4127
4128         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4129
4130         u8         reserved_4[0x40];
4131
4132         struct mlx5_ifc_tirc_bits ctx;
4133 };
4134
4135 struct mlx5_ifc_modify_sq_out_bits {
4136         u8         status[0x8];
4137         u8         reserved_0[0x18];
4138
4139         u8         syndrome[0x20];
4140
4141         u8         reserved_1[0x40];
4142 };
4143
4144 struct mlx5_ifc_modify_sq_in_bits {
4145         u8         opcode[0x10];
4146         u8         reserved_0[0x10];
4147
4148         u8         reserved_1[0x10];
4149         u8         op_mod[0x10];
4150
4151         u8         sq_state[0x4];
4152         u8         reserved_2[0x4];
4153         u8         sqn[0x18];
4154
4155         u8         reserved_3[0x20];
4156
4157         u8         modify_bitmask[0x40];
4158
4159         u8         reserved_4[0x40];
4160
4161         struct mlx5_ifc_sqc_bits ctx;
4162 };
4163
4164 struct mlx5_ifc_modify_rqt_out_bits {
4165         u8         status[0x8];
4166         u8         reserved_0[0x18];
4167
4168         u8         syndrome[0x20];
4169
4170         u8         reserved_1[0x40];
4171 };
4172
4173 struct mlx5_ifc_rqt_bitmask_bits {
4174         u8         reserved[0x20];
4175
4176         u8         reserved1[0x1f];
4177         u8         rqn_list[0x1];
4178 };
4179
4180 struct mlx5_ifc_modify_rqt_in_bits {
4181         u8         opcode[0x10];
4182         u8         reserved_0[0x10];
4183
4184         u8         reserved_1[0x10];
4185         u8         op_mod[0x10];
4186
4187         u8         reserved_2[0x8];
4188         u8         rqtn[0x18];
4189
4190         u8         reserved_3[0x20];
4191
4192         struct mlx5_ifc_rqt_bitmask_bits bitmask;
4193
4194         u8         reserved_4[0x40];
4195
4196         struct mlx5_ifc_rqtc_bits ctx;
4197 };
4198
4199 struct mlx5_ifc_modify_rq_out_bits {
4200         u8         status[0x8];
4201         u8         reserved_0[0x18];
4202
4203         u8         syndrome[0x20];
4204
4205         u8         reserved_1[0x40];
4206 };
4207
4208 struct mlx5_ifc_modify_rq_in_bits {
4209         u8         opcode[0x10];
4210         u8         reserved_0[0x10];
4211
4212         u8         reserved_1[0x10];
4213         u8         op_mod[0x10];
4214
4215         u8         rq_state[0x4];
4216         u8         reserved_2[0x4];
4217         u8         rqn[0x18];
4218
4219         u8         reserved_3[0x20];
4220
4221         u8         modify_bitmask[0x40];
4222
4223         u8         reserved_4[0x40];
4224
4225         struct mlx5_ifc_rqc_bits ctx;
4226 };
4227
4228 struct mlx5_ifc_modify_rmp_out_bits {
4229         u8         status[0x8];
4230         u8         reserved_0[0x18];
4231
4232         u8         syndrome[0x20];
4233
4234         u8         reserved_1[0x40];
4235 };
4236
4237 struct mlx5_ifc_rmp_bitmask_bits {
4238         u8         reserved[0x20];
4239
4240         u8         reserved1[0x1f];
4241         u8         lwm[0x1];
4242 };
4243
4244 struct mlx5_ifc_modify_rmp_in_bits {
4245         u8         opcode[0x10];
4246         u8         reserved_0[0x10];
4247
4248         u8         reserved_1[0x10];
4249         u8         op_mod[0x10];
4250
4251         u8         rmp_state[0x4];
4252         u8         reserved_2[0x4];
4253         u8         rmpn[0x18];
4254
4255         u8         reserved_3[0x20];
4256
4257         struct mlx5_ifc_rmp_bitmask_bits bitmask;
4258
4259         u8         reserved_4[0x40];
4260
4261         struct mlx5_ifc_rmpc_bits ctx;
4262 };
4263
4264 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4265         u8         status[0x8];
4266         u8         reserved_0[0x18];
4267
4268         u8         syndrome[0x20];
4269
4270         u8         reserved_1[0x40];
4271 };
4272
4273 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4274         u8         reserved_0[0x19];
4275         u8         mtu[0x1];
4276         u8         change_event[0x1];
4277         u8         promisc[0x1];
4278         u8         permanent_address[0x1];
4279         u8         addresses_list[0x1];
4280         u8         roce_en[0x1];
4281         u8         reserved_1[0x1];
4282 };
4283
4284 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4285         u8         opcode[0x10];
4286         u8         reserved_0[0x10];
4287
4288         u8         reserved_1[0x10];
4289         u8         op_mod[0x10];
4290
4291         u8         other_vport[0x1];
4292         u8         reserved_2[0xf];
4293         u8         vport_number[0x10];
4294
4295         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4296
4297         u8         reserved_3[0x780];
4298
4299         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4300 };
4301
4302 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4303         u8         status[0x8];
4304         u8         reserved_0[0x18];
4305
4306         u8         syndrome[0x20];
4307
4308         u8         reserved_1[0x40];
4309 };
4310
4311 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4312         u8         opcode[0x10];
4313         u8         reserved_0[0x10];
4314
4315         u8         reserved_1[0x10];
4316         u8         op_mod[0x10];
4317
4318         u8         other_vport[0x1];
4319         u8         reserved_2[0xb];
4320         u8         port_num[0x4];
4321         u8         vport_number[0x10];
4322
4323         u8         reserved_3[0x20];
4324
4325         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4326 };
4327
4328 struct mlx5_ifc_modify_cq_out_bits {
4329         u8         status[0x8];
4330         u8         reserved_0[0x18];
4331
4332         u8         syndrome[0x20];
4333
4334         u8         reserved_1[0x40];
4335 };
4336
4337 enum {
4338         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
4339         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
4340 };
4341
4342 struct mlx5_ifc_modify_cq_in_bits {
4343         u8         opcode[0x10];
4344         u8         reserved_0[0x10];
4345
4346         u8         reserved_1[0x10];
4347         u8         op_mod[0x10];
4348
4349         u8         reserved_2[0x8];
4350         u8         cqn[0x18];
4351
4352         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4353
4354         struct mlx5_ifc_cqc_bits cq_context;
4355
4356         u8         reserved_3[0x600];
4357
4358         u8         pas[0][0x40];
4359 };
4360
4361 struct mlx5_ifc_modify_cong_status_out_bits {
4362         u8         status[0x8];
4363         u8         reserved_0[0x18];
4364
4365         u8         syndrome[0x20];
4366
4367         u8         reserved_1[0x40];
4368 };
4369
4370 struct mlx5_ifc_modify_cong_status_in_bits {
4371         u8         opcode[0x10];
4372         u8         reserved_0[0x10];
4373
4374         u8         reserved_1[0x10];
4375         u8         op_mod[0x10];
4376
4377         u8         reserved_2[0x18];
4378         u8         priority[0x4];
4379         u8         cong_protocol[0x4];
4380
4381         u8         enable[0x1];
4382         u8         tag_enable[0x1];
4383         u8         reserved_3[0x1e];
4384 };
4385
4386 struct mlx5_ifc_modify_cong_params_out_bits {
4387         u8         status[0x8];
4388         u8         reserved_0[0x18];
4389
4390         u8         syndrome[0x20];
4391
4392         u8         reserved_1[0x40];
4393 };
4394
4395 struct mlx5_ifc_modify_cong_params_in_bits {
4396         u8         opcode[0x10];
4397         u8         reserved_0[0x10];
4398
4399         u8         reserved_1[0x10];
4400         u8         op_mod[0x10];
4401
4402         u8         reserved_2[0x1c];
4403         u8         cong_protocol[0x4];
4404
4405         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4406
4407         u8         reserved_3[0x80];
4408
4409         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4410 };
4411
4412 struct mlx5_ifc_manage_pages_out_bits {
4413         u8         status[0x8];
4414         u8         reserved_0[0x18];
4415
4416         u8         syndrome[0x20];
4417
4418         u8         output_num_entries[0x20];
4419
4420         u8         reserved_1[0x20];
4421
4422         u8         pas[0][0x40];
4423 };
4424
4425 enum {
4426         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
4427         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
4428         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
4429 };
4430
4431 struct mlx5_ifc_manage_pages_in_bits {
4432         u8         opcode[0x10];
4433         u8         reserved_0[0x10];
4434
4435         u8         reserved_1[0x10];
4436         u8         op_mod[0x10];
4437
4438         u8         reserved_2[0x10];
4439         u8         function_id[0x10];
4440
4441         u8         input_num_entries[0x20];
4442
4443         u8         pas[0][0x40];
4444 };
4445
4446 struct mlx5_ifc_mad_ifc_out_bits {
4447         u8         status[0x8];
4448         u8         reserved_0[0x18];
4449
4450         u8         syndrome[0x20];
4451
4452         u8         reserved_1[0x40];
4453
4454         u8         response_mad_packet[256][0x8];
4455 };
4456
4457 struct mlx5_ifc_mad_ifc_in_bits {
4458         u8         opcode[0x10];
4459         u8         reserved_0[0x10];
4460
4461         u8         reserved_1[0x10];
4462         u8         op_mod[0x10];
4463
4464         u8         remote_lid[0x10];
4465         u8         reserved_2[0x8];
4466         u8         port[0x8];
4467
4468         u8         reserved_3[0x20];
4469
4470         u8         mad[256][0x8];
4471 };
4472
4473 struct mlx5_ifc_init_hca_out_bits {
4474         u8         status[0x8];
4475         u8         reserved_0[0x18];
4476
4477         u8         syndrome[0x20];
4478
4479         u8         reserved_1[0x40];
4480 };
4481
4482 struct mlx5_ifc_init_hca_in_bits {
4483         u8         opcode[0x10];
4484         u8         reserved_0[0x10];
4485
4486         u8         reserved_1[0x10];
4487         u8         op_mod[0x10];
4488
4489         u8         reserved_2[0x40];
4490 };
4491
4492 struct mlx5_ifc_init2rtr_qp_out_bits {
4493         u8         status[0x8];
4494         u8         reserved_0[0x18];
4495
4496         u8         syndrome[0x20];
4497
4498         u8         reserved_1[0x40];
4499 };
4500
4501 struct mlx5_ifc_init2rtr_qp_in_bits {
4502         u8         opcode[0x10];
4503         u8         reserved_0[0x10];
4504
4505         u8         reserved_1[0x10];
4506         u8         op_mod[0x10];
4507
4508         u8         reserved_2[0x8];
4509         u8         qpn[0x18];
4510
4511         u8         reserved_3[0x20];
4512
4513         u8         opt_param_mask[0x20];
4514
4515         u8         reserved_4[0x20];
4516
4517         struct mlx5_ifc_qpc_bits qpc;
4518
4519         u8         reserved_5[0x80];
4520 };
4521
4522 struct mlx5_ifc_init2init_qp_out_bits {
4523         u8         status[0x8];
4524         u8         reserved_0[0x18];
4525
4526         u8         syndrome[0x20];
4527
4528         u8         reserved_1[0x40];
4529 };
4530
4531 struct mlx5_ifc_init2init_qp_in_bits {
4532         u8         opcode[0x10];
4533         u8         reserved_0[0x10];
4534
4535         u8         reserved_1[0x10];
4536         u8         op_mod[0x10];
4537
4538         u8         reserved_2[0x8];
4539         u8         qpn[0x18];
4540
4541         u8         reserved_3[0x20];
4542
4543         u8         opt_param_mask[0x20];
4544
4545         u8         reserved_4[0x20];
4546
4547         struct mlx5_ifc_qpc_bits qpc;
4548
4549         u8         reserved_5[0x80];
4550 };
4551
4552 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4553         u8         status[0x8];
4554         u8         reserved_0[0x18];
4555
4556         u8         syndrome[0x20];
4557
4558         u8         reserved_1[0x40];
4559
4560         u8         packet_headers_log[128][0x8];
4561
4562         u8         packet_syndrome[64][0x8];
4563 };
4564
4565 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4566         u8         opcode[0x10];
4567         u8         reserved_0[0x10];
4568
4569         u8         reserved_1[0x10];
4570         u8         op_mod[0x10];
4571
4572         u8         reserved_2[0x40];
4573 };
4574
4575 struct mlx5_ifc_gen_eqe_in_bits {
4576         u8         opcode[0x10];
4577         u8         reserved_0[0x10];
4578
4579         u8         reserved_1[0x10];
4580         u8         op_mod[0x10];
4581
4582         u8         reserved_2[0x18];
4583         u8         eq_number[0x8];
4584
4585         u8         reserved_3[0x20];
4586
4587         u8         eqe[64][0x8];
4588 };
4589
4590 struct mlx5_ifc_gen_eq_out_bits {
4591         u8         status[0x8];
4592         u8         reserved_0[0x18];
4593
4594         u8         syndrome[0x20];
4595
4596         u8         reserved_1[0x40];
4597 };
4598
4599 struct mlx5_ifc_enable_hca_out_bits {
4600         u8         status[0x8];
4601         u8         reserved_0[0x18];
4602
4603         u8         syndrome[0x20];
4604
4605         u8         reserved_1[0x20];
4606 };
4607
4608 struct mlx5_ifc_enable_hca_in_bits {
4609         u8         opcode[0x10];
4610         u8         reserved_0[0x10];
4611
4612         u8         reserved_1[0x10];
4613         u8         op_mod[0x10];
4614
4615         u8         reserved_2[0x10];
4616         u8         function_id[0x10];
4617
4618         u8         reserved_3[0x20];
4619 };
4620
4621 struct mlx5_ifc_drain_dct_out_bits {
4622         u8         status[0x8];
4623         u8         reserved_0[0x18];
4624
4625         u8         syndrome[0x20];
4626
4627         u8         reserved_1[0x40];
4628 };
4629
4630 struct mlx5_ifc_drain_dct_in_bits {
4631         u8         opcode[0x10];
4632         u8         reserved_0[0x10];
4633
4634         u8         reserved_1[0x10];
4635         u8         op_mod[0x10];
4636
4637         u8         reserved_2[0x8];
4638         u8         dctn[0x18];
4639
4640         u8         reserved_3[0x20];
4641 };
4642
4643 struct mlx5_ifc_disable_hca_out_bits {
4644         u8         status[0x8];
4645         u8         reserved_0[0x18];
4646
4647         u8         syndrome[0x20];
4648
4649         u8         reserved_1[0x20];
4650 };
4651
4652 struct mlx5_ifc_disable_hca_in_bits {
4653         u8         opcode[0x10];
4654         u8         reserved_0[0x10];
4655
4656         u8         reserved_1[0x10];
4657         u8         op_mod[0x10];
4658
4659         u8         reserved_2[0x10];
4660         u8         function_id[0x10];
4661
4662         u8         reserved_3[0x20];
4663 };
4664
4665 struct mlx5_ifc_detach_from_mcg_out_bits {
4666         u8         status[0x8];
4667         u8         reserved_0[0x18];
4668
4669         u8         syndrome[0x20];
4670
4671         u8         reserved_1[0x40];
4672 };
4673
4674 struct mlx5_ifc_detach_from_mcg_in_bits {
4675         u8         opcode[0x10];
4676         u8         reserved_0[0x10];
4677
4678         u8         reserved_1[0x10];
4679         u8         op_mod[0x10];
4680
4681         u8         reserved_2[0x8];
4682         u8         qpn[0x18];
4683
4684         u8         reserved_3[0x20];
4685
4686         u8         multicast_gid[16][0x8];
4687 };
4688
4689 struct mlx5_ifc_destroy_xrc_srq_out_bits {
4690         u8         status[0x8];
4691         u8         reserved_0[0x18];
4692
4693         u8         syndrome[0x20];
4694
4695         u8         reserved_1[0x40];
4696 };
4697
4698 struct mlx5_ifc_destroy_xrc_srq_in_bits {
4699         u8         opcode[0x10];
4700         u8         reserved_0[0x10];
4701
4702         u8         reserved_1[0x10];
4703         u8         op_mod[0x10];
4704
4705         u8         reserved_2[0x8];
4706         u8         xrc_srqn[0x18];
4707
4708         u8         reserved_3[0x20];
4709 };
4710
4711 struct mlx5_ifc_destroy_tis_out_bits {
4712         u8         status[0x8];
4713         u8         reserved_0[0x18];
4714
4715         u8         syndrome[0x20];
4716
4717         u8         reserved_1[0x40];
4718 };
4719
4720 struct mlx5_ifc_destroy_tis_in_bits {
4721         u8         opcode[0x10];
4722         u8         reserved_0[0x10];
4723
4724         u8         reserved_1[0x10];
4725         u8         op_mod[0x10];
4726
4727         u8         reserved_2[0x8];
4728         u8         tisn[0x18];
4729
4730         u8         reserved_3[0x20];
4731 };
4732
4733 struct mlx5_ifc_destroy_tir_out_bits {
4734         u8         status[0x8];
4735         u8         reserved_0[0x18];
4736
4737         u8         syndrome[0x20];
4738
4739         u8         reserved_1[0x40];
4740 };
4741
4742 struct mlx5_ifc_destroy_tir_in_bits {
4743         u8         opcode[0x10];
4744         u8         reserved_0[0x10];
4745
4746         u8         reserved_1[0x10];
4747         u8         op_mod[0x10];
4748
4749         u8         reserved_2[0x8];
4750         u8         tirn[0x18];
4751
4752         u8         reserved_3[0x20];
4753 };
4754
4755 struct mlx5_ifc_destroy_srq_out_bits {
4756         u8         status[0x8];
4757         u8         reserved_0[0x18];
4758
4759         u8         syndrome[0x20];
4760
4761         u8         reserved_1[0x40];
4762 };
4763
4764 struct mlx5_ifc_destroy_srq_in_bits {
4765         u8         opcode[0x10];
4766         u8         reserved_0[0x10];
4767
4768         u8         reserved_1[0x10];
4769         u8         op_mod[0x10];
4770
4771         u8         reserved_2[0x8];
4772         u8         srqn[0x18];
4773
4774         u8         reserved_3[0x20];
4775 };
4776
4777 struct mlx5_ifc_destroy_sq_out_bits {
4778         u8         status[0x8];
4779         u8         reserved_0[0x18];
4780
4781         u8         syndrome[0x20];
4782
4783         u8         reserved_1[0x40];
4784 };
4785
4786 struct mlx5_ifc_destroy_sq_in_bits {
4787         u8         opcode[0x10];
4788         u8         reserved_0[0x10];
4789
4790         u8         reserved_1[0x10];
4791         u8         op_mod[0x10];
4792
4793         u8         reserved_2[0x8];
4794         u8         sqn[0x18];
4795
4796         u8         reserved_3[0x20];
4797 };
4798
4799 struct mlx5_ifc_destroy_rqt_out_bits {
4800         u8         status[0x8];
4801         u8         reserved_0[0x18];
4802
4803         u8         syndrome[0x20];
4804
4805         u8         reserved_1[0x40];
4806 };
4807
4808 struct mlx5_ifc_destroy_rqt_in_bits {
4809         u8         opcode[0x10];
4810         u8         reserved_0[0x10];
4811
4812         u8         reserved_1[0x10];
4813         u8         op_mod[0x10];
4814
4815         u8         reserved_2[0x8];
4816         u8         rqtn[0x18];
4817
4818         u8         reserved_3[0x20];
4819 };
4820
4821 struct mlx5_ifc_destroy_rq_out_bits {
4822         u8         status[0x8];
4823         u8         reserved_0[0x18];
4824
4825         u8         syndrome[0x20];
4826
4827         u8         reserved_1[0x40];
4828 };
4829
4830 struct mlx5_ifc_destroy_rq_in_bits {
4831         u8         opcode[0x10];
4832         u8         reserved_0[0x10];
4833
4834         u8         reserved_1[0x10];
4835         u8         op_mod[0x10];
4836
4837         u8         reserved_2[0x8];
4838         u8         rqn[0x18];
4839
4840         u8         reserved_3[0x20];
4841 };
4842
4843 struct mlx5_ifc_destroy_rmp_out_bits {
4844         u8         status[0x8];
4845         u8         reserved_0[0x18];
4846
4847         u8         syndrome[0x20];
4848
4849         u8         reserved_1[0x40];
4850 };
4851
4852 struct mlx5_ifc_destroy_rmp_in_bits {
4853         u8         opcode[0x10];
4854         u8         reserved_0[0x10];
4855
4856         u8         reserved_1[0x10];
4857         u8         op_mod[0x10];
4858
4859         u8         reserved_2[0x8];
4860         u8         rmpn[0x18];
4861
4862         u8         reserved_3[0x20];
4863 };
4864
4865 struct mlx5_ifc_destroy_qp_out_bits {
4866         u8         status[0x8];
4867         u8         reserved_0[0x18];
4868
4869         u8         syndrome[0x20];
4870
4871         u8         reserved_1[0x40];
4872 };
4873
4874 struct mlx5_ifc_destroy_qp_in_bits {
4875         u8         opcode[0x10];
4876         u8         reserved_0[0x10];
4877
4878         u8         reserved_1[0x10];
4879         u8         op_mod[0x10];
4880
4881         u8         reserved_2[0x8];
4882         u8         qpn[0x18];
4883
4884         u8         reserved_3[0x20];
4885 };
4886
4887 struct mlx5_ifc_destroy_psv_out_bits {
4888         u8         status[0x8];
4889         u8         reserved_0[0x18];
4890
4891         u8         syndrome[0x20];
4892
4893         u8         reserved_1[0x40];
4894 };
4895
4896 struct mlx5_ifc_destroy_psv_in_bits {
4897         u8         opcode[0x10];
4898         u8         reserved_0[0x10];
4899
4900         u8         reserved_1[0x10];
4901         u8         op_mod[0x10];
4902
4903         u8         reserved_2[0x8];
4904         u8         psvn[0x18];
4905
4906         u8         reserved_3[0x20];
4907 };
4908
4909 struct mlx5_ifc_destroy_mkey_out_bits {
4910         u8         status[0x8];
4911         u8         reserved_0[0x18];
4912
4913         u8         syndrome[0x20];
4914
4915         u8         reserved_1[0x40];
4916 };
4917
4918 struct mlx5_ifc_destroy_mkey_in_bits {
4919         u8         opcode[0x10];
4920         u8         reserved_0[0x10];
4921
4922         u8         reserved_1[0x10];
4923         u8         op_mod[0x10];
4924
4925         u8         reserved_2[0x8];
4926         u8         mkey_index[0x18];
4927
4928         u8         reserved_3[0x20];
4929 };
4930
4931 struct mlx5_ifc_destroy_flow_table_out_bits {
4932         u8         status[0x8];
4933         u8         reserved_0[0x18];
4934
4935         u8         syndrome[0x20];
4936
4937         u8         reserved_1[0x40];
4938 };
4939
4940 struct mlx5_ifc_destroy_flow_table_in_bits {
4941         u8         opcode[0x10];
4942         u8         reserved_0[0x10];
4943
4944         u8         reserved_1[0x10];
4945         u8         op_mod[0x10];
4946
4947         u8         reserved_2[0x40];
4948
4949         u8         table_type[0x8];
4950         u8         reserved_3[0x18];
4951
4952         u8         reserved_4[0x8];
4953         u8         table_id[0x18];
4954
4955         u8         reserved_5[0x140];
4956 };
4957
4958 struct mlx5_ifc_destroy_flow_group_out_bits {
4959         u8         status[0x8];
4960         u8         reserved_0[0x18];
4961
4962         u8         syndrome[0x20];
4963
4964         u8         reserved_1[0x40];
4965 };
4966
4967 struct mlx5_ifc_destroy_flow_group_in_bits {
4968         u8         opcode[0x10];
4969         u8         reserved_0[0x10];
4970
4971         u8         reserved_1[0x10];
4972         u8         op_mod[0x10];
4973
4974         u8         reserved_2[0x40];
4975
4976         u8         table_type[0x8];
4977         u8         reserved_3[0x18];
4978
4979         u8         reserved_4[0x8];
4980         u8         table_id[0x18];
4981
4982         u8         group_id[0x20];
4983
4984         u8         reserved_5[0x120];
4985 };
4986
4987 struct mlx5_ifc_destroy_eq_out_bits {
4988         u8         status[0x8];
4989         u8         reserved_0[0x18];
4990
4991         u8         syndrome[0x20];
4992
4993         u8         reserved_1[0x40];
4994 };
4995
4996 struct mlx5_ifc_destroy_eq_in_bits {
4997         u8         opcode[0x10];
4998         u8         reserved_0[0x10];
4999
5000         u8         reserved_1[0x10];
5001         u8         op_mod[0x10];
5002
5003         u8         reserved_2[0x18];
5004         u8         eq_number[0x8];
5005
5006         u8         reserved_3[0x20];
5007 };
5008
5009 struct mlx5_ifc_destroy_dct_out_bits {
5010         u8         status[0x8];
5011         u8         reserved_0[0x18];
5012
5013         u8         syndrome[0x20];
5014
5015         u8         reserved_1[0x40];
5016 };
5017
5018 struct mlx5_ifc_destroy_dct_in_bits {
5019         u8         opcode[0x10];
5020         u8         reserved_0[0x10];
5021
5022         u8         reserved_1[0x10];
5023         u8         op_mod[0x10];
5024
5025         u8         reserved_2[0x8];
5026         u8         dctn[0x18];
5027
5028         u8         reserved_3[0x20];
5029 };
5030
5031 struct mlx5_ifc_destroy_cq_out_bits {
5032         u8         status[0x8];
5033         u8         reserved_0[0x18];
5034
5035         u8         syndrome[0x20];
5036
5037         u8         reserved_1[0x40];
5038 };
5039
5040 struct mlx5_ifc_destroy_cq_in_bits {
5041         u8         opcode[0x10];
5042         u8         reserved_0[0x10];
5043
5044         u8         reserved_1[0x10];
5045         u8         op_mod[0x10];
5046
5047         u8         reserved_2[0x8];
5048         u8         cqn[0x18];
5049
5050         u8         reserved_3[0x20];
5051 };
5052
5053 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5054         u8         status[0x8];
5055         u8         reserved_0[0x18];
5056
5057         u8         syndrome[0x20];
5058
5059         u8         reserved_1[0x40];
5060 };
5061
5062 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5063         u8         opcode[0x10];
5064         u8         reserved_0[0x10];
5065
5066         u8         reserved_1[0x10];
5067         u8         op_mod[0x10];
5068
5069         u8         reserved_2[0x20];
5070
5071         u8         reserved_3[0x10];
5072         u8         vxlan_udp_port[0x10];
5073 };
5074
5075 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5076         u8         status[0x8];
5077         u8         reserved_0[0x18];
5078
5079         u8         syndrome[0x20];
5080
5081         u8         reserved_1[0x40];
5082 };
5083
5084 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5085         u8         opcode[0x10];
5086         u8         reserved_0[0x10];
5087
5088         u8         reserved_1[0x10];
5089         u8         op_mod[0x10];
5090
5091         u8         reserved_2[0x60];
5092
5093         u8         reserved_3[0x8];
5094         u8         table_index[0x18];
5095
5096         u8         reserved_4[0x140];
5097 };
5098
5099 struct mlx5_ifc_delete_fte_out_bits {
5100         u8         status[0x8];
5101         u8         reserved_0[0x18];
5102
5103         u8         syndrome[0x20];
5104
5105         u8         reserved_1[0x40];
5106 };
5107
5108 struct mlx5_ifc_delete_fte_in_bits {
5109         u8         opcode[0x10];
5110         u8         reserved_0[0x10];
5111
5112         u8         reserved_1[0x10];
5113         u8         op_mod[0x10];
5114
5115         u8         reserved_2[0x40];
5116
5117         u8         table_type[0x8];
5118         u8         reserved_3[0x18];
5119
5120         u8         reserved_4[0x8];
5121         u8         table_id[0x18];
5122
5123         u8         reserved_5[0x40];
5124
5125         u8         flow_index[0x20];
5126
5127         u8         reserved_6[0xe0];
5128 };
5129
5130 struct mlx5_ifc_dealloc_xrcd_out_bits {
5131         u8         status[0x8];
5132         u8         reserved_0[0x18];
5133
5134         u8         syndrome[0x20];
5135
5136         u8         reserved_1[0x40];
5137 };
5138
5139 struct mlx5_ifc_dealloc_xrcd_in_bits {
5140         u8         opcode[0x10];
5141         u8         reserved_0[0x10];
5142
5143         u8         reserved_1[0x10];
5144         u8         op_mod[0x10];
5145
5146         u8         reserved_2[0x8];
5147         u8         xrcd[0x18];
5148
5149         u8         reserved_3[0x20];
5150 };
5151
5152 struct mlx5_ifc_dealloc_uar_out_bits {
5153         u8         status[0x8];
5154         u8         reserved_0[0x18];
5155
5156         u8         syndrome[0x20];
5157
5158         u8         reserved_1[0x40];
5159 };
5160
5161 struct mlx5_ifc_dealloc_uar_in_bits {
5162         u8         opcode[0x10];
5163         u8         reserved_0[0x10];
5164
5165         u8         reserved_1[0x10];
5166         u8         op_mod[0x10];
5167
5168         u8         reserved_2[0x8];
5169         u8         uar[0x18];
5170
5171         u8         reserved_3[0x20];
5172 };
5173
5174 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5175         u8         status[0x8];
5176         u8         reserved_0[0x18];
5177
5178         u8         syndrome[0x20];
5179
5180         u8         reserved_1[0x40];
5181 };
5182
5183 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5184         u8         opcode[0x10];
5185         u8         reserved_0[0x10];
5186
5187         u8         reserved_1[0x10];
5188         u8         op_mod[0x10];
5189
5190         u8         reserved_2[0x8];
5191         u8         transport_domain[0x18];
5192
5193         u8         reserved_3[0x20];
5194 };
5195
5196 struct mlx5_ifc_dealloc_q_counter_out_bits {
5197         u8         status[0x8];
5198         u8         reserved_0[0x18];
5199
5200         u8         syndrome[0x20];
5201
5202         u8         reserved_1[0x40];
5203 };
5204
5205 struct mlx5_ifc_dealloc_q_counter_in_bits {
5206         u8         opcode[0x10];
5207         u8         reserved_0[0x10];
5208
5209         u8         reserved_1[0x10];
5210         u8         op_mod[0x10];
5211
5212         u8         reserved_2[0x18];
5213         u8         counter_set_id[0x8];
5214
5215         u8         reserved_3[0x20];
5216 };
5217
5218 struct mlx5_ifc_dealloc_pd_out_bits {
5219         u8         status[0x8];
5220         u8         reserved_0[0x18];
5221
5222         u8         syndrome[0x20];
5223
5224         u8         reserved_1[0x40];
5225 };
5226
5227 struct mlx5_ifc_dealloc_pd_in_bits {
5228         u8         opcode[0x10];
5229         u8         reserved_0[0x10];
5230
5231         u8         reserved_1[0x10];
5232         u8         op_mod[0x10];
5233
5234         u8         reserved_2[0x8];
5235         u8         pd[0x18];
5236
5237         u8         reserved_3[0x20];
5238 };
5239
5240 struct mlx5_ifc_create_xrc_srq_out_bits {
5241         u8         status[0x8];
5242         u8         reserved_0[0x18];
5243
5244         u8         syndrome[0x20];
5245
5246         u8         reserved_1[0x8];
5247         u8         xrc_srqn[0x18];
5248
5249         u8         reserved_2[0x20];
5250 };
5251
5252 struct mlx5_ifc_create_xrc_srq_in_bits {
5253         u8         opcode[0x10];
5254         u8         reserved_0[0x10];
5255
5256         u8         reserved_1[0x10];
5257         u8         op_mod[0x10];
5258
5259         u8         reserved_2[0x40];
5260
5261         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5262
5263         u8         reserved_3[0x600];
5264
5265         u8         pas[0][0x40];
5266 };
5267
5268 struct mlx5_ifc_create_tis_out_bits {
5269         u8         status[0x8];
5270         u8         reserved_0[0x18];
5271
5272         u8         syndrome[0x20];
5273
5274         u8         reserved_1[0x8];
5275         u8         tisn[0x18];
5276
5277         u8         reserved_2[0x20];
5278 };
5279
5280 struct mlx5_ifc_create_tis_in_bits {
5281         u8         opcode[0x10];
5282         u8         reserved_0[0x10];
5283
5284         u8         reserved_1[0x10];
5285         u8         op_mod[0x10];
5286
5287         u8         reserved_2[0xc0];
5288
5289         struct mlx5_ifc_tisc_bits ctx;
5290 };
5291
5292 struct mlx5_ifc_create_tir_out_bits {
5293         u8         status[0x8];
5294         u8         reserved_0[0x18];
5295
5296         u8         syndrome[0x20];
5297
5298         u8         reserved_1[0x8];
5299         u8         tirn[0x18];
5300
5301         u8         reserved_2[0x20];
5302 };
5303
5304 struct mlx5_ifc_create_tir_in_bits {
5305         u8         opcode[0x10];
5306         u8         reserved_0[0x10];
5307
5308         u8         reserved_1[0x10];
5309         u8         op_mod[0x10];
5310
5311         u8         reserved_2[0xc0];
5312
5313         struct mlx5_ifc_tirc_bits ctx;
5314 };
5315
5316 struct mlx5_ifc_create_srq_out_bits {
5317         u8         status[0x8];
5318         u8         reserved_0[0x18];
5319
5320         u8         syndrome[0x20];
5321
5322         u8         reserved_1[0x8];
5323         u8         srqn[0x18];
5324
5325         u8         reserved_2[0x20];
5326 };
5327
5328 struct mlx5_ifc_create_srq_in_bits {
5329         u8         opcode[0x10];
5330         u8         reserved_0[0x10];
5331
5332         u8         reserved_1[0x10];
5333         u8         op_mod[0x10];
5334
5335         u8         reserved_2[0x40];
5336
5337         struct mlx5_ifc_srqc_bits srq_context_entry;
5338
5339         u8         reserved_3[0x600];
5340
5341         u8         pas[0][0x40];
5342 };
5343
5344 struct mlx5_ifc_create_sq_out_bits {
5345         u8         status[0x8];
5346         u8         reserved_0[0x18];
5347
5348         u8         syndrome[0x20];
5349
5350         u8         reserved_1[0x8];
5351         u8         sqn[0x18];
5352
5353         u8         reserved_2[0x20];
5354 };
5355
5356 struct mlx5_ifc_create_sq_in_bits {
5357         u8         opcode[0x10];
5358         u8         reserved_0[0x10];
5359
5360         u8         reserved_1[0x10];
5361         u8         op_mod[0x10];
5362
5363         u8         reserved_2[0xc0];
5364
5365         struct mlx5_ifc_sqc_bits ctx;
5366 };
5367
5368 struct mlx5_ifc_create_rqt_out_bits {
5369         u8         status[0x8];
5370         u8         reserved_0[0x18];
5371
5372         u8         syndrome[0x20];
5373
5374         u8         reserved_1[0x8];
5375         u8         rqtn[0x18];
5376
5377         u8         reserved_2[0x20];
5378 };
5379
5380 struct mlx5_ifc_create_rqt_in_bits {
5381         u8         opcode[0x10];
5382         u8         reserved_0[0x10];
5383
5384         u8         reserved_1[0x10];
5385         u8         op_mod[0x10];
5386
5387         u8         reserved_2[0xc0];
5388
5389         struct mlx5_ifc_rqtc_bits rqt_context;
5390 };
5391
5392 struct mlx5_ifc_create_rq_out_bits {
5393         u8         status[0x8];
5394         u8         reserved_0[0x18];
5395
5396         u8         syndrome[0x20];
5397
5398         u8         reserved_1[0x8];
5399         u8         rqn[0x18];
5400
5401         u8         reserved_2[0x20];
5402 };
5403
5404 struct mlx5_ifc_create_rq_in_bits {
5405         u8         opcode[0x10];
5406         u8         reserved_0[0x10];
5407
5408         u8         reserved_1[0x10];
5409         u8         op_mod[0x10];
5410
5411         u8         reserved_2[0xc0];
5412
5413         struct mlx5_ifc_rqc_bits ctx;
5414 };
5415
5416 struct mlx5_ifc_create_rmp_out_bits {
5417         u8         status[0x8];
5418         u8         reserved_0[0x18];
5419
5420         u8         syndrome[0x20];
5421
5422         u8         reserved_1[0x8];
5423         u8         rmpn[0x18];
5424
5425         u8         reserved_2[0x20];
5426 };
5427
5428 struct mlx5_ifc_create_rmp_in_bits {
5429         u8         opcode[0x10];
5430         u8         reserved_0[0x10];
5431
5432         u8         reserved_1[0x10];
5433         u8         op_mod[0x10];
5434
5435         u8         reserved_2[0xc0];
5436
5437         struct mlx5_ifc_rmpc_bits ctx;
5438 };
5439
5440 struct mlx5_ifc_create_qp_out_bits {
5441         u8         status[0x8];
5442         u8         reserved_0[0x18];
5443
5444         u8         syndrome[0x20];
5445
5446         u8         reserved_1[0x8];
5447         u8         qpn[0x18];
5448
5449         u8         reserved_2[0x20];
5450 };
5451
5452 struct mlx5_ifc_create_qp_in_bits {
5453         u8         opcode[0x10];
5454         u8         reserved_0[0x10];
5455
5456         u8         reserved_1[0x10];
5457         u8         op_mod[0x10];
5458
5459         u8         reserved_2[0x40];
5460
5461         u8         opt_param_mask[0x20];
5462
5463         u8         reserved_3[0x20];
5464
5465         struct mlx5_ifc_qpc_bits qpc;
5466
5467         u8         reserved_4[0x80];
5468
5469         u8         pas[0][0x40];
5470 };
5471
5472 struct mlx5_ifc_create_psv_out_bits {
5473         u8         status[0x8];
5474         u8         reserved_0[0x18];
5475
5476         u8         syndrome[0x20];
5477
5478         u8         reserved_1[0x40];
5479
5480         u8         reserved_2[0x8];
5481         u8         psv0_index[0x18];
5482
5483         u8         reserved_3[0x8];
5484         u8         psv1_index[0x18];
5485
5486         u8         reserved_4[0x8];
5487         u8         psv2_index[0x18];
5488
5489         u8         reserved_5[0x8];
5490         u8         psv3_index[0x18];
5491 };
5492
5493 struct mlx5_ifc_create_psv_in_bits {
5494         u8         opcode[0x10];
5495         u8         reserved_0[0x10];
5496
5497         u8         reserved_1[0x10];
5498         u8         op_mod[0x10];
5499
5500         u8         num_psv[0x4];
5501         u8         reserved_2[0x4];
5502         u8         pd[0x18];
5503
5504         u8         reserved_3[0x20];
5505 };
5506
5507 struct mlx5_ifc_create_mkey_out_bits {
5508         u8         status[0x8];
5509         u8         reserved_0[0x18];
5510
5511         u8         syndrome[0x20];
5512
5513         u8         reserved_1[0x8];
5514         u8         mkey_index[0x18];
5515
5516         u8         reserved_2[0x20];
5517 };
5518
5519 struct mlx5_ifc_create_mkey_in_bits {
5520         u8         opcode[0x10];
5521         u8         reserved_0[0x10];
5522
5523         u8         reserved_1[0x10];
5524         u8         op_mod[0x10];
5525
5526         u8         reserved_2[0x20];
5527
5528         u8         pg_access[0x1];
5529         u8         reserved_3[0x1f];
5530
5531         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5532
5533         u8         reserved_4[0x80];
5534
5535         u8         translations_octword_actual_size[0x20];
5536
5537         u8         reserved_5[0x560];
5538
5539         u8         klm_pas_mtt[0][0x20];
5540 };
5541
5542 struct mlx5_ifc_create_flow_table_out_bits {
5543         u8         status[0x8];
5544         u8         reserved_0[0x18];
5545
5546         u8         syndrome[0x20];
5547
5548         u8         reserved_1[0x8];
5549         u8         table_id[0x18];
5550
5551         u8         reserved_2[0x20];
5552 };
5553
5554 struct mlx5_ifc_create_flow_table_in_bits {
5555         u8         opcode[0x10];
5556         u8         reserved_0[0x10];
5557
5558         u8         reserved_1[0x10];
5559         u8         op_mod[0x10];
5560
5561         u8         reserved_2[0x40];
5562
5563         u8         table_type[0x8];
5564         u8         reserved_3[0x18];
5565
5566         u8         reserved_4[0x20];
5567
5568         u8         reserved_5[0x8];
5569         u8         level[0x8];
5570         u8         reserved_6[0x8];
5571         u8         log_size[0x8];
5572
5573         u8         reserved_7[0x120];
5574 };
5575
5576 struct mlx5_ifc_create_flow_group_out_bits {
5577         u8         status[0x8];
5578         u8         reserved_0[0x18];
5579
5580         u8         syndrome[0x20];
5581
5582         u8         reserved_1[0x8];
5583         u8         group_id[0x18];
5584
5585         u8         reserved_2[0x20];
5586 };
5587
5588 enum {
5589         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5590         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5591         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5592 };
5593
5594 struct mlx5_ifc_create_flow_group_in_bits {
5595         u8         opcode[0x10];
5596         u8         reserved_0[0x10];
5597
5598         u8         reserved_1[0x10];
5599         u8         op_mod[0x10];
5600
5601         u8         reserved_2[0x40];
5602
5603         u8         table_type[0x8];
5604         u8         reserved_3[0x18];
5605
5606         u8         reserved_4[0x8];
5607         u8         table_id[0x18];
5608
5609         u8         reserved_5[0x20];
5610
5611         u8         start_flow_index[0x20];
5612
5613         u8         reserved_6[0x20];
5614
5615         u8         end_flow_index[0x20];
5616
5617         u8         reserved_7[0xa0];
5618
5619         u8         reserved_8[0x18];
5620         u8         match_criteria_enable[0x8];
5621
5622         struct mlx5_ifc_fte_match_param_bits match_criteria;
5623
5624         u8         reserved_9[0xe00];
5625 };
5626
5627 struct mlx5_ifc_create_eq_out_bits {
5628         u8         status[0x8];
5629         u8         reserved_0[0x18];
5630
5631         u8         syndrome[0x20];
5632
5633         u8         reserved_1[0x18];
5634         u8         eq_number[0x8];
5635
5636         u8         reserved_2[0x20];
5637 };
5638
5639 struct mlx5_ifc_create_eq_in_bits {
5640         u8         opcode[0x10];
5641         u8         reserved_0[0x10];
5642
5643         u8         reserved_1[0x10];
5644         u8         op_mod[0x10];
5645
5646         u8         reserved_2[0x40];
5647
5648         struct mlx5_ifc_eqc_bits eq_context_entry;
5649
5650         u8         reserved_3[0x40];
5651
5652         u8         event_bitmask[0x40];
5653
5654         u8         reserved_4[0x580];
5655
5656         u8         pas[0][0x40];
5657 };
5658
5659 struct mlx5_ifc_create_dct_out_bits {
5660         u8         status[0x8];
5661         u8         reserved_0[0x18];
5662
5663         u8         syndrome[0x20];
5664
5665         u8         reserved_1[0x8];
5666         u8         dctn[0x18];
5667
5668         u8         reserved_2[0x20];
5669 };
5670
5671 struct mlx5_ifc_create_dct_in_bits {
5672         u8         opcode[0x10];
5673         u8         reserved_0[0x10];
5674
5675         u8         reserved_1[0x10];
5676         u8         op_mod[0x10];
5677
5678         u8         reserved_2[0x40];
5679
5680         struct mlx5_ifc_dctc_bits dct_context_entry;
5681
5682         u8         reserved_3[0x180];
5683 };
5684
5685 struct mlx5_ifc_create_cq_out_bits {
5686         u8         status[0x8];
5687         u8         reserved_0[0x18];
5688
5689         u8         syndrome[0x20];
5690
5691         u8         reserved_1[0x8];
5692         u8         cqn[0x18];
5693
5694         u8         reserved_2[0x20];
5695 };
5696
5697 struct mlx5_ifc_create_cq_in_bits {
5698         u8         opcode[0x10];
5699         u8         reserved_0[0x10];
5700
5701         u8         reserved_1[0x10];
5702         u8         op_mod[0x10];
5703
5704         u8         reserved_2[0x40];
5705
5706         struct mlx5_ifc_cqc_bits cq_context;
5707
5708         u8         reserved_3[0x600];
5709
5710         u8         pas[0][0x40];
5711 };
5712
5713 struct mlx5_ifc_config_int_moderation_out_bits {
5714         u8         status[0x8];
5715         u8         reserved_0[0x18];
5716
5717         u8         syndrome[0x20];
5718
5719         u8         reserved_1[0x4];
5720         u8         min_delay[0xc];
5721         u8         int_vector[0x10];
5722
5723         u8         reserved_2[0x20];
5724 };
5725
5726 enum {
5727         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
5728         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
5729 };
5730
5731 struct mlx5_ifc_config_int_moderation_in_bits {
5732         u8         opcode[0x10];
5733         u8         reserved_0[0x10];
5734
5735         u8         reserved_1[0x10];
5736         u8         op_mod[0x10];
5737
5738         u8         reserved_2[0x4];
5739         u8         min_delay[0xc];
5740         u8         int_vector[0x10];
5741
5742         u8         reserved_3[0x20];
5743 };
5744
5745 struct mlx5_ifc_attach_to_mcg_out_bits {
5746         u8         status[0x8];
5747         u8         reserved_0[0x18];
5748
5749         u8         syndrome[0x20];
5750
5751         u8         reserved_1[0x40];
5752 };
5753
5754 struct mlx5_ifc_attach_to_mcg_in_bits {
5755         u8         opcode[0x10];
5756         u8         reserved_0[0x10];
5757
5758         u8         reserved_1[0x10];
5759         u8         op_mod[0x10];
5760
5761         u8         reserved_2[0x8];
5762         u8         qpn[0x18];
5763
5764         u8         reserved_3[0x20];
5765
5766         u8         multicast_gid[16][0x8];
5767 };
5768
5769 struct mlx5_ifc_arm_xrc_srq_out_bits {
5770         u8         status[0x8];
5771         u8         reserved_0[0x18];
5772
5773         u8         syndrome[0x20];
5774
5775         u8         reserved_1[0x40];
5776 };
5777
5778 enum {
5779         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
5780 };
5781
5782 struct mlx5_ifc_arm_xrc_srq_in_bits {
5783         u8         opcode[0x10];
5784         u8         reserved_0[0x10];
5785
5786         u8         reserved_1[0x10];
5787         u8         op_mod[0x10];
5788
5789         u8         reserved_2[0x8];
5790         u8         xrc_srqn[0x18];
5791
5792         u8         reserved_3[0x10];
5793         u8         lwm[0x10];
5794 };
5795
5796 struct mlx5_ifc_arm_rq_out_bits {
5797         u8         status[0x8];
5798         u8         reserved_0[0x18];
5799
5800         u8         syndrome[0x20];
5801
5802         u8         reserved_1[0x40];
5803 };
5804
5805 enum {
5806         MLX5_ARM_RQ_IN_OP_MOD_SRQ_  = 0x1,
5807 };
5808
5809 struct mlx5_ifc_arm_rq_in_bits {
5810         u8         opcode[0x10];
5811         u8         reserved_0[0x10];
5812
5813         u8         reserved_1[0x10];
5814         u8         op_mod[0x10];
5815
5816         u8         reserved_2[0x8];
5817         u8         srq_number[0x18];
5818
5819         u8         reserved_3[0x10];
5820         u8         lwm[0x10];
5821 };
5822
5823 struct mlx5_ifc_arm_dct_out_bits {
5824         u8         status[0x8];
5825         u8         reserved_0[0x18];
5826
5827         u8         syndrome[0x20];
5828
5829         u8         reserved_1[0x40];
5830 };
5831
5832 struct mlx5_ifc_arm_dct_in_bits {
5833         u8         opcode[0x10];
5834         u8         reserved_0[0x10];
5835
5836         u8         reserved_1[0x10];
5837         u8         op_mod[0x10];
5838
5839         u8         reserved_2[0x8];
5840         u8         dct_number[0x18];
5841
5842         u8         reserved_3[0x20];
5843 };
5844
5845 struct mlx5_ifc_alloc_xrcd_out_bits {
5846         u8         status[0x8];
5847         u8         reserved_0[0x18];
5848
5849         u8         syndrome[0x20];
5850
5851         u8         reserved_1[0x8];
5852         u8         xrcd[0x18];
5853
5854         u8         reserved_2[0x20];
5855 };
5856
5857 struct mlx5_ifc_alloc_xrcd_in_bits {
5858         u8         opcode[0x10];
5859         u8         reserved_0[0x10];
5860
5861         u8         reserved_1[0x10];
5862         u8         op_mod[0x10];
5863
5864         u8         reserved_2[0x40];
5865 };
5866
5867 struct mlx5_ifc_alloc_uar_out_bits {
5868         u8         status[0x8];
5869         u8         reserved_0[0x18];
5870
5871         u8         syndrome[0x20];
5872
5873         u8         reserved_1[0x8];
5874         u8         uar[0x18];
5875
5876         u8         reserved_2[0x20];
5877 };
5878
5879 struct mlx5_ifc_alloc_uar_in_bits {
5880         u8         opcode[0x10];
5881         u8         reserved_0[0x10];
5882
5883         u8         reserved_1[0x10];
5884         u8         op_mod[0x10];
5885
5886         u8         reserved_2[0x40];
5887 };
5888
5889 struct mlx5_ifc_alloc_transport_domain_out_bits {
5890         u8         status[0x8];
5891         u8         reserved_0[0x18];
5892
5893         u8         syndrome[0x20];
5894
5895         u8         reserved_1[0x8];
5896         u8         transport_domain[0x18];
5897
5898         u8         reserved_2[0x20];
5899 };
5900
5901 struct mlx5_ifc_alloc_transport_domain_in_bits {
5902         u8         opcode[0x10];
5903         u8         reserved_0[0x10];
5904
5905         u8         reserved_1[0x10];
5906         u8         op_mod[0x10];
5907
5908         u8         reserved_2[0x40];
5909 };
5910
5911 struct mlx5_ifc_alloc_q_counter_out_bits {
5912         u8         status[0x8];
5913         u8         reserved_0[0x18];
5914
5915         u8         syndrome[0x20];
5916
5917         u8         reserved_1[0x18];
5918         u8         counter_set_id[0x8];
5919
5920         u8         reserved_2[0x20];
5921 };
5922
5923 struct mlx5_ifc_alloc_q_counter_in_bits {
5924         u8         opcode[0x10];
5925         u8         reserved_0[0x10];
5926
5927         u8         reserved_1[0x10];
5928         u8         op_mod[0x10];
5929
5930         u8         reserved_2[0x40];
5931 };
5932
5933 struct mlx5_ifc_alloc_pd_out_bits {
5934         u8         status[0x8];
5935         u8         reserved_0[0x18];
5936
5937         u8         syndrome[0x20];
5938
5939         u8         reserved_1[0x8];
5940         u8         pd[0x18];
5941
5942         u8         reserved_2[0x20];
5943 };
5944
5945 struct mlx5_ifc_alloc_pd_in_bits {
5946         u8         opcode[0x10];
5947         u8         reserved_0[0x10];
5948
5949         u8         reserved_1[0x10];
5950         u8         op_mod[0x10];
5951
5952         u8         reserved_2[0x40];
5953 };
5954
5955 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
5956         u8         status[0x8];
5957         u8         reserved_0[0x18];
5958
5959         u8         syndrome[0x20];
5960
5961         u8         reserved_1[0x40];
5962 };
5963
5964 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
5965         u8         opcode[0x10];
5966         u8         reserved_0[0x10];
5967
5968         u8         reserved_1[0x10];
5969         u8         op_mod[0x10];
5970
5971         u8         reserved_2[0x20];
5972
5973         u8         reserved_3[0x10];
5974         u8         vxlan_udp_port[0x10];
5975 };
5976
5977 struct mlx5_ifc_access_register_out_bits {
5978         u8         status[0x8];
5979         u8         reserved_0[0x18];
5980
5981         u8         syndrome[0x20];
5982
5983         u8         reserved_1[0x40];
5984
5985         u8         register_data[0][0x20];
5986 };
5987
5988 enum {
5989         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
5990         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
5991 };
5992
5993 struct mlx5_ifc_access_register_in_bits {
5994         u8         opcode[0x10];
5995         u8         reserved_0[0x10];
5996
5997         u8         reserved_1[0x10];
5998         u8         op_mod[0x10];
5999
6000         u8         reserved_2[0x10];
6001         u8         register_id[0x10];
6002
6003         u8         argument[0x20];
6004
6005         u8         register_data[0][0x20];
6006 };
6007
6008 struct mlx5_ifc_sltp_reg_bits {
6009         u8         status[0x4];
6010         u8         version[0x4];
6011         u8         local_port[0x8];
6012         u8         pnat[0x2];
6013         u8         reserved_0[0x2];
6014         u8         lane[0x4];
6015         u8         reserved_1[0x8];
6016
6017         u8         reserved_2[0x20];
6018
6019         u8         reserved_3[0x7];
6020         u8         polarity[0x1];
6021         u8         ob_tap0[0x8];
6022         u8         ob_tap1[0x8];
6023         u8         ob_tap2[0x8];
6024
6025         u8         reserved_4[0xc];
6026         u8         ob_preemp_mode[0x4];
6027         u8         ob_reg[0x8];
6028         u8         ob_bias[0x8];
6029
6030         u8         reserved_5[0x20];
6031 };
6032
6033 struct mlx5_ifc_slrg_reg_bits {
6034         u8         status[0x4];
6035         u8         version[0x4];
6036         u8         local_port[0x8];
6037         u8         pnat[0x2];
6038         u8         reserved_0[0x2];
6039         u8         lane[0x4];
6040         u8         reserved_1[0x8];
6041
6042         u8         time_to_link_up[0x10];
6043         u8         reserved_2[0xc];
6044         u8         grade_lane_speed[0x4];
6045
6046         u8         grade_version[0x8];
6047         u8         grade[0x18];
6048
6049         u8         reserved_3[0x4];
6050         u8         height_grade_type[0x4];
6051         u8         height_grade[0x18];
6052
6053         u8         height_dz[0x10];
6054         u8         height_dv[0x10];
6055
6056         u8         reserved_4[0x10];
6057         u8         height_sigma[0x10];
6058
6059         u8         reserved_5[0x20];
6060
6061         u8         reserved_6[0x4];
6062         u8         phase_grade_type[0x4];
6063         u8         phase_grade[0x18];
6064
6065         u8         reserved_7[0x8];
6066         u8         phase_eo_pos[0x8];
6067         u8         reserved_8[0x8];
6068         u8         phase_eo_neg[0x8];
6069
6070         u8         ffe_set_tested[0x10];
6071         u8         test_errors_per_lane[0x10];
6072 };
6073
6074 struct mlx5_ifc_pvlc_reg_bits {
6075         u8         reserved_0[0x8];
6076         u8         local_port[0x8];
6077         u8         reserved_1[0x10];
6078
6079         u8         reserved_2[0x1c];
6080         u8         vl_hw_cap[0x4];
6081
6082         u8         reserved_3[0x1c];
6083         u8         vl_admin[0x4];
6084
6085         u8         reserved_4[0x1c];
6086         u8         vl_operational[0x4];
6087 };
6088
6089 struct mlx5_ifc_pude_reg_bits {
6090         u8         swid[0x8];
6091         u8         local_port[0x8];
6092         u8         reserved_0[0x4];
6093         u8         admin_status[0x4];
6094         u8         reserved_1[0x4];
6095         u8         oper_status[0x4];
6096
6097         u8         reserved_2[0x60];
6098 };
6099
6100 struct mlx5_ifc_ptys_reg_bits {
6101         u8         reserved_0[0x8];
6102         u8         local_port[0x8];
6103         u8         reserved_1[0xd];
6104         u8         proto_mask[0x3];
6105
6106         u8         reserved_2[0x40];
6107
6108         u8         eth_proto_capability[0x20];
6109
6110         u8         ib_link_width_capability[0x10];
6111         u8         ib_proto_capability[0x10];
6112
6113         u8         reserved_3[0x20];
6114
6115         u8         eth_proto_admin[0x20];
6116
6117         u8         ib_link_width_admin[0x10];
6118         u8         ib_proto_admin[0x10];
6119
6120         u8         reserved_4[0x20];
6121
6122         u8         eth_proto_oper[0x20];
6123
6124         u8         ib_link_width_oper[0x10];
6125         u8         ib_proto_oper[0x10];
6126
6127         u8         reserved_5[0x20];
6128
6129         u8         eth_proto_lp_advertise[0x20];
6130
6131         u8         reserved_6[0x60];
6132 };
6133
6134 struct mlx5_ifc_ptas_reg_bits {
6135         u8         reserved_0[0x20];
6136
6137         u8         algorithm_options[0x10];
6138         u8         reserved_1[0x4];
6139         u8         repetitions_mode[0x4];
6140         u8         num_of_repetitions[0x8];
6141
6142         u8         grade_version[0x8];
6143         u8         height_grade_type[0x4];
6144         u8         phase_grade_type[0x4];
6145         u8         height_grade_weight[0x8];
6146         u8         phase_grade_weight[0x8];
6147
6148         u8         gisim_measure_bits[0x10];
6149         u8         adaptive_tap_measure_bits[0x10];
6150
6151         u8         ber_bath_high_error_threshold[0x10];
6152         u8         ber_bath_mid_error_threshold[0x10];
6153
6154         u8         ber_bath_low_error_threshold[0x10];
6155         u8         one_ratio_high_threshold[0x10];
6156
6157         u8         one_ratio_high_mid_threshold[0x10];
6158         u8         one_ratio_low_mid_threshold[0x10];
6159
6160         u8         one_ratio_low_threshold[0x10];
6161         u8         ndeo_error_threshold[0x10];
6162
6163         u8         mixer_offset_step_size[0x10];
6164         u8         reserved_2[0x8];
6165         u8         mix90_phase_for_voltage_bath[0x8];
6166
6167         u8         mixer_offset_start[0x10];
6168         u8         mixer_offset_end[0x10];
6169
6170         u8         reserved_3[0x15];
6171         u8         ber_test_time[0xb];
6172 };
6173
6174 struct mlx5_ifc_pspa_reg_bits {
6175         u8         swid[0x8];
6176         u8         local_port[0x8];
6177         u8         sub_port[0x8];
6178         u8         reserved_0[0x8];
6179
6180         u8         reserved_1[0x20];
6181 };
6182
6183 struct mlx5_ifc_pqdr_reg_bits {
6184         u8         reserved_0[0x8];
6185         u8         local_port[0x8];
6186         u8         reserved_1[0x5];
6187         u8         prio[0x3];
6188         u8         reserved_2[0x6];
6189         u8         mode[0x2];
6190
6191         u8         reserved_3[0x20];
6192
6193         u8         reserved_4[0x10];
6194         u8         min_threshold[0x10];
6195
6196         u8         reserved_5[0x10];
6197         u8         max_threshold[0x10];
6198
6199         u8         reserved_6[0x10];
6200         u8         mark_probability_denominator[0x10];
6201
6202         u8         reserved_7[0x60];
6203 };
6204
6205 struct mlx5_ifc_ppsc_reg_bits {
6206         u8         reserved_0[0x8];
6207         u8         local_port[0x8];
6208         u8         reserved_1[0x10];
6209
6210         u8         reserved_2[0x60];
6211
6212         u8         reserved_3[0x1c];
6213         u8         wrps_admin[0x4];
6214
6215         u8         reserved_4[0x1c];
6216         u8         wrps_status[0x4];
6217
6218         u8         reserved_5[0x8];
6219         u8         up_threshold[0x8];
6220         u8         reserved_6[0x8];
6221         u8         down_threshold[0x8];
6222
6223         u8         reserved_7[0x20];
6224
6225         u8         reserved_8[0x1c];
6226         u8         srps_admin[0x4];
6227
6228         u8         reserved_9[0x1c];
6229         u8         srps_status[0x4];
6230
6231         u8         reserved_10[0x40];
6232 };
6233
6234 struct mlx5_ifc_pplr_reg_bits {
6235         u8         reserved_0[0x8];
6236         u8         local_port[0x8];
6237         u8         reserved_1[0x10];
6238
6239         u8         reserved_2[0x8];
6240         u8         lb_cap[0x8];
6241         u8         reserved_3[0x8];
6242         u8         lb_en[0x8];
6243 };
6244
6245 struct mlx5_ifc_pplm_reg_bits {
6246         u8         reserved_0[0x8];
6247         u8         local_port[0x8];
6248         u8         reserved_1[0x10];
6249
6250         u8         reserved_2[0x20];
6251
6252         u8         port_profile_mode[0x8];
6253         u8         static_port_profile[0x8];
6254         u8         active_port_profile[0x8];
6255         u8         reserved_3[0x8];
6256
6257         u8         retransmission_active[0x8];
6258         u8         fec_mode_active[0x18];
6259
6260         u8         reserved_4[0x20];
6261 };
6262
6263 struct mlx5_ifc_ppcnt_reg_bits {
6264         u8         swid[0x8];
6265         u8         local_port[0x8];
6266         u8         pnat[0x2];
6267         u8         reserved_0[0x8];
6268         u8         grp[0x6];
6269
6270         u8         clr[0x1];
6271         u8         reserved_1[0x1c];
6272         u8         prio_tc[0x3];
6273
6274         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6275 };
6276
6277 struct mlx5_ifc_ppad_reg_bits {
6278         u8         reserved_0[0x3];
6279         u8         single_mac[0x1];
6280         u8         reserved_1[0x4];
6281         u8         local_port[0x8];
6282         u8         mac_47_32[0x10];
6283
6284         u8         mac_31_0[0x20];
6285
6286         u8         reserved_2[0x40];
6287 };
6288
6289 struct mlx5_ifc_pmtu_reg_bits {
6290         u8         reserved_0[0x8];
6291         u8         local_port[0x8];
6292         u8         reserved_1[0x10];
6293
6294         u8         max_mtu[0x10];
6295         u8         reserved_2[0x10];
6296
6297         u8         admin_mtu[0x10];
6298         u8         reserved_3[0x10];
6299
6300         u8         oper_mtu[0x10];
6301         u8         reserved_4[0x10];
6302 };
6303
6304 struct mlx5_ifc_pmpr_reg_bits {
6305         u8         reserved_0[0x8];
6306         u8         module[0x8];
6307         u8         reserved_1[0x10];
6308
6309         u8         reserved_2[0x18];
6310         u8         attenuation_5g[0x8];
6311
6312         u8         reserved_3[0x18];
6313         u8         attenuation_7g[0x8];
6314
6315         u8         reserved_4[0x18];
6316         u8         attenuation_12g[0x8];
6317 };
6318
6319 struct mlx5_ifc_pmpe_reg_bits {
6320         u8         reserved_0[0x8];
6321         u8         module[0x8];
6322         u8         reserved_1[0xc];
6323         u8         module_status[0x4];
6324
6325         u8         reserved_2[0x60];
6326 };
6327
6328 struct mlx5_ifc_pmpc_reg_bits {
6329         u8         module_state_updated[32][0x8];
6330 };
6331
6332 struct mlx5_ifc_pmlpn_reg_bits {
6333         u8         reserved_0[0x4];
6334         u8         mlpn_status[0x4];
6335         u8         local_port[0x8];
6336         u8         reserved_1[0x10];
6337
6338         u8         e[0x1];
6339         u8         reserved_2[0x1f];
6340 };
6341
6342 struct mlx5_ifc_pmlp_reg_bits {
6343         u8         rxtx[0x1];
6344         u8         reserved_0[0x7];
6345         u8         local_port[0x8];
6346         u8         reserved_1[0x8];
6347         u8         width[0x8];
6348
6349         u8         lane0_module_mapping[0x20];
6350
6351         u8         lane1_module_mapping[0x20];
6352
6353         u8         lane2_module_mapping[0x20];
6354
6355         u8         lane3_module_mapping[0x20];
6356
6357         u8         reserved_2[0x160];
6358 };
6359
6360 struct mlx5_ifc_pmaos_reg_bits {
6361         u8         reserved_0[0x8];
6362         u8         module[0x8];
6363         u8         reserved_1[0x4];
6364         u8         admin_status[0x4];
6365         u8         reserved_2[0x4];
6366         u8         oper_status[0x4];
6367
6368         u8         ase[0x1];
6369         u8         ee[0x1];
6370         u8         reserved_3[0x1c];
6371         u8         e[0x2];
6372
6373         u8         reserved_4[0x40];
6374 };
6375
6376 struct mlx5_ifc_plpc_reg_bits {
6377         u8         reserved_0[0x4];
6378         u8         profile_id[0xc];
6379         u8         reserved_1[0x4];
6380         u8         proto_mask[0x4];
6381         u8         reserved_2[0x8];
6382
6383         u8         reserved_3[0x10];
6384         u8         lane_speed[0x10];
6385
6386         u8         reserved_4[0x17];
6387         u8         lpbf[0x1];
6388         u8         fec_mode_policy[0x8];
6389
6390         u8         retransmission_capability[0x8];
6391         u8         fec_mode_capability[0x18];
6392
6393         u8         retransmission_support_admin[0x8];
6394         u8         fec_mode_support_admin[0x18];
6395
6396         u8         retransmission_request_admin[0x8];
6397         u8         fec_mode_request_admin[0x18];
6398
6399         u8         reserved_5[0x80];
6400 };
6401
6402 struct mlx5_ifc_plib_reg_bits {
6403         u8         reserved_0[0x8];
6404         u8         local_port[0x8];
6405         u8         reserved_1[0x8];
6406         u8         ib_port[0x8];
6407
6408         u8         reserved_2[0x60];
6409 };
6410
6411 struct mlx5_ifc_plbf_reg_bits {
6412         u8         reserved_0[0x8];
6413         u8         local_port[0x8];
6414         u8         reserved_1[0xd];
6415         u8         lbf_mode[0x3];
6416
6417         u8         reserved_2[0x20];
6418 };
6419
6420 struct mlx5_ifc_pipg_reg_bits {
6421         u8         reserved_0[0x8];
6422         u8         local_port[0x8];
6423         u8         reserved_1[0x10];
6424
6425         u8         dic[0x1];
6426         u8         reserved_2[0x19];
6427         u8         ipg[0x4];
6428         u8         reserved_3[0x2];
6429 };
6430
6431 struct mlx5_ifc_pifr_reg_bits {
6432         u8         reserved_0[0x8];
6433         u8         local_port[0x8];
6434         u8         reserved_1[0x10];
6435
6436         u8         reserved_2[0xe0];
6437
6438         u8         port_filter[8][0x20];
6439
6440         u8         port_filter_update_en[8][0x20];
6441 };
6442
6443 struct mlx5_ifc_pfcc_reg_bits {
6444         u8         reserved_0[0x8];
6445         u8         local_port[0x8];
6446         u8         reserved_1[0x10];
6447
6448         u8         ppan[0x4];
6449         u8         reserved_2[0x4];
6450         u8         prio_mask_tx[0x8];
6451         u8         reserved_3[0x8];
6452         u8         prio_mask_rx[0x8];
6453
6454         u8         pptx[0x1];
6455         u8         aptx[0x1];
6456         u8         reserved_4[0x6];
6457         u8         pfctx[0x8];
6458         u8         reserved_5[0x10];
6459
6460         u8         pprx[0x1];
6461         u8         aprx[0x1];
6462         u8         reserved_6[0x6];
6463         u8         pfcrx[0x8];
6464         u8         reserved_7[0x10];
6465
6466         u8         reserved_8[0x80];
6467 };
6468
6469 struct mlx5_ifc_pelc_reg_bits {
6470         u8         op[0x4];
6471         u8         reserved_0[0x4];
6472         u8         local_port[0x8];
6473         u8         reserved_1[0x10];
6474
6475         u8         op_admin[0x8];
6476         u8         op_capability[0x8];
6477         u8         op_request[0x8];
6478         u8         op_active[0x8];
6479
6480         u8         admin[0x40];
6481
6482         u8         capability[0x40];
6483
6484         u8         request[0x40];
6485
6486         u8         active[0x40];
6487
6488         u8         reserved_2[0x80];
6489 };
6490
6491 struct mlx5_ifc_peir_reg_bits {
6492         u8         reserved_0[0x8];
6493         u8         local_port[0x8];
6494         u8         reserved_1[0x10];
6495
6496         u8         reserved_2[0xc];
6497         u8         error_count[0x4];
6498         u8         reserved_3[0x10];
6499
6500         u8         reserved_4[0xc];
6501         u8         lane[0x4];
6502         u8         reserved_5[0x8];
6503         u8         error_type[0x8];
6504 };
6505
6506 struct mlx5_ifc_pcap_reg_bits {
6507         u8         reserved_0[0x8];
6508         u8         local_port[0x8];
6509         u8         reserved_1[0x10];
6510
6511         u8         port_capability_mask[4][0x20];
6512 };
6513
6514 struct mlx5_ifc_paos_reg_bits {
6515         u8         swid[0x8];
6516         u8         local_port[0x8];
6517         u8         reserved_0[0x4];
6518         u8         admin_status[0x4];
6519         u8         reserved_1[0x4];
6520         u8         oper_status[0x4];
6521
6522         u8         ase[0x1];
6523         u8         ee[0x1];
6524         u8         reserved_2[0x1c];
6525         u8         e[0x2];
6526
6527         u8         reserved_3[0x40];
6528 };
6529
6530 struct mlx5_ifc_pamp_reg_bits {
6531         u8         reserved_0[0x8];
6532         u8         opamp_group[0x8];
6533         u8         reserved_1[0xc];
6534         u8         opamp_group_type[0x4];
6535
6536         u8         start_index[0x10];
6537         u8         reserved_2[0x4];
6538         u8         num_of_indices[0xc];
6539
6540         u8         index_data[18][0x10];
6541 };
6542
6543 struct mlx5_ifc_lane_2_module_mapping_bits {
6544         u8         reserved_0[0x6];
6545         u8         rx_lane[0x2];
6546         u8         reserved_1[0x6];
6547         u8         tx_lane[0x2];
6548         u8         reserved_2[0x8];
6549         u8         module[0x8];
6550 };
6551
6552 struct mlx5_ifc_bufferx_reg_bits {
6553         u8         reserved_0[0x6];
6554         u8         lossy[0x1];
6555         u8         epsb[0x1];
6556         u8         reserved_1[0xc];
6557         u8         size[0xc];
6558
6559         u8         xoff_threshold[0x10];
6560         u8         xon_threshold[0x10];
6561 };
6562
6563 struct mlx5_ifc_set_node_in_bits {
6564         u8         node_description[64][0x8];
6565 };
6566
6567 struct mlx5_ifc_register_power_settings_bits {
6568         u8         reserved_0[0x18];
6569         u8         power_settings_level[0x8];
6570
6571         u8         reserved_1[0x60];
6572 };
6573
6574 struct mlx5_ifc_register_host_endianness_bits {
6575         u8         he[0x1];
6576         u8         reserved_0[0x1f];
6577
6578         u8         reserved_1[0x60];
6579 };
6580
6581 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6582         u8         reserved_0[0x20];
6583
6584         u8         mkey[0x20];
6585
6586         u8         addressh_63_32[0x20];
6587
6588         u8         addressl_31_0[0x20];
6589 };
6590
6591 struct mlx5_ifc_ud_adrs_vector_bits {
6592         u8         dc_key[0x40];
6593
6594         u8         ext[0x1];
6595         u8         reserved_0[0x7];
6596         u8         destination_qp_dct[0x18];
6597
6598         u8         static_rate[0x4];
6599         u8         sl_eth_prio[0x4];
6600         u8         fl[0x1];
6601         u8         mlid[0x7];
6602         u8         rlid_udp_sport[0x10];
6603
6604         u8         reserved_1[0x20];
6605
6606         u8         rmac_47_16[0x20];
6607
6608         u8         rmac_15_0[0x10];
6609         u8         tclass[0x8];
6610         u8         hop_limit[0x8];
6611
6612         u8         reserved_2[0x1];
6613         u8         grh[0x1];
6614         u8         reserved_3[0x2];
6615         u8         src_addr_index[0x8];
6616         u8         flow_label[0x14];
6617
6618         u8         rgid_rip[16][0x8];
6619 };
6620
6621 struct mlx5_ifc_pages_req_event_bits {
6622         u8         reserved_0[0x10];
6623         u8         function_id[0x10];
6624
6625         u8         num_pages[0x20];
6626
6627         u8         reserved_1[0xa0];
6628 };
6629
6630 struct mlx5_ifc_eqe_bits {
6631         u8         reserved_0[0x8];
6632         u8         event_type[0x8];
6633         u8         reserved_1[0x8];
6634         u8         event_sub_type[0x8];
6635
6636         u8         reserved_2[0xe0];
6637
6638         union mlx5_ifc_event_auto_bits event_data;
6639
6640         u8         reserved_3[0x10];
6641         u8         signature[0x8];
6642         u8         reserved_4[0x7];
6643         u8         owner[0x1];
6644 };
6645
6646 enum {
6647         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
6648 };
6649
6650 struct mlx5_ifc_cmd_queue_entry_bits {
6651         u8         type[0x8];
6652         u8         reserved_0[0x18];
6653
6654         u8         input_length[0x20];
6655
6656         u8         input_mailbox_pointer_63_32[0x20];
6657
6658         u8         input_mailbox_pointer_31_9[0x17];
6659         u8         reserved_1[0x9];
6660
6661         u8         command_input_inline_data[16][0x8];
6662
6663         u8         command_output_inline_data[16][0x8];
6664
6665         u8         output_mailbox_pointer_63_32[0x20];
6666
6667         u8         output_mailbox_pointer_31_9[0x17];
6668         u8         reserved_2[0x9];
6669
6670         u8         output_length[0x20];
6671
6672         u8         token[0x8];
6673         u8         signature[0x8];
6674         u8         reserved_3[0x8];
6675         u8         status[0x7];
6676         u8         ownership[0x1];
6677 };
6678
6679 struct mlx5_ifc_cmd_out_bits {
6680         u8         status[0x8];
6681         u8         reserved_0[0x18];
6682
6683         u8         syndrome[0x20];
6684
6685         u8         command_output[0x20];
6686 };
6687
6688 struct mlx5_ifc_cmd_in_bits {
6689         u8         opcode[0x10];
6690         u8         reserved_0[0x10];
6691
6692         u8         reserved_1[0x10];
6693         u8         op_mod[0x10];
6694
6695         u8         command[0][0x20];
6696 };
6697
6698 struct mlx5_ifc_cmd_if_box_bits {
6699         u8         mailbox_data[512][0x8];
6700
6701         u8         reserved_0[0x180];
6702
6703         u8         next_pointer_63_32[0x20];
6704
6705         u8         next_pointer_31_10[0x16];
6706         u8         reserved_1[0xa];
6707
6708         u8         block_number[0x20];
6709
6710         u8         reserved_2[0x8];
6711         u8         token[0x8];
6712         u8         ctrl_signature[0x8];
6713         u8         signature[0x8];
6714 };
6715
6716 struct mlx5_ifc_mtt_bits {
6717         u8         ptag_63_32[0x20];
6718
6719         u8         ptag_31_8[0x18];
6720         u8         reserved_0[0x6];
6721         u8         wr_en[0x1];
6722         u8         rd_en[0x1];
6723 };
6724
6725 enum {
6726         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
6727         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
6728         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
6729 };
6730
6731 enum {
6732         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
6733         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
6734         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
6735 };
6736
6737 enum {
6738         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
6739         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
6740         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
6741         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
6742         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
6743         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
6744         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
6745         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
6746         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
6747         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
6748         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
6749 };
6750
6751 struct mlx5_ifc_initial_seg_bits {
6752         u8         fw_rev_minor[0x10];
6753         u8         fw_rev_major[0x10];
6754
6755         u8         cmd_interface_rev[0x10];
6756         u8         fw_rev_subminor[0x10];
6757
6758         u8         reserved_0[0x40];
6759
6760         u8         cmdq_phy_addr_63_32[0x20];
6761
6762         u8         cmdq_phy_addr_31_12[0x14];
6763         u8         reserved_1[0x2];
6764         u8         nic_interface[0x2];
6765         u8         log_cmdq_size[0x4];
6766         u8         log_cmdq_stride[0x4];
6767
6768         u8         command_doorbell_vector[0x20];
6769
6770         u8         reserved_2[0xf00];
6771
6772         u8         initializing[0x1];
6773         u8         reserved_3[0x4];
6774         u8         nic_interface_supported[0x3];
6775         u8         reserved_4[0x18];
6776
6777         struct mlx5_ifc_health_buffer_bits health_buffer;
6778
6779         u8         no_dram_nic_offset[0x20];
6780
6781         u8         reserved_5[0x6e40];
6782
6783         u8         reserved_6[0x1f];
6784         u8         clear_int[0x1];
6785
6786         u8         health_syndrome[0x8];
6787         u8         health_counter[0x18];
6788
6789         u8         reserved_7[0x17fc0];
6790 };
6791
6792 union mlx5_ifc_ports_control_registers_document_bits {
6793         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6794         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6795         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6796         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6797         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6798         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6799         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6800         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6801         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6802         struct mlx5_ifc_pamp_reg_bits pamp_reg;
6803         struct mlx5_ifc_paos_reg_bits paos_reg;
6804         struct mlx5_ifc_pcap_reg_bits pcap_reg;
6805         struct mlx5_ifc_peir_reg_bits peir_reg;
6806         struct mlx5_ifc_pelc_reg_bits pelc_reg;
6807         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
6808         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6809         struct mlx5_ifc_pifr_reg_bits pifr_reg;
6810         struct mlx5_ifc_pipg_reg_bits pipg_reg;
6811         struct mlx5_ifc_plbf_reg_bits plbf_reg;
6812         struct mlx5_ifc_plib_reg_bits plib_reg;
6813         struct mlx5_ifc_plpc_reg_bits plpc_reg;
6814         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
6815         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
6816         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
6817         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
6818         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
6819         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
6820         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
6821         struct mlx5_ifc_ppad_reg_bits ppad_reg;
6822         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
6823         struct mlx5_ifc_pplm_reg_bits pplm_reg;
6824         struct mlx5_ifc_pplr_reg_bits pplr_reg;
6825         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
6826         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
6827         struct mlx5_ifc_pspa_reg_bits pspa_reg;
6828         struct mlx5_ifc_ptas_reg_bits ptas_reg;
6829         struct mlx5_ifc_ptys_reg_bits ptys_reg;
6830         struct mlx5_ifc_pude_reg_bits pude_reg;
6831         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
6832         struct mlx5_ifc_slrg_reg_bits slrg_reg;
6833         struct mlx5_ifc_sltp_reg_bits sltp_reg;
6834         u8         reserved_0[0x60e0];
6835 };
6836
6837 union mlx5_ifc_debug_enhancements_document_bits {
6838         struct mlx5_ifc_health_buffer_bits health_buffer;
6839         u8         reserved_0[0x200];
6840 };
6841
6842 union mlx5_ifc_uplink_pci_interface_document_bits {
6843         struct mlx5_ifc_initial_seg_bits initial_seg;
6844         u8         reserved_0[0x20060];
6845 };
6846
6847 #endif /* MLX5_IFC_H */