2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
71 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
72 MLX5_CMD_OP_INIT_HCA = 0x102,
73 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
74 MLX5_CMD_OP_ENABLE_HCA = 0x104,
75 MLX5_CMD_OP_DISABLE_HCA = 0x105,
76 MLX5_CMD_OP_QUERY_PAGES = 0x107,
77 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
78 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
79 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
80 MLX5_CMD_OP_SET_ISSI = 0x10b,
81 MLX5_CMD_OP_CREATE_MKEY = 0x200,
82 MLX5_CMD_OP_QUERY_MKEY = 0x201,
83 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
84 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
85 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
86 MLX5_CMD_OP_CREATE_EQ = 0x301,
87 MLX5_CMD_OP_DESTROY_EQ = 0x302,
88 MLX5_CMD_OP_QUERY_EQ = 0x303,
89 MLX5_CMD_OP_GEN_EQE = 0x304,
90 MLX5_CMD_OP_CREATE_CQ = 0x400,
91 MLX5_CMD_OP_DESTROY_CQ = 0x401,
92 MLX5_CMD_OP_QUERY_CQ = 0x402,
93 MLX5_CMD_OP_MODIFY_CQ = 0x403,
94 MLX5_CMD_OP_CREATE_QP = 0x500,
95 MLX5_CMD_OP_DESTROY_QP = 0x501,
96 MLX5_CMD_OP_RST2INIT_QP = 0x502,
97 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
98 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
99 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
100 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
101 MLX5_CMD_OP_2ERR_QP = 0x507,
102 MLX5_CMD_OP_2RST_QP = 0x50a,
103 MLX5_CMD_OP_QUERY_QP = 0x50b,
104 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
105 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
106 MLX5_CMD_OP_CREATE_PSV = 0x600,
107 MLX5_CMD_OP_DESTROY_PSV = 0x601,
108 MLX5_CMD_OP_CREATE_SRQ = 0x700,
109 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
110 MLX5_CMD_OP_QUERY_SRQ = 0x702,
111 MLX5_CMD_OP_ARM_RQ = 0x703,
112 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
113 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
114 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
115 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
116 MLX5_CMD_OP_CREATE_DCT = 0x710,
117 MLX5_CMD_OP_DESTROY_DCT = 0x711,
118 MLX5_CMD_OP_DRAIN_DCT = 0x712,
119 MLX5_CMD_OP_QUERY_DCT = 0x713,
120 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
121 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
122 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
123 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
124 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
125 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
126 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
127 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
128 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
129 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
130 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
131 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
132 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
133 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
134 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
135 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
136 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
137 MLX5_CMD_OP_ALLOC_PD = 0x800,
138 MLX5_CMD_OP_DEALLOC_PD = 0x801,
139 MLX5_CMD_OP_ALLOC_UAR = 0x802,
140 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
141 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
142 MLX5_CMD_OP_ACCESS_REG = 0x805,
143 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
144 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
145 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
146 MLX5_CMD_OP_MAD_IFC = 0x50d,
147 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
148 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
149 MLX5_CMD_OP_NOP = 0x80d,
150 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
151 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
152 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
153 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
154 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
155 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
156 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
157 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
158 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
159 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
160 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
161 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
162 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
163 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
164 MLX5_CMD_OP_CREATE_TIR = 0x900,
165 MLX5_CMD_OP_MODIFY_TIR = 0x901,
166 MLX5_CMD_OP_DESTROY_TIR = 0x902,
167 MLX5_CMD_OP_QUERY_TIR = 0x903,
168 MLX5_CMD_OP_CREATE_SQ = 0x904,
169 MLX5_CMD_OP_MODIFY_SQ = 0x905,
170 MLX5_CMD_OP_DESTROY_SQ = 0x906,
171 MLX5_CMD_OP_QUERY_SQ = 0x907,
172 MLX5_CMD_OP_CREATE_RQ = 0x908,
173 MLX5_CMD_OP_MODIFY_RQ = 0x909,
174 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
175 MLX5_CMD_OP_QUERY_RQ = 0x90b,
176 MLX5_CMD_OP_CREATE_RMP = 0x90c,
177 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
178 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
179 MLX5_CMD_OP_QUERY_RMP = 0x90f,
180 MLX5_CMD_OP_CREATE_TIS = 0x912,
181 MLX5_CMD_OP_MODIFY_TIS = 0x913,
182 MLX5_CMD_OP_DESTROY_TIS = 0x914,
183 MLX5_CMD_OP_QUERY_TIS = 0x915,
184 MLX5_CMD_OP_CREATE_RQT = 0x916,
185 MLX5_CMD_OP_MODIFY_RQT = 0x917,
186 MLX5_CMD_OP_DESTROY_RQT = 0x918,
187 MLX5_CMD_OP_QUERY_RQT = 0x919,
188 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
189 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
190 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
191 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
192 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
193 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
194 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
195 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
196 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938
199 struct mlx5_ifc_flow_table_fields_supported_bits {
202 u8 outer_ether_type[0x1];
204 u8 outer_first_prio[0x1];
205 u8 outer_first_cfi[0x1];
206 u8 outer_first_vid[0x1];
208 u8 outer_second_prio[0x1];
209 u8 outer_second_cfi[0x1];
210 u8 outer_second_vid[0x1];
215 u8 outer_ip_protocol[0x1];
216 u8 outer_ip_ecn[0x1];
217 u8 outer_ip_dscp[0x1];
218 u8 outer_udp_sport[0x1];
219 u8 outer_udp_dport[0x1];
220 u8 outer_tcp_sport[0x1];
221 u8 outer_tcp_dport[0x1];
222 u8 outer_tcp_flags[0x1];
223 u8 outer_gre_protocol[0x1];
224 u8 outer_gre_key[0x1];
225 u8 outer_vxlan_vni[0x1];
227 u8 source_eswitch_port[0x1];
231 u8 inner_ether_type[0x1];
233 u8 inner_first_prio[0x1];
234 u8 inner_first_cfi[0x1];
235 u8 inner_first_vid[0x1];
237 u8 inner_second_prio[0x1];
238 u8 inner_second_cfi[0x1];
239 u8 inner_second_vid[0x1];
244 u8 inner_ip_protocol[0x1];
245 u8 inner_ip_ecn[0x1];
246 u8 inner_ip_dscp[0x1];
247 u8 inner_udp_sport[0x1];
248 u8 inner_udp_dport[0x1];
249 u8 inner_tcp_sport[0x1];
250 u8 inner_tcp_dport[0x1];
251 u8 inner_tcp_flags[0x1];
257 struct mlx5_ifc_flow_table_prop_layout_bits {
262 u8 log_max_ft_size[0x6];
264 u8 max_ft_level[0x8];
269 u8 log_max_ft_num[0x8];
272 u8 log_max_destination[0x8];
275 u8 log_max_flow[0x8];
279 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
281 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
284 struct mlx5_ifc_odp_per_transport_service_cap_bits {
294 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
329 struct mlx5_ifc_fte_match_set_misc_bits {
333 u8 source_port[0x10];
335 u8 outer_second_prio[0x3];
336 u8 outer_second_cfi[0x1];
337 u8 outer_second_vid[0xc];
338 u8 inner_second_prio[0x3];
339 u8 inner_second_cfi[0x1];
340 u8 inner_second_vid[0xc];
342 u8 outer_second_vlan_tag[0x1];
343 u8 inner_second_vlan_tag[0x1];
345 u8 gre_protocol[0x10];
356 u8 outer_ipv6_flow_label[0x14];
359 u8 inner_ipv6_flow_label[0x14];
364 struct mlx5_ifc_cmd_pas_bits {
371 struct mlx5_ifc_uint64_bits {
378 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
379 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
380 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
381 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
382 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
383 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
384 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
385 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
386 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
387 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
390 struct mlx5_ifc_ads_bits {
403 u8 src_addr_index[0x8];
412 u8 rgid_rip[16][0x8];
432 struct mlx5_ifc_flow_table_nic_cap_bits {
433 u8 reserved_0[0x200];
435 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
437 u8 reserved_1[0x200];
439 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
441 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
443 u8 reserved_2[0x200];
445 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
447 u8 reserved_3[0x7200];
450 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
454 u8 lro_psh_flag[0x1];
455 u8 lro_time_stamp[0x1];
459 u8 rss_ind_tbl_cap[0x4];
461 u8 tunnel_lso_const_out_ip_id[0x1];
463 u8 tunnel_statless_gre[0x1];
464 u8 tunnel_stateless_vxlan[0x1];
469 u8 lro_min_mss_size[0x10];
471 u8 reserved_6[0x120];
473 u8 lro_timer_supported_periods[4][0x20];
475 u8 reserved_7[0x600];
478 struct mlx5_ifc_roce_cap_bits {
487 u8 roce_version[0x8];
490 u8 r_roce_dest_udp_port[0x10];
492 u8 r_roce_max_src_udp_port[0x10];
493 u8 r_roce_min_src_udp_port[0x10];
496 u8 roce_address_table_size[0x10];
498 u8 reserved_6[0x700];
502 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
503 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
504 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
505 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
506 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
507 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
508 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
509 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
510 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
514 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
515 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
516 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
517 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
518 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
519 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
520 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
521 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
522 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
525 struct mlx5_ifc_atomic_caps_bits {
528 u8 atomic_req_endianness[0x1];
534 u8 atomic_operations[0x10];
537 u8 atomic_size_qp[0x10];
540 u8 atomic_size_dc[0x10];
542 u8 reserved_6[0x720];
545 struct mlx5_ifc_odp_cap_bits {
553 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
555 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
557 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
559 u8 reserved_3[0x720];
563 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
564 MLX5_WQ_TYPE_CYCLIC = 0x1,
565 MLX5_WQ_TYPE_STRQ = 0x2,
569 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
570 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
574 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
575 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
576 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
577 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
578 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
582 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
583 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
584 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
585 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
586 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
587 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
591 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
592 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
596 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
597 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
598 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
602 MLX5_CAP_PORT_TYPE_IB = 0x0,
603 MLX5_CAP_PORT_TYPE_ETH = 0x1,
606 struct mlx5_ifc_cmd_hca_cap_bits {
609 u8 log_max_srq_sz[0x8];
610 u8 log_max_qp_sz[0x8];
619 u8 log_max_cq_sz[0x8];
623 u8 log_max_eq_sz[0x8];
625 u8 log_max_mkey[0x6];
629 u8 max_indirection[0x8];
631 u8 log_max_mrw_sz[0x7];
633 u8 log_max_bsf_list_size[0x6];
635 u8 log_max_klm_list_size[0x6];
638 u8 log_max_ra_req_dc[0x6];
640 u8 log_max_ra_res_dc[0x6];
643 u8 log_max_ra_req_qp[0x6];
645 u8 log_max_ra_res_qp[0x6];
648 u8 cc_query_allowed[0x1];
649 u8 cc_modify_allowed[0x1];
651 u8 gid_table_size[0x10];
653 u8 out_of_seq_cnt[0x1];
654 u8 vport_counters[0x1];
657 u8 pkey_table_size[0x10];
659 u8 vport_group_manager[0x1];
660 u8 vhca_group_manager[0x1];
665 u8 nic_flow_table[0x1];
667 u8 local_ca_ack_delay[0x5];
674 u8 reserved_21[0x18];
676 u8 stat_rate_support[0x10];
680 u8 compact_address_vector[0x1];
682 u8 drain_sigerr[0x1];
683 u8 cmdif_checksum[0x2];
686 u8 wq_signature[0x1];
687 u8 sctr_data_cqe[0x1];
694 u8 eth_net_offloads[0x1];
701 u8 cq_moderation[0x1];
707 u8 scqe_break_moderation[0x1];
728 u8 pad_tx_eth_packet[0x1];
730 u8 log_bf_reg_size[0x5];
731 u8 reserved_38[0x10];
733 u8 reserved_39[0x10];
734 u8 max_wqe_sz_sq[0x10];
736 u8 reserved_40[0x10];
737 u8 max_wqe_sz_rq[0x10];
739 u8 reserved_41[0x10];
740 u8 max_wqe_sz_sq_dc[0x10];
745 u8 reserved_43[0x18];
749 u8 log_max_transport_domain[0x5];
753 u8 log_max_xrcd[0x5];
755 u8 reserved_47[0x20];
766 u8 basic_cyclic_rcv_wqe[0x1];
772 u8 log_max_rqt_size[0x5];
774 u8 log_max_tis_per_sq[0x5];
777 u8 log_max_stride_sz_rq[0x5];
779 u8 log_min_stride_sz_rq[0x5];
781 u8 log_max_stride_sz_sq[0x5];
783 u8 log_min_stride_sz_sq[0x5];
785 u8 reserved_60[0x1b];
786 u8 log_max_wq_sz[0x5];
788 u8 reserved_61[0xa0];
791 u8 log_max_l2_table[0x5];
793 u8 log_uar_page_sz[0x10];
795 u8 reserved_64[0x100];
797 u8 reserved_65[0x1f];
800 u8 cqe_zip_timeout[0x10];
801 u8 cqe_zip_max_num[0x10];
803 u8 reserved_66[0x220];
807 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_FLOW_TABLE_ = 0x1,
808 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_TIR = 0x2,
811 struct mlx5_ifc_dest_format_struct_bits {
812 u8 destination_type[0x8];
813 u8 destination_id[0x18];
818 struct mlx5_ifc_fte_match_param_bits {
819 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
821 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
823 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
825 u8 reserved_0[0xa00];
829 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
830 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
831 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
832 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
833 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
836 struct mlx5_ifc_rx_hash_field_select_bits {
837 u8 l3_prot_type[0x1];
838 u8 l4_prot_type[0x1];
839 u8 selected_fields[0x1e];
843 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
844 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
848 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
849 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
852 struct mlx5_ifc_wq_bits {
854 u8 wq_signature[0x1];
855 u8 end_padding_mode[0x2];
859 u8 hds_skip_first_sge[0x1];
860 u8 log2_hds_buf_size[0x3];
878 u8 log_wq_stride[0x4];
880 u8 log_wq_pg_sz[0x5];
884 u8 reserved_7[0x4e0];
886 struct mlx5_ifc_cmd_pas_bits pas[0];
889 struct mlx5_ifc_rq_num_bits {
894 struct mlx5_ifc_mac_address_layout_bits {
896 u8 mac_addr_47_32[0x10];
898 u8 mac_addr_31_0[0x20];
901 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
904 u8 min_time_between_cnps[0x20];
909 u8 cnp_802p_prio[0x3];
911 u8 reserved_3[0x720];
914 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
918 u8 clamp_tgt_rate[0x1];
920 u8 clamp_tgt_rate_after_time_inc[0x1];
925 u8 rpg_time_reset[0x20];
927 u8 rpg_byte_reset[0x20];
929 u8 rpg_threshold[0x20];
931 u8 rpg_max_rate[0x20];
933 u8 rpg_ai_rate[0x20];
935 u8 rpg_hai_rate[0x20];
939 u8 rpg_min_dec_fac[0x20];
941 u8 rpg_min_rate[0x20];
945 u8 rate_to_set_on_first_cnp[0x20];
949 u8 dce_tcp_rtt[0x20];
951 u8 rate_reduce_monitor_period[0x20];
955 u8 initial_alpha_value[0x20];
957 u8 reserved_7[0x4a0];
960 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
963 u8 rppp_max_rps[0x20];
965 u8 rpg_time_reset[0x20];
967 u8 rpg_byte_reset[0x20];
969 u8 rpg_threshold[0x20];
971 u8 rpg_max_rate[0x20];
973 u8 rpg_ai_rate[0x20];
975 u8 rpg_hai_rate[0x20];
979 u8 rpg_min_dec_fac[0x20];
981 u8 rpg_min_rate[0x20];
983 u8 reserved_1[0x640];
987 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
988 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
989 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
992 struct mlx5_ifc_resize_field_select_bits {
993 u8 resize_field_select[0x20];
997 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
998 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
999 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1000 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1003 struct mlx5_ifc_modify_field_select_bits {
1004 u8 modify_field_select[0x20];
1007 struct mlx5_ifc_field_select_r_roce_np_bits {
1008 u8 field_select_r_roce_np[0x20];
1011 struct mlx5_ifc_field_select_r_roce_rp_bits {
1012 u8 field_select_r_roce_rp[0x20];
1016 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1017 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1018 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1019 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1020 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1021 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1022 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1023 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1024 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1025 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1028 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1029 u8 field_select_8021qaurp[0x20];
1032 struct mlx5_ifc_phys_layer_cntrs_bits {
1033 u8 time_since_last_clear_high[0x20];
1035 u8 time_since_last_clear_low[0x20];
1037 u8 symbol_errors_high[0x20];
1039 u8 symbol_errors_low[0x20];
1041 u8 sync_headers_errors_high[0x20];
1043 u8 sync_headers_errors_low[0x20];
1045 u8 edpl_bip_errors_lane0_high[0x20];
1047 u8 edpl_bip_errors_lane0_low[0x20];
1049 u8 edpl_bip_errors_lane1_high[0x20];
1051 u8 edpl_bip_errors_lane1_low[0x20];
1053 u8 edpl_bip_errors_lane2_high[0x20];
1055 u8 edpl_bip_errors_lane2_low[0x20];
1057 u8 edpl_bip_errors_lane3_high[0x20];
1059 u8 edpl_bip_errors_lane3_low[0x20];
1061 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1063 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1065 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1067 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1069 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1071 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1073 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1075 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1077 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1079 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1081 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1083 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1085 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1087 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1089 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1091 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1093 u8 rs_fec_corrected_blocks_high[0x20];
1095 u8 rs_fec_corrected_blocks_low[0x20];
1097 u8 rs_fec_uncorrectable_blocks_high[0x20];
1099 u8 rs_fec_uncorrectable_blocks_low[0x20];
1101 u8 rs_fec_no_errors_blocks_high[0x20];
1103 u8 rs_fec_no_errors_blocks_low[0x20];
1105 u8 rs_fec_single_error_blocks_high[0x20];
1107 u8 rs_fec_single_error_blocks_low[0x20];
1109 u8 rs_fec_corrected_symbols_total_high[0x20];
1111 u8 rs_fec_corrected_symbols_total_low[0x20];
1113 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1115 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1117 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1119 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1121 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1123 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1125 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1127 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1129 u8 link_down_events[0x20];
1131 u8 successful_recovery_events[0x20];
1133 u8 reserved_0[0x180];
1136 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1137 u8 transmit_queue_high[0x20];
1139 u8 transmit_queue_low[0x20];
1141 u8 reserved_0[0x780];
1144 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1145 u8 rx_octets_high[0x20];
1147 u8 rx_octets_low[0x20];
1149 u8 reserved_0[0xc0];
1151 u8 rx_frames_high[0x20];
1153 u8 rx_frames_low[0x20];
1155 u8 tx_octets_high[0x20];
1157 u8 tx_octets_low[0x20];
1159 u8 reserved_1[0xc0];
1161 u8 tx_frames_high[0x20];
1163 u8 tx_frames_low[0x20];
1165 u8 rx_pause_high[0x20];
1167 u8 rx_pause_low[0x20];
1169 u8 rx_pause_duration_high[0x20];
1171 u8 rx_pause_duration_low[0x20];
1173 u8 tx_pause_high[0x20];
1175 u8 tx_pause_low[0x20];
1177 u8 tx_pause_duration_high[0x20];
1179 u8 tx_pause_duration_low[0x20];
1181 u8 rx_pause_transition_high[0x20];
1183 u8 rx_pause_transition_low[0x20];
1185 u8 reserved_2[0x400];
1188 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1189 u8 port_transmit_wait_high[0x20];
1191 u8 port_transmit_wait_low[0x20];
1193 u8 reserved_0[0x780];
1196 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1197 u8 dot3stats_alignment_errors_high[0x20];
1199 u8 dot3stats_alignment_errors_low[0x20];
1201 u8 dot3stats_fcs_errors_high[0x20];
1203 u8 dot3stats_fcs_errors_low[0x20];
1205 u8 dot3stats_single_collision_frames_high[0x20];
1207 u8 dot3stats_single_collision_frames_low[0x20];
1209 u8 dot3stats_multiple_collision_frames_high[0x20];
1211 u8 dot3stats_multiple_collision_frames_low[0x20];
1213 u8 dot3stats_sqe_test_errors_high[0x20];
1215 u8 dot3stats_sqe_test_errors_low[0x20];
1217 u8 dot3stats_deferred_transmissions_high[0x20];
1219 u8 dot3stats_deferred_transmissions_low[0x20];
1221 u8 dot3stats_late_collisions_high[0x20];
1223 u8 dot3stats_late_collisions_low[0x20];
1225 u8 dot3stats_excessive_collisions_high[0x20];
1227 u8 dot3stats_excessive_collisions_low[0x20];
1229 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1231 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1233 u8 dot3stats_carrier_sense_errors_high[0x20];
1235 u8 dot3stats_carrier_sense_errors_low[0x20];
1237 u8 dot3stats_frame_too_longs_high[0x20];
1239 u8 dot3stats_frame_too_longs_low[0x20];
1241 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1243 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1245 u8 dot3stats_symbol_errors_high[0x20];
1247 u8 dot3stats_symbol_errors_low[0x20];
1249 u8 dot3control_in_unknown_opcodes_high[0x20];
1251 u8 dot3control_in_unknown_opcodes_low[0x20];
1253 u8 dot3in_pause_frames_high[0x20];
1255 u8 dot3in_pause_frames_low[0x20];
1257 u8 dot3out_pause_frames_high[0x20];
1259 u8 dot3out_pause_frames_low[0x20];
1261 u8 reserved_0[0x3c0];
1264 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1265 u8 ether_stats_drop_events_high[0x20];
1267 u8 ether_stats_drop_events_low[0x20];
1269 u8 ether_stats_octets_high[0x20];
1271 u8 ether_stats_octets_low[0x20];
1273 u8 ether_stats_pkts_high[0x20];
1275 u8 ether_stats_pkts_low[0x20];
1277 u8 ether_stats_broadcast_pkts_high[0x20];
1279 u8 ether_stats_broadcast_pkts_low[0x20];
1281 u8 ether_stats_multicast_pkts_high[0x20];
1283 u8 ether_stats_multicast_pkts_low[0x20];
1285 u8 ether_stats_crc_align_errors_high[0x20];
1287 u8 ether_stats_crc_align_errors_low[0x20];
1289 u8 ether_stats_undersize_pkts_high[0x20];
1291 u8 ether_stats_undersize_pkts_low[0x20];
1293 u8 ether_stats_oversize_pkts_high[0x20];
1295 u8 ether_stats_oversize_pkts_low[0x20];
1297 u8 ether_stats_fragments_high[0x20];
1299 u8 ether_stats_fragments_low[0x20];
1301 u8 ether_stats_jabbers_high[0x20];
1303 u8 ether_stats_jabbers_low[0x20];
1305 u8 ether_stats_collisions_high[0x20];
1307 u8 ether_stats_collisions_low[0x20];
1309 u8 ether_stats_pkts64octets_high[0x20];
1311 u8 ether_stats_pkts64octets_low[0x20];
1313 u8 ether_stats_pkts65to127octets_high[0x20];
1315 u8 ether_stats_pkts65to127octets_low[0x20];
1317 u8 ether_stats_pkts128to255octets_high[0x20];
1319 u8 ether_stats_pkts128to255octets_low[0x20];
1321 u8 ether_stats_pkts256to511octets_high[0x20];
1323 u8 ether_stats_pkts256to511octets_low[0x20];
1325 u8 ether_stats_pkts512to1023octets_high[0x20];
1327 u8 ether_stats_pkts512to1023octets_low[0x20];
1329 u8 ether_stats_pkts1024to1518octets_high[0x20];
1331 u8 ether_stats_pkts1024to1518octets_low[0x20];
1333 u8 ether_stats_pkts1519to2047octets_high[0x20];
1335 u8 ether_stats_pkts1519to2047octets_low[0x20];
1337 u8 ether_stats_pkts2048to4095octets_high[0x20];
1339 u8 ether_stats_pkts2048to4095octets_low[0x20];
1341 u8 ether_stats_pkts4096to8191octets_high[0x20];
1343 u8 ether_stats_pkts4096to8191octets_low[0x20];
1345 u8 ether_stats_pkts8192to10239octets_high[0x20];
1347 u8 ether_stats_pkts8192to10239octets_low[0x20];
1349 u8 reserved_0[0x280];
1352 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1353 u8 if_in_octets_high[0x20];
1355 u8 if_in_octets_low[0x20];
1357 u8 if_in_ucast_pkts_high[0x20];
1359 u8 if_in_ucast_pkts_low[0x20];
1361 u8 if_in_discards_high[0x20];
1363 u8 if_in_discards_low[0x20];
1365 u8 if_in_errors_high[0x20];
1367 u8 if_in_errors_low[0x20];
1369 u8 if_in_unknown_protos_high[0x20];
1371 u8 if_in_unknown_protos_low[0x20];
1373 u8 if_out_octets_high[0x20];
1375 u8 if_out_octets_low[0x20];
1377 u8 if_out_ucast_pkts_high[0x20];
1379 u8 if_out_ucast_pkts_low[0x20];
1381 u8 if_out_discards_high[0x20];
1383 u8 if_out_discards_low[0x20];
1385 u8 if_out_errors_high[0x20];
1387 u8 if_out_errors_low[0x20];
1389 u8 if_in_multicast_pkts_high[0x20];
1391 u8 if_in_multicast_pkts_low[0x20];
1393 u8 if_in_broadcast_pkts_high[0x20];
1395 u8 if_in_broadcast_pkts_low[0x20];
1397 u8 if_out_multicast_pkts_high[0x20];
1399 u8 if_out_multicast_pkts_low[0x20];
1401 u8 if_out_broadcast_pkts_high[0x20];
1403 u8 if_out_broadcast_pkts_low[0x20];
1405 u8 reserved_0[0x480];
1408 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1409 u8 a_frames_transmitted_ok_high[0x20];
1411 u8 a_frames_transmitted_ok_low[0x20];
1413 u8 a_frames_received_ok_high[0x20];
1415 u8 a_frames_received_ok_low[0x20];
1417 u8 a_frame_check_sequence_errors_high[0x20];
1419 u8 a_frame_check_sequence_errors_low[0x20];
1421 u8 a_alignment_errors_high[0x20];
1423 u8 a_alignment_errors_low[0x20];
1425 u8 a_octets_transmitted_ok_high[0x20];
1427 u8 a_octets_transmitted_ok_low[0x20];
1429 u8 a_octets_received_ok_high[0x20];
1431 u8 a_octets_received_ok_low[0x20];
1433 u8 a_multicast_frames_xmitted_ok_high[0x20];
1435 u8 a_multicast_frames_xmitted_ok_low[0x20];
1437 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1439 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1441 u8 a_multicast_frames_received_ok_high[0x20];
1443 u8 a_multicast_frames_received_ok_low[0x20];
1445 u8 a_broadcast_frames_received_ok_high[0x20];
1447 u8 a_broadcast_frames_received_ok_low[0x20];
1449 u8 a_in_range_length_errors_high[0x20];
1451 u8 a_in_range_length_errors_low[0x20];
1453 u8 a_out_of_range_length_field_high[0x20];
1455 u8 a_out_of_range_length_field_low[0x20];
1457 u8 a_frame_too_long_errors_high[0x20];
1459 u8 a_frame_too_long_errors_low[0x20];
1461 u8 a_symbol_error_during_carrier_high[0x20];
1463 u8 a_symbol_error_during_carrier_low[0x20];
1465 u8 a_mac_control_frames_transmitted_high[0x20];
1467 u8 a_mac_control_frames_transmitted_low[0x20];
1469 u8 a_mac_control_frames_received_high[0x20];
1471 u8 a_mac_control_frames_received_low[0x20];
1473 u8 a_unsupported_opcodes_received_high[0x20];
1475 u8 a_unsupported_opcodes_received_low[0x20];
1477 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1479 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1481 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1483 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1485 u8 reserved_0[0x300];
1488 struct mlx5_ifc_cmd_inter_comp_event_bits {
1489 u8 command_completion_vector[0x20];
1491 u8 reserved_0[0xc0];
1494 struct mlx5_ifc_stall_vl_event_bits {
1495 u8 reserved_0[0x18];
1500 u8 reserved_2[0xa0];
1503 struct mlx5_ifc_db_bf_congestion_event_bits {
1504 u8 event_subtype[0x8];
1506 u8 congestion_level[0x8];
1509 u8 reserved_2[0xa0];
1512 struct mlx5_ifc_gpio_event_bits {
1513 u8 reserved_0[0x60];
1515 u8 gpio_event_hi[0x20];
1517 u8 gpio_event_lo[0x20];
1519 u8 reserved_1[0x40];
1522 struct mlx5_ifc_port_state_change_event_bits {
1523 u8 reserved_0[0x40];
1526 u8 reserved_1[0x1c];
1528 u8 reserved_2[0x80];
1531 struct mlx5_ifc_dropped_packet_logged_bits {
1532 u8 reserved_0[0xe0];
1536 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1537 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1540 struct mlx5_ifc_cq_error_bits {
1544 u8 reserved_1[0x20];
1546 u8 reserved_2[0x18];
1549 u8 reserved_3[0x80];
1552 struct mlx5_ifc_rdma_page_fault_event_bits {
1553 u8 bytes_committed[0x20];
1557 u8 reserved_0[0x10];
1558 u8 packet_len[0x10];
1560 u8 rdma_op_len[0x20];
1571 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1572 u8 bytes_committed[0x20];
1574 u8 reserved_0[0x10];
1577 u8 reserved_1[0x10];
1580 u8 reserved_2[0x60];
1589 struct mlx5_ifc_qp_events_bits {
1590 u8 reserved_0[0xa0];
1593 u8 reserved_1[0x18];
1596 u8 qpn_rqn_sqn[0x18];
1599 struct mlx5_ifc_dct_events_bits {
1600 u8 reserved_0[0xc0];
1603 u8 dct_number[0x18];
1606 struct mlx5_ifc_comp_event_bits {
1607 u8 reserved_0[0xc0];
1614 MLX5_QPC_STATE_RST = 0x0,
1615 MLX5_QPC_STATE_INIT = 0x1,
1616 MLX5_QPC_STATE_RTR = 0x2,
1617 MLX5_QPC_STATE_RTS = 0x3,
1618 MLX5_QPC_STATE_SQER = 0x4,
1619 MLX5_QPC_STATE_ERR = 0x6,
1620 MLX5_QPC_STATE_SQD = 0x7,
1621 MLX5_QPC_STATE_SUSPENDED = 0x9,
1625 MLX5_QPC_ST_RC = 0x0,
1626 MLX5_QPC_ST_UC = 0x1,
1627 MLX5_QPC_ST_UD = 0x2,
1628 MLX5_QPC_ST_XRC = 0x3,
1629 MLX5_QPC_ST_DCI = 0x5,
1630 MLX5_QPC_ST_QP0 = 0x7,
1631 MLX5_QPC_ST_QP1 = 0x8,
1632 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1633 MLX5_QPC_ST_REG_UMR = 0xc,
1637 MLX5_QPC_PM_STATE_ARMED = 0x0,
1638 MLX5_QPC_PM_STATE_REARM = 0x1,
1639 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1640 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1644 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1645 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1649 MLX5_QPC_MTU_256_BYTES = 0x1,
1650 MLX5_QPC_MTU_512_BYTES = 0x2,
1651 MLX5_QPC_MTU_1K_BYTES = 0x3,
1652 MLX5_QPC_MTU_2K_BYTES = 0x4,
1653 MLX5_QPC_MTU_4K_BYTES = 0x5,
1654 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1658 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1659 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1660 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1661 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1662 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1663 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1664 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1665 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1669 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1670 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1671 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1675 MLX5_QPC_CS_RES_DISABLE = 0x0,
1676 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1677 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1680 struct mlx5_ifc_qpc_bits {
1687 u8 end_padding_mode[0x2];
1690 u8 wq_signature[0x1];
1691 u8 block_lb_mc[0x1];
1692 u8 atomic_like_write_en[0x1];
1693 u8 latency_sensitive[0x1];
1695 u8 drain_sigerr[0x1];
1700 u8 log_msg_max[0x5];
1702 u8 log_rq_size[0x4];
1703 u8 log_rq_stride[0x3];
1705 u8 log_sq_size[0x4];
1710 u8 counter_set_id[0x8];
1714 u8 user_index[0x18];
1716 u8 reserved_10[0x3];
1717 u8 log_page_size[0x5];
1718 u8 remote_qpn[0x18];
1720 struct mlx5_ifc_ads_bits primary_address_path;
1722 struct mlx5_ifc_ads_bits secondary_address_path;
1724 u8 log_ack_req_freq[0x4];
1725 u8 reserved_11[0x4];
1726 u8 log_sra_max[0x3];
1727 u8 reserved_12[0x2];
1728 u8 retry_count[0x3];
1730 u8 reserved_13[0x1];
1732 u8 cur_rnr_retry[0x3];
1733 u8 cur_retry_count[0x3];
1734 u8 reserved_14[0x5];
1736 u8 reserved_15[0x20];
1738 u8 reserved_16[0x8];
1739 u8 next_send_psn[0x18];
1741 u8 reserved_17[0x8];
1744 u8 reserved_18[0x40];
1746 u8 reserved_19[0x8];
1747 u8 last_acked_psn[0x18];
1749 u8 reserved_20[0x8];
1752 u8 reserved_21[0x8];
1753 u8 log_rra_max[0x3];
1754 u8 reserved_22[0x1];
1755 u8 atomic_mode[0x4];
1759 u8 reserved_23[0x1];
1760 u8 page_offset[0x6];
1761 u8 reserved_24[0x3];
1762 u8 cd_slave_receive[0x1];
1763 u8 cd_slave_send[0x1];
1766 u8 reserved_25[0x3];
1767 u8 min_rnr_nak[0x5];
1768 u8 next_rcv_psn[0x18];
1770 u8 reserved_26[0x8];
1773 u8 reserved_27[0x8];
1780 u8 reserved_28[0x5];
1784 u8 reserved_29[0x8];
1787 u8 hw_sq_wqebb_counter[0x10];
1788 u8 sw_sq_wqebb_counter[0x10];
1790 u8 hw_rq_counter[0x20];
1792 u8 sw_rq_counter[0x20];
1794 u8 reserved_30[0x20];
1796 u8 reserved_31[0xf];
1801 u8 dc_access_key[0x40];
1803 u8 reserved_32[0xc0];
1806 struct mlx5_ifc_roce_addr_layout_bits {
1807 u8 source_l3_address[16][0x8];
1812 u8 source_mac_47_32[0x10];
1814 u8 source_mac_31_0[0x20];
1816 u8 reserved_1[0x14];
1817 u8 roce_l3_type[0x4];
1818 u8 roce_version[0x8];
1820 u8 reserved_2[0x20];
1823 union mlx5_ifc_hca_cap_union_bits {
1824 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1825 struct mlx5_ifc_odp_cap_bits odp_cap;
1826 struct mlx5_ifc_atomic_caps_bits atomic_caps;
1827 struct mlx5_ifc_roce_cap_bits roce_cap;
1828 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1829 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1830 u8 reserved_0[0x8000];
1834 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
1835 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
1836 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
1839 struct mlx5_ifc_flow_context_bits {
1840 u8 reserved_0[0x20];
1847 u8 reserved_2[0x10];
1851 u8 destination_list_size[0x18];
1853 u8 reserved_4[0x160];
1855 struct mlx5_ifc_fte_match_param_bits match_value;
1857 u8 reserved_5[0x600];
1859 struct mlx5_ifc_dest_format_struct_bits destination[0];
1863 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
1864 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
1867 struct mlx5_ifc_xrc_srqc_bits {
1869 u8 log_xrc_srq_size[0x4];
1870 u8 reserved_0[0x18];
1872 u8 wq_signature[0x1];
1876 u8 basic_cyclic_rcv_wqe[0x1];
1877 u8 log_rq_stride[0x3];
1880 u8 page_offset[0x6];
1884 u8 reserved_3[0x20];
1886 u8 user_index_equal_xrc_srqn[0x1];
1888 u8 log_page_size[0x6];
1889 u8 user_index[0x18];
1891 u8 reserved_5[0x20];
1899 u8 reserved_7[0x40];
1901 u8 db_record_addr_h[0x20];
1903 u8 db_record_addr_l[0x1e];
1906 u8 reserved_9[0x80];
1909 struct mlx5_ifc_traffic_counter_bits {
1915 struct mlx5_ifc_tisc_bits {
1918 u8 reserved_1[0x10];
1920 u8 reserved_2[0x100];
1923 u8 transport_domain[0x18];
1925 u8 reserved_4[0x3c0];
1929 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1930 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
1934 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
1935 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
1939 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0,
1940 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1,
1941 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2,
1945 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
1946 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
1949 struct mlx5_ifc_tirc_bits {
1950 u8 reserved_0[0x20];
1953 u8 reserved_1[0x1c];
1955 u8 reserved_2[0x40];
1958 u8 lro_timeout_period_usecs[0x10];
1959 u8 lro_enable_mask[0x4];
1960 u8 lro_max_ip_payload_size[0x8];
1962 u8 reserved_4[0x40];
1965 u8 inline_rqn[0x18];
1967 u8 rx_hash_symmetric[0x1];
1969 u8 tunneled_offload_en[0x1];
1971 u8 indirect_table[0x18];
1975 u8 self_lb_block[0x2];
1976 u8 transport_domain[0x18];
1978 u8 rx_hash_toeplitz_key[10][0x20];
1980 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1982 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1984 u8 reserved_9[0x4c0];
1988 MLX5_SRQC_STATE_GOOD = 0x0,
1989 MLX5_SRQC_STATE_ERROR = 0x1,
1992 struct mlx5_ifc_srqc_bits {
1994 u8 log_srq_size[0x4];
1995 u8 reserved_0[0x18];
1997 u8 wq_signature[0x1];
2002 u8 log_rq_stride[0x3];
2005 u8 page_offset[0x6];
2009 u8 reserved_4[0x20];
2012 u8 log_page_size[0x6];
2013 u8 reserved_6[0x18];
2015 u8 reserved_7[0x20];
2023 u8 reserved_9[0x40];
2025 u8 db_record_addr_h[0x20];
2027 u8 db_record_addr_l[0x1e];
2028 u8 reserved_10[0x2];
2030 u8 reserved_11[0x80];
2034 MLX5_SQC_STATE_RST = 0x0,
2035 MLX5_SQC_STATE_RDY = 0x1,
2036 MLX5_SQC_STATE_ERR = 0x3,
2039 struct mlx5_ifc_sqc_bits {
2043 u8 flush_in_error_en[0x1];
2046 u8 reserved_1[0x14];
2049 u8 user_index[0x18];
2054 u8 reserved_4[0xa0];
2056 u8 tis_lst_sz[0x10];
2057 u8 reserved_5[0x10];
2059 u8 reserved_6[0x40];
2064 struct mlx5_ifc_wq_bits wq;
2067 struct mlx5_ifc_rqtc_bits {
2068 u8 reserved_0[0xa0];
2070 u8 reserved_1[0x10];
2071 u8 rqt_max_size[0x10];
2073 u8 reserved_2[0x10];
2074 u8 rqt_actual_size[0x10];
2076 u8 reserved_3[0x6a0];
2078 struct mlx5_ifc_rq_num_bits rq_num[0];
2082 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2083 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2087 MLX5_RQC_STATE_RST = 0x0,
2088 MLX5_RQC_STATE_RDY = 0x1,
2089 MLX5_RQC_STATE_ERR = 0x3,
2092 struct mlx5_ifc_rqc_bits {
2096 u8 mem_rq_type[0x4];
2099 u8 flush_in_error_en[0x1];
2100 u8 reserved_2[0x12];
2103 u8 user_index[0x18];
2108 u8 counter_set_id[0x8];
2109 u8 reserved_5[0x18];
2114 u8 reserved_7[0xe0];
2116 struct mlx5_ifc_wq_bits wq;
2120 MLX5_RMPC_STATE_RDY = 0x1,
2121 MLX5_RMPC_STATE_ERR = 0x3,
2124 struct mlx5_ifc_rmpc_bits {
2127 u8 reserved_1[0x14];
2129 u8 basic_cyclic_rcv_wqe[0x1];
2130 u8 reserved_2[0x1f];
2132 u8 reserved_3[0x140];
2134 struct mlx5_ifc_wq_bits wq;
2138 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0,
2141 struct mlx5_ifc_nic_vport_context_bits {
2142 u8 reserved_0[0x1f];
2145 u8 reserved_1[0x760];
2148 u8 allowed_list_type[0x3];
2150 u8 allowed_list_size[0xc];
2152 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2154 u8 reserved_4[0x20];
2156 u8 current_uc_mac_address[0][0x40];
2160 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2161 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2162 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2165 struct mlx5_ifc_mkc_bits {
2169 u8 small_fence_on_rdma_read_response[0x1];
2176 u8 access_mode[0x2];
2182 u8 reserved_3[0x20];
2188 u8 expected_sigerr_count[0x1];
2193 u8 start_addr[0x40];
2197 u8 bsf_octword_size[0x20];
2199 u8 reserved_6[0x80];
2201 u8 translations_octword_size[0x20];
2203 u8 reserved_7[0x1b];
2204 u8 log_page_size[0x5];
2206 u8 reserved_8[0x20];
2209 struct mlx5_ifc_pkey_bits {
2210 u8 reserved_0[0x10];
2214 struct mlx5_ifc_array128_auto_bits {
2215 u8 array128_auto[16][0x8];
2218 struct mlx5_ifc_hca_vport_context_bits {
2219 u8 field_select[0x20];
2221 u8 reserved_0[0xe0];
2223 u8 sm_virt_aware[0x1];
2226 u8 grh_required[0x1];
2227 u8 reserved_1[0x10];
2228 u8 port_state_policy[0x4];
2229 u8 phy_port_state[0x4];
2230 u8 vport_state[0x4];
2232 u8 reserved_2[0x60];
2240 u8 cap_mask1_field_select[0x20];
2244 u8 cap_mask2_field_select[0x20];
2246 u8 reserved_3[0x80];
2250 u8 init_type_reply[0x4];
2252 u8 subnet_timeout[0x5];
2258 u8 qkey_violation_counter[0x10];
2259 u8 pkey_violation_counter[0x10];
2261 u8 reserved_6[0xca0];
2265 MLX5_EQC_STATUS_OK = 0x0,
2266 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2270 MLX5_EQC_ST_ARMED = 0x9,
2271 MLX5_EQC_ST_FIRED = 0xa,
2274 struct mlx5_ifc_eqc_bits {
2283 u8 reserved_3[0x20];
2285 u8 reserved_4[0x14];
2286 u8 page_offset[0x6];
2290 u8 log_eq_size[0x5];
2293 u8 reserved_7[0x20];
2295 u8 reserved_8[0x18];
2299 u8 log_page_size[0x5];
2300 u8 reserved_10[0x18];
2302 u8 reserved_11[0x60];
2304 u8 reserved_12[0x8];
2305 u8 consumer_counter[0x18];
2307 u8 reserved_13[0x8];
2308 u8 producer_counter[0x18];
2310 u8 reserved_14[0x80];
2314 MLX5_DCTC_STATE_ACTIVE = 0x0,
2315 MLX5_DCTC_STATE_DRAINING = 0x1,
2316 MLX5_DCTC_STATE_DRAINED = 0x2,
2320 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2321 MLX5_DCTC_CS_RES_NA = 0x1,
2322 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2326 MLX5_DCTC_MTU_256_BYTES = 0x1,
2327 MLX5_DCTC_MTU_512_BYTES = 0x2,
2328 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2329 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2330 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2333 struct mlx5_ifc_dctc_bits {
2336 u8 reserved_1[0x18];
2339 u8 user_index[0x18];
2344 u8 counter_set_id[0x8];
2345 u8 atomic_mode[0x4];
2349 u8 atomic_like_write_en[0x1];
2350 u8 latency_sensitive[0x1];
2358 u8 min_rnr_nak[0x5];
2368 u8 reserved_10[0x4];
2369 u8 flow_label[0x14];
2371 u8 dc_access_key[0x40];
2373 u8 reserved_11[0x5];
2376 u8 pkey_index[0x10];
2378 u8 reserved_12[0x8];
2379 u8 my_addr_index[0x8];
2380 u8 reserved_13[0x8];
2383 u8 dc_access_key_violation_count[0x20];
2385 u8 reserved_14[0x14];
2391 u8 reserved_15[0x40];
2395 MLX5_CQC_STATUS_OK = 0x0,
2396 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2397 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2401 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2402 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2406 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2407 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2408 MLX5_CQC_ST_FIRED = 0xa,
2411 struct mlx5_ifc_cqc_bits {
2417 u8 scqe_break_moderation_en[0x1];
2421 u8 mini_cqe_res_format[0x2];
2425 u8 reserved_4[0x20];
2427 u8 reserved_5[0x14];
2428 u8 page_offset[0x6];
2432 u8 log_cq_size[0x5];
2437 u8 cq_max_count[0x10];
2439 u8 reserved_9[0x18];
2442 u8 reserved_10[0x3];
2443 u8 log_page_size[0x5];
2444 u8 reserved_11[0x18];
2446 u8 reserved_12[0x20];
2448 u8 reserved_13[0x8];
2449 u8 last_notified_index[0x18];
2451 u8 reserved_14[0x8];
2452 u8 last_solicit_index[0x18];
2454 u8 reserved_15[0x8];
2455 u8 consumer_counter[0x18];
2457 u8 reserved_16[0x8];
2458 u8 producer_counter[0x18];
2460 u8 reserved_17[0x40];
2465 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2466 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2467 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2468 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2469 u8 reserved_0[0x800];
2472 struct mlx5_ifc_query_adapter_param_block_bits {
2473 u8 reserved_0[0xe0];
2475 u8 reserved_1[0x10];
2476 u8 vsd_vendor_id[0x10];
2480 u8 vsd_contd_psid[16][0x8];
2483 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2484 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2485 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2486 u8 reserved_0[0x20];
2489 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2490 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2491 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2492 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2493 u8 reserved_0[0x20];
2496 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2497 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2498 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2499 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2500 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2501 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2502 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2503 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2504 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2505 u8 reserved_0[0x7c0];
2508 union mlx5_ifc_event_auto_bits {
2509 struct mlx5_ifc_comp_event_bits comp_event;
2510 struct mlx5_ifc_dct_events_bits dct_events;
2511 struct mlx5_ifc_qp_events_bits qp_events;
2512 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2513 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2514 struct mlx5_ifc_cq_error_bits cq_error;
2515 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2516 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2517 struct mlx5_ifc_gpio_event_bits gpio_event;
2518 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2519 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2520 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2521 u8 reserved_0[0xe0];
2524 struct mlx5_ifc_health_buffer_bits {
2525 u8 reserved_0[0x100];
2527 u8 assert_existptr[0x20];
2529 u8 assert_callra[0x20];
2531 u8 reserved_1[0x40];
2533 u8 fw_version[0x20];
2537 u8 reserved_2[0x20];
2539 u8 irisc_index[0x8];
2544 struct mlx5_ifc_register_loopback_control_bits {
2548 u8 reserved_1[0x10];
2550 u8 reserved_2[0x60];
2553 struct mlx5_ifc_teardown_hca_out_bits {
2555 u8 reserved_0[0x18];
2559 u8 reserved_1[0x40];
2563 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2564 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2567 struct mlx5_ifc_teardown_hca_in_bits {
2569 u8 reserved_0[0x10];
2571 u8 reserved_1[0x10];
2574 u8 reserved_2[0x10];
2577 u8 reserved_3[0x20];
2580 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2582 u8 reserved_0[0x18];
2586 u8 reserved_1[0x40];
2589 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2591 u8 reserved_0[0x10];
2593 u8 reserved_1[0x10];
2599 u8 reserved_3[0x20];
2601 u8 opt_param_mask[0x20];
2603 u8 reserved_4[0x20];
2605 struct mlx5_ifc_qpc_bits qpc;
2607 u8 reserved_5[0x80];
2610 struct mlx5_ifc_sqd2rts_qp_out_bits {
2612 u8 reserved_0[0x18];
2616 u8 reserved_1[0x40];
2619 struct mlx5_ifc_sqd2rts_qp_in_bits {
2621 u8 reserved_0[0x10];
2623 u8 reserved_1[0x10];
2629 u8 reserved_3[0x20];
2631 u8 opt_param_mask[0x20];
2633 u8 reserved_4[0x20];
2635 struct mlx5_ifc_qpc_bits qpc;
2637 u8 reserved_5[0x80];
2640 struct mlx5_ifc_set_roce_address_out_bits {
2642 u8 reserved_0[0x18];
2646 u8 reserved_1[0x40];
2649 struct mlx5_ifc_set_roce_address_in_bits {
2651 u8 reserved_0[0x10];
2653 u8 reserved_1[0x10];
2656 u8 roce_address_index[0x10];
2657 u8 reserved_2[0x10];
2659 u8 reserved_3[0x20];
2661 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2664 struct mlx5_ifc_set_mad_demux_out_bits {
2666 u8 reserved_0[0x18];
2670 u8 reserved_1[0x40];
2674 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2675 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2678 struct mlx5_ifc_set_mad_demux_in_bits {
2680 u8 reserved_0[0x10];
2682 u8 reserved_1[0x10];
2685 u8 reserved_2[0x20];
2689 u8 reserved_4[0x18];
2692 struct mlx5_ifc_set_l2_table_entry_out_bits {
2694 u8 reserved_0[0x18];
2698 u8 reserved_1[0x40];
2701 struct mlx5_ifc_set_l2_table_entry_in_bits {
2703 u8 reserved_0[0x10];
2705 u8 reserved_1[0x10];
2708 u8 reserved_2[0x60];
2711 u8 table_index[0x18];
2713 u8 reserved_4[0x20];
2715 u8 reserved_5[0x13];
2719 struct mlx5_ifc_mac_address_layout_bits mac_address;
2721 u8 reserved_6[0xc0];
2724 struct mlx5_ifc_set_issi_out_bits {
2726 u8 reserved_0[0x18];
2730 u8 reserved_1[0x40];
2733 struct mlx5_ifc_set_issi_in_bits {
2735 u8 reserved_0[0x10];
2737 u8 reserved_1[0x10];
2740 u8 reserved_2[0x10];
2741 u8 current_issi[0x10];
2743 u8 reserved_3[0x20];
2746 struct mlx5_ifc_set_hca_cap_out_bits {
2748 u8 reserved_0[0x18];
2752 u8 reserved_1[0x40];
2755 struct mlx5_ifc_set_hca_cap_in_bits {
2757 u8 reserved_0[0x10];
2759 u8 reserved_1[0x10];
2762 u8 reserved_2[0x40];
2764 union mlx5_ifc_hca_cap_union_bits capability;
2767 struct mlx5_ifc_set_fte_out_bits {
2769 u8 reserved_0[0x18];
2773 u8 reserved_1[0x40];
2776 struct mlx5_ifc_set_fte_in_bits {
2778 u8 reserved_0[0x10];
2780 u8 reserved_1[0x10];
2783 u8 reserved_2[0x40];
2786 u8 reserved_3[0x18];
2791 u8 reserved_5[0x40];
2793 u8 flow_index[0x20];
2795 u8 reserved_6[0xe0];
2797 struct mlx5_ifc_flow_context_bits flow_context;
2800 struct mlx5_ifc_rts2rts_qp_out_bits {
2802 u8 reserved_0[0x18];
2806 u8 reserved_1[0x40];
2809 struct mlx5_ifc_rts2rts_qp_in_bits {
2811 u8 reserved_0[0x10];
2813 u8 reserved_1[0x10];
2819 u8 reserved_3[0x20];
2821 u8 opt_param_mask[0x20];
2823 u8 reserved_4[0x20];
2825 struct mlx5_ifc_qpc_bits qpc;
2827 u8 reserved_5[0x80];
2830 struct mlx5_ifc_rtr2rts_qp_out_bits {
2832 u8 reserved_0[0x18];
2836 u8 reserved_1[0x40];
2839 struct mlx5_ifc_rtr2rts_qp_in_bits {
2841 u8 reserved_0[0x10];
2843 u8 reserved_1[0x10];
2849 u8 reserved_3[0x20];
2851 u8 opt_param_mask[0x20];
2853 u8 reserved_4[0x20];
2855 struct mlx5_ifc_qpc_bits qpc;
2857 u8 reserved_5[0x80];
2860 struct mlx5_ifc_rst2init_qp_out_bits {
2862 u8 reserved_0[0x18];
2866 u8 reserved_1[0x40];
2869 struct mlx5_ifc_rst2init_qp_in_bits {
2871 u8 reserved_0[0x10];
2873 u8 reserved_1[0x10];
2879 u8 reserved_3[0x20];
2881 u8 opt_param_mask[0x20];
2883 u8 reserved_4[0x20];
2885 struct mlx5_ifc_qpc_bits qpc;
2887 u8 reserved_5[0x80];
2890 struct mlx5_ifc_query_xrc_srq_out_bits {
2892 u8 reserved_0[0x18];
2896 u8 reserved_1[0x40];
2898 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
2900 u8 reserved_2[0x600];
2905 struct mlx5_ifc_query_xrc_srq_in_bits {
2907 u8 reserved_0[0x10];
2909 u8 reserved_1[0x10];
2915 u8 reserved_3[0x20];
2919 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
2920 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
2923 struct mlx5_ifc_query_vport_state_out_bits {
2925 u8 reserved_0[0x18];
2929 u8 reserved_1[0x20];
2931 u8 reserved_2[0x18];
2932 u8 admin_state[0x4];
2937 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
2940 struct mlx5_ifc_query_vport_state_in_bits {
2942 u8 reserved_0[0x10];
2944 u8 reserved_1[0x10];
2947 u8 other_vport[0x1];
2949 u8 vport_number[0x10];
2951 u8 reserved_3[0x20];
2954 struct mlx5_ifc_query_vport_counter_out_bits {
2956 u8 reserved_0[0x18];
2960 u8 reserved_1[0x40];
2962 struct mlx5_ifc_traffic_counter_bits received_errors;
2964 struct mlx5_ifc_traffic_counter_bits transmit_errors;
2966 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
2968 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
2970 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
2972 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
2974 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
2976 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
2978 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
2980 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
2982 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
2984 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
2986 u8 reserved_2[0xa00];
2990 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
2993 struct mlx5_ifc_query_vport_counter_in_bits {
2995 u8 reserved_0[0x10];
2997 u8 reserved_1[0x10];
3000 u8 other_vport[0x1];
3002 u8 vport_number[0x10];
3004 u8 reserved_3[0x60];
3007 u8 reserved_4[0x1f];
3009 u8 reserved_5[0x20];
3012 struct mlx5_ifc_query_tis_out_bits {
3014 u8 reserved_0[0x18];
3018 u8 reserved_1[0x40];
3020 struct mlx5_ifc_tisc_bits tis_context;
3023 struct mlx5_ifc_query_tis_in_bits {
3025 u8 reserved_0[0x10];
3027 u8 reserved_1[0x10];
3033 u8 reserved_3[0x20];
3036 struct mlx5_ifc_query_tir_out_bits {
3038 u8 reserved_0[0x18];
3042 u8 reserved_1[0xc0];
3044 struct mlx5_ifc_tirc_bits tir_context;
3047 struct mlx5_ifc_query_tir_in_bits {
3049 u8 reserved_0[0x10];
3051 u8 reserved_1[0x10];
3057 u8 reserved_3[0x20];
3060 struct mlx5_ifc_query_srq_out_bits {
3062 u8 reserved_0[0x18];
3066 u8 reserved_1[0x40];
3068 struct mlx5_ifc_srqc_bits srq_context_entry;
3070 u8 reserved_2[0x600];
3075 struct mlx5_ifc_query_srq_in_bits {
3077 u8 reserved_0[0x10];
3079 u8 reserved_1[0x10];
3085 u8 reserved_3[0x20];
3088 struct mlx5_ifc_query_sq_out_bits {
3090 u8 reserved_0[0x18];
3094 u8 reserved_1[0xc0];
3096 struct mlx5_ifc_sqc_bits sq_context;
3099 struct mlx5_ifc_query_sq_in_bits {
3101 u8 reserved_0[0x10];
3103 u8 reserved_1[0x10];
3109 u8 reserved_3[0x20];
3112 struct mlx5_ifc_query_special_contexts_out_bits {
3114 u8 reserved_0[0x18];
3118 u8 reserved_1[0x20];
3123 struct mlx5_ifc_query_special_contexts_in_bits {
3125 u8 reserved_0[0x10];
3127 u8 reserved_1[0x10];
3130 u8 reserved_2[0x40];
3133 struct mlx5_ifc_query_rqt_out_bits {
3135 u8 reserved_0[0x18];
3139 u8 reserved_1[0xc0];
3141 struct mlx5_ifc_rqtc_bits rqt_context;
3144 struct mlx5_ifc_query_rqt_in_bits {
3146 u8 reserved_0[0x10];
3148 u8 reserved_1[0x10];
3154 u8 reserved_3[0x20];
3157 struct mlx5_ifc_query_rq_out_bits {
3159 u8 reserved_0[0x18];
3163 u8 reserved_1[0xc0];
3165 struct mlx5_ifc_rqc_bits rq_context;
3168 struct mlx5_ifc_query_rq_in_bits {
3170 u8 reserved_0[0x10];
3172 u8 reserved_1[0x10];
3178 u8 reserved_3[0x20];
3181 struct mlx5_ifc_query_roce_address_out_bits {
3183 u8 reserved_0[0x18];
3187 u8 reserved_1[0x40];
3189 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3192 struct mlx5_ifc_query_roce_address_in_bits {
3194 u8 reserved_0[0x10];
3196 u8 reserved_1[0x10];
3199 u8 roce_address_index[0x10];
3200 u8 reserved_2[0x10];
3202 u8 reserved_3[0x20];
3205 struct mlx5_ifc_query_rmp_out_bits {
3207 u8 reserved_0[0x18];
3211 u8 reserved_1[0xc0];
3213 struct mlx5_ifc_rmpc_bits rmp_context;
3216 struct mlx5_ifc_query_rmp_in_bits {
3218 u8 reserved_0[0x10];
3220 u8 reserved_1[0x10];
3226 u8 reserved_3[0x20];
3229 struct mlx5_ifc_query_qp_out_bits {
3231 u8 reserved_0[0x18];
3235 u8 reserved_1[0x40];
3237 u8 opt_param_mask[0x20];
3239 u8 reserved_2[0x20];
3241 struct mlx5_ifc_qpc_bits qpc;
3243 u8 reserved_3[0x80];
3248 struct mlx5_ifc_query_qp_in_bits {
3250 u8 reserved_0[0x10];
3252 u8 reserved_1[0x10];
3258 u8 reserved_3[0x20];
3261 struct mlx5_ifc_query_q_counter_out_bits {
3263 u8 reserved_0[0x18];
3267 u8 reserved_1[0x40];
3269 u8 rx_write_requests[0x20];
3271 u8 reserved_2[0x20];
3273 u8 rx_read_requests[0x20];
3275 u8 reserved_3[0x20];
3277 u8 rx_atomic_requests[0x20];
3279 u8 reserved_4[0x20];
3281 u8 rx_dct_connect[0x20];
3283 u8 reserved_5[0x20];
3285 u8 out_of_buffer[0x20];
3287 u8 reserved_6[0x20];
3289 u8 out_of_sequence[0x20];
3291 u8 reserved_7[0x620];
3294 struct mlx5_ifc_query_q_counter_in_bits {
3296 u8 reserved_0[0x10];
3298 u8 reserved_1[0x10];
3301 u8 reserved_2[0x80];
3304 u8 reserved_3[0x1f];
3306 u8 reserved_4[0x18];
3307 u8 counter_set_id[0x8];
3310 struct mlx5_ifc_query_pages_out_bits {
3312 u8 reserved_0[0x18];
3316 u8 reserved_1[0x10];
3317 u8 function_id[0x10];
3323 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3324 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3325 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3328 struct mlx5_ifc_query_pages_in_bits {
3330 u8 reserved_0[0x10];
3332 u8 reserved_1[0x10];
3335 u8 reserved_2[0x10];
3336 u8 function_id[0x10];
3338 u8 reserved_3[0x20];
3341 struct mlx5_ifc_query_nic_vport_context_out_bits {
3343 u8 reserved_0[0x18];
3347 u8 reserved_1[0x40];
3349 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3352 struct mlx5_ifc_query_nic_vport_context_in_bits {
3354 u8 reserved_0[0x10];
3356 u8 reserved_1[0x10];
3359 u8 other_vport[0x1];
3361 u8 vport_number[0x10];
3364 u8 allowed_list_type[0x3];
3365 u8 reserved_4[0x18];
3368 struct mlx5_ifc_query_mkey_out_bits {
3370 u8 reserved_0[0x18];
3374 u8 reserved_1[0x40];
3376 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3378 u8 reserved_2[0x600];
3380 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3382 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3385 struct mlx5_ifc_query_mkey_in_bits {
3387 u8 reserved_0[0x10];
3389 u8 reserved_1[0x10];
3393 u8 mkey_index[0x18];
3396 u8 reserved_3[0x1f];
3399 struct mlx5_ifc_query_mad_demux_out_bits {
3401 u8 reserved_0[0x18];
3405 u8 reserved_1[0x40];
3407 u8 mad_dumux_parameters_block[0x20];
3410 struct mlx5_ifc_query_mad_demux_in_bits {
3412 u8 reserved_0[0x10];
3414 u8 reserved_1[0x10];
3417 u8 reserved_2[0x40];
3420 struct mlx5_ifc_query_l2_table_entry_out_bits {
3422 u8 reserved_0[0x18];
3426 u8 reserved_1[0xa0];
3428 u8 reserved_2[0x13];
3432 struct mlx5_ifc_mac_address_layout_bits mac_address;
3434 u8 reserved_3[0xc0];
3437 struct mlx5_ifc_query_l2_table_entry_in_bits {
3439 u8 reserved_0[0x10];
3441 u8 reserved_1[0x10];
3444 u8 reserved_2[0x60];
3447 u8 table_index[0x18];
3449 u8 reserved_4[0x140];
3452 struct mlx5_ifc_query_issi_out_bits {
3454 u8 reserved_0[0x18];
3458 u8 reserved_1[0x10];
3459 u8 current_issi[0x10];
3461 u8 reserved_2[0xa0];
3463 u8 supported_issi_reserved[76][0x8];
3464 u8 supported_issi_dw0[0x20];
3467 struct mlx5_ifc_query_issi_in_bits {
3469 u8 reserved_0[0x10];
3471 u8 reserved_1[0x10];
3474 u8 reserved_2[0x40];
3477 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3479 u8 reserved_0[0x18];
3483 u8 reserved_1[0x40];
3485 struct mlx5_ifc_pkey_bits pkey[0];
3488 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3490 u8 reserved_0[0x10];
3492 u8 reserved_1[0x10];
3495 u8 other_vport[0x1];
3497 u8 vport_number[0x10];
3499 u8 reserved_3[0x10];
3500 u8 pkey_index[0x10];
3503 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3505 u8 reserved_0[0x18];
3509 u8 reserved_1[0x20];
3512 u8 reserved_2[0x10];
3514 struct mlx5_ifc_array128_auto_bits gid[0];
3517 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3519 u8 reserved_0[0x10];
3521 u8 reserved_1[0x10];
3524 u8 other_vport[0x1];
3526 u8 vport_number[0x10];
3528 u8 reserved_3[0x10];
3532 struct mlx5_ifc_query_hca_vport_context_out_bits {
3534 u8 reserved_0[0x18];
3538 u8 reserved_1[0x40];
3540 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3543 struct mlx5_ifc_query_hca_vport_context_in_bits {
3545 u8 reserved_0[0x10];
3547 u8 reserved_1[0x10];
3550 u8 other_vport[0x1];
3552 u8 vport_number[0x10];
3554 u8 reserved_3[0x20];
3557 struct mlx5_ifc_query_hca_cap_out_bits {
3559 u8 reserved_0[0x18];
3563 u8 reserved_1[0x40];
3565 union mlx5_ifc_hca_cap_union_bits capability;
3568 struct mlx5_ifc_query_hca_cap_in_bits {
3570 u8 reserved_0[0x10];
3572 u8 reserved_1[0x10];
3575 u8 reserved_2[0x40];
3578 struct mlx5_ifc_query_flow_table_out_bits {
3580 u8 reserved_0[0x18];
3584 u8 reserved_1[0x80];
3591 u8 reserved_4[0x120];
3594 struct mlx5_ifc_query_flow_table_in_bits {
3596 u8 reserved_0[0x10];
3598 u8 reserved_1[0x10];
3601 u8 reserved_2[0x40];
3604 u8 reserved_3[0x18];
3609 u8 reserved_5[0x140];
3612 struct mlx5_ifc_query_fte_out_bits {
3614 u8 reserved_0[0x18];
3618 u8 reserved_1[0x1c0];
3620 struct mlx5_ifc_flow_context_bits flow_context;
3623 struct mlx5_ifc_query_fte_in_bits {
3625 u8 reserved_0[0x10];
3627 u8 reserved_1[0x10];
3630 u8 reserved_2[0x40];
3633 u8 reserved_3[0x18];
3638 u8 reserved_5[0x40];
3640 u8 flow_index[0x20];
3642 u8 reserved_6[0xe0];
3646 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3647 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3648 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3651 struct mlx5_ifc_query_flow_group_out_bits {
3653 u8 reserved_0[0x18];
3657 u8 reserved_1[0xa0];
3659 u8 start_flow_index[0x20];
3661 u8 reserved_2[0x20];
3663 u8 end_flow_index[0x20];
3665 u8 reserved_3[0xa0];
3667 u8 reserved_4[0x18];
3668 u8 match_criteria_enable[0x8];
3670 struct mlx5_ifc_fte_match_param_bits match_criteria;
3672 u8 reserved_5[0xe00];
3675 struct mlx5_ifc_query_flow_group_in_bits {
3677 u8 reserved_0[0x10];
3679 u8 reserved_1[0x10];
3682 u8 reserved_2[0x40];
3685 u8 reserved_3[0x18];
3692 u8 reserved_5[0x120];
3695 struct mlx5_ifc_query_eq_out_bits {
3697 u8 reserved_0[0x18];
3701 u8 reserved_1[0x40];
3703 struct mlx5_ifc_eqc_bits eq_context_entry;
3705 u8 reserved_2[0x40];
3707 u8 event_bitmask[0x40];
3709 u8 reserved_3[0x580];
3714 struct mlx5_ifc_query_eq_in_bits {
3716 u8 reserved_0[0x10];
3718 u8 reserved_1[0x10];
3721 u8 reserved_2[0x18];
3724 u8 reserved_3[0x20];
3727 struct mlx5_ifc_query_dct_out_bits {
3729 u8 reserved_0[0x18];
3733 u8 reserved_1[0x40];
3735 struct mlx5_ifc_dctc_bits dct_context_entry;
3737 u8 reserved_2[0x180];
3740 struct mlx5_ifc_query_dct_in_bits {
3742 u8 reserved_0[0x10];
3744 u8 reserved_1[0x10];
3750 u8 reserved_3[0x20];
3753 struct mlx5_ifc_query_cq_out_bits {
3755 u8 reserved_0[0x18];
3759 u8 reserved_1[0x40];
3761 struct mlx5_ifc_cqc_bits cq_context;
3763 u8 reserved_2[0x600];
3768 struct mlx5_ifc_query_cq_in_bits {
3770 u8 reserved_0[0x10];
3772 u8 reserved_1[0x10];
3778 u8 reserved_3[0x20];
3781 struct mlx5_ifc_query_cong_status_out_bits {
3783 u8 reserved_0[0x18];
3787 u8 reserved_1[0x20];
3791 u8 reserved_2[0x1e];
3794 struct mlx5_ifc_query_cong_status_in_bits {
3796 u8 reserved_0[0x10];
3798 u8 reserved_1[0x10];
3801 u8 reserved_2[0x18];
3803 u8 cong_protocol[0x4];
3805 u8 reserved_3[0x20];
3808 struct mlx5_ifc_query_cong_statistics_out_bits {
3810 u8 reserved_0[0x18];
3814 u8 reserved_1[0x40];
3820 u8 cnp_ignored_high[0x20];
3822 u8 cnp_ignored_low[0x20];
3824 u8 cnp_handled_high[0x20];
3826 u8 cnp_handled_low[0x20];
3828 u8 reserved_2[0x100];
3830 u8 time_stamp_high[0x20];
3832 u8 time_stamp_low[0x20];
3834 u8 accumulators_period[0x20];
3836 u8 ecn_marked_roce_packets_high[0x20];
3838 u8 ecn_marked_roce_packets_low[0x20];
3840 u8 cnps_sent_high[0x20];
3842 u8 cnps_sent_low[0x20];
3844 u8 reserved_3[0x560];
3847 struct mlx5_ifc_query_cong_statistics_in_bits {
3849 u8 reserved_0[0x10];
3851 u8 reserved_1[0x10];
3855 u8 reserved_2[0x1f];
3857 u8 reserved_3[0x20];
3860 struct mlx5_ifc_query_cong_params_out_bits {
3862 u8 reserved_0[0x18];
3866 u8 reserved_1[0x40];
3868 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
3871 struct mlx5_ifc_query_cong_params_in_bits {
3873 u8 reserved_0[0x10];
3875 u8 reserved_1[0x10];
3878 u8 reserved_2[0x1c];
3879 u8 cong_protocol[0x4];
3881 u8 reserved_3[0x20];
3884 struct mlx5_ifc_query_adapter_out_bits {
3886 u8 reserved_0[0x18];
3890 u8 reserved_1[0x40];
3892 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
3895 struct mlx5_ifc_query_adapter_in_bits {
3897 u8 reserved_0[0x10];
3899 u8 reserved_1[0x10];
3902 u8 reserved_2[0x40];
3905 struct mlx5_ifc_qp_2rst_out_bits {
3907 u8 reserved_0[0x18];
3911 u8 reserved_1[0x40];
3914 struct mlx5_ifc_qp_2rst_in_bits {
3916 u8 reserved_0[0x10];
3918 u8 reserved_1[0x10];
3924 u8 reserved_3[0x20];
3927 struct mlx5_ifc_qp_2err_out_bits {
3929 u8 reserved_0[0x18];
3933 u8 reserved_1[0x40];
3936 struct mlx5_ifc_qp_2err_in_bits {
3938 u8 reserved_0[0x10];
3940 u8 reserved_1[0x10];
3946 u8 reserved_3[0x20];
3949 struct mlx5_ifc_page_fault_resume_out_bits {
3951 u8 reserved_0[0x18];
3955 u8 reserved_1[0x40];
3958 struct mlx5_ifc_page_fault_resume_in_bits {
3960 u8 reserved_0[0x10];
3962 u8 reserved_1[0x10];
3972 u8 reserved_3[0x20];
3975 struct mlx5_ifc_nop_out_bits {
3977 u8 reserved_0[0x18];
3981 u8 reserved_1[0x40];
3984 struct mlx5_ifc_nop_in_bits {
3986 u8 reserved_0[0x10];
3988 u8 reserved_1[0x10];
3991 u8 reserved_2[0x40];
3994 struct mlx5_ifc_modify_vport_state_out_bits {
3996 u8 reserved_0[0x18];
4000 u8 reserved_1[0x40];
4003 struct mlx5_ifc_modify_vport_state_in_bits {
4005 u8 reserved_0[0x10];
4007 u8 reserved_1[0x10];
4010 u8 other_vport[0x1];
4012 u8 vport_number[0x10];
4014 u8 reserved_3[0x18];
4015 u8 admin_state[0x4];
4019 struct mlx5_ifc_modify_tis_out_bits {
4021 u8 reserved_0[0x18];
4025 u8 reserved_1[0x40];
4028 struct mlx5_ifc_modify_tis_in_bits {
4030 u8 reserved_0[0x10];
4032 u8 reserved_1[0x10];
4038 u8 reserved_3[0x20];
4040 u8 modify_bitmask[0x40];
4042 u8 reserved_4[0x40];
4044 struct mlx5_ifc_tisc_bits ctx;
4047 struct mlx5_ifc_modify_tir_out_bits {
4049 u8 reserved_0[0x18];
4053 u8 reserved_1[0x40];
4056 struct mlx5_ifc_modify_tir_in_bits {
4058 u8 reserved_0[0x10];
4060 u8 reserved_1[0x10];
4066 u8 reserved_3[0x20];
4068 u8 modify_bitmask[0x40];
4070 u8 reserved_4[0x40];
4072 struct mlx5_ifc_tirc_bits ctx;
4075 struct mlx5_ifc_modify_sq_out_bits {
4077 u8 reserved_0[0x18];
4081 u8 reserved_1[0x40];
4084 struct mlx5_ifc_modify_sq_in_bits {
4086 u8 reserved_0[0x10];
4088 u8 reserved_1[0x10];
4095 u8 reserved_3[0x20];
4097 u8 modify_bitmask[0x40];
4099 u8 reserved_4[0x40];
4101 struct mlx5_ifc_sqc_bits ctx;
4104 struct mlx5_ifc_modify_rqt_out_bits {
4106 u8 reserved_0[0x18];
4110 u8 reserved_1[0x40];
4113 struct mlx5_ifc_modify_rqt_in_bits {
4115 u8 reserved_0[0x10];
4117 u8 reserved_1[0x10];
4123 u8 reserved_3[0x20];
4125 u8 modify_bitmask[0x40];
4127 u8 reserved_4[0x40];
4129 struct mlx5_ifc_rqtc_bits ctx;
4132 struct mlx5_ifc_modify_rq_out_bits {
4134 u8 reserved_0[0x18];
4138 u8 reserved_1[0x40];
4141 struct mlx5_ifc_modify_rq_in_bits {
4143 u8 reserved_0[0x10];
4145 u8 reserved_1[0x10];
4152 u8 reserved_3[0x20];
4154 u8 modify_bitmask[0x40];
4156 u8 reserved_4[0x40];
4158 struct mlx5_ifc_rqc_bits ctx;
4161 struct mlx5_ifc_modify_rmp_out_bits {
4163 u8 reserved_0[0x18];
4167 u8 reserved_1[0x40];
4170 struct mlx5_ifc_modify_rmp_in_bits {
4172 u8 reserved_0[0x10];
4174 u8 reserved_1[0x10];
4181 u8 reserved_3[0x20];
4183 u8 modify_bitmask[0x40];
4185 u8 reserved_4[0x40];
4187 struct mlx5_ifc_rmpc_bits ctx;
4190 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4192 u8 reserved_0[0x18];
4196 u8 reserved_1[0x40];
4199 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4200 u8 reserved_0[0x1c];
4201 u8 permanent_address[0x1];
4202 u8 addresses_list[0x1];
4207 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4209 u8 reserved_0[0x10];
4211 u8 reserved_1[0x10];
4214 u8 other_vport[0x1];
4216 u8 vport_number[0x10];
4218 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4220 u8 reserved_3[0x780];
4222 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4225 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4227 u8 reserved_0[0x18];
4231 u8 reserved_1[0x40];
4234 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4236 u8 reserved_0[0x10];
4238 u8 reserved_1[0x10];
4241 u8 other_vport[0x1];
4243 u8 vport_number[0x10];
4245 u8 reserved_3[0x20];
4247 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4250 struct mlx5_ifc_modify_cq_out_bits {
4252 u8 reserved_0[0x18];
4256 u8 reserved_1[0x40];
4260 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4261 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4264 struct mlx5_ifc_modify_cq_in_bits {
4266 u8 reserved_0[0x10];
4268 u8 reserved_1[0x10];
4274 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4276 struct mlx5_ifc_cqc_bits cq_context;
4278 u8 reserved_3[0x600];
4283 struct mlx5_ifc_modify_cong_status_out_bits {
4285 u8 reserved_0[0x18];
4289 u8 reserved_1[0x40];
4292 struct mlx5_ifc_modify_cong_status_in_bits {
4294 u8 reserved_0[0x10];
4296 u8 reserved_1[0x10];
4299 u8 reserved_2[0x18];
4301 u8 cong_protocol[0x4];
4305 u8 reserved_3[0x1e];
4308 struct mlx5_ifc_modify_cong_params_out_bits {
4310 u8 reserved_0[0x18];
4314 u8 reserved_1[0x40];
4317 struct mlx5_ifc_modify_cong_params_in_bits {
4319 u8 reserved_0[0x10];
4321 u8 reserved_1[0x10];
4324 u8 reserved_2[0x1c];
4325 u8 cong_protocol[0x4];
4327 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4329 u8 reserved_3[0x80];
4331 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4334 struct mlx5_ifc_manage_pages_out_bits {
4336 u8 reserved_0[0x18];
4340 u8 output_num_entries[0x20];
4342 u8 reserved_1[0x20];
4348 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4349 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4350 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4353 struct mlx5_ifc_manage_pages_in_bits {
4355 u8 reserved_0[0x10];
4357 u8 reserved_1[0x10];
4360 u8 reserved_2[0x10];
4361 u8 function_id[0x10];
4363 u8 input_num_entries[0x20];
4368 struct mlx5_ifc_mad_ifc_out_bits {
4370 u8 reserved_0[0x18];
4374 u8 reserved_1[0x40];
4376 u8 response_mad_packet[256][0x8];
4379 struct mlx5_ifc_mad_ifc_in_bits {
4381 u8 reserved_0[0x10];
4383 u8 reserved_1[0x10];
4386 u8 remote_lid[0x10];
4390 u8 reserved_3[0x20];
4395 struct mlx5_ifc_init_hca_out_bits {
4397 u8 reserved_0[0x18];
4401 u8 reserved_1[0x40];
4404 struct mlx5_ifc_init_hca_in_bits {
4406 u8 reserved_0[0x10];
4408 u8 reserved_1[0x10];
4411 u8 reserved_2[0x40];
4414 struct mlx5_ifc_init2rtr_qp_out_bits {
4416 u8 reserved_0[0x18];
4420 u8 reserved_1[0x40];
4423 struct mlx5_ifc_init2rtr_qp_in_bits {
4425 u8 reserved_0[0x10];
4427 u8 reserved_1[0x10];
4433 u8 reserved_3[0x20];
4435 u8 opt_param_mask[0x20];
4437 u8 reserved_4[0x20];
4439 struct mlx5_ifc_qpc_bits qpc;
4441 u8 reserved_5[0x80];
4444 struct mlx5_ifc_init2init_qp_out_bits {
4446 u8 reserved_0[0x18];
4450 u8 reserved_1[0x40];
4453 struct mlx5_ifc_init2init_qp_in_bits {
4455 u8 reserved_0[0x10];
4457 u8 reserved_1[0x10];
4463 u8 reserved_3[0x20];
4465 u8 opt_param_mask[0x20];
4467 u8 reserved_4[0x20];
4469 struct mlx5_ifc_qpc_bits qpc;
4471 u8 reserved_5[0x80];
4474 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4476 u8 reserved_0[0x18];
4480 u8 reserved_1[0x40];
4482 u8 packet_headers_log[128][0x8];
4484 u8 packet_syndrome[64][0x8];
4487 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4489 u8 reserved_0[0x10];
4491 u8 reserved_1[0x10];
4494 u8 reserved_2[0x40];
4497 struct mlx5_ifc_gen_eqe_in_bits {
4499 u8 reserved_0[0x10];
4501 u8 reserved_1[0x10];
4504 u8 reserved_2[0x18];
4507 u8 reserved_3[0x20];
4512 struct mlx5_ifc_gen_eq_out_bits {
4514 u8 reserved_0[0x18];
4518 u8 reserved_1[0x40];
4521 struct mlx5_ifc_enable_hca_out_bits {
4523 u8 reserved_0[0x18];
4527 u8 reserved_1[0x20];
4530 struct mlx5_ifc_enable_hca_in_bits {
4532 u8 reserved_0[0x10];
4534 u8 reserved_1[0x10];
4537 u8 reserved_2[0x10];
4538 u8 function_id[0x10];
4540 u8 reserved_3[0x20];
4543 struct mlx5_ifc_drain_dct_out_bits {
4545 u8 reserved_0[0x18];
4549 u8 reserved_1[0x40];
4552 struct mlx5_ifc_drain_dct_in_bits {
4554 u8 reserved_0[0x10];
4556 u8 reserved_1[0x10];
4562 u8 reserved_3[0x20];
4565 struct mlx5_ifc_disable_hca_out_bits {
4567 u8 reserved_0[0x18];
4571 u8 reserved_1[0x20];
4574 struct mlx5_ifc_disable_hca_in_bits {
4576 u8 reserved_0[0x10];
4578 u8 reserved_1[0x10];
4581 u8 reserved_2[0x10];
4582 u8 function_id[0x10];
4584 u8 reserved_3[0x20];
4587 struct mlx5_ifc_detach_from_mcg_out_bits {
4589 u8 reserved_0[0x18];
4593 u8 reserved_1[0x40];
4596 struct mlx5_ifc_detach_from_mcg_in_bits {
4598 u8 reserved_0[0x10];
4600 u8 reserved_1[0x10];
4606 u8 reserved_3[0x20];
4608 u8 multicast_gid[16][0x8];
4611 struct mlx5_ifc_destroy_xrc_srq_out_bits {
4613 u8 reserved_0[0x18];
4617 u8 reserved_1[0x40];
4620 struct mlx5_ifc_destroy_xrc_srq_in_bits {
4622 u8 reserved_0[0x10];
4624 u8 reserved_1[0x10];
4630 u8 reserved_3[0x20];
4633 struct mlx5_ifc_destroy_tis_out_bits {
4635 u8 reserved_0[0x18];
4639 u8 reserved_1[0x40];
4642 struct mlx5_ifc_destroy_tis_in_bits {
4644 u8 reserved_0[0x10];
4646 u8 reserved_1[0x10];
4652 u8 reserved_3[0x20];
4655 struct mlx5_ifc_destroy_tir_out_bits {
4657 u8 reserved_0[0x18];
4661 u8 reserved_1[0x40];
4664 struct mlx5_ifc_destroy_tir_in_bits {
4666 u8 reserved_0[0x10];
4668 u8 reserved_1[0x10];
4674 u8 reserved_3[0x20];
4677 struct mlx5_ifc_destroy_srq_out_bits {
4679 u8 reserved_0[0x18];
4683 u8 reserved_1[0x40];
4686 struct mlx5_ifc_destroy_srq_in_bits {
4688 u8 reserved_0[0x10];
4690 u8 reserved_1[0x10];
4696 u8 reserved_3[0x20];
4699 struct mlx5_ifc_destroy_sq_out_bits {
4701 u8 reserved_0[0x18];
4705 u8 reserved_1[0x40];
4708 struct mlx5_ifc_destroy_sq_in_bits {
4710 u8 reserved_0[0x10];
4712 u8 reserved_1[0x10];
4718 u8 reserved_3[0x20];
4721 struct mlx5_ifc_destroy_rqt_out_bits {
4723 u8 reserved_0[0x18];
4727 u8 reserved_1[0x40];
4730 struct mlx5_ifc_destroy_rqt_in_bits {
4732 u8 reserved_0[0x10];
4734 u8 reserved_1[0x10];
4740 u8 reserved_3[0x20];
4743 struct mlx5_ifc_destroy_rq_out_bits {
4745 u8 reserved_0[0x18];
4749 u8 reserved_1[0x40];
4752 struct mlx5_ifc_destroy_rq_in_bits {
4754 u8 reserved_0[0x10];
4756 u8 reserved_1[0x10];
4762 u8 reserved_3[0x20];
4765 struct mlx5_ifc_destroy_rmp_out_bits {
4767 u8 reserved_0[0x18];
4771 u8 reserved_1[0x40];
4774 struct mlx5_ifc_destroy_rmp_in_bits {
4776 u8 reserved_0[0x10];
4778 u8 reserved_1[0x10];
4784 u8 reserved_3[0x20];
4787 struct mlx5_ifc_destroy_qp_out_bits {
4789 u8 reserved_0[0x18];
4793 u8 reserved_1[0x40];
4796 struct mlx5_ifc_destroy_qp_in_bits {
4798 u8 reserved_0[0x10];
4800 u8 reserved_1[0x10];
4806 u8 reserved_3[0x20];
4809 struct mlx5_ifc_destroy_psv_out_bits {
4811 u8 reserved_0[0x18];
4815 u8 reserved_1[0x40];
4818 struct mlx5_ifc_destroy_psv_in_bits {
4820 u8 reserved_0[0x10];
4822 u8 reserved_1[0x10];
4828 u8 reserved_3[0x20];
4831 struct mlx5_ifc_destroy_mkey_out_bits {
4833 u8 reserved_0[0x18];
4837 u8 reserved_1[0x40];
4840 struct mlx5_ifc_destroy_mkey_in_bits {
4842 u8 reserved_0[0x10];
4844 u8 reserved_1[0x10];
4848 u8 mkey_index[0x18];
4850 u8 reserved_3[0x20];
4853 struct mlx5_ifc_destroy_flow_table_out_bits {
4855 u8 reserved_0[0x18];
4859 u8 reserved_1[0x40];
4862 struct mlx5_ifc_destroy_flow_table_in_bits {
4864 u8 reserved_0[0x10];
4866 u8 reserved_1[0x10];
4869 u8 reserved_2[0x40];
4872 u8 reserved_3[0x18];
4877 u8 reserved_5[0x140];
4880 struct mlx5_ifc_destroy_flow_group_out_bits {
4882 u8 reserved_0[0x18];
4886 u8 reserved_1[0x40];
4889 struct mlx5_ifc_destroy_flow_group_in_bits {
4891 u8 reserved_0[0x10];
4893 u8 reserved_1[0x10];
4896 u8 reserved_2[0x40];
4899 u8 reserved_3[0x18];
4906 u8 reserved_5[0x120];
4909 struct mlx5_ifc_destroy_eq_out_bits {
4911 u8 reserved_0[0x18];
4915 u8 reserved_1[0x40];
4918 struct mlx5_ifc_destroy_eq_in_bits {
4920 u8 reserved_0[0x10];
4922 u8 reserved_1[0x10];
4925 u8 reserved_2[0x18];
4928 u8 reserved_3[0x20];
4931 struct mlx5_ifc_destroy_dct_out_bits {
4933 u8 reserved_0[0x18];
4937 u8 reserved_1[0x40];
4940 struct mlx5_ifc_destroy_dct_in_bits {
4942 u8 reserved_0[0x10];
4944 u8 reserved_1[0x10];
4950 u8 reserved_3[0x20];
4953 struct mlx5_ifc_destroy_cq_out_bits {
4955 u8 reserved_0[0x18];
4959 u8 reserved_1[0x40];
4962 struct mlx5_ifc_destroy_cq_in_bits {
4964 u8 reserved_0[0x10];
4966 u8 reserved_1[0x10];
4972 u8 reserved_3[0x20];
4975 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
4977 u8 reserved_0[0x18];
4981 u8 reserved_1[0x40];
4984 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
4986 u8 reserved_0[0x10];
4988 u8 reserved_1[0x10];
4991 u8 reserved_2[0x20];
4993 u8 reserved_3[0x10];
4994 u8 vxlan_udp_port[0x10];
4997 struct mlx5_ifc_delete_l2_table_entry_out_bits {
4999 u8 reserved_0[0x18];
5003 u8 reserved_1[0x40];
5006 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5008 u8 reserved_0[0x10];
5010 u8 reserved_1[0x10];
5013 u8 reserved_2[0x60];
5016 u8 table_index[0x18];
5018 u8 reserved_4[0x140];
5021 struct mlx5_ifc_delete_fte_out_bits {
5023 u8 reserved_0[0x18];
5027 u8 reserved_1[0x40];
5030 struct mlx5_ifc_delete_fte_in_bits {
5032 u8 reserved_0[0x10];
5034 u8 reserved_1[0x10];
5037 u8 reserved_2[0x40];
5040 u8 reserved_3[0x18];
5045 u8 reserved_5[0x40];
5047 u8 flow_index[0x20];
5049 u8 reserved_6[0xe0];
5052 struct mlx5_ifc_dealloc_xrcd_out_bits {
5054 u8 reserved_0[0x18];
5058 u8 reserved_1[0x40];
5061 struct mlx5_ifc_dealloc_xrcd_in_bits {
5063 u8 reserved_0[0x10];
5065 u8 reserved_1[0x10];
5071 u8 reserved_3[0x20];
5074 struct mlx5_ifc_dealloc_uar_out_bits {
5076 u8 reserved_0[0x18];
5080 u8 reserved_1[0x40];
5083 struct mlx5_ifc_dealloc_uar_in_bits {
5085 u8 reserved_0[0x10];
5087 u8 reserved_1[0x10];
5093 u8 reserved_3[0x20];
5096 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5098 u8 reserved_0[0x18];
5102 u8 reserved_1[0x40];
5105 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5107 u8 reserved_0[0x10];
5109 u8 reserved_1[0x10];
5113 u8 transport_domain[0x18];
5115 u8 reserved_3[0x20];
5118 struct mlx5_ifc_dealloc_q_counter_out_bits {
5120 u8 reserved_0[0x18];
5124 u8 reserved_1[0x40];
5127 struct mlx5_ifc_dealloc_q_counter_in_bits {
5129 u8 reserved_0[0x10];
5131 u8 reserved_1[0x10];
5134 u8 reserved_2[0x18];
5135 u8 counter_set_id[0x8];
5137 u8 reserved_3[0x20];
5140 struct mlx5_ifc_dealloc_pd_out_bits {
5142 u8 reserved_0[0x18];
5146 u8 reserved_1[0x40];
5149 struct mlx5_ifc_dealloc_pd_in_bits {
5151 u8 reserved_0[0x10];
5153 u8 reserved_1[0x10];
5159 u8 reserved_3[0x20];
5162 struct mlx5_ifc_create_xrc_srq_out_bits {
5164 u8 reserved_0[0x18];
5171 u8 reserved_2[0x20];
5174 struct mlx5_ifc_create_xrc_srq_in_bits {
5176 u8 reserved_0[0x10];
5178 u8 reserved_1[0x10];
5181 u8 reserved_2[0x40];
5183 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5185 u8 reserved_3[0x600];
5190 struct mlx5_ifc_create_tis_out_bits {
5192 u8 reserved_0[0x18];
5199 u8 reserved_2[0x20];
5202 struct mlx5_ifc_create_tis_in_bits {
5204 u8 reserved_0[0x10];
5206 u8 reserved_1[0x10];
5209 u8 reserved_2[0xc0];
5211 struct mlx5_ifc_tisc_bits ctx;
5214 struct mlx5_ifc_create_tir_out_bits {
5216 u8 reserved_0[0x18];
5223 u8 reserved_2[0x20];
5226 struct mlx5_ifc_create_tir_in_bits {
5228 u8 reserved_0[0x10];
5230 u8 reserved_1[0x10];
5233 u8 reserved_2[0xc0];
5235 struct mlx5_ifc_tirc_bits ctx;
5238 struct mlx5_ifc_create_srq_out_bits {
5240 u8 reserved_0[0x18];
5247 u8 reserved_2[0x20];
5250 struct mlx5_ifc_create_srq_in_bits {
5252 u8 reserved_0[0x10];
5254 u8 reserved_1[0x10];
5257 u8 reserved_2[0x40];
5259 struct mlx5_ifc_srqc_bits srq_context_entry;
5261 u8 reserved_3[0x600];
5266 struct mlx5_ifc_create_sq_out_bits {
5268 u8 reserved_0[0x18];
5275 u8 reserved_2[0x20];
5278 struct mlx5_ifc_create_sq_in_bits {
5280 u8 reserved_0[0x10];
5282 u8 reserved_1[0x10];
5285 u8 reserved_2[0xc0];
5287 struct mlx5_ifc_sqc_bits ctx;
5290 struct mlx5_ifc_create_rqt_out_bits {
5292 u8 reserved_0[0x18];
5299 u8 reserved_2[0x20];
5302 struct mlx5_ifc_create_rqt_in_bits {
5304 u8 reserved_0[0x10];
5306 u8 reserved_1[0x10];
5309 u8 reserved_2[0xc0];
5311 struct mlx5_ifc_rqtc_bits rqt_context;
5314 struct mlx5_ifc_create_rq_out_bits {
5316 u8 reserved_0[0x18];
5323 u8 reserved_2[0x20];
5326 struct mlx5_ifc_create_rq_in_bits {
5328 u8 reserved_0[0x10];
5330 u8 reserved_1[0x10];
5333 u8 reserved_2[0xc0];
5335 struct mlx5_ifc_rqc_bits ctx;
5338 struct mlx5_ifc_create_rmp_out_bits {
5340 u8 reserved_0[0x18];
5347 u8 reserved_2[0x20];
5350 struct mlx5_ifc_create_rmp_in_bits {
5352 u8 reserved_0[0x10];
5354 u8 reserved_1[0x10];
5357 u8 reserved_2[0xc0];
5359 struct mlx5_ifc_rmpc_bits ctx;
5362 struct mlx5_ifc_create_qp_out_bits {
5364 u8 reserved_0[0x18];
5371 u8 reserved_2[0x20];
5374 struct mlx5_ifc_create_qp_in_bits {
5376 u8 reserved_0[0x10];
5378 u8 reserved_1[0x10];
5381 u8 reserved_2[0x40];
5383 u8 opt_param_mask[0x20];
5385 u8 reserved_3[0x20];
5387 struct mlx5_ifc_qpc_bits qpc;
5389 u8 reserved_4[0x80];
5394 struct mlx5_ifc_create_psv_out_bits {
5396 u8 reserved_0[0x18];
5400 u8 reserved_1[0x40];
5403 u8 psv0_index[0x18];
5406 u8 psv1_index[0x18];
5409 u8 psv2_index[0x18];
5412 u8 psv3_index[0x18];
5415 struct mlx5_ifc_create_psv_in_bits {
5417 u8 reserved_0[0x10];
5419 u8 reserved_1[0x10];
5426 u8 reserved_3[0x20];
5429 struct mlx5_ifc_create_mkey_out_bits {
5431 u8 reserved_0[0x18];
5436 u8 mkey_index[0x18];
5438 u8 reserved_2[0x20];
5441 struct mlx5_ifc_create_mkey_in_bits {
5443 u8 reserved_0[0x10];
5445 u8 reserved_1[0x10];
5448 u8 reserved_2[0x20];
5451 u8 reserved_3[0x1f];
5453 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5455 u8 reserved_4[0x80];
5457 u8 translations_octword_actual_size[0x20];
5459 u8 reserved_5[0x560];
5461 u8 klm_pas_mtt[0][0x20];
5464 struct mlx5_ifc_create_flow_table_out_bits {
5466 u8 reserved_0[0x18];
5473 u8 reserved_2[0x20];
5476 struct mlx5_ifc_create_flow_table_in_bits {
5478 u8 reserved_0[0x10];
5480 u8 reserved_1[0x10];
5483 u8 reserved_2[0x40];
5486 u8 reserved_3[0x18];
5488 u8 reserved_4[0x20];
5495 u8 reserved_7[0x120];
5498 struct mlx5_ifc_create_flow_group_out_bits {
5500 u8 reserved_0[0x18];
5507 u8 reserved_2[0x20];
5511 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5512 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5513 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5516 struct mlx5_ifc_create_flow_group_in_bits {
5518 u8 reserved_0[0x10];
5520 u8 reserved_1[0x10];
5523 u8 reserved_2[0x40];
5526 u8 reserved_3[0x18];
5531 u8 reserved_5[0x20];
5533 u8 start_flow_index[0x20];
5535 u8 reserved_6[0x20];
5537 u8 end_flow_index[0x20];
5539 u8 reserved_7[0xa0];
5541 u8 reserved_8[0x18];
5542 u8 match_criteria_enable[0x8];
5544 struct mlx5_ifc_fte_match_param_bits match_criteria;
5546 u8 reserved_9[0xe00];
5549 struct mlx5_ifc_create_eq_out_bits {
5551 u8 reserved_0[0x18];
5555 u8 reserved_1[0x18];
5558 u8 reserved_2[0x20];
5561 struct mlx5_ifc_create_eq_in_bits {
5563 u8 reserved_0[0x10];
5565 u8 reserved_1[0x10];
5568 u8 reserved_2[0x40];
5570 struct mlx5_ifc_eqc_bits eq_context_entry;
5572 u8 reserved_3[0x40];
5574 u8 event_bitmask[0x40];
5576 u8 reserved_4[0x580];
5581 struct mlx5_ifc_create_dct_out_bits {
5583 u8 reserved_0[0x18];
5590 u8 reserved_2[0x20];
5593 struct mlx5_ifc_create_dct_in_bits {
5595 u8 reserved_0[0x10];
5597 u8 reserved_1[0x10];
5600 u8 reserved_2[0x40];
5602 struct mlx5_ifc_dctc_bits dct_context_entry;
5604 u8 reserved_3[0x180];
5607 struct mlx5_ifc_create_cq_out_bits {
5609 u8 reserved_0[0x18];
5616 u8 reserved_2[0x20];
5619 struct mlx5_ifc_create_cq_in_bits {
5621 u8 reserved_0[0x10];
5623 u8 reserved_1[0x10];
5626 u8 reserved_2[0x40];
5628 struct mlx5_ifc_cqc_bits cq_context;
5630 u8 reserved_3[0x600];
5635 struct mlx5_ifc_config_int_moderation_out_bits {
5637 u8 reserved_0[0x18];
5643 u8 int_vector[0x10];
5645 u8 reserved_2[0x20];
5649 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
5650 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
5653 struct mlx5_ifc_config_int_moderation_in_bits {
5655 u8 reserved_0[0x10];
5657 u8 reserved_1[0x10];
5662 u8 int_vector[0x10];
5664 u8 reserved_3[0x20];
5667 struct mlx5_ifc_attach_to_mcg_out_bits {
5669 u8 reserved_0[0x18];
5673 u8 reserved_1[0x40];
5676 struct mlx5_ifc_attach_to_mcg_in_bits {
5678 u8 reserved_0[0x10];
5680 u8 reserved_1[0x10];
5686 u8 reserved_3[0x20];
5688 u8 multicast_gid[16][0x8];
5691 struct mlx5_ifc_arm_xrc_srq_out_bits {
5693 u8 reserved_0[0x18];
5697 u8 reserved_1[0x40];
5701 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
5704 struct mlx5_ifc_arm_xrc_srq_in_bits {
5706 u8 reserved_0[0x10];
5708 u8 reserved_1[0x10];
5714 u8 reserved_3[0x10];
5718 struct mlx5_ifc_arm_rq_out_bits {
5720 u8 reserved_0[0x18];
5724 u8 reserved_1[0x40];
5728 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
5731 struct mlx5_ifc_arm_rq_in_bits {
5733 u8 reserved_0[0x10];
5735 u8 reserved_1[0x10];
5739 u8 srq_number[0x18];
5741 u8 reserved_3[0x10];
5745 struct mlx5_ifc_arm_dct_out_bits {
5747 u8 reserved_0[0x18];
5751 u8 reserved_1[0x40];
5754 struct mlx5_ifc_arm_dct_in_bits {
5756 u8 reserved_0[0x10];
5758 u8 reserved_1[0x10];
5762 u8 dct_number[0x18];
5764 u8 reserved_3[0x20];
5767 struct mlx5_ifc_alloc_xrcd_out_bits {
5769 u8 reserved_0[0x18];
5776 u8 reserved_2[0x20];
5779 struct mlx5_ifc_alloc_xrcd_in_bits {
5781 u8 reserved_0[0x10];
5783 u8 reserved_1[0x10];
5786 u8 reserved_2[0x40];
5789 struct mlx5_ifc_alloc_uar_out_bits {
5791 u8 reserved_0[0x18];
5798 u8 reserved_2[0x20];
5801 struct mlx5_ifc_alloc_uar_in_bits {
5803 u8 reserved_0[0x10];
5805 u8 reserved_1[0x10];
5808 u8 reserved_2[0x40];
5811 struct mlx5_ifc_alloc_transport_domain_out_bits {
5813 u8 reserved_0[0x18];
5818 u8 transport_domain[0x18];
5820 u8 reserved_2[0x20];
5823 struct mlx5_ifc_alloc_transport_domain_in_bits {
5825 u8 reserved_0[0x10];
5827 u8 reserved_1[0x10];
5830 u8 reserved_2[0x40];
5833 struct mlx5_ifc_alloc_q_counter_out_bits {
5835 u8 reserved_0[0x18];
5839 u8 reserved_1[0x18];
5840 u8 counter_set_id[0x8];
5842 u8 reserved_2[0x20];
5845 struct mlx5_ifc_alloc_q_counter_in_bits {
5847 u8 reserved_0[0x10];
5849 u8 reserved_1[0x10];
5852 u8 reserved_2[0x40];
5855 struct mlx5_ifc_alloc_pd_out_bits {
5857 u8 reserved_0[0x18];
5864 u8 reserved_2[0x20];
5867 struct mlx5_ifc_alloc_pd_in_bits {
5869 u8 reserved_0[0x10];
5871 u8 reserved_1[0x10];
5874 u8 reserved_2[0x40];
5877 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
5879 u8 reserved_0[0x18];
5883 u8 reserved_1[0x40];
5886 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
5888 u8 reserved_0[0x10];
5890 u8 reserved_1[0x10];
5893 u8 reserved_2[0x20];
5895 u8 reserved_3[0x10];
5896 u8 vxlan_udp_port[0x10];
5899 struct mlx5_ifc_access_register_out_bits {
5901 u8 reserved_0[0x18];
5905 u8 reserved_1[0x40];
5907 u8 register_data[0][0x20];
5911 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
5912 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
5915 struct mlx5_ifc_access_register_in_bits {
5917 u8 reserved_0[0x10];
5919 u8 reserved_1[0x10];
5922 u8 reserved_2[0x10];
5923 u8 register_id[0x10];
5927 u8 register_data[0][0x20];
5930 struct mlx5_ifc_sltp_reg_bits {
5939 u8 reserved_2[0x20];
5948 u8 ob_preemp_mode[0x4];
5952 u8 reserved_5[0x20];
5955 struct mlx5_ifc_slrg_reg_bits {
5964 u8 time_to_link_up[0x10];
5966 u8 grade_lane_speed[0x4];
5968 u8 grade_version[0x8];
5972 u8 height_grade_type[0x4];
5973 u8 height_grade[0x18];
5978 u8 reserved_4[0x10];
5979 u8 height_sigma[0x10];
5981 u8 reserved_5[0x20];
5984 u8 phase_grade_type[0x4];
5985 u8 phase_grade[0x18];
5988 u8 phase_eo_pos[0x8];
5990 u8 phase_eo_neg[0x8];
5992 u8 ffe_set_tested[0x10];
5993 u8 test_errors_per_lane[0x10];
5996 struct mlx5_ifc_pvlc_reg_bits {
5999 u8 reserved_1[0x10];
6001 u8 reserved_2[0x1c];
6004 u8 reserved_3[0x1c];
6007 u8 reserved_4[0x1c];
6008 u8 vl_operational[0x4];
6011 struct mlx5_ifc_pude_reg_bits {
6015 u8 admin_status[0x4];
6017 u8 oper_status[0x4];
6019 u8 reserved_2[0x60];
6022 struct mlx5_ifc_ptys_reg_bits {
6028 u8 reserved_2[0x40];
6030 u8 eth_proto_capability[0x20];
6032 u8 ib_link_width_capability[0x10];
6033 u8 ib_proto_capability[0x10];
6035 u8 reserved_3[0x20];
6037 u8 eth_proto_admin[0x20];
6039 u8 ib_link_width_admin[0x10];
6040 u8 ib_proto_admin[0x10];
6042 u8 reserved_4[0x20];
6044 u8 eth_proto_oper[0x20];
6046 u8 ib_link_width_oper[0x10];
6047 u8 ib_proto_oper[0x10];
6049 u8 reserved_5[0x20];
6051 u8 eth_proto_lp_advertise[0x20];
6053 u8 reserved_6[0x60];
6056 struct mlx5_ifc_ptas_reg_bits {
6057 u8 reserved_0[0x20];
6059 u8 algorithm_options[0x10];
6061 u8 repetitions_mode[0x4];
6062 u8 num_of_repetitions[0x8];
6064 u8 grade_version[0x8];
6065 u8 height_grade_type[0x4];
6066 u8 phase_grade_type[0x4];
6067 u8 height_grade_weight[0x8];
6068 u8 phase_grade_weight[0x8];
6070 u8 gisim_measure_bits[0x10];
6071 u8 adaptive_tap_measure_bits[0x10];
6073 u8 ber_bath_high_error_threshold[0x10];
6074 u8 ber_bath_mid_error_threshold[0x10];
6076 u8 ber_bath_low_error_threshold[0x10];
6077 u8 one_ratio_high_threshold[0x10];
6079 u8 one_ratio_high_mid_threshold[0x10];
6080 u8 one_ratio_low_mid_threshold[0x10];
6082 u8 one_ratio_low_threshold[0x10];
6083 u8 ndeo_error_threshold[0x10];
6085 u8 mixer_offset_step_size[0x10];
6087 u8 mix90_phase_for_voltage_bath[0x8];
6089 u8 mixer_offset_start[0x10];
6090 u8 mixer_offset_end[0x10];
6092 u8 reserved_3[0x15];
6093 u8 ber_test_time[0xb];
6096 struct mlx5_ifc_pspa_reg_bits {
6102 u8 reserved_1[0x20];
6105 struct mlx5_ifc_pqdr_reg_bits {
6113 u8 reserved_3[0x20];
6115 u8 reserved_4[0x10];
6116 u8 min_threshold[0x10];
6118 u8 reserved_5[0x10];
6119 u8 max_threshold[0x10];
6121 u8 reserved_6[0x10];
6122 u8 mark_probability_denominator[0x10];
6124 u8 reserved_7[0x60];
6127 struct mlx5_ifc_ppsc_reg_bits {
6130 u8 reserved_1[0x10];
6132 u8 reserved_2[0x60];
6134 u8 reserved_3[0x1c];
6137 u8 reserved_4[0x1c];
6138 u8 wrps_status[0x4];
6141 u8 up_threshold[0x8];
6143 u8 down_threshold[0x8];
6145 u8 reserved_7[0x20];
6147 u8 reserved_8[0x1c];
6150 u8 reserved_9[0x1c];
6151 u8 srps_status[0x4];
6153 u8 reserved_10[0x40];
6156 struct mlx5_ifc_pplr_reg_bits {
6159 u8 reserved_1[0x10];
6167 struct mlx5_ifc_pplm_reg_bits {
6170 u8 reserved_1[0x10];
6172 u8 reserved_2[0x20];
6174 u8 port_profile_mode[0x8];
6175 u8 static_port_profile[0x8];
6176 u8 active_port_profile[0x8];
6179 u8 retransmission_active[0x8];
6180 u8 fec_mode_active[0x18];
6182 u8 reserved_4[0x20];
6185 struct mlx5_ifc_ppcnt_reg_bits {
6193 u8 reserved_1[0x1c];
6196 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6199 struct mlx5_ifc_ppad_reg_bits {
6208 u8 reserved_2[0x40];
6211 struct mlx5_ifc_pmtu_reg_bits {
6214 u8 reserved_1[0x10];
6217 u8 reserved_2[0x10];
6220 u8 reserved_3[0x10];
6223 u8 reserved_4[0x10];
6226 struct mlx5_ifc_pmpr_reg_bits {
6229 u8 reserved_1[0x10];
6231 u8 reserved_2[0x18];
6232 u8 attenuation_5g[0x8];
6234 u8 reserved_3[0x18];
6235 u8 attenuation_7g[0x8];
6237 u8 reserved_4[0x18];
6238 u8 attenuation_12g[0x8];
6241 struct mlx5_ifc_pmpe_reg_bits {
6245 u8 module_status[0x4];
6247 u8 reserved_2[0x60];
6250 struct mlx5_ifc_pmpc_reg_bits {
6251 u8 module_state_updated[32][0x8];
6254 struct mlx5_ifc_pmlpn_reg_bits {
6256 u8 mlpn_status[0x4];
6258 u8 reserved_1[0x10];
6261 u8 reserved_2[0x1f];
6264 struct mlx5_ifc_pmlp_reg_bits {
6271 u8 lane0_module_mapping[0x20];
6273 u8 lane1_module_mapping[0x20];
6275 u8 lane2_module_mapping[0x20];
6277 u8 lane3_module_mapping[0x20];
6279 u8 reserved_2[0x160];
6282 struct mlx5_ifc_pmaos_reg_bits {
6286 u8 admin_status[0x4];
6288 u8 oper_status[0x4];
6292 u8 reserved_3[0x1c];
6295 u8 reserved_4[0x40];
6298 struct mlx5_ifc_plpc_reg_bits {
6305 u8 reserved_3[0x10];
6306 u8 lane_speed[0x10];
6308 u8 reserved_4[0x17];
6310 u8 fec_mode_policy[0x8];
6312 u8 retransmission_capability[0x8];
6313 u8 fec_mode_capability[0x18];
6315 u8 retransmission_support_admin[0x8];
6316 u8 fec_mode_support_admin[0x18];
6318 u8 retransmission_request_admin[0x8];
6319 u8 fec_mode_request_admin[0x18];
6321 u8 reserved_5[0x80];
6324 struct mlx5_ifc_plib_reg_bits {
6330 u8 reserved_2[0x60];
6333 struct mlx5_ifc_plbf_reg_bits {
6339 u8 reserved_2[0x20];
6342 struct mlx5_ifc_pipg_reg_bits {
6345 u8 reserved_1[0x10];
6348 u8 reserved_2[0x19];
6353 struct mlx5_ifc_pifr_reg_bits {
6356 u8 reserved_1[0x10];
6358 u8 reserved_2[0xe0];
6360 u8 port_filter[8][0x20];
6362 u8 port_filter_update_en[8][0x20];
6365 struct mlx5_ifc_pfcc_reg_bits {
6368 u8 reserved_1[0x10];
6372 u8 prio_mask_tx[0x8];
6374 u8 prio_mask_rx[0x8];
6380 u8 reserved_5[0x10];
6386 u8 reserved_7[0x10];
6388 u8 reserved_8[0x80];
6391 struct mlx5_ifc_pelc_reg_bits {
6395 u8 reserved_1[0x10];
6398 u8 op_capability[0x8];
6404 u8 capability[0x40];
6410 u8 reserved_2[0x80];
6413 struct mlx5_ifc_peir_reg_bits {
6416 u8 reserved_1[0x10];
6419 u8 error_count[0x4];
6420 u8 reserved_3[0x10];
6428 struct mlx5_ifc_pcap_reg_bits {
6431 u8 reserved_1[0x10];
6433 u8 port_capability_mask[4][0x20];
6436 struct mlx5_ifc_paos_reg_bits {
6440 u8 admin_status[0x4];
6442 u8 oper_status[0x4];
6446 u8 reserved_2[0x1c];
6449 u8 reserved_3[0x40];
6452 struct mlx5_ifc_pamp_reg_bits {
6454 u8 opamp_group[0x8];
6456 u8 opamp_group_type[0x4];
6458 u8 start_index[0x10];
6460 u8 num_of_indices[0xc];
6462 u8 index_data[18][0x10];
6465 struct mlx5_ifc_lane_2_module_mapping_bits {
6474 struct mlx5_ifc_bufferx_reg_bits {
6481 u8 xoff_threshold[0x10];
6482 u8 xon_threshold[0x10];
6485 struct mlx5_ifc_set_node_in_bits {
6486 u8 node_description[64][0x8];
6489 struct mlx5_ifc_register_power_settings_bits {
6490 u8 reserved_0[0x18];
6491 u8 power_settings_level[0x8];
6493 u8 reserved_1[0x60];
6496 struct mlx5_ifc_register_host_endianness_bits {
6498 u8 reserved_0[0x1f];
6500 u8 reserved_1[0x60];
6503 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6504 u8 reserved_0[0x20];
6508 u8 addressh_63_32[0x20];
6510 u8 addressl_31_0[0x20];
6513 struct mlx5_ifc_ud_adrs_vector_bits {
6518 u8 destination_qp_dct[0x18];
6520 u8 static_rate[0x4];
6521 u8 sl_eth_prio[0x4];
6524 u8 rlid_udp_sport[0x10];
6526 u8 reserved_1[0x20];
6528 u8 rmac_47_16[0x20];
6537 u8 src_addr_index[0x8];
6538 u8 flow_label[0x14];
6540 u8 rgid_rip[16][0x8];
6543 struct mlx5_ifc_pages_req_event_bits {
6544 u8 reserved_0[0x10];
6545 u8 function_id[0x10];
6549 u8 reserved_1[0xa0];
6552 struct mlx5_ifc_eqe_bits {
6556 u8 event_sub_type[0x8];
6558 u8 reserved_2[0xe0];
6560 union mlx5_ifc_event_auto_bits event_data;
6562 u8 reserved_3[0x10];
6569 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
6572 struct mlx5_ifc_cmd_queue_entry_bits {
6574 u8 reserved_0[0x18];
6576 u8 input_length[0x20];
6578 u8 input_mailbox_pointer_63_32[0x20];
6580 u8 input_mailbox_pointer_31_9[0x17];
6583 u8 command_input_inline_data[16][0x8];
6585 u8 command_output_inline_data[16][0x8];
6587 u8 output_mailbox_pointer_63_32[0x20];
6589 u8 output_mailbox_pointer_31_9[0x17];
6592 u8 output_length[0x20];
6601 struct mlx5_ifc_cmd_out_bits {
6603 u8 reserved_0[0x18];
6607 u8 command_output[0x20];
6610 struct mlx5_ifc_cmd_in_bits {
6612 u8 reserved_0[0x10];
6614 u8 reserved_1[0x10];
6617 u8 command[0][0x20];
6620 struct mlx5_ifc_cmd_if_box_bits {
6621 u8 mailbox_data[512][0x8];
6623 u8 reserved_0[0x180];
6625 u8 next_pointer_63_32[0x20];
6627 u8 next_pointer_31_10[0x16];
6630 u8 block_number[0x20];
6634 u8 ctrl_signature[0x8];
6638 struct mlx5_ifc_mtt_bits {
6639 u8 ptag_63_32[0x20];
6648 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
6649 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
6650 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
6654 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
6655 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
6656 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
6660 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
6661 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
6662 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
6663 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
6664 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
6665 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
6666 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
6667 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
6668 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
6669 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
6670 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
6673 struct mlx5_ifc_initial_seg_bits {
6674 u8 fw_rev_minor[0x10];
6675 u8 fw_rev_major[0x10];
6677 u8 cmd_interface_rev[0x10];
6678 u8 fw_rev_subminor[0x10];
6680 u8 reserved_0[0x40];
6682 u8 cmdq_phy_addr_63_32[0x20];
6684 u8 cmdq_phy_addr_31_12[0x14];
6686 u8 nic_interface[0x2];
6687 u8 log_cmdq_size[0x4];
6688 u8 log_cmdq_stride[0x4];
6690 u8 command_doorbell_vector[0x20];
6692 u8 reserved_2[0xf00];
6694 u8 initializing[0x1];
6696 u8 nic_interface_supported[0x3];
6697 u8 reserved_4[0x18];
6699 struct mlx5_ifc_health_buffer_bits health_buffer;
6701 u8 no_dram_nic_offset[0x20];
6703 u8 reserved_5[0x6e40];
6705 u8 reserved_6[0x1f];
6708 u8 health_syndrome[0x8];
6709 u8 health_counter[0x18];
6711 u8 reserved_7[0x17fc0];
6714 union mlx5_ifc_ports_control_registers_document_bits {
6715 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6716 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6717 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6718 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6719 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6720 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6721 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6722 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6723 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6724 struct mlx5_ifc_pamp_reg_bits pamp_reg;
6725 struct mlx5_ifc_paos_reg_bits paos_reg;
6726 struct mlx5_ifc_pcap_reg_bits pcap_reg;
6727 struct mlx5_ifc_peir_reg_bits peir_reg;
6728 struct mlx5_ifc_pelc_reg_bits pelc_reg;
6729 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
6730 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6731 struct mlx5_ifc_pifr_reg_bits pifr_reg;
6732 struct mlx5_ifc_pipg_reg_bits pipg_reg;
6733 struct mlx5_ifc_plbf_reg_bits plbf_reg;
6734 struct mlx5_ifc_plib_reg_bits plib_reg;
6735 struct mlx5_ifc_plpc_reg_bits plpc_reg;
6736 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
6737 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
6738 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
6739 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
6740 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
6741 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
6742 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
6743 struct mlx5_ifc_ppad_reg_bits ppad_reg;
6744 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
6745 struct mlx5_ifc_pplm_reg_bits pplm_reg;
6746 struct mlx5_ifc_pplr_reg_bits pplr_reg;
6747 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
6748 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
6749 struct mlx5_ifc_pspa_reg_bits pspa_reg;
6750 struct mlx5_ifc_ptas_reg_bits ptas_reg;
6751 struct mlx5_ifc_ptys_reg_bits ptys_reg;
6752 struct mlx5_ifc_pude_reg_bits pude_reg;
6753 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
6754 struct mlx5_ifc_slrg_reg_bits slrg_reg;
6755 struct mlx5_ifc_sltp_reg_bits sltp_reg;
6756 u8 reserved_0[0x60e0];
6759 union mlx5_ifc_debug_enhancements_document_bits {
6760 struct mlx5_ifc_health_buffer_bits health_buffer;
6761 u8 reserved_0[0x200];
6764 union mlx5_ifc_uplink_pci_interface_document_bits {
6765 struct mlx5_ifc_initial_seg_bits initial_seg;
6766 u8 reserved_0[0x20060];
6769 #endif /* MLX5_IFC_H */