include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  71         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  72 };
  73
  74 enum {
  75         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  76         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  77         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  78         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  79         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  80         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  81         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  82         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  83         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  84         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  85         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  86         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  87         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  88         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  89         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  90         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  91         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  92         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  93         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  94         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  95         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  96         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  97         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  98         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
  99         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 100         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 101         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 102         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 103         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 104         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 105         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 106         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 107         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 108         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 109         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 110         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 111         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 112         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 113         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 114         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 115         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 116         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 117         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 118         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 119         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 120         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 121         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 122         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 123         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 124         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 125         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 126         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 127         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 128         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 129         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 130         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 131         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 132         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 133         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 134         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 135         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 136         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 137         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 138         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 139         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 140         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 141         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 142         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 143         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 144         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 145         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 146         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 147         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 148         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 149         MLX5_CMD_OP_DETTACH_FROM_MCG              = 0x807,
 150         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 151         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 152         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 153         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 154         MLX5_CMD_OP_NOP                           = 0x80d,
 155         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 156         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 157         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 158         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 159         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 160         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 161         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 162         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 163         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 164         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 165         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 166         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 167         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 168         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 169         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 170         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 171         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 172         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 173         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 174         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 175         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 176         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 177         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 178         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 179         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 180         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 181         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 182         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 183         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 184         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 185         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 186         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 187         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 188         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 189         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 190         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 191         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 192         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 193         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 194         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 195         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 196         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 197         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 198         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 199         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 200         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 201         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 202         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 203         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 204         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 205         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c
 206 };
 207
 208 struct mlx5_ifc_flow_table_fields_supported_bits {
 209         u8         outer_dmac[0x1];
 210         u8         outer_smac[0x1];
 211         u8         outer_ether_type[0x1];
 212         u8         reserved_at_3[0x1];
 213         u8         outer_first_prio[0x1];
 214         u8         outer_first_cfi[0x1];
 215         u8         outer_first_vid[0x1];
 216         u8         reserved_at_7[0x1];
 217         u8         outer_second_prio[0x1];
 218         u8         outer_second_cfi[0x1];
 219         u8         outer_second_vid[0x1];
 220         u8         reserved_at_b[0x1];
 221         u8         outer_sip[0x1];
 222         u8         outer_dip[0x1];
 223         u8         outer_frag[0x1];
 224         u8         outer_ip_protocol[0x1];
 225         u8         outer_ip_ecn[0x1];
 226         u8         outer_ip_dscp[0x1];
 227         u8         outer_udp_sport[0x1];
 228         u8         outer_udp_dport[0x1];
 229         u8         outer_tcp_sport[0x1];
 230         u8         outer_tcp_dport[0x1];
 231         u8         outer_tcp_flags[0x1];
 232         u8         outer_gre_protocol[0x1];
 233         u8         outer_gre_key[0x1];
 234         u8         outer_vxlan_vni[0x1];
 235         u8         reserved_at_1a[0x5];
 236         u8         source_eswitch_port[0x1];
 237
 238         u8         inner_dmac[0x1];
 239         u8         inner_smac[0x1];
 240         u8         inner_ether_type[0x1];
 241         u8         reserved_at_23[0x1];
 242         u8         inner_first_prio[0x1];
 243         u8         inner_first_cfi[0x1];
 244         u8         inner_first_vid[0x1];
 245         u8         reserved_at_27[0x1];
 246         u8         inner_second_prio[0x1];
 247         u8         inner_second_cfi[0x1];
 248         u8         inner_second_vid[0x1];
 249         u8         reserved_at_2b[0x1];
 250         u8         inner_sip[0x1];
 251         u8         inner_dip[0x1];
 252         u8         inner_frag[0x1];
 253         u8         inner_ip_protocol[0x1];
 254         u8         inner_ip_ecn[0x1];
 255         u8         inner_ip_dscp[0x1];
 256         u8         inner_udp_sport[0x1];
 257         u8         inner_udp_dport[0x1];
 258         u8         inner_tcp_sport[0x1];
 259         u8         inner_tcp_dport[0x1];
 260         u8         inner_tcp_flags[0x1];
 261         u8         reserved_at_37[0x9];
 262
 263         u8         reserved_at_40[0x40];
 264 };
 265
 266 struct mlx5_ifc_flow_table_prop_layout_bits {
 267         u8         ft_support[0x1];
 268         u8         reserved_at_1[0x2];
 269         u8         flow_modify_en[0x1];
 270         u8         modify_root[0x1];
 271         u8         identified_miss_table_mode[0x1];
 272         u8         flow_table_modify[0x1];
 273         u8         reserved_at_7[0x19];
 274
 275         u8         reserved_at_20[0x2];
 276         u8         log_max_ft_size[0x6];
 277         u8         reserved_at_28[0x10];
 278         u8         max_ft_level[0x8];
 279
 280         u8         reserved_at_40[0x20];
 281
 282         u8         reserved_at_60[0x18];
 283         u8         log_max_ft_num[0x8];
 284
 285         u8         reserved_at_80[0x18];
 286         u8         log_max_destination[0x8];
 287
 288         u8         reserved_at_a0[0x18];
 289         u8         log_max_flow[0x8];
 290
 291         u8         reserved_at_c0[0x40];
 292
 293         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 294
 295         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 296 };
 297
 298 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 299         u8         send[0x1];
 300         u8         receive[0x1];
 301         u8         write[0x1];
 302         u8         read[0x1];
 303         u8         reserved_at_4[0x1];
 304         u8         srq_receive[0x1];
 305         u8         reserved_at_6[0x1a];
 306 };
 307
 308 struct mlx5_ifc_ipv4_layout_bits {
 309         u8         reserved_at_0[0x60];
 310
 311         u8         ipv4[0x20];
 312 };
 313
 314 struct mlx5_ifc_ipv6_layout_bits {
 315         u8         ipv6[16][0x8];
 316 };
 317
 318 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 319         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 320         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 321         u8         reserved_at_0[0x80];
 322 };
 323
 324 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 325         u8         smac_47_16[0x20];
 326
 327         u8         smac_15_0[0x10];
 328         u8         ethertype[0x10];
 329
 330         u8         dmac_47_16[0x20];
 331
 332         u8         dmac_15_0[0x10];
 333         u8         first_prio[0x3];
 334         u8         first_cfi[0x1];
 335         u8         first_vid[0xc];
 336
 337         u8         ip_protocol[0x8];
 338         u8         ip_dscp[0x6];
 339         u8         ip_ecn[0x2];
 340         u8         vlan_tag[0x1];
 341         u8         reserved_at_91[0x1];
 342         u8         frag[0x1];
 343         u8         reserved_at_93[0x4];
 344         u8         tcp_flags[0x9];
 345
 346         u8         tcp_sport[0x10];
 347         u8         tcp_dport[0x10];
 348
 349         u8         reserved_at_c0[0x20];
 350
 351         u8         udp_sport[0x10];
 352         u8         udp_dport[0x10];
 353
 354         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 355
 356         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 357 };
 358
 359 struct mlx5_ifc_fte_match_set_misc_bits {
 360         u8         reserved_at_0[0x20];
 361
 362         u8         reserved_at_20[0x10];
 363         u8         source_port[0x10];
 364
 365         u8         outer_second_prio[0x3];
 366         u8         outer_second_cfi[0x1];
 367         u8         outer_second_vid[0xc];
 368         u8         inner_second_prio[0x3];
 369         u8         inner_second_cfi[0x1];
 370         u8         inner_second_vid[0xc];
 371
 372         u8         outer_second_vlan_tag[0x1];
 373         u8         inner_second_vlan_tag[0x1];
 374         u8         reserved_at_62[0xe];
 375         u8         gre_protocol[0x10];
 376
 377         u8         gre_key_h[0x18];
 378         u8         gre_key_l[0x8];
 379
 380         u8         vxlan_vni[0x18];
 381         u8         reserved_at_b8[0x8];
 382
 383         u8         reserved_at_c0[0x20];
 384
 385         u8         reserved_at_e0[0xc];
 386         u8         outer_ipv6_flow_label[0x14];
 387
 388         u8         reserved_at_100[0xc];
 389         u8         inner_ipv6_flow_label[0x14];
 390
 391         u8         reserved_at_120[0xe0];
 392 };
 393
 394 struct mlx5_ifc_cmd_pas_bits {
 395         u8         pa_h[0x20];
 396
 397         u8         pa_l[0x14];
 398         u8         reserved_at_34[0xc];
 399 };
 400
 401 struct mlx5_ifc_uint64_bits {
 402         u8         hi[0x20];
 403
 404         u8         lo[0x20];
 405 };
 406
 407 enum {
 408         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 409         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 410         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 411         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 412         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 413         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 414         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 415         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 416         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 417         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 418 };
 419
 420 struct mlx5_ifc_ads_bits {
 421         u8         fl[0x1];
 422         u8         free_ar[0x1];
 423         u8         reserved_at_2[0xe];
 424         u8         pkey_index[0x10];
 425
 426         u8         reserved_at_20[0x8];
 427         u8         grh[0x1];
 428         u8         mlid[0x7];
 429         u8         rlid[0x10];
 430
 431         u8         ack_timeout[0x5];
 432         u8         reserved_at_45[0x3];
 433         u8         src_addr_index[0x8];
 434         u8         reserved_at_50[0x4];
 435         u8         stat_rate[0x4];
 436         u8         hop_limit[0x8];
 437
 438         u8         reserved_at_60[0x4];
 439         u8         tclass[0x8];
 440         u8         flow_label[0x14];
 441
 442         u8         rgid_rip[16][0x8];
 443
 444         u8         reserved_at_100[0x4];
 445         u8         f_dscp[0x1];
 446         u8         f_ecn[0x1];
 447         u8         reserved_at_106[0x1];
 448         u8         f_eth_prio[0x1];
 449         u8         ecn[0x2];
 450         u8         dscp[0x6];
 451         u8         udp_sport[0x10];
 452
 453         u8         dei_cfi[0x1];
 454         u8         eth_prio[0x3];
 455         u8         sl[0x4];
 456         u8         port[0x8];
 457         u8         rmac_47_32[0x10];
 458
 459         u8         rmac_31_0[0x20];
 460 };
 461
 462 struct mlx5_ifc_flow_table_nic_cap_bits {
 463         u8         nic_rx_multi_path_tirs[0x1];
 464         u8         reserved_at_1[0x1ff];
 465
 466         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 467
 468         u8         reserved_at_400[0x200];
 469
 470         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 471
 472         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 473
 474         u8         reserved_at_a00[0x200];
 475
 476         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 477
 478         u8         reserved_at_e00[0x7200];
 479 };
 480
 481 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 482         u8     reserved_at_0[0x200];
 483
 484         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 485
 486         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 487
 488         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 489
 490         u8      reserved_at_800[0x7800];
 491 };
 492
 493 struct mlx5_ifc_e_switch_cap_bits {
 494         u8         vport_svlan_strip[0x1];
 495         u8         vport_cvlan_strip[0x1];
 496         u8         vport_svlan_insert[0x1];
 497         u8         vport_cvlan_insert_if_not_exist[0x1];
 498         u8         vport_cvlan_insert_overwrite[0x1];
 499         u8         reserved_at_5[0x1b];
 500
 501         u8         reserved_at_20[0x7e0];
 502 };
 503
 504 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 505         u8         csum_cap[0x1];
 506         u8         vlan_cap[0x1];
 507         u8         lro_cap[0x1];
 508         u8         lro_psh_flag[0x1];
 509         u8         lro_time_stamp[0x1];
 510         u8         reserved_at_5[0x3];
 511         u8         self_lb_en_modifiable[0x1];
 512         u8         reserved_at_9[0x2];
 513         u8         max_lso_cap[0x5];
 514         u8         reserved_at_10[0x4];
 515         u8         rss_ind_tbl_cap[0x4];
 516         u8         reserved_at_18[0x3];
 517         u8         tunnel_lso_const_out_ip_id[0x1];
 518         u8         reserved_at_1c[0x2];
 519         u8         tunnel_statless_gre[0x1];
 520         u8         tunnel_stateless_vxlan[0x1];
 521
 522         u8         reserved_at_20[0x20];
 523
 524         u8         reserved_at_40[0x10];
 525         u8         lro_min_mss_size[0x10];
 526
 527         u8         reserved_at_60[0x120];
 528
 529         u8         lro_timer_supported_periods[4][0x20];
 530
 531         u8         reserved_at_200[0x600];
 532 };
 533
 534 struct mlx5_ifc_roce_cap_bits {
 535         u8         roce_apm[0x1];
 536         u8         reserved_at_1[0x1f];
 537
 538         u8         reserved_at_20[0x60];
 539
 540         u8         reserved_at_80[0xc];
 541         u8         l3_type[0x4];
 542         u8         reserved_at_90[0x8];
 543         u8         roce_version[0x8];
 544
 545         u8         reserved_at_a0[0x10];
 546         u8         r_roce_dest_udp_port[0x10];
 547
 548         u8         r_roce_max_src_udp_port[0x10];
 549         u8         r_roce_min_src_udp_port[0x10];
 550
 551         u8         reserved_at_e0[0x10];
 552         u8         roce_address_table_size[0x10];
 553
 554         u8         reserved_at_100[0x700];
 555 };
 556
 557 enum {
 558         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 559         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 560         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 561         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 562         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 563         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 564         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 565         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 566         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 567 };
 568
 569 enum {
 570         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 571         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 572         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 573         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 574         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 575         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 576         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 577         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 578         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 579 };
 580
 581 struct mlx5_ifc_atomic_caps_bits {
 582         u8         reserved_at_0[0x40];
 583
 584         u8         atomic_req_8B_endianess_mode[0x2];
 585         u8         reserved_at_42[0x4];
 586         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 587
 588         u8         reserved_at_47[0x19];
 589
 590         u8         reserved_at_60[0x20];
 591
 592         u8         reserved_at_80[0x10];
 593         u8         atomic_operations[0x10];
 594
 595         u8         reserved_at_a0[0x10];
 596         u8         atomic_size_qp[0x10];
 597
 598         u8         reserved_at_c0[0x10];
 599         u8         atomic_size_dc[0x10];
 600
 601         u8         reserved_at_e0[0x720];
 602 };
 603
 604 struct mlx5_ifc_odp_cap_bits {
 605         u8         reserved_at_0[0x40];
 606
 607         u8         sig[0x1];
 608         u8         reserved_at_41[0x1f];
 609
 610         u8         reserved_at_60[0x20];
 611
 612         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 613
 614         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 615
 616         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 617
 618         u8         reserved_at_e0[0x720];
 619 };
 620
 621 struct mlx5_ifc_calc_op {
 622         u8        reserved_at_0[0x10];
 623         u8        reserved_at_10[0x9];
 624         u8        op_swap_endianness[0x1];
 625         u8        op_min[0x1];
 626         u8        op_xor[0x1];
 627         u8        op_or[0x1];
 628         u8        op_and[0x1];
 629         u8        op_max[0x1];
 630         u8        op_add[0x1];
 631 };
 632
 633 struct mlx5_ifc_vector_calc_cap_bits {
 634         u8         calc_matrix[0x1];
 635         u8         reserved_at_1[0x1f];
 636         u8         reserved_at_20[0x8];
 637         u8         max_vec_count[0x8];
 638         u8         reserved_at_30[0xd];
 639         u8         max_chunk_size[0x3];
 640         struct mlx5_ifc_calc_op calc0;
 641         struct mlx5_ifc_calc_op calc1;
 642         struct mlx5_ifc_calc_op calc2;
 643         struct mlx5_ifc_calc_op calc3;
 644
 645         u8         reserved_at_e0[0x720];
 646 };
 647
 648 enum {
 649         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 650         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 651         MLX5_WQ_TYPE_STRQ         = 0x2,
 652 };
 653
 654 enum {
 655         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 656         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 657 };
 658
 659 enum {
 660         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 661         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 662         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 663         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 664         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 665 };
 666
 667 enum {
 668         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 669         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 670         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 671         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 672         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 673         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 674 };
 675
 676 enum {
 677         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 678         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 679 };
 680
 681 enum {
 682         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 683         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 684         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 685 };
 686
 687 enum {
 688         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 689         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 690 };
 691
 692 struct mlx5_ifc_cmd_hca_cap_bits {
 693         u8         reserved_at_0[0x80];
 694
 695         u8         log_max_srq_sz[0x8];
 696         u8         log_max_qp_sz[0x8];
 697         u8         reserved_at_90[0xb];
 698         u8         log_max_qp[0x5];
 699
 700         u8         reserved_at_a0[0xb];
 701         u8         log_max_srq[0x5];
 702         u8         reserved_at_b0[0x10];
 703
 704         u8         reserved_at_c0[0x8];
 705         u8         log_max_cq_sz[0x8];
 706         u8         reserved_at_d0[0xb];
 707         u8         log_max_cq[0x5];
 708
 709         u8         log_max_eq_sz[0x8];
 710         u8         reserved_at_e8[0x2];
 711         u8         log_max_mkey[0x6];
 712         u8         reserved_at_f0[0xc];
 713         u8         log_max_eq[0x4];
 714
 715         u8         max_indirection[0x8];
 716         u8         reserved_at_108[0x1];
 717         u8         log_max_mrw_sz[0x7];
 718         u8         reserved_at_110[0x2];
 719         u8         log_max_bsf_list_size[0x6];
 720         u8         reserved_at_118[0x2];
 721         u8         log_max_klm_list_size[0x6];
 722
 723         u8         reserved_at_120[0xa];
 724         u8         log_max_ra_req_dc[0x6];
 725         u8         reserved_at_130[0xa];
 726         u8         log_max_ra_res_dc[0x6];
 727
 728         u8         reserved_at_140[0xa];
 729         u8         log_max_ra_req_qp[0x6];
 730         u8         reserved_at_150[0xa];
 731         u8         log_max_ra_res_qp[0x6];
 732
 733         u8         pad_cap[0x1];
 734         u8         cc_query_allowed[0x1];
 735         u8         cc_modify_allowed[0x1];
 736         u8         reserved_at_163[0xd];
 737         u8         gid_table_size[0x10];
 738
 739         u8         out_of_seq_cnt[0x1];
 740         u8         vport_counters[0x1];
 741         u8         reserved_at_182[0x4];
 742         u8         max_qp_cnt[0xa];
 743         u8         pkey_table_size[0x10];
 744
 745         u8         vport_group_manager[0x1];
 746         u8         vhca_group_manager[0x1];
 747         u8         ib_virt[0x1];
 748         u8         eth_virt[0x1];
 749         u8         reserved_at_1a4[0x1];
 750         u8         ets[0x1];
 751         u8         nic_flow_table[0x1];
 752         u8         eswitch_flow_table[0x1];
 753         u8         early_vf_enable[0x1];
 754         u8         reserved_at_1a9[0x2];
 755         u8         local_ca_ack_delay[0x5];
 756         u8         reserved_at_1af[0x6];
 757         u8         port_type[0x2];
 758         u8         num_ports[0x8];
 759
 760         u8         reserved_at_1c0[0x3];
 761         u8         log_max_msg[0x5];
 762         u8         reserved_at_1c8[0x4];
 763         u8         max_tc[0x4];
 764         u8         reserved_at_1d0[0x6];
 765         u8         rol_s[0x1];
 766         u8         rol_g[0x1];
 767         u8         reserved_at_1d8[0x1];
 768         u8         wol_s[0x1];
 769         u8         wol_g[0x1];
 770         u8         wol_a[0x1];
 771         u8         wol_b[0x1];
 772         u8         wol_m[0x1];
 773         u8         wol_u[0x1];
 774         u8         wol_p[0x1];
 775
 776         u8         stat_rate_support[0x10];
 777         u8         reserved_at_1f0[0xc];
 778         u8         cqe_version[0x4];
 779
 780         u8         compact_address_vector[0x1];
 781         u8         reserved_at_200[0x3];
 782         u8         ipoib_basic_offloads[0x1];
 783         u8         reserved_at_205[0xa];
 784         u8         drain_sigerr[0x1];
 785         u8         cmdif_checksum[0x2];
 786         u8         sigerr_cqe[0x1];
 787         u8         reserved_at_213[0x1];
 788         u8         wq_signature[0x1];
 789         u8         sctr_data_cqe[0x1];
 790         u8         reserved_at_216[0x1];
 791         u8         sho[0x1];
 792         u8         tph[0x1];
 793         u8         rf[0x1];
 794         u8         dct[0x1];
 795         u8         reserved_at_21b[0x1];
 796         u8         eth_net_offloads[0x1];
 797         u8         roce[0x1];
 798         u8         atomic[0x1];
 799         u8         reserved_at_21f[0x1];
 800
 801         u8         cq_oi[0x1];
 802         u8         cq_resize[0x1];
 803         u8         cq_moderation[0x1];
 804         u8         reserved_at_223[0x3];
 805         u8         cq_eq_remap[0x1];
 806         u8         pg[0x1];
 807         u8         block_lb_mc[0x1];
 808         u8         reserved_at_229[0x1];
 809         u8         scqe_break_moderation[0x1];
 810         u8         reserved_at_22a[0x1];
 811         u8         cd[0x1];
 812         u8         reserved_at_22d[0x1];
 813         u8         apm[0x1];
 814         u8         vector_calc[0x1];
 815         u8         reserved_at_22f[0x1];
 816         u8         imaicl[0x1];
 817         u8         reserved_at_232[0x4];
 818         u8         qkv[0x1];
 819         u8         pkv[0x1];
 820         u8         set_deth_sqpn[0x1];
 821         u8         reserved_at_239[0x3];
 822         u8         xrc[0x1];
 823         u8         ud[0x1];
 824         u8         uc[0x1];
 825         u8         rc[0x1];
 826
 827         u8         reserved_at_240[0xa];
 828         u8         uar_sz[0x6];
 829         u8         reserved_at_250[0x8];
 830         u8         log_pg_sz[0x8];
 831
 832         u8         bf[0x1];
 833         u8         reserved_at_261[0x1];
 834         u8         pad_tx_eth_packet[0x1];
 835         u8         reserved_at_263[0x8];
 836         u8         log_bf_reg_size[0x5];
 837         u8         reserved_at_270[0x10];
 838
 839         u8         reserved_at_280[0x10];
 840         u8         max_wqe_sz_sq[0x10];
 841
 842         u8         reserved_at_2a0[0x10];
 843         u8         max_wqe_sz_rq[0x10];
 844
 845         u8         reserved_at_2c0[0x10];
 846         u8         max_wqe_sz_sq_dc[0x10];
 847
 848         u8         reserved_at_2e0[0x7];
 849         u8         max_qp_mcg[0x19];
 850
 851         u8         reserved_at_300[0x18];
 852         u8         log_max_mcg[0x8];
 853
 854         u8         reserved_at_320[0x3];
 855         u8         log_max_transport_domain[0x5];
 856         u8         reserved_at_328[0x3];
 857         u8         log_max_pd[0x5];
 858         u8         reserved_at_330[0xb];
 859         u8         log_max_xrcd[0x5];
 860
 861         u8         reserved_at_340[0x20];
 862
 863         u8         reserved_at_360[0x3];
 864         u8         log_max_rq[0x5];
 865         u8         reserved_at_368[0x3];
 866         u8         log_max_sq[0x5];
 867         u8         reserved_at_370[0x3];
 868         u8         log_max_tir[0x5];
 869         u8         reserved_at_378[0x3];
 870         u8         log_max_tis[0x5];
 871
 872         u8         basic_cyclic_rcv_wqe[0x1];
 873         u8         reserved_at_381[0x2];
 874         u8         log_max_rmp[0x5];
 875         u8         reserved_at_388[0x3];
 876         u8         log_max_rqt[0x5];
 877         u8         reserved_at_390[0x3];
 878         u8         log_max_rqt_size[0x5];
 879         u8         reserved_at_398[0x3];
 880         u8         log_max_tis_per_sq[0x5];
 881
 882         u8         reserved_at_3a0[0x3];
 883         u8         log_max_stride_sz_rq[0x5];
 884         u8         reserved_at_3a8[0x3];
 885         u8         log_min_stride_sz_rq[0x5];
 886         u8         reserved_at_3b0[0x3];
 887         u8         log_max_stride_sz_sq[0x5];
 888         u8         reserved_at_3b8[0x3];
 889         u8         log_min_stride_sz_sq[0x5];
 890
 891         u8         reserved_at_3c0[0x1b];
 892         u8         log_max_wq_sz[0x5];
 893
 894         u8         nic_vport_change_event[0x1];
 895         u8         reserved_at_3e1[0xa];
 896         u8         log_max_vlan_list[0x5];
 897         u8         reserved_at_3f0[0x3];
 898         u8         log_max_current_mc_list[0x5];
 899         u8         reserved_at_3f8[0x3];
 900         u8         log_max_current_uc_list[0x5];
 901
 902         u8         reserved_at_400[0x80];
 903
 904         u8         reserved_at_480[0x3];
 905         u8         log_max_l2_table[0x5];
 906         u8         reserved_at_488[0x8];
 907         u8         log_uar_page_sz[0x10];
 908
 909         u8         reserved_at_4a0[0x20];
 910         u8         device_frequency_mhz[0x20];
 911         u8         device_frequency_khz[0x20];
 912
 913         u8         reserved_at_500[0x80];
 914
 915         u8         reserved_at_580[0x3f];
 916         u8         cqe_zip[0x1];
 917
 918         u8         cqe_zip_timeout[0x10];
 919         u8         cqe_zip_max_num[0x10];
 920
 921         u8         reserved_at_5e0[0x220];
 922 };
 923
 924 enum mlx5_flow_destination_type {
 925         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
 926         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
 927         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
 928 };
 929
 930 struct mlx5_ifc_dest_format_struct_bits {
 931         u8         destination_type[0x8];
 932         u8         destination_id[0x18];
 933
 934         u8         reserved_at_20[0x20];
 935 };
 936
 937 struct mlx5_ifc_fte_match_param_bits {
 938         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
 939
 940         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
 941
 942         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 943
 944         u8         reserved_at_600[0xa00];
 945 };
 946
 947 enum {
 948         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
 949         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
 950         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
 951         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
 952         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
 953 };
 954
 955 struct mlx5_ifc_rx_hash_field_select_bits {
 956         u8         l3_prot_type[0x1];
 957         u8         l4_prot_type[0x1];
 958         u8         selected_fields[0x1e];
 959 };
 960
 961 enum {
 962         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
 963         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
 964 };
 965
 966 enum {
 967         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
 968         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
 969 };
 970
 971 struct mlx5_ifc_wq_bits {
 972         u8         wq_type[0x4];
 973         u8         wq_signature[0x1];
 974         u8         end_padding_mode[0x2];
 975         u8         cd_slave[0x1];
 976         u8         reserved_at_8[0x18];
 977
 978         u8         hds_skip_first_sge[0x1];
 979         u8         log2_hds_buf_size[0x3];
 980         u8         reserved_at_24[0x7];
 981         u8         page_offset[0x5];
 982         u8         lwm[0x10];
 983
 984         u8         reserved_at_40[0x8];
 985         u8         pd[0x18];
 986
 987         u8         reserved_at_60[0x8];
 988         u8         uar_page[0x18];
 989
 990         u8         dbr_addr[0x40];
 991
 992         u8         hw_counter[0x20];
 993
 994         u8         sw_counter[0x20];
 995
 996         u8         reserved_at_100[0xc];
 997         u8         log_wq_stride[0x4];
 998         u8         reserved_at_110[0x3];
 999         u8         log_wq_pg_sz[0x5];
1000         u8         reserved_at_118[0x3];
1001         u8         log_wq_sz[0x5];
1002
1003         u8         reserved_at_120[0x4e0];
1004
1005         struct mlx5_ifc_cmd_pas_bits pas[0];
1006 };
1007
1008 struct mlx5_ifc_rq_num_bits {
1009         u8         reserved_at_0[0x8];
1010         u8         rq_num[0x18];
1011 };
1012
1013 struct mlx5_ifc_mac_address_layout_bits {
1014         u8         reserved_at_0[0x10];
1015         u8         mac_addr_47_32[0x10];
1016
1017         u8         mac_addr_31_0[0x20];
1018 };
1019
1020 struct mlx5_ifc_vlan_layout_bits {
1021         u8         reserved_at_0[0x14];
1022         u8         vlan[0x0c];
1023
1024         u8         reserved_at_20[0x20];
1025 };
1026
1027 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1028         u8         reserved_at_0[0xa0];
1029
1030         u8         min_time_between_cnps[0x20];
1031
1032         u8         reserved_at_c0[0x12];
1033         u8         cnp_dscp[0x6];
1034         u8         reserved_at_d8[0x5];
1035         u8         cnp_802p_prio[0x3];
1036
1037         u8         reserved_at_e0[0x720];
1038 };
1039
1040 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1041         u8         reserved_at_0[0x60];
1042
1043         u8         reserved_at_60[0x4];
1044         u8         clamp_tgt_rate[0x1];
1045         u8         reserved_at_65[0x3];
1046         u8         clamp_tgt_rate_after_time_inc[0x1];
1047         u8         reserved_at_69[0x17];
1048
1049         u8         reserved_at_80[0x20];
1050
1051         u8         rpg_time_reset[0x20];
1052
1053         u8         rpg_byte_reset[0x20];
1054
1055         u8         rpg_threshold[0x20];
1056
1057         u8         rpg_max_rate[0x20];
1058
1059         u8         rpg_ai_rate[0x20];
1060
1061         u8         rpg_hai_rate[0x20];
1062
1063         u8         rpg_gd[0x20];
1064
1065         u8         rpg_min_dec_fac[0x20];
1066
1067         u8         rpg_min_rate[0x20];
1068
1069         u8         reserved_at_1c0[0xe0];
1070
1071         u8         rate_to_set_on_first_cnp[0x20];
1072
1073         u8         dce_tcp_g[0x20];
1074
1075         u8         dce_tcp_rtt[0x20];
1076
1077         u8         rate_reduce_monitor_period[0x20];
1078
1079         u8         reserved_at_320[0x20];
1080
1081         u8         initial_alpha_value[0x20];
1082
1083         u8         reserved_at_360[0x4a0];
1084 };
1085
1086 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1087         u8         reserved_at_0[0x80];
1088
1089         u8         rppp_max_rps[0x20];
1090
1091         u8         rpg_time_reset[0x20];
1092
1093         u8         rpg_byte_reset[0x20];
1094
1095         u8         rpg_threshold[0x20];
1096
1097         u8         rpg_max_rate[0x20];
1098
1099         u8         rpg_ai_rate[0x20];
1100
1101         u8         rpg_hai_rate[0x20];
1102
1103         u8         rpg_gd[0x20];
1104
1105         u8         rpg_min_dec_fac[0x20];
1106
1107         u8         rpg_min_rate[0x20];
1108
1109         u8         reserved_at_1c0[0x640];
1110 };
1111
1112 enum {
1113         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1114         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1115         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1116 };
1117
1118 struct mlx5_ifc_resize_field_select_bits {
1119         u8         resize_field_select[0x20];
1120 };
1121
1122 enum {
1123         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1124         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1125         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1126         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1127 };
1128
1129 struct mlx5_ifc_modify_field_select_bits {
1130         u8         modify_field_select[0x20];
1131 };
1132
1133 struct mlx5_ifc_field_select_r_roce_np_bits {
1134         u8         field_select_r_roce_np[0x20];
1135 };
1136
1137 struct mlx5_ifc_field_select_r_roce_rp_bits {
1138         u8         field_select_r_roce_rp[0x20];
1139 };
1140
1141 enum {
1142         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1143         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1144         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1145         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1146         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1147         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1148         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1149         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1150         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1151         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1152 };
1153
1154 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1155         u8         field_select_8021qaurp[0x20];
1156 };
1157
1158 struct mlx5_ifc_phys_layer_cntrs_bits {
1159         u8         time_since_last_clear_high[0x20];
1160
1161         u8         time_since_last_clear_low[0x20];
1162
1163         u8         symbol_errors_high[0x20];
1164
1165         u8         symbol_errors_low[0x20];
1166
1167         u8         sync_headers_errors_high[0x20];
1168
1169         u8         sync_headers_errors_low[0x20];
1170
1171         u8         edpl_bip_errors_lane0_high[0x20];
1172
1173         u8         edpl_bip_errors_lane0_low[0x20];
1174
1175         u8         edpl_bip_errors_lane1_high[0x20];
1176
1177         u8         edpl_bip_errors_lane1_low[0x20];
1178
1179         u8         edpl_bip_errors_lane2_high[0x20];
1180
1181         u8         edpl_bip_errors_lane2_low[0x20];
1182
1183         u8         edpl_bip_errors_lane3_high[0x20];
1184
1185         u8         edpl_bip_errors_lane3_low[0x20];
1186
1187         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1188
1189         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1190
1191         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1192
1193         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1194
1195         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1196
1197         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1198
1199         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1200
1201         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1202
1203         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1204
1205         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1206
1207         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1208
1209         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1210
1211         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1212
1213         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1214
1215         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1216
1217         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1218
1219         u8         rs_fec_corrected_blocks_high[0x20];
1220
1221         u8         rs_fec_corrected_blocks_low[0x20];
1222
1223         u8         rs_fec_uncorrectable_blocks_high[0x20];
1224
1225         u8         rs_fec_uncorrectable_blocks_low[0x20];
1226
1227         u8         rs_fec_no_errors_blocks_high[0x20];
1228
1229         u8         rs_fec_no_errors_blocks_low[0x20];
1230
1231         u8         rs_fec_single_error_blocks_high[0x20];
1232
1233         u8         rs_fec_single_error_blocks_low[0x20];
1234
1235         u8         rs_fec_corrected_symbols_total_high[0x20];
1236
1237         u8         rs_fec_corrected_symbols_total_low[0x20];
1238
1239         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1240
1241         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1242
1243         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1244
1245         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1246
1247         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1248
1249         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1250
1251         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1252
1253         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1254
1255         u8         link_down_events[0x20];
1256
1257         u8         successful_recovery_events[0x20];
1258
1259         u8         reserved_at_640[0x180];
1260 };
1261
1262 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1263         u8         symbol_error_counter[0x10];
1264
1265         u8         link_error_recovery_counter[0x8];
1266
1267         u8         link_downed_counter[0x8];
1268
1269         u8         port_rcv_errors[0x10];
1270
1271         u8         port_rcv_remote_physical_errors[0x10];
1272
1273         u8         port_rcv_switch_relay_errors[0x10];
1274
1275         u8         port_xmit_discards[0x10];
1276
1277         u8         port_xmit_constraint_errors[0x8];
1278
1279         u8         port_rcv_constraint_errors[0x8];
1280
1281         u8         reserved_at_70[0x8];
1282
1283         u8         link_overrun_errors[0x8];
1284
1285         u8         reserved_at_80[0x10];
1286
1287         u8         vl_15_dropped[0x10];
1288
1289         u8         reserved_at_a0[0xa0];
1290 };
1291
1292 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1293         u8         transmit_queue_high[0x20];
1294
1295         u8         transmit_queue_low[0x20];
1296
1297         u8         reserved_at_40[0x780];
1298 };
1299
1300 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1301         u8         rx_octets_high[0x20];
1302
1303         u8         rx_octets_low[0x20];
1304
1305         u8         reserved_at_40[0xc0];
1306
1307         u8         rx_frames_high[0x20];
1308
1309         u8         rx_frames_low[0x20];
1310
1311         u8         tx_octets_high[0x20];
1312
1313         u8         tx_octets_low[0x20];
1314
1315         u8         reserved_at_180[0xc0];
1316
1317         u8         tx_frames_high[0x20];
1318
1319         u8         tx_frames_low[0x20];
1320
1321         u8         rx_pause_high[0x20];
1322
1323         u8         rx_pause_low[0x20];
1324
1325         u8         rx_pause_duration_high[0x20];
1326
1327         u8         rx_pause_duration_low[0x20];
1328
1329         u8         tx_pause_high[0x20];
1330
1331         u8         tx_pause_low[0x20];
1332
1333         u8         tx_pause_duration_high[0x20];
1334
1335         u8         tx_pause_duration_low[0x20];
1336
1337         u8         rx_pause_transition_high[0x20];
1338
1339         u8         rx_pause_transition_low[0x20];
1340
1341         u8         reserved_at_3c0[0x400];
1342 };
1343
1344 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1345         u8         port_transmit_wait_high[0x20];
1346
1347         u8         port_transmit_wait_low[0x20];
1348
1349         u8         reserved_at_40[0x780];
1350 };
1351
1352 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1353         u8         dot3stats_alignment_errors_high[0x20];
1354
1355         u8         dot3stats_alignment_errors_low[0x20];
1356
1357         u8         dot3stats_fcs_errors_high[0x20];
1358
1359         u8         dot3stats_fcs_errors_low[0x20];
1360
1361         u8         dot3stats_single_collision_frames_high[0x20];
1362
1363         u8         dot3stats_single_collision_frames_low[0x20];
1364
1365         u8         dot3stats_multiple_collision_frames_high[0x20];
1366
1367         u8         dot3stats_multiple_collision_frames_low[0x20];
1368
1369         u8         dot3stats_sqe_test_errors_high[0x20];
1370
1371         u8         dot3stats_sqe_test_errors_low[0x20];
1372
1373         u8         dot3stats_deferred_transmissions_high[0x20];
1374
1375         u8         dot3stats_deferred_transmissions_low[0x20];
1376
1377         u8         dot3stats_late_collisions_high[0x20];
1378
1379         u8         dot3stats_late_collisions_low[0x20];
1380
1381         u8         dot3stats_excessive_collisions_high[0x20];
1382
1383         u8         dot3stats_excessive_collisions_low[0x20];
1384
1385         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1386
1387         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1388
1389         u8         dot3stats_carrier_sense_errors_high[0x20];
1390
1391         u8         dot3stats_carrier_sense_errors_low[0x20];
1392
1393         u8         dot3stats_frame_too_longs_high[0x20];
1394
1395         u8         dot3stats_frame_too_longs_low[0x20];
1396
1397         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1398
1399         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1400
1401         u8         dot3stats_symbol_errors_high[0x20];
1402
1403         u8         dot3stats_symbol_errors_low[0x20];
1404
1405         u8         dot3control_in_unknown_opcodes_high[0x20];
1406
1407         u8         dot3control_in_unknown_opcodes_low[0x20];
1408
1409         u8         dot3in_pause_frames_high[0x20];
1410
1411         u8         dot3in_pause_frames_low[0x20];
1412
1413         u8         dot3out_pause_frames_high[0x20];
1414
1415         u8         dot3out_pause_frames_low[0x20];
1416
1417         u8         reserved_at_400[0x3c0];
1418 };
1419
1420 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1421         u8         ether_stats_drop_events_high[0x20];
1422
1423         u8         ether_stats_drop_events_low[0x20];
1424
1425         u8         ether_stats_octets_high[0x20];
1426
1427         u8         ether_stats_octets_low[0x20];
1428
1429         u8         ether_stats_pkts_high[0x20];
1430
1431         u8         ether_stats_pkts_low[0x20];
1432
1433         u8         ether_stats_broadcast_pkts_high[0x20];
1434
1435         u8         ether_stats_broadcast_pkts_low[0x20];
1436
1437         u8         ether_stats_multicast_pkts_high[0x20];
1438
1439         u8         ether_stats_multicast_pkts_low[0x20];
1440
1441         u8         ether_stats_crc_align_errors_high[0x20];
1442
1443         u8         ether_stats_crc_align_errors_low[0x20];
1444
1445         u8         ether_stats_undersize_pkts_high[0x20];
1446
1447         u8         ether_stats_undersize_pkts_low[0x20];
1448
1449         u8         ether_stats_oversize_pkts_high[0x20];
1450
1451         u8         ether_stats_oversize_pkts_low[0x20];
1452
1453         u8         ether_stats_fragments_high[0x20];
1454
1455         u8         ether_stats_fragments_low[0x20];
1456
1457         u8         ether_stats_jabbers_high[0x20];
1458
1459         u8         ether_stats_jabbers_low[0x20];
1460
1461         u8         ether_stats_collisions_high[0x20];
1462
1463         u8         ether_stats_collisions_low[0x20];
1464
1465         u8         ether_stats_pkts64octets_high[0x20];
1466
1467         u8         ether_stats_pkts64octets_low[0x20];
1468
1469         u8         ether_stats_pkts65to127octets_high[0x20];
1470
1471         u8         ether_stats_pkts65to127octets_low[0x20];
1472
1473         u8         ether_stats_pkts128to255octets_high[0x20];
1474
1475         u8         ether_stats_pkts128to255octets_low[0x20];
1476
1477         u8         ether_stats_pkts256to511octets_high[0x20];
1478
1479         u8         ether_stats_pkts256to511octets_low[0x20];
1480
1481         u8         ether_stats_pkts512to1023octets_high[0x20];
1482
1483         u8         ether_stats_pkts512to1023octets_low[0x20];
1484
1485         u8         ether_stats_pkts1024to1518octets_high[0x20];
1486
1487         u8         ether_stats_pkts1024to1518octets_low[0x20];
1488
1489         u8         ether_stats_pkts1519to2047octets_high[0x20];
1490
1491         u8         ether_stats_pkts1519to2047octets_low[0x20];
1492
1493         u8         ether_stats_pkts2048to4095octets_high[0x20];
1494
1495         u8         ether_stats_pkts2048to4095octets_low[0x20];
1496
1497         u8         ether_stats_pkts4096to8191octets_high[0x20];
1498
1499         u8         ether_stats_pkts4096to8191octets_low[0x20];
1500
1501         u8         ether_stats_pkts8192to10239octets_high[0x20];
1502
1503         u8         ether_stats_pkts8192to10239octets_low[0x20];
1504
1505         u8         reserved_at_540[0x280];
1506 };
1507
1508 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1509         u8         if_in_octets_high[0x20];
1510
1511         u8         if_in_octets_low[0x20];
1512
1513         u8         if_in_ucast_pkts_high[0x20];
1514
1515         u8         if_in_ucast_pkts_low[0x20];
1516
1517         u8         if_in_discards_high[0x20];
1518
1519         u8         if_in_discards_low[0x20];
1520
1521         u8         if_in_errors_high[0x20];
1522
1523         u8         if_in_errors_low[0x20];
1524
1525         u8         if_in_unknown_protos_high[0x20];
1526
1527         u8         if_in_unknown_protos_low[0x20];
1528
1529         u8         if_out_octets_high[0x20];
1530
1531         u8         if_out_octets_low[0x20];
1532
1533         u8         if_out_ucast_pkts_high[0x20];
1534
1535         u8         if_out_ucast_pkts_low[0x20];
1536
1537         u8         if_out_discards_high[0x20];
1538
1539         u8         if_out_discards_low[0x20];
1540
1541         u8         if_out_errors_high[0x20];
1542
1543         u8         if_out_errors_low[0x20];
1544
1545         u8         if_in_multicast_pkts_high[0x20];
1546
1547         u8         if_in_multicast_pkts_low[0x20];
1548
1549         u8         if_in_broadcast_pkts_high[0x20];
1550
1551         u8         if_in_broadcast_pkts_low[0x20];
1552
1553         u8         if_out_multicast_pkts_high[0x20];
1554
1555         u8         if_out_multicast_pkts_low[0x20];
1556
1557         u8         if_out_broadcast_pkts_high[0x20];
1558
1559         u8         if_out_broadcast_pkts_low[0x20];
1560
1561         u8         reserved_at_340[0x480];
1562 };
1563
1564 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1565         u8         a_frames_transmitted_ok_high[0x20];
1566
1567         u8         a_frames_transmitted_ok_low[0x20];
1568
1569         u8         a_frames_received_ok_high[0x20];
1570
1571         u8         a_frames_received_ok_low[0x20];
1572
1573         u8         a_frame_check_sequence_errors_high[0x20];
1574
1575         u8         a_frame_check_sequence_errors_low[0x20];
1576
1577         u8         a_alignment_errors_high[0x20];
1578
1579         u8         a_alignment_errors_low[0x20];
1580
1581         u8         a_octets_transmitted_ok_high[0x20];
1582
1583         u8         a_octets_transmitted_ok_low[0x20];
1584
1585         u8         a_octets_received_ok_high[0x20];
1586
1587         u8         a_octets_received_ok_low[0x20];
1588
1589         u8         a_multicast_frames_xmitted_ok_high[0x20];
1590
1591         u8         a_multicast_frames_xmitted_ok_low[0x20];
1592
1593         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1594
1595         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1596
1597         u8         a_multicast_frames_received_ok_high[0x20];
1598
1599         u8         a_multicast_frames_received_ok_low[0x20];
1600
1601         u8         a_broadcast_frames_received_ok_high[0x20];
1602
1603         u8         a_broadcast_frames_received_ok_low[0x20];
1604
1605         u8         a_in_range_length_errors_high[0x20];
1606
1607         u8         a_in_range_length_errors_low[0x20];
1608
1609         u8         a_out_of_range_length_field_high[0x20];
1610
1611         u8         a_out_of_range_length_field_low[0x20];
1612
1613         u8         a_frame_too_long_errors_high[0x20];
1614
1615         u8         a_frame_too_long_errors_low[0x20];
1616
1617         u8         a_symbol_error_during_carrier_high[0x20];
1618
1619         u8         a_symbol_error_during_carrier_low[0x20];
1620
1621         u8         a_mac_control_frames_transmitted_high[0x20];
1622
1623         u8         a_mac_control_frames_transmitted_low[0x20];
1624
1625         u8         a_mac_control_frames_received_high[0x20];
1626
1627         u8         a_mac_control_frames_received_low[0x20];
1628
1629         u8         a_unsupported_opcodes_received_high[0x20];
1630
1631         u8         a_unsupported_opcodes_received_low[0x20];
1632
1633         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1634
1635         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1636
1637         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1638
1639         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1640
1641         u8         reserved_at_4c0[0x300];
1642 };
1643
1644 struct mlx5_ifc_cmd_inter_comp_event_bits {
1645         u8         command_completion_vector[0x20];
1646
1647         u8         reserved_at_20[0xc0];
1648 };
1649
1650 struct mlx5_ifc_stall_vl_event_bits {
1651         u8         reserved_at_0[0x18];
1652         u8         port_num[0x1];
1653         u8         reserved_at_19[0x3];
1654         u8         vl[0x4];
1655
1656         u8         reserved_at_20[0xa0];
1657 };
1658
1659 struct mlx5_ifc_db_bf_congestion_event_bits {
1660         u8         event_subtype[0x8];
1661         u8         reserved_at_8[0x8];
1662         u8         congestion_level[0x8];
1663         u8         reserved_at_18[0x8];
1664
1665         u8         reserved_at_20[0xa0];
1666 };
1667
1668 struct mlx5_ifc_gpio_event_bits {
1669         u8         reserved_at_0[0x60];
1670
1671         u8         gpio_event_hi[0x20];
1672
1673         u8         gpio_event_lo[0x20];
1674
1675         u8         reserved_at_a0[0x40];
1676 };
1677
1678 struct mlx5_ifc_port_state_change_event_bits {
1679         u8         reserved_at_0[0x40];
1680
1681         u8         port_num[0x4];
1682         u8         reserved_at_44[0x1c];
1683
1684         u8         reserved_at_60[0x80];
1685 };
1686
1687 struct mlx5_ifc_dropped_packet_logged_bits {
1688         u8         reserved_at_0[0xe0];
1689 };
1690
1691 enum {
1692         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1693         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1694 };
1695
1696 struct mlx5_ifc_cq_error_bits {
1697         u8         reserved_at_0[0x8];
1698         u8         cqn[0x18];
1699
1700         u8         reserved_at_20[0x20];
1701
1702         u8         reserved_at_40[0x18];
1703         u8         syndrome[0x8];
1704
1705         u8         reserved_at_60[0x80];
1706 };
1707
1708 struct mlx5_ifc_rdma_page_fault_event_bits {
1709         u8         bytes_committed[0x20];
1710
1711         u8         r_key[0x20];
1712
1713         u8         reserved_at_40[0x10];
1714         u8         packet_len[0x10];
1715
1716         u8         rdma_op_len[0x20];
1717
1718         u8         rdma_va[0x40];
1719
1720         u8         reserved_at_c0[0x5];
1721         u8         rdma[0x1];
1722         u8         write[0x1];
1723         u8         requestor[0x1];
1724         u8         qp_number[0x18];
1725 };
1726
1727 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1728         u8         bytes_committed[0x20];
1729
1730         u8         reserved_at_20[0x10];
1731         u8         wqe_index[0x10];
1732
1733         u8         reserved_at_40[0x10];
1734         u8         len[0x10];
1735
1736         u8         reserved_at_60[0x60];
1737
1738         u8         reserved_at_c0[0x5];
1739         u8         rdma[0x1];
1740         u8         write_read[0x1];
1741         u8         requestor[0x1];
1742         u8         qpn[0x18];
1743 };
1744
1745 struct mlx5_ifc_qp_events_bits {
1746         u8         reserved_at_0[0xa0];
1747
1748         u8         type[0x8];
1749         u8         reserved_at_a8[0x18];
1750
1751         u8         reserved_at_c0[0x8];
1752         u8         qpn_rqn_sqn[0x18];
1753 };
1754
1755 struct mlx5_ifc_dct_events_bits {
1756         u8         reserved_at_0[0xc0];
1757
1758         u8         reserved_at_c0[0x8];
1759         u8         dct_number[0x18];
1760 };
1761
1762 struct mlx5_ifc_comp_event_bits {
1763         u8         reserved_at_0[0xc0];
1764
1765         u8         reserved_at_c0[0x8];
1766         u8         cq_number[0x18];
1767 };
1768
1769 enum {
1770         MLX5_QPC_STATE_RST        = 0x0,
1771         MLX5_QPC_STATE_INIT       = 0x1,
1772         MLX5_QPC_STATE_RTR        = 0x2,
1773         MLX5_QPC_STATE_RTS        = 0x3,
1774         MLX5_QPC_STATE_SQER       = 0x4,
1775         MLX5_QPC_STATE_ERR        = 0x6,
1776         MLX5_QPC_STATE_SQD        = 0x7,
1777         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1778 };
1779
1780 enum {
1781         MLX5_QPC_ST_RC            = 0x0,
1782         MLX5_QPC_ST_UC            = 0x1,
1783         MLX5_QPC_ST_UD            = 0x2,
1784         MLX5_QPC_ST_XRC           = 0x3,
1785         MLX5_QPC_ST_DCI           = 0x5,
1786         MLX5_QPC_ST_QP0           = 0x7,
1787         MLX5_QPC_ST_QP1           = 0x8,
1788         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1789         MLX5_QPC_ST_REG_UMR       = 0xc,
1790 };
1791
1792 enum {
1793         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1794         MLX5_QPC_PM_STATE_REARM     = 0x1,
1795         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1796         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1797 };
1798
1799 enum {
1800         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1801         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1802 };
1803
1804 enum {
1805         MLX5_QPC_MTU_256_BYTES        = 0x1,
1806         MLX5_QPC_MTU_512_BYTES        = 0x2,
1807         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1808         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1809         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1810         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1811 };
1812
1813 enum {
1814         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1815         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1816         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1817         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1818         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1819         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1820         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1821         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1822 };
1823
1824 enum {
1825         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1826         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1827         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1828 };
1829
1830 enum {
1831         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1832         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1833         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1834 };
1835
1836 struct mlx5_ifc_qpc_bits {
1837         u8         state[0x4];
1838         u8         reserved_at_4[0x4];
1839         u8         st[0x8];
1840         u8         reserved_at_10[0x3];
1841         u8         pm_state[0x2];
1842         u8         reserved_at_15[0x7];
1843         u8         end_padding_mode[0x2];
1844         u8         reserved_at_1e[0x2];
1845
1846         u8         wq_signature[0x1];
1847         u8         block_lb_mc[0x1];
1848         u8         atomic_like_write_en[0x1];
1849         u8         latency_sensitive[0x1];
1850         u8         reserved_at_24[0x1];
1851         u8         drain_sigerr[0x1];
1852         u8         reserved_at_26[0x2];
1853         u8         pd[0x18];
1854
1855         u8         mtu[0x3];
1856         u8         log_msg_max[0x5];
1857         u8         reserved_at_48[0x1];
1858         u8         log_rq_size[0x4];
1859         u8         log_rq_stride[0x3];
1860         u8         no_sq[0x1];
1861         u8         log_sq_size[0x4];
1862         u8         reserved_at_55[0x6];
1863         u8         rlky[0x1];
1864         u8         ulp_stateless_offload_mode[0x4];
1865
1866         u8         counter_set_id[0x8];
1867         u8         uar_page[0x18];
1868
1869         u8         reserved_at_80[0x8];
1870         u8         user_index[0x18];
1871
1872         u8         reserved_at_a0[0x3];
1873         u8         log_page_size[0x5];
1874         u8         remote_qpn[0x18];
1875
1876         struct mlx5_ifc_ads_bits primary_address_path;
1877
1878         struct mlx5_ifc_ads_bits secondary_address_path;
1879
1880         u8         log_ack_req_freq[0x4];
1881         u8         reserved_at_384[0x4];
1882         u8         log_sra_max[0x3];
1883         u8         reserved_at_38b[0x2];
1884         u8         retry_count[0x3];
1885         u8         rnr_retry[0x3];
1886         u8         reserved_at_393[0x1];
1887         u8         fre[0x1];
1888         u8         cur_rnr_retry[0x3];
1889         u8         cur_retry_count[0x3];
1890         u8         reserved_at_39b[0x5];
1891
1892         u8         reserved_at_3a0[0x20];
1893
1894         u8         reserved_at_3c0[0x8];
1895         u8         next_send_psn[0x18];
1896
1897         u8         reserved_at_3e0[0x8];
1898         u8         cqn_snd[0x18];
1899
1900         u8         reserved_at_400[0x40];
1901
1902         u8         reserved_at_440[0x8];
1903         u8         last_acked_psn[0x18];
1904
1905         u8         reserved_at_460[0x8];
1906         u8         ssn[0x18];
1907
1908         u8         reserved_at_480[0x8];
1909         u8         log_rra_max[0x3];
1910         u8         reserved_at_48b[0x1];
1911         u8         atomic_mode[0x4];
1912         u8         rre[0x1];
1913         u8         rwe[0x1];
1914         u8         rae[0x1];
1915         u8         reserved_at_493[0x1];
1916         u8         page_offset[0x6];
1917         u8         reserved_at_49a[0x3];
1918         u8         cd_slave_receive[0x1];
1919         u8         cd_slave_send[0x1];
1920         u8         cd_master[0x1];
1921
1922         u8         reserved_at_4a0[0x3];
1923         u8         min_rnr_nak[0x5];
1924         u8         next_rcv_psn[0x18];
1925
1926         u8         reserved_at_4c0[0x8];
1927         u8         xrcd[0x18];
1928
1929         u8         reserved_at_4e0[0x8];
1930         u8         cqn_rcv[0x18];
1931
1932         u8         dbr_addr[0x40];
1933
1934         u8         q_key[0x20];
1935
1936         u8         reserved_at_560[0x5];
1937         u8         rq_type[0x3];
1938         u8         srqn_rmpn[0x18];
1939
1940         u8         reserved_at_580[0x8];
1941         u8         rmsn[0x18];
1942
1943         u8         hw_sq_wqebb_counter[0x10];
1944         u8         sw_sq_wqebb_counter[0x10];
1945
1946         u8         hw_rq_counter[0x20];
1947
1948         u8         sw_rq_counter[0x20];
1949
1950         u8         reserved_at_600[0x20];
1951
1952         u8         reserved_at_620[0xf];
1953         u8         cgs[0x1];
1954         u8         cs_req[0x8];
1955         u8         cs_res[0x8];
1956
1957         u8         dc_access_key[0x40];
1958
1959         u8         reserved_at_680[0xc0];
1960 };
1961
1962 struct mlx5_ifc_roce_addr_layout_bits {
1963         u8         source_l3_address[16][0x8];
1964
1965         u8         reserved_at_80[0x3];
1966         u8         vlan_valid[0x1];
1967         u8         vlan_id[0xc];
1968         u8         source_mac_47_32[0x10];
1969
1970         u8         source_mac_31_0[0x20];
1971
1972         u8         reserved_at_c0[0x14];
1973         u8         roce_l3_type[0x4];
1974         u8         roce_version[0x8];
1975
1976         u8         reserved_at_e0[0x20];
1977 };
1978
1979 union mlx5_ifc_hca_cap_union_bits {
1980         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1981         struct mlx5_ifc_odp_cap_bits odp_cap;
1982         struct mlx5_ifc_atomic_caps_bits atomic_caps;
1983         struct mlx5_ifc_roce_cap_bits roce_cap;
1984         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1985         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1986         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
1987         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
1988         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
1989         u8         reserved_at_0[0x8000];
1990 };
1991
1992 enum {
1993         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
1994         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
1995         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
1996 };
1997
1998 struct mlx5_ifc_flow_context_bits {
1999         u8         reserved_at_0[0x20];
2000
2001         u8         group_id[0x20];
2002
2003         u8         reserved_at_40[0x8];
2004         u8         flow_tag[0x18];
2005
2006         u8         reserved_at_60[0x10];
2007         u8         action[0x10];
2008
2009         u8         reserved_at_80[0x8];
2010         u8         destination_list_size[0x18];
2011
2012         u8         reserved_at_a0[0x160];
2013
2014         struct mlx5_ifc_fte_match_param_bits match_value;
2015
2016         u8         reserved_at_1200[0x600];
2017
2018         struct mlx5_ifc_dest_format_struct_bits destination[0];
2019 };
2020
2021 enum {
2022         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2023         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2024 };
2025
2026 struct mlx5_ifc_xrc_srqc_bits {
2027         u8         state[0x4];
2028         u8         log_xrc_srq_size[0x4];
2029         u8         reserved_at_8[0x18];
2030
2031         u8         wq_signature[0x1];
2032         u8         cont_srq[0x1];
2033         u8         reserved_at_22[0x1];
2034         u8         rlky[0x1];
2035         u8         basic_cyclic_rcv_wqe[0x1];
2036         u8         log_rq_stride[0x3];
2037         u8         xrcd[0x18];
2038
2039         u8         page_offset[0x6];
2040         u8         reserved_at_46[0x2];
2041         u8         cqn[0x18];
2042
2043         u8         reserved_at_60[0x20];
2044
2045         u8         user_index_equal_xrc_srqn[0x1];
2046         u8         reserved_at_81[0x1];
2047         u8         log_page_size[0x6];
2048         u8         user_index[0x18];
2049
2050         u8         reserved_at_a0[0x20];
2051
2052         u8         reserved_at_c0[0x8];
2053         u8         pd[0x18];
2054
2055         u8         lwm[0x10];
2056         u8         wqe_cnt[0x10];
2057
2058         u8         reserved_at_100[0x40];
2059
2060         u8         db_record_addr_h[0x20];
2061
2062         u8         db_record_addr_l[0x1e];
2063         u8         reserved_at_17e[0x2];
2064
2065         u8         reserved_at_180[0x80];
2066 };
2067
2068 struct mlx5_ifc_traffic_counter_bits {
2069         u8         packets[0x40];
2070
2071         u8         octets[0x40];
2072 };
2073
2074 struct mlx5_ifc_tisc_bits {
2075         u8         reserved_at_0[0xc];
2076         u8         prio[0x4];
2077         u8         reserved_at_10[0x10];
2078
2079         u8         reserved_at_20[0x100];
2080
2081         u8         reserved_at_120[0x8];
2082         u8         transport_domain[0x18];
2083
2084         u8         reserved_at_140[0x3c0];
2085 };
2086
2087 enum {
2088         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2089         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2090 };
2091
2092 enum {
2093         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2094         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2095 };
2096
2097 enum {
2098         MLX5_RX_HASH_FN_NONE           = 0x0,
2099         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2100         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2101 };
2102
2103 enum {
2104         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2105         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2106 };
2107
2108 struct mlx5_ifc_tirc_bits {
2109         u8         reserved_at_0[0x20];
2110
2111         u8         disp_type[0x4];
2112         u8         reserved_at_24[0x1c];
2113
2114         u8         reserved_at_40[0x40];
2115
2116         u8         reserved_at_80[0x4];
2117         u8         lro_timeout_period_usecs[0x10];
2118         u8         lro_enable_mask[0x4];
2119         u8         lro_max_ip_payload_size[0x8];
2120
2121         u8         reserved_at_a0[0x40];
2122
2123         u8         reserved_at_e0[0x8];
2124         u8         inline_rqn[0x18];
2125
2126         u8         rx_hash_symmetric[0x1];
2127         u8         reserved_at_101[0x1];
2128         u8         tunneled_offload_en[0x1];
2129         u8         reserved_at_103[0x5];
2130         u8         indirect_table[0x18];
2131
2132         u8         rx_hash_fn[0x4];
2133         u8         reserved_at_124[0x2];
2134         u8         self_lb_block[0x2];
2135         u8         transport_domain[0x18];
2136
2137         u8         rx_hash_toeplitz_key[10][0x20];
2138
2139         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2140
2141         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2142
2143         u8         reserved_at_2c0[0x4c0];
2144 };
2145
2146 enum {
2147         MLX5_SRQC_STATE_GOOD   = 0x0,
2148         MLX5_SRQC_STATE_ERROR  = 0x1,
2149 };
2150
2151 struct mlx5_ifc_srqc_bits {
2152         u8         state[0x4];
2153         u8         log_srq_size[0x4];
2154         u8         reserved_at_8[0x18];
2155
2156         u8         wq_signature[0x1];
2157         u8         cont_srq[0x1];
2158         u8         reserved_at_22[0x1];
2159         u8         rlky[0x1];
2160         u8         reserved_at_24[0x1];
2161         u8         log_rq_stride[0x3];
2162         u8         xrcd[0x18];
2163
2164         u8         page_offset[0x6];
2165         u8         reserved_at_46[0x2];
2166         u8         cqn[0x18];
2167
2168         u8         reserved_at_60[0x20];
2169
2170         u8         reserved_at_80[0x2];
2171         u8         log_page_size[0x6];
2172         u8         reserved_at_88[0x18];
2173
2174         u8         reserved_at_a0[0x20];
2175
2176         u8         reserved_at_c0[0x8];
2177         u8         pd[0x18];
2178
2179         u8         lwm[0x10];
2180         u8         wqe_cnt[0x10];
2181
2182         u8         reserved_at_100[0x40];
2183
2184         u8         dbr_addr[0x40];
2185
2186         u8         reserved_at_180[0x80];
2187 };
2188
2189 enum {
2190         MLX5_SQC_STATE_RST  = 0x0,
2191         MLX5_SQC_STATE_RDY  = 0x1,
2192         MLX5_SQC_STATE_ERR  = 0x3,
2193 };
2194
2195 struct mlx5_ifc_sqc_bits {
2196         u8         rlky[0x1];
2197         u8         cd_master[0x1];
2198         u8         fre[0x1];
2199         u8         flush_in_error_en[0x1];
2200         u8         reserved_at_4[0x4];
2201         u8         state[0x4];
2202         u8         reserved_at_c[0x14];
2203
2204         u8         reserved_at_20[0x8];
2205         u8         user_index[0x18];
2206
2207         u8         reserved_at_40[0x8];
2208         u8         cqn[0x18];
2209
2210         u8         reserved_at_60[0xa0];
2211
2212         u8         tis_lst_sz[0x10];
2213         u8         reserved_at_110[0x10];
2214
2215         u8         reserved_at_120[0x40];
2216
2217         u8         reserved_at_160[0x8];
2218         u8         tis_num_0[0x18];
2219
2220         struct mlx5_ifc_wq_bits wq;
2221 };
2222
2223 struct mlx5_ifc_rqtc_bits {
2224         u8         reserved_at_0[0xa0];
2225
2226         u8         reserved_at_a0[0x10];
2227         u8         rqt_max_size[0x10];
2228
2229         u8         reserved_at_c0[0x10];
2230         u8         rqt_actual_size[0x10];
2231
2232         u8         reserved_at_e0[0x6a0];
2233
2234         struct mlx5_ifc_rq_num_bits rq_num[0];
2235 };
2236
2237 enum {
2238         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2239         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2240 };
2241
2242 enum {
2243         MLX5_RQC_STATE_RST  = 0x0,
2244         MLX5_RQC_STATE_RDY  = 0x1,
2245         MLX5_RQC_STATE_ERR  = 0x3,
2246 };
2247
2248 struct mlx5_ifc_rqc_bits {
2249         u8         rlky[0x1];
2250         u8         reserved_at_1[0x2];
2251         u8         vsd[0x1];
2252         u8         mem_rq_type[0x4];
2253         u8         state[0x4];
2254         u8         reserved_at_c[0x1];
2255         u8         flush_in_error_en[0x1];
2256         u8         reserved_at_e[0x12];
2257
2258         u8         reserved_at_20[0x8];
2259         u8         user_index[0x18];
2260
2261         u8         reserved_at_40[0x8];
2262         u8         cqn[0x18];
2263
2264         u8         counter_set_id[0x8];
2265         u8         reserved_at_68[0x18];
2266
2267         u8         reserved_at_80[0x8];
2268         u8         rmpn[0x18];
2269
2270         u8         reserved_at_a0[0xe0];
2271
2272         struct mlx5_ifc_wq_bits wq;
2273 };
2274
2275 enum {
2276         MLX5_RMPC_STATE_RDY  = 0x1,
2277         MLX5_RMPC_STATE_ERR  = 0x3,
2278 };
2279
2280 struct mlx5_ifc_rmpc_bits {
2281         u8         reserved_at_0[0x8];
2282         u8         state[0x4];
2283         u8         reserved_at_c[0x14];
2284
2285         u8         basic_cyclic_rcv_wqe[0x1];
2286         u8         reserved_at_21[0x1f];
2287
2288         u8         reserved_at_40[0x140];
2289
2290         struct mlx5_ifc_wq_bits wq;
2291 };
2292
2293 struct mlx5_ifc_nic_vport_context_bits {
2294         u8         reserved_at_0[0x1f];
2295         u8         roce_en[0x1];
2296
2297         u8         arm_change_event[0x1];
2298         u8         reserved_at_21[0x1a];
2299         u8         event_on_mtu[0x1];
2300         u8         event_on_promisc_change[0x1];
2301         u8         event_on_vlan_change[0x1];
2302         u8         event_on_mc_address_change[0x1];
2303         u8         event_on_uc_address_change[0x1];
2304
2305         u8         reserved_at_40[0xf0];
2306
2307         u8         mtu[0x10];
2308
2309         u8         system_image_guid[0x40];
2310         u8         port_guid[0x40];
2311         u8         node_guid[0x40];
2312
2313         u8         reserved_at_200[0x140];
2314         u8         qkey_violation_counter[0x10];
2315         u8         reserved_at_350[0x430];
2316
2317         u8         promisc_uc[0x1];
2318         u8         promisc_mc[0x1];
2319         u8         promisc_all[0x1];
2320         u8         reserved_at_783[0x2];
2321         u8         allowed_list_type[0x3];
2322         u8         reserved_at_788[0xc];
2323         u8         allowed_list_size[0xc];
2324
2325         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2326
2327         u8         reserved_at_7e0[0x20];
2328
2329         u8         current_uc_mac_address[0][0x40];
2330 };
2331
2332 enum {
2333         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2334         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2335         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2336 };
2337
2338 struct mlx5_ifc_mkc_bits {
2339         u8         reserved_at_0[0x1];
2340         u8         free[0x1];
2341         u8         reserved_at_2[0xd];
2342         u8         small_fence_on_rdma_read_response[0x1];
2343         u8         umr_en[0x1];
2344         u8         a[0x1];
2345         u8         rw[0x1];
2346         u8         rr[0x1];
2347         u8         lw[0x1];
2348         u8         lr[0x1];
2349         u8         access_mode[0x2];
2350         u8         reserved_at_18[0x8];
2351
2352         u8         qpn[0x18];
2353         u8         mkey_7_0[0x8];
2354
2355         u8         reserved_at_40[0x20];
2356
2357         u8         length64[0x1];
2358         u8         bsf_en[0x1];
2359         u8         sync_umr[0x1];
2360         u8         reserved_at_63[0x2];
2361         u8         expected_sigerr_count[0x1];
2362         u8         reserved_at_66[0x1];
2363         u8         en_rinval[0x1];
2364         u8         pd[0x18];
2365
2366         u8         start_addr[0x40];
2367
2368         u8         len[0x40];
2369
2370         u8         bsf_octword_size[0x20];
2371
2372         u8         reserved_at_120[0x80];
2373
2374         u8         translations_octword_size[0x20];
2375
2376         u8         reserved_at_1c0[0x1b];
2377         u8         log_page_size[0x5];
2378
2379         u8         reserved_at_1e0[0x20];
2380 };
2381
2382 struct mlx5_ifc_pkey_bits {
2383         u8         reserved_at_0[0x10];
2384         u8         pkey[0x10];
2385 };
2386
2387 struct mlx5_ifc_array128_auto_bits {
2388         u8         array128_auto[16][0x8];
2389 };
2390
2391 struct mlx5_ifc_hca_vport_context_bits {
2392         u8         field_select[0x20];
2393
2394         u8         reserved_at_20[0xe0];
2395
2396         u8         sm_virt_aware[0x1];
2397         u8         has_smi[0x1];
2398         u8         has_raw[0x1];
2399         u8         grh_required[0x1];
2400         u8         reserved_at_104[0xc];
2401         u8         port_physical_state[0x4];
2402         u8         vport_state_policy[0x4];
2403         u8         port_state[0x4];
2404         u8         vport_state[0x4];
2405
2406         u8         reserved_at_120[0x20];
2407
2408         u8         system_image_guid[0x40];
2409
2410         u8         port_guid[0x40];
2411
2412         u8         node_guid[0x40];
2413
2414         u8         cap_mask1[0x20];
2415
2416         u8         cap_mask1_field_select[0x20];
2417
2418         u8         cap_mask2[0x20];
2419
2420         u8         cap_mask2_field_select[0x20];
2421
2422         u8         reserved_at_280[0x80];
2423
2424         u8         lid[0x10];
2425         u8         reserved_at_310[0x4];
2426         u8         init_type_reply[0x4];
2427         u8         lmc[0x3];
2428         u8         subnet_timeout[0x5];
2429
2430         u8         sm_lid[0x10];
2431         u8         sm_sl[0x4];
2432         u8         reserved_at_334[0xc];
2433
2434         u8         qkey_violation_counter[0x10];
2435         u8         pkey_violation_counter[0x10];
2436
2437         u8         reserved_at_360[0xca0];
2438 };
2439
2440 struct mlx5_ifc_esw_vport_context_bits {
2441         u8         reserved_at_0[0x3];
2442         u8         vport_svlan_strip[0x1];
2443         u8         vport_cvlan_strip[0x1];
2444         u8         vport_svlan_insert[0x1];
2445         u8         vport_cvlan_insert[0x2];
2446         u8         reserved_at_8[0x18];
2447
2448         u8         reserved_at_20[0x20];
2449
2450         u8         svlan_cfi[0x1];
2451         u8         svlan_pcp[0x3];
2452         u8         svlan_id[0xc];
2453         u8         cvlan_cfi[0x1];
2454         u8         cvlan_pcp[0x3];
2455         u8         cvlan_id[0xc];
2456
2457         u8         reserved_at_60[0x7a0];
2458 };
2459
2460 enum {
2461         MLX5_EQC_STATUS_OK                = 0x0,
2462         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2463 };
2464
2465 enum {
2466         MLX5_EQC_ST_ARMED  = 0x9,
2467         MLX5_EQC_ST_FIRED  = 0xa,
2468 };
2469
2470 struct mlx5_ifc_eqc_bits {
2471         u8         status[0x4];
2472         u8         reserved_at_4[0x9];
2473         u8         ec[0x1];
2474         u8         oi[0x1];
2475         u8         reserved_at_f[0x5];
2476         u8         st[0x4];
2477         u8         reserved_at_18[0x8];
2478
2479         u8         reserved_at_20[0x20];
2480
2481         u8         reserved_at_40[0x14];
2482         u8         page_offset[0x6];
2483         u8         reserved_at_5a[0x6];
2484
2485         u8         reserved_at_60[0x3];
2486         u8         log_eq_size[0x5];
2487         u8         uar_page[0x18];
2488
2489         u8         reserved_at_80[0x20];
2490
2491         u8         reserved_at_a0[0x18];
2492         u8         intr[0x8];
2493
2494         u8         reserved_at_c0[0x3];
2495         u8         log_page_size[0x5];
2496         u8         reserved_at_c8[0x18];
2497
2498         u8         reserved_at_e0[0x60];
2499
2500         u8         reserved_at_140[0x8];
2501         u8         consumer_counter[0x18];
2502
2503         u8         reserved_at_160[0x8];
2504         u8         producer_counter[0x18];
2505
2506         u8         reserved_at_180[0x80];
2507 };
2508
2509 enum {
2510         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2511         MLX5_DCTC_STATE_DRAINING  = 0x1,
2512         MLX5_DCTC_STATE_DRAINED   = 0x2,
2513 };
2514
2515 enum {
2516         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2517         MLX5_DCTC_CS_RES_NA         = 0x1,
2518         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2519 };
2520
2521 enum {
2522         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2523         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2524         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2525         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2526         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2527 };
2528
2529 struct mlx5_ifc_dctc_bits {
2530         u8         reserved_at_0[0x4];
2531         u8         state[0x4];
2532         u8         reserved_at_8[0x18];
2533
2534         u8         reserved_at_20[0x8];
2535         u8         user_index[0x18];
2536
2537         u8         reserved_at_40[0x8];
2538         u8         cqn[0x18];
2539
2540         u8         counter_set_id[0x8];
2541         u8         atomic_mode[0x4];
2542         u8         rre[0x1];
2543         u8         rwe[0x1];
2544         u8         rae[0x1];
2545         u8         atomic_like_write_en[0x1];
2546         u8         latency_sensitive[0x1];
2547         u8         rlky[0x1];
2548         u8         free_ar[0x1];
2549         u8         reserved_at_73[0xd];
2550
2551         u8         reserved_at_80[0x8];
2552         u8         cs_res[0x8];
2553         u8         reserved_at_90[0x3];
2554         u8         min_rnr_nak[0x5];
2555         u8         reserved_at_98[0x8];
2556
2557         u8         reserved_at_a0[0x8];
2558         u8         srqn[0x18];
2559
2560         u8         reserved_at_c0[0x8];
2561         u8         pd[0x18];
2562
2563         u8         tclass[0x8];
2564         u8         reserved_at_e8[0x4];
2565         u8         flow_label[0x14];
2566
2567         u8         dc_access_key[0x40];
2568
2569         u8         reserved_at_140[0x5];
2570         u8         mtu[0x3];
2571         u8         port[0x8];
2572         u8         pkey_index[0x10];
2573
2574         u8         reserved_at_160[0x8];
2575         u8         my_addr_index[0x8];
2576         u8         reserved_at_170[0x8];
2577         u8         hop_limit[0x8];
2578
2579         u8         dc_access_key_violation_count[0x20];
2580
2581         u8         reserved_at_1a0[0x14];
2582         u8         dei_cfi[0x1];
2583         u8         eth_prio[0x3];
2584         u8         ecn[0x2];
2585         u8         dscp[0x6];
2586
2587         u8         reserved_at_1c0[0x40];
2588 };
2589
2590 enum {
2591         MLX5_CQC_STATUS_OK             = 0x0,
2592         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2593         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2594 };
2595
2596 enum {
2597         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2598         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2599 };
2600
2601 enum {
2602         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2603         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2604         MLX5_CQC_ST_FIRED                                 = 0xa,
2605 };
2606
2607 struct mlx5_ifc_cqc_bits {
2608         u8         status[0x4];
2609         u8         reserved_at_4[0x4];
2610         u8         cqe_sz[0x3];
2611         u8         cc[0x1];
2612         u8         reserved_at_c[0x1];
2613         u8         scqe_break_moderation_en[0x1];
2614         u8         oi[0x1];
2615         u8         reserved_at_f[0x2];
2616         u8         cqe_zip_en[0x1];
2617         u8         mini_cqe_res_format[0x2];
2618         u8         st[0x4];
2619         u8         reserved_at_18[0x8];
2620
2621         u8         reserved_at_20[0x20];
2622
2623         u8         reserved_at_40[0x14];
2624         u8         page_offset[0x6];
2625         u8         reserved_at_5a[0x6];
2626
2627         u8         reserved_at_60[0x3];
2628         u8         log_cq_size[0x5];
2629         u8         uar_page[0x18];
2630
2631         u8         reserved_at_80[0x4];
2632         u8         cq_period[0xc];
2633         u8         cq_max_count[0x10];
2634
2635         u8         reserved_at_a0[0x18];
2636         u8         c_eqn[0x8];
2637
2638         u8         reserved_at_c0[0x3];
2639         u8         log_page_size[0x5];
2640         u8         reserved_at_c8[0x18];
2641
2642         u8         reserved_at_e0[0x20];
2643
2644         u8         reserved_at_100[0x8];
2645         u8         last_notified_index[0x18];
2646
2647         u8         reserved_at_120[0x8];
2648         u8         last_solicit_index[0x18];
2649
2650         u8         reserved_at_140[0x8];
2651         u8         consumer_counter[0x18];
2652
2653         u8         reserved_at_160[0x8];
2654         u8         producer_counter[0x18];
2655
2656         u8         reserved_at_180[0x40];
2657
2658         u8         dbr_addr[0x40];
2659 };
2660
2661 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2662         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2663         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2664         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2665         u8         reserved_at_0[0x800];
2666 };
2667
2668 struct mlx5_ifc_query_adapter_param_block_bits {
2669         u8         reserved_at_0[0xc0];
2670
2671         u8         reserved_at_c0[0x8];
2672         u8         ieee_vendor_id[0x18];
2673
2674         u8         reserved_at_e0[0x10];
2675         u8         vsd_vendor_id[0x10];
2676
2677         u8         vsd[208][0x8];
2678
2679         u8         vsd_contd_psid[16][0x8];
2680 };
2681
2682 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2683         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2684         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2685         u8         reserved_at_0[0x20];
2686 };
2687
2688 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2689         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2690         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2691         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2692         u8         reserved_at_0[0x20];
2693 };
2694
2695 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2696         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2697         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2698         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2699         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2700         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2701         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2702         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2703         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2704         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2705         u8         reserved_at_0[0x7c0];
2706 };
2707
2708 union mlx5_ifc_event_auto_bits {
2709         struct mlx5_ifc_comp_event_bits comp_event;
2710         struct mlx5_ifc_dct_events_bits dct_events;
2711         struct mlx5_ifc_qp_events_bits qp_events;
2712         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2713         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2714         struct mlx5_ifc_cq_error_bits cq_error;
2715         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2716         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2717         struct mlx5_ifc_gpio_event_bits gpio_event;
2718         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2719         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2720         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2721         u8         reserved_at_0[0xe0];
2722 };
2723
2724 struct mlx5_ifc_health_buffer_bits {
2725         u8         reserved_at_0[0x100];
2726
2727         u8         assert_existptr[0x20];
2728
2729         u8         assert_callra[0x20];
2730
2731         u8         reserved_at_140[0x40];
2732
2733         u8         fw_version[0x20];
2734
2735         u8         hw_id[0x20];
2736
2737         u8         reserved_at_1c0[0x20];
2738
2739         u8         irisc_index[0x8];
2740         u8         synd[0x8];
2741         u8         ext_synd[0x10];
2742 };
2743
2744 struct mlx5_ifc_register_loopback_control_bits {
2745         u8         no_lb[0x1];
2746         u8         reserved_at_1[0x7];
2747         u8         port[0x8];
2748         u8         reserved_at_10[0x10];
2749
2750         u8         reserved_at_20[0x60];
2751 };
2752
2753 struct mlx5_ifc_teardown_hca_out_bits {
2754         u8         status[0x8];
2755         u8         reserved_at_8[0x18];
2756
2757         u8         syndrome[0x20];
2758
2759         u8         reserved_at_40[0x40];
2760 };
2761
2762 enum {
2763         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
2764         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
2765 };
2766
2767 struct mlx5_ifc_teardown_hca_in_bits {
2768         u8         opcode[0x10];
2769         u8         reserved_at_10[0x10];
2770
2771         u8         reserved_at_20[0x10];
2772         u8         op_mod[0x10];
2773
2774         u8         reserved_at_40[0x10];
2775         u8         profile[0x10];
2776
2777         u8         reserved_at_60[0x20];
2778 };
2779
2780 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2781         u8         status[0x8];
2782         u8         reserved_at_8[0x18];
2783
2784         u8         syndrome[0x20];
2785
2786         u8         reserved_at_40[0x40];
2787 };
2788
2789 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2790         u8         opcode[0x10];
2791         u8         reserved_at_10[0x10];
2792
2793         u8         reserved_at_20[0x10];
2794         u8         op_mod[0x10];
2795
2796         u8         reserved_at_40[0x8];
2797         u8         qpn[0x18];
2798
2799         u8         reserved_at_60[0x20];
2800
2801         u8         opt_param_mask[0x20];
2802
2803         u8         reserved_at_a0[0x20];
2804
2805         struct mlx5_ifc_qpc_bits qpc;
2806
2807         u8         reserved_at_800[0x80];
2808 };
2809
2810 struct mlx5_ifc_sqd2rts_qp_out_bits {
2811         u8         status[0x8];
2812         u8         reserved_at_8[0x18];
2813
2814         u8         syndrome[0x20];
2815
2816         u8         reserved_at_40[0x40];
2817 };
2818
2819 struct mlx5_ifc_sqd2rts_qp_in_bits {
2820         u8         opcode[0x10];
2821         u8         reserved_at_10[0x10];
2822
2823         u8         reserved_at_20[0x10];
2824         u8         op_mod[0x10];
2825
2826         u8         reserved_at_40[0x8];
2827         u8         qpn[0x18];
2828
2829         u8         reserved_at_60[0x20];
2830
2831         u8         opt_param_mask[0x20];
2832
2833         u8         reserved_at_a0[0x20];
2834
2835         struct mlx5_ifc_qpc_bits qpc;
2836
2837         u8         reserved_at_800[0x80];
2838 };
2839
2840 struct mlx5_ifc_set_roce_address_out_bits {
2841         u8         status[0x8];
2842         u8         reserved_at_8[0x18];
2843
2844         u8         syndrome[0x20];
2845
2846         u8         reserved_at_40[0x40];
2847 };
2848
2849 struct mlx5_ifc_set_roce_address_in_bits {
2850         u8         opcode[0x10];
2851         u8         reserved_at_10[0x10];
2852
2853         u8         reserved_at_20[0x10];
2854         u8         op_mod[0x10];
2855
2856         u8         roce_address_index[0x10];
2857         u8         reserved_at_50[0x10];
2858
2859         u8         reserved_at_60[0x20];
2860
2861         struct mlx5_ifc_roce_addr_layout_bits roce_address;
2862 };
2863
2864 struct mlx5_ifc_set_mad_demux_out_bits {
2865         u8         status[0x8];
2866         u8         reserved_at_8[0x18];
2867
2868         u8         syndrome[0x20];
2869
2870         u8         reserved_at_40[0x40];
2871 };
2872
2873 enum {
2874         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
2875         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
2876 };
2877
2878 struct mlx5_ifc_set_mad_demux_in_bits {
2879         u8         opcode[0x10];
2880         u8         reserved_at_10[0x10];
2881
2882         u8         reserved_at_20[0x10];
2883         u8         op_mod[0x10];
2884
2885         u8         reserved_at_40[0x20];
2886
2887         u8         reserved_at_60[0x6];
2888         u8         demux_mode[0x2];
2889         u8         reserved_at_68[0x18];
2890 };
2891
2892 struct mlx5_ifc_set_l2_table_entry_out_bits {
2893         u8         status[0x8];
2894         u8         reserved_at_8[0x18];
2895
2896         u8         syndrome[0x20];
2897
2898         u8         reserved_at_40[0x40];
2899 };
2900
2901 struct mlx5_ifc_set_l2_table_entry_in_bits {
2902         u8         opcode[0x10];
2903         u8         reserved_at_10[0x10];
2904
2905         u8         reserved_at_20[0x10];
2906         u8         op_mod[0x10];
2907
2908         u8         reserved_at_40[0x60];
2909
2910         u8         reserved_at_a0[0x8];
2911         u8         table_index[0x18];
2912
2913         u8         reserved_at_c0[0x20];
2914
2915         u8         reserved_at_e0[0x13];
2916         u8         vlan_valid[0x1];
2917         u8         vlan[0xc];
2918
2919         struct mlx5_ifc_mac_address_layout_bits mac_address;
2920
2921         u8         reserved_at_140[0xc0];
2922 };
2923
2924 struct mlx5_ifc_set_issi_out_bits {
2925         u8         status[0x8];
2926         u8         reserved_at_8[0x18];
2927
2928         u8         syndrome[0x20];
2929
2930         u8         reserved_at_40[0x40];
2931 };
2932
2933 struct mlx5_ifc_set_issi_in_bits {
2934         u8         opcode[0x10];
2935         u8         reserved_at_10[0x10];
2936
2937         u8         reserved_at_20[0x10];
2938         u8         op_mod[0x10];
2939
2940         u8         reserved_at_40[0x10];
2941         u8         current_issi[0x10];
2942
2943         u8         reserved_at_60[0x20];
2944 };
2945
2946 struct mlx5_ifc_set_hca_cap_out_bits {
2947         u8         status[0x8];
2948         u8         reserved_at_8[0x18];
2949
2950         u8         syndrome[0x20];
2951
2952         u8         reserved_at_40[0x40];
2953 };
2954
2955 struct mlx5_ifc_set_hca_cap_in_bits {
2956         u8         opcode[0x10];
2957         u8         reserved_at_10[0x10];
2958
2959         u8         reserved_at_20[0x10];
2960         u8         op_mod[0x10];
2961
2962         u8         reserved_at_40[0x40];
2963
2964         union mlx5_ifc_hca_cap_union_bits capability;
2965 };
2966
2967 enum {
2968         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
2969         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
2970         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
2971         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
2972 };
2973
2974 struct mlx5_ifc_set_fte_out_bits {
2975         u8         status[0x8];
2976         u8         reserved_at_8[0x18];
2977
2978         u8         syndrome[0x20];
2979
2980         u8         reserved_at_40[0x40];
2981 };
2982
2983 struct mlx5_ifc_set_fte_in_bits {
2984         u8         opcode[0x10];
2985         u8         reserved_at_10[0x10];
2986
2987         u8         reserved_at_20[0x10];
2988         u8         op_mod[0x10];
2989
2990         u8         reserved_at_40[0x40];
2991
2992         u8         table_type[0x8];
2993         u8         reserved_at_88[0x18];
2994
2995         u8         reserved_at_a0[0x8];
2996         u8         table_id[0x18];
2997
2998         u8         reserved_at_c0[0x18];
2999         u8         modify_enable_mask[0x8];
3000
3001         u8         reserved_at_e0[0x20];
3002
3003         u8         flow_index[0x20];
3004
3005         u8         reserved_at_120[0xe0];
3006
3007         struct mlx5_ifc_flow_context_bits flow_context;
3008 };
3009
3010 struct mlx5_ifc_rts2rts_qp_out_bits {
3011         u8         status[0x8];
3012         u8         reserved_at_8[0x18];
3013
3014         u8         syndrome[0x20];
3015
3016         u8         reserved_at_40[0x40];
3017 };
3018
3019 struct mlx5_ifc_rts2rts_qp_in_bits {
3020         u8         opcode[0x10];
3021         u8         reserved_at_10[0x10];
3022
3023         u8         reserved_at_20[0x10];
3024         u8         op_mod[0x10];
3025
3026         u8         reserved_at_40[0x8];
3027         u8         qpn[0x18];
3028
3029         u8         reserved_at_60[0x20];
3030
3031         u8         opt_param_mask[0x20];
3032
3033         u8         reserved_at_a0[0x20];
3034
3035         struct mlx5_ifc_qpc_bits qpc;
3036
3037         u8         reserved_at_800[0x80];
3038 };
3039
3040 struct mlx5_ifc_rtr2rts_qp_out_bits {
3041         u8         status[0x8];
3042         u8         reserved_at_8[0x18];
3043
3044         u8         syndrome[0x20];
3045
3046         u8         reserved_at_40[0x40];
3047 };
3048
3049 struct mlx5_ifc_rtr2rts_qp_in_bits {
3050         u8         opcode[0x10];
3051         u8         reserved_at_10[0x10];
3052
3053         u8         reserved_at_20[0x10];
3054         u8         op_mod[0x10];
3055
3056         u8         reserved_at_40[0x8];
3057         u8         qpn[0x18];
3058
3059         u8         reserved_at_60[0x20];
3060
3061         u8         opt_param_mask[0x20];
3062
3063         u8         reserved_at_a0[0x20];
3064
3065         struct mlx5_ifc_qpc_bits qpc;
3066
3067         u8         reserved_at_800[0x80];
3068 };
3069
3070 struct mlx5_ifc_rst2init_qp_out_bits {
3071         u8         status[0x8];
3072         u8         reserved_at_8[0x18];
3073
3074         u8         syndrome[0x20];
3075
3076         u8         reserved_at_40[0x40];
3077 };
3078
3079 struct mlx5_ifc_rst2init_qp_in_bits {
3080         u8         opcode[0x10];
3081         u8         reserved_at_10[0x10];
3082
3083         u8         reserved_at_20[0x10];
3084         u8         op_mod[0x10];
3085
3086         u8         reserved_at_40[0x8];
3087         u8         qpn[0x18];
3088
3089         u8         reserved_at_60[0x20];
3090
3091         u8         opt_param_mask[0x20];
3092
3093         u8         reserved_at_a0[0x20];
3094
3095         struct mlx5_ifc_qpc_bits qpc;
3096
3097         u8         reserved_at_800[0x80];
3098 };
3099
3100 struct mlx5_ifc_query_xrc_srq_out_bits {
3101         u8         status[0x8];
3102         u8         reserved_at_8[0x18];
3103
3104         u8         syndrome[0x20];
3105
3106         u8         reserved_at_40[0x40];
3107
3108         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3109
3110         u8         reserved_at_280[0x600];
3111
3112         u8         pas[0][0x40];
3113 };
3114
3115 struct mlx5_ifc_query_xrc_srq_in_bits {
3116         u8         opcode[0x10];
3117         u8         reserved_at_10[0x10];
3118
3119         u8         reserved_at_20[0x10];
3120         u8         op_mod[0x10];
3121
3122         u8         reserved_at_40[0x8];
3123         u8         xrc_srqn[0x18];
3124
3125         u8         reserved_at_60[0x20];
3126 };
3127
3128 enum {
3129         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3130         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3131 };
3132
3133 struct mlx5_ifc_query_vport_state_out_bits {
3134         u8         status[0x8];
3135         u8         reserved_at_8[0x18];
3136
3137         u8         syndrome[0x20];
3138
3139         u8         reserved_at_40[0x20];
3140
3141         u8         reserved_at_60[0x18];
3142         u8         admin_state[0x4];
3143         u8         state[0x4];
3144 };
3145
3146 enum {
3147         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3148         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3149 };
3150
3151 struct mlx5_ifc_query_vport_state_in_bits {
3152         u8         opcode[0x10];
3153         u8         reserved_at_10[0x10];
3154
3155         u8         reserved_at_20[0x10];
3156         u8         op_mod[0x10];
3157
3158         u8         other_vport[0x1];
3159         u8         reserved_at_41[0xf];
3160         u8         vport_number[0x10];
3161
3162         u8         reserved_at_60[0x20];
3163 };
3164
3165 struct mlx5_ifc_query_vport_counter_out_bits {
3166         u8         status[0x8];
3167         u8         reserved_at_8[0x18];
3168
3169         u8         syndrome[0x20];
3170
3171         u8         reserved_at_40[0x40];
3172
3173         struct mlx5_ifc_traffic_counter_bits received_errors;
3174
3175         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3176
3177         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3178
3179         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3180
3181         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3182
3183         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3184
3185         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3186
3187         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3188
3189         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3190
3191         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3192
3193         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3194
3195         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3196
3197         u8         reserved_at_680[0xa00];
3198 };
3199
3200 enum {
3201         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3202 };
3203
3204 struct mlx5_ifc_query_vport_counter_in_bits {
3205         u8         opcode[0x10];
3206         u8         reserved_at_10[0x10];
3207
3208         u8         reserved_at_20[0x10];
3209         u8         op_mod[0x10];
3210
3211         u8         other_vport[0x1];
3212         u8         reserved_at_41[0xb];
3213         u8         port_num[0x4];
3214         u8         vport_number[0x10];
3215
3216         u8         reserved_at_60[0x60];
3217
3218         u8         clear[0x1];
3219         u8         reserved_at_c1[0x1f];
3220
3221         u8         reserved_at_e0[0x20];
3222 };
3223
3224 struct mlx5_ifc_query_tis_out_bits {
3225         u8         status[0x8];
3226         u8         reserved_at_8[0x18];
3227
3228         u8         syndrome[0x20];
3229
3230         u8         reserved_at_40[0x40];
3231
3232         struct mlx5_ifc_tisc_bits tis_context;
3233 };
3234
3235 struct mlx5_ifc_query_tis_in_bits {
3236         u8         opcode[0x10];
3237         u8         reserved_at_10[0x10];
3238
3239         u8         reserved_at_20[0x10];
3240         u8         op_mod[0x10];
3241
3242         u8         reserved_at_40[0x8];
3243         u8         tisn[0x18];
3244
3245         u8         reserved_at_60[0x20];
3246 };
3247
3248 struct mlx5_ifc_query_tir_out_bits {
3249         u8         status[0x8];
3250         u8         reserved_at_8[0x18];
3251
3252         u8         syndrome[0x20];
3253
3254         u8         reserved_at_40[0xc0];
3255
3256         struct mlx5_ifc_tirc_bits tir_context;
3257 };
3258
3259 struct mlx5_ifc_query_tir_in_bits {
3260         u8         opcode[0x10];
3261         u8         reserved_at_10[0x10];
3262
3263         u8         reserved_at_20[0x10];
3264         u8         op_mod[0x10];
3265
3266         u8         reserved_at_40[0x8];
3267         u8         tirn[0x18];
3268
3269         u8         reserved_at_60[0x20];
3270 };
3271
3272 struct mlx5_ifc_query_srq_out_bits {
3273         u8         status[0x8];
3274         u8         reserved_at_8[0x18];
3275
3276         u8         syndrome[0x20];
3277
3278         u8         reserved_at_40[0x40];
3279
3280         struct mlx5_ifc_srqc_bits srq_context_entry;
3281
3282         u8         reserved_at_280[0x600];
3283
3284         u8         pas[0][0x40];
3285 };
3286
3287 struct mlx5_ifc_query_srq_in_bits {
3288         u8         opcode[0x10];
3289         u8         reserved_at_10[0x10];
3290
3291         u8         reserved_at_20[0x10];
3292         u8         op_mod[0x10];
3293
3294         u8         reserved_at_40[0x8];
3295         u8         srqn[0x18];
3296
3297         u8         reserved_at_60[0x20];
3298 };
3299
3300 struct mlx5_ifc_query_sq_out_bits {
3301         u8         status[0x8];
3302         u8         reserved_at_8[0x18];
3303
3304         u8         syndrome[0x20];
3305
3306         u8         reserved_at_40[0xc0];
3307
3308         struct mlx5_ifc_sqc_bits sq_context;
3309 };
3310
3311 struct mlx5_ifc_query_sq_in_bits {
3312         u8         opcode[0x10];
3313         u8         reserved_at_10[0x10];
3314
3315         u8         reserved_at_20[0x10];
3316         u8         op_mod[0x10];
3317
3318         u8         reserved_at_40[0x8];
3319         u8         sqn[0x18];
3320
3321         u8         reserved_at_60[0x20];
3322 };
3323
3324 struct mlx5_ifc_query_special_contexts_out_bits {
3325         u8         status[0x8];
3326         u8         reserved_at_8[0x18];
3327
3328         u8         syndrome[0x20];
3329
3330         u8         reserved_at_40[0x20];
3331
3332         u8         resd_lkey[0x20];
3333 };
3334
3335 struct mlx5_ifc_query_special_contexts_in_bits {
3336         u8         opcode[0x10];
3337         u8         reserved_at_10[0x10];
3338
3339         u8         reserved_at_20[0x10];
3340         u8         op_mod[0x10];
3341
3342         u8         reserved_at_40[0x40];
3343 };
3344
3345 struct mlx5_ifc_query_rqt_out_bits {
3346         u8         status[0x8];
3347         u8         reserved_at_8[0x18];
3348
3349         u8         syndrome[0x20];
3350
3351         u8         reserved_at_40[0xc0];
3352
3353         struct mlx5_ifc_rqtc_bits rqt_context;
3354 };
3355
3356 struct mlx5_ifc_query_rqt_in_bits {
3357         u8         opcode[0x10];
3358         u8         reserved_at_10[0x10];
3359
3360         u8         reserved_at_20[0x10];
3361         u8         op_mod[0x10];
3362
3363         u8         reserved_at_40[0x8];
3364         u8         rqtn[0x18];
3365
3366         u8         reserved_at_60[0x20];
3367 };
3368
3369 struct mlx5_ifc_query_rq_out_bits {
3370         u8         status[0x8];
3371         u8         reserved_at_8[0x18];
3372
3373         u8         syndrome[0x20];
3374
3375         u8         reserved_at_40[0xc0];
3376
3377         struct mlx5_ifc_rqc_bits rq_context;
3378 };
3379
3380 struct mlx5_ifc_query_rq_in_bits {
3381         u8         opcode[0x10];
3382         u8         reserved_at_10[0x10];
3383
3384         u8         reserved_at_20[0x10];
3385         u8         op_mod[0x10];
3386
3387         u8         reserved_at_40[0x8];
3388         u8         rqn[0x18];
3389
3390         u8         reserved_at_60[0x20];
3391 };
3392
3393 struct mlx5_ifc_query_roce_address_out_bits {
3394         u8         status[0x8];
3395         u8         reserved_at_8[0x18];
3396
3397         u8         syndrome[0x20];
3398
3399         u8         reserved_at_40[0x40];
3400
3401         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3402 };
3403
3404 struct mlx5_ifc_query_roce_address_in_bits {
3405         u8         opcode[0x10];
3406         u8         reserved_at_10[0x10];
3407
3408         u8         reserved_at_20[0x10];
3409         u8         op_mod[0x10];
3410
3411         u8         roce_address_index[0x10];
3412         u8         reserved_at_50[0x10];
3413
3414         u8         reserved_at_60[0x20];
3415 };
3416
3417 struct mlx5_ifc_query_rmp_out_bits {
3418         u8         status[0x8];
3419         u8         reserved_at_8[0x18];
3420
3421         u8         syndrome[0x20];
3422
3423         u8         reserved_at_40[0xc0];
3424
3425         struct mlx5_ifc_rmpc_bits rmp_context;
3426 };
3427
3428 struct mlx5_ifc_query_rmp_in_bits {
3429         u8         opcode[0x10];
3430         u8         reserved_at_10[0x10];
3431
3432         u8         reserved_at_20[0x10];
3433         u8         op_mod[0x10];
3434
3435         u8         reserved_at_40[0x8];
3436         u8         rmpn[0x18];
3437
3438         u8         reserved_at_60[0x20];
3439 };
3440
3441 struct mlx5_ifc_query_qp_out_bits {
3442         u8         status[0x8];
3443         u8         reserved_at_8[0x18];
3444
3445         u8         syndrome[0x20];
3446
3447         u8         reserved_at_40[0x40];
3448
3449         u8         opt_param_mask[0x20];
3450
3451         u8         reserved_at_a0[0x20];
3452
3453         struct mlx5_ifc_qpc_bits qpc;
3454
3455         u8         reserved_at_800[0x80];
3456
3457         u8         pas[0][0x40];
3458 };
3459
3460 struct mlx5_ifc_query_qp_in_bits {
3461         u8         opcode[0x10];
3462         u8         reserved_at_10[0x10];
3463
3464         u8         reserved_at_20[0x10];
3465         u8         op_mod[0x10];
3466
3467         u8         reserved_at_40[0x8];
3468         u8         qpn[0x18];
3469
3470         u8         reserved_at_60[0x20];
3471 };
3472
3473 struct mlx5_ifc_query_q_counter_out_bits {
3474         u8         status[0x8];
3475         u8         reserved_at_8[0x18];
3476
3477         u8         syndrome[0x20];
3478
3479         u8         reserved_at_40[0x40];
3480
3481         u8         rx_write_requests[0x20];
3482
3483         u8         reserved_at_a0[0x20];
3484
3485         u8         rx_read_requests[0x20];
3486
3487         u8         reserved_at_e0[0x20];
3488
3489         u8         rx_atomic_requests[0x20];
3490
3491         u8         reserved_at_120[0x20];
3492
3493         u8         rx_dct_connect[0x20];
3494
3495         u8         reserved_at_160[0x20];
3496
3497         u8         out_of_buffer[0x20];
3498
3499         u8         reserved_at_1a0[0x20];
3500
3501         u8         out_of_sequence[0x20];
3502
3503         u8         reserved_at_1e0[0x620];
3504 };
3505
3506 struct mlx5_ifc_query_q_counter_in_bits {
3507         u8         opcode[0x10];
3508         u8         reserved_at_10[0x10];
3509
3510         u8         reserved_at_20[0x10];
3511         u8         op_mod[0x10];
3512
3513         u8         reserved_at_40[0x80];
3514
3515         u8         clear[0x1];
3516         u8         reserved_at_c1[0x1f];
3517
3518         u8         reserved_at_e0[0x18];
3519         u8         counter_set_id[0x8];
3520 };
3521
3522 struct mlx5_ifc_query_pages_out_bits {
3523         u8         status[0x8];
3524         u8         reserved_at_8[0x18];
3525
3526         u8         syndrome[0x20];
3527
3528         u8         reserved_at_40[0x10];
3529         u8         function_id[0x10];
3530
3531         u8         num_pages[0x20];
3532 };
3533
3534 enum {
3535         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3536         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3537         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3538 };
3539
3540 struct mlx5_ifc_query_pages_in_bits {
3541         u8         opcode[0x10];
3542         u8         reserved_at_10[0x10];
3543
3544         u8         reserved_at_20[0x10];
3545         u8         op_mod[0x10];
3546
3547         u8         reserved_at_40[0x10];
3548         u8         function_id[0x10];
3549
3550         u8         reserved_at_60[0x20];
3551 };
3552
3553 struct mlx5_ifc_query_nic_vport_context_out_bits {
3554         u8         status[0x8];
3555         u8         reserved_at_8[0x18];
3556
3557         u8         syndrome[0x20];
3558
3559         u8         reserved_at_40[0x40];
3560
3561         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3562 };
3563
3564 struct mlx5_ifc_query_nic_vport_context_in_bits {
3565         u8         opcode[0x10];
3566         u8         reserved_at_10[0x10];
3567
3568         u8         reserved_at_20[0x10];
3569         u8         op_mod[0x10];
3570
3571         u8         other_vport[0x1];
3572         u8         reserved_at_41[0xf];
3573         u8         vport_number[0x10];
3574
3575         u8         reserved_at_60[0x5];
3576         u8         allowed_list_type[0x3];
3577         u8         reserved_at_68[0x18];
3578 };
3579
3580 struct mlx5_ifc_query_mkey_out_bits {
3581         u8         status[0x8];
3582         u8         reserved_at_8[0x18];
3583
3584         u8         syndrome[0x20];
3585
3586         u8         reserved_at_40[0x40];
3587
3588         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3589
3590         u8         reserved_at_280[0x600];
3591
3592         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3593
3594         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3595 };
3596
3597 struct mlx5_ifc_query_mkey_in_bits {
3598         u8         opcode[0x10];
3599         u8         reserved_at_10[0x10];
3600
3601         u8         reserved_at_20[0x10];
3602         u8         op_mod[0x10];
3603
3604         u8         reserved_at_40[0x8];
3605         u8         mkey_index[0x18];
3606
3607         u8         pg_access[0x1];
3608         u8         reserved_at_61[0x1f];
3609 };
3610
3611 struct mlx5_ifc_query_mad_demux_out_bits {
3612         u8         status[0x8];
3613         u8         reserved_at_8[0x18];
3614
3615         u8         syndrome[0x20];
3616
3617         u8         reserved_at_40[0x40];
3618
3619         u8         mad_dumux_parameters_block[0x20];
3620 };
3621
3622 struct mlx5_ifc_query_mad_demux_in_bits {
3623         u8         opcode[0x10];
3624         u8         reserved_at_10[0x10];
3625
3626         u8         reserved_at_20[0x10];
3627         u8         op_mod[0x10];
3628
3629         u8         reserved_at_40[0x40];
3630 };
3631
3632 struct mlx5_ifc_query_l2_table_entry_out_bits {
3633         u8         status[0x8];
3634         u8         reserved_at_8[0x18];
3635
3636         u8         syndrome[0x20];
3637
3638         u8         reserved_at_40[0xa0];
3639
3640         u8         reserved_at_e0[0x13];
3641         u8         vlan_valid[0x1];
3642         u8         vlan[0xc];
3643
3644         struct mlx5_ifc_mac_address_layout_bits mac_address;
3645
3646         u8         reserved_at_140[0xc0];
3647 };
3648
3649 struct mlx5_ifc_query_l2_table_entry_in_bits {
3650         u8         opcode[0x10];
3651         u8         reserved_at_10[0x10];
3652
3653         u8         reserved_at_20[0x10];
3654         u8         op_mod[0x10];
3655
3656         u8         reserved_at_40[0x60];
3657
3658         u8         reserved_at_a0[0x8];
3659         u8         table_index[0x18];
3660
3661         u8         reserved_at_c0[0x140];
3662 };
3663
3664 struct mlx5_ifc_query_issi_out_bits {
3665         u8         status[0x8];
3666         u8         reserved_at_8[0x18];
3667
3668         u8         syndrome[0x20];
3669
3670         u8         reserved_at_40[0x10];
3671         u8         current_issi[0x10];
3672
3673         u8         reserved_at_60[0xa0];
3674
3675         u8         reserved_at_100[76][0x8];
3676         u8         supported_issi_dw0[0x20];
3677 };
3678
3679 struct mlx5_ifc_query_issi_in_bits {
3680         u8         opcode[0x10];
3681         u8         reserved_at_10[0x10];
3682
3683         u8         reserved_at_20[0x10];
3684         u8         op_mod[0x10];
3685
3686         u8         reserved_at_40[0x40];
3687 };
3688
3689 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3690         u8         status[0x8];
3691         u8         reserved_at_8[0x18];
3692
3693         u8         syndrome[0x20];
3694
3695         u8         reserved_at_40[0x40];
3696
3697         struct mlx5_ifc_pkey_bits pkey[0];
3698 };
3699
3700 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3701         u8         opcode[0x10];
3702         u8         reserved_at_10[0x10];
3703
3704         u8         reserved_at_20[0x10];
3705         u8         op_mod[0x10];
3706
3707         u8         other_vport[0x1];
3708         u8         reserved_at_41[0xb];
3709         u8         port_num[0x4];
3710         u8         vport_number[0x10];
3711
3712         u8         reserved_at_60[0x10];
3713         u8         pkey_index[0x10];
3714 };
3715
3716 enum {
3717         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
3718         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
3719         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
3720 };
3721
3722 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3723         u8         status[0x8];
3724         u8         reserved_at_8[0x18];
3725
3726         u8         syndrome[0x20];
3727
3728         u8         reserved_at_40[0x20];
3729
3730         u8         gids_num[0x10];
3731         u8         reserved_at_70[0x10];
3732
3733         struct mlx5_ifc_array128_auto_bits gid[0];
3734 };
3735
3736 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3737         u8         opcode[0x10];
3738         u8         reserved_at_10[0x10];
3739
3740         u8         reserved_at_20[0x10];
3741         u8         op_mod[0x10];
3742
3743         u8         other_vport[0x1];
3744         u8         reserved_at_41[0xb];
3745         u8         port_num[0x4];
3746         u8         vport_number[0x10];
3747
3748         u8         reserved_at_60[0x10];
3749         u8         gid_index[0x10];
3750 };
3751
3752 struct mlx5_ifc_query_hca_vport_context_out_bits {
3753         u8         status[0x8];
3754         u8         reserved_at_8[0x18];
3755
3756         u8         syndrome[0x20];
3757
3758         u8         reserved_at_40[0x40];
3759
3760         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3761 };
3762
3763 struct mlx5_ifc_query_hca_vport_context_in_bits {
3764         u8         opcode[0x10];
3765         u8         reserved_at_10[0x10];
3766
3767         u8         reserved_at_20[0x10];
3768         u8         op_mod[0x10];
3769
3770         u8         other_vport[0x1];
3771         u8         reserved_at_41[0xb];
3772         u8         port_num[0x4];
3773         u8         vport_number[0x10];
3774
3775         u8         reserved_at_60[0x20];
3776 };
3777
3778 struct mlx5_ifc_query_hca_cap_out_bits {
3779         u8         status[0x8];
3780         u8         reserved_at_8[0x18];
3781
3782         u8         syndrome[0x20];
3783
3784         u8         reserved_at_40[0x40];
3785
3786         union mlx5_ifc_hca_cap_union_bits capability;
3787 };
3788
3789 struct mlx5_ifc_query_hca_cap_in_bits {
3790         u8         opcode[0x10];
3791         u8         reserved_at_10[0x10];
3792
3793         u8         reserved_at_20[0x10];
3794         u8         op_mod[0x10];
3795
3796         u8         reserved_at_40[0x40];
3797 };
3798
3799 struct mlx5_ifc_query_flow_table_out_bits {
3800         u8         status[0x8];
3801         u8         reserved_at_8[0x18];
3802
3803         u8         syndrome[0x20];
3804
3805         u8         reserved_at_40[0x80];
3806
3807         u8         reserved_at_c0[0x8];
3808         u8         level[0x8];
3809         u8         reserved_at_d0[0x8];
3810         u8         log_size[0x8];
3811
3812         u8         reserved_at_e0[0x120];
3813 };
3814
3815 struct mlx5_ifc_query_flow_table_in_bits {
3816         u8         opcode[0x10];
3817         u8         reserved_at_10[0x10];
3818
3819         u8         reserved_at_20[0x10];
3820         u8         op_mod[0x10];
3821
3822         u8         reserved_at_40[0x40];
3823
3824         u8         table_type[0x8];
3825         u8         reserved_at_88[0x18];
3826
3827         u8         reserved_at_a0[0x8];
3828         u8         table_id[0x18];
3829
3830         u8         reserved_at_c0[0x140];
3831 };
3832
3833 struct mlx5_ifc_query_fte_out_bits {
3834         u8         status[0x8];
3835         u8         reserved_at_8[0x18];
3836
3837         u8         syndrome[0x20];
3838
3839         u8         reserved_at_40[0x1c0];
3840
3841         struct mlx5_ifc_flow_context_bits flow_context;
3842 };
3843
3844 struct mlx5_ifc_query_fte_in_bits {
3845         u8         opcode[0x10];
3846         u8         reserved_at_10[0x10];
3847
3848         u8         reserved_at_20[0x10];
3849         u8         op_mod[0x10];
3850
3851         u8         reserved_at_40[0x40];
3852
3853         u8         table_type[0x8];
3854         u8         reserved_at_88[0x18];
3855
3856         u8         reserved_at_a0[0x8];
3857         u8         table_id[0x18];
3858
3859         u8         reserved_at_c0[0x40];
3860
3861         u8         flow_index[0x20];
3862
3863         u8         reserved_at_120[0xe0];
3864 };
3865
3866 enum {
3867         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
3868         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
3869         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
3870 };
3871
3872 struct mlx5_ifc_query_flow_group_out_bits {
3873         u8         status[0x8];
3874         u8         reserved_at_8[0x18];
3875
3876         u8         syndrome[0x20];
3877
3878         u8         reserved_at_40[0xa0];
3879
3880         u8         start_flow_index[0x20];
3881
3882         u8         reserved_at_100[0x20];
3883
3884         u8         end_flow_index[0x20];
3885
3886         u8         reserved_at_140[0xa0];
3887
3888         u8         reserved_at_1e0[0x18];
3889         u8         match_criteria_enable[0x8];
3890
3891         struct mlx5_ifc_fte_match_param_bits match_criteria;
3892
3893         u8         reserved_at_1200[0xe00];
3894 };
3895
3896 struct mlx5_ifc_query_flow_group_in_bits {
3897         u8         opcode[0x10];
3898         u8         reserved_at_10[0x10];
3899
3900         u8         reserved_at_20[0x10];
3901         u8         op_mod[0x10];
3902
3903         u8         reserved_at_40[0x40];
3904
3905         u8         table_type[0x8];
3906         u8         reserved_at_88[0x18];
3907
3908         u8         reserved_at_a0[0x8];
3909         u8         table_id[0x18];
3910
3911         u8         group_id[0x20];
3912
3913         u8         reserved_at_e0[0x120];
3914 };
3915
3916 struct mlx5_ifc_query_esw_vport_context_out_bits {
3917         u8         status[0x8];
3918         u8         reserved_at_8[0x18];
3919
3920         u8         syndrome[0x20];
3921
3922         u8         reserved_at_40[0x40];
3923
3924         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3925 };
3926
3927 struct mlx5_ifc_query_esw_vport_context_in_bits {
3928         u8         opcode[0x10];
3929         u8         reserved_at_10[0x10];
3930
3931         u8         reserved_at_20[0x10];
3932         u8         op_mod[0x10];
3933
3934         u8         other_vport[0x1];
3935         u8         reserved_at_41[0xf];
3936         u8         vport_number[0x10];
3937
3938         u8         reserved_at_60[0x20];
3939 };
3940
3941 struct mlx5_ifc_modify_esw_vport_context_out_bits {
3942         u8         status[0x8];
3943         u8         reserved_at_8[0x18];
3944
3945         u8         syndrome[0x20];
3946
3947         u8         reserved_at_40[0x40];
3948 };
3949
3950 struct mlx5_ifc_esw_vport_context_fields_select_bits {
3951         u8         reserved_at_0[0x1c];
3952         u8         vport_cvlan_insert[0x1];
3953         u8         vport_svlan_insert[0x1];
3954         u8         vport_cvlan_strip[0x1];
3955         u8         vport_svlan_strip[0x1];
3956 };
3957
3958 struct mlx5_ifc_modify_esw_vport_context_in_bits {
3959         u8         opcode[0x10];
3960         u8         reserved_at_10[0x10];
3961
3962         u8         reserved_at_20[0x10];
3963         u8         op_mod[0x10];
3964
3965         u8         other_vport[0x1];
3966         u8         reserved_at_41[0xf];
3967         u8         vport_number[0x10];
3968
3969         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
3970
3971         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3972 };
3973
3974 struct mlx5_ifc_query_eq_out_bits {
3975         u8         status[0x8];
3976         u8         reserved_at_8[0x18];
3977
3978         u8         syndrome[0x20];
3979
3980         u8         reserved_at_40[0x40];
3981
3982         struct mlx5_ifc_eqc_bits eq_context_entry;
3983
3984         u8         reserved_at_280[0x40];
3985
3986         u8         event_bitmask[0x40];
3987
3988         u8         reserved_at_300[0x580];
3989
3990         u8         pas[0][0x40];
3991 };
3992
3993 struct mlx5_ifc_query_eq_in_bits {
3994         u8         opcode[0x10];
3995         u8         reserved_at_10[0x10];
3996
3997         u8         reserved_at_20[0x10];
3998         u8         op_mod[0x10];
3999
4000         u8         reserved_at_40[0x18];
4001         u8         eq_number[0x8];
4002
4003         u8         reserved_at_60[0x20];
4004 };
4005
4006 struct mlx5_ifc_query_dct_out_bits {
4007         u8         status[0x8];
4008         u8         reserved_at_8[0x18];
4009
4010         u8         syndrome[0x20];
4011
4012         u8         reserved_at_40[0x40];
4013
4014         struct mlx5_ifc_dctc_bits dct_context_entry;
4015
4016         u8         reserved_at_280[0x180];
4017 };
4018
4019 struct mlx5_ifc_query_dct_in_bits {
4020         u8         opcode[0x10];
4021         u8         reserved_at_10[0x10];
4022
4023         u8         reserved_at_20[0x10];
4024         u8         op_mod[0x10];
4025
4026         u8         reserved_at_40[0x8];
4027         u8         dctn[0x18];
4028
4029         u8         reserved_at_60[0x20];
4030 };
4031
4032 struct mlx5_ifc_query_cq_out_bits {
4033         u8         status[0x8];
4034         u8         reserved_at_8[0x18];
4035
4036         u8         syndrome[0x20];
4037
4038         u8         reserved_at_40[0x40];
4039
4040         struct mlx5_ifc_cqc_bits cq_context;
4041
4042         u8         reserved_at_280[0x600];
4043
4044         u8         pas[0][0x40];
4045 };
4046
4047 struct mlx5_ifc_query_cq_in_bits {
4048         u8         opcode[0x10];
4049         u8         reserved_at_10[0x10];
4050
4051         u8         reserved_at_20[0x10];
4052         u8         op_mod[0x10];
4053
4054         u8         reserved_at_40[0x8];
4055         u8         cqn[0x18];
4056
4057         u8         reserved_at_60[0x20];
4058 };
4059
4060 struct mlx5_ifc_query_cong_status_out_bits {
4061         u8         status[0x8];
4062         u8         reserved_at_8[0x18];
4063
4064         u8         syndrome[0x20];
4065
4066         u8         reserved_at_40[0x20];
4067
4068         u8         enable[0x1];
4069         u8         tag_enable[0x1];
4070         u8         reserved_at_62[0x1e];
4071 };
4072
4073 struct mlx5_ifc_query_cong_status_in_bits {
4074         u8         opcode[0x10];
4075         u8         reserved_at_10[0x10];
4076
4077         u8         reserved_at_20[0x10];
4078         u8         op_mod[0x10];
4079
4080         u8         reserved_at_40[0x18];
4081         u8         priority[0x4];
4082         u8         cong_protocol[0x4];
4083
4084         u8         reserved_at_60[0x20];
4085 };
4086
4087 struct mlx5_ifc_query_cong_statistics_out_bits {
4088         u8         status[0x8];
4089         u8         reserved_at_8[0x18];
4090
4091         u8         syndrome[0x20];
4092
4093         u8         reserved_at_40[0x40];
4094
4095         u8         cur_flows[0x20];
4096
4097         u8         sum_flows[0x20];
4098
4099         u8         cnp_ignored_high[0x20];
4100
4101         u8         cnp_ignored_low[0x20];
4102
4103         u8         cnp_handled_high[0x20];
4104
4105         u8         cnp_handled_low[0x20];
4106
4107         u8         reserved_at_140[0x100];
4108
4109         u8         time_stamp_high[0x20];
4110
4111         u8         time_stamp_low[0x20];
4112
4113         u8         accumulators_period[0x20];
4114
4115         u8         ecn_marked_roce_packets_high[0x20];
4116
4117         u8         ecn_marked_roce_packets_low[0x20];
4118
4119         u8         cnps_sent_high[0x20];
4120
4121         u8         cnps_sent_low[0x20];
4122
4123         u8         reserved_at_320[0x560];
4124 };
4125
4126 struct mlx5_ifc_query_cong_statistics_in_bits {
4127         u8         opcode[0x10];
4128         u8         reserved_at_10[0x10];
4129
4130         u8         reserved_at_20[0x10];
4131         u8         op_mod[0x10];
4132
4133         u8         clear[0x1];
4134         u8         reserved_at_41[0x1f];
4135
4136         u8         reserved_at_60[0x20];
4137 };
4138
4139 struct mlx5_ifc_query_cong_params_out_bits {
4140         u8         status[0x8];
4141         u8         reserved_at_8[0x18];
4142
4143         u8         syndrome[0x20];
4144
4145         u8         reserved_at_40[0x40];
4146
4147         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4148 };
4149
4150 struct mlx5_ifc_query_cong_params_in_bits {
4151         u8         opcode[0x10];
4152         u8         reserved_at_10[0x10];
4153
4154         u8         reserved_at_20[0x10];
4155         u8         op_mod[0x10];
4156
4157         u8         reserved_at_40[0x1c];
4158         u8         cong_protocol[0x4];
4159
4160         u8         reserved_at_60[0x20];
4161 };
4162
4163 struct mlx5_ifc_query_adapter_out_bits {
4164         u8         status[0x8];
4165         u8         reserved_at_8[0x18];
4166
4167         u8         syndrome[0x20];
4168
4169         u8         reserved_at_40[0x40];
4170
4171         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4172 };
4173
4174 struct mlx5_ifc_query_adapter_in_bits {
4175         u8         opcode[0x10];
4176         u8         reserved_at_10[0x10];
4177
4178         u8         reserved_at_20[0x10];
4179         u8         op_mod[0x10];
4180
4181         u8         reserved_at_40[0x40];
4182 };
4183
4184 struct mlx5_ifc_qp_2rst_out_bits {
4185         u8         status[0x8];
4186         u8         reserved_at_8[0x18];
4187
4188         u8         syndrome[0x20];
4189
4190         u8         reserved_at_40[0x40];
4191 };
4192
4193 struct mlx5_ifc_qp_2rst_in_bits {
4194         u8         opcode[0x10];
4195         u8         reserved_at_10[0x10];
4196
4197         u8         reserved_at_20[0x10];
4198         u8         op_mod[0x10];
4199
4200         u8         reserved_at_40[0x8];
4201         u8         qpn[0x18];
4202
4203         u8         reserved_at_60[0x20];
4204 };
4205
4206 struct mlx5_ifc_qp_2err_out_bits {
4207         u8         status[0x8];
4208         u8         reserved_at_8[0x18];
4209
4210         u8         syndrome[0x20];
4211
4212         u8         reserved_at_40[0x40];
4213 };
4214
4215 struct mlx5_ifc_qp_2err_in_bits {
4216         u8         opcode[0x10];
4217         u8         reserved_at_10[0x10];
4218
4219         u8         reserved_at_20[0x10];
4220         u8         op_mod[0x10];
4221
4222         u8         reserved_at_40[0x8];
4223         u8         qpn[0x18];
4224
4225         u8         reserved_at_60[0x20];
4226 };
4227
4228 struct mlx5_ifc_page_fault_resume_out_bits {
4229         u8         status[0x8];
4230         u8         reserved_at_8[0x18];
4231
4232         u8         syndrome[0x20];
4233
4234         u8         reserved_at_40[0x40];
4235 };
4236
4237 struct mlx5_ifc_page_fault_resume_in_bits {
4238         u8         opcode[0x10];
4239         u8         reserved_at_10[0x10];
4240
4241         u8         reserved_at_20[0x10];
4242         u8         op_mod[0x10];
4243
4244         u8         error[0x1];
4245         u8         reserved_at_41[0x4];
4246         u8         rdma[0x1];
4247         u8         read_write[0x1];
4248         u8         req_res[0x1];
4249         u8         qpn[0x18];
4250
4251         u8         reserved_at_60[0x20];
4252 };
4253
4254 struct mlx5_ifc_nop_out_bits {
4255         u8         status[0x8];
4256         u8         reserved_at_8[0x18];
4257
4258         u8         syndrome[0x20];
4259
4260         u8         reserved_at_40[0x40];
4261 };
4262
4263 struct mlx5_ifc_nop_in_bits {
4264         u8         opcode[0x10];
4265         u8         reserved_at_10[0x10];
4266
4267         u8         reserved_at_20[0x10];
4268         u8         op_mod[0x10];
4269
4270         u8         reserved_at_40[0x40];
4271 };
4272
4273 struct mlx5_ifc_modify_vport_state_out_bits {
4274         u8         status[0x8];
4275         u8         reserved_at_8[0x18];
4276
4277         u8         syndrome[0x20];
4278
4279         u8         reserved_at_40[0x40];
4280 };
4281
4282 struct mlx5_ifc_modify_vport_state_in_bits {
4283         u8         opcode[0x10];
4284         u8         reserved_at_10[0x10];
4285
4286         u8         reserved_at_20[0x10];
4287         u8         op_mod[0x10];
4288
4289         u8         other_vport[0x1];
4290         u8         reserved_at_41[0xf];
4291         u8         vport_number[0x10];
4292
4293         u8         reserved_at_60[0x18];
4294         u8         admin_state[0x4];
4295         u8         reserved_at_7c[0x4];
4296 };
4297
4298 struct mlx5_ifc_modify_tis_out_bits {
4299         u8         status[0x8];
4300         u8         reserved_at_8[0x18];
4301
4302         u8         syndrome[0x20];
4303
4304         u8         reserved_at_40[0x40];
4305 };
4306
4307 struct mlx5_ifc_modify_tis_bitmask_bits {
4308         u8         reserved_at_0[0x20];
4309
4310         u8         reserved_at_20[0x1f];
4311         u8         prio[0x1];
4312 };
4313
4314 struct mlx5_ifc_modify_tis_in_bits {
4315         u8         opcode[0x10];
4316         u8         reserved_at_10[0x10];
4317
4318         u8         reserved_at_20[0x10];
4319         u8         op_mod[0x10];
4320
4321         u8         reserved_at_40[0x8];
4322         u8         tisn[0x18];
4323
4324         u8         reserved_at_60[0x20];
4325
4326         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4327
4328         u8         reserved_at_c0[0x40];
4329
4330         struct mlx5_ifc_tisc_bits ctx;
4331 };
4332
4333 struct mlx5_ifc_modify_tir_bitmask_bits {
4334         u8         reserved_at_0[0x20];
4335
4336         u8         reserved_at_20[0x1b];
4337         u8         self_lb_en[0x1];
4338         u8         reserved_at_3c[0x1];
4339         u8         hash[0x1];
4340         u8         reserved_at_3e[0x1];
4341         u8         lro[0x1];
4342 };
4343
4344 struct mlx5_ifc_modify_tir_out_bits {
4345         u8         status[0x8];
4346         u8         reserved_at_8[0x18];
4347
4348         u8         syndrome[0x20];
4349
4350         u8         reserved_at_40[0x40];
4351 };
4352
4353 struct mlx5_ifc_modify_tir_in_bits {
4354         u8         opcode[0x10];
4355         u8         reserved_at_10[0x10];
4356
4357         u8         reserved_at_20[0x10];
4358         u8         op_mod[0x10];
4359
4360         u8         reserved_at_40[0x8];
4361         u8         tirn[0x18];
4362
4363         u8         reserved_at_60[0x20];
4364
4365         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4366
4367         u8         reserved_at_c0[0x40];
4368
4369         struct mlx5_ifc_tirc_bits ctx;
4370 };
4371
4372 struct mlx5_ifc_modify_sq_out_bits {
4373         u8         status[0x8];
4374         u8         reserved_at_8[0x18];
4375
4376         u8         syndrome[0x20];
4377
4378         u8         reserved_at_40[0x40];
4379 };
4380
4381 struct mlx5_ifc_modify_sq_in_bits {
4382         u8         opcode[0x10];
4383         u8         reserved_at_10[0x10];
4384
4385         u8         reserved_at_20[0x10];
4386         u8         op_mod[0x10];
4387
4388         u8         sq_state[0x4];
4389         u8         reserved_at_44[0x4];
4390         u8         sqn[0x18];
4391
4392         u8         reserved_at_60[0x20];
4393
4394         u8         modify_bitmask[0x40];
4395
4396         u8         reserved_at_c0[0x40];
4397
4398         struct mlx5_ifc_sqc_bits ctx;
4399 };
4400
4401 struct mlx5_ifc_modify_rqt_out_bits {
4402         u8         status[0x8];
4403         u8         reserved_at_8[0x18];
4404
4405         u8         syndrome[0x20];
4406
4407         u8         reserved_at_40[0x40];
4408 };
4409
4410 struct mlx5_ifc_rqt_bitmask_bits {
4411         u8         reserved_at_0[0x20];
4412
4413         u8         reserved_at_20[0x1f];
4414         u8         rqn_list[0x1];
4415 };
4416
4417 struct mlx5_ifc_modify_rqt_in_bits {
4418         u8         opcode[0x10];
4419         u8         reserved_at_10[0x10];
4420
4421         u8         reserved_at_20[0x10];
4422         u8         op_mod[0x10];
4423
4424         u8         reserved_at_40[0x8];
4425         u8         rqtn[0x18];
4426
4427         u8         reserved_at_60[0x20];
4428
4429         struct mlx5_ifc_rqt_bitmask_bits bitmask;
4430
4431         u8         reserved_at_c0[0x40];
4432
4433         struct mlx5_ifc_rqtc_bits ctx;
4434 };
4435
4436 struct mlx5_ifc_modify_rq_out_bits {
4437         u8         status[0x8];
4438         u8         reserved_at_8[0x18];
4439
4440         u8         syndrome[0x20];
4441
4442         u8         reserved_at_40[0x40];
4443 };
4444
4445 struct mlx5_ifc_modify_rq_in_bits {
4446         u8         opcode[0x10];
4447         u8         reserved_at_10[0x10];
4448
4449         u8         reserved_at_20[0x10];
4450         u8         op_mod[0x10];
4451
4452         u8         rq_state[0x4];
4453         u8         reserved_at_44[0x4];
4454         u8         rqn[0x18];
4455
4456         u8         reserved_at_60[0x20];
4457
4458         u8         modify_bitmask[0x40];
4459
4460         u8         reserved_at_c0[0x40];
4461
4462         struct mlx5_ifc_rqc_bits ctx;
4463 };
4464
4465 struct mlx5_ifc_modify_rmp_out_bits {
4466         u8         status[0x8];
4467         u8         reserved_at_8[0x18];
4468
4469         u8         syndrome[0x20];
4470
4471         u8         reserved_at_40[0x40];
4472 };
4473
4474 struct mlx5_ifc_rmp_bitmask_bits {
4475         u8         reserved_at_0[0x20];
4476
4477         u8         reserved_at_20[0x1f];
4478         u8         lwm[0x1];
4479 };
4480
4481 struct mlx5_ifc_modify_rmp_in_bits {
4482         u8         opcode[0x10];
4483         u8         reserved_at_10[0x10];
4484
4485         u8         reserved_at_20[0x10];
4486         u8         op_mod[0x10];
4487
4488         u8         rmp_state[0x4];
4489         u8         reserved_at_44[0x4];
4490         u8         rmpn[0x18];
4491
4492         u8         reserved_at_60[0x20];
4493
4494         struct mlx5_ifc_rmp_bitmask_bits bitmask;
4495
4496         u8         reserved_at_c0[0x40];
4497
4498         struct mlx5_ifc_rmpc_bits ctx;
4499 };
4500
4501 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4502         u8         status[0x8];
4503         u8         reserved_at_8[0x18];
4504
4505         u8         syndrome[0x20];
4506
4507         u8         reserved_at_40[0x40];
4508 };
4509
4510 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4511         u8         reserved_at_0[0x19];
4512         u8         mtu[0x1];
4513         u8         change_event[0x1];
4514         u8         promisc[0x1];
4515         u8         permanent_address[0x1];
4516         u8         addresses_list[0x1];
4517         u8         roce_en[0x1];
4518         u8         reserved_at_1f[0x1];
4519 };
4520
4521 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4522         u8         opcode[0x10];
4523         u8         reserved_at_10[0x10];
4524
4525         u8         reserved_at_20[0x10];
4526         u8         op_mod[0x10];
4527
4528         u8         other_vport[0x1];
4529         u8         reserved_at_41[0xf];
4530         u8         vport_number[0x10];
4531
4532         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4533
4534         u8         reserved_at_80[0x780];
4535
4536         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4537 };
4538
4539 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4540         u8         status[0x8];
4541         u8         reserved_at_8[0x18];
4542
4543         u8         syndrome[0x20];
4544
4545         u8         reserved_at_40[0x40];
4546 };
4547
4548 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4549         u8         opcode[0x10];
4550         u8         reserved_at_10[0x10];
4551
4552         u8         reserved_at_20[0x10];
4553         u8         op_mod[0x10];
4554
4555         u8         other_vport[0x1];
4556         u8         reserved_at_41[0xb];
4557         u8         port_num[0x4];
4558         u8         vport_number[0x10];
4559
4560         u8         reserved_at_60[0x20];
4561
4562         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4563 };
4564
4565 struct mlx5_ifc_modify_cq_out_bits {
4566         u8         status[0x8];
4567         u8         reserved_at_8[0x18];
4568
4569         u8         syndrome[0x20];
4570
4571         u8         reserved_at_40[0x40];
4572 };
4573
4574 enum {
4575         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
4576         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
4577 };
4578
4579 struct mlx5_ifc_modify_cq_in_bits {
4580         u8         opcode[0x10];
4581         u8         reserved_at_10[0x10];
4582
4583         u8         reserved_at_20[0x10];
4584         u8         op_mod[0x10];
4585
4586         u8         reserved_at_40[0x8];
4587         u8         cqn[0x18];
4588
4589         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4590
4591         struct mlx5_ifc_cqc_bits cq_context;
4592
4593         u8         reserved_at_280[0x600];
4594
4595         u8         pas[0][0x40];
4596 };
4597
4598 struct mlx5_ifc_modify_cong_status_out_bits {
4599         u8         status[0x8];
4600         u8         reserved_at_8[0x18];
4601
4602         u8         syndrome[0x20];
4603
4604         u8         reserved_at_40[0x40];
4605 };
4606
4607 struct mlx5_ifc_modify_cong_status_in_bits {
4608         u8         opcode[0x10];
4609         u8         reserved_at_10[0x10];
4610
4611         u8         reserved_at_20[0x10];
4612         u8         op_mod[0x10];
4613
4614         u8         reserved_at_40[0x18];
4615         u8         priority[0x4];
4616         u8         cong_protocol[0x4];
4617
4618         u8         enable[0x1];
4619         u8         tag_enable[0x1];
4620         u8         reserved_at_62[0x1e];
4621 };
4622
4623 struct mlx5_ifc_modify_cong_params_out_bits {
4624         u8         status[0x8];
4625         u8         reserved_at_8[0x18];
4626
4627         u8         syndrome[0x20];
4628
4629         u8         reserved_at_40[0x40];
4630 };
4631
4632 struct mlx5_ifc_modify_cong_params_in_bits {
4633         u8         opcode[0x10];
4634         u8         reserved_at_10[0x10];
4635
4636         u8         reserved_at_20[0x10];
4637         u8         op_mod[0x10];
4638
4639         u8         reserved_at_40[0x1c];
4640         u8         cong_protocol[0x4];
4641
4642         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4643
4644         u8         reserved_at_80[0x80];
4645
4646         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4647 };
4648
4649 struct mlx5_ifc_manage_pages_out_bits {
4650         u8         status[0x8];
4651         u8         reserved_at_8[0x18];
4652
4653         u8         syndrome[0x20];
4654
4655         u8         output_num_entries[0x20];
4656
4657         u8         reserved_at_60[0x20];
4658
4659         u8         pas[0][0x40];
4660 };
4661
4662 enum {
4663         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
4664         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
4665         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
4666 };
4667
4668 struct mlx5_ifc_manage_pages_in_bits {
4669         u8         opcode[0x10];
4670         u8         reserved_at_10[0x10];
4671
4672         u8         reserved_at_20[0x10];
4673         u8         op_mod[0x10];
4674
4675         u8         reserved_at_40[0x10];
4676         u8         function_id[0x10];
4677
4678         u8         input_num_entries[0x20];
4679
4680         u8         pas[0][0x40];
4681 };
4682
4683 struct mlx5_ifc_mad_ifc_out_bits {
4684         u8         status[0x8];
4685         u8         reserved_at_8[0x18];
4686
4687         u8         syndrome[0x20];
4688
4689         u8         reserved_at_40[0x40];
4690
4691         u8         response_mad_packet[256][0x8];
4692 };
4693
4694 struct mlx5_ifc_mad_ifc_in_bits {
4695         u8         opcode[0x10];
4696         u8         reserved_at_10[0x10];
4697
4698         u8         reserved_at_20[0x10];
4699         u8         op_mod[0x10];
4700
4701         u8         remote_lid[0x10];
4702         u8         reserved_at_50[0x8];
4703         u8         port[0x8];
4704
4705         u8         reserved_at_60[0x20];
4706
4707         u8         mad[256][0x8];
4708 };
4709
4710 struct mlx5_ifc_init_hca_out_bits {
4711         u8         status[0x8];
4712         u8         reserved_at_8[0x18];
4713
4714         u8         syndrome[0x20];
4715
4716         u8         reserved_at_40[0x40];
4717 };
4718
4719 struct mlx5_ifc_init_hca_in_bits {
4720         u8         opcode[0x10];
4721         u8         reserved_at_10[0x10];
4722
4723         u8         reserved_at_20[0x10];
4724         u8         op_mod[0x10];
4725
4726         u8         reserved_at_40[0x40];
4727 };
4728
4729 struct mlx5_ifc_init2rtr_qp_out_bits {
4730         u8         status[0x8];
4731         u8         reserved_at_8[0x18];
4732
4733         u8         syndrome[0x20];
4734
4735         u8         reserved_at_40[0x40];
4736 };
4737
4738 struct mlx5_ifc_init2rtr_qp_in_bits {
4739         u8         opcode[0x10];
4740         u8         reserved_at_10[0x10];
4741
4742         u8         reserved_at_20[0x10];
4743         u8         op_mod[0x10];
4744
4745         u8         reserved_at_40[0x8];
4746         u8         qpn[0x18];
4747
4748         u8         reserved_at_60[0x20];
4749
4750         u8         opt_param_mask[0x20];
4751
4752         u8         reserved_at_a0[0x20];
4753
4754         struct mlx5_ifc_qpc_bits qpc;
4755
4756         u8         reserved_at_800[0x80];
4757 };
4758
4759 struct mlx5_ifc_init2init_qp_out_bits {
4760         u8         status[0x8];
4761         u8         reserved_at_8[0x18];
4762
4763         u8         syndrome[0x20];
4764
4765         u8         reserved_at_40[0x40];
4766 };
4767
4768 struct mlx5_ifc_init2init_qp_in_bits {
4769         u8         opcode[0x10];
4770         u8         reserved_at_10[0x10];
4771
4772         u8         reserved_at_20[0x10];
4773         u8         op_mod[0x10];
4774
4775         u8         reserved_at_40[0x8];
4776         u8         qpn[0x18];
4777
4778         u8         reserved_at_60[0x20];
4779
4780         u8         opt_param_mask[0x20];
4781
4782         u8         reserved_at_a0[0x20];
4783
4784         struct mlx5_ifc_qpc_bits qpc;
4785
4786         u8         reserved_at_800[0x80];
4787 };
4788
4789 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4790         u8         status[0x8];
4791         u8         reserved_at_8[0x18];
4792
4793         u8         syndrome[0x20];
4794
4795         u8         reserved_at_40[0x40];
4796
4797         u8         packet_headers_log[128][0x8];
4798
4799         u8         packet_syndrome[64][0x8];
4800 };
4801
4802 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4803         u8         opcode[0x10];
4804         u8         reserved_at_10[0x10];
4805
4806         u8         reserved_at_20[0x10];
4807         u8         op_mod[0x10];
4808
4809         u8         reserved_at_40[0x40];
4810 };
4811
4812 struct mlx5_ifc_gen_eqe_in_bits {
4813         u8         opcode[0x10];
4814         u8         reserved_at_10[0x10];
4815
4816         u8         reserved_at_20[0x10];
4817         u8         op_mod[0x10];
4818
4819         u8         reserved_at_40[0x18];
4820         u8         eq_number[0x8];
4821
4822         u8         reserved_at_60[0x20];
4823
4824         u8         eqe[64][0x8];
4825 };
4826
4827 struct mlx5_ifc_gen_eq_out_bits {
4828         u8         status[0x8];
4829         u8         reserved_at_8[0x18];
4830
4831         u8         syndrome[0x20];
4832
4833         u8         reserved_at_40[0x40];
4834 };
4835
4836 struct mlx5_ifc_enable_hca_out_bits {
4837         u8         status[0x8];
4838         u8         reserved_at_8[0x18];
4839
4840         u8         syndrome[0x20];
4841
4842         u8         reserved_at_40[0x20];
4843 };
4844
4845 struct mlx5_ifc_enable_hca_in_bits {
4846         u8         opcode[0x10];
4847         u8         reserved_at_10[0x10];
4848
4849         u8         reserved_at_20[0x10];
4850         u8         op_mod[0x10];
4851
4852         u8         reserved_at_40[0x10];
4853         u8         function_id[0x10];
4854
4855         u8         reserved_at_60[0x20];
4856 };
4857
4858 struct mlx5_ifc_drain_dct_out_bits {
4859         u8         status[0x8];
4860         u8         reserved_at_8[0x18];
4861
4862         u8         syndrome[0x20];
4863
4864         u8         reserved_at_40[0x40];
4865 };
4866
4867 struct mlx5_ifc_drain_dct_in_bits {
4868         u8         opcode[0x10];
4869         u8         reserved_at_10[0x10];
4870
4871         u8         reserved_at_20[0x10];
4872         u8         op_mod[0x10];
4873
4874         u8         reserved_at_40[0x8];
4875         u8         dctn[0x18];
4876
4877         u8         reserved_at_60[0x20];
4878 };
4879
4880 struct mlx5_ifc_disable_hca_out_bits {
4881         u8         status[0x8];
4882         u8         reserved_at_8[0x18];
4883
4884         u8         syndrome[0x20];
4885
4886         u8         reserved_at_40[0x20];
4887 };
4888
4889 struct mlx5_ifc_disable_hca_in_bits {
4890         u8         opcode[0x10];
4891         u8         reserved_at_10[0x10];
4892
4893         u8         reserved_at_20[0x10];
4894         u8         op_mod[0x10];
4895
4896         u8         reserved_at_40[0x10];
4897         u8         function_id[0x10];
4898
4899         u8         reserved_at_60[0x20];
4900 };
4901
4902 struct mlx5_ifc_detach_from_mcg_out_bits {
4903         u8         status[0x8];
4904         u8         reserved_at_8[0x18];
4905
4906         u8         syndrome[0x20];
4907
4908         u8         reserved_at_40[0x40];
4909 };
4910
4911 struct mlx5_ifc_detach_from_mcg_in_bits {
4912         u8         opcode[0x10];
4913         u8         reserved_at_10[0x10];
4914
4915         u8         reserved_at_20[0x10];
4916         u8         op_mod[0x10];
4917
4918         u8         reserved_at_40[0x8];
4919         u8         qpn[0x18];
4920
4921         u8         reserved_at_60[0x20];
4922
4923         u8         multicast_gid[16][0x8];
4924 };
4925
4926 struct mlx5_ifc_destroy_xrc_srq_out_bits {
4927         u8         status[0x8];
4928         u8         reserved_at_8[0x18];
4929
4930         u8         syndrome[0x20];
4931
4932         u8         reserved_at_40[0x40];
4933 };
4934
4935 struct mlx5_ifc_destroy_xrc_srq_in_bits {
4936         u8         opcode[0x10];
4937         u8         reserved_at_10[0x10];
4938
4939         u8         reserved_at_20[0x10];
4940         u8         op_mod[0x10];
4941
4942         u8         reserved_at_40[0x8];
4943         u8         xrc_srqn[0x18];
4944
4945         u8         reserved_at_60[0x20];
4946 };
4947
4948 struct mlx5_ifc_destroy_tis_out_bits {
4949         u8         status[0x8];
4950         u8         reserved_at_8[0x18];
4951
4952         u8         syndrome[0x20];
4953
4954         u8         reserved_at_40[0x40];
4955 };
4956
4957 struct mlx5_ifc_destroy_tis_in_bits {
4958         u8         opcode[0x10];
4959         u8         reserved_at_10[0x10];
4960
4961         u8         reserved_at_20[0x10];
4962         u8         op_mod[0x10];
4963
4964         u8         reserved_at_40[0x8];
4965         u8         tisn[0x18];
4966
4967         u8         reserved_at_60[0x20];
4968 };
4969
4970 struct mlx5_ifc_destroy_tir_out_bits {
4971         u8         status[0x8];
4972         u8         reserved_at_8[0x18];
4973
4974         u8         syndrome[0x20];
4975
4976         u8         reserved_at_40[0x40];
4977 };
4978
4979 struct mlx5_ifc_destroy_tir_in_bits {
4980         u8         opcode[0x10];
4981         u8         reserved_at_10[0x10];
4982
4983         u8         reserved_at_20[0x10];
4984         u8         op_mod[0x10];
4985
4986         u8         reserved_at_40[0x8];
4987         u8         tirn[0x18];
4988
4989         u8         reserved_at_60[0x20];
4990 };
4991
4992 struct mlx5_ifc_destroy_srq_out_bits {
4993         u8         status[0x8];
4994         u8         reserved_at_8[0x18];
4995
4996         u8         syndrome[0x20];
4997
4998         u8         reserved_at_40[0x40];
4999 };
5000
5001 struct mlx5_ifc_destroy_srq_in_bits {
5002         u8         opcode[0x10];
5003         u8         reserved_at_10[0x10];
5004
5005         u8         reserved_at_20[0x10];
5006         u8         op_mod[0x10];
5007
5008         u8         reserved_at_40[0x8];
5009         u8         srqn[0x18];
5010
5011         u8         reserved_at_60[0x20];
5012 };
5013
5014 struct mlx5_ifc_destroy_sq_out_bits {
5015         u8         status[0x8];
5016         u8         reserved_at_8[0x18];
5017
5018         u8         syndrome[0x20];
5019
5020         u8         reserved_at_40[0x40];
5021 };
5022
5023 struct mlx5_ifc_destroy_sq_in_bits {
5024         u8         opcode[0x10];
5025         u8         reserved_at_10[0x10];
5026
5027         u8         reserved_at_20[0x10];
5028         u8         op_mod[0x10];
5029
5030         u8         reserved_at_40[0x8];
5031         u8         sqn[0x18];
5032
5033         u8         reserved_at_60[0x20];
5034 };
5035
5036 struct mlx5_ifc_destroy_rqt_out_bits {
5037         u8         status[0x8];
5038         u8         reserved_at_8[0x18];
5039
5040         u8         syndrome[0x20];
5041
5042         u8         reserved_at_40[0x40];
5043 };
5044
5045 struct mlx5_ifc_destroy_rqt_in_bits {
5046         u8         opcode[0x10];
5047         u8         reserved_at_10[0x10];
5048
5049         u8         reserved_at_20[0x10];
5050         u8         op_mod[0x10];
5051
5052         u8         reserved_at_40[0x8];
5053         u8         rqtn[0x18];
5054
5055         u8         reserved_at_60[0x20];
5056 };
5057
5058 struct mlx5_ifc_destroy_rq_out_bits {
5059         u8         status[0x8];
5060         u8         reserved_at_8[0x18];
5061
5062         u8         syndrome[0x20];
5063
5064         u8         reserved_at_40[0x40];
5065 };
5066
5067 struct mlx5_ifc_destroy_rq_in_bits {
5068         u8         opcode[0x10];
5069         u8         reserved_at_10[0x10];
5070
5071         u8         reserved_at_20[0x10];
5072         u8         op_mod[0x10];
5073
5074         u8         reserved_at_40[0x8];
5075         u8         rqn[0x18];
5076
5077         u8         reserved_at_60[0x20];
5078 };
5079
5080 struct mlx5_ifc_destroy_rmp_out_bits {
5081         u8         status[0x8];
5082         u8         reserved_at_8[0x18];
5083
5084         u8         syndrome[0x20];
5085
5086         u8         reserved_at_40[0x40];
5087 };
5088
5089 struct mlx5_ifc_destroy_rmp_in_bits {
5090         u8         opcode[0x10];
5091         u8         reserved_at_10[0x10];
5092
5093         u8         reserved_at_20[0x10];
5094         u8         op_mod[0x10];
5095
5096         u8         reserved_at_40[0x8];
5097         u8         rmpn[0x18];
5098
5099         u8         reserved_at_60[0x20];
5100 };
5101
5102 struct mlx5_ifc_destroy_qp_out_bits {
5103         u8         status[0x8];
5104         u8         reserved_at_8[0x18];
5105
5106         u8         syndrome[0x20];
5107
5108         u8         reserved_at_40[0x40];
5109 };
5110
5111 struct mlx5_ifc_destroy_qp_in_bits {
5112         u8         opcode[0x10];
5113         u8         reserved_at_10[0x10];
5114
5115         u8         reserved_at_20[0x10];
5116         u8         op_mod[0x10];
5117
5118         u8         reserved_at_40[0x8];
5119         u8         qpn[0x18];
5120
5121         u8         reserved_at_60[0x20];
5122 };
5123
5124 struct mlx5_ifc_destroy_psv_out_bits {
5125         u8         status[0x8];
5126         u8         reserved_at_8[0x18];
5127
5128         u8         syndrome[0x20];
5129
5130         u8         reserved_at_40[0x40];
5131 };
5132
5133 struct mlx5_ifc_destroy_psv_in_bits {
5134         u8         opcode[0x10];
5135         u8         reserved_at_10[0x10];
5136
5137         u8         reserved_at_20[0x10];
5138         u8         op_mod[0x10];
5139
5140         u8         reserved_at_40[0x8];
5141         u8         psvn[0x18];
5142
5143         u8         reserved_at_60[0x20];
5144 };
5145
5146 struct mlx5_ifc_destroy_mkey_out_bits {
5147         u8         status[0x8];
5148         u8         reserved_at_8[0x18];
5149
5150         u8         syndrome[0x20];
5151
5152         u8         reserved_at_40[0x40];
5153 };
5154
5155 struct mlx5_ifc_destroy_mkey_in_bits {
5156         u8         opcode[0x10];
5157         u8         reserved_at_10[0x10];
5158
5159         u8         reserved_at_20[0x10];
5160         u8         op_mod[0x10];
5161
5162         u8         reserved_at_40[0x8];
5163         u8         mkey_index[0x18];
5164
5165         u8         reserved_at_60[0x20];
5166 };
5167
5168 struct mlx5_ifc_destroy_flow_table_out_bits {
5169         u8         status[0x8];
5170         u8         reserved_at_8[0x18];
5171
5172         u8         syndrome[0x20];
5173
5174         u8         reserved_at_40[0x40];
5175 };
5176
5177 struct mlx5_ifc_destroy_flow_table_in_bits {
5178         u8         opcode[0x10];
5179         u8         reserved_at_10[0x10];
5180
5181         u8         reserved_at_20[0x10];
5182         u8         op_mod[0x10];
5183
5184         u8         reserved_at_40[0x40];
5185
5186         u8         table_type[0x8];
5187         u8         reserved_at_88[0x18];
5188
5189         u8         reserved_at_a0[0x8];
5190         u8         table_id[0x18];
5191
5192         u8         reserved_at_c0[0x140];
5193 };
5194
5195 struct mlx5_ifc_destroy_flow_group_out_bits {
5196         u8         status[0x8];
5197         u8         reserved_at_8[0x18];
5198
5199         u8         syndrome[0x20];
5200
5201         u8         reserved_at_40[0x40];
5202 };
5203
5204 struct mlx5_ifc_destroy_flow_group_in_bits {
5205         u8         opcode[0x10];
5206         u8         reserved_at_10[0x10];
5207
5208         u8         reserved_at_20[0x10];
5209         u8         op_mod[0x10];
5210
5211         u8         reserved_at_40[0x40];
5212
5213         u8         table_type[0x8];
5214         u8         reserved_at_88[0x18];
5215
5216         u8         reserved_at_a0[0x8];
5217         u8         table_id[0x18];
5218
5219         u8         group_id[0x20];
5220
5221         u8         reserved_at_e0[0x120];
5222 };
5223
5224 struct mlx5_ifc_destroy_eq_out_bits {
5225         u8         status[0x8];
5226         u8         reserved_at_8[0x18];
5227
5228         u8         syndrome[0x20];
5229
5230         u8         reserved_at_40[0x40];
5231 };
5232
5233 struct mlx5_ifc_destroy_eq_in_bits {
5234         u8         opcode[0x10];
5235         u8         reserved_at_10[0x10];
5236
5237         u8         reserved_at_20[0x10];
5238         u8         op_mod[0x10];
5239
5240         u8         reserved_at_40[0x18];
5241         u8         eq_number[0x8];
5242
5243         u8         reserved_at_60[0x20];
5244 };
5245
5246 struct mlx5_ifc_destroy_dct_out_bits {
5247         u8         status[0x8];
5248         u8         reserved_at_8[0x18];
5249
5250         u8         syndrome[0x20];
5251
5252         u8         reserved_at_40[0x40];
5253 };
5254
5255 struct mlx5_ifc_destroy_dct_in_bits {
5256         u8         opcode[0x10];
5257         u8         reserved_at_10[0x10];
5258
5259         u8         reserved_at_20[0x10];
5260         u8         op_mod[0x10];
5261
5262         u8         reserved_at_40[0x8];
5263         u8         dctn[0x18];
5264
5265         u8         reserved_at_60[0x20];
5266 };
5267
5268 struct mlx5_ifc_destroy_cq_out_bits {
5269         u8         status[0x8];
5270         u8         reserved_at_8[0x18];
5271
5272         u8         syndrome[0x20];
5273
5274         u8         reserved_at_40[0x40];
5275 };
5276
5277 struct mlx5_ifc_destroy_cq_in_bits {
5278         u8         opcode[0x10];
5279         u8         reserved_at_10[0x10];
5280
5281         u8         reserved_at_20[0x10];
5282         u8         op_mod[0x10];
5283
5284         u8         reserved_at_40[0x8];
5285         u8         cqn[0x18];
5286
5287         u8         reserved_at_60[0x20];
5288 };
5289
5290 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5291         u8         status[0x8];
5292         u8         reserved_at_8[0x18];
5293
5294         u8         syndrome[0x20];
5295
5296         u8         reserved_at_40[0x40];
5297 };
5298
5299 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5300         u8         opcode[0x10];
5301         u8         reserved_at_10[0x10];
5302
5303         u8         reserved_at_20[0x10];
5304         u8         op_mod[0x10];
5305
5306         u8         reserved_at_40[0x20];
5307
5308         u8         reserved_at_60[0x10];
5309         u8         vxlan_udp_port[0x10];
5310 };
5311
5312 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5313         u8         status[0x8];
5314         u8         reserved_at_8[0x18];
5315
5316         u8         syndrome[0x20];
5317
5318         u8         reserved_at_40[0x40];
5319 };
5320
5321 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5322         u8         opcode[0x10];
5323         u8         reserved_at_10[0x10];
5324
5325         u8         reserved_at_20[0x10];
5326         u8         op_mod[0x10];
5327
5328         u8         reserved_at_40[0x60];
5329
5330         u8         reserved_at_a0[0x8];
5331         u8         table_index[0x18];
5332
5333         u8         reserved_at_c0[0x140];
5334 };
5335
5336 struct mlx5_ifc_delete_fte_out_bits {
5337         u8         status[0x8];
5338         u8         reserved_at_8[0x18];
5339
5340         u8         syndrome[0x20];
5341
5342         u8         reserved_at_40[0x40];
5343 };
5344
5345 struct mlx5_ifc_delete_fte_in_bits {
5346         u8         opcode[0x10];
5347         u8         reserved_at_10[0x10];
5348
5349         u8         reserved_at_20[0x10];
5350         u8         op_mod[0x10];
5351
5352         u8         reserved_at_40[0x40];
5353
5354         u8         table_type[0x8];
5355         u8         reserved_at_88[0x18];
5356
5357         u8         reserved_at_a0[0x8];
5358         u8         table_id[0x18];
5359
5360         u8         reserved_at_c0[0x40];
5361
5362         u8         flow_index[0x20];
5363
5364         u8         reserved_at_120[0xe0];
5365 };
5366
5367 struct mlx5_ifc_dealloc_xrcd_out_bits {
5368         u8         status[0x8];
5369         u8         reserved_at_8[0x18];
5370
5371         u8         syndrome[0x20];
5372
5373         u8         reserved_at_40[0x40];
5374 };
5375
5376 struct mlx5_ifc_dealloc_xrcd_in_bits {
5377         u8         opcode[0x10];
5378         u8         reserved_at_10[0x10];
5379
5380         u8         reserved_at_20[0x10];
5381         u8         op_mod[0x10];
5382
5383         u8         reserved_at_40[0x8];
5384         u8         xrcd[0x18];
5385
5386         u8         reserved_at_60[0x20];
5387 };
5388
5389 struct mlx5_ifc_dealloc_uar_out_bits {
5390         u8         status[0x8];
5391         u8         reserved_at_8[0x18];
5392
5393         u8         syndrome[0x20];
5394
5395         u8         reserved_at_40[0x40];
5396 };
5397
5398 struct mlx5_ifc_dealloc_uar_in_bits {
5399         u8         opcode[0x10];
5400         u8         reserved_at_10[0x10];
5401
5402         u8         reserved_at_20[0x10];
5403         u8         op_mod[0x10];
5404
5405         u8         reserved_at_40[0x8];
5406         u8         uar[0x18];
5407
5408         u8         reserved_at_60[0x20];
5409 };
5410
5411 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5412         u8         status[0x8];
5413         u8         reserved_at_8[0x18];
5414
5415         u8         syndrome[0x20];
5416
5417         u8         reserved_at_40[0x40];
5418 };
5419
5420 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5421         u8         opcode[0x10];
5422         u8         reserved_at_10[0x10];
5423
5424         u8         reserved_at_20[0x10];
5425         u8         op_mod[0x10];
5426
5427         u8         reserved_at_40[0x8];
5428         u8         transport_domain[0x18];
5429
5430         u8         reserved_at_60[0x20];
5431 };
5432
5433 struct mlx5_ifc_dealloc_q_counter_out_bits {
5434         u8         status[0x8];
5435         u8         reserved_at_8[0x18];
5436
5437         u8         syndrome[0x20];
5438
5439         u8         reserved_at_40[0x40];
5440 };
5441
5442 struct mlx5_ifc_dealloc_q_counter_in_bits {
5443         u8         opcode[0x10];
5444         u8         reserved_at_10[0x10];
5445
5446         u8         reserved_at_20[0x10];
5447         u8         op_mod[0x10];
5448
5449         u8         reserved_at_40[0x18];
5450         u8         counter_set_id[0x8];
5451
5452         u8         reserved_at_60[0x20];
5453 };
5454
5455 struct mlx5_ifc_dealloc_pd_out_bits {
5456         u8         status[0x8];
5457         u8         reserved_at_8[0x18];
5458
5459         u8         syndrome[0x20];
5460
5461         u8         reserved_at_40[0x40];
5462 };
5463
5464 struct mlx5_ifc_dealloc_pd_in_bits {
5465         u8         opcode[0x10];
5466         u8         reserved_at_10[0x10];
5467
5468         u8         reserved_at_20[0x10];
5469         u8         op_mod[0x10];
5470
5471         u8         reserved_at_40[0x8];
5472         u8         pd[0x18];
5473
5474         u8         reserved_at_60[0x20];
5475 };
5476
5477 struct mlx5_ifc_create_xrc_srq_out_bits {
5478         u8         status[0x8];
5479         u8         reserved_at_8[0x18];
5480
5481         u8         syndrome[0x20];
5482
5483         u8         reserved_at_40[0x8];
5484         u8         xrc_srqn[0x18];
5485
5486         u8         reserved_at_60[0x20];
5487 };
5488
5489 struct mlx5_ifc_create_xrc_srq_in_bits {
5490         u8         opcode[0x10];
5491         u8         reserved_at_10[0x10];
5492
5493         u8         reserved_at_20[0x10];
5494         u8         op_mod[0x10];
5495
5496         u8         reserved_at_40[0x40];
5497
5498         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5499
5500         u8         reserved_at_280[0x600];
5501
5502         u8         pas[0][0x40];
5503 };
5504
5505 struct mlx5_ifc_create_tis_out_bits {
5506         u8         status[0x8];
5507         u8         reserved_at_8[0x18];
5508
5509         u8         syndrome[0x20];
5510
5511         u8         reserved_at_40[0x8];
5512         u8         tisn[0x18];
5513
5514         u8         reserved_at_60[0x20];
5515 };
5516
5517 struct mlx5_ifc_create_tis_in_bits {
5518         u8         opcode[0x10];
5519         u8         reserved_at_10[0x10];
5520
5521         u8         reserved_at_20[0x10];
5522         u8         op_mod[0x10];
5523
5524         u8         reserved_at_40[0xc0];
5525
5526         struct mlx5_ifc_tisc_bits ctx;
5527 };
5528
5529 struct mlx5_ifc_create_tir_out_bits {
5530         u8         status[0x8];
5531         u8         reserved_at_8[0x18];
5532
5533         u8         syndrome[0x20];
5534
5535         u8         reserved_at_40[0x8];
5536         u8         tirn[0x18];
5537
5538         u8         reserved_at_60[0x20];
5539 };
5540
5541 struct mlx5_ifc_create_tir_in_bits {
5542         u8         opcode[0x10];
5543         u8         reserved_at_10[0x10];
5544
5545         u8         reserved_at_20[0x10];
5546         u8         op_mod[0x10];
5547
5548         u8         reserved_at_40[0xc0];
5549
5550         struct mlx5_ifc_tirc_bits ctx;
5551 };
5552
5553 struct mlx5_ifc_create_srq_out_bits {
5554         u8         status[0x8];
5555         u8         reserved_at_8[0x18];
5556
5557         u8         syndrome[0x20];
5558
5559         u8         reserved_at_40[0x8];
5560         u8         srqn[0x18];
5561
5562         u8         reserved_at_60[0x20];
5563 };
5564
5565 struct mlx5_ifc_create_srq_in_bits {
5566         u8         opcode[0x10];
5567         u8         reserved_at_10[0x10];
5568
5569         u8         reserved_at_20[0x10];
5570         u8         op_mod[0x10];
5571
5572         u8         reserved_at_40[0x40];
5573
5574         struct mlx5_ifc_srqc_bits srq_context_entry;
5575
5576         u8         reserved_at_280[0x600];
5577
5578         u8         pas[0][0x40];
5579 };
5580
5581 struct mlx5_ifc_create_sq_out_bits {
5582         u8         status[0x8];
5583         u8         reserved_at_8[0x18];
5584
5585         u8         syndrome[0x20];
5586
5587         u8         reserved_at_40[0x8];
5588         u8         sqn[0x18];
5589
5590         u8         reserved_at_60[0x20];
5591 };
5592
5593 struct mlx5_ifc_create_sq_in_bits {
5594         u8         opcode[0x10];
5595         u8         reserved_at_10[0x10];
5596
5597         u8         reserved_at_20[0x10];
5598         u8         op_mod[0x10];
5599
5600         u8         reserved_at_40[0xc0];
5601
5602         struct mlx5_ifc_sqc_bits ctx;
5603 };
5604
5605 struct mlx5_ifc_create_rqt_out_bits {
5606         u8         status[0x8];
5607         u8         reserved_at_8[0x18];
5608
5609         u8         syndrome[0x20];
5610
5611         u8         reserved_at_40[0x8];
5612         u8         rqtn[0x18];
5613
5614         u8         reserved_at_60[0x20];
5615 };
5616
5617 struct mlx5_ifc_create_rqt_in_bits {
5618         u8         opcode[0x10];
5619         u8         reserved_at_10[0x10];
5620
5621         u8         reserved_at_20[0x10];
5622         u8         op_mod[0x10];
5623
5624         u8         reserved_at_40[0xc0];
5625
5626         struct mlx5_ifc_rqtc_bits rqt_context;
5627 };
5628
5629 struct mlx5_ifc_create_rq_out_bits {
5630         u8         status[0x8];
5631         u8         reserved_at_8[0x18];
5632
5633         u8         syndrome[0x20];
5634
5635         u8         reserved_at_40[0x8];
5636         u8         rqn[0x18];
5637
5638         u8         reserved_at_60[0x20];
5639 };
5640
5641 struct mlx5_ifc_create_rq_in_bits {
5642         u8         opcode[0x10];
5643         u8         reserved_at_10[0x10];
5644
5645         u8         reserved_at_20[0x10];
5646         u8         op_mod[0x10];
5647
5648         u8         reserved_at_40[0xc0];
5649
5650         struct mlx5_ifc_rqc_bits ctx;
5651 };
5652
5653 struct mlx5_ifc_create_rmp_out_bits {
5654         u8         status[0x8];
5655         u8         reserved_at_8[0x18];
5656
5657         u8         syndrome[0x20];
5658
5659         u8         reserved_at_40[0x8];
5660         u8         rmpn[0x18];
5661
5662         u8         reserved_at_60[0x20];
5663 };
5664
5665 struct mlx5_ifc_create_rmp_in_bits {
5666         u8         opcode[0x10];
5667         u8         reserved_at_10[0x10];
5668
5669         u8         reserved_at_20[0x10];
5670         u8         op_mod[0x10];
5671
5672         u8         reserved_at_40[0xc0];
5673
5674         struct mlx5_ifc_rmpc_bits ctx;
5675 };
5676
5677 struct mlx5_ifc_create_qp_out_bits {
5678         u8         status[0x8];
5679         u8         reserved_at_8[0x18];
5680
5681         u8         syndrome[0x20];
5682
5683         u8         reserved_at_40[0x8];
5684         u8         qpn[0x18];
5685
5686         u8         reserved_at_60[0x20];
5687 };
5688
5689 struct mlx5_ifc_create_qp_in_bits {
5690         u8         opcode[0x10];
5691         u8         reserved_at_10[0x10];
5692
5693         u8         reserved_at_20[0x10];
5694         u8         op_mod[0x10];
5695
5696         u8         reserved_at_40[0x40];
5697
5698         u8         opt_param_mask[0x20];
5699
5700         u8         reserved_at_a0[0x20];
5701
5702         struct mlx5_ifc_qpc_bits qpc;
5703
5704         u8         reserved_at_800[0x80];
5705
5706         u8         pas[0][0x40];
5707 };
5708
5709 struct mlx5_ifc_create_psv_out_bits {
5710         u8         status[0x8];
5711         u8         reserved_at_8[0x18];
5712
5713         u8         syndrome[0x20];
5714
5715         u8         reserved_at_40[0x40];
5716
5717         u8         reserved_at_80[0x8];
5718         u8         psv0_index[0x18];
5719
5720         u8         reserved_at_a0[0x8];
5721         u8         psv1_index[0x18];
5722
5723         u8         reserved_at_c0[0x8];
5724         u8         psv2_index[0x18];
5725
5726         u8         reserved_at_e0[0x8];
5727         u8         psv3_index[0x18];
5728 };
5729
5730 struct mlx5_ifc_create_psv_in_bits {
5731         u8         opcode[0x10];
5732         u8         reserved_at_10[0x10];
5733
5734         u8         reserved_at_20[0x10];
5735         u8         op_mod[0x10];
5736
5737         u8         num_psv[0x4];
5738         u8         reserved_at_44[0x4];
5739         u8         pd[0x18];
5740
5741         u8         reserved_at_60[0x20];
5742 };
5743
5744 struct mlx5_ifc_create_mkey_out_bits {
5745         u8         status[0x8];
5746         u8         reserved_at_8[0x18];
5747
5748         u8         syndrome[0x20];
5749
5750         u8         reserved_at_40[0x8];
5751         u8         mkey_index[0x18];
5752
5753         u8         reserved_at_60[0x20];
5754 };
5755
5756 struct mlx5_ifc_create_mkey_in_bits {
5757         u8         opcode[0x10];
5758         u8         reserved_at_10[0x10];
5759
5760         u8         reserved_at_20[0x10];
5761         u8         op_mod[0x10];
5762
5763         u8         reserved_at_40[0x20];
5764
5765         u8         pg_access[0x1];
5766         u8         reserved_at_61[0x1f];
5767
5768         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5769
5770         u8         reserved_at_280[0x80];
5771
5772         u8         translations_octword_actual_size[0x20];
5773
5774         u8         reserved_at_320[0x560];
5775
5776         u8         klm_pas_mtt[0][0x20];
5777 };
5778
5779 struct mlx5_ifc_create_flow_table_out_bits {
5780         u8         status[0x8];
5781         u8         reserved_at_8[0x18];
5782
5783         u8         syndrome[0x20];
5784
5785         u8         reserved_at_40[0x8];
5786         u8         table_id[0x18];
5787
5788         u8         reserved_at_60[0x20];
5789 };
5790
5791 struct mlx5_ifc_create_flow_table_in_bits {
5792         u8         opcode[0x10];
5793         u8         reserved_at_10[0x10];
5794
5795         u8         reserved_at_20[0x10];
5796         u8         op_mod[0x10];
5797
5798         u8         reserved_at_40[0x40];
5799
5800         u8         table_type[0x8];
5801         u8         reserved_at_88[0x18];
5802
5803         u8         reserved_at_a0[0x20];
5804
5805         u8         reserved_at_c0[0x4];
5806         u8         table_miss_mode[0x4];
5807         u8         level[0x8];
5808         u8         reserved_at_d0[0x8];
5809         u8         log_size[0x8];
5810
5811         u8         reserved_at_e0[0x8];
5812         u8         table_miss_id[0x18];
5813
5814         u8         reserved_at_100[0x100];
5815 };
5816
5817 struct mlx5_ifc_create_flow_group_out_bits {
5818         u8         status[0x8];
5819         u8         reserved_at_8[0x18];
5820
5821         u8         syndrome[0x20];
5822
5823         u8         reserved_at_40[0x8];
5824         u8         group_id[0x18];
5825
5826         u8         reserved_at_60[0x20];
5827 };
5828
5829 enum {
5830         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5831         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5832         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5833 };
5834
5835 struct mlx5_ifc_create_flow_group_in_bits {
5836         u8         opcode[0x10];
5837         u8         reserved_at_10[0x10];
5838
5839         u8         reserved_at_20[0x10];
5840         u8         op_mod[0x10];
5841
5842         u8         reserved_at_40[0x40];
5843
5844         u8         table_type[0x8];
5845         u8         reserved_at_88[0x18];
5846
5847         u8         reserved_at_a0[0x8];
5848         u8         table_id[0x18];
5849
5850         u8         reserved_at_c0[0x20];
5851
5852         u8         start_flow_index[0x20];
5853
5854         u8         reserved_at_100[0x20];
5855
5856         u8         end_flow_index[0x20];
5857
5858         u8         reserved_at_140[0xa0];
5859
5860         u8         reserved_at_1e0[0x18];
5861         u8         match_criteria_enable[0x8];
5862
5863         struct mlx5_ifc_fte_match_param_bits match_criteria;
5864
5865         u8         reserved_at_1200[0xe00];
5866 };
5867
5868 struct mlx5_ifc_create_eq_out_bits {
5869         u8         status[0x8];
5870         u8         reserved_at_8[0x18];
5871
5872         u8         syndrome[0x20];
5873
5874         u8         reserved_at_40[0x18];
5875         u8         eq_number[0x8];
5876
5877         u8         reserved_at_60[0x20];
5878 };
5879
5880 struct mlx5_ifc_create_eq_in_bits {
5881         u8         opcode[0x10];
5882         u8         reserved_at_10[0x10];
5883
5884         u8         reserved_at_20[0x10];
5885         u8         op_mod[0x10];
5886
5887         u8         reserved_at_40[0x40];
5888
5889         struct mlx5_ifc_eqc_bits eq_context_entry;
5890
5891         u8         reserved_at_280[0x40];
5892
5893         u8         event_bitmask[0x40];
5894
5895         u8         reserved_at_300[0x580];
5896
5897         u8         pas[0][0x40];
5898 };
5899
5900 struct mlx5_ifc_create_dct_out_bits {
5901         u8         status[0x8];
5902         u8         reserved_at_8[0x18];
5903
5904         u8         syndrome[0x20];
5905
5906         u8         reserved_at_40[0x8];
5907         u8         dctn[0x18];
5908
5909         u8         reserved_at_60[0x20];
5910 };
5911
5912 struct mlx5_ifc_create_dct_in_bits {
5913         u8         opcode[0x10];
5914         u8         reserved_at_10[0x10];
5915
5916         u8         reserved_at_20[0x10];
5917         u8         op_mod[0x10];
5918
5919         u8         reserved_at_40[0x40];
5920
5921         struct mlx5_ifc_dctc_bits dct_context_entry;
5922
5923         u8         reserved_at_280[0x180];
5924 };
5925
5926 struct mlx5_ifc_create_cq_out_bits {
5927         u8         status[0x8];
5928         u8         reserved_at_8[0x18];
5929
5930         u8         syndrome[0x20];
5931
5932         u8         reserved_at_40[0x8];
5933         u8         cqn[0x18];
5934
5935         u8         reserved_at_60[0x20];
5936 };
5937
5938 struct mlx5_ifc_create_cq_in_bits {
5939         u8         opcode[0x10];
5940         u8         reserved_at_10[0x10];
5941
5942         u8         reserved_at_20[0x10];
5943         u8         op_mod[0x10];
5944
5945         u8         reserved_at_40[0x40];
5946
5947         struct mlx5_ifc_cqc_bits cq_context;
5948
5949         u8         reserved_at_280[0x600];
5950
5951         u8         pas[0][0x40];
5952 };
5953
5954 struct mlx5_ifc_config_int_moderation_out_bits {
5955         u8         status[0x8];
5956         u8         reserved_at_8[0x18];
5957
5958         u8         syndrome[0x20];
5959
5960         u8         reserved_at_40[0x4];
5961         u8         min_delay[0xc];
5962         u8         int_vector[0x10];
5963
5964         u8         reserved_at_60[0x20];
5965 };
5966
5967 enum {
5968         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
5969         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
5970 };
5971
5972 struct mlx5_ifc_config_int_moderation_in_bits {
5973         u8         opcode[0x10];
5974         u8         reserved_at_10[0x10];
5975
5976         u8         reserved_at_20[0x10];
5977         u8         op_mod[0x10];
5978
5979         u8         reserved_at_40[0x4];
5980         u8         min_delay[0xc];
5981         u8         int_vector[0x10];
5982
5983         u8         reserved_at_60[0x20];
5984 };
5985
5986 struct mlx5_ifc_attach_to_mcg_out_bits {
5987         u8         status[0x8];
5988         u8         reserved_at_8[0x18];
5989
5990         u8         syndrome[0x20];
5991
5992         u8         reserved_at_40[0x40];
5993 };
5994
5995 struct mlx5_ifc_attach_to_mcg_in_bits {
5996         u8         opcode[0x10];
5997         u8         reserved_at_10[0x10];
5998
5999         u8         reserved_at_20[0x10];
6000         u8         op_mod[0x10];
6001
6002         u8         reserved_at_40[0x8];
6003         u8         qpn[0x18];
6004
6005         u8         reserved_at_60[0x20];
6006
6007         u8         multicast_gid[16][0x8];
6008 };
6009
6010 struct mlx5_ifc_arm_xrc_srq_out_bits {
6011         u8         status[0x8];
6012         u8         reserved_at_8[0x18];
6013
6014         u8         syndrome[0x20];
6015
6016         u8         reserved_at_40[0x40];
6017 };
6018
6019 enum {
6020         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
6021 };
6022
6023 struct mlx5_ifc_arm_xrc_srq_in_bits {
6024         u8         opcode[0x10];
6025         u8         reserved_at_10[0x10];
6026
6027         u8         reserved_at_20[0x10];
6028         u8         op_mod[0x10];
6029
6030         u8         reserved_at_40[0x8];
6031         u8         xrc_srqn[0x18];
6032
6033         u8         reserved_at_60[0x10];
6034         u8         lwm[0x10];
6035 };
6036
6037 struct mlx5_ifc_arm_rq_out_bits {
6038         u8         status[0x8];
6039         u8         reserved_at_8[0x18];
6040
6041         u8         syndrome[0x20];
6042
6043         u8         reserved_at_40[0x40];
6044 };
6045
6046 enum {
6047         MLX5_ARM_RQ_IN_OP_MOD_SRQ_  = 0x1,
6048 };
6049
6050 struct mlx5_ifc_arm_rq_in_bits {
6051         u8         opcode[0x10];
6052         u8         reserved_at_10[0x10];
6053
6054         u8         reserved_at_20[0x10];
6055         u8         op_mod[0x10];
6056
6057         u8         reserved_at_40[0x8];
6058         u8         srq_number[0x18];
6059
6060         u8         reserved_at_60[0x10];
6061         u8         lwm[0x10];
6062 };
6063
6064 struct mlx5_ifc_arm_dct_out_bits {
6065         u8         status[0x8];
6066         u8         reserved_at_8[0x18];
6067
6068         u8         syndrome[0x20];
6069
6070         u8         reserved_at_40[0x40];
6071 };
6072
6073 struct mlx5_ifc_arm_dct_in_bits {
6074         u8         opcode[0x10];
6075         u8         reserved_at_10[0x10];
6076
6077         u8         reserved_at_20[0x10];
6078         u8         op_mod[0x10];
6079
6080         u8         reserved_at_40[0x8];
6081         u8         dct_number[0x18];
6082
6083         u8         reserved_at_60[0x20];
6084 };
6085
6086 struct mlx5_ifc_alloc_xrcd_out_bits {
6087         u8         status[0x8];
6088         u8         reserved_at_8[0x18];
6089
6090         u8         syndrome[0x20];
6091
6092         u8         reserved_at_40[0x8];
6093         u8         xrcd[0x18];
6094
6095         u8         reserved_at_60[0x20];
6096 };
6097
6098 struct mlx5_ifc_alloc_xrcd_in_bits {
6099         u8         opcode[0x10];
6100         u8         reserved_at_10[0x10];
6101
6102         u8         reserved_at_20[0x10];
6103         u8         op_mod[0x10];
6104
6105         u8         reserved_at_40[0x40];
6106 };
6107
6108 struct mlx5_ifc_alloc_uar_out_bits {
6109         u8         status[0x8];
6110         u8         reserved_at_8[0x18];
6111
6112         u8         syndrome[0x20];
6113
6114         u8         reserved_at_40[0x8];
6115         u8         uar[0x18];
6116
6117         u8         reserved_at_60[0x20];
6118 };
6119
6120 struct mlx5_ifc_alloc_uar_in_bits {
6121         u8         opcode[0x10];
6122         u8         reserved_at_10[0x10];
6123
6124         u8         reserved_at_20[0x10];
6125         u8         op_mod[0x10];
6126
6127         u8         reserved_at_40[0x40];
6128 };
6129
6130 struct mlx5_ifc_alloc_transport_domain_out_bits {
6131         u8         status[0x8];
6132         u8         reserved_at_8[0x18];
6133
6134         u8         syndrome[0x20];
6135
6136         u8         reserved_at_40[0x8];
6137         u8         transport_domain[0x18];
6138
6139         u8         reserved_at_60[0x20];
6140 };
6141
6142 struct mlx5_ifc_alloc_transport_domain_in_bits {
6143         u8         opcode[0x10];
6144         u8         reserved_at_10[0x10];
6145
6146         u8         reserved_at_20[0x10];
6147         u8         op_mod[0x10];
6148
6149         u8         reserved_at_40[0x40];
6150 };
6151
6152 struct mlx5_ifc_alloc_q_counter_out_bits {
6153         u8         status[0x8];
6154         u8         reserved_at_8[0x18];
6155
6156         u8         syndrome[0x20];
6157
6158         u8         reserved_at_40[0x18];
6159         u8         counter_set_id[0x8];
6160
6161         u8         reserved_at_60[0x20];
6162 };
6163
6164 struct mlx5_ifc_alloc_q_counter_in_bits {
6165         u8         opcode[0x10];
6166         u8         reserved_at_10[0x10];
6167
6168         u8         reserved_at_20[0x10];
6169         u8         op_mod[0x10];
6170
6171         u8         reserved_at_40[0x40];
6172 };
6173
6174 struct mlx5_ifc_alloc_pd_out_bits {
6175         u8         status[0x8];
6176         u8         reserved_at_8[0x18];
6177
6178         u8         syndrome[0x20];
6179
6180         u8         reserved_at_40[0x8];
6181         u8         pd[0x18];
6182
6183         u8         reserved_at_60[0x20];
6184 };
6185
6186 struct mlx5_ifc_alloc_pd_in_bits {
6187         u8         opcode[0x10];
6188         u8         reserved_at_10[0x10];
6189
6190         u8         reserved_at_20[0x10];
6191         u8         op_mod[0x10];
6192
6193         u8         reserved_at_40[0x40];
6194 };
6195
6196 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6197         u8         status[0x8];
6198         u8         reserved_at_8[0x18];
6199
6200         u8         syndrome[0x20];
6201
6202         u8         reserved_at_40[0x40];
6203 };
6204
6205 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6206         u8         opcode[0x10];
6207         u8         reserved_at_10[0x10];
6208
6209         u8         reserved_at_20[0x10];
6210         u8         op_mod[0x10];
6211
6212         u8         reserved_at_40[0x20];
6213
6214         u8         reserved_at_60[0x10];
6215         u8         vxlan_udp_port[0x10];
6216 };
6217
6218 struct mlx5_ifc_access_register_out_bits {
6219         u8         status[0x8];
6220         u8         reserved_at_8[0x18];
6221
6222         u8         syndrome[0x20];
6223
6224         u8         reserved_at_40[0x40];
6225
6226         u8         register_data[0][0x20];
6227 };
6228
6229 enum {
6230         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
6231         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
6232 };
6233
6234 struct mlx5_ifc_access_register_in_bits {
6235         u8         opcode[0x10];
6236         u8         reserved_at_10[0x10];
6237
6238         u8         reserved_at_20[0x10];
6239         u8         op_mod[0x10];
6240
6241         u8         reserved_at_40[0x10];
6242         u8         register_id[0x10];
6243
6244         u8         argument[0x20];
6245
6246         u8         register_data[0][0x20];
6247 };
6248
6249 struct mlx5_ifc_sltp_reg_bits {
6250         u8         status[0x4];
6251         u8         version[0x4];
6252         u8         local_port[0x8];
6253         u8         pnat[0x2];
6254         u8         reserved_at_12[0x2];
6255         u8         lane[0x4];
6256         u8         reserved_at_18[0x8];
6257
6258         u8         reserved_at_20[0x20];
6259
6260         u8         reserved_at_40[0x7];
6261         u8         polarity[0x1];
6262         u8         ob_tap0[0x8];
6263         u8         ob_tap1[0x8];
6264         u8         ob_tap2[0x8];
6265
6266         u8         reserved_at_60[0xc];
6267         u8         ob_preemp_mode[0x4];
6268         u8         ob_reg[0x8];
6269         u8         ob_bias[0x8];
6270
6271         u8         reserved_at_80[0x20];
6272 };
6273
6274 struct mlx5_ifc_slrg_reg_bits {
6275         u8         status[0x4];
6276         u8         version[0x4];
6277         u8         local_port[0x8];
6278         u8         pnat[0x2];
6279         u8         reserved_at_12[0x2];
6280         u8         lane[0x4];
6281         u8         reserved_at_18[0x8];
6282
6283         u8         time_to_link_up[0x10];
6284         u8         reserved_at_30[0xc];
6285         u8         grade_lane_speed[0x4];
6286
6287         u8         grade_version[0x8];
6288         u8         grade[0x18];
6289
6290         u8         reserved_at_60[0x4];
6291         u8         height_grade_type[0x4];
6292         u8         height_grade[0x18];
6293
6294         u8         height_dz[0x10];
6295         u8         height_dv[0x10];
6296
6297         u8         reserved_at_a0[0x10];
6298         u8         height_sigma[0x10];
6299
6300         u8         reserved_at_c0[0x20];
6301
6302         u8         reserved_at_e0[0x4];
6303         u8         phase_grade_type[0x4];
6304         u8         phase_grade[0x18];
6305
6306         u8         reserved_at_100[0x8];
6307         u8         phase_eo_pos[0x8];
6308         u8         reserved_at_110[0x8];
6309         u8         phase_eo_neg[0x8];
6310
6311         u8         ffe_set_tested[0x10];
6312         u8         test_errors_per_lane[0x10];
6313 };
6314
6315 struct mlx5_ifc_pvlc_reg_bits {
6316         u8         reserved_at_0[0x8];
6317         u8         local_port[0x8];
6318         u8         reserved_at_10[0x10];
6319
6320         u8         reserved_at_20[0x1c];
6321         u8         vl_hw_cap[0x4];
6322
6323         u8         reserved_at_40[0x1c];
6324         u8         vl_admin[0x4];
6325
6326         u8         reserved_at_60[0x1c];
6327         u8         vl_operational[0x4];
6328 };
6329
6330 struct mlx5_ifc_pude_reg_bits {
6331         u8         swid[0x8];
6332         u8         local_port[0x8];
6333         u8         reserved_at_10[0x4];
6334         u8         admin_status[0x4];
6335         u8         reserved_at_18[0x4];
6336         u8         oper_status[0x4];
6337
6338         u8         reserved_at_20[0x60];
6339 };
6340
6341 struct mlx5_ifc_ptys_reg_bits {
6342         u8         reserved_at_0[0x8];
6343         u8         local_port[0x8];
6344         u8         reserved_at_10[0xd];
6345         u8         proto_mask[0x3];
6346
6347         u8         reserved_at_20[0x40];
6348
6349         u8         eth_proto_capability[0x20];
6350
6351         u8         ib_link_width_capability[0x10];
6352         u8         ib_proto_capability[0x10];
6353
6354         u8         reserved_at_a0[0x20];
6355
6356         u8         eth_proto_admin[0x20];
6357
6358         u8         ib_link_width_admin[0x10];
6359         u8         ib_proto_admin[0x10];
6360
6361         u8         reserved_at_100[0x20];
6362
6363         u8         eth_proto_oper[0x20];
6364
6365         u8         ib_link_width_oper[0x10];
6366         u8         ib_proto_oper[0x10];
6367
6368         u8         reserved_at_160[0x20];
6369
6370         u8         eth_proto_lp_advertise[0x20];
6371
6372         u8         reserved_at_1a0[0x60];
6373 };
6374
6375 struct mlx5_ifc_ptas_reg_bits {
6376         u8         reserved_at_0[0x20];
6377
6378         u8         algorithm_options[0x10];
6379         u8         reserved_at_30[0x4];
6380         u8         repetitions_mode[0x4];
6381         u8         num_of_repetitions[0x8];
6382
6383         u8         grade_version[0x8];
6384         u8         height_grade_type[0x4];
6385         u8         phase_grade_type[0x4];
6386         u8         height_grade_weight[0x8];
6387         u8         phase_grade_weight[0x8];
6388
6389         u8         gisim_measure_bits[0x10];
6390         u8         adaptive_tap_measure_bits[0x10];
6391
6392         u8         ber_bath_high_error_threshold[0x10];
6393         u8         ber_bath_mid_error_threshold[0x10];
6394
6395         u8         ber_bath_low_error_threshold[0x10];
6396         u8         one_ratio_high_threshold[0x10];
6397
6398         u8         one_ratio_high_mid_threshold[0x10];
6399         u8         one_ratio_low_mid_threshold[0x10];
6400
6401         u8         one_ratio_low_threshold[0x10];
6402         u8         ndeo_error_threshold[0x10];
6403
6404         u8         mixer_offset_step_size[0x10];
6405         u8         reserved_at_110[0x8];
6406         u8         mix90_phase_for_voltage_bath[0x8];
6407
6408         u8         mixer_offset_start[0x10];
6409         u8         mixer_offset_end[0x10];
6410
6411         u8         reserved_at_140[0x15];
6412         u8         ber_test_time[0xb];
6413 };
6414
6415 struct mlx5_ifc_pspa_reg_bits {
6416         u8         swid[0x8];
6417         u8         local_port[0x8];
6418         u8         sub_port[0x8];
6419         u8         reserved_at_18[0x8];
6420
6421         u8         reserved_at_20[0x20];
6422 };
6423
6424 struct mlx5_ifc_pqdr_reg_bits {
6425         u8         reserved_at_0[0x8];
6426         u8         local_port[0x8];
6427         u8         reserved_at_10[0x5];
6428         u8         prio[0x3];
6429         u8         reserved_at_18[0x6];
6430         u8         mode[0x2];
6431
6432         u8         reserved_at_20[0x20];
6433
6434         u8         reserved_at_40[0x10];
6435         u8         min_threshold[0x10];
6436
6437         u8         reserved_at_60[0x10];
6438         u8         max_threshold[0x10];
6439
6440         u8         reserved_at_80[0x10];
6441         u8         mark_probability_denominator[0x10];
6442
6443         u8         reserved_at_a0[0x60];
6444 };
6445
6446 struct mlx5_ifc_ppsc_reg_bits {
6447         u8         reserved_at_0[0x8];
6448         u8         local_port[0x8];
6449         u8         reserved_at_10[0x10];
6450
6451         u8         reserved_at_20[0x60];
6452
6453         u8         reserved_at_80[0x1c];
6454         u8         wrps_admin[0x4];
6455
6456         u8         reserved_at_a0[0x1c];
6457         u8         wrps_status[0x4];
6458
6459         u8         reserved_at_c0[0x8];
6460         u8         up_threshold[0x8];
6461         u8         reserved_at_d0[0x8];
6462         u8         down_threshold[0x8];
6463
6464         u8         reserved_at_e0[0x20];
6465
6466         u8         reserved_at_100[0x1c];
6467         u8         srps_admin[0x4];
6468
6469         u8         reserved_at_120[0x1c];
6470         u8         srps_status[0x4];
6471
6472         u8         reserved_at_140[0x40];
6473 };
6474
6475 struct mlx5_ifc_pplr_reg_bits {
6476         u8         reserved_at_0[0x8];
6477         u8         local_port[0x8];
6478         u8         reserved_at_10[0x10];
6479
6480         u8         reserved_at_20[0x8];
6481         u8         lb_cap[0x8];
6482         u8         reserved_at_30[0x8];
6483         u8         lb_en[0x8];
6484 };
6485
6486 struct mlx5_ifc_pplm_reg_bits {
6487         u8         reserved_at_0[0x8];
6488         u8         local_port[0x8];
6489         u8         reserved_at_10[0x10];
6490
6491         u8         reserved_at_20[0x20];
6492
6493         u8         port_profile_mode[0x8];
6494         u8         static_port_profile[0x8];
6495         u8         active_port_profile[0x8];
6496         u8         reserved_at_58[0x8];
6497
6498         u8         retransmission_active[0x8];
6499         u8         fec_mode_active[0x18];
6500
6501         u8         reserved_at_80[0x20];
6502 };
6503
6504 struct mlx5_ifc_ppcnt_reg_bits {
6505         u8         swid[0x8];
6506         u8         local_port[0x8];
6507         u8         pnat[0x2];
6508         u8         reserved_at_12[0x8];
6509         u8         grp[0x6];
6510
6511         u8         clr[0x1];
6512         u8         reserved_at_21[0x1c];
6513         u8         prio_tc[0x3];
6514
6515         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6516 };
6517
6518 struct mlx5_ifc_ppad_reg_bits {
6519         u8         reserved_at_0[0x3];
6520         u8         single_mac[0x1];
6521         u8         reserved_at_4[0x4];
6522         u8         local_port[0x8];
6523         u8         mac_47_32[0x10];
6524
6525         u8         mac_31_0[0x20];
6526
6527         u8         reserved_at_40[0x40];
6528 };
6529
6530 struct mlx5_ifc_pmtu_reg_bits {
6531         u8         reserved_at_0[0x8];
6532         u8         local_port[0x8];
6533         u8         reserved_at_10[0x10];
6534
6535         u8         max_mtu[0x10];
6536         u8         reserved_at_30[0x10];
6537
6538         u8         admin_mtu[0x10];
6539         u8         reserved_at_50[0x10];
6540
6541         u8         oper_mtu[0x10];
6542         u8         reserved_at_70[0x10];
6543 };
6544
6545 struct mlx5_ifc_pmpr_reg_bits {
6546         u8         reserved_at_0[0x8];
6547         u8         module[0x8];
6548         u8         reserved_at_10[0x10];
6549
6550         u8         reserved_at_20[0x18];
6551         u8         attenuation_5g[0x8];
6552
6553         u8         reserved_at_40[0x18];
6554         u8         attenuation_7g[0x8];
6555
6556         u8         reserved_at_60[0x18];
6557         u8         attenuation_12g[0x8];
6558 };
6559
6560 struct mlx5_ifc_pmpe_reg_bits {
6561         u8         reserved_at_0[0x8];
6562         u8         module[0x8];
6563         u8         reserved_at_10[0xc];
6564         u8         module_status[0x4];
6565
6566         u8         reserved_at_20[0x60];
6567 };
6568
6569 struct mlx5_ifc_pmpc_reg_bits {
6570         u8         module_state_updated[32][0x8];
6571 };
6572
6573 struct mlx5_ifc_pmlpn_reg_bits {
6574         u8         reserved_at_0[0x4];
6575         u8         mlpn_status[0x4];
6576         u8         local_port[0x8];
6577         u8         reserved_at_10[0x10];
6578
6579         u8         e[0x1];
6580         u8         reserved_at_21[0x1f];
6581 };
6582
6583 struct mlx5_ifc_pmlp_reg_bits {
6584         u8         rxtx[0x1];
6585         u8         reserved_at_1[0x7];
6586         u8         local_port[0x8];
6587         u8         reserved_at_10[0x8];
6588         u8         width[0x8];
6589
6590         u8         lane0_module_mapping[0x20];
6591
6592         u8         lane1_module_mapping[0x20];
6593
6594         u8         lane2_module_mapping[0x20];
6595
6596         u8         lane3_module_mapping[0x20];
6597
6598         u8         reserved_at_a0[0x160];
6599 };
6600
6601 struct mlx5_ifc_pmaos_reg_bits {
6602         u8         reserved_at_0[0x8];
6603         u8         module[0x8];
6604         u8         reserved_at_10[0x4];
6605         u8         admin_status[0x4];
6606         u8         reserved_at_18[0x4];
6607         u8         oper_status[0x4];
6608
6609         u8         ase[0x1];
6610         u8         ee[0x1];
6611         u8         reserved_at_22[0x1c];
6612         u8         e[0x2];
6613
6614         u8         reserved_at_40[0x40];
6615 };
6616
6617 struct mlx5_ifc_plpc_reg_bits {
6618         u8         reserved_at_0[0x4];
6619         u8         profile_id[0xc];
6620         u8         reserved_at_10[0x4];
6621         u8         proto_mask[0x4];
6622         u8         reserved_at_18[0x8];
6623
6624         u8         reserved_at_20[0x10];
6625         u8         lane_speed[0x10];
6626
6627         u8         reserved_at_40[0x17];
6628         u8         lpbf[0x1];
6629         u8         fec_mode_policy[0x8];
6630
6631         u8         retransmission_capability[0x8];
6632         u8         fec_mode_capability[0x18];
6633
6634         u8         retransmission_support_admin[0x8];
6635         u8         fec_mode_support_admin[0x18];
6636
6637         u8         retransmission_request_admin[0x8];
6638         u8         fec_mode_request_admin[0x18];
6639
6640         u8         reserved_at_c0[0x80];
6641 };
6642
6643 struct mlx5_ifc_plib_reg_bits {
6644         u8         reserved_at_0[0x8];
6645         u8         local_port[0x8];
6646         u8         reserved_at_10[0x8];
6647         u8         ib_port[0x8];
6648
6649         u8         reserved_at_20[0x60];
6650 };
6651
6652 struct mlx5_ifc_plbf_reg_bits {
6653         u8         reserved_at_0[0x8];
6654         u8         local_port[0x8];
6655         u8         reserved_at_10[0xd];
6656         u8         lbf_mode[0x3];
6657
6658         u8         reserved_at_20[0x20];
6659 };
6660
6661 struct mlx5_ifc_pipg_reg_bits {
6662         u8         reserved_at_0[0x8];
6663         u8         local_port[0x8];
6664         u8         reserved_at_10[0x10];
6665
6666         u8         dic[0x1];
6667         u8         reserved_at_21[0x19];
6668         u8         ipg[0x4];
6669         u8         reserved_at_3e[0x2];
6670 };
6671
6672 struct mlx5_ifc_pifr_reg_bits {
6673         u8         reserved_at_0[0x8];
6674         u8         local_port[0x8];
6675         u8         reserved_at_10[0x10];
6676
6677         u8         reserved_at_20[0xe0];
6678
6679         u8         port_filter[8][0x20];
6680
6681         u8         port_filter_update_en[8][0x20];
6682 };
6683
6684 struct mlx5_ifc_pfcc_reg_bits {
6685         u8         reserved_at_0[0x8];
6686         u8         local_port[0x8];
6687         u8         reserved_at_10[0x10];
6688
6689         u8         ppan[0x4];
6690         u8         reserved_at_24[0x4];
6691         u8         prio_mask_tx[0x8];
6692         u8         reserved_at_30[0x8];
6693         u8         prio_mask_rx[0x8];
6694
6695         u8         pptx[0x1];
6696         u8         aptx[0x1];
6697         u8         reserved_at_42[0x6];
6698         u8         pfctx[0x8];
6699         u8         reserved_at_50[0x10];
6700
6701         u8         pprx[0x1];
6702         u8         aprx[0x1];
6703         u8         reserved_at_62[0x6];
6704         u8         pfcrx[0x8];
6705         u8         reserved_at_70[0x10];
6706
6707         u8         reserved_at_80[0x80];
6708 };
6709
6710 struct mlx5_ifc_pelc_reg_bits {
6711         u8         op[0x4];
6712         u8         reserved_at_4[0x4];
6713         u8         local_port[0x8];
6714         u8         reserved_at_10[0x10];
6715
6716         u8         op_admin[0x8];
6717         u8         op_capability[0x8];
6718         u8         op_request[0x8];
6719         u8         op_active[0x8];
6720
6721         u8         admin[0x40];
6722
6723         u8         capability[0x40];
6724
6725         u8         request[0x40];
6726
6727         u8         active[0x40];
6728
6729         u8         reserved_at_140[0x80];
6730 };
6731
6732 struct mlx5_ifc_peir_reg_bits {
6733         u8         reserved_at_0[0x8];
6734         u8         local_port[0x8];
6735         u8         reserved_at_10[0x10];
6736
6737         u8         reserved_at_20[0xc];
6738         u8         error_count[0x4];
6739         u8         reserved_at_30[0x10];
6740
6741         u8         reserved_at_40[0xc];
6742         u8         lane[0x4];
6743         u8         reserved_at_50[0x8];
6744         u8         error_type[0x8];
6745 };
6746
6747 struct mlx5_ifc_pcap_reg_bits {
6748         u8         reserved_at_0[0x8];
6749         u8         local_port[0x8];
6750         u8         reserved_at_10[0x10];
6751
6752         u8         port_capability_mask[4][0x20];
6753 };
6754
6755 struct mlx5_ifc_paos_reg_bits {
6756         u8         swid[0x8];
6757         u8         local_port[0x8];
6758         u8         reserved_at_10[0x4];
6759         u8         admin_status[0x4];
6760         u8         reserved_at_18[0x4];
6761         u8         oper_status[0x4];
6762
6763         u8         ase[0x1];
6764         u8         ee[0x1];
6765         u8         reserved_at_22[0x1c];
6766         u8         e[0x2];
6767
6768         u8         reserved_at_40[0x40];
6769 };
6770
6771 struct mlx5_ifc_pamp_reg_bits {
6772         u8         reserved_at_0[0x8];
6773         u8         opamp_group[0x8];
6774         u8         reserved_at_10[0xc];
6775         u8         opamp_group_type[0x4];
6776
6777         u8         start_index[0x10];
6778         u8         reserved_at_30[0x4];
6779         u8         num_of_indices[0xc];
6780
6781         u8         index_data[18][0x10];
6782 };
6783
6784 struct mlx5_ifc_lane_2_module_mapping_bits {
6785         u8         reserved_at_0[0x6];
6786         u8         rx_lane[0x2];
6787         u8         reserved_at_8[0x6];
6788         u8         tx_lane[0x2];
6789         u8         reserved_at_10[0x8];
6790         u8         module[0x8];
6791 };
6792
6793 struct mlx5_ifc_bufferx_reg_bits {
6794         u8         reserved_at_0[0x6];
6795         u8         lossy[0x1];
6796         u8         epsb[0x1];
6797         u8         reserved_at_8[0xc];
6798         u8         size[0xc];
6799
6800         u8         xoff_threshold[0x10];
6801         u8         xon_threshold[0x10];
6802 };
6803
6804 struct mlx5_ifc_set_node_in_bits {
6805         u8         node_description[64][0x8];
6806 };
6807
6808 struct mlx5_ifc_register_power_settings_bits {
6809         u8         reserved_at_0[0x18];
6810         u8         power_settings_level[0x8];
6811
6812         u8         reserved_at_20[0x60];
6813 };
6814
6815 struct mlx5_ifc_register_host_endianness_bits {
6816         u8         he[0x1];
6817         u8         reserved_at_1[0x1f];
6818
6819         u8         reserved_at_20[0x60];
6820 };
6821
6822 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6823         u8         reserved_at_0[0x20];
6824
6825         u8         mkey[0x20];
6826
6827         u8         addressh_63_32[0x20];
6828
6829         u8         addressl_31_0[0x20];
6830 };
6831
6832 struct mlx5_ifc_ud_adrs_vector_bits {
6833         u8         dc_key[0x40];
6834
6835         u8         ext[0x1];
6836         u8         reserved_at_41[0x7];
6837         u8         destination_qp_dct[0x18];
6838
6839         u8         static_rate[0x4];
6840         u8         sl_eth_prio[0x4];
6841         u8         fl[0x1];
6842         u8         mlid[0x7];
6843         u8         rlid_udp_sport[0x10];
6844
6845         u8         reserved_at_80[0x20];
6846
6847         u8         rmac_47_16[0x20];
6848
6849         u8         rmac_15_0[0x10];
6850         u8         tclass[0x8];
6851         u8         hop_limit[0x8];
6852
6853         u8         reserved_at_e0[0x1];
6854         u8         grh[0x1];
6855         u8         reserved_at_e2[0x2];
6856         u8         src_addr_index[0x8];
6857         u8         flow_label[0x14];
6858
6859         u8         rgid_rip[16][0x8];
6860 };
6861
6862 struct mlx5_ifc_pages_req_event_bits {
6863         u8         reserved_at_0[0x10];
6864         u8         function_id[0x10];
6865
6866         u8         num_pages[0x20];
6867
6868         u8         reserved_at_40[0xa0];
6869 };
6870
6871 struct mlx5_ifc_eqe_bits {
6872         u8         reserved_at_0[0x8];
6873         u8         event_type[0x8];
6874         u8         reserved_at_10[0x8];
6875         u8         event_sub_type[0x8];
6876
6877         u8         reserved_at_20[0xe0];
6878
6879         union mlx5_ifc_event_auto_bits event_data;
6880
6881         u8         reserved_at_1e0[0x10];
6882         u8         signature[0x8];
6883         u8         reserved_at_1f8[0x7];
6884         u8         owner[0x1];
6885 };
6886
6887 enum {
6888         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
6889 };
6890
6891 struct mlx5_ifc_cmd_queue_entry_bits {
6892         u8         type[0x8];
6893         u8         reserved_at_8[0x18];
6894
6895         u8         input_length[0x20];
6896
6897         u8         input_mailbox_pointer_63_32[0x20];
6898
6899         u8         input_mailbox_pointer_31_9[0x17];
6900         u8         reserved_at_77[0x9];
6901
6902         u8         command_input_inline_data[16][0x8];
6903
6904         u8         command_output_inline_data[16][0x8];
6905
6906         u8         output_mailbox_pointer_63_32[0x20];
6907
6908         u8         output_mailbox_pointer_31_9[0x17];
6909         u8         reserved_at_1b7[0x9];
6910
6911         u8         output_length[0x20];
6912
6913         u8         token[0x8];
6914         u8         signature[0x8];
6915         u8         reserved_at_1f0[0x8];
6916         u8         status[0x7];
6917         u8         ownership[0x1];
6918 };
6919
6920 struct mlx5_ifc_cmd_out_bits {
6921         u8         status[0x8];
6922         u8         reserved_at_8[0x18];
6923
6924         u8         syndrome[0x20];
6925
6926         u8         command_output[0x20];
6927 };
6928
6929 struct mlx5_ifc_cmd_in_bits {
6930         u8         opcode[0x10];
6931         u8         reserved_at_10[0x10];
6932
6933         u8         reserved_at_20[0x10];
6934         u8         op_mod[0x10];
6935
6936         u8         command[0][0x20];
6937 };
6938
6939 struct mlx5_ifc_cmd_if_box_bits {
6940         u8         mailbox_data[512][0x8];
6941
6942         u8         reserved_at_1000[0x180];
6943
6944         u8         next_pointer_63_32[0x20];
6945
6946         u8         next_pointer_31_10[0x16];
6947         u8         reserved_at_11b6[0xa];
6948
6949         u8         block_number[0x20];
6950
6951         u8         reserved_at_11e0[0x8];
6952         u8         token[0x8];
6953         u8         ctrl_signature[0x8];
6954         u8         signature[0x8];
6955 };
6956
6957 struct mlx5_ifc_mtt_bits {
6958         u8         ptag_63_32[0x20];
6959
6960         u8         ptag_31_8[0x18];
6961         u8         reserved_at_38[0x6];
6962         u8         wr_en[0x1];
6963         u8         rd_en[0x1];
6964 };
6965
6966 struct mlx5_ifc_query_wol_rol_out_bits {
6967         u8         status[0x8];
6968         u8         reserved_at_8[0x18];
6969
6970         u8         syndrome[0x20];
6971
6972         u8         reserved_at_40[0x10];
6973         u8         rol_mode[0x8];
6974         u8         wol_mode[0x8];
6975
6976         u8         reserved_at_60[0x20];
6977 };
6978
6979 struct mlx5_ifc_query_wol_rol_in_bits {
6980         u8         opcode[0x10];
6981         u8         reserved_at_10[0x10];
6982
6983         u8         reserved_at_20[0x10];
6984         u8         op_mod[0x10];
6985
6986         u8         reserved_at_40[0x40];
6987 };
6988
6989 struct mlx5_ifc_set_wol_rol_out_bits {
6990         u8         status[0x8];
6991         u8         reserved_at_8[0x18];
6992
6993         u8         syndrome[0x20];
6994
6995         u8         reserved_at_40[0x40];
6996 };
6997
6998 struct mlx5_ifc_set_wol_rol_in_bits {
6999         u8         opcode[0x10];
7000         u8         reserved_at_10[0x10];
7001
7002         u8         reserved_at_20[0x10];
7003         u8         op_mod[0x10];
7004
7005         u8         rol_mode_valid[0x1];
7006         u8         wol_mode_valid[0x1];
7007         u8         reserved_at_42[0xe];
7008         u8         rol_mode[0x8];
7009         u8         wol_mode[0x8];
7010
7011         u8         reserved_at_60[0x20];
7012 };
7013
7014 enum {
7015         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
7016         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
7017         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
7018 };
7019
7020 enum {
7021         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
7022         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
7023         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
7024 };
7025
7026 enum {
7027         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
7028         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
7029         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
7030         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
7031         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
7032         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
7033         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
7034         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
7035         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
7036         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
7037         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
7038 };
7039
7040 struct mlx5_ifc_initial_seg_bits {
7041         u8         fw_rev_minor[0x10];
7042         u8         fw_rev_major[0x10];
7043
7044         u8         cmd_interface_rev[0x10];
7045         u8         fw_rev_subminor[0x10];
7046
7047         u8         reserved_at_40[0x40];
7048
7049         u8         cmdq_phy_addr_63_32[0x20];
7050
7051         u8         cmdq_phy_addr_31_12[0x14];
7052         u8         reserved_at_b4[0x2];
7053         u8         nic_interface[0x2];
7054         u8         log_cmdq_size[0x4];
7055         u8         log_cmdq_stride[0x4];
7056
7057         u8         command_doorbell_vector[0x20];
7058
7059         u8         reserved_at_e0[0xf00];
7060
7061         u8         initializing[0x1];
7062         u8         reserved_at_fe1[0x4];
7063         u8         nic_interface_supported[0x3];
7064         u8         reserved_at_fe8[0x18];
7065
7066         struct mlx5_ifc_health_buffer_bits health_buffer;
7067
7068         u8         no_dram_nic_offset[0x20];
7069
7070         u8         reserved_at_1220[0x6e40];
7071
7072         u8         reserved_at_8060[0x1f];
7073         u8         clear_int[0x1];
7074
7075         u8         health_syndrome[0x8];
7076         u8         health_counter[0x18];
7077
7078         u8         reserved_at_80a0[0x17fc0];
7079 };
7080
7081 union mlx5_ifc_ports_control_registers_document_bits {
7082         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7083         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7084         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7085         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7086         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7087         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7088         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7089         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7090         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7091         struct mlx5_ifc_pamp_reg_bits pamp_reg;
7092         struct mlx5_ifc_paos_reg_bits paos_reg;
7093         struct mlx5_ifc_pcap_reg_bits pcap_reg;
7094         struct mlx5_ifc_peir_reg_bits peir_reg;
7095         struct mlx5_ifc_pelc_reg_bits pelc_reg;
7096         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7097         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7098         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7099         struct mlx5_ifc_pifr_reg_bits pifr_reg;
7100         struct mlx5_ifc_pipg_reg_bits pipg_reg;
7101         struct mlx5_ifc_plbf_reg_bits plbf_reg;
7102         struct mlx5_ifc_plib_reg_bits plib_reg;
7103         struct mlx5_ifc_plpc_reg_bits plpc_reg;
7104         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7105         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7106         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7107         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7108         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7109         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7110         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7111         struct mlx5_ifc_ppad_reg_bits ppad_reg;
7112         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7113         struct mlx5_ifc_pplm_reg_bits pplm_reg;
7114         struct mlx5_ifc_pplr_reg_bits pplr_reg;
7115         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7116         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7117         struct mlx5_ifc_pspa_reg_bits pspa_reg;
7118         struct mlx5_ifc_ptas_reg_bits ptas_reg;
7119         struct mlx5_ifc_ptys_reg_bits ptys_reg;
7120         struct mlx5_ifc_pude_reg_bits pude_reg;
7121         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7122         struct mlx5_ifc_slrg_reg_bits slrg_reg;
7123         struct mlx5_ifc_sltp_reg_bits sltp_reg;
7124         u8         reserved_at_0[0x60e0];
7125 };
7126
7127 union mlx5_ifc_debug_enhancements_document_bits {
7128         struct mlx5_ifc_health_buffer_bits health_buffer;
7129         u8         reserved_at_0[0x200];
7130 };
7131
7132 union mlx5_ifc_uplink_pci_interface_document_bits {
7133         struct mlx5_ifc_initial_seg_bits initial_seg;
7134         u8         reserved_at_0[0x20060];
7135 };
7136
7137 struct mlx5_ifc_set_flow_table_root_out_bits {
7138         u8         status[0x8];
7139         u8         reserved_at_8[0x18];
7140
7141         u8         syndrome[0x20];
7142
7143         u8         reserved_at_40[0x40];
7144 };
7145
7146 struct mlx5_ifc_set_flow_table_root_in_bits {
7147         u8         opcode[0x10];
7148         u8         reserved_at_10[0x10];
7149
7150         u8         reserved_at_20[0x10];
7151         u8         op_mod[0x10];
7152
7153         u8         reserved_at_40[0x40];
7154
7155         u8         table_type[0x8];
7156         u8         reserved_at_88[0x18];
7157
7158         u8         reserved_at_a0[0x8];
7159         u8         table_id[0x18];
7160
7161         u8         reserved_at_c0[0x140];
7162 };
7163
7164 enum {
7165         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7166 };
7167
7168 struct mlx5_ifc_modify_flow_table_out_bits {
7169         u8         status[0x8];
7170         u8         reserved_at_8[0x18];
7171
7172         u8         syndrome[0x20];
7173
7174         u8         reserved_at_40[0x40];
7175 };
7176
7177 struct mlx5_ifc_modify_flow_table_in_bits {
7178         u8         opcode[0x10];
7179         u8         reserved_at_10[0x10];
7180
7181         u8         reserved_at_20[0x10];
7182         u8         op_mod[0x10];
7183
7184         u8         reserved_at_40[0x20];
7185
7186         u8         reserved_at_60[0x10];
7187         u8         modify_field_select[0x10];
7188
7189         u8         table_type[0x8];
7190         u8         reserved_at_88[0x18];
7191
7192         u8         reserved_at_a0[0x8];
7193         u8         table_id[0x18];
7194
7195         u8         reserved_at_c0[0x4];
7196         u8         table_miss_mode[0x4];
7197         u8         reserved_at_c8[0x18];
7198
7199         u8         reserved_at_e0[0x8];
7200         u8         table_miss_id[0x18];
7201
7202         u8         reserved_at_100[0x100];
7203 };
7204
7205 struct mlx5_ifc_ets_tcn_config_reg_bits {
7206         u8         g[0x1];
7207         u8         b[0x1];
7208         u8         r[0x1];
7209         u8         reserved_at_3[0x9];
7210         u8         group[0x4];
7211         u8         reserved_at_10[0x9];
7212         u8         bw_allocation[0x7];
7213
7214         u8         reserved_at_20[0xc];
7215         u8         max_bw_units[0x4];
7216         u8         reserved_at_30[0x8];
7217         u8         max_bw_value[0x8];
7218 };
7219
7220 struct mlx5_ifc_ets_global_config_reg_bits {
7221         u8         reserved_at_0[0x2];
7222         u8         r[0x1];
7223         u8         reserved_at_3[0x1d];
7224
7225         u8         reserved_at_20[0xc];
7226         u8         max_bw_units[0x4];
7227         u8         reserved_at_30[0x8];
7228         u8         max_bw_value[0x8];
7229 };
7230
7231 struct mlx5_ifc_qetc_reg_bits {
7232         u8                                         reserved_at_0[0x8];
7233         u8                                         port_number[0x8];
7234         u8                                         reserved_at_10[0x30];
7235
7236         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
7237         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7238 };
7239
7240 struct mlx5_ifc_qtct_reg_bits {
7241         u8         reserved_at_0[0x8];
7242         u8         port_number[0x8];
7243         u8         reserved_at_10[0xd];
7244         u8         prio[0x3];
7245
7246         u8         reserved_at_20[0x1d];
7247         u8         tclass[0x3];
7248 };
7249
7250 #endif /* MLX5_IFC_H */