include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  71         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  72 };
  73
  74 enum {
  75         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  76         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  77         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  78         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  79         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  80         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  81         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  82         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  83         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  84         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  85         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  86         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  87         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  88         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  89         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  90         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  91         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  92         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  93         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  94         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  95         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  96         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  97         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  98         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
  99         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 100         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 101         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 102         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 103         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 104         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 105         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 106         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 107         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 108         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 109         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 110         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 111         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 112         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 113         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 114         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 115         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 116         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 117         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 118         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 119         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 120         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 121         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 122         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 123         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 124         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 125         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 126         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 127         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 128         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 129         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 130         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 131         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 132         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 133         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 134         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 135         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 136         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 137         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 138         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 139         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 140         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 141         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 142         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 143         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 144         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 145         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 146         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 147         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 148         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 149         MLX5_CMD_OP_DETTACH_FROM_MCG              = 0x807,
 150         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 151         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 152         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 153         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 154         MLX5_CMD_OP_NOP                           = 0x80d,
 155         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 156         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 157         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 158         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 159         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 160         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 161         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 162         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 163         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 164         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 165         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 166         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 167         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 168         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 169         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 170         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 171         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 172         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 173         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 174         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 175         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 176         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 177         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 178         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 179         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 180         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 181         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 182         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 183         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 184         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 185         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 186         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 187         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 188         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 189         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 190         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 191         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 192         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 193         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 194         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 195         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 196         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 197         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 198         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 199         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 200         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 201         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 202         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 203         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c
 204 };
 205
 206 struct mlx5_ifc_flow_table_fields_supported_bits {
 207         u8         outer_dmac[0x1];
 208         u8         outer_smac[0x1];
 209         u8         outer_ether_type[0x1];
 210         u8         reserved_at_3[0x1];
 211         u8         outer_first_prio[0x1];
 212         u8         outer_first_cfi[0x1];
 213         u8         outer_first_vid[0x1];
 214         u8         reserved_at_7[0x1];
 215         u8         outer_second_prio[0x1];
 216         u8         outer_second_cfi[0x1];
 217         u8         outer_second_vid[0x1];
 218         u8         reserved_at_b[0x1];
 219         u8         outer_sip[0x1];
 220         u8         outer_dip[0x1];
 221         u8         outer_frag[0x1];
 222         u8         outer_ip_protocol[0x1];
 223         u8         outer_ip_ecn[0x1];
 224         u8         outer_ip_dscp[0x1];
 225         u8         outer_udp_sport[0x1];
 226         u8         outer_udp_dport[0x1];
 227         u8         outer_tcp_sport[0x1];
 228         u8         outer_tcp_dport[0x1];
 229         u8         outer_tcp_flags[0x1];
 230         u8         outer_gre_protocol[0x1];
 231         u8         outer_gre_key[0x1];
 232         u8         outer_vxlan_vni[0x1];
 233         u8         reserved_at_1a[0x5];
 234         u8         source_eswitch_port[0x1];
 235
 236         u8         inner_dmac[0x1];
 237         u8         inner_smac[0x1];
 238         u8         inner_ether_type[0x1];
 239         u8         reserved_at_23[0x1];
 240         u8         inner_first_prio[0x1];
 241         u8         inner_first_cfi[0x1];
 242         u8         inner_first_vid[0x1];
 243         u8         reserved_at_27[0x1];
 244         u8         inner_second_prio[0x1];
 245         u8         inner_second_cfi[0x1];
 246         u8         inner_second_vid[0x1];
 247         u8         reserved_at_2b[0x1];
 248         u8         inner_sip[0x1];
 249         u8         inner_dip[0x1];
 250         u8         inner_frag[0x1];
 251         u8         inner_ip_protocol[0x1];
 252         u8         inner_ip_ecn[0x1];
 253         u8         inner_ip_dscp[0x1];
 254         u8         inner_udp_sport[0x1];
 255         u8         inner_udp_dport[0x1];
 256         u8         inner_tcp_sport[0x1];
 257         u8         inner_tcp_dport[0x1];
 258         u8         inner_tcp_flags[0x1];
 259         u8         reserved_at_37[0x9];
 260
 261         u8         reserved_at_40[0x40];
 262 };
 263
 264 struct mlx5_ifc_flow_table_prop_layout_bits {
 265         u8         ft_support[0x1];
 266         u8         reserved_at_1[0x2];
 267         u8         flow_modify_en[0x1];
 268         u8         modify_root[0x1];
 269         u8         identified_miss_table_mode[0x1];
 270         u8         flow_table_modify[0x1];
 271         u8         reserved_at_7[0x19];
 272
 273         u8         reserved_at_20[0x2];
 274         u8         log_max_ft_size[0x6];
 275         u8         reserved_at_28[0x10];
 276         u8         max_ft_level[0x8];
 277
 278         u8         reserved_at_40[0x20];
 279
 280         u8         reserved_at_60[0x18];
 281         u8         log_max_ft_num[0x8];
 282
 283         u8         reserved_at_80[0x18];
 284         u8         log_max_destination[0x8];
 285
 286         u8         reserved_at_a0[0x18];
 287         u8         log_max_flow[0x8];
 288
 289         u8         reserved_at_c0[0x40];
 290
 291         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 292
 293         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 294 };
 295
 296 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 297         u8         send[0x1];
 298         u8         receive[0x1];
 299         u8         write[0x1];
 300         u8         read[0x1];
 301         u8         reserved_at_4[0x1];
 302         u8         srq_receive[0x1];
 303         u8         reserved_at_6[0x1a];
 304 };
 305
 306 struct mlx5_ifc_ipv4_layout_bits {
 307         u8         reserved_at_0[0x60];
 308
 309         u8         ipv4[0x20];
 310 };
 311
 312 struct mlx5_ifc_ipv6_layout_bits {
 313         u8         ipv6[16][0x8];
 314 };
 315
 316 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 317         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 318         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 319         u8         reserved_at_0[0x80];
 320 };
 321
 322 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 323         u8         smac_47_16[0x20];
 324
 325         u8         smac_15_0[0x10];
 326         u8         ethertype[0x10];
 327
 328         u8         dmac_47_16[0x20];
 329
 330         u8         dmac_15_0[0x10];
 331         u8         first_prio[0x3];
 332         u8         first_cfi[0x1];
 333         u8         first_vid[0xc];
 334
 335         u8         ip_protocol[0x8];
 336         u8         ip_dscp[0x6];
 337         u8         ip_ecn[0x2];
 338         u8         vlan_tag[0x1];
 339         u8         reserved_at_91[0x1];
 340         u8         frag[0x1];
 341         u8         reserved_at_93[0x4];
 342         u8         tcp_flags[0x9];
 343
 344         u8         tcp_sport[0x10];
 345         u8         tcp_dport[0x10];
 346
 347         u8         reserved_at_c0[0x20];
 348
 349         u8         udp_sport[0x10];
 350         u8         udp_dport[0x10];
 351
 352         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 353
 354         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 355 };
 356
 357 struct mlx5_ifc_fte_match_set_misc_bits {
 358         u8         reserved_at_0[0x20];
 359
 360         u8         reserved_at_20[0x10];
 361         u8         source_port[0x10];
 362
 363         u8         outer_second_prio[0x3];
 364         u8         outer_second_cfi[0x1];
 365         u8         outer_second_vid[0xc];
 366         u8         inner_second_prio[0x3];
 367         u8         inner_second_cfi[0x1];
 368         u8         inner_second_vid[0xc];
 369
 370         u8         outer_second_vlan_tag[0x1];
 371         u8         inner_second_vlan_tag[0x1];
 372         u8         reserved_at_62[0xe];
 373         u8         gre_protocol[0x10];
 374
 375         u8         gre_key_h[0x18];
 376         u8         gre_key_l[0x8];
 377
 378         u8         vxlan_vni[0x18];
 379         u8         reserved_at_b8[0x8];
 380
 381         u8         reserved_at_c0[0x20];
 382
 383         u8         reserved_at_e0[0xc];
 384         u8         outer_ipv6_flow_label[0x14];
 385
 386         u8         reserved_at_100[0xc];
 387         u8         inner_ipv6_flow_label[0x14];
 388
 389         u8         reserved_at_120[0xe0];
 390 };
 391
 392 struct mlx5_ifc_cmd_pas_bits {
 393         u8         pa_h[0x20];
 394
 395         u8         pa_l[0x14];
 396         u8         reserved_at_34[0xc];
 397 };
 398
 399 struct mlx5_ifc_uint64_bits {
 400         u8         hi[0x20];
 401
 402         u8         lo[0x20];
 403 };
 404
 405 enum {
 406         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 407         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 408         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 409         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 410         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 411         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 412         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 413         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 414         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 415         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 416 };
 417
 418 struct mlx5_ifc_ads_bits {
 419         u8         fl[0x1];
 420         u8         free_ar[0x1];
 421         u8         reserved_at_2[0xe];
 422         u8         pkey_index[0x10];
 423
 424         u8         reserved_at_20[0x8];
 425         u8         grh[0x1];
 426         u8         mlid[0x7];
 427         u8         rlid[0x10];
 428
 429         u8         ack_timeout[0x5];
 430         u8         reserved_at_45[0x3];
 431         u8         src_addr_index[0x8];
 432         u8         reserved_at_50[0x4];
 433         u8         stat_rate[0x4];
 434         u8         hop_limit[0x8];
 435
 436         u8         reserved_at_60[0x4];
 437         u8         tclass[0x8];
 438         u8         flow_label[0x14];
 439
 440         u8         rgid_rip[16][0x8];
 441
 442         u8         reserved_at_100[0x4];
 443         u8         f_dscp[0x1];
 444         u8         f_ecn[0x1];
 445         u8         reserved_at_106[0x1];
 446         u8         f_eth_prio[0x1];
 447         u8         ecn[0x2];
 448         u8         dscp[0x6];
 449         u8         udp_sport[0x10];
 450
 451         u8         dei_cfi[0x1];
 452         u8         eth_prio[0x3];
 453         u8         sl[0x4];
 454         u8         port[0x8];
 455         u8         rmac_47_32[0x10];
 456
 457         u8         rmac_31_0[0x20];
 458 };
 459
 460 struct mlx5_ifc_flow_table_nic_cap_bits {
 461         u8         reserved_at_0[0x200];
 462
 463         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 464
 465         u8         reserved_at_400[0x200];
 466
 467         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 468
 469         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 470
 471         u8         reserved_at_a00[0x200];
 472
 473         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 474
 475         u8         reserved_at_e00[0x7200];
 476 };
 477
 478 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 479         u8     reserved_at_0[0x200];
 480
 481         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 482
 483         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 484
 485         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 486
 487         u8      reserved_at_800[0x7800];
 488 };
 489
 490 struct mlx5_ifc_e_switch_cap_bits {
 491         u8         vport_svlan_strip[0x1];
 492         u8         vport_cvlan_strip[0x1];
 493         u8         vport_svlan_insert[0x1];
 494         u8         vport_cvlan_insert_if_not_exist[0x1];
 495         u8         vport_cvlan_insert_overwrite[0x1];
 496         u8         reserved_at_5[0x1b];
 497
 498         u8         reserved_at_20[0x7e0];
 499 };
 500
 501 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 502         u8         csum_cap[0x1];
 503         u8         vlan_cap[0x1];
 504         u8         lro_cap[0x1];
 505         u8         lro_psh_flag[0x1];
 506         u8         lro_time_stamp[0x1];
 507         u8         reserved_at_5[0x3];
 508         u8         self_lb_en_modifiable[0x1];
 509         u8         reserved_at_9[0x2];
 510         u8         max_lso_cap[0x5];
 511         u8         reserved_at_10[0x4];
 512         u8         rss_ind_tbl_cap[0x4];
 513         u8         reserved_at_18[0x3];
 514         u8         tunnel_lso_const_out_ip_id[0x1];
 515         u8         reserved_at_1c[0x2];
 516         u8         tunnel_statless_gre[0x1];
 517         u8         tunnel_stateless_vxlan[0x1];
 518
 519         u8         reserved_at_20[0x20];
 520
 521         u8         reserved_at_40[0x10];
 522         u8         lro_min_mss_size[0x10];
 523
 524         u8         reserved_at_60[0x120];
 525
 526         u8         lro_timer_supported_periods[4][0x20];
 527
 528         u8         reserved_at_200[0x600];
 529 };
 530
 531 struct mlx5_ifc_roce_cap_bits {
 532         u8         roce_apm[0x1];
 533         u8         reserved_at_1[0x1f];
 534
 535         u8         reserved_at_20[0x60];
 536
 537         u8         reserved_at_80[0xc];
 538         u8         l3_type[0x4];
 539         u8         reserved_at_90[0x8];
 540         u8         roce_version[0x8];
 541
 542         u8         reserved_at_a0[0x10];
 543         u8         r_roce_dest_udp_port[0x10];
 544
 545         u8         r_roce_max_src_udp_port[0x10];
 546         u8         r_roce_min_src_udp_port[0x10];
 547
 548         u8         reserved_at_e0[0x10];
 549         u8         roce_address_table_size[0x10];
 550
 551         u8         reserved_at_100[0x700];
 552 };
 553
 554 enum {
 555         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 556         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 557         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 558         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 559         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 560         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 561         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 562         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 563         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 564 };
 565
 566 enum {
 567         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 568         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 569         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 570         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 571         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 572         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 573         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 574         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 575         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 576 };
 577
 578 struct mlx5_ifc_atomic_caps_bits {
 579         u8         reserved_at_0[0x40];
 580
 581         u8         atomic_req_8B_endianess_mode[0x2];
 582         u8         reserved_at_42[0x4];
 583         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 584
 585         u8         reserved_at_47[0x19];
 586
 587         u8         reserved_at_60[0x20];
 588
 589         u8         reserved_at_80[0x10];
 590         u8         atomic_operations[0x10];
 591
 592         u8         reserved_at_a0[0x10];
 593         u8         atomic_size_qp[0x10];
 594
 595         u8         reserved_at_c0[0x10];
 596         u8         atomic_size_dc[0x10];
 597
 598         u8         reserved_at_e0[0x720];
 599 };
 600
 601 struct mlx5_ifc_odp_cap_bits {
 602         u8         reserved_at_0[0x40];
 603
 604         u8         sig[0x1];
 605         u8         reserved_at_41[0x1f];
 606
 607         u8         reserved_at_60[0x20];
 608
 609         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 610
 611         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 612
 613         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 614
 615         u8         reserved_at_e0[0x720];
 616 };
 617
 618 enum {
 619         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 620         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 621         MLX5_WQ_TYPE_STRQ         = 0x2,
 622 };
 623
 624 enum {
 625         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 626         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 627 };
 628
 629 enum {
 630         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 631         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 632         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 633         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 634         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 635 };
 636
 637 enum {
 638         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 639         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 640         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 641         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 642         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 643         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 644 };
 645
 646 enum {
 647         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 648         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 649 };
 650
 651 enum {
 652         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 653         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 654         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 655 };
 656
 657 enum {
 658         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 659         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 660 };
 661
 662 struct mlx5_ifc_cmd_hca_cap_bits {
 663         u8         reserved_at_0[0x80];
 664
 665         u8         log_max_srq_sz[0x8];
 666         u8         log_max_qp_sz[0x8];
 667         u8         reserved_at_90[0xb];
 668         u8         log_max_qp[0x5];
 669
 670         u8         reserved_at_a0[0xb];
 671         u8         log_max_srq[0x5];
 672         u8         reserved_at_b0[0x10];
 673
 674         u8         reserved_at_c0[0x8];
 675         u8         log_max_cq_sz[0x8];
 676         u8         reserved_at_d0[0xb];
 677         u8         log_max_cq[0x5];
 678
 679         u8         log_max_eq_sz[0x8];
 680         u8         reserved_at_e8[0x2];
 681         u8         log_max_mkey[0x6];
 682         u8         reserved_at_f0[0xc];
 683         u8         log_max_eq[0x4];
 684
 685         u8         max_indirection[0x8];
 686         u8         reserved_at_108[0x1];
 687         u8         log_max_mrw_sz[0x7];
 688         u8         reserved_at_110[0x2];
 689         u8         log_max_bsf_list_size[0x6];
 690         u8         reserved_at_118[0x2];
 691         u8         log_max_klm_list_size[0x6];
 692
 693         u8         reserved_at_120[0xa];
 694         u8         log_max_ra_req_dc[0x6];
 695         u8         reserved_at_130[0xa];
 696         u8         log_max_ra_res_dc[0x6];
 697
 698         u8         reserved_at_140[0xa];
 699         u8         log_max_ra_req_qp[0x6];
 700         u8         reserved_at_150[0xa];
 701         u8         log_max_ra_res_qp[0x6];
 702
 703         u8         pad_cap[0x1];
 704         u8         cc_query_allowed[0x1];
 705         u8         cc_modify_allowed[0x1];
 706         u8         reserved_at_163[0xd];
 707         u8         gid_table_size[0x10];
 708
 709         u8         out_of_seq_cnt[0x1];
 710         u8         vport_counters[0x1];
 711         u8         reserved_at_182[0x4];
 712         u8         max_qp_cnt[0xa];
 713         u8         pkey_table_size[0x10];
 714
 715         u8         vport_group_manager[0x1];
 716         u8         vhca_group_manager[0x1];
 717         u8         ib_virt[0x1];
 718         u8         eth_virt[0x1];
 719         u8         reserved_at_1a4[0x1];
 720         u8         ets[0x1];
 721         u8         nic_flow_table[0x1];
 722         u8         eswitch_flow_table[0x1];
 723         u8         early_vf_enable;
 724         u8         reserved_at_1a8[0x2];
 725         u8         local_ca_ack_delay[0x5];
 726         u8         reserved_at_1af[0x6];
 727         u8         port_type[0x2];
 728         u8         num_ports[0x8];
 729
 730         u8         reserved_at_1bf[0x3];
 731         u8         log_max_msg[0x5];
 732         u8         reserved_at_1c7[0x4];
 733         u8         max_tc[0x4];
 734         u8         reserved_at_1cf[0x10];
 735
 736         u8         stat_rate_support[0x10];
 737         u8         reserved_at_1ef[0xc];
 738         u8         cqe_version[0x4];
 739
 740         u8         compact_address_vector[0x1];
 741         u8         reserved_at_200[0xe];
 742         u8         drain_sigerr[0x1];
 743         u8         cmdif_checksum[0x2];
 744         u8         sigerr_cqe[0x1];
 745         u8         reserved_at_212[0x1];
 746         u8         wq_signature[0x1];
 747         u8         sctr_data_cqe[0x1];
 748         u8         reserved_at_215[0x1];
 749         u8         sho[0x1];
 750         u8         tph[0x1];
 751         u8         rf[0x1];
 752         u8         dct[0x1];
 753         u8         reserved_at_21a[0x1];
 754         u8         eth_net_offloads[0x1];
 755         u8         roce[0x1];
 756         u8         atomic[0x1];
 757         u8         reserved_at_21e[0x1];
 758
 759         u8         cq_oi[0x1];
 760         u8         cq_resize[0x1];
 761         u8         cq_moderation[0x1];
 762         u8         reserved_at_222[0x3];
 763         u8         cq_eq_remap[0x1];
 764         u8         pg[0x1];
 765         u8         block_lb_mc[0x1];
 766         u8         reserved_at_228[0x1];
 767         u8         scqe_break_moderation[0x1];
 768         u8         reserved_at_22a[0x1];
 769         u8         cd[0x1];
 770         u8         reserved_at_22c[0x1];
 771         u8         apm[0x1];
 772         u8         reserved_at_22e[0x7];
 773         u8         qkv[0x1];
 774         u8         pkv[0x1];
 775         u8         reserved_at_237[0x4];
 776         u8         xrc[0x1];
 777         u8         ud[0x1];
 778         u8         uc[0x1];
 779         u8         rc[0x1];
 780
 781         u8         reserved_at_23f[0xa];
 782         u8         uar_sz[0x6];
 783         u8         reserved_at_24f[0x8];
 784         u8         log_pg_sz[0x8];
 785
 786         u8         bf[0x1];
 787         u8         reserved_at_260[0x1];
 788         u8         pad_tx_eth_packet[0x1];
 789         u8         reserved_at_262[0x8];
 790         u8         log_bf_reg_size[0x5];
 791         u8         reserved_at_26f[0x10];
 792
 793         u8         reserved_at_27f[0x10];
 794         u8         max_wqe_sz_sq[0x10];
 795
 796         u8         reserved_at_29f[0x10];
 797         u8         max_wqe_sz_rq[0x10];
 798
 799         u8         reserved_at_2bf[0x10];
 800         u8         max_wqe_sz_sq_dc[0x10];
 801
 802         u8         reserved_at_2df[0x7];
 803         u8         max_qp_mcg[0x19];
 804
 805         u8         reserved_at_2ff[0x18];
 806         u8         log_max_mcg[0x8];
 807
 808         u8         reserved_at_31f[0x3];
 809         u8         log_max_transport_domain[0x5];
 810         u8         reserved_at_327[0x3];
 811         u8         log_max_pd[0x5];
 812         u8         reserved_at_32f[0xb];
 813         u8         log_max_xrcd[0x5];
 814
 815         u8         reserved_at_33f[0x20];
 816
 817         u8         reserved_at_35f[0x3];
 818         u8         log_max_rq[0x5];
 819         u8         reserved_at_367[0x3];
 820         u8         log_max_sq[0x5];
 821         u8         reserved_at_36f[0x3];
 822         u8         log_max_tir[0x5];
 823         u8         reserved_at_377[0x3];
 824         u8         log_max_tis[0x5];
 825
 826         u8         basic_cyclic_rcv_wqe[0x1];
 827         u8         reserved_at_380[0x2];
 828         u8         log_max_rmp[0x5];
 829         u8         reserved_at_387[0x3];
 830         u8         log_max_rqt[0x5];
 831         u8         reserved_at_38f[0x3];
 832         u8         log_max_rqt_size[0x5];
 833         u8         reserved_at_397[0x3];
 834         u8         log_max_tis_per_sq[0x5];
 835
 836         u8         reserved_at_39f[0x3];
 837         u8         log_max_stride_sz_rq[0x5];
 838         u8         reserved_at_3a7[0x3];
 839         u8         log_min_stride_sz_rq[0x5];
 840         u8         reserved_at_3af[0x3];
 841         u8         log_max_stride_sz_sq[0x5];
 842         u8         reserved_at_3b7[0x3];
 843         u8         log_min_stride_sz_sq[0x5];
 844
 845         u8         reserved_at_3bf[0x1b];
 846         u8         log_max_wq_sz[0x5];
 847
 848         u8         nic_vport_change_event[0x1];
 849         u8         reserved_at_3e0[0xa];
 850         u8         log_max_vlan_list[0x5];
 851         u8         reserved_at_3ef[0x3];
 852         u8         log_max_current_mc_list[0x5];
 853         u8         reserved_at_3f7[0x3];
 854         u8         log_max_current_uc_list[0x5];
 855
 856         u8         reserved_at_3ff[0x80];
 857
 858         u8         reserved_at_47f[0x3];
 859         u8         log_max_l2_table[0x5];
 860         u8         reserved_at_487[0x8];
 861         u8         log_uar_page_sz[0x10];
 862
 863         u8         reserved_at_49f[0x20];
 864         u8         device_frequency_mhz[0x20];
 865         u8         device_frequency_khz[0x20];
 866         u8         reserved_at_4ff[0x5f];
 867         u8         cqe_zip[0x1];
 868
 869         u8         cqe_zip_timeout[0x10];
 870         u8         cqe_zip_max_num[0x10];
 871
 872         u8         reserved_at_57f[0x220];
 873 };
 874
 875 enum mlx5_flow_destination_type {
 876         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
 877         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
 878         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
 879 };
 880
 881 struct mlx5_ifc_dest_format_struct_bits {
 882         u8         destination_type[0x8];
 883         u8         destination_id[0x18];
 884
 885         u8         reserved_at_20[0x20];
 886 };
 887
 888 struct mlx5_ifc_fte_match_param_bits {
 889         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
 890
 891         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
 892
 893         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 894
 895         u8         reserved_at_600[0xa00];
 896 };
 897
 898 enum {
 899         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
 900         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
 901         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
 902         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
 903         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
 904 };
 905
 906 struct mlx5_ifc_rx_hash_field_select_bits {
 907         u8         l3_prot_type[0x1];
 908         u8         l4_prot_type[0x1];
 909         u8         selected_fields[0x1e];
 910 };
 911
 912 enum {
 913         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
 914         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
 915 };
 916
 917 enum {
 918         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
 919         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
 920 };
 921
 922 struct mlx5_ifc_wq_bits {
 923         u8         wq_type[0x4];
 924         u8         wq_signature[0x1];
 925         u8         end_padding_mode[0x2];
 926         u8         cd_slave[0x1];
 927         u8         reserved_at_8[0x18];
 928
 929         u8         hds_skip_first_sge[0x1];
 930         u8         log2_hds_buf_size[0x3];
 931         u8         reserved_at_24[0x7];
 932         u8         page_offset[0x5];
 933         u8         lwm[0x10];
 934
 935         u8         reserved_at_40[0x8];
 936         u8         pd[0x18];
 937
 938         u8         reserved_at_60[0x8];
 939         u8         uar_page[0x18];
 940
 941         u8         dbr_addr[0x40];
 942
 943         u8         hw_counter[0x20];
 944
 945         u8         sw_counter[0x20];
 946
 947         u8         reserved_at_100[0xc];
 948         u8         log_wq_stride[0x4];
 949         u8         reserved_at_110[0x3];
 950         u8         log_wq_pg_sz[0x5];
 951         u8         reserved_at_118[0x3];
 952         u8         log_wq_sz[0x5];
 953
 954         u8         reserved_at_120[0x4e0];
 955
 956         struct mlx5_ifc_cmd_pas_bits pas[0];
 957 };
 958
 959 struct mlx5_ifc_rq_num_bits {
 960         u8         reserved_at_0[0x8];
 961         u8         rq_num[0x18];
 962 };
 963
 964 struct mlx5_ifc_mac_address_layout_bits {
 965         u8         reserved_at_0[0x10];
 966         u8         mac_addr_47_32[0x10];
 967
 968         u8         mac_addr_31_0[0x20];
 969 };
 970
 971 struct mlx5_ifc_vlan_layout_bits {
 972         u8         reserved_at_0[0x14];
 973         u8         vlan[0x0c];
 974
 975         u8         reserved_at_20[0x20];
 976 };
 977
 978 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
 979         u8         reserved_at_0[0xa0];
 980
 981         u8         min_time_between_cnps[0x20];
 982
 983         u8         reserved_at_c0[0x12];
 984         u8         cnp_dscp[0x6];
 985         u8         reserved_at_d8[0x5];
 986         u8         cnp_802p_prio[0x3];
 987
 988         u8         reserved_at_e0[0x720];
 989 };
 990
 991 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
 992         u8         reserved_at_0[0x60];
 993
 994         u8         reserved_at_60[0x4];
 995         u8         clamp_tgt_rate[0x1];
 996         u8         reserved_at_65[0x3];
 997         u8         clamp_tgt_rate_after_time_inc[0x1];
 998         u8         reserved_at_69[0x17];
 999
1000         u8         reserved_at_80[0x20];
1001
1002         u8         rpg_time_reset[0x20];
1003
1004         u8         rpg_byte_reset[0x20];
1005
1006         u8         rpg_threshold[0x20];
1007
1008         u8         rpg_max_rate[0x20];
1009
1010         u8         rpg_ai_rate[0x20];
1011
1012         u8         rpg_hai_rate[0x20];
1013
1014         u8         rpg_gd[0x20];
1015
1016         u8         rpg_min_dec_fac[0x20];
1017
1018         u8         rpg_min_rate[0x20];
1019
1020         u8         reserved_at_1c0[0xe0];
1021
1022         u8         rate_to_set_on_first_cnp[0x20];
1023
1024         u8         dce_tcp_g[0x20];
1025
1026         u8         dce_tcp_rtt[0x20];
1027
1028         u8         rate_reduce_monitor_period[0x20];
1029
1030         u8         reserved_at_320[0x20];
1031
1032         u8         initial_alpha_value[0x20];
1033
1034         u8         reserved_at_360[0x4a0];
1035 };
1036
1037 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1038         u8         reserved_at_0[0x80];
1039
1040         u8         rppp_max_rps[0x20];
1041
1042         u8         rpg_time_reset[0x20];
1043
1044         u8         rpg_byte_reset[0x20];
1045
1046         u8         rpg_threshold[0x20];
1047
1048         u8         rpg_max_rate[0x20];
1049
1050         u8         rpg_ai_rate[0x20];
1051
1052         u8         rpg_hai_rate[0x20];
1053
1054         u8         rpg_gd[0x20];
1055
1056         u8         rpg_min_dec_fac[0x20];
1057
1058         u8         rpg_min_rate[0x20];
1059
1060         u8         reserved_at_1c0[0x640];
1061 };
1062
1063 enum {
1064         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1065         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1066         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1067 };
1068
1069 struct mlx5_ifc_resize_field_select_bits {
1070         u8         resize_field_select[0x20];
1071 };
1072
1073 enum {
1074         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1075         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1076         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1077         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1078 };
1079
1080 struct mlx5_ifc_modify_field_select_bits {
1081         u8         modify_field_select[0x20];
1082 };
1083
1084 struct mlx5_ifc_field_select_r_roce_np_bits {
1085         u8         field_select_r_roce_np[0x20];
1086 };
1087
1088 struct mlx5_ifc_field_select_r_roce_rp_bits {
1089         u8         field_select_r_roce_rp[0x20];
1090 };
1091
1092 enum {
1093         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1094         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1095         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1096         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1097         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1098         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1099         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1100         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1101         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1102         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1103 };
1104
1105 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1106         u8         field_select_8021qaurp[0x20];
1107 };
1108
1109 struct mlx5_ifc_phys_layer_cntrs_bits {
1110         u8         time_since_last_clear_high[0x20];
1111
1112         u8         time_since_last_clear_low[0x20];
1113
1114         u8         symbol_errors_high[0x20];
1115
1116         u8         symbol_errors_low[0x20];
1117
1118         u8         sync_headers_errors_high[0x20];
1119
1120         u8         sync_headers_errors_low[0x20];
1121
1122         u8         edpl_bip_errors_lane0_high[0x20];
1123
1124         u8         edpl_bip_errors_lane0_low[0x20];
1125
1126         u8         edpl_bip_errors_lane1_high[0x20];
1127
1128         u8         edpl_bip_errors_lane1_low[0x20];
1129
1130         u8         edpl_bip_errors_lane2_high[0x20];
1131
1132         u8         edpl_bip_errors_lane2_low[0x20];
1133
1134         u8         edpl_bip_errors_lane3_high[0x20];
1135
1136         u8         edpl_bip_errors_lane3_low[0x20];
1137
1138         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1139
1140         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1141
1142         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1143
1144         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1145
1146         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1147
1148         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1149
1150         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1151
1152         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1153
1154         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1155
1156         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1157
1158         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1159
1160         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1161
1162         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1163
1164         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1165
1166         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1167
1168         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1169
1170         u8         rs_fec_corrected_blocks_high[0x20];
1171
1172         u8         rs_fec_corrected_blocks_low[0x20];
1173
1174         u8         rs_fec_uncorrectable_blocks_high[0x20];
1175
1176         u8         rs_fec_uncorrectable_blocks_low[0x20];
1177
1178         u8         rs_fec_no_errors_blocks_high[0x20];
1179
1180         u8         rs_fec_no_errors_blocks_low[0x20];
1181
1182         u8         rs_fec_single_error_blocks_high[0x20];
1183
1184         u8         rs_fec_single_error_blocks_low[0x20];
1185
1186         u8         rs_fec_corrected_symbols_total_high[0x20];
1187
1188         u8         rs_fec_corrected_symbols_total_low[0x20];
1189
1190         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1191
1192         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1193
1194         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1195
1196         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1197
1198         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1199
1200         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1201
1202         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1203
1204         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1205
1206         u8         link_down_events[0x20];
1207
1208         u8         successful_recovery_events[0x20];
1209
1210         u8         reserved_at_640[0x180];
1211 };
1212
1213 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1214         u8         transmit_queue_high[0x20];
1215
1216         u8         transmit_queue_low[0x20];
1217
1218         u8         reserved_at_40[0x780];
1219 };
1220
1221 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1222         u8         rx_octets_high[0x20];
1223
1224         u8         rx_octets_low[0x20];
1225
1226         u8         reserved_at_40[0xc0];
1227
1228         u8         rx_frames_high[0x20];
1229
1230         u8         rx_frames_low[0x20];
1231
1232         u8         tx_octets_high[0x20];
1233
1234         u8         tx_octets_low[0x20];
1235
1236         u8         reserved_at_180[0xc0];
1237
1238         u8         tx_frames_high[0x20];
1239
1240         u8         tx_frames_low[0x20];
1241
1242         u8         rx_pause_high[0x20];
1243
1244         u8         rx_pause_low[0x20];
1245
1246         u8         rx_pause_duration_high[0x20];
1247
1248         u8         rx_pause_duration_low[0x20];
1249
1250         u8         tx_pause_high[0x20];
1251
1252         u8         tx_pause_low[0x20];
1253
1254         u8         tx_pause_duration_high[0x20];
1255
1256         u8         tx_pause_duration_low[0x20];
1257
1258         u8         rx_pause_transition_high[0x20];
1259
1260         u8         rx_pause_transition_low[0x20];
1261
1262         u8         reserved_at_3c0[0x400];
1263 };
1264
1265 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1266         u8         port_transmit_wait_high[0x20];
1267
1268         u8         port_transmit_wait_low[0x20];
1269
1270         u8         reserved_at_40[0x780];
1271 };
1272
1273 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1274         u8         dot3stats_alignment_errors_high[0x20];
1275
1276         u8         dot3stats_alignment_errors_low[0x20];
1277
1278         u8         dot3stats_fcs_errors_high[0x20];
1279
1280         u8         dot3stats_fcs_errors_low[0x20];
1281
1282         u8         dot3stats_single_collision_frames_high[0x20];
1283
1284         u8         dot3stats_single_collision_frames_low[0x20];
1285
1286         u8         dot3stats_multiple_collision_frames_high[0x20];
1287
1288         u8         dot3stats_multiple_collision_frames_low[0x20];
1289
1290         u8         dot3stats_sqe_test_errors_high[0x20];
1291
1292         u8         dot3stats_sqe_test_errors_low[0x20];
1293
1294         u8         dot3stats_deferred_transmissions_high[0x20];
1295
1296         u8         dot3stats_deferred_transmissions_low[0x20];
1297
1298         u8         dot3stats_late_collisions_high[0x20];
1299
1300         u8         dot3stats_late_collisions_low[0x20];
1301
1302         u8         dot3stats_excessive_collisions_high[0x20];
1303
1304         u8         dot3stats_excessive_collisions_low[0x20];
1305
1306         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1307
1308         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1309
1310         u8         dot3stats_carrier_sense_errors_high[0x20];
1311
1312         u8         dot3stats_carrier_sense_errors_low[0x20];
1313
1314         u8         dot3stats_frame_too_longs_high[0x20];
1315
1316         u8         dot3stats_frame_too_longs_low[0x20];
1317
1318         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1319
1320         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1321
1322         u8         dot3stats_symbol_errors_high[0x20];
1323
1324         u8         dot3stats_symbol_errors_low[0x20];
1325
1326         u8         dot3control_in_unknown_opcodes_high[0x20];
1327
1328         u8         dot3control_in_unknown_opcodes_low[0x20];
1329
1330         u8         dot3in_pause_frames_high[0x20];
1331
1332         u8         dot3in_pause_frames_low[0x20];
1333
1334         u8         dot3out_pause_frames_high[0x20];
1335
1336         u8         dot3out_pause_frames_low[0x20];
1337
1338         u8         reserved_at_400[0x3c0];
1339 };
1340
1341 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1342         u8         ether_stats_drop_events_high[0x20];
1343
1344         u8         ether_stats_drop_events_low[0x20];
1345
1346         u8         ether_stats_octets_high[0x20];
1347
1348         u8         ether_stats_octets_low[0x20];
1349
1350         u8         ether_stats_pkts_high[0x20];
1351
1352         u8         ether_stats_pkts_low[0x20];
1353
1354         u8         ether_stats_broadcast_pkts_high[0x20];
1355
1356         u8         ether_stats_broadcast_pkts_low[0x20];
1357
1358         u8         ether_stats_multicast_pkts_high[0x20];
1359
1360         u8         ether_stats_multicast_pkts_low[0x20];
1361
1362         u8         ether_stats_crc_align_errors_high[0x20];
1363
1364         u8         ether_stats_crc_align_errors_low[0x20];
1365
1366         u8         ether_stats_undersize_pkts_high[0x20];
1367
1368         u8         ether_stats_undersize_pkts_low[0x20];
1369
1370         u8         ether_stats_oversize_pkts_high[0x20];
1371
1372         u8         ether_stats_oversize_pkts_low[0x20];
1373
1374         u8         ether_stats_fragments_high[0x20];
1375
1376         u8         ether_stats_fragments_low[0x20];
1377
1378         u8         ether_stats_jabbers_high[0x20];
1379
1380         u8         ether_stats_jabbers_low[0x20];
1381
1382         u8         ether_stats_collisions_high[0x20];
1383
1384         u8         ether_stats_collisions_low[0x20];
1385
1386         u8         ether_stats_pkts64octets_high[0x20];
1387
1388         u8         ether_stats_pkts64octets_low[0x20];
1389
1390         u8         ether_stats_pkts65to127octets_high[0x20];
1391
1392         u8         ether_stats_pkts65to127octets_low[0x20];
1393
1394         u8         ether_stats_pkts128to255octets_high[0x20];
1395
1396         u8         ether_stats_pkts128to255octets_low[0x20];
1397
1398         u8         ether_stats_pkts256to511octets_high[0x20];
1399
1400         u8         ether_stats_pkts256to511octets_low[0x20];
1401
1402         u8         ether_stats_pkts512to1023octets_high[0x20];
1403
1404         u8         ether_stats_pkts512to1023octets_low[0x20];
1405
1406         u8         ether_stats_pkts1024to1518octets_high[0x20];
1407
1408         u8         ether_stats_pkts1024to1518octets_low[0x20];
1409
1410         u8         ether_stats_pkts1519to2047octets_high[0x20];
1411
1412         u8         ether_stats_pkts1519to2047octets_low[0x20];
1413
1414         u8         ether_stats_pkts2048to4095octets_high[0x20];
1415
1416         u8         ether_stats_pkts2048to4095octets_low[0x20];
1417
1418         u8         ether_stats_pkts4096to8191octets_high[0x20];
1419
1420         u8         ether_stats_pkts4096to8191octets_low[0x20];
1421
1422         u8         ether_stats_pkts8192to10239octets_high[0x20];
1423
1424         u8         ether_stats_pkts8192to10239octets_low[0x20];
1425
1426         u8         reserved_at_540[0x280];
1427 };
1428
1429 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1430         u8         if_in_octets_high[0x20];
1431
1432         u8         if_in_octets_low[0x20];
1433
1434         u8         if_in_ucast_pkts_high[0x20];
1435
1436         u8         if_in_ucast_pkts_low[0x20];
1437
1438         u8         if_in_discards_high[0x20];
1439
1440         u8         if_in_discards_low[0x20];
1441
1442         u8         if_in_errors_high[0x20];
1443
1444         u8         if_in_errors_low[0x20];
1445
1446         u8         if_in_unknown_protos_high[0x20];
1447
1448         u8         if_in_unknown_protos_low[0x20];
1449
1450         u8         if_out_octets_high[0x20];
1451
1452         u8         if_out_octets_low[0x20];
1453
1454         u8         if_out_ucast_pkts_high[0x20];
1455
1456         u8         if_out_ucast_pkts_low[0x20];
1457
1458         u8         if_out_discards_high[0x20];
1459
1460         u8         if_out_discards_low[0x20];
1461
1462         u8         if_out_errors_high[0x20];
1463
1464         u8         if_out_errors_low[0x20];
1465
1466         u8         if_in_multicast_pkts_high[0x20];
1467
1468         u8         if_in_multicast_pkts_low[0x20];
1469
1470         u8         if_in_broadcast_pkts_high[0x20];
1471
1472         u8         if_in_broadcast_pkts_low[0x20];
1473
1474         u8         if_out_multicast_pkts_high[0x20];
1475
1476         u8         if_out_multicast_pkts_low[0x20];
1477
1478         u8         if_out_broadcast_pkts_high[0x20];
1479
1480         u8         if_out_broadcast_pkts_low[0x20];
1481
1482         u8         reserved_at_340[0x480];
1483 };
1484
1485 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1486         u8         a_frames_transmitted_ok_high[0x20];
1487
1488         u8         a_frames_transmitted_ok_low[0x20];
1489
1490         u8         a_frames_received_ok_high[0x20];
1491
1492         u8         a_frames_received_ok_low[0x20];
1493
1494         u8         a_frame_check_sequence_errors_high[0x20];
1495
1496         u8         a_frame_check_sequence_errors_low[0x20];
1497
1498         u8         a_alignment_errors_high[0x20];
1499
1500         u8         a_alignment_errors_low[0x20];
1501
1502         u8         a_octets_transmitted_ok_high[0x20];
1503
1504         u8         a_octets_transmitted_ok_low[0x20];
1505
1506         u8         a_octets_received_ok_high[0x20];
1507
1508         u8         a_octets_received_ok_low[0x20];
1509
1510         u8         a_multicast_frames_xmitted_ok_high[0x20];
1511
1512         u8         a_multicast_frames_xmitted_ok_low[0x20];
1513
1514         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1515
1516         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1517
1518         u8         a_multicast_frames_received_ok_high[0x20];
1519
1520         u8         a_multicast_frames_received_ok_low[0x20];
1521
1522         u8         a_broadcast_frames_received_ok_high[0x20];
1523
1524         u8         a_broadcast_frames_received_ok_low[0x20];
1525
1526         u8         a_in_range_length_errors_high[0x20];
1527
1528         u8         a_in_range_length_errors_low[0x20];
1529
1530         u8         a_out_of_range_length_field_high[0x20];
1531
1532         u8         a_out_of_range_length_field_low[0x20];
1533
1534         u8         a_frame_too_long_errors_high[0x20];
1535
1536         u8         a_frame_too_long_errors_low[0x20];
1537
1538         u8         a_symbol_error_during_carrier_high[0x20];
1539
1540         u8         a_symbol_error_during_carrier_low[0x20];
1541
1542         u8         a_mac_control_frames_transmitted_high[0x20];
1543
1544         u8         a_mac_control_frames_transmitted_low[0x20];
1545
1546         u8         a_mac_control_frames_received_high[0x20];
1547
1548         u8         a_mac_control_frames_received_low[0x20];
1549
1550         u8         a_unsupported_opcodes_received_high[0x20];
1551
1552         u8         a_unsupported_opcodes_received_low[0x20];
1553
1554         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1555
1556         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1557
1558         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1559
1560         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1561
1562         u8         reserved_at_4c0[0x300];
1563 };
1564
1565 struct mlx5_ifc_cmd_inter_comp_event_bits {
1566         u8         command_completion_vector[0x20];
1567
1568         u8         reserved_at_20[0xc0];
1569 };
1570
1571 struct mlx5_ifc_stall_vl_event_bits {
1572         u8         reserved_at_0[0x18];
1573         u8         port_num[0x1];
1574         u8         reserved_at_19[0x3];
1575         u8         vl[0x4];
1576
1577         u8         reserved_at_20[0xa0];
1578 };
1579
1580 struct mlx5_ifc_db_bf_congestion_event_bits {
1581         u8         event_subtype[0x8];
1582         u8         reserved_at_8[0x8];
1583         u8         congestion_level[0x8];
1584         u8         reserved_at_18[0x8];
1585
1586         u8         reserved_at_20[0xa0];
1587 };
1588
1589 struct mlx5_ifc_gpio_event_bits {
1590         u8         reserved_at_0[0x60];
1591
1592         u8         gpio_event_hi[0x20];
1593
1594         u8         gpio_event_lo[0x20];
1595
1596         u8         reserved_at_a0[0x40];
1597 };
1598
1599 struct mlx5_ifc_port_state_change_event_bits {
1600         u8         reserved_at_0[0x40];
1601
1602         u8         port_num[0x4];
1603         u8         reserved_at_44[0x1c];
1604
1605         u8         reserved_at_60[0x80];
1606 };
1607
1608 struct mlx5_ifc_dropped_packet_logged_bits {
1609         u8         reserved_at_0[0xe0];
1610 };
1611
1612 enum {
1613         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1614         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1615 };
1616
1617 struct mlx5_ifc_cq_error_bits {
1618         u8         reserved_at_0[0x8];
1619         u8         cqn[0x18];
1620
1621         u8         reserved_at_20[0x20];
1622
1623         u8         reserved_at_40[0x18];
1624         u8         syndrome[0x8];
1625
1626         u8         reserved_at_60[0x80];
1627 };
1628
1629 struct mlx5_ifc_rdma_page_fault_event_bits {
1630         u8         bytes_committed[0x20];
1631
1632         u8         r_key[0x20];
1633
1634         u8         reserved_at_40[0x10];
1635         u8         packet_len[0x10];
1636
1637         u8         rdma_op_len[0x20];
1638
1639         u8         rdma_va[0x40];
1640
1641         u8         reserved_at_c0[0x5];
1642         u8         rdma[0x1];
1643         u8         write[0x1];
1644         u8         requestor[0x1];
1645         u8         qp_number[0x18];
1646 };
1647
1648 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1649         u8         bytes_committed[0x20];
1650
1651         u8         reserved_at_20[0x10];
1652         u8         wqe_index[0x10];
1653
1654         u8         reserved_at_40[0x10];
1655         u8         len[0x10];
1656
1657         u8         reserved_at_60[0x60];
1658
1659         u8         reserved_at_c0[0x5];
1660         u8         rdma[0x1];
1661         u8         write_read[0x1];
1662         u8         requestor[0x1];
1663         u8         qpn[0x18];
1664 };
1665
1666 struct mlx5_ifc_qp_events_bits {
1667         u8         reserved_at_0[0xa0];
1668
1669         u8         type[0x8];
1670         u8         reserved_at_a8[0x18];
1671
1672         u8         reserved_at_c0[0x8];
1673         u8         qpn_rqn_sqn[0x18];
1674 };
1675
1676 struct mlx5_ifc_dct_events_bits {
1677         u8         reserved_at_0[0xc0];
1678
1679         u8         reserved_at_c0[0x8];
1680         u8         dct_number[0x18];
1681 };
1682
1683 struct mlx5_ifc_comp_event_bits {
1684         u8         reserved_at_0[0xc0];
1685
1686         u8         reserved_at_c0[0x8];
1687         u8         cq_number[0x18];
1688 };
1689
1690 enum {
1691         MLX5_QPC_STATE_RST        = 0x0,
1692         MLX5_QPC_STATE_INIT       = 0x1,
1693         MLX5_QPC_STATE_RTR        = 0x2,
1694         MLX5_QPC_STATE_RTS        = 0x3,
1695         MLX5_QPC_STATE_SQER       = 0x4,
1696         MLX5_QPC_STATE_ERR        = 0x6,
1697         MLX5_QPC_STATE_SQD        = 0x7,
1698         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1699 };
1700
1701 enum {
1702         MLX5_QPC_ST_RC            = 0x0,
1703         MLX5_QPC_ST_UC            = 0x1,
1704         MLX5_QPC_ST_UD            = 0x2,
1705         MLX5_QPC_ST_XRC           = 0x3,
1706         MLX5_QPC_ST_DCI           = 0x5,
1707         MLX5_QPC_ST_QP0           = 0x7,
1708         MLX5_QPC_ST_QP1           = 0x8,
1709         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1710         MLX5_QPC_ST_REG_UMR       = 0xc,
1711 };
1712
1713 enum {
1714         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1715         MLX5_QPC_PM_STATE_REARM     = 0x1,
1716         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1717         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1718 };
1719
1720 enum {
1721         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1722         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1723 };
1724
1725 enum {
1726         MLX5_QPC_MTU_256_BYTES        = 0x1,
1727         MLX5_QPC_MTU_512_BYTES        = 0x2,
1728         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1729         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1730         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1731         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1732 };
1733
1734 enum {
1735         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1736         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1737         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1738         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1739         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1740         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1741         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1742         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1743 };
1744
1745 enum {
1746         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1747         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1748         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1749 };
1750
1751 enum {
1752         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1753         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1754         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1755 };
1756
1757 struct mlx5_ifc_qpc_bits {
1758         u8         state[0x4];
1759         u8         reserved_at_4[0x4];
1760         u8         st[0x8];
1761         u8         reserved_at_10[0x3];
1762         u8         pm_state[0x2];
1763         u8         reserved_at_15[0x7];
1764         u8         end_padding_mode[0x2];
1765         u8         reserved_at_1e[0x2];
1766
1767         u8         wq_signature[0x1];
1768         u8         block_lb_mc[0x1];
1769         u8         atomic_like_write_en[0x1];
1770         u8         latency_sensitive[0x1];
1771         u8         reserved_at_24[0x1];
1772         u8         drain_sigerr[0x1];
1773         u8         reserved_at_26[0x2];
1774         u8         pd[0x18];
1775
1776         u8         mtu[0x3];
1777         u8         log_msg_max[0x5];
1778         u8         reserved_at_48[0x1];
1779         u8         log_rq_size[0x4];
1780         u8         log_rq_stride[0x3];
1781         u8         no_sq[0x1];
1782         u8         log_sq_size[0x4];
1783         u8         reserved_at_55[0x6];
1784         u8         rlky[0x1];
1785         u8         reserved_at_5c[0x4];
1786
1787         u8         counter_set_id[0x8];
1788         u8         uar_page[0x18];
1789
1790         u8         reserved_at_80[0x8];
1791         u8         user_index[0x18];
1792
1793         u8         reserved_at_a0[0x3];
1794         u8         log_page_size[0x5];
1795         u8         remote_qpn[0x18];
1796
1797         struct mlx5_ifc_ads_bits primary_address_path;
1798
1799         struct mlx5_ifc_ads_bits secondary_address_path;
1800
1801         u8         log_ack_req_freq[0x4];
1802         u8         reserved_at_384[0x4];
1803         u8         log_sra_max[0x3];
1804         u8         reserved_at_38b[0x2];
1805         u8         retry_count[0x3];
1806         u8         rnr_retry[0x3];
1807         u8         reserved_at_393[0x1];
1808         u8         fre[0x1];
1809         u8         cur_rnr_retry[0x3];
1810         u8         cur_retry_count[0x3];
1811         u8         reserved_at_39b[0x5];
1812
1813         u8         reserved_at_3a0[0x20];
1814
1815         u8         reserved_at_3c0[0x8];
1816         u8         next_send_psn[0x18];
1817
1818         u8         reserved_at_3e0[0x8];
1819         u8         cqn_snd[0x18];
1820
1821         u8         reserved_at_400[0x40];
1822
1823         u8         reserved_at_440[0x8];
1824         u8         last_acked_psn[0x18];
1825
1826         u8         reserved_at_460[0x8];
1827         u8         ssn[0x18];
1828
1829         u8         reserved_at_480[0x8];
1830         u8         log_rra_max[0x3];
1831         u8         reserved_at_48b[0x1];
1832         u8         atomic_mode[0x4];
1833         u8         rre[0x1];
1834         u8         rwe[0x1];
1835         u8         rae[0x1];
1836         u8         reserved_at_493[0x1];
1837         u8         page_offset[0x6];
1838         u8         reserved_at_49a[0x3];
1839         u8         cd_slave_receive[0x1];
1840         u8         cd_slave_send[0x1];
1841         u8         cd_master[0x1];
1842
1843         u8         reserved_at_4a0[0x3];
1844         u8         min_rnr_nak[0x5];
1845         u8         next_rcv_psn[0x18];
1846
1847         u8         reserved_at_4c0[0x8];
1848         u8         xrcd[0x18];
1849
1850         u8         reserved_at_4e0[0x8];
1851         u8         cqn_rcv[0x18];
1852
1853         u8         dbr_addr[0x40];
1854
1855         u8         q_key[0x20];
1856
1857         u8         reserved_at_560[0x5];
1858         u8         rq_type[0x3];
1859         u8         srqn_rmpn[0x18];
1860
1861         u8         reserved_at_580[0x8];
1862         u8         rmsn[0x18];
1863
1864         u8         hw_sq_wqebb_counter[0x10];
1865         u8         sw_sq_wqebb_counter[0x10];
1866
1867         u8         hw_rq_counter[0x20];
1868
1869         u8         sw_rq_counter[0x20];
1870
1871         u8         reserved_at_600[0x20];
1872
1873         u8         reserved_at_620[0xf];
1874         u8         cgs[0x1];
1875         u8         cs_req[0x8];
1876         u8         cs_res[0x8];
1877
1878         u8         dc_access_key[0x40];
1879
1880         u8         reserved_at_680[0xc0];
1881 };
1882
1883 struct mlx5_ifc_roce_addr_layout_bits {
1884         u8         source_l3_address[16][0x8];
1885
1886         u8         reserved_at_80[0x3];
1887         u8         vlan_valid[0x1];
1888         u8         vlan_id[0xc];
1889         u8         source_mac_47_32[0x10];
1890
1891         u8         source_mac_31_0[0x20];
1892
1893         u8         reserved_at_c0[0x14];
1894         u8         roce_l3_type[0x4];
1895         u8         roce_version[0x8];
1896
1897         u8         reserved_at_e0[0x20];
1898 };
1899
1900 union mlx5_ifc_hca_cap_union_bits {
1901         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1902         struct mlx5_ifc_odp_cap_bits odp_cap;
1903         struct mlx5_ifc_atomic_caps_bits atomic_caps;
1904         struct mlx5_ifc_roce_cap_bits roce_cap;
1905         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1906         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1907         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
1908         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
1909         u8         reserved_at_0[0x8000];
1910 };
1911
1912 enum {
1913         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
1914         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
1915         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
1916 };
1917
1918 struct mlx5_ifc_flow_context_bits {
1919         u8         reserved_at_0[0x20];
1920
1921         u8         group_id[0x20];
1922
1923         u8         reserved_at_40[0x8];
1924         u8         flow_tag[0x18];
1925
1926         u8         reserved_at_60[0x10];
1927         u8         action[0x10];
1928
1929         u8         reserved_at_80[0x8];
1930         u8         destination_list_size[0x18];
1931
1932         u8         reserved_at_a0[0x160];
1933
1934         struct mlx5_ifc_fte_match_param_bits match_value;
1935
1936         u8         reserved_at_1200[0x600];
1937
1938         struct mlx5_ifc_dest_format_struct_bits destination[0];
1939 };
1940
1941 enum {
1942         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
1943         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
1944 };
1945
1946 struct mlx5_ifc_xrc_srqc_bits {
1947         u8         state[0x4];
1948         u8         log_xrc_srq_size[0x4];
1949         u8         reserved_at_8[0x18];
1950
1951         u8         wq_signature[0x1];
1952         u8         cont_srq[0x1];
1953         u8         reserved_at_22[0x1];
1954         u8         rlky[0x1];
1955         u8         basic_cyclic_rcv_wqe[0x1];
1956         u8         log_rq_stride[0x3];
1957         u8         xrcd[0x18];
1958
1959         u8         page_offset[0x6];
1960         u8         reserved_at_46[0x2];
1961         u8         cqn[0x18];
1962
1963         u8         reserved_at_60[0x20];
1964
1965         u8         user_index_equal_xrc_srqn[0x1];
1966         u8         reserved_at_81[0x1];
1967         u8         log_page_size[0x6];
1968         u8         user_index[0x18];
1969
1970         u8         reserved_at_a0[0x20];
1971
1972         u8         reserved_at_c0[0x8];
1973         u8         pd[0x18];
1974
1975         u8         lwm[0x10];
1976         u8         wqe_cnt[0x10];
1977
1978         u8         reserved_at_100[0x40];
1979
1980         u8         db_record_addr_h[0x20];
1981
1982         u8         db_record_addr_l[0x1e];
1983         u8         reserved_at_17e[0x2];
1984
1985         u8         reserved_at_180[0x80];
1986 };
1987
1988 struct mlx5_ifc_traffic_counter_bits {
1989         u8         packets[0x40];
1990
1991         u8         octets[0x40];
1992 };
1993
1994 struct mlx5_ifc_tisc_bits {
1995         u8         reserved_at_0[0xc];
1996         u8         prio[0x4];
1997         u8         reserved_at_10[0x10];
1998
1999         u8         reserved_at_20[0x100];
2000
2001         u8         reserved_at_120[0x8];
2002         u8         transport_domain[0x18];
2003
2004         u8         reserved_at_140[0x3c0];
2005 };
2006
2007 enum {
2008         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2009         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2010 };
2011
2012 enum {
2013         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2014         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2015 };
2016
2017 enum {
2018         MLX5_RX_HASH_FN_NONE           = 0x0,
2019         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2020         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2021 };
2022
2023 enum {
2024         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2025         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2026 };
2027
2028 struct mlx5_ifc_tirc_bits {
2029         u8         reserved_at_0[0x20];
2030
2031         u8         disp_type[0x4];
2032         u8         reserved_at_24[0x1c];
2033
2034         u8         reserved_at_40[0x40];
2035
2036         u8         reserved_at_80[0x4];
2037         u8         lro_timeout_period_usecs[0x10];
2038         u8         lro_enable_mask[0x4];
2039         u8         lro_max_ip_payload_size[0x8];
2040
2041         u8         reserved_at_a0[0x40];
2042
2043         u8         reserved_at_e0[0x8];
2044         u8         inline_rqn[0x18];
2045
2046         u8         rx_hash_symmetric[0x1];
2047         u8         reserved_at_101[0x1];
2048         u8         tunneled_offload_en[0x1];
2049         u8         reserved_at_103[0x5];
2050         u8         indirect_table[0x18];
2051
2052         u8         rx_hash_fn[0x4];
2053         u8         reserved_at_124[0x2];
2054         u8         self_lb_block[0x2];
2055         u8         transport_domain[0x18];
2056
2057         u8         rx_hash_toeplitz_key[10][0x20];
2058
2059         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2060
2061         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2062
2063         u8         reserved_at_2c0[0x4c0];
2064 };
2065
2066 enum {
2067         MLX5_SRQC_STATE_GOOD   = 0x0,
2068         MLX5_SRQC_STATE_ERROR  = 0x1,
2069 };
2070
2071 struct mlx5_ifc_srqc_bits {
2072         u8         state[0x4];
2073         u8         log_srq_size[0x4];
2074         u8         reserved_at_8[0x18];
2075
2076         u8         wq_signature[0x1];
2077         u8         cont_srq[0x1];
2078         u8         reserved_at_22[0x1];
2079         u8         rlky[0x1];
2080         u8         reserved_at_24[0x1];
2081         u8         log_rq_stride[0x3];
2082         u8         xrcd[0x18];
2083
2084         u8         page_offset[0x6];
2085         u8         reserved_at_46[0x2];
2086         u8         cqn[0x18];
2087
2088         u8         reserved_at_60[0x20];
2089
2090         u8         reserved_at_80[0x2];
2091         u8         log_page_size[0x6];
2092         u8         reserved_at_88[0x18];
2093
2094         u8         reserved_at_a0[0x20];
2095
2096         u8         reserved_at_c0[0x8];
2097         u8         pd[0x18];
2098
2099         u8         lwm[0x10];
2100         u8         wqe_cnt[0x10];
2101
2102         u8         reserved_at_100[0x40];
2103
2104         u8         dbr_addr[0x40];
2105
2106         u8         reserved_at_180[0x80];
2107 };
2108
2109 enum {
2110         MLX5_SQC_STATE_RST  = 0x0,
2111         MLX5_SQC_STATE_RDY  = 0x1,
2112         MLX5_SQC_STATE_ERR  = 0x3,
2113 };
2114
2115 struct mlx5_ifc_sqc_bits {
2116         u8         rlky[0x1];
2117         u8         cd_master[0x1];
2118         u8         fre[0x1];
2119         u8         flush_in_error_en[0x1];
2120         u8         reserved_at_4[0x4];
2121         u8         state[0x4];
2122         u8         reserved_at_c[0x14];
2123
2124         u8         reserved_at_20[0x8];
2125         u8         user_index[0x18];
2126
2127         u8         reserved_at_40[0x8];
2128         u8         cqn[0x18];
2129
2130         u8         reserved_at_60[0xa0];
2131
2132         u8         tis_lst_sz[0x10];
2133         u8         reserved_at_110[0x10];
2134
2135         u8         reserved_at_120[0x40];
2136
2137         u8         reserved_at_160[0x8];
2138         u8         tis_num_0[0x18];
2139
2140         struct mlx5_ifc_wq_bits wq;
2141 };
2142
2143 struct mlx5_ifc_rqtc_bits {
2144         u8         reserved_at_0[0xa0];
2145
2146         u8         reserved_at_a0[0x10];
2147         u8         rqt_max_size[0x10];
2148
2149         u8         reserved_at_c0[0x10];
2150         u8         rqt_actual_size[0x10];
2151
2152         u8         reserved_at_e0[0x6a0];
2153
2154         struct mlx5_ifc_rq_num_bits rq_num[0];
2155 };
2156
2157 enum {
2158         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2159         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2160 };
2161
2162 enum {
2163         MLX5_RQC_STATE_RST  = 0x0,
2164         MLX5_RQC_STATE_RDY  = 0x1,
2165         MLX5_RQC_STATE_ERR  = 0x3,
2166 };
2167
2168 struct mlx5_ifc_rqc_bits {
2169         u8         rlky[0x1];
2170         u8         reserved_at_1[0x2];
2171         u8         vsd[0x1];
2172         u8         mem_rq_type[0x4];
2173         u8         state[0x4];
2174         u8         reserved_at_c[0x1];
2175         u8         flush_in_error_en[0x1];
2176         u8         reserved_at_e[0x12];
2177
2178         u8         reserved_at_20[0x8];
2179         u8         user_index[0x18];
2180
2181         u8         reserved_at_40[0x8];
2182         u8         cqn[0x18];
2183
2184         u8         counter_set_id[0x8];
2185         u8         reserved_at_68[0x18];
2186
2187         u8         reserved_at_80[0x8];
2188         u8         rmpn[0x18];
2189
2190         u8         reserved_at_a0[0xe0];
2191
2192         struct mlx5_ifc_wq_bits wq;
2193 };
2194
2195 enum {
2196         MLX5_RMPC_STATE_RDY  = 0x1,
2197         MLX5_RMPC_STATE_ERR  = 0x3,
2198 };
2199
2200 struct mlx5_ifc_rmpc_bits {
2201         u8         reserved_at_0[0x8];
2202         u8         state[0x4];
2203         u8         reserved_at_c[0x14];
2204
2205         u8         basic_cyclic_rcv_wqe[0x1];
2206         u8         reserved_at_21[0x1f];
2207
2208         u8         reserved_at_40[0x140];
2209
2210         struct mlx5_ifc_wq_bits wq;
2211 };
2212
2213 struct mlx5_ifc_nic_vport_context_bits {
2214         u8         reserved_at_0[0x1f];
2215         u8         roce_en[0x1];
2216
2217         u8         arm_change_event[0x1];
2218         u8         reserved_at_21[0x1a];
2219         u8         event_on_mtu[0x1];
2220         u8         event_on_promisc_change[0x1];
2221         u8         event_on_vlan_change[0x1];
2222         u8         event_on_mc_address_change[0x1];
2223         u8         event_on_uc_address_change[0x1];
2224
2225         u8         reserved_at_40[0xf0];
2226
2227         u8         mtu[0x10];
2228
2229         u8         system_image_guid[0x40];
2230         u8         port_guid[0x40];
2231         u8         node_guid[0x40];
2232
2233         u8         reserved_at_200[0x140];
2234         u8         qkey_violation_counter[0x10];
2235         u8         reserved_at_350[0x430];
2236
2237         u8         promisc_uc[0x1];
2238         u8         promisc_mc[0x1];
2239         u8         promisc_all[0x1];
2240         u8         reserved_at_783[0x2];
2241         u8         allowed_list_type[0x3];
2242         u8         reserved_at_788[0xc];
2243         u8         allowed_list_size[0xc];
2244
2245         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2246
2247         u8         reserved_at_7e0[0x20];
2248
2249         u8         current_uc_mac_address[0][0x40];
2250 };
2251
2252 enum {
2253         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2254         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2255         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2256 };
2257
2258 struct mlx5_ifc_mkc_bits {
2259         u8         reserved_at_0[0x1];
2260         u8         free[0x1];
2261         u8         reserved_at_2[0xd];
2262         u8         small_fence_on_rdma_read_response[0x1];
2263         u8         umr_en[0x1];
2264         u8         a[0x1];
2265         u8         rw[0x1];
2266         u8         rr[0x1];
2267         u8         lw[0x1];
2268         u8         lr[0x1];
2269         u8         access_mode[0x2];
2270         u8         reserved_at_18[0x8];
2271
2272         u8         qpn[0x18];
2273         u8         mkey_7_0[0x8];
2274
2275         u8         reserved_at_40[0x20];
2276
2277         u8         length64[0x1];
2278         u8         bsf_en[0x1];
2279         u8         sync_umr[0x1];
2280         u8         reserved_at_63[0x2];
2281         u8         expected_sigerr_count[0x1];
2282         u8         reserved_at_66[0x1];
2283         u8         en_rinval[0x1];
2284         u8         pd[0x18];
2285
2286         u8         start_addr[0x40];
2287
2288         u8         len[0x40];
2289
2290         u8         bsf_octword_size[0x20];
2291
2292         u8         reserved_at_120[0x80];
2293
2294         u8         translations_octword_size[0x20];
2295
2296         u8         reserved_at_1c0[0x1b];
2297         u8         log_page_size[0x5];
2298
2299         u8         reserved_at_1e0[0x20];
2300 };
2301
2302 struct mlx5_ifc_pkey_bits {
2303         u8         reserved_at_0[0x10];
2304         u8         pkey[0x10];
2305 };
2306
2307 struct mlx5_ifc_array128_auto_bits {
2308         u8         array128_auto[16][0x8];
2309 };
2310
2311 struct mlx5_ifc_hca_vport_context_bits {
2312         u8         field_select[0x20];
2313
2314         u8         reserved_at_20[0xe0];
2315
2316         u8         sm_virt_aware[0x1];
2317         u8         has_smi[0x1];
2318         u8         has_raw[0x1];
2319         u8         grh_required[0x1];
2320         u8         reserved_at_104[0xc];
2321         u8         port_physical_state[0x4];
2322         u8         vport_state_policy[0x4];
2323         u8         port_state[0x4];
2324         u8         vport_state[0x4];
2325
2326         u8         reserved_at_120[0x20];
2327
2328         u8         system_image_guid[0x40];
2329
2330         u8         port_guid[0x40];
2331
2332         u8         node_guid[0x40];
2333
2334         u8         cap_mask1[0x20];
2335
2336         u8         cap_mask1_field_select[0x20];
2337
2338         u8         cap_mask2[0x20];
2339
2340         u8         cap_mask2_field_select[0x20];
2341
2342         u8         reserved_at_280[0x80];
2343
2344         u8         lid[0x10];
2345         u8         reserved_at_310[0x4];
2346         u8         init_type_reply[0x4];
2347         u8         lmc[0x3];
2348         u8         subnet_timeout[0x5];
2349
2350         u8         sm_lid[0x10];
2351         u8         sm_sl[0x4];
2352         u8         reserved_at_334[0xc];
2353
2354         u8         qkey_violation_counter[0x10];
2355         u8         pkey_violation_counter[0x10];
2356
2357         u8         reserved_at_360[0xca0];
2358 };
2359
2360 struct mlx5_ifc_esw_vport_context_bits {
2361         u8         reserved_at_0[0x3];
2362         u8         vport_svlan_strip[0x1];
2363         u8         vport_cvlan_strip[0x1];
2364         u8         vport_svlan_insert[0x1];
2365         u8         vport_cvlan_insert[0x2];
2366         u8         reserved_at_8[0x18];
2367
2368         u8         reserved_at_20[0x20];
2369
2370         u8         svlan_cfi[0x1];
2371         u8         svlan_pcp[0x3];
2372         u8         svlan_id[0xc];
2373         u8         cvlan_cfi[0x1];
2374         u8         cvlan_pcp[0x3];
2375         u8         cvlan_id[0xc];
2376
2377         u8         reserved_at_60[0x7a0];
2378 };
2379
2380 enum {
2381         MLX5_EQC_STATUS_OK                = 0x0,
2382         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2383 };
2384
2385 enum {
2386         MLX5_EQC_ST_ARMED  = 0x9,
2387         MLX5_EQC_ST_FIRED  = 0xa,
2388 };
2389
2390 struct mlx5_ifc_eqc_bits {
2391         u8         status[0x4];
2392         u8         reserved_at_4[0x9];
2393         u8         ec[0x1];
2394         u8         oi[0x1];
2395         u8         reserved_at_f[0x5];
2396         u8         st[0x4];
2397         u8         reserved_at_18[0x8];
2398
2399         u8         reserved_at_20[0x20];
2400
2401         u8         reserved_at_40[0x14];
2402         u8         page_offset[0x6];
2403         u8         reserved_at_5a[0x6];
2404
2405         u8         reserved_at_60[0x3];
2406         u8         log_eq_size[0x5];
2407         u8         uar_page[0x18];
2408
2409         u8         reserved_at_80[0x20];
2410
2411         u8         reserved_at_a0[0x18];
2412         u8         intr[0x8];
2413
2414         u8         reserved_at_c0[0x3];
2415         u8         log_page_size[0x5];
2416         u8         reserved_at_c8[0x18];
2417
2418         u8         reserved_at_e0[0x60];
2419
2420         u8         reserved_at_140[0x8];
2421         u8         consumer_counter[0x18];
2422
2423         u8         reserved_at_160[0x8];
2424         u8         producer_counter[0x18];
2425
2426         u8         reserved_at_180[0x80];
2427 };
2428
2429 enum {
2430         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2431         MLX5_DCTC_STATE_DRAINING  = 0x1,
2432         MLX5_DCTC_STATE_DRAINED   = 0x2,
2433 };
2434
2435 enum {
2436         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2437         MLX5_DCTC_CS_RES_NA         = 0x1,
2438         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2439 };
2440
2441 enum {
2442         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2443         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2444         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2445         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2446         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2447 };
2448
2449 struct mlx5_ifc_dctc_bits {
2450         u8         reserved_at_0[0x4];
2451         u8         state[0x4];
2452         u8         reserved_at_8[0x18];
2453
2454         u8         reserved_at_20[0x8];
2455         u8         user_index[0x18];
2456
2457         u8         reserved_at_40[0x8];
2458         u8         cqn[0x18];
2459
2460         u8         counter_set_id[0x8];
2461         u8         atomic_mode[0x4];
2462         u8         rre[0x1];
2463         u8         rwe[0x1];
2464         u8         rae[0x1];
2465         u8         atomic_like_write_en[0x1];
2466         u8         latency_sensitive[0x1];
2467         u8         rlky[0x1];
2468         u8         free_ar[0x1];
2469         u8         reserved_at_73[0xd];
2470
2471         u8         reserved_at_80[0x8];
2472         u8         cs_res[0x8];
2473         u8         reserved_at_90[0x3];
2474         u8         min_rnr_nak[0x5];
2475         u8         reserved_at_98[0x8];
2476
2477         u8         reserved_at_a0[0x8];
2478         u8         srqn[0x18];
2479
2480         u8         reserved_at_c0[0x8];
2481         u8         pd[0x18];
2482
2483         u8         tclass[0x8];
2484         u8         reserved_at_e8[0x4];
2485         u8         flow_label[0x14];
2486
2487         u8         dc_access_key[0x40];
2488
2489         u8         reserved_at_140[0x5];
2490         u8         mtu[0x3];
2491         u8         port[0x8];
2492         u8         pkey_index[0x10];
2493
2494         u8         reserved_at_160[0x8];
2495         u8         my_addr_index[0x8];
2496         u8         reserved_at_170[0x8];
2497         u8         hop_limit[0x8];
2498
2499         u8         dc_access_key_violation_count[0x20];
2500
2501         u8         reserved_at_1a0[0x14];
2502         u8         dei_cfi[0x1];
2503         u8         eth_prio[0x3];
2504         u8         ecn[0x2];
2505         u8         dscp[0x6];
2506
2507         u8         reserved_at_1c0[0x40];
2508 };
2509
2510 enum {
2511         MLX5_CQC_STATUS_OK             = 0x0,
2512         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2513         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2514 };
2515
2516 enum {
2517         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2518         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2519 };
2520
2521 enum {
2522         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2523         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2524         MLX5_CQC_ST_FIRED                                 = 0xa,
2525 };
2526
2527 struct mlx5_ifc_cqc_bits {
2528         u8         status[0x4];
2529         u8         reserved_at_4[0x4];
2530         u8         cqe_sz[0x3];
2531         u8         cc[0x1];
2532         u8         reserved_at_c[0x1];
2533         u8         scqe_break_moderation_en[0x1];
2534         u8         oi[0x1];
2535         u8         reserved_at_f[0x2];
2536         u8         cqe_zip_en[0x1];
2537         u8         mini_cqe_res_format[0x2];
2538         u8         st[0x4];
2539         u8         reserved_at_18[0x8];
2540
2541         u8         reserved_at_20[0x20];
2542
2543         u8         reserved_at_40[0x14];
2544         u8         page_offset[0x6];
2545         u8         reserved_at_5a[0x6];
2546
2547         u8         reserved_at_60[0x3];
2548         u8         log_cq_size[0x5];
2549         u8         uar_page[0x18];
2550
2551         u8         reserved_at_80[0x4];
2552         u8         cq_period[0xc];
2553         u8         cq_max_count[0x10];
2554
2555         u8         reserved_at_a0[0x18];
2556         u8         c_eqn[0x8];
2557
2558         u8         reserved_at_c0[0x3];
2559         u8         log_page_size[0x5];
2560         u8         reserved_at_c8[0x18];
2561
2562         u8         reserved_at_e0[0x20];
2563
2564         u8         reserved_at_100[0x8];
2565         u8         last_notified_index[0x18];
2566
2567         u8         reserved_at_120[0x8];
2568         u8         last_solicit_index[0x18];
2569
2570         u8         reserved_at_140[0x8];
2571         u8         consumer_counter[0x18];
2572
2573         u8         reserved_at_160[0x8];
2574         u8         producer_counter[0x18];
2575
2576         u8         reserved_at_180[0x40];
2577
2578         u8         dbr_addr[0x40];
2579 };
2580
2581 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2582         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2583         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2584         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2585         u8         reserved_at_0[0x800];
2586 };
2587
2588 struct mlx5_ifc_query_adapter_param_block_bits {
2589         u8         reserved_at_0[0xc0];
2590
2591         u8         reserved_at_c0[0x8];
2592         u8         ieee_vendor_id[0x18];
2593
2594         u8         reserved_at_e0[0x10];
2595         u8         vsd_vendor_id[0x10];
2596
2597         u8         vsd[208][0x8];
2598
2599         u8         vsd_contd_psid[16][0x8];
2600 };
2601
2602 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2603         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2604         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2605         u8         reserved_at_0[0x20];
2606 };
2607
2608 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2609         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2610         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2611         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2612         u8         reserved_at_0[0x20];
2613 };
2614
2615 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2616         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2617         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2618         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2619         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2620         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2621         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2622         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2623         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2624         u8         reserved_at_0[0x7c0];
2625 };
2626
2627 union mlx5_ifc_event_auto_bits {
2628         struct mlx5_ifc_comp_event_bits comp_event;
2629         struct mlx5_ifc_dct_events_bits dct_events;
2630         struct mlx5_ifc_qp_events_bits qp_events;
2631         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2632         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2633         struct mlx5_ifc_cq_error_bits cq_error;
2634         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2635         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2636         struct mlx5_ifc_gpio_event_bits gpio_event;
2637         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2638         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2639         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2640         u8         reserved_at_0[0xe0];
2641 };
2642
2643 struct mlx5_ifc_health_buffer_bits {
2644         u8         reserved_at_0[0x100];
2645
2646         u8         assert_existptr[0x20];
2647
2648         u8         assert_callra[0x20];
2649
2650         u8         reserved_at_140[0x40];
2651
2652         u8         fw_version[0x20];
2653
2654         u8         hw_id[0x20];
2655
2656         u8         reserved_at_1c0[0x20];
2657
2658         u8         irisc_index[0x8];
2659         u8         synd[0x8];
2660         u8         ext_synd[0x10];
2661 };
2662
2663 struct mlx5_ifc_register_loopback_control_bits {
2664         u8         no_lb[0x1];
2665         u8         reserved_at_1[0x7];
2666         u8         port[0x8];
2667         u8         reserved_at_10[0x10];
2668
2669         u8         reserved_at_20[0x60];
2670 };
2671
2672 struct mlx5_ifc_teardown_hca_out_bits {
2673         u8         status[0x8];
2674         u8         reserved_at_8[0x18];
2675
2676         u8         syndrome[0x20];
2677
2678         u8         reserved_at_40[0x40];
2679 };
2680
2681 enum {
2682         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
2683         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
2684 };
2685
2686 struct mlx5_ifc_teardown_hca_in_bits {
2687         u8         opcode[0x10];
2688         u8         reserved_at_10[0x10];
2689
2690         u8         reserved_at_20[0x10];
2691         u8         op_mod[0x10];
2692
2693         u8         reserved_at_40[0x10];
2694         u8         profile[0x10];
2695
2696         u8         reserved_at_60[0x20];
2697 };
2698
2699 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2700         u8         status[0x8];
2701         u8         reserved_at_8[0x18];
2702
2703         u8         syndrome[0x20];
2704
2705         u8         reserved_at_40[0x40];
2706 };
2707
2708 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2709         u8         opcode[0x10];
2710         u8         reserved_at_10[0x10];
2711
2712         u8         reserved_at_20[0x10];
2713         u8         op_mod[0x10];
2714
2715         u8         reserved_at_40[0x8];
2716         u8         qpn[0x18];
2717
2718         u8         reserved_at_60[0x20];
2719
2720         u8         opt_param_mask[0x20];
2721
2722         u8         reserved_at_a0[0x20];
2723
2724         struct mlx5_ifc_qpc_bits qpc;
2725
2726         u8         reserved_at_800[0x80];
2727 };
2728
2729 struct mlx5_ifc_sqd2rts_qp_out_bits {
2730         u8         status[0x8];
2731         u8         reserved_at_8[0x18];
2732
2733         u8         syndrome[0x20];
2734
2735         u8         reserved_at_40[0x40];
2736 };
2737
2738 struct mlx5_ifc_sqd2rts_qp_in_bits {
2739         u8         opcode[0x10];
2740         u8         reserved_at_10[0x10];
2741
2742         u8         reserved_at_20[0x10];
2743         u8         op_mod[0x10];
2744
2745         u8         reserved_at_40[0x8];
2746         u8         qpn[0x18];
2747
2748         u8         reserved_at_60[0x20];
2749
2750         u8         opt_param_mask[0x20];
2751
2752         u8         reserved_at_a0[0x20];
2753
2754         struct mlx5_ifc_qpc_bits qpc;
2755
2756         u8         reserved_at_800[0x80];
2757 };
2758
2759 struct mlx5_ifc_set_roce_address_out_bits {
2760         u8         status[0x8];
2761         u8         reserved_at_8[0x18];
2762
2763         u8         syndrome[0x20];
2764
2765         u8         reserved_at_40[0x40];
2766 };
2767
2768 struct mlx5_ifc_set_roce_address_in_bits {
2769         u8         opcode[0x10];
2770         u8         reserved_at_10[0x10];
2771
2772         u8         reserved_at_20[0x10];
2773         u8         op_mod[0x10];
2774
2775         u8         roce_address_index[0x10];
2776         u8         reserved_at_50[0x10];
2777
2778         u8         reserved_at_60[0x20];
2779
2780         struct mlx5_ifc_roce_addr_layout_bits roce_address;
2781 };
2782
2783 struct mlx5_ifc_set_mad_demux_out_bits {
2784         u8         status[0x8];
2785         u8         reserved_at_8[0x18];
2786
2787         u8         syndrome[0x20];
2788
2789         u8         reserved_at_40[0x40];
2790 };
2791
2792 enum {
2793         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
2794         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
2795 };
2796
2797 struct mlx5_ifc_set_mad_demux_in_bits {
2798         u8         opcode[0x10];
2799         u8         reserved_at_10[0x10];
2800
2801         u8         reserved_at_20[0x10];
2802         u8         op_mod[0x10];
2803
2804         u8         reserved_at_40[0x20];
2805
2806         u8         reserved_at_60[0x6];
2807         u8         demux_mode[0x2];
2808         u8         reserved_at_68[0x18];
2809 };
2810
2811 struct mlx5_ifc_set_l2_table_entry_out_bits {
2812         u8         status[0x8];
2813         u8         reserved_at_8[0x18];
2814
2815         u8         syndrome[0x20];
2816
2817         u8         reserved_at_40[0x40];
2818 };
2819
2820 struct mlx5_ifc_set_l2_table_entry_in_bits {
2821         u8         opcode[0x10];
2822         u8         reserved_at_10[0x10];
2823
2824         u8         reserved_at_20[0x10];
2825         u8         op_mod[0x10];
2826
2827         u8         reserved_at_40[0x60];
2828
2829         u8         reserved_at_a0[0x8];
2830         u8         table_index[0x18];
2831
2832         u8         reserved_at_c0[0x20];
2833
2834         u8         reserved_at_e0[0x13];
2835         u8         vlan_valid[0x1];
2836         u8         vlan[0xc];
2837
2838         struct mlx5_ifc_mac_address_layout_bits mac_address;
2839
2840         u8         reserved_at_140[0xc0];
2841 };
2842
2843 struct mlx5_ifc_set_issi_out_bits {
2844         u8         status[0x8];
2845         u8         reserved_at_8[0x18];
2846
2847         u8         syndrome[0x20];
2848
2849         u8         reserved_at_40[0x40];
2850 };
2851
2852 struct mlx5_ifc_set_issi_in_bits {
2853         u8         opcode[0x10];
2854         u8         reserved_at_10[0x10];
2855
2856         u8         reserved_at_20[0x10];
2857         u8         op_mod[0x10];
2858
2859         u8         reserved_at_40[0x10];
2860         u8         current_issi[0x10];
2861
2862         u8         reserved_at_60[0x20];
2863 };
2864
2865 struct mlx5_ifc_set_hca_cap_out_bits {
2866         u8         status[0x8];
2867         u8         reserved_at_8[0x18];
2868
2869         u8         syndrome[0x20];
2870
2871         u8         reserved_at_40[0x40];
2872 };
2873
2874 struct mlx5_ifc_set_hca_cap_in_bits {
2875         u8         opcode[0x10];
2876         u8         reserved_at_10[0x10];
2877
2878         u8         reserved_at_20[0x10];
2879         u8         op_mod[0x10];
2880
2881         u8         reserved_at_40[0x40];
2882
2883         union mlx5_ifc_hca_cap_union_bits capability;
2884 };
2885
2886 enum {
2887         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
2888         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
2889         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
2890         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
2891 };
2892
2893 struct mlx5_ifc_set_fte_out_bits {
2894         u8         status[0x8];
2895         u8         reserved_at_8[0x18];
2896
2897         u8         syndrome[0x20];
2898
2899         u8         reserved_at_40[0x40];
2900 };
2901
2902 struct mlx5_ifc_set_fte_in_bits {
2903         u8         opcode[0x10];
2904         u8         reserved_at_10[0x10];
2905
2906         u8         reserved_at_20[0x10];
2907         u8         op_mod[0x10];
2908
2909         u8         reserved_at_40[0x40];
2910
2911         u8         table_type[0x8];
2912         u8         reserved_at_88[0x18];
2913
2914         u8         reserved_at_a0[0x8];
2915         u8         table_id[0x18];
2916
2917         u8         reserved_at_c0[0x18];
2918         u8         modify_enable_mask[0x8];
2919
2920         u8         reserved_at_e0[0x20];
2921
2922         u8         flow_index[0x20];
2923
2924         u8         reserved_at_120[0xe0];
2925
2926         struct mlx5_ifc_flow_context_bits flow_context;
2927 };
2928
2929 struct mlx5_ifc_rts2rts_qp_out_bits {
2930         u8         status[0x8];
2931         u8         reserved_at_8[0x18];
2932
2933         u8         syndrome[0x20];
2934
2935         u8         reserved_at_40[0x40];
2936 };
2937
2938 struct mlx5_ifc_rts2rts_qp_in_bits {
2939         u8         opcode[0x10];
2940         u8         reserved_at_10[0x10];
2941
2942         u8         reserved_at_20[0x10];
2943         u8         op_mod[0x10];
2944
2945         u8         reserved_at_40[0x8];
2946         u8         qpn[0x18];
2947
2948         u8         reserved_at_60[0x20];
2949
2950         u8         opt_param_mask[0x20];
2951
2952         u8         reserved_at_a0[0x20];
2953
2954         struct mlx5_ifc_qpc_bits qpc;
2955
2956         u8         reserved_at_800[0x80];
2957 };
2958
2959 struct mlx5_ifc_rtr2rts_qp_out_bits {
2960         u8         status[0x8];
2961         u8         reserved_at_8[0x18];
2962
2963         u8         syndrome[0x20];
2964
2965         u8         reserved_at_40[0x40];
2966 };
2967
2968 struct mlx5_ifc_rtr2rts_qp_in_bits {
2969         u8         opcode[0x10];
2970         u8         reserved_at_10[0x10];
2971
2972         u8         reserved_at_20[0x10];
2973         u8         op_mod[0x10];
2974
2975         u8         reserved_at_40[0x8];
2976         u8         qpn[0x18];
2977
2978         u8         reserved_at_60[0x20];
2979
2980         u8         opt_param_mask[0x20];
2981
2982         u8         reserved_at_a0[0x20];
2983
2984         struct mlx5_ifc_qpc_bits qpc;
2985
2986         u8         reserved_at_800[0x80];
2987 };
2988
2989 struct mlx5_ifc_rst2init_qp_out_bits {
2990         u8         status[0x8];
2991         u8         reserved_at_8[0x18];
2992
2993         u8         syndrome[0x20];
2994
2995         u8         reserved_at_40[0x40];
2996 };
2997
2998 struct mlx5_ifc_rst2init_qp_in_bits {
2999         u8         opcode[0x10];
3000         u8         reserved_at_10[0x10];
3001
3002         u8         reserved_at_20[0x10];
3003         u8         op_mod[0x10];
3004
3005         u8         reserved_at_40[0x8];
3006         u8         qpn[0x18];
3007
3008         u8         reserved_at_60[0x20];
3009
3010         u8         opt_param_mask[0x20];
3011
3012         u8         reserved_at_a0[0x20];
3013
3014         struct mlx5_ifc_qpc_bits qpc;
3015
3016         u8         reserved_at_800[0x80];
3017 };
3018
3019 struct mlx5_ifc_query_xrc_srq_out_bits {
3020         u8         status[0x8];
3021         u8         reserved_at_8[0x18];
3022
3023         u8         syndrome[0x20];
3024
3025         u8         reserved_at_40[0x40];
3026
3027         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3028
3029         u8         reserved_at_280[0x600];
3030
3031         u8         pas[0][0x40];
3032 };
3033
3034 struct mlx5_ifc_query_xrc_srq_in_bits {
3035         u8         opcode[0x10];
3036         u8         reserved_at_10[0x10];
3037
3038         u8         reserved_at_20[0x10];
3039         u8         op_mod[0x10];
3040
3041         u8         reserved_at_40[0x8];
3042         u8         xrc_srqn[0x18];
3043
3044         u8         reserved_at_60[0x20];
3045 };
3046
3047 enum {
3048         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3049         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3050 };
3051
3052 struct mlx5_ifc_query_vport_state_out_bits {
3053         u8         status[0x8];
3054         u8         reserved_at_8[0x18];
3055
3056         u8         syndrome[0x20];
3057
3058         u8         reserved_at_40[0x20];
3059
3060         u8         reserved_at_60[0x18];
3061         u8         admin_state[0x4];
3062         u8         state[0x4];
3063 };
3064
3065 enum {
3066         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3067         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3068 };
3069
3070 struct mlx5_ifc_query_vport_state_in_bits {
3071         u8         opcode[0x10];
3072         u8         reserved_at_10[0x10];
3073
3074         u8         reserved_at_20[0x10];
3075         u8         op_mod[0x10];
3076
3077         u8         other_vport[0x1];
3078         u8         reserved_at_41[0xf];
3079         u8         vport_number[0x10];
3080
3081         u8         reserved_at_60[0x20];
3082 };
3083
3084 struct mlx5_ifc_query_vport_counter_out_bits {
3085         u8         status[0x8];
3086         u8         reserved_at_8[0x18];
3087
3088         u8         syndrome[0x20];
3089
3090         u8         reserved_at_40[0x40];
3091
3092         struct mlx5_ifc_traffic_counter_bits received_errors;
3093
3094         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3095
3096         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3097
3098         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3099
3100         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3101
3102         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3103
3104         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3105
3106         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3107
3108         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3109
3110         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3111
3112         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3113
3114         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3115
3116         u8         reserved_at_680[0xa00];
3117 };
3118
3119 enum {
3120         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3121 };
3122
3123 struct mlx5_ifc_query_vport_counter_in_bits {
3124         u8         opcode[0x10];
3125         u8         reserved_at_10[0x10];
3126
3127         u8         reserved_at_20[0x10];
3128         u8         op_mod[0x10];
3129
3130         u8         other_vport[0x1];
3131         u8         reserved_at_41[0xf];
3132         u8         vport_number[0x10];
3133
3134         u8         reserved_at_60[0x60];
3135
3136         u8         clear[0x1];
3137         u8         reserved_at_c1[0x1f];
3138
3139         u8         reserved_at_e0[0x20];
3140 };
3141
3142 struct mlx5_ifc_query_tis_out_bits {
3143         u8         status[0x8];
3144         u8         reserved_at_8[0x18];
3145
3146         u8         syndrome[0x20];
3147
3148         u8         reserved_at_40[0x40];
3149
3150         struct mlx5_ifc_tisc_bits tis_context;
3151 };
3152
3153 struct mlx5_ifc_query_tis_in_bits {
3154         u8         opcode[0x10];
3155         u8         reserved_at_10[0x10];
3156
3157         u8         reserved_at_20[0x10];
3158         u8         op_mod[0x10];
3159
3160         u8         reserved_at_40[0x8];
3161         u8         tisn[0x18];
3162
3163         u8         reserved_at_60[0x20];
3164 };
3165
3166 struct mlx5_ifc_query_tir_out_bits {
3167         u8         status[0x8];
3168         u8         reserved_at_8[0x18];
3169
3170         u8         syndrome[0x20];
3171
3172         u8         reserved_at_40[0xc0];
3173
3174         struct mlx5_ifc_tirc_bits tir_context;
3175 };
3176
3177 struct mlx5_ifc_query_tir_in_bits {
3178         u8         opcode[0x10];
3179         u8         reserved_at_10[0x10];
3180
3181         u8         reserved_at_20[0x10];
3182         u8         op_mod[0x10];
3183
3184         u8         reserved_at_40[0x8];
3185         u8         tirn[0x18];
3186
3187         u8         reserved_at_60[0x20];
3188 };
3189
3190 struct mlx5_ifc_query_srq_out_bits {
3191         u8         status[0x8];
3192         u8         reserved_at_8[0x18];
3193
3194         u8         syndrome[0x20];
3195
3196         u8         reserved_at_40[0x40];
3197
3198         struct mlx5_ifc_srqc_bits srq_context_entry;
3199
3200         u8         reserved_at_280[0x600];
3201
3202         u8         pas[0][0x40];
3203 };
3204
3205 struct mlx5_ifc_query_srq_in_bits {
3206         u8         opcode[0x10];
3207         u8         reserved_at_10[0x10];
3208
3209         u8         reserved_at_20[0x10];
3210         u8         op_mod[0x10];
3211
3212         u8         reserved_at_40[0x8];
3213         u8         srqn[0x18];
3214
3215         u8         reserved_at_60[0x20];
3216 };
3217
3218 struct mlx5_ifc_query_sq_out_bits {
3219         u8         status[0x8];
3220         u8         reserved_at_8[0x18];
3221
3222         u8         syndrome[0x20];
3223
3224         u8         reserved_at_40[0xc0];
3225
3226         struct mlx5_ifc_sqc_bits sq_context;
3227 };
3228
3229 struct mlx5_ifc_query_sq_in_bits {
3230         u8         opcode[0x10];
3231         u8         reserved_at_10[0x10];
3232
3233         u8         reserved_at_20[0x10];
3234         u8         op_mod[0x10];
3235
3236         u8         reserved_at_40[0x8];
3237         u8         sqn[0x18];
3238
3239         u8         reserved_at_60[0x20];
3240 };
3241
3242 struct mlx5_ifc_query_special_contexts_out_bits {
3243         u8         status[0x8];
3244         u8         reserved_at_8[0x18];
3245
3246         u8         syndrome[0x20];
3247
3248         u8         reserved_at_40[0x20];
3249
3250         u8         resd_lkey[0x20];
3251 };
3252
3253 struct mlx5_ifc_query_special_contexts_in_bits {
3254         u8         opcode[0x10];
3255         u8         reserved_at_10[0x10];
3256
3257         u8         reserved_at_20[0x10];
3258         u8         op_mod[0x10];
3259
3260         u8         reserved_at_40[0x40];
3261 };
3262
3263 struct mlx5_ifc_query_rqt_out_bits {
3264         u8         status[0x8];
3265         u8         reserved_at_8[0x18];
3266
3267         u8         syndrome[0x20];
3268
3269         u8         reserved_at_40[0xc0];
3270
3271         struct mlx5_ifc_rqtc_bits rqt_context;
3272 };
3273
3274 struct mlx5_ifc_query_rqt_in_bits {
3275         u8         opcode[0x10];
3276         u8         reserved_at_10[0x10];
3277
3278         u8         reserved_at_20[0x10];
3279         u8         op_mod[0x10];
3280
3281         u8         reserved_at_40[0x8];
3282         u8         rqtn[0x18];
3283
3284         u8         reserved_at_60[0x20];
3285 };
3286
3287 struct mlx5_ifc_query_rq_out_bits {
3288         u8         status[0x8];
3289         u8         reserved_at_8[0x18];
3290
3291         u8         syndrome[0x20];
3292
3293         u8         reserved_at_40[0xc0];
3294
3295         struct mlx5_ifc_rqc_bits rq_context;
3296 };
3297
3298 struct mlx5_ifc_query_rq_in_bits {
3299         u8         opcode[0x10];
3300         u8         reserved_at_10[0x10];
3301
3302         u8         reserved_at_20[0x10];
3303         u8         op_mod[0x10];
3304
3305         u8         reserved_at_40[0x8];
3306         u8         rqn[0x18];
3307
3308         u8         reserved_at_60[0x20];
3309 };
3310
3311 struct mlx5_ifc_query_roce_address_out_bits {
3312         u8         status[0x8];
3313         u8         reserved_at_8[0x18];
3314
3315         u8         syndrome[0x20];
3316
3317         u8         reserved_at_40[0x40];
3318
3319         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3320 };
3321
3322 struct mlx5_ifc_query_roce_address_in_bits {
3323         u8         opcode[0x10];
3324         u8         reserved_at_10[0x10];
3325
3326         u8         reserved_at_20[0x10];
3327         u8         op_mod[0x10];
3328
3329         u8         roce_address_index[0x10];
3330         u8         reserved_at_50[0x10];
3331
3332         u8         reserved_at_60[0x20];
3333 };
3334
3335 struct mlx5_ifc_query_rmp_out_bits {
3336         u8         status[0x8];
3337         u8         reserved_at_8[0x18];
3338
3339         u8         syndrome[0x20];
3340
3341         u8         reserved_at_40[0xc0];
3342
3343         struct mlx5_ifc_rmpc_bits rmp_context;
3344 };
3345
3346 struct mlx5_ifc_query_rmp_in_bits {
3347         u8         opcode[0x10];
3348         u8         reserved_at_10[0x10];
3349
3350         u8         reserved_at_20[0x10];
3351         u8         op_mod[0x10];
3352
3353         u8         reserved_at_40[0x8];
3354         u8         rmpn[0x18];
3355
3356         u8         reserved_at_60[0x20];
3357 };
3358
3359 struct mlx5_ifc_query_qp_out_bits {
3360         u8         status[0x8];
3361         u8         reserved_at_8[0x18];
3362
3363         u8         syndrome[0x20];
3364
3365         u8         reserved_at_40[0x40];
3366
3367         u8         opt_param_mask[0x20];
3368
3369         u8         reserved_at_a0[0x20];
3370
3371         struct mlx5_ifc_qpc_bits qpc;
3372
3373         u8         reserved_at_800[0x80];
3374
3375         u8         pas[0][0x40];
3376 };
3377
3378 struct mlx5_ifc_query_qp_in_bits {
3379         u8         opcode[0x10];
3380         u8         reserved_at_10[0x10];
3381
3382         u8         reserved_at_20[0x10];
3383         u8         op_mod[0x10];
3384
3385         u8         reserved_at_40[0x8];
3386         u8         qpn[0x18];
3387
3388         u8         reserved_at_60[0x20];
3389 };
3390
3391 struct mlx5_ifc_query_q_counter_out_bits {
3392         u8         status[0x8];
3393         u8         reserved_at_8[0x18];
3394
3395         u8         syndrome[0x20];
3396
3397         u8         reserved_at_40[0x40];
3398
3399         u8         rx_write_requests[0x20];
3400
3401         u8         reserved_at_a0[0x20];
3402
3403         u8         rx_read_requests[0x20];
3404
3405         u8         reserved_at_e0[0x20];
3406
3407         u8         rx_atomic_requests[0x20];
3408
3409         u8         reserved_at_120[0x20];
3410
3411         u8         rx_dct_connect[0x20];
3412
3413         u8         reserved_at_160[0x20];
3414
3415         u8         out_of_buffer[0x20];
3416
3417         u8         reserved_at_1a0[0x20];
3418
3419         u8         out_of_sequence[0x20];
3420
3421         u8         reserved_at_1e0[0x620];
3422 };
3423
3424 struct mlx5_ifc_query_q_counter_in_bits {
3425         u8         opcode[0x10];
3426         u8         reserved_at_10[0x10];
3427
3428         u8         reserved_at_20[0x10];
3429         u8         op_mod[0x10];
3430
3431         u8         reserved_at_40[0x80];
3432
3433         u8         clear[0x1];
3434         u8         reserved_at_c1[0x1f];
3435
3436         u8         reserved_at_e0[0x18];
3437         u8         counter_set_id[0x8];
3438 };
3439
3440 struct mlx5_ifc_query_pages_out_bits {
3441         u8         status[0x8];
3442         u8         reserved_at_8[0x18];
3443
3444         u8         syndrome[0x20];
3445
3446         u8         reserved_at_40[0x10];
3447         u8         function_id[0x10];
3448
3449         u8         num_pages[0x20];
3450 };
3451
3452 enum {
3453         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3454         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3455         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3456 };
3457
3458 struct mlx5_ifc_query_pages_in_bits {
3459         u8         opcode[0x10];
3460         u8         reserved_at_10[0x10];
3461
3462         u8         reserved_at_20[0x10];
3463         u8         op_mod[0x10];
3464
3465         u8         reserved_at_40[0x10];
3466         u8         function_id[0x10];
3467
3468         u8         reserved_at_60[0x20];
3469 };
3470
3471 struct mlx5_ifc_query_nic_vport_context_out_bits {
3472         u8         status[0x8];
3473         u8         reserved_at_8[0x18];
3474
3475         u8         syndrome[0x20];
3476
3477         u8         reserved_at_40[0x40];
3478
3479         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3480 };
3481
3482 struct mlx5_ifc_query_nic_vport_context_in_bits {
3483         u8         opcode[0x10];
3484         u8         reserved_at_10[0x10];
3485
3486         u8         reserved_at_20[0x10];
3487         u8         op_mod[0x10];
3488
3489         u8         other_vport[0x1];
3490         u8         reserved_at_41[0xf];
3491         u8         vport_number[0x10];
3492
3493         u8         reserved_at_60[0x5];
3494         u8         allowed_list_type[0x3];
3495         u8         reserved_at_68[0x18];
3496 };
3497
3498 struct mlx5_ifc_query_mkey_out_bits {
3499         u8         status[0x8];
3500         u8         reserved_at_8[0x18];
3501
3502         u8         syndrome[0x20];
3503
3504         u8         reserved_at_40[0x40];
3505
3506         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3507
3508         u8         reserved_at_280[0x600];
3509
3510         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3511
3512         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3513 };
3514
3515 struct mlx5_ifc_query_mkey_in_bits {
3516         u8         opcode[0x10];
3517         u8         reserved_at_10[0x10];
3518
3519         u8         reserved_at_20[0x10];
3520         u8         op_mod[0x10];
3521
3522         u8         reserved_at_40[0x8];
3523         u8         mkey_index[0x18];
3524
3525         u8         pg_access[0x1];
3526         u8         reserved_at_61[0x1f];
3527 };
3528
3529 struct mlx5_ifc_query_mad_demux_out_bits {
3530         u8         status[0x8];
3531         u8         reserved_at_8[0x18];
3532
3533         u8         syndrome[0x20];
3534
3535         u8         reserved_at_40[0x40];
3536
3537         u8         mad_dumux_parameters_block[0x20];
3538 };
3539
3540 struct mlx5_ifc_query_mad_demux_in_bits {
3541         u8         opcode[0x10];
3542         u8         reserved_at_10[0x10];
3543
3544         u8         reserved_at_20[0x10];
3545         u8         op_mod[0x10];
3546
3547         u8         reserved_at_40[0x40];
3548 };
3549
3550 struct mlx5_ifc_query_l2_table_entry_out_bits {
3551         u8         status[0x8];
3552         u8         reserved_at_8[0x18];
3553
3554         u8         syndrome[0x20];
3555
3556         u8         reserved_at_40[0xa0];
3557
3558         u8         reserved_at_e0[0x13];
3559         u8         vlan_valid[0x1];
3560         u8         vlan[0xc];
3561
3562         struct mlx5_ifc_mac_address_layout_bits mac_address;
3563
3564         u8         reserved_at_140[0xc0];
3565 };
3566
3567 struct mlx5_ifc_query_l2_table_entry_in_bits {
3568         u8         opcode[0x10];
3569         u8         reserved_at_10[0x10];
3570
3571         u8         reserved_at_20[0x10];
3572         u8         op_mod[0x10];
3573
3574         u8         reserved_at_40[0x60];
3575
3576         u8         reserved_at_a0[0x8];
3577         u8         table_index[0x18];
3578
3579         u8         reserved_at_c0[0x140];
3580 };
3581
3582 struct mlx5_ifc_query_issi_out_bits {
3583         u8         status[0x8];
3584         u8         reserved_at_8[0x18];
3585
3586         u8         syndrome[0x20];
3587
3588         u8         reserved_at_40[0x10];
3589         u8         current_issi[0x10];
3590
3591         u8         reserved_at_60[0xa0];
3592
3593         u8         reserved_at_100[76][0x8];
3594         u8         supported_issi_dw0[0x20];
3595 };
3596
3597 struct mlx5_ifc_query_issi_in_bits {
3598         u8         opcode[0x10];
3599         u8         reserved_at_10[0x10];
3600
3601         u8         reserved_at_20[0x10];
3602         u8         op_mod[0x10];
3603
3604         u8         reserved_at_40[0x40];
3605 };
3606
3607 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3608         u8         status[0x8];
3609         u8         reserved_at_8[0x18];
3610
3611         u8         syndrome[0x20];
3612
3613         u8         reserved_at_40[0x40];
3614
3615         struct mlx5_ifc_pkey_bits pkey[0];
3616 };
3617
3618 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3619         u8         opcode[0x10];
3620         u8         reserved_at_10[0x10];
3621
3622         u8         reserved_at_20[0x10];
3623         u8         op_mod[0x10];
3624
3625         u8         other_vport[0x1];
3626         u8         reserved_at_41[0xb];
3627         u8         port_num[0x4];
3628         u8         vport_number[0x10];
3629
3630         u8         reserved_at_60[0x10];
3631         u8         pkey_index[0x10];
3632 };
3633
3634 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3635         u8         status[0x8];
3636         u8         reserved_at_8[0x18];
3637
3638         u8         syndrome[0x20];
3639
3640         u8         reserved_at_40[0x20];
3641
3642         u8         gids_num[0x10];
3643         u8         reserved_at_70[0x10];
3644
3645         struct mlx5_ifc_array128_auto_bits gid[0];
3646 };
3647
3648 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3649         u8         opcode[0x10];
3650         u8         reserved_at_10[0x10];
3651
3652         u8         reserved_at_20[0x10];
3653         u8         op_mod[0x10];
3654
3655         u8         other_vport[0x1];
3656         u8         reserved_at_41[0xb];
3657         u8         port_num[0x4];
3658         u8         vport_number[0x10];
3659
3660         u8         reserved_at_60[0x10];
3661         u8         gid_index[0x10];
3662 };
3663
3664 struct mlx5_ifc_query_hca_vport_context_out_bits {
3665         u8         status[0x8];
3666         u8         reserved_at_8[0x18];
3667
3668         u8         syndrome[0x20];
3669
3670         u8         reserved_at_40[0x40];
3671
3672         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3673 };
3674
3675 struct mlx5_ifc_query_hca_vport_context_in_bits {
3676         u8         opcode[0x10];
3677         u8         reserved_at_10[0x10];
3678
3679         u8         reserved_at_20[0x10];
3680         u8         op_mod[0x10];
3681
3682         u8         other_vport[0x1];
3683         u8         reserved_at_41[0xb];
3684         u8         port_num[0x4];
3685         u8         vport_number[0x10];
3686
3687         u8         reserved_at_60[0x20];
3688 };
3689
3690 struct mlx5_ifc_query_hca_cap_out_bits {
3691         u8         status[0x8];
3692         u8         reserved_at_8[0x18];
3693
3694         u8         syndrome[0x20];
3695
3696         u8         reserved_at_40[0x40];
3697
3698         union mlx5_ifc_hca_cap_union_bits capability;
3699 };
3700
3701 struct mlx5_ifc_query_hca_cap_in_bits {
3702         u8         opcode[0x10];
3703         u8         reserved_at_10[0x10];
3704
3705         u8         reserved_at_20[0x10];
3706         u8         op_mod[0x10];
3707
3708         u8         reserved_at_40[0x40];
3709 };
3710
3711 struct mlx5_ifc_query_flow_table_out_bits {
3712         u8         status[0x8];
3713         u8         reserved_at_8[0x18];
3714
3715         u8         syndrome[0x20];
3716
3717         u8         reserved_at_40[0x80];
3718
3719         u8         reserved_at_c0[0x8];
3720         u8         level[0x8];
3721         u8         reserved_at_d0[0x8];
3722         u8         log_size[0x8];
3723
3724         u8         reserved_at_e0[0x120];
3725 };
3726
3727 struct mlx5_ifc_query_flow_table_in_bits {
3728         u8         opcode[0x10];
3729         u8         reserved_at_10[0x10];
3730
3731         u8         reserved_at_20[0x10];
3732         u8         op_mod[0x10];
3733
3734         u8         reserved_at_40[0x40];
3735
3736         u8         table_type[0x8];
3737         u8         reserved_at_88[0x18];
3738
3739         u8         reserved_at_a0[0x8];
3740         u8         table_id[0x18];
3741
3742         u8         reserved_at_c0[0x140];
3743 };
3744
3745 struct mlx5_ifc_query_fte_out_bits {
3746         u8         status[0x8];
3747         u8         reserved_at_8[0x18];
3748
3749         u8         syndrome[0x20];
3750
3751         u8         reserved_at_40[0x1c0];
3752
3753         struct mlx5_ifc_flow_context_bits flow_context;
3754 };
3755
3756 struct mlx5_ifc_query_fte_in_bits {
3757         u8         opcode[0x10];
3758         u8         reserved_at_10[0x10];
3759
3760         u8         reserved_at_20[0x10];
3761         u8         op_mod[0x10];
3762
3763         u8         reserved_at_40[0x40];
3764
3765         u8         table_type[0x8];
3766         u8         reserved_at_88[0x18];
3767
3768         u8         reserved_at_a0[0x8];
3769         u8         table_id[0x18];
3770
3771         u8         reserved_at_c0[0x40];
3772
3773         u8         flow_index[0x20];
3774
3775         u8         reserved_at_120[0xe0];
3776 };
3777
3778 enum {
3779         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
3780         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
3781         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
3782 };
3783
3784 struct mlx5_ifc_query_flow_group_out_bits {
3785         u8         status[0x8];
3786         u8         reserved_at_8[0x18];
3787
3788         u8         syndrome[0x20];
3789
3790         u8         reserved_at_40[0xa0];
3791
3792         u8         start_flow_index[0x20];
3793
3794         u8         reserved_at_100[0x20];
3795
3796         u8         end_flow_index[0x20];
3797
3798         u8         reserved_at_140[0xa0];
3799
3800         u8         reserved_at_1e0[0x18];
3801         u8         match_criteria_enable[0x8];
3802
3803         struct mlx5_ifc_fte_match_param_bits match_criteria;
3804
3805         u8         reserved_at_1200[0xe00];
3806 };
3807
3808 struct mlx5_ifc_query_flow_group_in_bits {
3809         u8         opcode[0x10];
3810         u8         reserved_at_10[0x10];
3811
3812         u8         reserved_at_20[0x10];
3813         u8         op_mod[0x10];
3814
3815         u8         reserved_at_40[0x40];
3816
3817         u8         table_type[0x8];
3818         u8         reserved_at_88[0x18];
3819
3820         u8         reserved_at_a0[0x8];
3821         u8         table_id[0x18];
3822
3823         u8         group_id[0x20];
3824
3825         u8         reserved_at_e0[0x120];
3826 };
3827
3828 struct mlx5_ifc_query_esw_vport_context_out_bits {
3829         u8         status[0x8];
3830         u8         reserved_at_8[0x18];
3831
3832         u8         syndrome[0x20];
3833
3834         u8         reserved_at_40[0x40];
3835
3836         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3837 };
3838
3839 struct mlx5_ifc_query_esw_vport_context_in_bits {
3840         u8         opcode[0x10];
3841         u8         reserved_at_10[0x10];
3842
3843         u8         reserved_at_20[0x10];
3844         u8         op_mod[0x10];
3845
3846         u8         other_vport[0x1];
3847         u8         reserved_at_41[0xf];
3848         u8         vport_number[0x10];
3849
3850         u8         reserved_at_60[0x20];
3851 };
3852
3853 struct mlx5_ifc_modify_esw_vport_context_out_bits {
3854         u8         status[0x8];
3855         u8         reserved_at_8[0x18];
3856
3857         u8         syndrome[0x20];
3858
3859         u8         reserved_at_40[0x40];
3860 };
3861
3862 struct mlx5_ifc_esw_vport_context_fields_select_bits {
3863         u8         reserved_at_0[0x1c];
3864         u8         vport_cvlan_insert[0x1];
3865         u8         vport_svlan_insert[0x1];
3866         u8         vport_cvlan_strip[0x1];
3867         u8         vport_svlan_strip[0x1];
3868 };
3869
3870 struct mlx5_ifc_modify_esw_vport_context_in_bits {
3871         u8         opcode[0x10];
3872         u8         reserved_at_10[0x10];
3873
3874         u8         reserved_at_20[0x10];
3875         u8         op_mod[0x10];
3876
3877         u8         other_vport[0x1];
3878         u8         reserved_at_41[0xf];
3879         u8         vport_number[0x10];
3880
3881         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
3882
3883         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3884 };
3885
3886 struct mlx5_ifc_query_eq_out_bits {
3887         u8         status[0x8];
3888         u8         reserved_at_8[0x18];
3889
3890         u8         syndrome[0x20];
3891
3892         u8         reserved_at_40[0x40];
3893
3894         struct mlx5_ifc_eqc_bits eq_context_entry;
3895
3896         u8         reserved_at_280[0x40];
3897
3898         u8         event_bitmask[0x40];
3899
3900         u8         reserved_at_300[0x580];
3901
3902         u8         pas[0][0x40];
3903 };
3904
3905 struct mlx5_ifc_query_eq_in_bits {
3906         u8         opcode[0x10];
3907         u8         reserved_at_10[0x10];
3908
3909         u8         reserved_at_20[0x10];
3910         u8         op_mod[0x10];
3911
3912         u8         reserved_at_40[0x18];
3913         u8         eq_number[0x8];
3914
3915         u8         reserved_at_60[0x20];
3916 };
3917
3918 struct mlx5_ifc_query_dct_out_bits {
3919         u8         status[0x8];
3920         u8         reserved_at_8[0x18];
3921
3922         u8         syndrome[0x20];
3923
3924         u8         reserved_at_40[0x40];
3925
3926         struct mlx5_ifc_dctc_bits dct_context_entry;
3927
3928         u8         reserved_at_280[0x180];
3929 };
3930
3931 struct mlx5_ifc_query_dct_in_bits {
3932         u8         opcode[0x10];
3933         u8         reserved_at_10[0x10];
3934
3935         u8         reserved_at_20[0x10];
3936         u8         op_mod[0x10];
3937
3938         u8         reserved_at_40[0x8];
3939         u8         dctn[0x18];
3940
3941         u8         reserved_at_60[0x20];
3942 };
3943
3944 struct mlx5_ifc_query_cq_out_bits {
3945         u8         status[0x8];
3946         u8         reserved_at_8[0x18];
3947
3948         u8         syndrome[0x20];
3949
3950         u8         reserved_at_40[0x40];
3951
3952         struct mlx5_ifc_cqc_bits cq_context;
3953
3954         u8         reserved_at_280[0x600];
3955
3956         u8         pas[0][0x40];
3957 };
3958
3959 struct mlx5_ifc_query_cq_in_bits {
3960         u8         opcode[0x10];
3961         u8         reserved_at_10[0x10];
3962
3963         u8         reserved_at_20[0x10];
3964         u8         op_mod[0x10];
3965
3966         u8         reserved_at_40[0x8];
3967         u8         cqn[0x18];
3968
3969         u8         reserved_at_60[0x20];
3970 };
3971
3972 struct mlx5_ifc_query_cong_status_out_bits {
3973         u8         status[0x8];
3974         u8         reserved_at_8[0x18];
3975
3976         u8         syndrome[0x20];
3977
3978         u8         reserved_at_40[0x20];
3979
3980         u8         enable[0x1];
3981         u8         tag_enable[0x1];
3982         u8         reserved_at_62[0x1e];
3983 };
3984
3985 struct mlx5_ifc_query_cong_status_in_bits {
3986         u8         opcode[0x10];
3987         u8         reserved_at_10[0x10];
3988
3989         u8         reserved_at_20[0x10];
3990         u8         op_mod[0x10];
3991
3992         u8         reserved_at_40[0x18];
3993         u8         priority[0x4];
3994         u8         cong_protocol[0x4];
3995
3996         u8         reserved_at_60[0x20];
3997 };
3998
3999 struct mlx5_ifc_query_cong_statistics_out_bits {
4000         u8         status[0x8];
4001         u8         reserved_at_8[0x18];
4002
4003         u8         syndrome[0x20];
4004
4005         u8         reserved_at_40[0x40];
4006
4007         u8         cur_flows[0x20];
4008
4009         u8         sum_flows[0x20];
4010
4011         u8         cnp_ignored_high[0x20];
4012
4013         u8         cnp_ignored_low[0x20];
4014
4015         u8         cnp_handled_high[0x20];
4016
4017         u8         cnp_handled_low[0x20];
4018
4019         u8         reserved_at_140[0x100];
4020
4021         u8         time_stamp_high[0x20];
4022
4023         u8         time_stamp_low[0x20];
4024
4025         u8         accumulators_period[0x20];
4026
4027         u8         ecn_marked_roce_packets_high[0x20];
4028
4029         u8         ecn_marked_roce_packets_low[0x20];
4030
4031         u8         cnps_sent_high[0x20];
4032
4033         u8         cnps_sent_low[0x20];
4034
4035         u8         reserved_at_320[0x560];
4036 };
4037
4038 struct mlx5_ifc_query_cong_statistics_in_bits {
4039         u8         opcode[0x10];
4040         u8         reserved_at_10[0x10];
4041
4042         u8         reserved_at_20[0x10];
4043         u8         op_mod[0x10];
4044
4045         u8         clear[0x1];
4046         u8         reserved_at_41[0x1f];
4047
4048         u8         reserved_at_60[0x20];
4049 };
4050
4051 struct mlx5_ifc_query_cong_params_out_bits {
4052         u8         status[0x8];
4053         u8         reserved_at_8[0x18];
4054
4055         u8         syndrome[0x20];
4056
4057         u8         reserved_at_40[0x40];
4058
4059         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4060 };
4061
4062 struct mlx5_ifc_query_cong_params_in_bits {
4063         u8         opcode[0x10];
4064         u8         reserved_at_10[0x10];
4065
4066         u8         reserved_at_20[0x10];
4067         u8         op_mod[0x10];
4068
4069         u8         reserved_at_40[0x1c];
4070         u8         cong_protocol[0x4];
4071
4072         u8         reserved_at_60[0x20];
4073 };
4074
4075 struct mlx5_ifc_query_adapter_out_bits {
4076         u8         status[0x8];
4077         u8         reserved_at_8[0x18];
4078
4079         u8         syndrome[0x20];
4080
4081         u8         reserved_at_40[0x40];
4082
4083         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4084 };
4085
4086 struct mlx5_ifc_query_adapter_in_bits {
4087         u8         opcode[0x10];
4088         u8         reserved_at_10[0x10];
4089
4090         u8         reserved_at_20[0x10];
4091         u8         op_mod[0x10];
4092
4093         u8         reserved_at_40[0x40];
4094 };
4095
4096 struct mlx5_ifc_qp_2rst_out_bits {
4097         u8         status[0x8];
4098         u8         reserved_at_8[0x18];
4099
4100         u8         syndrome[0x20];
4101
4102         u8         reserved_at_40[0x40];
4103 };
4104
4105 struct mlx5_ifc_qp_2rst_in_bits {
4106         u8         opcode[0x10];
4107         u8         reserved_at_10[0x10];
4108
4109         u8         reserved_at_20[0x10];
4110         u8         op_mod[0x10];
4111
4112         u8         reserved_at_40[0x8];
4113         u8         qpn[0x18];
4114
4115         u8         reserved_at_60[0x20];
4116 };
4117
4118 struct mlx5_ifc_qp_2err_out_bits {
4119         u8         status[0x8];
4120         u8         reserved_at_8[0x18];
4121
4122         u8         syndrome[0x20];
4123
4124         u8         reserved_at_40[0x40];
4125 };
4126
4127 struct mlx5_ifc_qp_2err_in_bits {
4128         u8         opcode[0x10];
4129         u8         reserved_at_10[0x10];
4130
4131         u8         reserved_at_20[0x10];
4132         u8         op_mod[0x10];
4133
4134         u8         reserved_at_40[0x8];
4135         u8         qpn[0x18];
4136
4137         u8         reserved_at_60[0x20];
4138 };
4139
4140 struct mlx5_ifc_page_fault_resume_out_bits {
4141         u8         status[0x8];
4142         u8         reserved_at_8[0x18];
4143
4144         u8         syndrome[0x20];
4145
4146         u8         reserved_at_40[0x40];
4147 };
4148
4149 struct mlx5_ifc_page_fault_resume_in_bits {
4150         u8         opcode[0x10];
4151         u8         reserved_at_10[0x10];
4152
4153         u8         reserved_at_20[0x10];
4154         u8         op_mod[0x10];
4155
4156         u8         error[0x1];
4157         u8         reserved_at_41[0x4];
4158         u8         rdma[0x1];
4159         u8         read_write[0x1];
4160         u8         req_res[0x1];
4161         u8         qpn[0x18];
4162
4163         u8         reserved_at_60[0x20];
4164 };
4165
4166 struct mlx5_ifc_nop_out_bits {
4167         u8         status[0x8];
4168         u8         reserved_at_8[0x18];
4169
4170         u8         syndrome[0x20];
4171
4172         u8         reserved_at_40[0x40];
4173 };
4174
4175 struct mlx5_ifc_nop_in_bits {
4176         u8         opcode[0x10];
4177         u8         reserved_at_10[0x10];
4178
4179         u8         reserved_at_20[0x10];
4180         u8         op_mod[0x10];
4181
4182         u8         reserved_at_40[0x40];
4183 };
4184
4185 struct mlx5_ifc_modify_vport_state_out_bits {
4186         u8         status[0x8];
4187         u8         reserved_at_8[0x18];
4188
4189         u8         syndrome[0x20];
4190
4191         u8         reserved_at_40[0x40];
4192 };
4193
4194 struct mlx5_ifc_modify_vport_state_in_bits {
4195         u8         opcode[0x10];
4196         u8         reserved_at_10[0x10];
4197
4198         u8         reserved_at_20[0x10];
4199         u8         op_mod[0x10];
4200
4201         u8         other_vport[0x1];
4202         u8         reserved_at_41[0xf];
4203         u8         vport_number[0x10];
4204
4205         u8         reserved_at_60[0x18];
4206         u8         admin_state[0x4];
4207         u8         reserved_at_7c[0x4];
4208 };
4209
4210 struct mlx5_ifc_modify_tis_out_bits {
4211         u8         status[0x8];
4212         u8         reserved_at_8[0x18];
4213
4214         u8         syndrome[0x20];
4215
4216         u8         reserved_at_40[0x40];
4217 };
4218
4219 struct mlx5_ifc_modify_tis_bitmask_bits {
4220         u8         reserved_at_0[0x20];
4221
4222         u8         reserved_at_20[0x1f];
4223         u8         prio[0x1];
4224 };
4225
4226 struct mlx5_ifc_modify_tis_in_bits {
4227         u8         opcode[0x10];
4228         u8         reserved_at_10[0x10];
4229
4230         u8         reserved_at_20[0x10];
4231         u8         op_mod[0x10];
4232
4233         u8         reserved_at_40[0x8];
4234         u8         tisn[0x18];
4235
4236         u8         reserved_at_60[0x20];
4237
4238         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4239
4240         u8         reserved_at_c0[0x40];
4241
4242         struct mlx5_ifc_tisc_bits ctx;
4243 };
4244
4245 struct mlx5_ifc_modify_tir_bitmask_bits {
4246         u8         reserved_at_0[0x20];
4247
4248         u8         reserved_at_20[0x1b];
4249         u8         self_lb_en[0x1];
4250         u8         reserved_at_3c[0x3];
4251         u8         lro[0x1];
4252 };
4253
4254 struct mlx5_ifc_modify_tir_out_bits {
4255         u8         status[0x8];
4256         u8         reserved_at_8[0x18];
4257
4258         u8         syndrome[0x20];
4259
4260         u8         reserved_at_40[0x40];
4261 };
4262
4263 struct mlx5_ifc_modify_tir_in_bits {
4264         u8         opcode[0x10];
4265         u8         reserved_at_10[0x10];
4266
4267         u8         reserved_at_20[0x10];
4268         u8         op_mod[0x10];
4269
4270         u8         reserved_at_40[0x8];
4271         u8         tirn[0x18];
4272
4273         u8         reserved_at_60[0x20];
4274
4275         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4276
4277         u8         reserved_at_c0[0x40];
4278
4279         struct mlx5_ifc_tirc_bits ctx;
4280 };
4281
4282 struct mlx5_ifc_modify_sq_out_bits {
4283         u8         status[0x8];
4284         u8         reserved_at_8[0x18];
4285
4286         u8         syndrome[0x20];
4287
4288         u8         reserved_at_40[0x40];
4289 };
4290
4291 struct mlx5_ifc_modify_sq_in_bits {
4292         u8         opcode[0x10];
4293         u8         reserved_at_10[0x10];
4294
4295         u8         reserved_at_20[0x10];
4296         u8         op_mod[0x10];
4297
4298         u8         sq_state[0x4];
4299         u8         reserved_at_44[0x4];
4300         u8         sqn[0x18];
4301
4302         u8         reserved_at_60[0x20];
4303
4304         u8         modify_bitmask[0x40];
4305
4306         u8         reserved_at_c0[0x40];
4307
4308         struct mlx5_ifc_sqc_bits ctx;
4309 };
4310
4311 struct mlx5_ifc_modify_rqt_out_bits {
4312         u8         status[0x8];
4313         u8         reserved_at_8[0x18];
4314
4315         u8         syndrome[0x20];
4316
4317         u8         reserved_at_40[0x40];
4318 };
4319
4320 struct mlx5_ifc_rqt_bitmask_bits {
4321         u8         reserved_at_0[0x20];
4322
4323         u8         reserved_at_20[0x1f];
4324         u8         rqn_list[0x1];
4325 };
4326
4327 struct mlx5_ifc_modify_rqt_in_bits {
4328         u8         opcode[0x10];
4329         u8         reserved_at_10[0x10];
4330
4331         u8         reserved_at_20[0x10];
4332         u8         op_mod[0x10];
4333
4334         u8         reserved_at_40[0x8];
4335         u8         rqtn[0x18];
4336
4337         u8         reserved_at_60[0x20];
4338
4339         struct mlx5_ifc_rqt_bitmask_bits bitmask;
4340
4341         u8         reserved_at_c0[0x40];
4342
4343         struct mlx5_ifc_rqtc_bits ctx;
4344 };
4345
4346 struct mlx5_ifc_modify_rq_out_bits {
4347         u8         status[0x8];
4348         u8         reserved_at_8[0x18];
4349
4350         u8         syndrome[0x20];
4351
4352         u8         reserved_at_40[0x40];
4353 };
4354
4355 struct mlx5_ifc_modify_rq_in_bits {
4356         u8         opcode[0x10];
4357         u8         reserved_at_10[0x10];
4358
4359         u8         reserved_at_20[0x10];
4360         u8         op_mod[0x10];
4361
4362         u8         rq_state[0x4];
4363         u8         reserved_at_44[0x4];
4364         u8         rqn[0x18];
4365
4366         u8         reserved_at_60[0x20];
4367
4368         u8         modify_bitmask[0x40];
4369
4370         u8         reserved_at_c0[0x40];
4371
4372         struct mlx5_ifc_rqc_bits ctx;
4373 };
4374
4375 struct mlx5_ifc_modify_rmp_out_bits {
4376         u8         status[0x8];
4377         u8         reserved_at_8[0x18];
4378
4379         u8         syndrome[0x20];
4380
4381         u8         reserved_at_40[0x40];
4382 };
4383
4384 struct mlx5_ifc_rmp_bitmask_bits {
4385         u8         reserved_at_0[0x20];
4386
4387         u8         reserved_at_20[0x1f];
4388         u8         lwm[0x1];
4389 };
4390
4391 struct mlx5_ifc_modify_rmp_in_bits {
4392         u8         opcode[0x10];
4393         u8         reserved_at_10[0x10];
4394
4395         u8         reserved_at_20[0x10];
4396         u8         op_mod[0x10];
4397
4398         u8         rmp_state[0x4];
4399         u8         reserved_at_44[0x4];
4400         u8         rmpn[0x18];
4401
4402         u8         reserved_at_60[0x20];
4403
4404         struct mlx5_ifc_rmp_bitmask_bits bitmask;
4405
4406         u8         reserved_at_c0[0x40];
4407
4408         struct mlx5_ifc_rmpc_bits ctx;
4409 };
4410
4411 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4412         u8         status[0x8];
4413         u8         reserved_at_8[0x18];
4414
4415         u8         syndrome[0x20];
4416
4417         u8         reserved_at_40[0x40];
4418 };
4419
4420 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4421         u8         reserved_at_0[0x19];
4422         u8         mtu[0x1];
4423         u8         change_event[0x1];
4424         u8         promisc[0x1];
4425         u8         permanent_address[0x1];
4426         u8         addresses_list[0x1];
4427         u8         roce_en[0x1];
4428         u8         reserved_at_1f[0x1];
4429 };
4430
4431 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4432         u8         opcode[0x10];
4433         u8         reserved_at_10[0x10];
4434
4435         u8         reserved_at_20[0x10];
4436         u8         op_mod[0x10];
4437
4438         u8         other_vport[0x1];
4439         u8         reserved_at_41[0xf];
4440         u8         vport_number[0x10];
4441
4442         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4443
4444         u8         reserved_at_80[0x780];
4445
4446         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4447 };
4448
4449 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4450         u8         status[0x8];
4451         u8         reserved_at_8[0x18];
4452
4453         u8         syndrome[0x20];
4454
4455         u8         reserved_at_40[0x40];
4456 };
4457
4458 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4459         u8         opcode[0x10];
4460         u8         reserved_at_10[0x10];
4461
4462         u8         reserved_at_20[0x10];
4463         u8         op_mod[0x10];
4464
4465         u8         other_vport[0x1];
4466         u8         reserved_at_41[0xb];
4467         u8         port_num[0x4];
4468         u8         vport_number[0x10];
4469
4470         u8         reserved_at_60[0x20];
4471
4472         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4473 };
4474
4475 struct mlx5_ifc_modify_cq_out_bits {
4476         u8         status[0x8];
4477         u8         reserved_at_8[0x18];
4478
4479         u8         syndrome[0x20];
4480
4481         u8         reserved_at_40[0x40];
4482 };
4483
4484 enum {
4485         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
4486         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
4487 };
4488
4489 struct mlx5_ifc_modify_cq_in_bits {
4490         u8         opcode[0x10];
4491         u8         reserved_at_10[0x10];
4492
4493         u8         reserved_at_20[0x10];
4494         u8         op_mod[0x10];
4495
4496         u8         reserved_at_40[0x8];
4497         u8         cqn[0x18];
4498
4499         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4500
4501         struct mlx5_ifc_cqc_bits cq_context;
4502
4503         u8         reserved_at_280[0x600];
4504
4505         u8         pas[0][0x40];
4506 };
4507
4508 struct mlx5_ifc_modify_cong_status_out_bits {
4509         u8         status[0x8];
4510         u8         reserved_at_8[0x18];
4511
4512         u8         syndrome[0x20];
4513
4514         u8         reserved_at_40[0x40];
4515 };
4516
4517 struct mlx5_ifc_modify_cong_status_in_bits {
4518         u8         opcode[0x10];
4519         u8         reserved_at_10[0x10];
4520
4521         u8         reserved_at_20[0x10];
4522         u8         op_mod[0x10];
4523
4524         u8         reserved_at_40[0x18];
4525         u8         priority[0x4];
4526         u8         cong_protocol[0x4];
4527
4528         u8         enable[0x1];
4529         u8         tag_enable[0x1];
4530         u8         reserved_at_62[0x1e];
4531 };
4532
4533 struct mlx5_ifc_modify_cong_params_out_bits {
4534         u8         status[0x8];
4535         u8         reserved_at_8[0x18];
4536
4537         u8         syndrome[0x20];
4538
4539         u8         reserved_at_40[0x40];
4540 };
4541
4542 struct mlx5_ifc_modify_cong_params_in_bits {
4543         u8         opcode[0x10];
4544         u8         reserved_at_10[0x10];
4545
4546         u8         reserved_at_20[0x10];
4547         u8         op_mod[0x10];
4548
4549         u8         reserved_at_40[0x1c];
4550         u8         cong_protocol[0x4];
4551
4552         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4553
4554         u8         reserved_at_80[0x80];
4555
4556         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4557 };
4558
4559 struct mlx5_ifc_manage_pages_out_bits {
4560         u8         status[0x8];
4561         u8         reserved_at_8[0x18];
4562
4563         u8         syndrome[0x20];
4564
4565         u8         output_num_entries[0x20];
4566
4567         u8         reserved_at_60[0x20];
4568
4569         u8         pas[0][0x40];
4570 };
4571
4572 enum {
4573         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
4574         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
4575         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
4576 };
4577
4578 struct mlx5_ifc_manage_pages_in_bits {
4579         u8         opcode[0x10];
4580         u8         reserved_at_10[0x10];
4581
4582         u8         reserved_at_20[0x10];
4583         u8         op_mod[0x10];
4584
4585         u8         reserved_at_40[0x10];
4586         u8         function_id[0x10];
4587
4588         u8         input_num_entries[0x20];
4589
4590         u8         pas[0][0x40];
4591 };
4592
4593 struct mlx5_ifc_mad_ifc_out_bits {
4594         u8         status[0x8];
4595         u8         reserved_at_8[0x18];
4596
4597         u8         syndrome[0x20];
4598
4599         u8         reserved_at_40[0x40];
4600
4601         u8         response_mad_packet[256][0x8];
4602 };
4603
4604 struct mlx5_ifc_mad_ifc_in_bits {
4605         u8         opcode[0x10];
4606         u8         reserved_at_10[0x10];
4607
4608         u8         reserved_at_20[0x10];
4609         u8         op_mod[0x10];
4610
4611         u8         remote_lid[0x10];
4612         u8         reserved_at_50[0x8];
4613         u8         port[0x8];
4614
4615         u8         reserved_at_60[0x20];
4616
4617         u8         mad[256][0x8];
4618 };
4619
4620 struct mlx5_ifc_init_hca_out_bits {
4621         u8         status[0x8];
4622         u8         reserved_at_8[0x18];
4623
4624         u8         syndrome[0x20];
4625
4626         u8         reserved_at_40[0x40];
4627 };
4628
4629 struct mlx5_ifc_init_hca_in_bits {
4630         u8         opcode[0x10];
4631         u8         reserved_at_10[0x10];
4632
4633         u8         reserved_at_20[0x10];
4634         u8         op_mod[0x10];
4635
4636         u8         reserved_at_40[0x40];
4637 };
4638
4639 struct mlx5_ifc_init2rtr_qp_out_bits {
4640         u8         status[0x8];
4641         u8         reserved_at_8[0x18];
4642
4643         u8         syndrome[0x20];
4644
4645         u8         reserved_at_40[0x40];
4646 };
4647
4648 struct mlx5_ifc_init2rtr_qp_in_bits {
4649         u8         opcode[0x10];
4650         u8         reserved_at_10[0x10];
4651
4652         u8         reserved_at_20[0x10];
4653         u8         op_mod[0x10];
4654
4655         u8         reserved_at_40[0x8];
4656         u8         qpn[0x18];
4657
4658         u8         reserved_at_60[0x20];
4659
4660         u8         opt_param_mask[0x20];
4661
4662         u8         reserved_at_a0[0x20];
4663
4664         struct mlx5_ifc_qpc_bits qpc;
4665
4666         u8         reserved_at_800[0x80];
4667 };
4668
4669 struct mlx5_ifc_init2init_qp_out_bits {
4670         u8         status[0x8];
4671         u8         reserved_at_8[0x18];
4672
4673         u8         syndrome[0x20];
4674
4675         u8         reserved_at_40[0x40];
4676 };
4677
4678 struct mlx5_ifc_init2init_qp_in_bits {
4679         u8         opcode[0x10];
4680         u8         reserved_at_10[0x10];
4681
4682         u8         reserved_at_20[0x10];
4683         u8         op_mod[0x10];
4684
4685         u8         reserved_at_40[0x8];
4686         u8         qpn[0x18];
4687
4688         u8         reserved_at_60[0x20];
4689
4690         u8         opt_param_mask[0x20];
4691
4692         u8         reserved_at_a0[0x20];
4693
4694         struct mlx5_ifc_qpc_bits qpc;
4695
4696         u8         reserved_at_800[0x80];
4697 };
4698
4699 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4700         u8         status[0x8];
4701         u8         reserved_at_8[0x18];
4702
4703         u8         syndrome[0x20];
4704
4705         u8         reserved_at_40[0x40];
4706
4707         u8         packet_headers_log[128][0x8];
4708
4709         u8         packet_syndrome[64][0x8];
4710 };
4711
4712 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4713         u8         opcode[0x10];
4714         u8         reserved_at_10[0x10];
4715
4716         u8         reserved_at_20[0x10];
4717         u8         op_mod[0x10];
4718
4719         u8         reserved_at_40[0x40];
4720 };
4721
4722 struct mlx5_ifc_gen_eqe_in_bits {
4723         u8         opcode[0x10];
4724         u8         reserved_at_10[0x10];
4725
4726         u8         reserved_at_20[0x10];
4727         u8         op_mod[0x10];
4728
4729         u8         reserved_at_40[0x18];
4730         u8         eq_number[0x8];
4731
4732         u8         reserved_at_60[0x20];
4733
4734         u8         eqe[64][0x8];
4735 };
4736
4737 struct mlx5_ifc_gen_eq_out_bits {
4738         u8         status[0x8];
4739         u8         reserved_at_8[0x18];
4740
4741         u8         syndrome[0x20];
4742
4743         u8         reserved_at_40[0x40];
4744 };
4745
4746 struct mlx5_ifc_enable_hca_out_bits {
4747         u8         status[0x8];
4748         u8         reserved_at_8[0x18];
4749
4750         u8         syndrome[0x20];
4751
4752         u8         reserved_at_40[0x20];
4753 };
4754
4755 struct mlx5_ifc_enable_hca_in_bits {
4756         u8         opcode[0x10];
4757         u8         reserved_at_10[0x10];
4758
4759         u8         reserved_at_20[0x10];
4760         u8         op_mod[0x10];
4761
4762         u8         reserved_at_40[0x10];
4763         u8         function_id[0x10];
4764
4765         u8         reserved_at_60[0x20];
4766 };
4767
4768 struct mlx5_ifc_drain_dct_out_bits {
4769         u8         status[0x8];
4770         u8         reserved_at_8[0x18];
4771
4772         u8         syndrome[0x20];
4773
4774         u8         reserved_at_40[0x40];
4775 };
4776
4777 struct mlx5_ifc_drain_dct_in_bits {
4778         u8         opcode[0x10];
4779         u8         reserved_at_10[0x10];
4780
4781         u8         reserved_at_20[0x10];
4782         u8         op_mod[0x10];
4783
4784         u8         reserved_at_40[0x8];
4785         u8         dctn[0x18];
4786
4787         u8         reserved_at_60[0x20];
4788 };
4789
4790 struct mlx5_ifc_disable_hca_out_bits {
4791         u8         status[0x8];
4792         u8         reserved_at_8[0x18];
4793
4794         u8         syndrome[0x20];
4795
4796         u8         reserved_at_40[0x20];
4797 };
4798
4799 struct mlx5_ifc_disable_hca_in_bits {
4800         u8         opcode[0x10];
4801         u8         reserved_at_10[0x10];
4802
4803         u8         reserved_at_20[0x10];
4804         u8         op_mod[0x10];
4805
4806         u8         reserved_at_40[0x10];
4807         u8         function_id[0x10];
4808
4809         u8         reserved_at_60[0x20];
4810 };
4811
4812 struct mlx5_ifc_detach_from_mcg_out_bits {
4813         u8         status[0x8];
4814         u8         reserved_at_8[0x18];
4815
4816         u8         syndrome[0x20];
4817
4818         u8         reserved_at_40[0x40];
4819 };
4820
4821 struct mlx5_ifc_detach_from_mcg_in_bits {
4822         u8         opcode[0x10];
4823         u8         reserved_at_10[0x10];
4824
4825         u8         reserved_at_20[0x10];
4826         u8         op_mod[0x10];
4827
4828         u8         reserved_at_40[0x8];
4829         u8         qpn[0x18];
4830
4831         u8         reserved_at_60[0x20];
4832
4833         u8         multicast_gid[16][0x8];
4834 };
4835
4836 struct mlx5_ifc_destroy_xrc_srq_out_bits {
4837         u8         status[0x8];
4838         u8         reserved_at_8[0x18];
4839
4840         u8         syndrome[0x20];
4841
4842         u8         reserved_at_40[0x40];
4843 };
4844
4845 struct mlx5_ifc_destroy_xrc_srq_in_bits {
4846         u8         opcode[0x10];
4847         u8         reserved_at_10[0x10];
4848
4849         u8         reserved_at_20[0x10];
4850         u8         op_mod[0x10];
4851
4852         u8         reserved_at_40[0x8];
4853         u8         xrc_srqn[0x18];
4854
4855         u8         reserved_at_60[0x20];
4856 };
4857
4858 struct mlx5_ifc_destroy_tis_out_bits {
4859         u8         status[0x8];
4860         u8         reserved_at_8[0x18];
4861
4862         u8         syndrome[0x20];
4863
4864         u8         reserved_at_40[0x40];
4865 };
4866
4867 struct mlx5_ifc_destroy_tis_in_bits {
4868         u8         opcode[0x10];
4869         u8         reserved_at_10[0x10];
4870
4871         u8         reserved_at_20[0x10];
4872         u8         op_mod[0x10];
4873
4874         u8         reserved_at_40[0x8];
4875         u8         tisn[0x18];
4876
4877         u8         reserved_at_60[0x20];
4878 };
4879
4880 struct mlx5_ifc_destroy_tir_out_bits {
4881         u8         status[0x8];
4882         u8         reserved_at_8[0x18];
4883
4884         u8         syndrome[0x20];
4885
4886         u8         reserved_at_40[0x40];
4887 };
4888
4889 struct mlx5_ifc_destroy_tir_in_bits {
4890         u8         opcode[0x10];
4891         u8         reserved_at_10[0x10];
4892
4893         u8         reserved_at_20[0x10];
4894         u8         op_mod[0x10];
4895
4896         u8         reserved_at_40[0x8];
4897         u8         tirn[0x18];
4898
4899         u8         reserved_at_60[0x20];
4900 };
4901
4902 struct mlx5_ifc_destroy_srq_out_bits {
4903         u8         status[0x8];
4904         u8         reserved_at_8[0x18];
4905
4906         u8         syndrome[0x20];
4907
4908         u8         reserved_at_40[0x40];
4909 };
4910
4911 struct mlx5_ifc_destroy_srq_in_bits {
4912         u8         opcode[0x10];
4913         u8         reserved_at_10[0x10];
4914
4915         u8         reserved_at_20[0x10];
4916         u8         op_mod[0x10];
4917
4918         u8         reserved_at_40[0x8];
4919         u8         srqn[0x18];
4920
4921         u8         reserved_at_60[0x20];
4922 };
4923
4924 struct mlx5_ifc_destroy_sq_out_bits {
4925         u8         status[0x8];
4926         u8         reserved_at_8[0x18];
4927
4928         u8         syndrome[0x20];
4929
4930         u8         reserved_at_40[0x40];
4931 };
4932
4933 struct mlx5_ifc_destroy_sq_in_bits {
4934         u8         opcode[0x10];
4935         u8         reserved_at_10[0x10];
4936
4937         u8         reserved_at_20[0x10];
4938         u8         op_mod[0x10];
4939
4940         u8         reserved_at_40[0x8];
4941         u8         sqn[0x18];
4942
4943         u8         reserved_at_60[0x20];
4944 };
4945
4946 struct mlx5_ifc_destroy_rqt_out_bits {
4947         u8         status[0x8];
4948         u8         reserved_at_8[0x18];
4949
4950         u8         syndrome[0x20];
4951
4952         u8         reserved_at_40[0x40];
4953 };
4954
4955 struct mlx5_ifc_destroy_rqt_in_bits {
4956         u8         opcode[0x10];
4957         u8         reserved_at_10[0x10];
4958
4959         u8         reserved_at_20[0x10];
4960         u8         op_mod[0x10];
4961
4962         u8         reserved_at_40[0x8];
4963         u8         rqtn[0x18];
4964
4965         u8         reserved_at_60[0x20];
4966 };
4967
4968 struct mlx5_ifc_destroy_rq_out_bits {
4969         u8         status[0x8];
4970         u8         reserved_at_8[0x18];
4971
4972         u8         syndrome[0x20];
4973
4974         u8         reserved_at_40[0x40];
4975 };
4976
4977 struct mlx5_ifc_destroy_rq_in_bits {
4978         u8         opcode[0x10];
4979         u8         reserved_at_10[0x10];
4980
4981         u8         reserved_at_20[0x10];
4982         u8         op_mod[0x10];
4983
4984         u8         reserved_at_40[0x8];
4985         u8         rqn[0x18];
4986
4987         u8         reserved_at_60[0x20];
4988 };
4989
4990 struct mlx5_ifc_destroy_rmp_out_bits {
4991         u8         status[0x8];
4992         u8         reserved_at_8[0x18];
4993
4994         u8         syndrome[0x20];
4995
4996         u8         reserved_at_40[0x40];
4997 };
4998
4999 struct mlx5_ifc_destroy_rmp_in_bits {
5000         u8         opcode[0x10];
5001         u8         reserved_at_10[0x10];
5002
5003         u8         reserved_at_20[0x10];
5004         u8         op_mod[0x10];
5005
5006         u8         reserved_at_40[0x8];
5007         u8         rmpn[0x18];
5008
5009         u8         reserved_at_60[0x20];
5010 };
5011
5012 struct mlx5_ifc_destroy_qp_out_bits {
5013         u8         status[0x8];
5014         u8         reserved_at_8[0x18];
5015
5016         u8         syndrome[0x20];
5017
5018         u8         reserved_at_40[0x40];
5019 };
5020
5021 struct mlx5_ifc_destroy_qp_in_bits {
5022         u8         opcode[0x10];
5023         u8         reserved_at_10[0x10];
5024
5025         u8         reserved_at_20[0x10];
5026         u8         op_mod[0x10];
5027
5028         u8         reserved_at_40[0x8];
5029         u8         qpn[0x18];
5030
5031         u8         reserved_at_60[0x20];
5032 };
5033
5034 struct mlx5_ifc_destroy_psv_out_bits {
5035         u8         status[0x8];
5036         u8         reserved_at_8[0x18];
5037
5038         u8         syndrome[0x20];
5039
5040         u8         reserved_at_40[0x40];
5041 };
5042
5043 struct mlx5_ifc_destroy_psv_in_bits {
5044         u8         opcode[0x10];
5045         u8         reserved_at_10[0x10];
5046
5047         u8         reserved_at_20[0x10];
5048         u8         op_mod[0x10];
5049
5050         u8         reserved_at_40[0x8];
5051         u8         psvn[0x18];
5052
5053         u8         reserved_at_60[0x20];
5054 };
5055
5056 struct mlx5_ifc_destroy_mkey_out_bits {
5057         u8         status[0x8];
5058         u8         reserved_at_8[0x18];
5059
5060         u8         syndrome[0x20];
5061
5062         u8         reserved_at_40[0x40];
5063 };
5064
5065 struct mlx5_ifc_destroy_mkey_in_bits {
5066         u8         opcode[0x10];
5067         u8         reserved_at_10[0x10];
5068
5069         u8         reserved_at_20[0x10];
5070         u8         op_mod[0x10];
5071
5072         u8         reserved_at_40[0x8];
5073         u8         mkey_index[0x18];
5074
5075         u8         reserved_at_60[0x20];
5076 };
5077
5078 struct mlx5_ifc_destroy_flow_table_out_bits {
5079         u8         status[0x8];
5080         u8         reserved_at_8[0x18];
5081
5082         u8         syndrome[0x20];
5083
5084         u8         reserved_at_40[0x40];
5085 };
5086
5087 struct mlx5_ifc_destroy_flow_table_in_bits {
5088         u8         opcode[0x10];
5089         u8         reserved_at_10[0x10];
5090
5091         u8         reserved_at_20[0x10];
5092         u8         op_mod[0x10];
5093
5094         u8         reserved_at_40[0x40];
5095
5096         u8         table_type[0x8];
5097         u8         reserved_at_88[0x18];
5098
5099         u8         reserved_at_a0[0x8];
5100         u8         table_id[0x18];
5101
5102         u8         reserved_at_c0[0x140];
5103 };
5104
5105 struct mlx5_ifc_destroy_flow_group_out_bits {
5106         u8         status[0x8];
5107         u8         reserved_at_8[0x18];
5108
5109         u8         syndrome[0x20];
5110
5111         u8         reserved_at_40[0x40];
5112 };
5113
5114 struct mlx5_ifc_destroy_flow_group_in_bits {
5115         u8         opcode[0x10];
5116         u8         reserved_at_10[0x10];
5117
5118         u8         reserved_at_20[0x10];
5119         u8         op_mod[0x10];
5120
5121         u8         reserved_at_40[0x40];
5122
5123         u8         table_type[0x8];
5124         u8         reserved_at_88[0x18];
5125
5126         u8         reserved_at_a0[0x8];
5127         u8         table_id[0x18];
5128
5129         u8         group_id[0x20];
5130
5131         u8         reserved_at_e0[0x120];
5132 };
5133
5134 struct mlx5_ifc_destroy_eq_out_bits {
5135         u8         status[0x8];
5136         u8         reserved_at_8[0x18];
5137
5138         u8         syndrome[0x20];
5139
5140         u8         reserved_at_40[0x40];
5141 };
5142
5143 struct mlx5_ifc_destroy_eq_in_bits {
5144         u8         opcode[0x10];
5145         u8         reserved_at_10[0x10];
5146
5147         u8         reserved_at_20[0x10];
5148         u8         op_mod[0x10];
5149
5150         u8         reserved_at_40[0x18];
5151         u8         eq_number[0x8];
5152
5153         u8         reserved_at_60[0x20];
5154 };
5155
5156 struct mlx5_ifc_destroy_dct_out_bits {
5157         u8         status[0x8];
5158         u8         reserved_at_8[0x18];
5159
5160         u8         syndrome[0x20];
5161
5162         u8         reserved_at_40[0x40];
5163 };
5164
5165 struct mlx5_ifc_destroy_dct_in_bits {
5166         u8         opcode[0x10];
5167         u8         reserved_at_10[0x10];
5168
5169         u8         reserved_at_20[0x10];
5170         u8         op_mod[0x10];
5171
5172         u8         reserved_at_40[0x8];
5173         u8         dctn[0x18];
5174
5175         u8         reserved_at_60[0x20];
5176 };
5177
5178 struct mlx5_ifc_destroy_cq_out_bits {
5179         u8         status[0x8];
5180         u8         reserved_at_8[0x18];
5181
5182         u8         syndrome[0x20];
5183
5184         u8         reserved_at_40[0x40];
5185 };
5186
5187 struct mlx5_ifc_destroy_cq_in_bits {
5188         u8         opcode[0x10];
5189         u8         reserved_at_10[0x10];
5190
5191         u8         reserved_at_20[0x10];
5192         u8         op_mod[0x10];
5193
5194         u8         reserved_at_40[0x8];
5195         u8         cqn[0x18];
5196
5197         u8         reserved_at_60[0x20];
5198 };
5199
5200 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5201         u8         status[0x8];
5202         u8         reserved_at_8[0x18];
5203
5204         u8         syndrome[0x20];
5205
5206         u8         reserved_at_40[0x40];
5207 };
5208
5209 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5210         u8         opcode[0x10];
5211         u8         reserved_at_10[0x10];
5212
5213         u8         reserved_at_20[0x10];
5214         u8         op_mod[0x10];
5215
5216         u8         reserved_at_40[0x20];
5217
5218         u8         reserved_at_60[0x10];
5219         u8         vxlan_udp_port[0x10];
5220 };
5221
5222 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5223         u8         status[0x8];
5224         u8         reserved_at_8[0x18];
5225
5226         u8         syndrome[0x20];
5227
5228         u8         reserved_at_40[0x40];
5229 };
5230
5231 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5232         u8         opcode[0x10];
5233         u8         reserved_at_10[0x10];
5234
5235         u8         reserved_at_20[0x10];
5236         u8         op_mod[0x10];
5237
5238         u8         reserved_at_40[0x60];
5239
5240         u8         reserved_at_a0[0x8];
5241         u8         table_index[0x18];
5242
5243         u8         reserved_at_c0[0x140];
5244 };
5245
5246 struct mlx5_ifc_delete_fte_out_bits {
5247         u8         status[0x8];
5248         u8         reserved_at_8[0x18];
5249
5250         u8         syndrome[0x20];
5251
5252         u8         reserved_at_40[0x40];
5253 };
5254
5255 struct mlx5_ifc_delete_fte_in_bits {
5256         u8         opcode[0x10];
5257         u8         reserved_at_10[0x10];
5258
5259         u8         reserved_at_20[0x10];
5260         u8         op_mod[0x10];
5261
5262         u8         reserved_at_40[0x40];
5263
5264         u8         table_type[0x8];
5265         u8         reserved_at_88[0x18];
5266
5267         u8         reserved_at_a0[0x8];
5268         u8         table_id[0x18];
5269
5270         u8         reserved_at_c0[0x40];
5271
5272         u8         flow_index[0x20];
5273
5274         u8         reserved_at_120[0xe0];
5275 };
5276
5277 struct mlx5_ifc_dealloc_xrcd_out_bits {
5278         u8         status[0x8];
5279         u8         reserved_at_8[0x18];
5280
5281         u8         syndrome[0x20];
5282
5283         u8         reserved_at_40[0x40];
5284 };
5285
5286 struct mlx5_ifc_dealloc_xrcd_in_bits {
5287         u8         opcode[0x10];
5288         u8         reserved_at_10[0x10];
5289
5290         u8         reserved_at_20[0x10];
5291         u8         op_mod[0x10];
5292
5293         u8         reserved_at_40[0x8];
5294         u8         xrcd[0x18];
5295
5296         u8         reserved_at_60[0x20];
5297 };
5298
5299 struct mlx5_ifc_dealloc_uar_out_bits {
5300         u8         status[0x8];
5301         u8         reserved_at_8[0x18];
5302
5303         u8         syndrome[0x20];
5304
5305         u8         reserved_at_40[0x40];
5306 };
5307
5308 struct mlx5_ifc_dealloc_uar_in_bits {
5309         u8         opcode[0x10];
5310         u8         reserved_at_10[0x10];
5311
5312         u8         reserved_at_20[0x10];
5313         u8         op_mod[0x10];
5314
5315         u8         reserved_at_40[0x8];
5316         u8         uar[0x18];
5317
5318         u8         reserved_at_60[0x20];
5319 };
5320
5321 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5322         u8         status[0x8];
5323         u8         reserved_at_8[0x18];
5324
5325         u8         syndrome[0x20];
5326
5327         u8         reserved_at_40[0x40];
5328 };
5329
5330 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5331         u8         opcode[0x10];
5332         u8         reserved_at_10[0x10];
5333
5334         u8         reserved_at_20[0x10];
5335         u8         op_mod[0x10];
5336
5337         u8         reserved_at_40[0x8];
5338         u8         transport_domain[0x18];
5339
5340         u8         reserved_at_60[0x20];
5341 };
5342
5343 struct mlx5_ifc_dealloc_q_counter_out_bits {
5344         u8         status[0x8];
5345         u8         reserved_at_8[0x18];
5346
5347         u8         syndrome[0x20];
5348
5349         u8         reserved_at_40[0x40];
5350 };
5351
5352 struct mlx5_ifc_dealloc_q_counter_in_bits {
5353         u8         opcode[0x10];
5354         u8         reserved_at_10[0x10];
5355
5356         u8         reserved_at_20[0x10];
5357         u8         op_mod[0x10];
5358
5359         u8         reserved_at_40[0x18];
5360         u8         counter_set_id[0x8];
5361
5362         u8         reserved_at_60[0x20];
5363 };
5364
5365 struct mlx5_ifc_dealloc_pd_out_bits {
5366         u8         status[0x8];
5367         u8         reserved_at_8[0x18];
5368
5369         u8         syndrome[0x20];
5370
5371         u8         reserved_at_40[0x40];
5372 };
5373
5374 struct mlx5_ifc_dealloc_pd_in_bits {
5375         u8         opcode[0x10];
5376         u8         reserved_at_10[0x10];
5377
5378         u8         reserved_at_20[0x10];
5379         u8         op_mod[0x10];
5380
5381         u8         reserved_at_40[0x8];
5382         u8         pd[0x18];
5383
5384         u8         reserved_at_60[0x20];
5385 };
5386
5387 struct mlx5_ifc_create_xrc_srq_out_bits {
5388         u8         status[0x8];
5389         u8         reserved_at_8[0x18];
5390
5391         u8         syndrome[0x20];
5392
5393         u8         reserved_at_40[0x8];
5394         u8         xrc_srqn[0x18];
5395
5396         u8         reserved_at_60[0x20];
5397 };
5398
5399 struct mlx5_ifc_create_xrc_srq_in_bits {
5400         u8         opcode[0x10];
5401         u8         reserved_at_10[0x10];
5402
5403         u8         reserved_at_20[0x10];
5404         u8         op_mod[0x10];
5405
5406         u8         reserved_at_40[0x40];
5407
5408         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5409
5410         u8         reserved_at_280[0x600];
5411
5412         u8         pas[0][0x40];
5413 };
5414
5415 struct mlx5_ifc_create_tis_out_bits {
5416         u8         status[0x8];
5417         u8         reserved_at_8[0x18];
5418
5419         u8         syndrome[0x20];
5420
5421         u8         reserved_at_40[0x8];
5422         u8         tisn[0x18];
5423
5424         u8         reserved_at_60[0x20];
5425 };
5426
5427 struct mlx5_ifc_create_tis_in_bits {
5428         u8         opcode[0x10];
5429         u8         reserved_at_10[0x10];
5430
5431         u8         reserved_at_20[0x10];
5432         u8         op_mod[0x10];
5433
5434         u8         reserved_at_40[0xc0];
5435
5436         struct mlx5_ifc_tisc_bits ctx;
5437 };
5438
5439 struct mlx5_ifc_create_tir_out_bits {
5440         u8         status[0x8];
5441         u8         reserved_at_8[0x18];
5442
5443         u8         syndrome[0x20];
5444
5445         u8         reserved_at_40[0x8];
5446         u8         tirn[0x18];
5447
5448         u8         reserved_at_60[0x20];
5449 };
5450
5451 struct mlx5_ifc_create_tir_in_bits {
5452         u8         opcode[0x10];
5453         u8         reserved_at_10[0x10];
5454
5455         u8         reserved_at_20[0x10];
5456         u8         op_mod[0x10];
5457
5458         u8         reserved_at_40[0xc0];
5459
5460         struct mlx5_ifc_tirc_bits ctx;
5461 };
5462
5463 struct mlx5_ifc_create_srq_out_bits {
5464         u8         status[0x8];
5465         u8         reserved_at_8[0x18];
5466
5467         u8         syndrome[0x20];
5468
5469         u8         reserved_at_40[0x8];
5470         u8         srqn[0x18];
5471
5472         u8         reserved_at_60[0x20];
5473 };
5474
5475 struct mlx5_ifc_create_srq_in_bits {
5476         u8         opcode[0x10];
5477         u8         reserved_at_10[0x10];
5478
5479         u8         reserved_at_20[0x10];
5480         u8         op_mod[0x10];
5481
5482         u8         reserved_at_40[0x40];
5483
5484         struct mlx5_ifc_srqc_bits srq_context_entry;
5485
5486         u8         reserved_at_280[0x600];
5487
5488         u8         pas[0][0x40];
5489 };
5490
5491 struct mlx5_ifc_create_sq_out_bits {
5492         u8         status[0x8];
5493         u8         reserved_at_8[0x18];
5494
5495         u8         syndrome[0x20];
5496
5497         u8         reserved_at_40[0x8];
5498         u8         sqn[0x18];
5499
5500         u8         reserved_at_60[0x20];
5501 };
5502
5503 struct mlx5_ifc_create_sq_in_bits {
5504         u8         opcode[0x10];
5505         u8         reserved_at_10[0x10];
5506
5507         u8         reserved_at_20[0x10];
5508         u8         op_mod[0x10];
5509
5510         u8         reserved_at_40[0xc0];
5511
5512         struct mlx5_ifc_sqc_bits ctx;
5513 };
5514
5515 struct mlx5_ifc_create_rqt_out_bits {
5516         u8         status[0x8];
5517         u8         reserved_at_8[0x18];
5518
5519         u8         syndrome[0x20];
5520
5521         u8         reserved_at_40[0x8];
5522         u8         rqtn[0x18];
5523
5524         u8         reserved_at_60[0x20];
5525 };
5526
5527 struct mlx5_ifc_create_rqt_in_bits {
5528         u8         opcode[0x10];
5529         u8         reserved_at_10[0x10];
5530
5531         u8         reserved_at_20[0x10];
5532         u8         op_mod[0x10];
5533
5534         u8         reserved_at_40[0xc0];
5535
5536         struct mlx5_ifc_rqtc_bits rqt_context;
5537 };
5538
5539 struct mlx5_ifc_create_rq_out_bits {
5540         u8         status[0x8];
5541         u8         reserved_at_8[0x18];
5542
5543         u8         syndrome[0x20];
5544
5545         u8         reserved_at_40[0x8];
5546         u8         rqn[0x18];
5547
5548         u8         reserved_at_60[0x20];
5549 };
5550
5551 struct mlx5_ifc_create_rq_in_bits {
5552         u8         opcode[0x10];
5553         u8         reserved_at_10[0x10];
5554
5555         u8         reserved_at_20[0x10];
5556         u8         op_mod[0x10];
5557
5558         u8         reserved_at_40[0xc0];
5559
5560         struct mlx5_ifc_rqc_bits ctx;
5561 };
5562
5563 struct mlx5_ifc_create_rmp_out_bits {
5564         u8         status[0x8];
5565         u8         reserved_at_8[0x18];
5566
5567         u8         syndrome[0x20];
5568
5569         u8         reserved_at_40[0x8];
5570         u8         rmpn[0x18];
5571
5572         u8         reserved_at_60[0x20];
5573 };
5574
5575 struct mlx5_ifc_create_rmp_in_bits {
5576         u8         opcode[0x10];
5577         u8         reserved_at_10[0x10];
5578
5579         u8         reserved_at_20[0x10];
5580         u8         op_mod[0x10];
5581
5582         u8         reserved_at_40[0xc0];
5583
5584         struct mlx5_ifc_rmpc_bits ctx;
5585 };
5586
5587 struct mlx5_ifc_create_qp_out_bits {
5588         u8         status[0x8];
5589         u8         reserved_at_8[0x18];
5590
5591         u8         syndrome[0x20];
5592
5593         u8         reserved_at_40[0x8];
5594         u8         qpn[0x18];
5595
5596         u8         reserved_at_60[0x20];
5597 };
5598
5599 struct mlx5_ifc_create_qp_in_bits {
5600         u8         opcode[0x10];
5601         u8         reserved_at_10[0x10];
5602
5603         u8         reserved_at_20[0x10];
5604         u8         op_mod[0x10];
5605
5606         u8         reserved_at_40[0x40];
5607
5608         u8         opt_param_mask[0x20];
5609
5610         u8         reserved_at_a0[0x20];
5611
5612         struct mlx5_ifc_qpc_bits qpc;
5613
5614         u8         reserved_at_800[0x80];
5615
5616         u8         pas[0][0x40];
5617 };
5618
5619 struct mlx5_ifc_create_psv_out_bits {
5620         u8         status[0x8];
5621         u8         reserved_at_8[0x18];
5622
5623         u8         syndrome[0x20];
5624
5625         u8         reserved_at_40[0x40];
5626
5627         u8         reserved_at_80[0x8];
5628         u8         psv0_index[0x18];
5629
5630         u8         reserved_at_a0[0x8];
5631         u8         psv1_index[0x18];
5632
5633         u8         reserved_at_c0[0x8];
5634         u8         psv2_index[0x18];
5635
5636         u8         reserved_at_e0[0x8];
5637         u8         psv3_index[0x18];
5638 };
5639
5640 struct mlx5_ifc_create_psv_in_bits {
5641         u8         opcode[0x10];
5642         u8         reserved_at_10[0x10];
5643
5644         u8         reserved_at_20[0x10];
5645         u8         op_mod[0x10];
5646
5647         u8         num_psv[0x4];
5648         u8         reserved_at_44[0x4];
5649         u8         pd[0x18];
5650
5651         u8         reserved_at_60[0x20];
5652 };
5653
5654 struct mlx5_ifc_create_mkey_out_bits {
5655         u8         status[0x8];
5656         u8         reserved_at_8[0x18];
5657
5658         u8         syndrome[0x20];
5659
5660         u8         reserved_at_40[0x8];
5661         u8         mkey_index[0x18];
5662
5663         u8         reserved_at_60[0x20];
5664 };
5665
5666 struct mlx5_ifc_create_mkey_in_bits {
5667         u8         opcode[0x10];
5668         u8         reserved_at_10[0x10];
5669
5670         u8         reserved_at_20[0x10];
5671         u8         op_mod[0x10];
5672
5673         u8         reserved_at_40[0x20];
5674
5675         u8         pg_access[0x1];
5676         u8         reserved_at_61[0x1f];
5677
5678         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5679
5680         u8         reserved_at_280[0x80];
5681
5682         u8         translations_octword_actual_size[0x20];
5683
5684         u8         reserved_at_320[0x560];
5685
5686         u8         klm_pas_mtt[0][0x20];
5687 };
5688
5689 struct mlx5_ifc_create_flow_table_out_bits {
5690         u8         status[0x8];
5691         u8         reserved_at_8[0x18];
5692
5693         u8         syndrome[0x20];
5694
5695         u8         reserved_at_40[0x8];
5696         u8         table_id[0x18];
5697
5698         u8         reserved_at_60[0x20];
5699 };
5700
5701 struct mlx5_ifc_create_flow_table_in_bits {
5702         u8         opcode[0x10];
5703         u8         reserved_at_10[0x10];
5704
5705         u8         reserved_at_20[0x10];
5706         u8         op_mod[0x10];
5707
5708         u8         reserved_at_40[0x40];
5709
5710         u8         table_type[0x8];
5711         u8         reserved_at_88[0x18];
5712
5713         u8         reserved_at_a0[0x20];
5714
5715         u8         reserved_at_c0[0x4];
5716         u8         table_miss_mode[0x4];
5717         u8         level[0x8];
5718         u8         reserved_at_d0[0x8];
5719         u8         log_size[0x8];
5720
5721         u8         reserved_at_e0[0x8];
5722         u8         table_miss_id[0x18];
5723
5724         u8         reserved_at_100[0x100];
5725 };
5726
5727 struct mlx5_ifc_create_flow_group_out_bits {
5728         u8         status[0x8];
5729         u8         reserved_at_8[0x18];
5730
5731         u8         syndrome[0x20];
5732
5733         u8         reserved_at_40[0x8];
5734         u8         group_id[0x18];
5735
5736         u8         reserved_at_60[0x20];
5737 };
5738
5739 enum {
5740         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5741         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5742         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5743 };
5744
5745 struct mlx5_ifc_create_flow_group_in_bits {
5746         u8         opcode[0x10];
5747         u8         reserved_at_10[0x10];
5748
5749         u8         reserved_at_20[0x10];
5750         u8         op_mod[0x10];
5751
5752         u8         reserved_at_40[0x40];
5753
5754         u8         table_type[0x8];
5755         u8         reserved_at_88[0x18];
5756
5757         u8         reserved_at_a0[0x8];
5758         u8         table_id[0x18];
5759
5760         u8         reserved_at_c0[0x20];
5761
5762         u8         start_flow_index[0x20];
5763
5764         u8         reserved_at_100[0x20];
5765
5766         u8         end_flow_index[0x20];
5767
5768         u8         reserved_at_140[0xa0];
5769
5770         u8         reserved_at_1e0[0x18];
5771         u8         match_criteria_enable[0x8];
5772
5773         struct mlx5_ifc_fte_match_param_bits match_criteria;
5774
5775         u8         reserved_at_1200[0xe00];
5776 };
5777
5778 struct mlx5_ifc_create_eq_out_bits {
5779         u8         status[0x8];
5780         u8         reserved_at_8[0x18];
5781
5782         u8         syndrome[0x20];
5783
5784         u8         reserved_at_40[0x18];
5785         u8         eq_number[0x8];
5786
5787         u8         reserved_at_60[0x20];
5788 };
5789
5790 struct mlx5_ifc_create_eq_in_bits {
5791         u8         opcode[0x10];
5792         u8         reserved_at_10[0x10];
5793
5794         u8         reserved_at_20[0x10];
5795         u8         op_mod[0x10];
5796
5797         u8         reserved_at_40[0x40];
5798
5799         struct mlx5_ifc_eqc_bits eq_context_entry;
5800
5801         u8         reserved_at_280[0x40];
5802
5803         u8         event_bitmask[0x40];
5804
5805         u8         reserved_at_300[0x580];
5806
5807         u8         pas[0][0x40];
5808 };
5809
5810 struct mlx5_ifc_create_dct_out_bits {
5811         u8         status[0x8];
5812         u8         reserved_at_8[0x18];
5813
5814         u8         syndrome[0x20];
5815
5816         u8         reserved_at_40[0x8];
5817         u8         dctn[0x18];
5818
5819         u8         reserved_at_60[0x20];
5820 };
5821
5822 struct mlx5_ifc_create_dct_in_bits {
5823         u8         opcode[0x10];
5824         u8         reserved_at_10[0x10];
5825
5826         u8         reserved_at_20[0x10];
5827         u8         op_mod[0x10];
5828
5829         u8         reserved_at_40[0x40];
5830
5831         struct mlx5_ifc_dctc_bits dct_context_entry;
5832
5833         u8         reserved_at_280[0x180];
5834 };
5835
5836 struct mlx5_ifc_create_cq_out_bits {
5837         u8         status[0x8];
5838         u8         reserved_at_8[0x18];
5839
5840         u8         syndrome[0x20];
5841
5842         u8         reserved_at_40[0x8];
5843         u8         cqn[0x18];
5844
5845         u8         reserved_at_60[0x20];
5846 };
5847
5848 struct mlx5_ifc_create_cq_in_bits {
5849         u8         opcode[0x10];
5850         u8         reserved_at_10[0x10];
5851
5852         u8         reserved_at_20[0x10];
5853         u8         op_mod[0x10];
5854
5855         u8         reserved_at_40[0x40];
5856
5857         struct mlx5_ifc_cqc_bits cq_context;
5858
5859         u8         reserved_at_280[0x600];
5860
5861         u8         pas[0][0x40];
5862 };
5863
5864 struct mlx5_ifc_config_int_moderation_out_bits {
5865         u8         status[0x8];
5866         u8         reserved_at_8[0x18];
5867
5868         u8         syndrome[0x20];
5869
5870         u8         reserved_at_40[0x4];
5871         u8         min_delay[0xc];
5872         u8         int_vector[0x10];
5873
5874         u8         reserved_at_60[0x20];
5875 };
5876
5877 enum {
5878         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
5879         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
5880 };
5881
5882 struct mlx5_ifc_config_int_moderation_in_bits {
5883         u8         opcode[0x10];
5884         u8         reserved_at_10[0x10];
5885
5886         u8         reserved_at_20[0x10];
5887         u8         op_mod[0x10];
5888
5889         u8         reserved_at_40[0x4];
5890         u8         min_delay[0xc];
5891         u8         int_vector[0x10];
5892
5893         u8         reserved_at_60[0x20];
5894 };
5895
5896 struct mlx5_ifc_attach_to_mcg_out_bits {
5897         u8         status[0x8];
5898         u8         reserved_at_8[0x18];
5899
5900         u8         syndrome[0x20];
5901
5902         u8         reserved_at_40[0x40];
5903 };
5904
5905 struct mlx5_ifc_attach_to_mcg_in_bits {
5906         u8         opcode[0x10];
5907         u8         reserved_at_10[0x10];
5908
5909         u8         reserved_at_20[0x10];
5910         u8         op_mod[0x10];
5911
5912         u8         reserved_at_40[0x8];
5913         u8         qpn[0x18];
5914
5915         u8         reserved_at_60[0x20];
5916
5917         u8         multicast_gid[16][0x8];
5918 };
5919
5920 struct mlx5_ifc_arm_xrc_srq_out_bits {
5921         u8         status[0x8];
5922         u8         reserved_at_8[0x18];
5923
5924         u8         syndrome[0x20];
5925
5926         u8         reserved_at_40[0x40];
5927 };
5928
5929 enum {
5930         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
5931 };
5932
5933 struct mlx5_ifc_arm_xrc_srq_in_bits {
5934         u8         opcode[0x10];
5935         u8         reserved_at_10[0x10];
5936
5937         u8         reserved_at_20[0x10];
5938         u8         op_mod[0x10];
5939
5940         u8         reserved_at_40[0x8];
5941         u8         xrc_srqn[0x18];
5942
5943         u8         reserved_at_60[0x10];
5944         u8         lwm[0x10];
5945 };
5946
5947 struct mlx5_ifc_arm_rq_out_bits {
5948         u8         status[0x8];
5949         u8         reserved_at_8[0x18];
5950
5951         u8         syndrome[0x20];
5952
5953         u8         reserved_at_40[0x40];
5954 };
5955
5956 enum {
5957         MLX5_ARM_RQ_IN_OP_MOD_SRQ_  = 0x1,
5958 };
5959
5960 struct mlx5_ifc_arm_rq_in_bits {
5961         u8         opcode[0x10];
5962         u8         reserved_at_10[0x10];
5963
5964         u8         reserved_at_20[0x10];
5965         u8         op_mod[0x10];
5966
5967         u8         reserved_at_40[0x8];
5968         u8         srq_number[0x18];
5969
5970         u8         reserved_at_60[0x10];
5971         u8         lwm[0x10];
5972 };
5973
5974 struct mlx5_ifc_arm_dct_out_bits {
5975         u8         status[0x8];
5976         u8         reserved_at_8[0x18];
5977
5978         u8         syndrome[0x20];
5979
5980         u8         reserved_at_40[0x40];
5981 };
5982
5983 struct mlx5_ifc_arm_dct_in_bits {
5984         u8         opcode[0x10];
5985         u8         reserved_at_10[0x10];
5986
5987         u8         reserved_at_20[0x10];
5988         u8         op_mod[0x10];
5989
5990         u8         reserved_at_40[0x8];
5991         u8         dct_number[0x18];
5992
5993         u8         reserved_at_60[0x20];
5994 };
5995
5996 struct mlx5_ifc_alloc_xrcd_out_bits {
5997         u8         status[0x8];
5998         u8         reserved_at_8[0x18];
5999
6000         u8         syndrome[0x20];
6001
6002         u8         reserved_at_40[0x8];
6003         u8         xrcd[0x18];
6004
6005         u8         reserved_at_60[0x20];
6006 };
6007
6008 struct mlx5_ifc_alloc_xrcd_in_bits {
6009         u8         opcode[0x10];
6010         u8         reserved_at_10[0x10];
6011
6012         u8         reserved_at_20[0x10];
6013         u8         op_mod[0x10];
6014
6015         u8         reserved_at_40[0x40];
6016 };
6017
6018 struct mlx5_ifc_alloc_uar_out_bits {
6019         u8         status[0x8];
6020         u8         reserved_at_8[0x18];
6021
6022         u8         syndrome[0x20];
6023
6024         u8         reserved_at_40[0x8];
6025         u8         uar[0x18];
6026
6027         u8         reserved_at_60[0x20];
6028 };
6029
6030 struct mlx5_ifc_alloc_uar_in_bits {
6031         u8         opcode[0x10];
6032         u8         reserved_at_10[0x10];
6033
6034         u8         reserved_at_20[0x10];
6035         u8         op_mod[0x10];
6036
6037         u8         reserved_at_40[0x40];
6038 };
6039
6040 struct mlx5_ifc_alloc_transport_domain_out_bits {
6041         u8         status[0x8];
6042         u8         reserved_at_8[0x18];
6043
6044         u8         syndrome[0x20];
6045
6046         u8         reserved_at_40[0x8];
6047         u8         transport_domain[0x18];
6048
6049         u8         reserved_at_60[0x20];
6050 };
6051
6052 struct mlx5_ifc_alloc_transport_domain_in_bits {
6053         u8         opcode[0x10];
6054         u8         reserved_at_10[0x10];
6055
6056         u8         reserved_at_20[0x10];
6057         u8         op_mod[0x10];
6058
6059         u8         reserved_at_40[0x40];
6060 };
6061
6062 struct mlx5_ifc_alloc_q_counter_out_bits {
6063         u8         status[0x8];
6064         u8         reserved_at_8[0x18];
6065
6066         u8         syndrome[0x20];
6067
6068         u8         reserved_at_40[0x18];
6069         u8         counter_set_id[0x8];
6070
6071         u8         reserved_at_60[0x20];
6072 };
6073
6074 struct mlx5_ifc_alloc_q_counter_in_bits {
6075         u8         opcode[0x10];
6076         u8         reserved_at_10[0x10];
6077
6078         u8         reserved_at_20[0x10];
6079         u8         op_mod[0x10];
6080
6081         u8         reserved_at_40[0x40];
6082 };
6083
6084 struct mlx5_ifc_alloc_pd_out_bits {
6085         u8         status[0x8];
6086         u8         reserved_at_8[0x18];
6087
6088         u8         syndrome[0x20];
6089
6090         u8         reserved_at_40[0x8];
6091         u8         pd[0x18];
6092
6093         u8         reserved_at_60[0x20];
6094 };
6095
6096 struct mlx5_ifc_alloc_pd_in_bits {
6097         u8         opcode[0x10];
6098         u8         reserved_at_10[0x10];
6099
6100         u8         reserved_at_20[0x10];
6101         u8         op_mod[0x10];
6102
6103         u8         reserved_at_40[0x40];
6104 };
6105
6106 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6107         u8         status[0x8];
6108         u8         reserved_at_8[0x18];
6109
6110         u8         syndrome[0x20];
6111
6112         u8         reserved_at_40[0x40];
6113 };
6114
6115 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6116         u8         opcode[0x10];
6117         u8         reserved_at_10[0x10];
6118
6119         u8         reserved_at_20[0x10];
6120         u8         op_mod[0x10];
6121
6122         u8         reserved_at_40[0x20];
6123
6124         u8         reserved_at_60[0x10];
6125         u8         vxlan_udp_port[0x10];
6126 };
6127
6128 struct mlx5_ifc_access_register_out_bits {
6129         u8         status[0x8];
6130         u8         reserved_at_8[0x18];
6131
6132         u8         syndrome[0x20];
6133
6134         u8         reserved_at_40[0x40];
6135
6136         u8         register_data[0][0x20];
6137 };
6138
6139 enum {
6140         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
6141         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
6142 };
6143
6144 struct mlx5_ifc_access_register_in_bits {
6145         u8         opcode[0x10];
6146         u8         reserved_at_10[0x10];
6147
6148         u8         reserved_at_20[0x10];
6149         u8         op_mod[0x10];
6150
6151         u8         reserved_at_40[0x10];
6152         u8         register_id[0x10];
6153
6154         u8         argument[0x20];
6155
6156         u8         register_data[0][0x20];
6157 };
6158
6159 struct mlx5_ifc_sltp_reg_bits {
6160         u8         status[0x4];
6161         u8         version[0x4];
6162         u8         local_port[0x8];
6163         u8         pnat[0x2];
6164         u8         reserved_at_12[0x2];
6165         u8         lane[0x4];
6166         u8         reserved_at_18[0x8];
6167
6168         u8         reserved_at_20[0x20];
6169
6170         u8         reserved_at_40[0x7];
6171         u8         polarity[0x1];
6172         u8         ob_tap0[0x8];
6173         u8         ob_tap1[0x8];
6174         u8         ob_tap2[0x8];
6175
6176         u8         reserved_at_60[0xc];
6177         u8         ob_preemp_mode[0x4];
6178         u8         ob_reg[0x8];
6179         u8         ob_bias[0x8];
6180
6181         u8         reserved_at_80[0x20];
6182 };
6183
6184 struct mlx5_ifc_slrg_reg_bits {
6185         u8         status[0x4];
6186         u8         version[0x4];
6187         u8         local_port[0x8];
6188         u8         pnat[0x2];
6189         u8         reserved_at_12[0x2];
6190         u8         lane[0x4];
6191         u8         reserved_at_18[0x8];
6192
6193         u8         time_to_link_up[0x10];
6194         u8         reserved_at_30[0xc];
6195         u8         grade_lane_speed[0x4];
6196
6197         u8         grade_version[0x8];
6198         u8         grade[0x18];
6199
6200         u8         reserved_at_60[0x4];
6201         u8         height_grade_type[0x4];
6202         u8         height_grade[0x18];
6203
6204         u8         height_dz[0x10];
6205         u8         height_dv[0x10];
6206
6207         u8         reserved_at_a0[0x10];
6208         u8         height_sigma[0x10];
6209
6210         u8         reserved_at_c0[0x20];
6211
6212         u8         reserved_at_e0[0x4];
6213         u8         phase_grade_type[0x4];
6214         u8         phase_grade[0x18];
6215
6216         u8         reserved_at_100[0x8];
6217         u8         phase_eo_pos[0x8];
6218         u8         reserved_at_110[0x8];
6219         u8         phase_eo_neg[0x8];
6220
6221         u8         ffe_set_tested[0x10];
6222         u8         test_errors_per_lane[0x10];
6223 };
6224
6225 struct mlx5_ifc_pvlc_reg_bits {
6226         u8         reserved_at_0[0x8];
6227         u8         local_port[0x8];
6228         u8         reserved_at_10[0x10];
6229
6230         u8         reserved_at_20[0x1c];
6231         u8         vl_hw_cap[0x4];
6232
6233         u8         reserved_at_40[0x1c];
6234         u8         vl_admin[0x4];
6235
6236         u8         reserved_at_60[0x1c];
6237         u8         vl_operational[0x4];
6238 };
6239
6240 struct mlx5_ifc_pude_reg_bits {
6241         u8         swid[0x8];
6242         u8         local_port[0x8];
6243         u8         reserved_at_10[0x4];
6244         u8         admin_status[0x4];
6245         u8         reserved_at_18[0x4];
6246         u8         oper_status[0x4];
6247
6248         u8         reserved_at_20[0x60];
6249 };
6250
6251 struct mlx5_ifc_ptys_reg_bits {
6252         u8         reserved_at_0[0x8];
6253         u8         local_port[0x8];
6254         u8         reserved_at_10[0xd];
6255         u8         proto_mask[0x3];
6256
6257         u8         reserved_at_20[0x40];
6258
6259         u8         eth_proto_capability[0x20];
6260
6261         u8         ib_link_width_capability[0x10];
6262         u8         ib_proto_capability[0x10];
6263
6264         u8         reserved_at_a0[0x20];
6265
6266         u8         eth_proto_admin[0x20];
6267
6268         u8         ib_link_width_admin[0x10];
6269         u8         ib_proto_admin[0x10];
6270
6271         u8         reserved_at_100[0x20];
6272
6273         u8         eth_proto_oper[0x20];
6274
6275         u8         ib_link_width_oper[0x10];
6276         u8         ib_proto_oper[0x10];
6277
6278         u8         reserved_at_160[0x20];
6279
6280         u8         eth_proto_lp_advertise[0x20];
6281
6282         u8         reserved_at_1a0[0x60];
6283 };
6284
6285 struct mlx5_ifc_ptas_reg_bits {
6286         u8         reserved_at_0[0x20];
6287
6288         u8         algorithm_options[0x10];
6289         u8         reserved_at_30[0x4];
6290         u8         repetitions_mode[0x4];
6291         u8         num_of_repetitions[0x8];
6292
6293         u8         grade_version[0x8];
6294         u8         height_grade_type[0x4];
6295         u8         phase_grade_type[0x4];
6296         u8         height_grade_weight[0x8];
6297         u8         phase_grade_weight[0x8];
6298
6299         u8         gisim_measure_bits[0x10];
6300         u8         adaptive_tap_measure_bits[0x10];
6301
6302         u8         ber_bath_high_error_threshold[0x10];
6303         u8         ber_bath_mid_error_threshold[0x10];
6304
6305         u8         ber_bath_low_error_threshold[0x10];
6306         u8         one_ratio_high_threshold[0x10];
6307
6308         u8         one_ratio_high_mid_threshold[0x10];
6309         u8         one_ratio_low_mid_threshold[0x10];
6310
6311         u8         one_ratio_low_threshold[0x10];
6312         u8         ndeo_error_threshold[0x10];
6313
6314         u8         mixer_offset_step_size[0x10];
6315         u8         reserved_at_110[0x8];
6316         u8         mix90_phase_for_voltage_bath[0x8];
6317
6318         u8         mixer_offset_start[0x10];
6319         u8         mixer_offset_end[0x10];
6320
6321         u8         reserved_at_140[0x15];
6322         u8         ber_test_time[0xb];
6323 };
6324
6325 struct mlx5_ifc_pspa_reg_bits {
6326         u8         swid[0x8];
6327         u8         local_port[0x8];
6328         u8         sub_port[0x8];
6329         u8         reserved_at_18[0x8];
6330
6331         u8         reserved_at_20[0x20];
6332 };
6333
6334 struct mlx5_ifc_pqdr_reg_bits {
6335         u8         reserved_at_0[0x8];
6336         u8         local_port[0x8];
6337         u8         reserved_at_10[0x5];
6338         u8         prio[0x3];
6339         u8         reserved_at_18[0x6];
6340         u8         mode[0x2];
6341
6342         u8         reserved_at_20[0x20];
6343
6344         u8         reserved_at_40[0x10];
6345         u8         min_threshold[0x10];
6346
6347         u8         reserved_at_60[0x10];
6348         u8         max_threshold[0x10];
6349
6350         u8         reserved_at_80[0x10];
6351         u8         mark_probability_denominator[0x10];
6352
6353         u8         reserved_at_a0[0x60];
6354 };
6355
6356 struct mlx5_ifc_ppsc_reg_bits {
6357         u8         reserved_at_0[0x8];
6358         u8         local_port[0x8];
6359         u8         reserved_at_10[0x10];
6360
6361         u8         reserved_at_20[0x60];
6362
6363         u8         reserved_at_80[0x1c];
6364         u8         wrps_admin[0x4];
6365
6366         u8         reserved_at_a0[0x1c];
6367         u8         wrps_status[0x4];
6368
6369         u8         reserved_at_c0[0x8];
6370         u8         up_threshold[0x8];
6371         u8         reserved_at_d0[0x8];
6372         u8         down_threshold[0x8];
6373
6374         u8         reserved_at_e0[0x20];
6375
6376         u8         reserved_at_100[0x1c];
6377         u8         srps_admin[0x4];
6378
6379         u8         reserved_at_120[0x1c];
6380         u8         srps_status[0x4];
6381
6382         u8         reserved_at_140[0x40];
6383 };
6384
6385 struct mlx5_ifc_pplr_reg_bits {
6386         u8         reserved_at_0[0x8];
6387         u8         local_port[0x8];
6388         u8         reserved_at_10[0x10];
6389
6390         u8         reserved_at_20[0x8];
6391         u8         lb_cap[0x8];
6392         u8         reserved_at_30[0x8];
6393         u8         lb_en[0x8];
6394 };
6395
6396 struct mlx5_ifc_pplm_reg_bits {
6397         u8         reserved_at_0[0x8];
6398         u8         local_port[0x8];
6399         u8         reserved_at_10[0x10];
6400
6401         u8         reserved_at_20[0x20];
6402
6403         u8         port_profile_mode[0x8];
6404         u8         static_port_profile[0x8];
6405         u8         active_port_profile[0x8];
6406         u8         reserved_at_58[0x8];
6407
6408         u8         retransmission_active[0x8];
6409         u8         fec_mode_active[0x18];
6410
6411         u8         reserved_at_80[0x20];
6412 };
6413
6414 struct mlx5_ifc_ppcnt_reg_bits {
6415         u8         swid[0x8];
6416         u8         local_port[0x8];
6417         u8         pnat[0x2];
6418         u8         reserved_at_12[0x8];
6419         u8         grp[0x6];
6420
6421         u8         clr[0x1];
6422         u8         reserved_at_21[0x1c];
6423         u8         prio_tc[0x3];
6424
6425         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6426 };
6427
6428 struct mlx5_ifc_ppad_reg_bits {
6429         u8         reserved_at_0[0x3];
6430         u8         single_mac[0x1];
6431         u8         reserved_at_4[0x4];
6432         u8         local_port[0x8];
6433         u8         mac_47_32[0x10];
6434
6435         u8         mac_31_0[0x20];
6436
6437         u8         reserved_at_40[0x40];
6438 };
6439
6440 struct mlx5_ifc_pmtu_reg_bits {
6441         u8         reserved_at_0[0x8];
6442         u8         local_port[0x8];
6443         u8         reserved_at_10[0x10];
6444
6445         u8         max_mtu[0x10];
6446         u8         reserved_at_30[0x10];
6447
6448         u8         admin_mtu[0x10];
6449         u8         reserved_at_50[0x10];
6450
6451         u8         oper_mtu[0x10];
6452         u8         reserved_at_70[0x10];
6453 };
6454
6455 struct mlx5_ifc_pmpr_reg_bits {
6456         u8         reserved_at_0[0x8];
6457         u8         module[0x8];
6458         u8         reserved_at_10[0x10];
6459
6460         u8         reserved_at_20[0x18];
6461         u8         attenuation_5g[0x8];
6462
6463         u8         reserved_at_40[0x18];
6464         u8         attenuation_7g[0x8];
6465
6466         u8         reserved_at_60[0x18];
6467         u8         attenuation_12g[0x8];
6468 };
6469
6470 struct mlx5_ifc_pmpe_reg_bits {
6471         u8         reserved_at_0[0x8];
6472         u8         module[0x8];
6473         u8         reserved_at_10[0xc];
6474         u8         module_status[0x4];
6475
6476         u8         reserved_at_20[0x60];
6477 };
6478
6479 struct mlx5_ifc_pmpc_reg_bits {
6480         u8         module_state_updated[32][0x8];
6481 };
6482
6483 struct mlx5_ifc_pmlpn_reg_bits {
6484         u8         reserved_at_0[0x4];
6485         u8         mlpn_status[0x4];
6486         u8         local_port[0x8];
6487         u8         reserved_at_10[0x10];
6488
6489         u8         e[0x1];
6490         u8         reserved_at_21[0x1f];
6491 };
6492
6493 struct mlx5_ifc_pmlp_reg_bits {
6494         u8         rxtx[0x1];
6495         u8         reserved_at_1[0x7];
6496         u8         local_port[0x8];
6497         u8         reserved_at_10[0x8];
6498         u8         width[0x8];
6499
6500         u8         lane0_module_mapping[0x20];
6501
6502         u8         lane1_module_mapping[0x20];
6503
6504         u8         lane2_module_mapping[0x20];
6505
6506         u8         lane3_module_mapping[0x20];
6507
6508         u8         reserved_at_a0[0x160];
6509 };
6510
6511 struct mlx5_ifc_pmaos_reg_bits {
6512         u8         reserved_at_0[0x8];
6513         u8         module[0x8];
6514         u8         reserved_at_10[0x4];
6515         u8         admin_status[0x4];
6516         u8         reserved_at_18[0x4];
6517         u8         oper_status[0x4];
6518
6519         u8         ase[0x1];
6520         u8         ee[0x1];
6521         u8         reserved_at_22[0x1c];
6522         u8         e[0x2];
6523
6524         u8         reserved_at_40[0x40];
6525 };
6526
6527 struct mlx5_ifc_plpc_reg_bits {
6528         u8         reserved_at_0[0x4];
6529         u8         profile_id[0xc];
6530         u8         reserved_at_10[0x4];
6531         u8         proto_mask[0x4];
6532         u8         reserved_at_18[0x8];
6533
6534         u8         reserved_at_20[0x10];
6535         u8         lane_speed[0x10];
6536
6537         u8         reserved_at_40[0x17];
6538         u8         lpbf[0x1];
6539         u8         fec_mode_policy[0x8];
6540
6541         u8         retransmission_capability[0x8];
6542         u8         fec_mode_capability[0x18];
6543
6544         u8         retransmission_support_admin[0x8];
6545         u8         fec_mode_support_admin[0x18];
6546
6547         u8         retransmission_request_admin[0x8];
6548         u8         fec_mode_request_admin[0x18];
6549
6550         u8         reserved_at_c0[0x80];
6551 };
6552
6553 struct mlx5_ifc_plib_reg_bits {
6554         u8         reserved_at_0[0x8];
6555         u8         local_port[0x8];
6556         u8         reserved_at_10[0x8];
6557         u8         ib_port[0x8];
6558
6559         u8         reserved_at_20[0x60];
6560 };
6561
6562 struct mlx5_ifc_plbf_reg_bits {
6563         u8         reserved_at_0[0x8];
6564         u8         local_port[0x8];
6565         u8         reserved_at_10[0xd];
6566         u8         lbf_mode[0x3];
6567
6568         u8         reserved_at_20[0x20];
6569 };
6570
6571 struct mlx5_ifc_pipg_reg_bits {
6572         u8         reserved_at_0[0x8];
6573         u8         local_port[0x8];
6574         u8         reserved_at_10[0x10];
6575
6576         u8         dic[0x1];
6577         u8         reserved_at_21[0x19];
6578         u8         ipg[0x4];
6579         u8         reserved_at_3e[0x2];
6580 };
6581
6582 struct mlx5_ifc_pifr_reg_bits {
6583         u8         reserved_at_0[0x8];
6584         u8         local_port[0x8];
6585         u8         reserved_at_10[0x10];
6586
6587         u8         reserved_at_20[0xe0];
6588
6589         u8         port_filter[8][0x20];
6590
6591         u8         port_filter_update_en[8][0x20];
6592 };
6593
6594 struct mlx5_ifc_pfcc_reg_bits {
6595         u8         reserved_at_0[0x8];
6596         u8         local_port[0x8];
6597         u8         reserved_at_10[0x10];
6598
6599         u8         ppan[0x4];
6600         u8         reserved_at_24[0x4];
6601         u8         prio_mask_tx[0x8];
6602         u8         reserved_at_30[0x8];
6603         u8         prio_mask_rx[0x8];
6604
6605         u8         pptx[0x1];
6606         u8         aptx[0x1];
6607         u8         reserved_at_42[0x6];
6608         u8         pfctx[0x8];
6609         u8         reserved_at_50[0x10];
6610
6611         u8         pprx[0x1];
6612         u8         aprx[0x1];
6613         u8         reserved_at_62[0x6];
6614         u8         pfcrx[0x8];
6615         u8         reserved_at_70[0x10];
6616
6617         u8         reserved_at_80[0x80];
6618 };
6619
6620 struct mlx5_ifc_pelc_reg_bits {
6621         u8         op[0x4];
6622         u8         reserved_at_4[0x4];
6623         u8         local_port[0x8];
6624         u8         reserved_at_10[0x10];
6625
6626         u8         op_admin[0x8];
6627         u8         op_capability[0x8];
6628         u8         op_request[0x8];
6629         u8         op_active[0x8];
6630
6631         u8         admin[0x40];
6632
6633         u8         capability[0x40];
6634
6635         u8         request[0x40];
6636
6637         u8         active[0x40];
6638
6639         u8         reserved_at_140[0x80];
6640 };
6641
6642 struct mlx5_ifc_peir_reg_bits {
6643         u8         reserved_at_0[0x8];
6644         u8         local_port[0x8];
6645         u8         reserved_at_10[0x10];
6646
6647         u8         reserved_at_20[0xc];
6648         u8         error_count[0x4];
6649         u8         reserved_at_30[0x10];
6650
6651         u8         reserved_at_40[0xc];
6652         u8         lane[0x4];
6653         u8         reserved_at_50[0x8];
6654         u8         error_type[0x8];
6655 };
6656
6657 struct mlx5_ifc_pcap_reg_bits {
6658         u8         reserved_at_0[0x8];
6659         u8         local_port[0x8];
6660         u8         reserved_at_10[0x10];
6661
6662         u8         port_capability_mask[4][0x20];
6663 };
6664
6665 struct mlx5_ifc_paos_reg_bits {
6666         u8         swid[0x8];
6667         u8         local_port[0x8];
6668         u8         reserved_at_10[0x4];
6669         u8         admin_status[0x4];
6670         u8         reserved_at_18[0x4];
6671         u8         oper_status[0x4];
6672
6673         u8         ase[0x1];
6674         u8         ee[0x1];
6675         u8         reserved_at_22[0x1c];
6676         u8         e[0x2];
6677
6678         u8         reserved_at_40[0x40];
6679 };
6680
6681 struct mlx5_ifc_pamp_reg_bits {
6682         u8         reserved_at_0[0x8];
6683         u8         opamp_group[0x8];
6684         u8         reserved_at_10[0xc];
6685         u8         opamp_group_type[0x4];
6686
6687         u8         start_index[0x10];
6688         u8         reserved_at_30[0x4];
6689         u8         num_of_indices[0xc];
6690
6691         u8         index_data[18][0x10];
6692 };
6693
6694 struct mlx5_ifc_lane_2_module_mapping_bits {
6695         u8         reserved_at_0[0x6];
6696         u8         rx_lane[0x2];
6697         u8         reserved_at_8[0x6];
6698         u8         tx_lane[0x2];
6699         u8         reserved_at_10[0x8];
6700         u8         module[0x8];
6701 };
6702
6703 struct mlx5_ifc_bufferx_reg_bits {
6704         u8         reserved_at_0[0x6];
6705         u8         lossy[0x1];
6706         u8         epsb[0x1];
6707         u8         reserved_at_8[0xc];
6708         u8         size[0xc];
6709
6710         u8         xoff_threshold[0x10];
6711         u8         xon_threshold[0x10];
6712 };
6713
6714 struct mlx5_ifc_set_node_in_bits {
6715         u8         node_description[64][0x8];
6716 };
6717
6718 struct mlx5_ifc_register_power_settings_bits {
6719         u8         reserved_at_0[0x18];
6720         u8         power_settings_level[0x8];
6721
6722         u8         reserved_at_20[0x60];
6723 };
6724
6725 struct mlx5_ifc_register_host_endianness_bits {
6726         u8         he[0x1];
6727         u8         reserved_at_1[0x1f];
6728
6729         u8         reserved_at_20[0x60];
6730 };
6731
6732 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6733         u8         reserved_at_0[0x20];
6734
6735         u8         mkey[0x20];
6736
6737         u8         addressh_63_32[0x20];
6738
6739         u8         addressl_31_0[0x20];
6740 };
6741
6742 struct mlx5_ifc_ud_adrs_vector_bits {
6743         u8         dc_key[0x40];
6744
6745         u8         ext[0x1];
6746         u8         reserved_at_41[0x7];
6747         u8         destination_qp_dct[0x18];
6748
6749         u8         static_rate[0x4];
6750         u8         sl_eth_prio[0x4];
6751         u8         fl[0x1];
6752         u8         mlid[0x7];
6753         u8         rlid_udp_sport[0x10];
6754
6755         u8         reserved_at_80[0x20];
6756
6757         u8         rmac_47_16[0x20];
6758
6759         u8         rmac_15_0[0x10];
6760         u8         tclass[0x8];
6761         u8         hop_limit[0x8];
6762
6763         u8         reserved_at_e0[0x1];
6764         u8         grh[0x1];
6765         u8         reserved_at_e2[0x2];
6766         u8         src_addr_index[0x8];
6767         u8         flow_label[0x14];
6768
6769         u8         rgid_rip[16][0x8];
6770 };
6771
6772 struct mlx5_ifc_pages_req_event_bits {
6773         u8         reserved_at_0[0x10];
6774         u8         function_id[0x10];
6775
6776         u8         num_pages[0x20];
6777
6778         u8         reserved_at_40[0xa0];
6779 };
6780
6781 struct mlx5_ifc_eqe_bits {
6782         u8         reserved_at_0[0x8];
6783         u8         event_type[0x8];
6784         u8         reserved_at_10[0x8];
6785         u8         event_sub_type[0x8];
6786
6787         u8         reserved_at_20[0xe0];
6788
6789         union mlx5_ifc_event_auto_bits event_data;
6790
6791         u8         reserved_at_1e0[0x10];
6792         u8         signature[0x8];
6793         u8         reserved_at_1f8[0x7];
6794         u8         owner[0x1];
6795 };
6796
6797 enum {
6798         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
6799 };
6800
6801 struct mlx5_ifc_cmd_queue_entry_bits {
6802         u8         type[0x8];
6803         u8         reserved_at_8[0x18];
6804
6805         u8         input_length[0x20];
6806
6807         u8         input_mailbox_pointer_63_32[0x20];
6808
6809         u8         input_mailbox_pointer_31_9[0x17];
6810         u8         reserved_at_77[0x9];
6811
6812         u8         command_input_inline_data[16][0x8];
6813
6814         u8         command_output_inline_data[16][0x8];
6815
6816         u8         output_mailbox_pointer_63_32[0x20];
6817
6818         u8         output_mailbox_pointer_31_9[0x17];
6819         u8         reserved_at_1b7[0x9];
6820
6821         u8         output_length[0x20];
6822
6823         u8         token[0x8];
6824         u8         signature[0x8];
6825         u8         reserved_at_1f0[0x8];
6826         u8         status[0x7];
6827         u8         ownership[0x1];
6828 };
6829
6830 struct mlx5_ifc_cmd_out_bits {
6831         u8         status[0x8];
6832         u8         reserved_at_8[0x18];
6833
6834         u8         syndrome[0x20];
6835
6836         u8         command_output[0x20];
6837 };
6838
6839 struct mlx5_ifc_cmd_in_bits {
6840         u8         opcode[0x10];
6841         u8         reserved_at_10[0x10];
6842
6843         u8         reserved_at_20[0x10];
6844         u8         op_mod[0x10];
6845
6846         u8         command[0][0x20];
6847 };
6848
6849 struct mlx5_ifc_cmd_if_box_bits {
6850         u8         mailbox_data[512][0x8];
6851
6852         u8         reserved_at_1000[0x180];
6853
6854         u8         next_pointer_63_32[0x20];
6855
6856         u8         next_pointer_31_10[0x16];
6857         u8         reserved_at_11b6[0xa];
6858
6859         u8         block_number[0x20];
6860
6861         u8         reserved_at_11e0[0x8];
6862         u8         token[0x8];
6863         u8         ctrl_signature[0x8];
6864         u8         signature[0x8];
6865 };
6866
6867 struct mlx5_ifc_mtt_bits {
6868         u8         ptag_63_32[0x20];
6869
6870         u8         ptag_31_8[0x18];
6871         u8         reserved_at_38[0x6];
6872         u8         wr_en[0x1];
6873         u8         rd_en[0x1];
6874 };
6875
6876 enum {
6877         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
6878         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
6879         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
6880 };
6881
6882 enum {
6883         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
6884         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
6885         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
6886 };
6887
6888 enum {
6889         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
6890         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
6891         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
6892         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
6893         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
6894         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
6895         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
6896         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
6897         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
6898         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
6899         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
6900 };
6901
6902 struct mlx5_ifc_initial_seg_bits {
6903         u8         fw_rev_minor[0x10];
6904         u8         fw_rev_major[0x10];
6905
6906         u8         cmd_interface_rev[0x10];
6907         u8         fw_rev_subminor[0x10];
6908
6909         u8         reserved_at_40[0x40];
6910
6911         u8         cmdq_phy_addr_63_32[0x20];
6912
6913         u8         cmdq_phy_addr_31_12[0x14];
6914         u8         reserved_at_b4[0x2];
6915         u8         nic_interface[0x2];
6916         u8         log_cmdq_size[0x4];
6917         u8         log_cmdq_stride[0x4];
6918
6919         u8         command_doorbell_vector[0x20];
6920
6921         u8         reserved_at_e0[0xf00];
6922
6923         u8         initializing[0x1];
6924         u8         reserved_at_fe1[0x4];
6925         u8         nic_interface_supported[0x3];
6926         u8         reserved_at_fe8[0x18];
6927
6928         struct mlx5_ifc_health_buffer_bits health_buffer;
6929
6930         u8         no_dram_nic_offset[0x20];
6931
6932         u8         reserved_at_1220[0x6e40];
6933
6934         u8         reserved_at_8060[0x1f];
6935         u8         clear_int[0x1];
6936
6937         u8         health_syndrome[0x8];
6938         u8         health_counter[0x18];
6939
6940         u8         reserved_at_80a0[0x17fc0];
6941 };
6942
6943 union mlx5_ifc_ports_control_registers_document_bits {
6944         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6945         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6946         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6947         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6948         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6949         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6950         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6951         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6952         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6953         struct mlx5_ifc_pamp_reg_bits pamp_reg;
6954         struct mlx5_ifc_paos_reg_bits paos_reg;
6955         struct mlx5_ifc_pcap_reg_bits pcap_reg;
6956         struct mlx5_ifc_peir_reg_bits peir_reg;
6957         struct mlx5_ifc_pelc_reg_bits pelc_reg;
6958         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
6959         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6960         struct mlx5_ifc_pifr_reg_bits pifr_reg;
6961         struct mlx5_ifc_pipg_reg_bits pipg_reg;
6962         struct mlx5_ifc_plbf_reg_bits plbf_reg;
6963         struct mlx5_ifc_plib_reg_bits plib_reg;
6964         struct mlx5_ifc_plpc_reg_bits plpc_reg;
6965         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
6966         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
6967         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
6968         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
6969         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
6970         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
6971         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
6972         struct mlx5_ifc_ppad_reg_bits ppad_reg;
6973         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
6974         struct mlx5_ifc_pplm_reg_bits pplm_reg;
6975         struct mlx5_ifc_pplr_reg_bits pplr_reg;
6976         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
6977         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
6978         struct mlx5_ifc_pspa_reg_bits pspa_reg;
6979         struct mlx5_ifc_ptas_reg_bits ptas_reg;
6980         struct mlx5_ifc_ptys_reg_bits ptys_reg;
6981         struct mlx5_ifc_pude_reg_bits pude_reg;
6982         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
6983         struct mlx5_ifc_slrg_reg_bits slrg_reg;
6984         struct mlx5_ifc_sltp_reg_bits sltp_reg;
6985         u8         reserved_at_0[0x60e0];
6986 };
6987
6988 union mlx5_ifc_debug_enhancements_document_bits {
6989         struct mlx5_ifc_health_buffer_bits health_buffer;
6990         u8         reserved_at_0[0x200];
6991 };
6992
6993 union mlx5_ifc_uplink_pci_interface_document_bits {
6994         struct mlx5_ifc_initial_seg_bits initial_seg;
6995         u8         reserved_at_0[0x20060];
6996 };
6997
6998 struct mlx5_ifc_set_flow_table_root_out_bits {
6999         u8         status[0x8];
7000         u8         reserved_at_8[0x18];
7001
7002         u8         syndrome[0x20];
7003
7004         u8         reserved_at_40[0x40];
7005 };
7006
7007 struct mlx5_ifc_set_flow_table_root_in_bits {
7008         u8         opcode[0x10];
7009         u8         reserved_at_10[0x10];
7010
7011         u8         reserved_at_20[0x10];
7012         u8         op_mod[0x10];
7013
7014         u8         reserved_at_40[0x40];
7015
7016         u8         table_type[0x8];
7017         u8         reserved_at_88[0x18];
7018
7019         u8         reserved_at_a0[0x8];
7020         u8         table_id[0x18];
7021
7022         u8         reserved_at_c0[0x140];
7023 };
7024
7025 enum {
7026         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7027 };
7028
7029 struct mlx5_ifc_modify_flow_table_out_bits {
7030         u8         status[0x8];
7031         u8         reserved_at_8[0x18];
7032
7033         u8         syndrome[0x20];
7034
7035         u8         reserved_at_40[0x40];
7036 };
7037
7038 struct mlx5_ifc_modify_flow_table_in_bits {
7039         u8         opcode[0x10];
7040         u8         reserved_at_10[0x10];
7041
7042         u8         reserved_at_20[0x10];
7043         u8         op_mod[0x10];
7044
7045         u8         reserved_at_40[0x20];
7046
7047         u8         reserved_at_60[0x10];
7048         u8         modify_field_select[0x10];
7049
7050         u8         table_type[0x8];
7051         u8         reserved_at_88[0x18];
7052
7053         u8         reserved_at_a0[0x8];
7054         u8         table_id[0x18];
7055
7056         u8         reserved_at_c0[0x4];
7057         u8         table_miss_mode[0x4];
7058         u8         reserved_at_c8[0x18];
7059
7060         u8         reserved_at_e0[0x8];
7061         u8         table_miss_id[0x18];
7062
7063         u8         reserved_at_100[0x100];
7064 };
7065
7066 struct mlx5_ifc_ets_tcn_config_reg_bits {
7067         u8         g[0x1];
7068         u8         b[0x1];
7069         u8         r[0x1];
7070         u8         reserved_at_3[0x9];
7071         u8         group[0x4];
7072         u8         reserved_at_10[0x9];
7073         u8         bw_allocation[0x7];
7074
7075         u8         reserved_at_20[0xc];
7076         u8         max_bw_units[0x4];
7077         u8         reserved_at_30[0x8];
7078         u8         max_bw_value[0x8];
7079 };
7080
7081 struct mlx5_ifc_ets_global_config_reg_bits {
7082         u8         reserved_at_0[0x2];
7083         u8         r[0x1];
7084         u8         reserved_at_3[0x1d];
7085
7086         u8         reserved_at_20[0xc];
7087         u8         max_bw_units[0x4];
7088         u8         reserved_at_30[0x8];
7089         u8         max_bw_value[0x8];
7090 };
7091
7092 struct mlx5_ifc_qetc_reg_bits {
7093         u8                                         reserved_at_0[0x8];
7094         u8                                         port_number[0x8];
7095         u8                                         reserved_at_10[0x30];
7096
7097         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
7098         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7099 };
7100
7101 struct mlx5_ifc_qtct_reg_bits {
7102         u8         reserved_at_0[0x8];
7103         u8         port_number[0x8];
7104         u8         reserved_at_10[0xd];
7105         u8         prio[0x3];
7106
7107         u8         reserved_at_20[0x1d];
7108         u8         tclass[0x3];
7109 };
7110
7111 #endif /* MLX5_IFC_H */