drm/tegra: sor: Factor out tegra_sor_set_parent_clock()

Switching the SOR parent clock can glitch if done while the clock is
enabled. Extract a common function that can be used to disable the
module clock, switch the parent and reenable the module clock.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index 757c6e8..ed03a1f 100644 (file)
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -225,6 +225,23 @@ static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
        writel(value, sor->regs + (offset << 2));
 }
 
+static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
+{
+       int err;
+
+       clk_disable_unprepare(sor->clk);
+
+       err = clk_set_parent(sor->clk, parent);
+       if (err < 0)
+               return err;
+
+       err = clk_prepare_enable(sor->clk);
+       if (err < 0)
+               return err;
+
+       return 0;
+}
+
 static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
                                   struct drm_dp_link *link)
 {
@@ -733,7 +750,8 @@ static int tegra_sor_power_down(struct tegra_sor *sor)
        if ((value & SOR_PWR_TRIGGER) != 0)
                return -ETIMEDOUT;
 
-       err = clk_set_parent(sor->clk, sor->clk_safe);
+       /* switch to safe parent clock */
+       err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
        if (err < 0)
                dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
 
@@ -1219,7 +1237,8 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
                return;
        }
 
-       err = clk_set_parent(sor->clk, sor->clk_safe);
+       /* switch to safe parent clock */
+       err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
        if (err < 0)
                dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
 
@@ -1326,10 +1345,10 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
        value &= ~SOR_PLL2_PORT_POWERDOWN;
        tegra_sor_writel(sor, value, SOR_PLL2);
 
-       /* switch to DP clock */
-       err = clk_set_parent(sor->clk, sor->clk_dp);
+       /* switch to DP parent clock */
+       err = tegra_sor_set_parent_clock(sor, sor->clk_dp);
        if (err < 0)
-               dev_err(sor->dev, "failed to set DP parent clock: %d\n", err);
+               dev_err(sor->dev, "failed to set parent clock: %d\n", err);
 
        /* power DP lanes */
        value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
@@ -1781,7 +1800,8 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
 
        reset_control_deassert(sor->rst);
 
-       err = clk_set_parent(sor->clk, sor->clk_safe);
+       /* switch to safe parent clock */
+       err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
        if (err < 0)
                dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
 
@@ -1892,7 +1912,8 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
 
        tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
 
-       err = clk_set_parent(sor->clk, sor->clk_parent);
+       /* switch to parent clock */
+       err = tegra_sor_set_parent_clock(sor, sor->clk_parent);
        if (err < 0)
                dev_err(sor->dev, "failed to set parent clock: %d\n", err);