ARM: dts: sun9i: Use sun9i specific mmc compatible

sun9i/A80 MMC controllers have a larger FIFO, and the FIFO DMA
trigger levels can be increased. Also, the mmc module clock parent
has a higher clock rate, and the sample and output delay phases
are different.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index e838f20..f4f61b0 100644 (file)
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -543,7 +543,7 @@
                };
 
                mmc0: mmc@01c0f000 {
-                       compatible = "allwinner,sun5i-a13-mmc";
+                       compatible = "allwinner,sun9i-a80-mmc";
                        reg = <0x01c0f000 0x1000>;
                        clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
                                 <&mmc0_clk 1>, <&mmc0_clk 2>;
@@ -557,7 +557,7 @@
                };
 
                mmc1: mmc@01c10000 {
-                       compatible = "allwinner,sun5i-a13-mmc";
+                       compatible = "allwinner,sun9i-a80-mmc";
                        reg = <0x01c10000 0x1000>;
                        clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
                                 <&mmc1_clk 1>, <&mmc1_clk 2>;
@@ -571,7 +571,7 @@
                };
 
                mmc2: mmc@01c11000 {
-                       compatible = "allwinner,sun5i-a13-mmc";
+                       compatible = "allwinner,sun9i-a80-mmc";
                        reg = <0x01c11000 0x1000>;
                        clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
                                 <&mmc2_clk 1>, <&mmc2_clk 2>;
@@ -585,7 +585,7 @@
                };
 
                mmc3: mmc@01c12000 {
-                       compatible = "allwinner,sun5i-a13-mmc";
+                       compatible = "allwinner,sun9i-a80-mmc";
                        reg = <0x01c12000 0x1000>;
                        clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
                                 <&mmc3_clk 1>, <&mmc3_clk 2>;