video: exynos: dp: Remove sink control to D0
authorSean Paul <seanpaul@chromium.org>
Sat, 14 Jul 2012 00:16:35 +0000 (17:16 -0700)
committerGerrit <chrome-bot@google.com>
Wed, 18 Jul 2012 19:06:52 +0000 (12:06 -0700)
Don't reset the sink power to D0. Removing this for three reasons:

1) It's not required in the SW link training documentation
2) The comment is incorrect, D0 is normal operation, not "power down"
3) It seems to change things in the link training that causes glitches

BUG=chrome-os-partner:11325
TEST=Tested on snow, glitching seems to be reduced

Change-Id: I3b87f953236b5597a4a10cbf3a1ea1d28fa8de91
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27424

drivers/video/exynos/exynos_dp_core.c

index 4ed9dc7..72a9c5d 100644 (file)
@@ -273,12 +273,6 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
        for (lane = 0; lane < lane_count; lane++)
                dp->link_train.cr_loop[lane] = 0;
 
-       /* Set sink to D0 (Sink Not Ready) mode. */
-       ret = exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
-                               DPCD_SET_POWER_STATE_D0);
-       if (ret)
-               return ret;
-
        /* Set link rate and count as you want to establish*/
        exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
        exynos_dp_set_lane_count(dp, dp->link_train.lane_count);