Merge tag 'keystone_dts_for_4.8' of git://git.kernel.org/pub/scm/linux/kernel/git...

ARM: Keystone DTS update for 4.8

	- Pinmux entries for K2G
	- PCI DTS entry fixup

* tag 'keystone_dts_for_4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
  ARM: dts: k2g-evm: Add pinmuxing for UART0
  ARM: dts: keystone: Header file for pinctrl constants
  ARM: dts: k2g: Add pinctrl support
  ARM: dts: keystone-k2l: Add pinctrl node
  ARM: dts: keystone: add interrupt property to PCI controller bindings
  ARM: dts: keystone: remove bogus IO resource entry from PCI binding

Signed-off-by: Olof Johansson <olof@lixom.net>

diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi
index 96b349f..9a51b8c 100644 (file)
--- a/arch/arm/boot/dts/keystone-k2e.dtsi
+++ b/arch/arm/boot/dts/keystone-k2e.dtsi
@@ -96,13 +96,16 @@
                        #address-cells = <3>;
                        #size-cells = <2>;
                        reg =  <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
-                       ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
-                               0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
+                       ranges = <0x82000000 0 0x60000000 0x60000000
+                                 0 0x10000000>;
 
                        status = "disabled";
                        device_type = "pci";
                        num-lanes = <2>;
+                       bus-range = <0x00 0xff>;
 
+                       /* error interrupt */
+                       interrupts = <GIC_SPI 385 IRQ_TYPE_EDGE_RISING>;
                        #interrupt-cells = <1>;
                        interrupt-map-mask = <0 0 0 7>;
                        interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */

diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts
index 5bfd9e7..692fcbb 100644 (file)
--- a/arch/arm/boot/dts/keystone-k2g-evm.dts
+++ b/arch/arm/boot/dts/keystone-k2g-evm.dts
@@ -27,6 +27,17 @@
 
 };
 
+&k2g_pinctrl {
+       uart0_pins: pinmux_uart0_pins {
+               pinctrl-single,pins = <
+                       K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* uart0_rxd.uart0_rxd */
+                       K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)      /* uart0_txd.uart0_txd */
+               >;
+       };
+};
+
 &uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_pins>;
        status = "okay";
 };

diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
index 7ff2796..3372615 100644 (file)
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -14,6 +14,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/keystone.h>
 #include "skeleton.dtsi"
 
 / {
@@ -75,6 +76,13 @@
                ranges = <0x0 0x0 0x0 0xc0000000>;
                dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
 
+               k2g_pinctrl: pinmux@02621000 {
+                       compatible = "pinctrl-single";
+                       reg = <0x02621000 0x410>;
+                       pinctrl-single,register-width = <32>;
+                       pinctrl-single,function-mask = <0x001b0007>;
+               };
+
                uart0: serial@02530c00 {
                        compatible = "ns16550a";
                        current-speed = <115200>;

diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi
index ff22ffc..2ee3d0a 100644 (file)
--- a/arch/arm/boot/dts/keystone-k2l.dtsi
+++ b/arch/arm/boot/dts/keystone-k2l.dtsi
@@ -54,6 +54,155 @@
                        interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
                };
 
+               k2l_pmx: pinmux@02620690 {
+                       compatible = "pinctrl-single";
+                       reg = <0x02620690 0xc>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       pinctrl-single,bit-per-mux;
+                       pinctrl-single,register-width = <32>;
+                       pinctrl-single,function-mask = <0x1>;
+                       status = "disabled";
+
+                       uart3_emifa_pins: pinmux_uart3_emifa_pins {
+                               pinctrl-single,bits = <
+                                       /* UART3_EMIFA_SEL */
+                                       0x0 0x0  0xc0
+                               >;
+                       };
+
+                       uart2_emifa_pins: pinmux_uart2_emifa_pins {
+                       pinctrl-single,bits = <
+                                       /* UART2_EMIFA_SEL */
+                                       0x0 0x0  0x30
+                               >;
+                       };
+
+                       uart01_spi2_pins: pinmux_uart01_spi2_pins {
+                               pinctrl-single,bits = <
+                                       /* UART01_SPI2_SEL */
+                                       0x0 0x0 0x4
+                               >;
+                       };
+
+                       dfesync_rp1_pins: pinmux_dfesync_rp1_pins{
+                               pinctrl-single,bits = <
+                                       /* DFESYNC_RP1_SEL */
+                                       0x0 0x0 0x2
+                               >;
+                       };
+
+                       avsif_pins: pinmux_avsif_pins {
+                               pinctrl-single,bits = <
+                                       /* AVSIF_SEL */
+                                       0x0 0x0 0x1
+                               >;
+                       };
+
+                       gpio_emu_pins: pinmux_gpio_emu_pins {
+                               pinctrl-single,bits = <
+                               /*
+                                * GPIO_EMU_SEL[31]: 0-GPIO31, 1-EMU33
+                                * GPIO_EMU_SEL[30]: 0-GPIO30, 1-EMU32
+                                * GPIO_EMU_SEL[29]: 0-GPIO29, 1-EMU31
+                                * GPIO_EMU_SEL[28]: 0-GPIO28, 1-EMU30
+                                * GPIO_EMU_SEL[27]: 0-GPIO27, 1-EMU29
+                                * GPIO_EMU_SEL[26]: 0-GPIO26, 1-EMU28
+                                * GPIO_EMU_SEL[25]: 0-GPIO25, 1-EMU27
+                                * GPIO_EMU_SEL[24]: 0-GPIO24, 1-EMU26
+                                * GPIO_EMU_SEL[23]: 0-GPIO23, 1-EMU25
+                                * GPIO_EMU_SEL[22]: 0-GPIO22, 1-EMU24
+                                * GPIO_EMU_SEL[21]: 0-GPIO21, 1-EMU23
+                                * GPIO_EMU_SEL[20]: 0-GPIO20, 1-EMU22
+                                * GPIO_EMU_SEL[19]: 0-GPIO19, 1-EMU21
+                                * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20
+                                * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19
+                                */
+                                       0x4 0x0000 0xFFFE0000
+                               >;
+                       };
+
+                       gpio_timio_pins: pinmux_gpio_timio_pins {
+                               pinctrl-single,bits = <
+                               /*
+                                * GPIO_TIMIO_SEL[15]: 0-GPIO15, 1-TIMO7
+                                * GPIO_TIMIO_SEL[14]: 0-GPIO14, 1-TIMO6
+                                * GPIO_TIMIO_SEL[13]: 0-GPIO13, 1-TIMO5
+                                * GPIO_TIMIO_SEL[12]: 0-GPIO12, 1-TIMO4
+                                * GPIO_TIMIO_SEL[11]: 0-GPIO11, 1-TIMO3
+                                * GPIO_TIMIO_SEL[10]: 0-GPIO10, 1-TIMO2
+                                * GPIO_TIMIO_SEL[9]: 0-GPIO9, 1-TIMI7
+                                * GPIO_TIMIO_SEL[8]: 0-GPIO8, 1-TIMI6
+                                * GPIO_TIMIO_SEL[7]: 0-GPIO7, 1-TIMI5
+                                * GPIO_TIMIO_SEL[6]: 0-GPIO6, 1-TIMI4
+                                * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3
+                                * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2
+                                */
+                                       0x4 0x0 0xFFF0
+                               >;
+                       };
+
+                       gpio_spi2cs_pins: pinmux_gpio_spi2cs_pins {
+                               pinctrl-single,bits = <
+                               /*
+                                * GPIO_SPI2CS_SEL[3]: 0-GPIO3, 1-SPI2CS4
+                                * GPIO_SPI2CS_SEL[2]: 0-GPIO2, 1-SPI2CS3
+                                * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2
+                                * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1
+                                */
+                                       0x4 0x0 0xF
+                               >;
+                       };
+
+                       gpio_dfeio_pins: pinmux_gpio_dfeio_pins {
+                               pinctrl-single,bits = <
+                               /*
+                                * GPIO_DFEIO_SEL[31]: 0-DFEIO17, 1-GPIO63
+                                * GPIO_DFEIO_SEL[30]: 0-DFEIO16, 1-GPIO62
+                                * GPIO_DFEIO_SEL[29]: 0-DFEIO15, 1-GPIO61
+                                * GPIO_DFEIO_SEL[28]: 0-DFEIO14, 1-GPIO60
+                                * GPIO_DFEIO_SEL[27]: 0-DFEIO13, 1-GPIO59
+                                * GPIO_DFEIO_SEL[26]: 0-DFEIO12, 1-GPIO58
+                                * GPIO_DFEIO_SEL[25]: 0-DFEIO11, 1-GPIO57
+                                * GPIO_DFEIO_SEL[24]: 0-DFEIO10, 1-GPIO56
+                                * GPIO_DFEIO_SEL[23]: 0-DFEIO9, 1-GPIO55
+                                * GPIO_DFEIO_SEL[22]: 0-DFEIO8, 1-GPIO54
+                                * GPIO_DFEIO_SEL[21]: 0-DFEIO7, 1-GPIO53
+                                * GPIO_DFEIO_SEL[20]: 0-DFEIO6, 1-GPIO52
+                                * GPIO_DFEIO_SEL[19]: 0-DFEIO5, 1-GPIO51
+                                * GPIO_DFEIO_SEL[18]: 0-DFEIO4, 1-GPIO50
+                                * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49
+                                * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48
+                                */
+                                       0x8 0x0 0xFFFF0000
+                               >;
+                       };
+
+                       gpio_emifa_pins: pinmux_gpio_emifa_pins {
+                               pinctrl-single,bits = <
+                               /*
+                                * GPIO_EMIFA_SEL[15]: 0-EMIFA17, 1-GPIO47
+                                * GPIO_EMIFA_SEL[14]: 0-EMIFA16, 1-GPIO46
+                                * GPIO_EMIFA_SEL[13]: 0-EMIFA15, 1-GPIO45
+                                * GPIO_EMIFA_SEL[12]: 0-EMIFA14, 1-GPIO44
+                                * GPIO_EMIFA_SEL[11]: 0-EMIFA13, 1-GPIO43
+                                * GPIO_EMIFA_SEL[10]: 0-EMIFA10, 1-GPIO42
+                                * GPIO_EMIFA_SEL[9]: 0-EMIFA9, 1-GPIO41
+                                * GPIO_EMIFA_SEL[8]: 0-EMIFA8, 1-GPIO40
+                                * GPIO_EMIFA_SEL[7]: 0-EMIFA7, 1-GPIO39
+                                * GPIO_EMIFA_SEL[6]: 0-EMIFA6, 1-GPIO38
+                                * GPIO_EMIFA_SEL[5]: 0-EMIFA5, 1-GPIO37
+                                * GPIO_EMIFA_SEL[4]: 0-EMIFA4, 1-GPIO36
+                                * GPIO_EMIFA_SEL[3]: 0-EMIFA3, 1-GPIO35
+                                * GPIO_EMIFA_SEL[2]: 0-EMIFA2, 1-GPIO34
+                                * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33
+                                * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32
+                                */
+                                       0x8 0x0 0xFFFF
+                               >;
+                       };
+               };
+
                dspgpio0: keystone_dsp_gpio@02620240 {
                        compatible = "ti,keystone-dsp-gpio";
                        gpio-controller;

diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index e34b226..e23f46d 100644 (file)
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -294,13 +294,16 @@
                        #address-cells = <3>;
                        #size-cells = <2>;
                        reg =  <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
-                       ranges = <0x81000000 0 0 0x23250000 0 0x4000
-                               0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
+                       ranges = <0x82000000 0 0x50000000 0x50000000
+                                 0 0x10000000>;
 
                        status = "disabled";
                        device_type = "pci";
                        num-lanes = <2>;
+                       bus-range = <0x00 0xff>;
 
+                       /* error interrupt */
+                       interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
                        #interrupt-cells = <1>;
                        interrupt-map-mask = <0 0 0 7>;
                        interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */

diff --git a/include/dt-bindings/pinctrl/keystone.h b/include/dt-bindings/pinctrl/keystone.h
new file mode 100644 (file)
index 0000000..7f97d77
--- /dev/null
+++ b/include/dt-bindings/pinctrl/keystone.h
@@ -0,0 +1,39 @@
+/*
+ * This header provides constants for Keystone pinctrl bindings.
+ *
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_KEYSTONE_H
+#define _DT_BINDINGS_PINCTRL_KEYSTONE_H
+
+#define MUX_MODE0      0
+#define MUX_MODE1      1
+#define MUX_MODE2      2
+#define MUX_MODE3      3
+#define MUX_MODE4      4
+#define MUX_MODE5      5
+
+#define BUFFER_CLASS_B (0 << 19)
+#define BUFFER_CLASS_C (1 << 19)
+#define BUFFER_CLASS_D (2 << 19)
+#define BUFFER_CLASS_E (3 << 19)
+
+#define PULL_DISABLE   (1 << 16)
+#define PIN_PULLUP     (1 << 17)
+#define PIN_PULLDOWN   (0 << 17)
+
+#define KEYSTONE_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset))
+
+#define K2G_CORE_IOPAD(pa) KEYSTONE_IOPAD_OFFSET((pa), 0x1000)
+
+#endif