Merge branch 'topic-0620/samsung-pm-3.4' into chromeos-exynos-3.4

* topic-0620/samsung-pm-3.4: (32 commits)
  CHROMIUM: exynos: pwm: Cosmetic tidy of PWM variable names
  CHROMIUM: exynos: Stop the PWM timer while configuring it.
  CHROMIUM: exynos: Ensure the manual update bit is off before setting it.
  exynos5: cpufreq: updated asv voltage table for cpufreq
  exynos: daisy: Add support for controlling the 32KHz peripheral clock
  trivial: regulator: Fix indentation in MAX77686
  ARM: exynos: Add thermal sensor driver platform data support
  thermal: exynos: Register the tmu sensor with the kernel thermal layer
  thermal: exynos5: Add exynos5 thermal sensor driver support
  hwmon: exynos4: Move thermal sensor driver to driver/thermal directory
  thermal: Add generic cpufreq cooling implementation
  ARM: EXYNOS5: Fix i2c suspend/resume issue
  ARM: Add missing clock definition
  ARM: EXYNOS: Add WDT reset register definitions
  regulator: Support for PMIC-MAX77686.
  mfd: Add suport for MAX77686.
  i2c: exynos: Add fix for i2c suspend/resume
  ARM: EXYNOS: Select ARM_CPU_SUSPEND & S5P_SLEEP if CPU_IDLE enabled
  UPSTREAM: cpufreq: exynos: Show list of available frequencies
  UPSTREAM: arm: exynos: Adapt to cpuidle core time keeping and irq enable
  ...

Conflicts:
	arch/arm/mach-exynos/include/mach/regs-pmu.h

Change-Id: I1d871adc49be46453f87e6f4487a1711065fc2f1

diff --cc arch/arm/mach-exynos/Kconfig
Simple merge

diff --cc arch/arm/mach-exynos/Makefile
Simple merge

diff --cc arch/arm/mach-exynos/clock-exynos5.c
Simple merge

diff --cc arch/arm/mach-exynos/common.c
Simple merge

diff --cc arch/arm/mach-exynos/include/mach/regs-clock.h
index cf4cf00,1d020dd..d281027
--- 1/arch/arm/mach-exynos/include/mach/regs-clock.h
--- 2/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@@ -290,9 -294,9 +296,10 @@@
  #define EXYNOS5_CLKSRC_MASK_TOP                       EXYNOS_CLKREG(0x10310)
  #define EXYNOS5_CLKSRC_MASK_GSCL              EXYNOS_CLKREG(0x10320)
  #define EXYNOS5_CLKSRC_MASK_DISP1_0           EXYNOS_CLKREG(0x1032C)
+ #define EXYNOS5_CLKSRC_MASK_MAUDIO            EXYNOS_CLKREG(0x10334)
  #define EXYNOS5_CLKSRC_MASK_FSYS              EXYNOS_CLKREG(0x10340)
  #define EXYNOS5_CLKSRC_MASK_PERIC0            EXYNOS_CLKREG(0x10350)
 +#define EXYNOS5_CLKSRC_MASK_PERIC1             EXYNOS_CLKREG(0x10354)
  
  #define EXYNOS5_CLKDIV_TOP0                   EXYNOS_CLKREG(0x10510)
  #define EXYNOS5_CLKDIV_TOP1                   EXYNOS_CLKREG(0x10514)
@@@ -304,10 -309,15 +312,17 @@@
  #define EXYNOS5_CLKDIV_FSYS2                  EXYNOS_CLKREG(0x10550)
  #define EXYNOS5_CLKDIV_FSYS3                  EXYNOS_CLKREG(0x10554)
  #define EXYNOS5_CLKDIV_PERIC0                 EXYNOS_CLKREG(0x10558)
+ #define EXYNOS5_CLKDIV_PERIC1                 EXYNOS_CLKREG(0x1055C)
+ #define EXYNOS5_CLKDIV_PERIC2                 EXYNOS_CLKREG(0x10560)
+ #define EXYNOS5_CLKDIV_PERIC3                 EXYNOS_CLKREG(0x10564)
+ #define EXYNOS5_CLKDIV_PERIC4                 EXYNOS_CLKREG(0x10568)
+ #define EXYNOS5_CLKDIV_PERIC5                 EXYNOS_CLKREG(0x1056C)
+ #define EXYNOS5_SCLK_DIV_ISP                  EXYNOS_CLKREG(0x10580)
+ #define EXYNOS5_CLKDIV_STAT_TOP0              EXYNOS_CLKREG(0x10610)
  
  #define EXYNOS5_CLKGATE_IP_ACP                        EXYNOS_CLKREG(0x08800)
 +#define EXYNOS5_CLKGATE_IP_ISP0                 EXYNOS_CLKREG(0x0C800)
 +#define EXYNOS5_CLKGATE_IP_ISP1                 EXYNOS_CLKREG(0x0C804)
  #define EXYNOS5_CLKGATE_IP_GSCL                       EXYNOS_CLKREG(0x10920)
  #define EXYNOS5_CLKGATE_IP_DISP1              EXYNOS_CLKREG(0x10928)
  #define EXYNOS5_CLKGATE_IP_MFC                        EXYNOS_CLKREG(0x1092C)

diff --cc arch/arm/mach-exynos/include/mach/regs-pmu.h
index df406b4,e8a771a..108407d
--- 1/arch/arm/mach-exynos/include/mach/regs-pmu.h
--- 2/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@@ -225,7 -218,151 +225,153 @@@
  #define S5P_SECSS_MEM_OPTION                  S5P_PMUREG(0x2EC8)
  #define S5P_ROTATOR_MEM_OPTION                        S5P_PMUREG(0x2F48)
  
+ /* For EXYNOS5 */
+ 
+ #define EXYNOS5_GPS_LPI                                       S5P_PMUREG(0x0004)
+ 
+ #define EXYNOS5_USB_CFG                                       S5P_PMUREG(0x0230)
+ 
+ #define EXYNOS5_SYS_WDTRESET                          (1 << 20)
+ #define EXYNOS5_AUTOMATIC_WDT_RESET_DISABLE           S5P_PMUREG(0x0408)
+ #define EXYNOS5_MASK_WDT_RESET_REQUEST                        S5P_PMUREG(0x040C)
+ 
+ #define EXYNOS5_ARM_CORE0_SYS_PWR_REG                 S5P_PMUREG(0x1000)
+ #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG   S5P_PMUREG(0x1004)
+ #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)
+ #define EXYNOS5_ARM_CORE1_SYS_PWR_REG                 S5P_PMUREG(0x1010)
+ #define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG   S5P_PMUREG(0x1014)
+ #define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1018)
+ #define EXYNOS5_FSYS_ARM_SYS_PWR_REG                  S5P_PMUREG(0x1040)
+ #define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG  S5P_PMUREG(0x1048)
+ #define EXYNOS5_ISP_ARM_SYS_PWR_REG                   S5P_PMUREG(0x1050)
+ #define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG     S5P_PMUREG(0x1054)
+ #define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG   S5P_PMUREG(0x1058)
+ #define EXYNOS5_ARM_COMMON_SYS_PWR_REG                        S5P_PMUREG(0x1080)
+ #define EXYNOS5_ARM_L2_SYS_PWR_REG                    S5P_PMUREG(0x10C0)
+ #define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG              S5P_PMUREG(0x1100)
+ #define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG              S5P_PMUREG(0x1104)
+ #define EXYNOS5_CMU_RESET_SYS_PWR_REG                 S5P_PMUREG(0x110C)
+ #define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG               S5P_PMUREG(0x1120)
+ #define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG               S5P_PMUREG(0x1124)
+ #define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG          S5P_PMUREG(0x112C)
+ #define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG            S5P_PMUREG(0x1130)
+ #define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG             S5P_PMUREG(0x1134)
+ #define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG            S5P_PMUREG(0x1138)
+ #define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG                       S5P_PMUREG(0x1140)
+ #define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG                       S5P_PMUREG(0x1144)
+ #define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG                       S5P_PMUREG(0x1148)
+ #define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG                       S5P_PMUREG(0x114C)
+ #define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG                       S5P_PMUREG(0x1150)
+ #define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG                       S5P_PMUREG(0x1154)
+ #define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG           S5P_PMUREG(0x1164)
+ #define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG           S5P_PMUREG(0x1170)
+ #define EXYNOS5_TOP_BUS_SYS_PWR_REG                   S5P_PMUREG(0x1180)
+ #define EXYNOS5_TOP_RETENTION_SYS_PWR_REG             S5P_PMUREG(0x1184)
+ #define EXYNOS5_TOP_PWR_SYS_PWR_REG                   S5P_PMUREG(0x1188)
+ #define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG            S5P_PMUREG(0x1190)
+ #define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG      S5P_PMUREG(0x1194)
+ #define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG            S5P_PMUREG(0x1198)
+ #define EXYNOS5_LOGIC_RESET_SYS_PWR_REG                       S5P_PMUREG(0x11A0)
+ #define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG                       S5P_PMUREG(0x11A4)
+ #define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG                S5P_PMUREG(0x11B0)
+ #define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG                S5P_PMUREG(0x11B4)
+ #define EXYNOS5_USBOTG_MEM_SYS_PWR_REG                        S5P_PMUREG(0x11C0)
+ #define EXYNOS5_G2D_MEM_SYS_PWR_REG                   S5P_PMUREG(0x11C8)
+ #define EXYNOS5_USBDRD_MEM_SYS_PWR_REG                        S5P_PMUREG(0x11CC)
+ #define EXYNOS5_SDMMC_MEM_SYS_PWR_REG                 S5P_PMUREG(0x11D0)
+ #define EXYNOS5_CSSYS_MEM_SYS_PWR_REG                 S5P_PMUREG(0x11D4)
+ #define EXYNOS5_SECSS_MEM_SYS_PWR_REG                 S5P_PMUREG(0x11D8)
+ #define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG                       S5P_PMUREG(0x11DC)
+ #define EXYNOS5_INTRAM_MEM_SYS_PWR_REG                        S5P_PMUREG(0x11E0)
+ #define EXYNOS5_INTROM_MEM_SYS_PWR_REG                        S5P_PMUREG(0x11E4)
+ #define EXYNOS5_JPEG_MEM_SYS_PWR_REG                  S5P_PMUREG(0x11E8)
+ #define EXYNOS5_HSI_MEM_SYS_PWR_REG                   S5P_PMUREG(0x11EC)
+ #define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG                        S5P_PMUREG(0x11F4)
+ #define EXYNOS5_SATA_MEM_SYS_PWR_REG                  S5P_PMUREG(0x11FC)
+ #define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG                S5P_PMUREG(0x1200)
+ #define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG         S5P_PMUREG(0x1204)
+ #define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG      S5P_PMUREG(0x1208)
+ #define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG                S5P_PMUREG(0x1220)
+ #define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG                S5P_PMUREG(0x1224)
+ #define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG                S5P_PMUREG(0x1228)
+ #define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG                S5P_PMUREG(0x122C)
+ #define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG                S5P_PMUREG(0x1230)
+ #define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG                S5P_PMUREG(0x1234)
+ #define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG         S5P_PMUREG(0x1238)
+ #define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x123C)
+ #define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG             S5P_PMUREG(0x1240)
+ #define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG      S5P_PMUREG(0x1250)
+ #define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG                       S5P_PMUREG(0x1260)
+ #define EXYNOS5_XUSBXTI_SYS_PWR_REG                   S5P_PMUREG(0x1280)
+ #define EXYNOS5_XXTI_SYS_PWR_REG                      S5P_PMUREG(0x1284)
+ #define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG             S5P_PMUREG(0x12C0)
+ #define EXYNOS5_GPIO_MODE_SYS_PWR_REG                 S5P_PMUREG(0x1300)
+ #define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG          S5P_PMUREG(0x1320)
+ #define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG             S5P_PMUREG(0x1340)
+ #define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG             S5P_PMUREG(0x1344)
+ #define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG         S5P_PMUREG(0x1348)
+ #define EXYNOS5_GSCL_SYS_PWR_REG                      S5P_PMUREG(0x1400)
+ #define EXYNOS5_ISP_SYS_PWR_REG                               S5P_PMUREG(0x1404)
+ #define EXYNOS5_MFC_SYS_PWR_REG                               S5P_PMUREG(0x1408)
+ #define EXYNOS5_G3D_SYS_PWR_REG                               S5P_PMUREG(0x140C)
+ #define EXYNOS5_DISP1_SYS_PWR_REG                     S5P_PMUREG(0x1414)
+ #define EXYNOS5_MAU_SYS_PWR_REG                               S5P_PMUREG(0x1418)
+ #define EXYNOS5_GPS_SYS_PWR_REG                               S5P_PMUREG(0x141C)
+ #define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG          S5P_PMUREG(0x1480)
+ #define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG           S5P_PMUREG(0x1484)
+ #define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG           S5P_PMUREG(0x1488)
+ #define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG           S5P_PMUREG(0x148C)
+ #define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG         S5P_PMUREG(0x1494)
+ #define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG           S5P_PMUREG(0x1498)
+ #define EXYNOS5_CMU_CLKSTOP_GPS_SYS_PWR_REG           S5P_PMUREG(0x149C)
+ #define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG           S5P_PMUREG(0x14C0)
+ #define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG            S5P_PMUREG(0x14C4)
+ #define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG            S5P_PMUREG(0x14C8)
+ #define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG            S5P_PMUREG(0x14CC)
+ #define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG          S5P_PMUREG(0x14D4)
+ #define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG            S5P_PMUREG(0x14D8)
+ #define EXYNOS5_CMU_SYSCLK_GPS_SYS_PWR_REG            S5P_PMUREG(0x14DC)
+ #define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG            S5P_PMUREG(0x1580)
+ #define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG             S5P_PMUREG(0x1584)
+ #define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG             S5P_PMUREG(0x1588)
+ #define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG             S5P_PMUREG(0x158C)
+ #define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG           S5P_PMUREG(0x1594)
+ #define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG             S5P_PMUREG(0x1598)
+ #define EXYNOS5_CMU_RESET_GPS_SYS_PWR_REG             S5P_PMUREG(0x159C)
+ 
+ #define EXYNOS5_ARM_CORE0_OPTION                      S5P_PMUREG(0x2008)
+ #define EXYNOS5_ARM_CORE1_OPTION                      S5P_PMUREG(0x2088)
+ #define EXYNOS5_FSYS_ARM_OPTION                               S5P_PMUREG(0x2208)
+ #define EXYNOS5_ISP_ARM_OPTION                                S5P_PMUREG(0x2288)
+ #define EXYNOS5_ARM_COMMON_OPTION                     S5P_PMUREG(0x2408)
+ #define EXYNOS5_TOP_PWR_OPTION                                S5P_PMUREG(0x2C48)
+ #define EXYNOS5_TOP_PWR_SYSMEM_OPTION                 S5P_PMUREG(0x2CC8)
+ #define EXYNOS5_JPEG_MEM_OPTION                               S5P_PMUREG(0x2F48)
+ #define EXYNOS5_GSCL_STATUS                           S5P_PMUREG(0x4004)
+ #define EXYNOS5_ISP_STATUS                            S5P_PMUREG(0x4024)
+ #define EXYNOS5_GSCL_OPTION                           S5P_PMUREG(0x4008)
+ #define EXYNOS5_ISP_OPTION                            S5P_PMUREG(0x4028)
+ #define EXYNOS5_MFC_OPTION                            S5P_PMUREG(0x4048)
+ #define EXYNOS5_G3D_CONFIGURATION                     S5P_PMUREG(0x4060)
+ #define EXYNOS5_G3D_STATUS                            S5P_PMUREG(0x4064)
+ #define EXYNOS5_G3D_OPTION                            S5P_PMUREG(0x4068)
+ #define EXYNOS5_DISP1_OPTION                          S5P_PMUREG(0x40A8)
+ #define EXYNOS5_MAU_OPTION                            S5P_PMUREG(0x40C8)
+ #define EXYNOS5_GPS_OPTION                            S5P_PMUREG(0x40E8)
+ 
+ #define EXYNOS5_USE_SC_FEEDBACK                                       (1 << 1)
+ #define EXYNOS5_USE_SC_COUNTER                                        (1 << 0)
+ 
+ #define EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL                   (1 << 2)
+ #define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN                        (1 << 7)
+ 
+ #define EXYNOS5_OPTION_USE_STANDBYWFE                         (1 << 24)
+ #define EXYNOS5_OPTION_USE_STANDBYWFI                         (1 << 16)
+ 
+ #define EXYNOS5_OPTION_USE_RETENTION                          (1 << 4)
+ 
+ #define EXYNOS5_SYS_I2C_CFG                                   S5P_SYSREG(0x234)
 +#define EXYNOS5_SYS_DISP1BLK_CFG              S5P_SYSREG(0x214)
 +#define ENABLE_FIMDBYPASS_DISP1                       (1 << 15)
  
  #endif /* __ASM_ARCH_REGS_PMU_H */

diff --cc drivers/i2c/busses/i2c-s3c2410.c
Simple merge