video: exynos: dp: Get pll lock before pattern set

According to the exynos datasheet (Figure 49-10), we should wait for PLL
lock before programming the training pattern when doing software eDP
link training.

BUG=chrome-os-partner:11325
TEST=Tested on snow

Change-Id: I0b7fe3e5904b6207cd329fb8d74de6ba78f828df
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27578
Reviewed-by: Mandeep Singh Baines <msb@chromium.org>

diff --git a/drivers/video/exynos/exynos_dp_core.c b/drivers/video/exynos/exynos_dp_core.c
index 3e705d0..4ed9dc7 100644 (file)
--- a/drivers/video/exynos/exynos_dp_core.c
+++ b/drivers/video/exynos/exynos_dp_core.c
@@ -26,6 +26,8 @@
 
 #include "exynos_dp_core.h"
 
+#define PLL_MAX_TRIES 100
+
 static int exynos_dp_init_dp(struct exynos_dp_device *dp)
 {
        exynos_dp_reset(dp);
@@ -260,7 +262,7 @@ static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
 
 static int exynos_dp_link_start(struct exynos_dp_device *dp)
 {
-       int ret, lane, lane_count;
+       int ret, lane, lane_count, pll_tries;
        u8 buf[4];
 
        lane_count = dp->link_train.lane_count;
@@ -293,6 +295,16 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
                exynos_dp_set_lane_lane_pre_emphasis(dp,
                        PRE_EMPHASIS_LEVEL_0, lane);
 
+       /* Wait for PLL lock */
+       pll_tries = 0;
+       while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+               if (pll_tries == PLL_MAX_TRIES)
+                       return -ETIMEDOUT;
+
+               pll_tries++;
+               udelay(100);
+       }
+
        /* Set training pattern 1 */
        exynos_dp_set_training_pattern(dp, TRAINING_PTN1);