MIPS: BMIPS: Add missing 7038 L1 register cells to BCM7435

7435 has 4 7038 L1 base register address for each of its Core + TP (for a total
of 4 threads of execution), add the two missing cells for Core 1. We are
providing HW interrupts 2/3 even for Core 1/TP0/TP1 because that's what they
are, and we can later decide to remap these in software to provide proper
interrupt affinity/parenting.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: john@phrozen.org
Cc: cernekee@gmail.com
Cc: jon.fraser@broadcom.com
Cc: jaedon.shin@gmail.com
Cc: dragan.stancevic@gmail.com
Cc: jogo@openwrt.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12378/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/boot/dts/brcm/bcm7435.dtsi b/arch/mips/boot/dts/brcm/bcm7435.dtsi
index 56035e5..a1757ef 100644 (file)
--- a/arch/mips/boot/dts/brcm/bcm7435.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7435.dtsi
@@ -63,13 +63,14 @@
 
                periph_intc: periph_intc@41b500 {
                        compatible = "brcm,bcm7038-l1-intc";
-                       reg = <0x41b500 0x40>, <0x41b600 0x40>;
+                       reg = <0x41b500 0x40>, <0x41b600 0x40>,
+                               <0x41b700 0x40>, <0x41b800 0x40>;
 
                        interrupt-controller;
                        #interrupt-cells = <1>;
 
                        interrupt-parent = <&cpu_intc>;
-                       interrupts = <2>, <3>;
+                       interrupts = <2>, <3>, <2>, <3>;
                };
 
                sun_l2_intc: sun_l2_intc@403000 {